From ac7a3d0b508f9a055a85f2aa8842a5e7d9b2ff3f Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Fri, 29 Jun 2018 01:22:18 +0100
Subject: Prelude: drop escape effect from sleep/verbosity primops

It appears that primops that have the escape effect are required to
write to the have_exception flag so I am dropping the effect from
primops that don't actually escape.
---
 aarch64/prelude.sail | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail
index 74298e00..73a084c4 100755
--- a/aarch64/prelude.sail
+++ b/aarch64/prelude.sail
@@ -350,11 +350,11 @@ union option ('a : Type) = {
 }
 */
 
-val __SleepRequest = {ocaml: "sleep_request", lem: "sleep_request", smt: "sleep_request", interpreter: "sleep_request", c: "sleep_request"}: unit -> unit effect {escape, rreg, undef}
+val __SleepRequest = {ocaml: "sleep_request", lem: "sleep_request", smt: "sleep_request", interpreter: "sleep_request", c: "sleep_request"}: unit -> unit effect {rreg, undef}
 
-val __WakeupRequest = {ocaml: "wakeup_request", lem: "wakeup_request", smt: "wakeup_request", interpreter: "wakeup_request", c: "wakeup_request"}: unit -> unit effect {escape, rreg, undef}
+val __WakeupRequest = {ocaml: "wakeup_request", lem: "wakeup_request", smt: "wakeup_request", interpreter: "wakeup_request", c: "wakeup_request"}: unit -> unit effect {rreg, undef}
 
-val __Sleeping = {ocaml: "sleeping", lem: "sleeping", smt: "sleeping", interpreter: "sleeping", c: "sleeping"}: unit -> bool effect {escape, rreg, undef}
+val __Sleeping = {ocaml: "sleeping", lem: "sleeping", smt: "sleeping", interpreter: "sleeping", c: "sleeping"}: unit -> bool effect {rreg, undef}
 
-val __GetVerbosity = {c: "sail_get_verbosity"}: unit -> bits(64) effect {escape, rreg, undef}
+val __GetVerbosity = {c: "sail_get_verbosity"}: unit -> bits(64) effect {rreg, undef}
 
-- 
cgit v1.2.3


From 34ccf330f5a58be476cae325883b2d207389f36a Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Fri, 29 Jun 2018 01:23:36 +0100
Subject: RTS: tweak TIMEOUT message

Making the message more like archex messages simplifies tooling.
Plus, it is a better message.
---
 lib/rts.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/rts.c b/lib/rts.c
index 23e16921..84ff4916 100644
--- a/lib/rts.c
+++ b/lib/rts.c
@@ -427,7 +427,7 @@ bool cycle_limit_reached(const unit u)
 unit cycle_count(const unit u)
 {
   if (cycle_limit_reached(UNIT)) {
-    printf("\n[Sail] cycle limit %" PRId64 " reached\n", g_cycle_limit);
+    printf("\n[Sail] TIMEOUT: exceeded %" PRId64 " cycles\n", g_cycle_limit);
     exit(EXIT_SUCCESS);
   }
   return UNIT;
-- 
cgit v1.2.3


From b5424eea9c13935680b4cd6b76a377ff524699cd Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Fri, 29 Jun 2018 01:25:59 +0100
Subject: Main: many small tweaks.

While trying to track down some strange behaviour, I added a lot
more try-catch blocks that I think will be useful in the future.

Also dropped spurious escape effects on primops.

Also, only advance PC if we executed an instruction.
---
 aarch64/elfmain.sail | 52 +++++++++++++++++++++++++++++++++++-----------------
 1 file changed, 35 insertions(+), 17 deletions(-)

diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index a231cf64..faaa8cc1 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -13,7 +13,7 @@ let CNT_IRQ  = [0x0000_000d,       0x0000_000a,        0x0000_03ff,        0x000
 // SGI Interrupts are 0-15, PPI interrupts are 16-31, so SPI interrupts have an offset of 32.
 let SPI_OFFSET = 32
 
-val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {escape, undef, wreg, rreg, rmem, wmem}
+val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem}
 
 // Advance CPU by one cycle
 val Step_CPU : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem}
@@ -70,11 +70,11 @@ function Step_CPU() = {
             print(concat_str("IMPLEMENTATION_DEFINED ", concat_str(s, "\n")));
             exit();
           }
-      }
+      };
+      if ~(__PC_changed) then _PC = _PC + __currentInstrLength else ();
+      if ShouldAdvanceIT then AArch32_ITAdvance() else ();
+      SSAdvance();
   };
-  if ~(__PC_changed) then _PC = _PC + __currentInstrLength else ();
-  if ShouldAdvanceIT then AArch32_ITAdvance() else ();
-  SSAdvance();
   __UpdateSystemCounter(); // should this happen even if sleeping?
 }
 
@@ -135,11 +135,17 @@ function Step_Timers() = {
 }
 
 // Simple top level fetch and execute loop.
-val fetch_and_execute : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem}
+val Step_System : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem}
 
-function fetch_and_execute () = {
+function Step_System () = {
     try {
-      Step_Timers();
+      try {
+        Step_Timers();
+      } catch {
+        _ => {
+          print(concat_str("Exception taken during Step_Timers.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+        }
+      };
 
       var prevEL = PSTATE.EL;
       var prevI = PSTATE.I;
@@ -150,12 +156,18 @@ function fetch_and_execute () = {
       var prevCNTHCTL_EL2 = CNTHCTL_EL2;
 
       if ~(__Sleeping()) then {
+        try {
           Step_CPU();
+        } catch {
+          _ => {
+            print(concat_str("Exception taken during Step_CPU.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+          }
+        };
       };
 
       // We want to keep track of what exception level we are in for debugging purposes.
-      if UInt(prevEL) > UInt(PSTATE.EL) then {
-        prerr_bits("[Sail] Exception level dropped to: ", PSTATE.EL)
+      if UInt(prevEL) != UInt(PSTATE.EL) then {
+        prerr_bits(concat_str(concat_str("[Sail] ", DecStr(get_cycle_count())), " Exception level changed to: "), PSTATE.EL)
       };
       if prevI != PSTATE.I then {
 	prerr_bits("[Sail] PSTATE.I changed to: ", PSTATE.I);
@@ -169,9 +181,9 @@ function fetch_and_execute () = {
       }
 
     } catch {
-      Error_See(str) if str == "HINT" => (),
       Error_ExceptionTaken(_) => {
 	// enable_tracing()
+        print(concat_str("Exception taken during Step_System.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
         ()
       },
       _ => {
@@ -179,7 +191,14 @@ function fetch_and_execute () = {
         exit()
       }
     };
-    __EndCycle(); // advance state of non-sleeping parts of the system
+    try {
+        __EndCycle(); // advance state of non-sleeping parts of the system
+    } catch {
+      _ => {
+        print(concat_str("Exception taken during __EndCycle.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+      }
+    };
+
 }
 
 let COLD_RESET : bool = true
@@ -189,7 +208,6 @@ val "load_raw" : (bits(64), string) -> unit
 val init : unit -> unit effect {escape, undef, rreg, wreg}
 
 function init() = {
-  __currentInstrLength = 4;
   TakeReset(COLD_RESET);
 }
 
@@ -201,10 +219,10 @@ function main() = {
   let verbosity = __GetVerbosity();
   init();
   while true do {
-    fetch_and_execute();
-    check_cycle_count();
     if verbosity[0] == bitone then {
-        print(concat_str("[SAIL] PC=", concat_str(HexStr(UInt(aget_PC())), "\n")));
-    }
+        print(concat_str("[Sail] PC=", concat_str(HexStr(UInt(aget_PC())), "\n")));
+    };
+    Step_System();
+    check_cycle_count();
   }
 }
-- 
cgit v1.2.3


From 668ae1bc10fc1d9ea4d62ae0a2708a52cd83e211 Mon Sep 17 00:00:00 2001
From: Alasdair
Date: Thu, 21 Jun 2018 03:19:11 +0100
Subject: Constant folding improvements

---
 src/constant_fold.ml | 101 ++++++++++++++++++++++++++++++++++++++-------------
 src/interpreter.ml   |   2 -
 src/process_file.ml  |   2 +-
 src/type_check.ml    |  17 ---------
 src/value2.lem       |  20 ++++------
 5 files changed, 84 insertions(+), 58 deletions(-)

diff --git a/src/constant_fold.ml b/src/constant_fold.ml
index 7a35226e..45d3efe0 100644
--- a/src/constant_fold.ml
+++ b/src/constant_fold.ml
@@ -59,10 +59,25 @@ module StringMap = Map.Make(String);;
    false = no folding, true = perform constant folding. *)
 let optimize_constant_fold = ref false
 
-let exp_of_value =
+let rec fexp_of_ctor (field, value) =
+  FE_aux (FE_Fexp (mk_id field, exp_of_value value), no_annot)
+  
+and exp_of_value =
   let open Value in
   function
   | V_int n -> mk_lit_exp (L_num n)
+  | V_bit Sail_lib.B0 -> mk_lit_exp L_zero
+  | V_bit Sail_lib.B1 -> mk_lit_exp L_one
+  | V_bool true -> mk_lit_exp L_true
+  | V_bool false -> mk_lit_exp L_false
+  | V_string str -> mk_lit_exp (L_string str)
+  | V_record ctors ->
+     mk_exp (E_record (FES_aux (FES_Fexps (List.map fexp_of_ctor (StringMap.bindings ctors), false), no_annot)))
+  | V_vector vs ->
+     mk_exp (E_vector (List.map exp_of_value vs))
+  | V_tuple vs ->
+     mk_exp (E_tuple (List.map exp_of_value vs))
+  | V_unit -> mk_lit_exp L_unit
   | _ -> failwith "No expression for value"
 
 (* We want to avoid evaluating things like print statements at compile
@@ -85,15 +100,23 @@ let safe_primops =
       "Elf_loader.elf_tohost"
     ]
 
-let is_literal = function
-  | E_aux (E_lit _, _) -> true
+let rec is_constant (E_aux (e_aux, _)) =
+  match e_aux with
+  | E_lit _ -> true
+  | E_vector exps -> List.for_all is_constant exps
+  | E_record (FES_aux (FES_Fexps (fexps, _), _)) -> List.for_all is_constant_fexp fexps
+  | E_cast (_, exp) -> is_constant exp
+  | E_tuple exps -> List.for_all is_constant exps
   | _ -> false
 
+and is_constant_fexp (FE_aux (FE_Fexp (_, exp), _)) = is_constant exp
+
 (* Wrapper around interpreter that repeatedly steps until done. *)
 let rec run ast frame =
   match frame with
   | Interpreter.Done (state, v) -> v
-  | Interpreter.Step _ ->
+  | Interpreter.Step (lazy_str, _, _, _) ->
+     prerr_endline (Lazy.force lazy_str);
      run ast (Interpreter.eval_frame ast frame)
   | Interpreter.Break frame ->
      run ast (Interpreter.eval_frame ast frame)
@@ -115,35 +138,57 @@ let rec run ast frame =
    - Throws an exception that isn't caught.
  *)
 
-let rewrite_constant_function_calls' ast =
+let rec rewrite_constant_function_calls' ast =
+  let rewrite_count = ref 0 in
+  let ok () = incr rewrite_count in
+  let not_ok () = decr rewrite_count in
+  
   let lstate, gstate =
     Interpreter.initial_state ast safe_primops
   in
   let gstate = { gstate with Interpreter.allow_registers = false } in
 
+  let evaluate e_aux annot =
+    let initial_monad = Interpreter.return (E_aux (e_aux, annot)) in
+    try
+      begin
+        let v = run ast (Interpreter.Step (lazy "", (lstate, gstate), initial_monad, [])) in
+        let exp = exp_of_value v in
+        try (ok (); Type_check.check_exp (env_of_annot annot) exp (typ_of_annot annot)) with
+        | Type_error (l, err) ->
+           (* A type error here would be unexpected, so don't ignore it! *)
+           Util.warn ("Type error when folding constants in "
+                      ^ string_of_exp (E_aux (e_aux, annot))
+                      ^ "\n" ^ Type_error.string_of_type_error err);
+           not_ok ();
+           E_aux (e_aux, annot)
+      end
+    with
+    (* Otherwise if anything goes wrong when trying to constant
+       fold, just continue without optimising. *)
+    | _ -> E_aux (e_aux, annot)
+  in
+    
   let rw_funcall e_aux annot =
     match e_aux with
-    | E_app (id, args) when List.for_all is_literal args ->
-       begin
-         let initial_monad = Interpreter.return (E_aux (e_aux, annot)) in
-         try
-           begin
-             let v = run ast (Interpreter.Step (lazy "", (lstate, gstate), initial_monad, [])) in
-             let exp = exp_of_value v in
-             try Type_check.check_exp (env_of_annot annot) exp (typ_of_annot annot) with
-             | Type_error (l, err) ->
-                (* A type error here would be unexpected, so don't ignore it! *)
-                Util.warn ("Type error when folding constants in "
-                           ^ string_of_exp (E_aux (e_aux, annot))
-                           ^ "\n" ^ Type_error.string_of_type_error err);
-                E_aux (e_aux, annot)
-           end
-         with
-         (* Otherwise if anything goes wrong when trying to constant
-            fold, just continue without optimising. *)
-         | _ -> E_aux (e_aux, annot)
-       end
+    | E_app (id, args) when List.for_all is_constant args ->
+       evaluate e_aux annot
+
+    | E_field (exp, id) when is_constant exp ->
+       evaluate e_aux annot      
+
+    | E_if (E_aux (E_lit (L_aux (L_true, _)), _), then_exp, _) -> ok (); then_exp
+    | E_if (E_aux (E_lit (L_aux (L_false, _)), _), _, else_exp) -> ok (); else_exp
+
+    | E_let (LB_aux (LB_val (P_aux (P_id id, _), bind), _), exp) when is_constant bind ->
+       ok ();
+       subst id bind exp
 
+    | E_let (LB_aux (LB_val (P_aux (P_typ (typ, P_aux (P_id id, _)), annot), bind), _), exp)
+         when is_constant bind ->
+       ok ();
+       subst id (E_aux (E_cast (typ, bind), annot)) exp
+       
     | _ -> E_aux (e_aux, annot)
   in
   let rw_exp = {
@@ -151,7 +196,11 @@ let rewrite_constant_function_calls' ast =
       e_aux = (fun (e_aux, annot) -> rw_funcall e_aux annot)
     } in
   let rw_defs = { rewriters_base with rewrite_exp = (fun _ -> fold_exp rw_exp) } in
-  rewrite_defs_base rw_defs ast
+  let ast = rewrite_defs_base rw_defs ast in
+  (* We keep iterating until we have no more re-writes to do *)
+  if !rewrite_count > 0
+  then rewrite_constant_function_calls' ast
+  else ast
 
 let rewrite_constant_function_calls ast =
   if !optimize_constant_fold then
diff --git a/src/interpreter.ml b/src/interpreter.ml
index 00846d73..99d5889a 100644
--- a/src/interpreter.ml
+++ b/src/interpreter.ml
@@ -232,7 +232,6 @@ let is_value_fexp (FE_aux (FE_Fexp (id, exp), _)) = is_value exp
 let value_of_fexp (FE_aux (FE_Fexp (id, exp), _)) = (string_of_id id, value_of_exp exp)
 
 let rec build_letchain id lbs (E_aux (_, annot) as exp) =
-  (* print_endline ("LETCHAIN " ^ string_of_exp exp); *)
   match lbs with
   | [] -> exp
   | lb :: lbs when IdSet.mem id (letbind_pat_ids lb)->
@@ -311,7 +310,6 @@ let rec step (E_aux (e_aux, annot) as orig_exp) =
      else
        failwith "Match failure"
 
-
   | E_vector_subrange (vec, n, m) ->
      wrap (E_app (mk_id "vector_subrange_dec", [vec; n; m]))
   | E_vector_access (vec, n) ->
diff --git a/src/process_file.ml b/src/process_file.ml
index 9603e986..9ed52e8d 100644
--- a/src/process_file.ml
+++ b/src/process_file.ml
@@ -403,7 +403,7 @@ let rewrite_ast_ocaml = rewrite Rewrites.rewrite_defs_ocaml
 let rewrite_ast_c ast =
   ast
   |> rewrite Rewrites.rewrite_defs_c
-  |> Constant_fold.rewrite_constant_function_calls
+  |> rewrite [("constant_fold", Constant_fold.rewrite_constant_function_calls)]
 
 let rewrite_ast_interpreter = rewrite Rewrites.rewrite_defs_interpreter
 let rewrite_ast_check = rewrite Rewrites.rewrite_defs_check
diff --git a/src/type_check.ml b/src/type_check.ml
index 0a29b6d6..afdf41c9 100644
--- a/src/type_check.ml
+++ b/src/type_check.ml
@@ -132,28 +132,11 @@ let is_unknown_type = function
   | (Typ_aux (Typ_internal_unknown, _)) -> true
   | _ -> false
 
-(* An index_sort is a more general form of range type: it can either
-   be IS_int, which represents every natural number, or some set of
-   natural numbers given by an IS_prop expression of the form
-   {'n. f('n) <= g('n) /\ ...} *)
-type index_sort =
-  | IS_int
-  | IS_prop of kid * (nexp * nexp) list
-
-let string_of_index_sort = function
-  | IS_int -> "INT"
-  | IS_prop (kid, constraints) ->
-     "{" ^ string_of_kid kid ^ " | "
-     ^ string_of_list " & " (fun (x, y) -> string_of_nexp x ^ " <= " ^ string_of_nexp y) constraints
-     ^ "}"
-
 let is_atom (Typ_aux (typ_aux, _)) =
   match typ_aux with
   | Typ_app (f, [_]) when string_of_id f = "atom" -> true
   | _ -> false
 
-
-
 let rec strip_id = function
   | Id_aux (Id x, _) -> Id_aux (Id x, Parse_ast.Unknown)
   | Id_aux (DeIid x, _) -> Id_aux (DeIid x, Parse_ast.Unknown)
diff --git a/src/value2.lem b/src/value2.lem
index 33416503..d9fd1263 100644
--- a/src/value2.lem
+++ b/src/value2.lem
@@ -70,17 +70,13 @@ type vl =
   | V_record of list (string * vl)
   | V_null (* Used for unitialized values and null pointers in C compilation *)
 
-let primops extern args =
-  match (extern, args) with
-  | ("and_bool", [V_bool b1; V_bool b2]) -> V_bool (b1 && b2)
-  | ("and_bool", [V_nondet; V_bool false]) -> V_bool false
-  | ("and_bool", [V_bool false; V_nondet]) -> V_bool false
-  | ("and_bool", _) -> V_nondet
 
-  | ("or_bool", [V_bool b1; V_bool b2]) -> V_bool (b1 || b2)
-  | ("or_bool", [V_nondet; V_bool true]) -> V_bool true
-  | ("or_bool", [V_bool true; V_nondet]) -> V_bool true
-  | ("or_bool", _) -> V_nondet
+let value_int_op_int op = function
+  | [V_int v1; V_int v2] -> V_int (op v1 v2)
+  | _ -> V_null
+end
 
-  | _ -> failwith ("Unimplemented primitive operation " ^ extern)
-  end
+let value_bool_op_int op = function
+  | [V_int v1; V_int v2] -> V_bool (op v1 v2)
+  | _ -> V_null
+end
-- 
cgit v1.2.3


From 13301a0f3b70117bc19243e14b712ddbd5c35eb7 Mon Sep 17 00:00:00 2001
From: Alasdair
Date: Sat, 30 Jun 2018 03:20:15 +0100
Subject: Fix an issue with vector_update_subrange

vector_update_subrange wasn't setting its return length correctly
---
 lib/sail.c                    |  3 ++-
 test/c/large_bitvector.expect | 12 ++++++++++++
 test/c/large_bitvector.sail   | 30 ++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 test/c/large_bitvector.expect
 create mode 100644 test/c/large_bitvector.sail

diff --git a/lib/sail.c b/lib/sail.c
index 4e5694e9..31b11284 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -670,6 +670,7 @@ void vector_update_subrange_sail_bits(sail_bits *rop,
   uint64_t m = mpz_get_ui(m_mpz);
 
   mpz_set(*rop->bits, *op.bits);
+  rop->len = op.len;
 
   for (uint64_t i = 0; i < n - (m - 1ul); i++) {
     if (mpz_tstbit(*slice.bits, i)) {
@@ -685,7 +686,7 @@ void slice(sail_bits *rop, const sail_bits op, const sail_int start_mpz, const s
   uint64_t start = mpz_get_ui(start_mpz);
   uint64_t len = mpz_get_ui(len_mpz);
 
-  mpz_set_ui(*rop->bits, 0ul);
+  mpz_set_ui(*rop->bits, 0);
   rop->len = len;
 
   for (uint64_t i = 0; i < len; i++) {
diff --git a/test/c/large_bitvector.expect b/test/c/large_bitvector.expect
new file mode 100644
index 00000000..f67ec84a
--- /dev/null
+++ b/test/c/large_bitvector.expect
@@ -0,0 +1,12 @@
+x = 0x1FFFF0000FFFFFFFF
+length(x) = 68
+y = 0x1FFFF0000FFFFFFFF1FFFF0000FFFFFFFF1FFFF0000FFFFFFFF
+length(y) = 204
+z = 0x1FFFF0000FFFFFFFF1FFFF0000FFFFFFFF1CAFE0000FFFFFFFF
+length(z) = 204
+q = 0xFF0000FFFFFFFF1FFFF0000FFFFFFFF1CAFE0000FFFFFFFF
+w = -24519554509435141245919758063389544641259977658452672513
+length(q) = 192
+0x8000
+0b1 @ zeros(64 * 3 - 1) = 0x800000000000000000000000000000000000000000000000
+q                       = 0x800000000000000000000000000000000000000000000000
diff --git a/test/c/large_bitvector.sail b/test/c/large_bitvector.sail
new file mode 100644
index 00000000..78189d7d
--- /dev/null
+++ b/test/c/large_bitvector.sail
@@ -0,0 +1,30 @@
+default Order dec
+
+$include <arith.sail>
+$include <vector_dec.sail>
+
+val "zeros" : forall 'n. int('n) -> bits('n)
+
+val main : unit -> unit
+
+function main() = {
+  let x = [0x1FFFF0000FFFF0000 with 15 .. 0 = 0xFFFF];
+  print_bits("x = ", x);
+  print_int("length(x) = ", length(x));
+  let y = replicate_bits(x, 3);
+  print_bits("y = ", y);
+  print_int("length(y) = ", length(y));
+  let z = [y with 63 .. (63 - 15) = 0xCAFE];
+  print_bits("z = ", z);
+  print_int("length(z) = ", length(z));
+  q = slice(z, 0, 64 * 3);
+  print_bits("q = ", q);
+  w = signed(q);
+  print_int("w = ", w);
+  print_int("length(q) = ", length(q));
+  print_bits("", [0xFFFF with 14 .. 0 = zeros(15)]);
+  print_bits("0b1 @ zeros(64 * 3 - 1) = ", 0b1 @ zeros(64 * 3 - 1));
+  q[64 * 3 - 2 .. 0] = zeros(64 * 3 - 1);
+  print_bits("q                       = ", q);
+  ()
+}
-- 
cgit v1.2.3


From b513bcc0fa8270a9a653d9be33cc4f7bac4639cb Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Fri, 29 Jun 2018 19:29:17 +0100
Subject: Main: trivial restructuring of print commands to make them easier to
 read/maintain

---
 aarch64/elfmain.sail | 62 +++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 52 insertions(+), 10 deletions(-)

diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index faaa8cc1..d6350b5b 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -43,7 +43,11 @@ function Step_CPU() = {
       fetch_ok = true;
   } catch {
       Error_ExceptionTaken() => {
-        print(concat_str("Exception taken during IFetch from PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" in cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+        print(concat_str("Exception taken during IFetch from PC=",
+              concat_str(HexStr(UInt(aget_PC())),
+              concat_str(" in cycle=",
+              concat_str(DecStr(get_cycle_count()),
+              "\n")))));
       },
       _ => {
         print("Exiting due to unhandled exception during fetch\n");
@@ -62,12 +66,20 @@ function Step_CPU() = {
           Error_See(_)              => try { AArch64_UndefinedFault() } catch { _ => print("Exception during SEE recovery\n") },
           Error_ReservedEncoding(_) => try { AArch64_UndefinedFault() } catch { _ => print("Exception during ReservedEncoding recovery\n") },
           Error_ExceptionTaken() => {
-            print(concat_str("ExceptionTaken during Decode/Execute from PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" opcode=", concat_str(HexStr(UInt(__currentInstr)), concat_str(" in cycle ", concat_str(DecStr(get_cycle_count()), "\n")))))));
+            print(concat_str("ExceptionTaken during Decode/Execute from PC=",
+                  concat_str(HexStr(UInt(aget_PC())),
+                  concat_str(" opcode=",
+                  concat_str(HexStr(UInt(__currentInstr)),
+                  concat_str(" in cycle ",
+                  concat_str(DecStr(get_cycle_count()),
+                  "\n")))))));
             // print("  This might just be a HINT like 0xd50320df\n");
             ()
           },
           Error_Implementation_Defined(s) => {
-            print(concat_str("IMPLEMENTATION_DEFINED ", concat_str(s, "\n")));
+            print(concat_str("IMPLEMENTATION_DEFINED ",
+                  concat_str(s,
+                  "\n")));
             exit();
           }
       };
@@ -143,7 +155,11 @@ function Step_System () = {
         Step_Timers();
       } catch {
         _ => {
-          print(concat_str("Exception taken during Step_Timers.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+          print(concat_str("Exception taken during Step_Timers.  PC=",
+                concat_str(HexStr(UInt(aget_PC())),
+                concat_str(" cycle=",
+                concat_str(DecStr(get_cycle_count()),
+                "\n")))));
         }
       };
 
@@ -160,18 +176,29 @@ function Step_System () = {
           Step_CPU();
         } catch {
           _ => {
-            print(concat_str("Exception taken during Step_CPU.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+            print(concat_str("Exception taken during Step_CPU.  PC=",
+                  concat_str(HexStr(UInt(aget_PC())),
+                  concat_str(" cycle=",
+                  concat_str(DecStr(get_cycle_count()),
+                  "\n")))));
           }
         };
       };
 
       // We want to keep track of what exception level we are in for debugging purposes.
       if UInt(prevEL) != UInt(PSTATE.EL) then {
-        prerr_bits(concat_str(concat_str("[Sail] ", DecStr(get_cycle_count())), " Exception level changed to: "), PSTATE.EL)
+        prerr_bits(concat_str("[Sail] ",
+                   concat_str(DecStr(get_cycle_count()),
+                   " Exception level changed to: ")),
+                   PSTATE.EL);
       };
       if prevI != PSTATE.I then {
 	prerr_bits("[Sail] PSTATE.I changed to: ", PSTATE.I);
-        print(concat_str("   at PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" in cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+        print(concat_str("   at PC=",
+              concat_str(HexStr(UInt(aget_PC())),
+              concat_str(" in cycle=",
+              concat_str(DecStr(get_cycle_count()),
+              "\n")))));
       };
       if prevCNTKCTL_EL1 != CNTKCTL_EL1 then {
         prerr_bits("[Clock] CNTKCTL_EL1 changed to ", CNTKCTL_EL1);
@@ -183,7 +210,11 @@ function Step_System () = {
     } catch {
       Error_ExceptionTaken(_) => {
 	// enable_tracing()
-        print(concat_str("Exception taken during Step_System.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+        print(concat_str("Exception taken during Step_System.  PC=",
+              concat_str(HexStr(UInt(aget_PC())),
+              concat_str(" cycle=",
+              concat_str(DecStr(get_cycle_count()),
+              "\n")))));
         ()
       },
       _ => {
@@ -195,7 +226,11 @@ function Step_System () = {
         __EndCycle(); // advance state of non-sleeping parts of the system
     } catch {
       _ => {
-        print(concat_str("Exception taken during __EndCycle.  PC=", concat_str(HexStr(UInt(aget_PC())), concat_str(" cycle=", concat_str(DecStr(get_cycle_count()), "\n")))));
+        print(concat_str("Exception taken during __EndCycle.  PC=",
+              concat_str(HexStr(UInt(aget_PC())),
+              concat_str(" cycle=",
+              concat_str(DecStr(get_cycle_count()),
+              "\n")))));
       }
     };
 
@@ -220,7 +255,14 @@ function main() = {
   init();
   while true do {
     if verbosity[0] == bitone then {
-        print(concat_str("[Sail] PC=", concat_str(HexStr(UInt(aget_PC())), "\n")));
+        nzcv = (PSTATE.N @ PSTATE.Z @ PSTATE.C @ PSTATE.V);
+        print(concat_str("[Sail] ",
+              concat_str(DecStr(get_cycle_count()),
+              concat_str(" PC=",
+              concat_str(HexStr(UInt(aget_PC())),
+              concat_str(" NZCV=",
+              concat_str(HexStr(UInt(nzcv)),
+              "\n")))))));
     };
     Step_System();
     check_cycle_count();
-- 
cgit v1.2.3


From 38e91b0f24b3ed0f022626d059ca4186e2ec43df Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Sat, 30 Jun 2018 19:19:35 +0100
Subject: RTS: Add length asserts to bits ops

Added assertions to check that length of bit operations
is sensible (i.e., consistent with type system).
---
 lib/sail.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/lib/sail.c b/lib/sail.c
index 31b11284..f5ddfc62 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -1,3 +1,4 @@
+#include<assert.h>
 #include<inttypes.h>
 #include<stdbool.h>
 #include<stdio.h>
@@ -419,6 +420,7 @@ void add_bits(sail_bits *rop, const sail_bits op1, const sail_bits op2)
 
 void sub_bits(sail_bits *rop, const sail_bits op1, const sail_bits op2)
 {
+  assert(op1.len == op2.len);
   rop->len = op1.len;
   mpz_sub(*rop->bits, *op1.bits, *op2.bits);
   normalize_sail_bits(rop);
@@ -440,18 +442,21 @@ void sub_bits_int(sail_bits *rop, const sail_bits op1, const mpz_t op2)
 
 void and_bits(sail_bits *rop, const sail_bits op1, const sail_bits op2)
 {
+  assert(op1.len == op2.len);
   rop->len = op1.len;
   mpz_and(*rop->bits, *op1.bits, *op2.bits);
 }
 
 void or_bits(sail_bits *rop, const sail_bits op1, const sail_bits op2)
 {
+  assert(op1.len == op2.len);
   rop->len = op1.len;
   mpz_ior(*rop->bits, *op1.bits, *op2.bits);
 }
 
 void xor_bits(sail_bits *rop, const sail_bits op1, const sail_bits op2)
 {
+  assert(op1.len == op2.len);
   rop->len = op1.len;
   mpz_xor(*rop->bits, *op1.bits, *op2.bits);
 }
@@ -495,12 +500,14 @@ void zeros(sail_bits *rop, const sail_int op)
 
 void zero_extend(sail_bits *rop, const sail_bits op, const sail_int len)
 {
+  assert(op.len <= mpz_get_ui(len));
   rop->len = mpz_get_ui(len);
   mpz_set(*rop->bits, *op.bits);
 }
 
 void sign_extend(sail_bits *rop, const sail_bits op, const sail_int len)
 {
+  assert(op.len <= mpz_get_ui(len));
   rop->len = mpz_get_ui(len);
   if(mpz_tstbit(*op.bits, op.len - 1)) {
     mpz_set(*rop->bits, *op.bits);
@@ -519,6 +526,7 @@ void length_sail_bits(sail_int *rop, const sail_bits op)
 
 bool eq_bits(const sail_bits op1, const sail_bits op2)
 {
+  assert(op1.len == op2.len);
   for (mp_bitcnt_t i = 0; i < op1.len; i++) {
     if (mpz_tstbit(*op1.bits, i) != mpz_tstbit(*op2.bits, i)) return false;
   }
@@ -527,6 +535,7 @@ bool eq_bits(const sail_bits op1, const sail_bits op2)
 
 bool neq_bits(const sail_bits op1, const sail_bits op2)
 {
+  assert(op1.len == op2.len);
   for (mp_bitcnt_t i = 0; i < op1.len; i++) {
     if (mpz_tstbit(*op1.bits, i) != mpz_tstbit(*op2.bits, i)) return true;
   }
@@ -548,6 +557,7 @@ void vector_subrange_sail_bits(sail_bits *rop,
 
 void sail_truncate(sail_bits *rop, const sail_bits op, const sail_int len)
 {
+  assert(op.len >= mpz_get_ui(len));
   rop->len = mpz_get_ui(len);
   mpz_set(*rop->bits, *op.bits);
   normalize_sail_bits(rop);
@@ -683,6 +693,7 @@ void vector_update_subrange_sail_bits(sail_bits *rop,
 
 void slice(sail_bits *rop, const sail_bits op, const sail_int start_mpz, const sail_int len_mpz)
 {
+  assert(mpz_get_ui(start_mpz) + mpz_get_ui(len_mpz) <= op.len);
   uint64_t start = mpz_get_ui(start_mpz);
   uint64_t len = mpz_get_ui(len_mpz);
 
-- 
cgit v1.2.3


From 5361c1d65c469cf9cdaeea345c4779f9c88aad55 Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Sat, 30 Jun 2018 20:21:30 +0100
Subject: RTS: fix replicate_bits

Fixes handling of Replicate(x, 0).
---
 lib/sail.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/sail.c b/lib/sail.c
index f5ddfc62..4e033c2a 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -604,8 +604,8 @@ void replicate_bits(sail_bits *rop, const sail_bits op1, const mpz_t op2)
 {
   uint64_t op2_ui = mpz_get_ui(op2);
   rop->len = op1.len * op2_ui;
-  mpz_set(*rop->bits, *op1.bits);
-  for (int i = 1; i < op2_ui; i++) {
+  mpz_set_ui(*rop->bits, 0);
+  for (int i = 0; i < op2_ui; i++) {
     mpz_mul_2exp(*rop->bits, *rop->bits, op1.len);
     mpz_ior(*rop->bits, *rop->bits, *op1.bits);
   }
-- 
cgit v1.2.3


From 117e87ce194c50b2221c7fd1966d6e0369423606 Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Sun, 1 Jul 2018 19:34:08 +0100
Subject: RTS: Fail on AArch32 and ASIMD

This change causes execution of AArch32 code or ASIMD code
to fail with an easily diagnosed error message of the form

   UNIMPLEMENTED: xxx support

where xxx is either AArch32 or ASIMD.

Having a clear error message allows these to be detected by triaging
scripts.

To make the AArch32 detection part work, you also need to change
HaveAnyAArch32 to read like this instead of just returning false.

    function HaveAnyAArch32 () =
      return ((CFG_ID_AA64PFR0_EL1_EL0 == 0x2)
              || (CFG_ID_AA64PFR0_EL1_EL1 == 0x2)
              || (CFG_ID_AA64PFR0_EL1_EL2 == 0x2)
              || (CFG_ID_AA64PFR0_EL1_EL3 == 0x2))
---
 aarch64/elfmain.sail | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index d6350b5b..bccbbda5 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -38,6 +38,10 @@ function Step_CPU() = {
 
   var fetch_ok = false;
   try {
+      if PSTATE.nRW != bitzero then {
+        print("UNIMPLEMENTED: AArch32 support\n");
+        exit()
+      };
       __currentInstr       = __fetchA64();
       __currentInstrLength = 4;
       fetch_ok = true;
@@ -56,6 +60,46 @@ function Step_CPU() = {
   };
 
   if fetch_ok then {
+      // Detect ASIMD instructions
+      is_asimd : bool = match __currentInstr {
+        // '0x00 110' @ _ : bits(25)   => true,  // ASIMD memory
+        0b0000110     @ (_ : bits(25)) => true,
+        0b0100110     @ (_ : bits(25)) => true,
+
+        // '0xx0111'  @ _ : bits(25)   => true,  // ASIMD
+        // '01x1111'  @ _ : bits(25)   => true,  // ASIMD
+        // 'x0x1111'  @ _ : bits(25)   => false, // FP
+        // '1xx0111'  @ _ : bits(25)   => false, // unallocated
+        // '11xx111'  @ _ : bits(25)   => false, // Crypto
+
+        0b0000111     @ (_ : bits(25)) => true,
+        0b0001111     @ (_ : bits(25)) => false,
+        0b0010111     @ (_ : bits(25)) => true,
+        0b0011111     @ (_ : bits(25)) => false,
+
+        0b0100111     @ (_ : bits(25)) => true,
+        0b0101111     @ (_ : bits(25)) => true,
+        0b0110111     @ (_ : bits(25)) => true,
+        0b0111111     @ (_ : bits(25)) => true,
+
+        0b1000111     @ (_ : bits(25)) => false,
+        0b1001111     @ (_ : bits(25)) => false,
+        0b1010111     @ (_ : bits(25)) => false,
+        0b1011111     @ (_ : bits(25)) => false,
+
+        0b1100111     @ (_ : bits(25)) => false,
+        0b1101111     @ (_ : bits(25)) => false,
+        0b1110111     @ (_ : bits(25)) => false,
+        0b1111111     @ (_ : bits(25)) => false,
+
+        _ => false
+      };
+      if is_asimd then {
+        print(concat_str("UNIMPLEMENTED: ASIMD support ",
+              concat_str(HexStr(UInt(__currentInstr)),
+              "\n")));
+        exit()
+      };
       try {
           __PC_changed = false;
           ShouldAdvanceIT = (PSTATE.nRW == [bitone]) & (PSTATE.T == [bitone]);
-- 
cgit v1.2.3


From d3025dc25f3e9c8f416dc304980945e82f5ee01e Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Fri, 29 Jun 2018 15:07:55 +0100
Subject: optimise cheri c build.

---
 cheri/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cheri/Makefile b/cheri/Makefile
index 1cd9ecc7..419fa4e1 100644
--- a/cheri/Makefile
+++ b/cheri/Makefile
@@ -36,7 +36,7 @@ coverage_report: bisect*.out
 	bisect-ppx-report -I _sbuild/_build -html $@ $^
 
 cheri.c: $(CHERI_SAILS) $(CHERI_MAIN)
-	$(SAIL) -memo_z3 -c $^ 1> $@
+	$(SAIL) -memo_z3 -O -c $^ 1> $@
 
 cheri_c: cheri.c ../lib/sail.h Makefile
 	gcc -O2 $< ../lib/*.c -lgmp -lz -I ../lib/ -o $@
-- 
cgit v1.2.3


From 61e4b53642c9ff30a82a600f23985e7555a67a0b Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Mon, 2 Jul 2018 17:01:02 +0100
Subject: cheri: the default cap for 256-bits no longer has reserved bits set.

---
 cheri/cheri_prelude_256.sail | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cheri/cheri_prelude_256.sail b/cheri/cheri_prelude_256.sail
index babfc117..08e285e7 100644
--- a/cheri/cheri_prelude_256.sail
+++ b/cheri/cheri_prelude_256.sail
@@ -86,7 +86,7 @@ let default_cap : CapStruct = struct {
   padding = zeros(),
   otype = zeros(),
   uperms = ones(),
-  perm_reserved11_14 = ones(),
+  perm_reserved11_14 = zeros(),
   access_system_regs = true,
   permit_unseal = true,
   permit_ccall = true,
@@ -178,7 +178,7 @@ function capStructToCapReg(cap) : CapStruct -> CapReg = cap.tag @ capStructToMem
 function setCapPerms(cap, perms) : (CapStruct, bits(31)) -> CapStruct =
     { cap with
       uperms                 = perms[30..15],
-      perm_reserved11_14     = perms[14..11],
+      /* perm_reserved11_14     = perms[14..11], XXX should allow to set? only affects cbuildcap. */
       access_system_regs     = perms[10],
       permit_unseal          = perms[9],
       permit_ccall           = perms[8],
-- 
cgit v1.2.3


From b89abf9c9e1a32892c14ab3c2e92656b1410ecac Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 29 Jun 2018 12:07:00 +0100
Subject: Coq building rule in MIPS makefile

---
 mips/Makefile | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/mips/Makefile b/mips/Makefile
index a8bce143..d3a21957 100644
--- a/mips/Makefile
+++ b/mips/Makefile
@@ -47,6 +47,13 @@ mips.v: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS)
 	$(SAIL) -coq -dcoq_undef_axioms -o mips -coq_lib mips_extras -undefined_gen -memo_z3 $^
 mips_types.v: mips.v
 
+MIPS_COQ = mips_types.v mips_extras.v mips.v
+COQ_LIBS = -R ../../bbv bbv -R ../lib/coq Sail
+
+%.vo: %.v
+	coqc $(COQ_LIBS) $<
+mips.vo: mips_types.vo mips_extras.vo
+
 M%.thy: m%.lem m%_types.lem mips_extras.lem
 	lem -isa -outdir . -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^
 	sed -i 's/datatype ast/datatype (plugins only: size) ast/' M$*_types.thy
@@ -63,5 +70,5 @@ include ../etc/loc.mk
 clean:
 	rm -rf mips Mips.thy mips.lem mips_types.lem _sbuild mips.c mips_c
 	rm -f mipsScript.sml mips_typesScript.sml mips_extrasScript.sml
-	rm -f mips.v mips_types.v
+	rm -f mips.v mips_types.v $(MIPS_COQ:%.v=%.vo) $(MIPS_COQ:%.v=%.glob) $(MIPS_COQ:%.v=.%.aux)
 	-Holmake cleanAll
-- 
cgit v1.2.3


From e0059c15e282c98bc227962a1df6ae0ad34de477 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 2 Jul 2018 13:00:58 +0100
Subject: Work around Coq issue with pattern binders

---
 src/pretty_print_coq.ml | 51 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 35 insertions(+), 16 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index ffe376e0..8d9dd881 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -537,9 +537,9 @@ let doc_typquant_items ctx delimit (TypQ_aux (tq,_)) =
 let doc_typquant_items_separate ctx delimit (TypQ_aux (tq,_)) =
   match tq with
   | TypQ_tq qis ->
-     separate_opt space (doc_quant_item_id ctx delimit) qis,
-     separate_opt space (doc_quant_item_constr ctx delimit) qis
-  | TypQ_no_forall -> empty, empty
+     Util.map_filter (doc_quant_item_id ctx delimit) qis,
+     Util.map_filter (doc_quant_item_constr ctx delimit) qis
+  | TypQ_no_forall -> [], []
 
 let doc_typquant ctx (TypQ_aux(tq,_)) typ = match tq with
 | TypQ_tq ((_ :: _) as qs) ->
@@ -1485,14 +1485,6 @@ let merge_kids_atoms pats =
   let gone,map,_ = List.fold_left try_eliminate (KidSet.empty, KBindings.empty, KidSet.empty) pats in
   gone,map
 
-let doc_binder ctxt (P_aux (p,ann) as pat, typ) =
-  let env = env_of_annot ann in
-  let exp_typ = Env.expand_synonyms env typ in
-  match p with
-  | P_id id
-  | P_typ (_,P_aux (P_id id,_)) when Util.is_none (is_auto_decomposed_exist env exp_typ) ->
-     parens (separate space [doc_id id; colon; doc_typ ctxt typ])
-  | _ -> squote ^^ parens (separate space [doc_pat ctxt true (pat, exp_typ); colon; doc_typ ctxt typ])
 
 let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
   let (tq,typ) = Env.get_val_spec_orig id (env_of_annot annot) in
@@ -1516,22 +1508,48 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
      been replaced by one of the term-level arguments is bound. *)
   let quantspp, constrspp = doc_typquant_items_separate ctxt braces tq in
   let exp = List.fold_left (fun body f -> f body) (bind exp) binds in
-  let patspp = separate_map space (doc_binder ctxt) pats in
-  let atom_constr_pp = separate_opt space (atom_constraint ctxt) pats in
+  let used_a_pattern = ref false in
+  let doc_binder (P_aux (p,ann) as pat, typ) =
+    let env = env_of_annot ann in
+    let exp_typ = Env.expand_synonyms env typ in
+    match p with
+    | P_id id
+    | P_typ (_,P_aux (P_id id,_)) when Util.is_none (is_auto_decomposed_exist env exp_typ) ->
+       parens (separate space [doc_id id; colon; doc_typ ctxt typ])
+    | _ ->
+       (used_a_pattern := true;
+        squote ^^ parens (separate space [doc_pat ctxt true (pat, exp_typ); colon; doc_typ ctxt typ]))
+  in
+  let patspp = separate_map space doc_binder pats in
+  let atom_constrs = Util.map_filter (atom_constraint ctxt) pats in
+  let atom_constr_pp = separate space atom_constrs in
   let retpp =
     if effectful eff
     then string "M" ^^ space ^^ parens (doc_typ ctxt ret_typ)
     else doc_typ ctxt ret_typ
   in
+  let idpp = doc_id id in
+  (* Work around Coq bug 7975 about pattern binders followed by implicit arguments *)
+  let implicitargs =
+    if !used_a_pattern && List.length constrspp + List.length atom_constrs > 0 then
+      separate space
+        ([string "Arguments"; idpp;] @
+            List.map (fun _ -> string "{_}") quantspp @
+            List.map (fun _ -> string "_") pats @
+            List.map (fun _ -> string "{_}") constrspp @
+            List.map (fun _ -> string "{_}") atom_constrs)
+      ^^ dot
+    else empty
+  in
   let _ = match guard with
     | None -> ()
     | _ ->
        raise (Reporting_basic.err_unreachable l
                 "guarded pattern expression should have been rewritten before pretty-printing") in
   group (prefix 3 1
-    (separate space [doc_id id; quantspp; patspp; constrspp; atom_constr_pp] ^/^
+    (separate space ([idpp] @ quantspp @ [patspp] @ constrspp @ [atom_constr_pp]) ^/^
        colon ^^ space ^^ retpp ^^ coloneq)
-    (doc_fun_body ctxt exp ^^ dot))
+    (doc_fun_body ctxt exp ^^ dot)) ^/^ implicitargs
 
 let get_id = function
   | [] -> failwith "FD_function with empty list"
@@ -1660,7 +1678,8 @@ let doc_axiom_typschm typ_env (TypSchm_aux (TypSchm_ts (tqs,typ),l) as ts) =
      let arg_typs_pp = separate space (List.map doc_typ' typs) in
      let ret_typ_pp = doc_typ empty_ctxt ret_ty in
      let tyvars_pp, constrs_pp = doc_typquant_items_separate empty_ctxt braces tqs in
-     string "forall" ^/^ tyvars_pp ^/^ arg_typs_pp ^/^ constrs_pp ^^ comma ^/^ ret_typ_pp
+     string "forall" ^/^ separate space tyvars_pp ^/^
+       arg_typs_pp ^/^ separate space constrs_pp ^^ comma ^/^ ret_typ_pp
   | _ -> doc_typschm empty_ctxt true ts
 
 let doc_val_spec unimplemented (VS_aux (VS_val_spec(tys,id,_,_),ann)) =
-- 
cgit v1.2.3


From 02923ba7a62b7b383a02fb04c40be31ffbdb75a4 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 2 Jul 2018 17:18:48 +0100
Subject: Coq: multiple record field updates Uses simple method of printing the
 entire record, in lieu of any decent record update syntax.

---
 src/pretty_print_coq.ml | 26 +++++++++++++++++++++++---
 src/type_check.ml       |  3 +++
 src/type_check.mli      |  3 +++
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 8d9dd881..6d9cbfc1 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1048,13 +1048,33 @@ let doc_exp_lem, doc_let_lem =
                                           (doc_fexp ctxt recordtyp) fexps)) in
        if aexp_needed then parens epp else epp
     | E_record_update(e,(FES_aux(FES_Fexps(fexps,_),_))) ->
-       let recordtyp = match annot with
+       let recordtyp, env = match annot with
          | Some (env, Typ_aux (Typ_id tid,_), _)
          | Some (env, Typ_aux (Typ_app (tid, _), _), _)
            when Env.is_record tid env ->
-           tid
+           tid, env
          | _ ->  raise (report l ("cannot get record type from annot " ^ string_of_annot annot ^ " of exp " ^ string_of_exp full_exp)) in
-       enclose_record_update (doc_op (string "with") (expY e) (separate_map semi_sp (doc_fexp ctxt recordtyp) fexps))
+       if List.length fexps > 1 then
+         let _,fields = Env.get_record recordtyp env in
+         let var, let_pp =
+           match e with
+           | E_aux (E_id id,_) -> id, empty
+           | _ -> let v = mk_id "_record" in (* TODO: collision avoid *)
+                  v, separate space [string "let "; doc_id v; coloneq; top_exp ctxt true e; string "in"] ^^ break 1
+         in
+         let doc_field (_,id) =
+           match List.find (fun (FE_aux (FE_Fexp (id',_),_)) -> Id.compare id id' == 0) fexps with
+           | fexp -> doc_fexp ctxt recordtyp fexp
+           | exception Not_found ->
+               let fname =
+                 if prefix_recordtype && string_of_id recordtyp <> "regstate"
+                 then (string (string_of_id recordtyp ^ "_")) ^^ doc_id id
+                 else doc_id id in
+               doc_op coloneq fname (doc_id var ^^ dot ^^ parens fname)
+         in let_pp ^^ enclose_record (align (separate_map (semi_sp ^^ break 1)
+                                               doc_field fields))
+       else
+         enclose_record_update (doc_op (string "with") (expY e) (separate_map semi_sp (doc_fexp ctxt recordtyp) fexps))
     | E_vector exps ->
        let t = Env.base_typ_of (env_of full_exp) (typ_of full_exp) in
        let start, (len, order, etyp) =
diff --git a/src/type_check.ml b/src/type_check.ml
index afdf41c9..db85bf33 100644
--- a/src/type_check.ml
+++ b/src/type_check.ml
@@ -355,6 +355,7 @@ module Env : sig
   val is_mapping : id -> t -> bool
   val add_record : id -> typquant -> (typ * id) list -> t -> t
   val is_record : id -> t -> bool
+  val get_record : id -> t -> typquant * (typ * id) list
   val get_accessor_fn : id -> id -> t -> typquant * typ
   val get_accessor : id -> id -> t -> typquant * typ * typ * effect
   val add_local : id -> mut * typ -> t -> t
@@ -917,6 +918,8 @@ end = struct
 
   let is_record id env = Bindings.mem id env.records
 
+  let get_record id env = Bindings.find id env.records
+
   let add_record id typq fields env =
     if bound_typ_id env id
     then typ_error (id_loc id) ("Cannot create record " ^ string_of_id id ^ ", type name is already bound")
diff --git a/src/type_check.mli b/src/type_check.mli
index 4f87e4e6..fd1ddb92 100644
--- a/src/type_check.mli
+++ b/src/type_check.mli
@@ -136,6 +136,9 @@ module Env : sig
 
   val is_record : id -> t -> bool
 
+  (** Returns record quantifiers and fields *)
+  val get_record : id -> t -> typquant * (typ * id) list
+
   (** Return type is: quantifier, argument type, return type, effect *)
   val get_accessor : id -> id -> t -> typquant * typ * typ * effect
 
-- 
cgit v1.2.3


From e6b40776a3c963ad3d16b644ba283d2d955cf0b5 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 2 Jul 2018 17:19:34 +0100
Subject: Coq: replace simpl in a tactic with a more precise "change" Prevents
 partial unfolding of Z.pow.

---
 lib/coq/Sail2_values.v | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 137be85c..ee8ea6a1 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -861,10 +861,17 @@ Ltac unbool_comparisons :=
   | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H
   end.
 (* Split up dependent pairs to get at proofs of properties *)
-(* TODO: simpl is probably too strong here *)
 Ltac extract_properties :=
-  repeat match goal with H := (projT1 ?X) |- _ => destruct X in *; simpl in H; unfold H in * end;
-  repeat match goal with |- context [projT1 ?X] => destruct X in *; simpl end.
+  repeat match goal with H := (projT1 ?X) |- _ =>
+    let x := fresh "x" in
+    let Hx := fresh "Hx" in
+    destruct X as [x Hx] in *;
+    change (projT1 (existT _ x Hx)) with x in *; unfold H in * end;
+  repeat match goal with |- context [projT1 ?X] =>
+    let x := fresh "x" in
+    let Hx := fresh "Hx" in
+    destruct X as [x Hx] in *;
+    change (projT1 (existT _ x Hx)) with x in * end.
 (* TODO: hyps, too? *)
 Ltac reduce_list_lengths :=
   repeat match goal with |- context [length_list ?X] => 
-- 
cgit v1.2.3


From fe5e67979d26bfa3c8c51863b24d97ab5553d56b Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 2 Jul 2018 17:56:23 +0100
Subject: Coq modulus operation that fits the type

---
 mips/mips_extras.v | 10 ++++++++++
 mips/prelude.sail  |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/mips/mips_extras.v b/mips/mips_extras.v
index b9dd6138..94e4779c 100644
--- a/mips/mips_extras.v
+++ b/mips/mips_extras.v
@@ -138,6 +138,16 @@ Definition eq_bit (x : bitU) (y : bitU) : bool :=
   | _,_ => false
   end.
 
+Require Import Zeuclid.
+Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
+refine (build_ex (ZEuclid.modulo m n)).
+constructor.
+destruct H.
+assert (Zabs n = n). { rewrite Zabs_eq; auto with zarith. }
+rewrite <- H at 3.
+lapply (ZEuclid.mod_always_pos m n); omega.
+Qed.
+
 (* Override the more general version *)
 
 Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
diff --git a/mips/prelude.sail b/mips/prelude.sail
index c411ad83..b3349799 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -104,7 +104,7 @@ overload operator / = {quotient_nat, quotient}
 val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot", coq: "Z.quot", _ : "tdiv_int"} : (int, int) -> int
 val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod", coq: "Z.rem", _ : "tmod_int"} : (int, int) -> int
 
-val modulus = {ocaml: "modulus", lem: "hardware_mod", _ : "tmod_int"} : forall 'n, 'n > 0 .  (int, atom('n)) -> range(0, 'n - 1)
+val modulus = {ocaml: "modulus", lem: "hardware_mod", coq: "euclid_modulo", _ : "tmod_int"} : forall 'n, 'n > 0 .  (int, atom('n)) -> range(0, 'n - 1)
 
 overload operator % = {modulus}
 
-- 
cgit v1.2.3


From 1f323e30d1e476e234ccfdaff9f9583d714e8854 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 2 Jul 2018 17:56:39 +0100
Subject: Coq: tidy up a bit of printing

---
 src/pretty_print_coq.ml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 6d9cbfc1..78507577 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1552,7 +1552,7 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
   (* Work around Coq bug 7975 about pattern binders followed by implicit arguments *)
   let implicitargs =
     if !used_a_pattern && List.length constrspp + List.length atom_constrs > 0 then
-      separate space
+      break 1 ^^ separate space
         ([string "Arguments"; idpp;] @
             List.map (fun _ -> string "{_}") quantspp @
             List.map (fun _ -> string "_") pats @
@@ -1568,8 +1568,8 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
                 "guarded pattern expression should have been rewritten before pretty-printing") in
   group (prefix 3 1
     (separate space ([idpp] @ quantspp @ [patspp] @ constrspp @ [atom_constr_pp]) ^/^
-       colon ^^ space ^^ retpp ^^ coloneq)
-    (doc_fun_body ctxt exp ^^ dot)) ^/^ implicitargs
+       separate space [colon; retpp; coloneq])
+    (doc_fun_body ctxt exp ^^ dot)) ^^ implicitargs
 
 let get_id = function
   | [] -> failwith "FD_function with empty list"
-- 
cgit v1.2.3


From 03b583083bc184af4e195e3cb53f5d47f6912403 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 2 Jul 2018 18:49:18 +0100
Subject: Coq: add some string functions

---
 lib/coq/Sail2_operators_mwords.v |  5 +--
 lib/coq/Sail2_values.v           | 71 ++++++++++++++++++++++++----------------
 2 files changed, 45 insertions(+), 31 deletions(-)

diff --git a/lib/coq/Sail2_operators_mwords.v b/lib/coq/Sail2_operators_mwords.v
index ee98c94e..bb4bf053 100644
--- a/lib/coq/Sail2_operators_mwords.v
+++ b/lib/coq/Sail2_operators_mwords.v
@@ -3,6 +3,7 @@ Require Import Sail2_operators.
 Require Import Sail2_prompt_monad.
 Require Import Sail2_prompt.
 Require Import bbv.Word.
+Require bbv.BinNotation.
 Require Import Arith.
 Require Import ZArith.
 Require Import Omega.
@@ -267,8 +268,8 @@ Definition msb := most_significant
 val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer
 Definition int_of_vec := int_of_bv
 
-val string_of_vec : forall 'a. Size 'a => mword 'a -> string
-Definition string_of_vec := string_of_bv*)
+val string_of_vec : forall 'a. Size 'a => mword 'a -> string*)
+Definition string_of_bits {n} (w : mword n) : string := string_of_bv w.
 Definition with_word' {n} (P : Type -> Type) : (forall n, Word.word n -> P (Word.word n)) -> mword n -> P (mword n) := fun f w => @with_word n _ (f (Z.to_nat n)) w.
 Definition word_binop {n} (f : forall n, Word.word n -> Word.word n -> Word.word n) : mword n -> mword n -> mword n := with_word' (fun x => x -> x) f.
 Definition word_unop {n} (f : forall n, Word.word n -> Word.word n) : mword n -> mword n := with_word' (fun x => x) f.
diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index ee8ea6a1..d1f6e560 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -2,6 +2,7 @@
 
 (*Require Import Sail_impl_base*)
 Require Export ZArith.
+Require Import Ascii.
 Require Export String.
 Require Import bbv.Word.
 Require Export List.
@@ -196,6 +197,13 @@ match b with
   | BU => "U"
 end%string.
 
+Definition bitU_char b :=
+match b with
+| B0 => "0"
+| B1 => "1"
+| BU => "?"
+end%char.
+
 (*instance (Show bitU)
   let show := showBitU
 end*)
@@ -463,47 +471,52 @@ Definition arith_op_bits (op : Z -> Z -> Z) (sign : bool) l r :=
   end.
 
 
-(*
-Definition char_of_nibble := function
-  | (B0, B0, B0, B0) => Some #'0'
-  | (B0, B0, B0, B1) => Some #'1'
-  | (B0, B0, B1, B0) => Some #'2'
-  | (B0, B0, B1, B1) => Some #'3'
-  | (B0, B1, B0, B0) => Some #'4'
-  | (B0, B1, B0, B1) => Some #'5'
-  | (B0, B1, B1, B0) => Some #'6'
-  | (B0, B1, B1, B1) => Some #'7'
-  | (B1, B0, B0, B0) => Some #'8'
-  | (B1, B0, B0, B1) => Some #'9'
-  | (B1, B0, B1, B0) => Some #'A'
-  | (B1, B0, B1, B1) => Some #'B'
-  | (B1, B1, B0, B0) => Some #'C'
-  | (B1, B1, B0, B1) => Some #'D'
-  | (B1, B1, B1, B0) => Some #'E'
-  | (B1, B1, B1, B1) => Some #'F'
+Definition char_of_nibble x :=
+  match x with
+  | (B0, B0, B0, B0) => Some "0"%char
+  | (B0, B0, B0, B1) => Some "1"%char
+  | (B0, B0, B1, B0) => Some "2"%char
+  | (B0, B0, B1, B1) => Some "3"%char
+  | (B0, B1, B0, B0) => Some "4"%char
+  | (B0, B1, B0, B1) => Some "5"%char
+  | (B0, B1, B1, B0) => Some "6"%char
+  | (B0, B1, B1, B1) => Some "7"%char
+  | (B1, B0, B0, B0) => Some "8"%char
+  | (B1, B0, B0, B1) => Some "9"%char
+  | (B1, B0, B1, B0) => Some "A"%char
+  | (B1, B0, B1, B1) => Some "B"%char
+  | (B1, B1, B0, B0) => Some "C"%char
+  | (B1, B1, B0, B1) => Some "D"%char
+  | (B1, B1, B1, B0) => Some "E"%char
+  | (B1, B1, B1, B1) => Some "F"%char
   | _ => None
-  end
+  end.
 
 Fixpoint hexstring_of_bits bs := match bs with
   | b1 :: b2 :: b3 :: b4 :: bs =>
      let n := char_of_nibble (b1, b2, b3, b4) in
      let s := hexstring_of_bits bs in
      match (n, s) with
-     | (Some n, Some s) => Some (n :: s)
+     | (Some n, Some s) => Some (String n s)
      | _ => None
      end
+  | [] => Some EmptyString
   | _ => None
-  end
-declare {isabelle} termination_argument hexstring_of_bits = automatic
+  end%string.
+
+Fixpoint binstring_of_bits bs := match bs with
+  | b :: bs => String (bitU_char b) (binstring_of_bits bs)
+  | [] => EmptyString
+  end.
 
 Definition show_bitlist bs :=
   match hexstring_of_bits bs with
-  | Some s => toString (#'0' :: #x' :: s)
-  | None => show bs
-  end
+  | Some s => String "0" (String "x" s)
+  | None => String "0" (String "b" (binstring_of_bits bs))
+  end.
 
 (*** List operations *)
-
+(*
 Definition inline (^^) := append_list
 
 val subrange_list_inc : forall a. list a -> Z -> Z -> list a*)
@@ -953,9 +966,9 @@ Definition extz_bv n (v : a) : option b := of_bits (extz_bits n (bits_of v)).
 (*val exts_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
 Definition exts_bv n (v : a) : option b := of_bits (exts_bits n (bits_of v)).
 
-(*val string_of_bv : forall a. Bitvector a => a -> string
-Definition string_of_bv v := show_bitlist (bits_of v)
-*)
+(*val string_of_bv : forall a. Bitvector a => a -> string *)
+Definition string_of_bv v := show_bitlist (bits_of v).
+
 End Bitvector_defs.
 
 (*** Bytes and addresses *)
-- 
cgit v1.2.3


From e4101799eebec8a13c8bb4588c8f7d9663858902 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Mon, 2 Jul 2018 18:56:14 +0100
Subject: Fix get_recursive_functions to not only pick up non-mutually
 recursive functions

The code to do this is rather ugly. It would be nice to have a generic
callgraph representation we could just query and not use the rewriter
in a weird way to extract this info.
---
 src/c_backend.ml | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/c_backend.ml b/src/c_backend.ml
index d18ca354..8a41df67 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -2684,6 +2684,26 @@ let rec get_recursive_functions (Defs defs) =
   match defs with
   | DEF_internal_mutrec fundefs :: defs ->
      IdSet.union (List.map id_of_fundef fundefs |> IdSet.of_list) (get_recursive_functions (Defs defs))
+
+  | (DEF_fundef fdef as def) :: defs ->
+     let open Rewriter in
+     let ids = ref IdSet.empty in
+     let collect_funcalls e_aux annot =
+       match e_aux with
+       | E_app (id, args) -> (ids := IdSet.add id !ids; E_aux (e_aux, annot))
+       | _ -> E_aux (e_aux, annot)
+     in
+     let map_exp = {
+         id_exp_alg with
+         e_aux = (fun (e_aux, annot) -> collect_funcalls e_aux annot)
+       } in
+     let map_defs = { rewriters_base with rewrite_exp = (fun _ -> fold_exp map_exp) } in
+     let _ = rewrite_def map_defs def in
+     if IdSet.mem (id_of_fundef fdef) !ids then
+       IdSet.add (id_of_fundef fdef) (get_recursive_functions (Defs defs))
+     else
+       get_recursive_functions (Defs defs)
+
   | _ :: defs -> get_recursive_functions (Defs defs)
   | [] -> IdSet.empty
 
-- 
cgit v1.2.3


From 4f986dfa677652e0fa984e356e22c392ea945934 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 3 Jul 2018 12:15:39 +0100
Subject: cheri: update to register file semantics. Most instructions now treat
 c0 as null capability while some still refer to DDC. Special registers moved
 out of general capability register file. All capabilties initialised to null
 except those required for MIPS compatibility.

---
 cheri/cheri_insts.sail          |  53 ++++++++++---------
 cheri/cheri_prelude_common.sail | 114 +++++++++++++++++++++++++---------------
 2 files changed, 101 insertions(+), 66 deletions(-)

diff --git a/cheri/cheri_insts.sail b/cheri/cheri_insts.sail
index 3df442d9..f1038ed6 100644
--- a/cheri/cheri_insts.sail
+++ b/cheri/cheri_insts.sail
@@ -363,14 +363,14 @@ function clause execute (CReadHwr(cd, sel)) =
      raise_c2_exception(CapEx_AccessSystemRegsViolation, sel)
   else {
     capVal : CapStruct = match unsigned(sel) {
-      0 => readCapReg(DDC),
-      1 => capRegToCapStruct(CTLSU),
-      8 => capRegToCapStruct(CTLSP),
-      22 => readCapReg(KR1C),
-      23 => readCapReg(KR2C),
-      29 => readCapReg(KCC),
-      30 => readCapReg(KDC),
-      31 => readCapReg(EPCC),
+      0  => capRegToCapStruct(DDC),
+      1  => capRegToCapStruct(CTLSU),
+      8  => capRegToCapStruct(CTLSP),
+      22 => capRegToCapStruct(KR1C),
+      23 => capRegToCapStruct(KR2C),
+      29 => capRegToCapStruct(KCC),
+      30 => capRegToCapStruct(KDC),
+      31 => capRegToCapStruct(EPCC),
       _  => {assert(false, "should be unreachable code"); undefined}
     };
     writeCapReg(cd, capVal);
@@ -401,14 +401,14 @@ function clause execute (CWriteHwr(cb, sel)) =
   else {
     capVal = readCapReg(cb);
     match unsigned(sel) {
-      0 => writeCapReg(DDC, capVal),
-      1 => CTLSU = capStructToCapReg(capVal),
-      8 => CTLSP = capStructToCapReg(capVal),
-      22 => writeCapReg(KR1C, capVal),
-      23 => writeCapReg(KR2C, capVal),
-      29 => writeCapReg(KCC, capVal),
-      30 => writeCapReg(KDC, capVal),
-      31 => writeCapReg(EPCC, capVal),
+      0  => DDC   = capStructToCapReg(capVal),
+      1  => CTLSU = capStructToCapReg(capVal),
+      8  => CTLSP = capStructToCapReg(capVal),
+      22 => KR1C  = capStructToCapReg(capVal),
+      23 => KR2C  = capStructToCapReg(capVal),
+      29 => KCC   = capStructToCapReg(capVal),
+      30 => KDC   = capStructToCapReg(capVal),
+      31 => EPCC  = capStructToCapReg(capVal),
       _  => assert(false, "should be unreachable code")
     };
   };
@@ -440,7 +440,7 @@ union clause ast = CToPtr : (regno, regno, regno)
 function clause execute(CToPtr(rd, cb, ct)) = 
 {
   checkCP2usable();
-  let ct_val = readCapReg(ct);
+  let ct_val = readCapRegDDC(ct);
   let cb_val = readCapReg(cb);
   if (register_inaccessible(cb)) then
     raise_c2_exception(CapEx_AccessSystemRegsViolation, cb)
@@ -714,7 +714,10 @@ function clause execute (ClearRegs(regset, m)) =
       match regset {
         GPLo  => wGPR(to_bits(5, i)) = zeros(),
         GPHi  => wGPR(to_bits(5, i+16)) = zeros(),
-        CLo   => writeCapReg(to_bits(5, i)) = null_cap,
+        CLo   => if i == 0 then
+                   DDC = capStructToCapReg(null_cap)
+                 else
+                   writeCapReg(to_bits(5, i)) = null_cap,
         CHi   => writeCapReg(to_bits(5, i+16)) = null_cap
       }
 }
@@ -723,7 +726,7 @@ union clause ast = CFromPtr : (regno, regno, regno)
 function clause execute (CFromPtr(cd, cb, rt)) =
 {
   checkCP2usable();
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   rt_val = rGPR(rt);
   if (register_inaccessible(cd)) then
     raise_c2_exception(CapEx_AccessSystemRegsViolation, cd)
@@ -747,7 +750,7 @@ union clause ast = CBuildCap : (regno, regno, regno)
 function clause execute (CBuildCap(cd, cb, ct)) =
 {
   checkCP2usable();
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   ct_val = readCapReg(ct);
   cb_base = getCapBase(cb_val);
   ct_base = getCapBase(ct_val);
@@ -859,7 +862,7 @@ union clause ast = CTestSubset : (regno, regno, regno)
 function clause execute (CTestSubset(rd, cb, ct)) =
 {
   checkCP2usable();
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   ct_val = readCapReg(ct);
   ct_top    = getCapTop(ct_val);
   ct_base   = getCapBase(ct_val);
@@ -1156,7 +1159,7 @@ union clause ast = CLoad : (regno, regno, regno, bits(8), bool, WordType, bool)
 function clause execute (CLoad(rd, cb, rt, offset, signext, width, linked)) =
 {
   checkCP2usable();
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   if (register_inaccessible(cb)) then
     raise_c2_exception(CapEx_AccessSystemRegsViolation, cb)
   else if not (cb_val.tag) then
@@ -1198,7 +1201,7 @@ union clause ast = CStore : (regno, regno, regno, regno, bits(8), WordType, bool
 function clause execute (CStore(rs, cb, rt, rd, offset, width, conditional)) =
 {
   checkCP2usable();
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   if (register_inaccessible(cb)) then
     raise_c2_exception(CapEx_AccessSystemRegsViolation, cb)
   else if not (cb_val.tag) then
@@ -1254,7 +1257,7 @@ function clause execute (CSC(cs, cb, rt, rd, offset, conditional)) =
 {
   checkCP2usable();
   cs_val = readCapReg(cs);
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   if (register_inaccessible(cs)) then
     raise_c2_exception(CapEx_AccessSystemRegsViolation, cs)
   else if (register_inaccessible(cb)) then
@@ -1303,7 +1306,7 @@ union clause ast = CLC : (regno, regno, regno, bits(16), bool)
 function clause execute (CLC(cd, cb, rt, offset, linked)) =  
 {
   checkCP2usable();
-  cb_val = readCapReg(cb);
+  cb_val = readCapRegDDC(cb);
   if (register_inaccessible(cd)) then
     raise_c2_exception(CapEx_AccessSystemRegsViolation, cd)
   else if (register_inaccessible(cb)) then
diff --git a/cheri/cheri_prelude_common.sail b/cheri/cheri_prelude_common.sail
index cc4c657a..d2b69de8 100644
--- a/cheri/cheri_prelude_common.sail
+++ b/cheri/cheri_prelude_common.sail
@@ -45,7 +45,7 @@ register PCC        : CapReg
 register nextPCC    : CapReg
 register delayedPCC : CapReg
 register inCCallDelay : bits(1)
-register C00 : CapReg /* aka default data capability, DDC */
+register DDC : CapReg
 register C01 : CapReg
 register C02 : CapReg
 register C03 : CapReg
@@ -72,22 +72,28 @@ register C23 : CapReg
 register C24 : CapReg /* aka return code capability, RCC */
 register C25 : CapReg
 register C26 : CapReg /* aka invoked data capability, IDC */
-register C27 : CapReg /* aka kernel reserved capability 1, KR1C */
-register C28 : CapReg /* aka kernel reserved capability 2, KR2C */
-register C29 : CapReg /* aka kernel code capability, KCC */
-register C30 : CapReg /* aka kernel data capability, KDC */
-register C31 : CapReg /* aka exception program counter capability, EPCC */
+register C27 : CapReg
+register C28 : CapReg
+register C29 : CapReg
+register C30 : CapReg
+register C31 : CapReg
 
 register CTLSU : CapReg /* User thread local storage capabiltiy */
 register CTLSP : CapReg /* Privileged thread local storage capabiltiy */
+register KR1C  : CapReg /* kernel reserved capability 1 */
+register KR2C  : CapReg /* kernel reserved capability 2 */
+register KCC   : CapReg /* kernel code capability */
+register KDC   : CapReg /* kernel data capability */
+register EPCC  : CapReg /* exception program counter capability */
 
-let DDC  : regno = 0b00000 /* C0  */
-let IDC  : regno = 0b11010 /* C26 */
-let KR1C : regno = 0b11011 /* C27 */
-let KR2C : regno = 0b11100 /* C28 */
-let KCC  : regno = 0b11101 /* C29 */
-let KDC  : regno = 0b11110 /* C30 */
-let EPCC : regno = 0b11111 /* C31 */
+let IDCNO  : regno = 0b11010 /* C26, invoked data capability used be CCall */
+
+/* Special register used to have these numbers -- here for transition purposes */
+let KR1CNO : regno = 0b11011 /* C27 */
+let KR2CNO : regno = 0b11100 /* C28 */
+let KCCNO  : regno = 0b11101 /* C29 */
+let KDCNO  : regno = 0b11110 /* C30 */
+let EPCCNO : regno = 0b11111 /* C31 */
 
 let CapRegs : vector(32, dec, register(CapReg)) =
   [
@@ -122,7 +128,7 @@ let CapRegs : vector(32, dec, register(CapReg)) =
     ref C03,
     ref C02,
     ref C01,
-    ref C00
+    ref DDC
   ]
 
 let max_otype = MAX(24) /*0xffffff*/
@@ -130,15 +136,32 @@ let have_cp2 = true
 
 /*!
 This function reads a given capability register and returns its contents converted to a CapStruct.
+If the argument is zero then the null capability is returned.
 */
 val readCapReg : regno -> CapStruct effect {rreg}
 function readCapReg(n) =
-  let 'i = unsigned(n) in
-  capRegToCapStruct(reg_deref(CapRegs[i]))
+  if (n == 0b00000) then
+    null_cap
+  else
+    let i = unsigned(n) in
+    capRegToCapStruct(reg_deref(CapRegs[i]))
+
+/*!
+This is the same as readCapReg except that when the argument is zero the value of DDC is returned 
+instead of the null capability. This is used for instructions that expect an address, where using
+null would always generate an exception.
+*/
+val readCapRegDDC : regno -> CapStruct effect {rreg}
+function readCapRegDDC(n) =
+  let i = unsigned(n) in
+  capRegToCapStruct(reg_deref(CapRegs[i])) /* NB CapRegs[0] is points to DDC */
 
 function writeCapReg(n, cap) : (regno, CapStruct) -> unit =
-  let 'i = unsigned(n) in
-  (*CapRegs[i]) = capStructToCapReg(cap) 
+  if (n == 0b00000) then
+    ()
+  else
+    let i = unsigned(n) in
+    (*CapRegs[i]) = capStructToCapReg(cap) 
 
 enum CapEx = {
   CapEx_None, 
@@ -214,22 +237,22 @@ function SignalException (ex) =
       let pcc = capRegToCapStruct(PCC) in
       let (success, epcc) = setCapOffset(pcc, pc) in
       if (success) then
-        C31 = capStructToCapReg(epcc)
+        EPCC = capStructToCapReg(epcc)
       else
-        C31 = capStructToCapReg(int_to_cap(to_bits(64, getCapBase(pcc)) + unsigned(pc)));
+        EPCC = capStructToCapReg(int_to_cap(to_bits(64, getCapBase(pcc)) + unsigned(pc)));
     };
 
-    nextPCC    = C29; /* KCC */
-    delayedPCC = C29; /* always write delayedPCC together with nextPCC so 
+    nextPCC    = KCC;
+    delayedPCC = KCC; /* always write delayedPCC together with nextPCC so 
                           that non-capability branches don't override PCC */
-    let base = getCapBase(capRegToCapStruct(C29)) in
+    let base = getCapBase(capRegToCapStruct(KCC)) in
     SignalExceptionMIPS(ex, to_bits(64, base));
   }
 
 function ERETHook() : unit -> unit =
   {
-    nextPCC    = C31;
-    delayedPCC = C31; /* always write delayedPCC together with nextPCC so 
+    nextPCC    = EPCC;
+    delayedPCC = EPCC; /* always write delayedPCC together with nextPCC so 
                           that non-capability branches don't override PCC */
   }
 
@@ -247,7 +270,7 @@ function raise_c2_exception8(capEx, regnum) =
 val raise_c2_exception : forall ('o : Type) . (CapEx, regno) -> 'o effect {escape, rreg, wreg}
 function raise_c2_exception(capEx, regnum) =
   let reg8 = 0b000 @ regnum in
-  if ((capEx == CapEx_AccessSystemRegsViolation) & (regnum == IDC)) then
+  if ((capEx == CapEx_AccessSystemRegsViolation) & (regnum == IDCNO)) then
      raise_c2_exception8(CapEx_AccessCCallIDCViolation, reg8)
   else
      raise_c2_exception8(capEx, reg8)
@@ -266,12 +289,12 @@ The following function should be called before reading or writing any capability
  */
 val register_inaccessible : regno -> bool effect {rreg}
 function register_inaccessible(r) =
-  ((r == IDC) & inCCallDelay) |
-  ((r == KR1C |
-    r == KR2C |
-    r == KDC  |
-    r == KCC  |
-    r == EPCC) & not (pcc_access_system_regs ()))
+  ((r == IDCNO) & inCCallDelay) |
+  ((r == KR1CNO |
+    r == KR2CNO |
+    r == KDCNO  |
+    r == KCCNO  |
+    r == EPCCNO) & not (pcc_access_system_regs ()))
 
 val MEMr_tag = "read_tag_bool"  : bits(64) -> bool effect { rmemt }
 val MEMw_tag = "write_tag_bool" : (bits(64) , bool) -> unit effect { wmvt }
@@ -355,7 +378,7 @@ val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) effect {rreg,
 function addrWrapper(addr, accessType, width) =
   {
     capno = 0b00000;
-    cap = readCapReg(capno);
+    cap = readCapRegDDC(capno);
     if (not (cap.tag)) then
       (raise_c2_exception(CapEx_TagViolation, capno))
     else if (cap.sealed) then
@@ -416,12 +439,21 @@ function checkCP2usable ()  =
 
 function init_cp2_state () = {
   let defaultBits = capStructToCapReg(default_cap);
+  let nullBits = capStructToCapReg(null_cap);
   PCC = defaultBits;
   nextPCC = defaultBits;
   delayedPCC = defaultBits;
-  foreach(i from 0 to 31) {
+  DDC  = defaultBits;
+  KCC  = defaultBits;
+  EPCC = defaultBits;
+  KDC  = nullBits;
+  KR1C = nullBits;
+  KR2C = nullBits;
+  CTLSP = nullBits;
+  CTLSU = nullBits;
+  foreach(i from 1 to 31) {
     let idx = to_bits(5, i) in
-    writeCapReg(idx, default_cap);
+    writeCapReg(idx, null_cap)
   }
 }
 
@@ -457,15 +489,15 @@ function dump_cp2_state () = {
   foreach(i from 0 to 31) {
     print(concat_str("DEBUG CAP REG ", concat_str(string_of_int(i), capToString(readCapReg(to_bits(5, i))))))
   };
-  print(concat_str("DEBUG CAP HWREG 00", capToString(capRegToCapStruct(C00))));
+  print(concat_str("DEBUG CAP HWREG 00", capToString(capRegToCapStruct(DDC))));
   print(concat_str("DEBUG CAP HWREG 01", capToString(capRegToCapStruct(CTLSU))));
   print(concat_str("DEBUG CAP HWREG 08", capToString(capRegToCapStruct(CTLSP))));
   /* TODO: these two should not be mirrored to match the FPGA */
-  print(concat_str("DEBUG CAP HWREG 22", capToString(capRegToCapStruct(C27))));
-  print(concat_str("DEBUG CAP HWREG 23", capToString(capRegToCapStruct(C28))));
+  print(concat_str("DEBUG CAP HWREG 22", capToString(capRegToCapStruct(KR1C))));
+  print(concat_str("DEBUG CAP HWREG 23", capToString(capRegToCapStruct(KR2C))));
   /* KCC, KDC, EPCC */
-  print(concat_str("DEBUG CAP HWREG 29", capToString(capRegToCapStruct(C29))));
-  print(concat_str("DEBUG CAP HWREG 30", capToString(capRegToCapStruct(C30))));
-  print(concat_str("DEBUG CAP HWREG 31", capToString(capRegToCapStruct(C31))));
+  print(concat_str("DEBUG CAP HWREG 29", capToString(capRegToCapStruct(KCC))));
+  print(concat_str("DEBUG CAP HWREG 30", capToString(capRegToCapStruct(KDC))));
+  print(concat_str("DEBUG CAP HWREG 31", capToString(capRegToCapStruct(EPCC))));
 
 }
-- 
cgit v1.2.3


From 9502f9ffabc5ec8f423974bd89da3d9810e4df80 Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Tue, 3 Jul 2018 14:00:22 +0100
Subject: Main: fix SEE handling

If a SEE exception is not caught within the decoder, it is
an error in the Sail implementation or in the instruction set spec.

This change ensures that we promptly detect and unambiguously report
such errors.
---
 aarch64/elfmain.sail | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index bccbbda5..44b6c14a 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -107,7 +107,12 @@ function Step_CPU() = {
       } catch {
           // note: if supporting AArch32 as well, call _UndefinedFault() instead
           Error_Undefined()         => try { AArch64_UndefinedFault() } catch { _ => print("Exception during Undefined recovery\n") },
-          Error_See(_)              => try { AArch64_UndefinedFault() } catch { _ => print("Exception during SEE recovery\n") },
+          Error_See(_) => {
+            print(concat_str("BROKEN: SEE support ",
+                  concat_str(HexStr(UInt(__currentInstr)),
+                  "\n")));
+            exit()
+          },
           Error_ReservedEncoding(_) => try { AArch64_UndefinedFault() } catch { _ => print("Exception during ReservedEncoding recovery\n") },
           Error_ExceptionTaken() => {
             print(concat_str("ExceptionTaken during Decode/Execute from PC=",
-- 
cgit v1.2.3


From a3a05ed727e2e7d8f0f3e54a444c556dbe2dfd83 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 3 Jul 2018 14:13:19 +0100
Subject: Fill in a few Coq functions for CHERI from the MIPS prelude

---
 mips/mips_extras.v | 8 ++++++++
 mips/prelude.sail  | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/mips/mips_extras.v b/mips/mips_extras.v
index 94e4779c..49899107 100644
--- a/mips/mips_extras.v
+++ b/mips/mips_extras.v
@@ -152,3 +152,11 @@ Qed.
 
 Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
 Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r.
+
+
+Definition print_endline (_:string) : unit := tt.
+Definition prerr_endline (_:string) : unit := tt.
+Definition prerr_string (_:string) : unit := tt.
+Definition putchar {T} (_:T) : unit := tt.
+Require DecimalString.
+Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z).
diff --git a/mips/prelude.sail b/mips/prelude.sail
index b3349799..697ef74a 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -55,7 +55,7 @@ val "prerr_string" : string -> unit
 
 val putchar = {c:"sail_putchar", _:"putchar"} : forall ('a : Type). 'a -> unit
 
-val concat_str = {lem: "stringAppend", _: "concat_str"} : (string, string) -> string
+val concat_str = {lem: "stringAppend", coq: "String.append", _: "concat_str"} : (string, string) -> string
 
 val string_of_int = "string_of_int" : int -> string
 /* Unused?
-- 
cgit v1.2.3


From c369d0897230bec405fc6cce7144d4f9f2956ed6 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 3 Jul 2018 14:19:48 +0100
Subject: Fix letbind_effects on LEXP_deref with an effectful subexpression

---
 src/rewrites.ml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rewrites.ml b/src/rewrites.ml
index 214ca571..c2bf0835 100644
--- a/src/rewrites.ml
+++ b/src/rewrites.ml
@@ -2606,7 +2606,7 @@ let rewrite_defs_letbind_effects =
     match lexp_aux with
     | LEXP_id _ -> k lexp
     | LEXP_deref exp ->
-       n_exp exp (fun exp ->
+       n_exp_name exp (fun exp ->
        k (fix_eff_lexp (LEXP_aux (LEXP_deref exp, annot))))
     | LEXP_memory (id,es) ->
        n_exp_nameL es (fun es -> 
-- 
cgit v1.2.3


From 226fd119ca929f24b568b9692403ca477c7511c4 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 3 Jul 2018 14:24:31 +0100
Subject: mips: just whitespace.

---
 mips/mips_insts.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail
index c678000e..2f6b0153 100644
--- a/mips/mips_insts.sail
+++ b/mips/mips_insts.sail
@@ -1465,7 +1465,7 @@ function clause execute (MFC0(rt, rd, sel, double)) = {
                                         @ 0b000    /* DS dcache sets */
                                         @ 0b000    /* DL dcache lines */
                                         @ 0b000    /* DA dcache assoc. */
-			       	 @ bool_to_bits(have_cp2) /* C2 CP2 presence */
+                                        @ bool_to_bits(have_cp2) /* C2 CP2 presence */
                                         @ 0b0      /* MD MDMX implemented */
                                         @ 0b0      /* PC performance counters */
                                         @ 0b0      /* WR watch registers */
-- 
cgit v1.2.3


From c1c51761101cd9313df3b111accb6237e558f0d2 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 3 Jul 2018 16:24:47 +0100
Subject: cheri: refine lwl/lwr cap length checks to be exact. They were
 previously a bit loose, but conservative.

---
 cheri/cheri_prelude_common.sail | 63 ++++++++++++++++++++++++++++++-----------
 mips/mips_insts.sail            | 24 ++++++----------
 mips/mips_prelude.sail          |  1 +
 mips/mips_wrappers.sail         |  4 +++
 4 files changed, 60 insertions(+), 32 deletions(-)

diff --git a/cheri/cheri_prelude_common.sail b/cheri/cheri_prelude_common.sail
index d2b69de8..764a4ff1 100644
--- a/cheri/cheri_prelude_common.sail
+++ b/cheri/cheri_prelude_common.sail
@@ -374,29 +374,60 @@ function MEMw_conditional_wrapper(addr, size, data) =
     success;
   }
 
-val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) effect {rreg, wreg, escape}
-function addrWrapper(addr, accessType, width) =
+val checkDDCPerms : (CapStruct, MemAccessType) -> unit effect {escape, rreg, wreg}
+function checkDDCPerms(ddc : CapStruct, accessType: MemAccessType) = 
   {
-    capno = 0b00000;
-    cap = readCapRegDDC(capno);
-    if (not (cap.tag)) then
-      (raise_c2_exception(CapEx_TagViolation, capno))
-    else if (cap.sealed) then
-        (raise_c2_exception(CapEx_SealViolation, capno));
+    if (not (ddc.tag)) then
+      raise_c2_exception(CapEx_TagViolation, 0b00000)
+    else if (ddc.sealed) then
+      raise_c2_exception(CapEx_SealViolation, 0b00000);
     match accessType {
-      Instruction  => if (~(cap.permit_execute)) then (raise_c2_exception(CapEx_PermitExecuteViolation, capno)),
-      LoadData     => if (~(cap.permit_load)) then (raise_c2_exception(CapEx_PermitLoadViolation, capno)),
-      StoreData    => if (~(cap.permit_store)) then (raise_c2_exception(CapEx_PermitStoreViolation, capno))
+      Instruction  => assert(false), /* Only data accesses use DDC */
+      LoadData     => if (~(ddc.permit_load)) then (raise_c2_exception(CapEx_PermitLoadViolation, 0b00000)),
+      StoreData    => if (~(ddc.permit_store)) then (raise_c2_exception(CapEx_PermitStoreViolation, 0b00000))
     };
-    cursor = getCapCursor(cap);
+  }
+
+val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) effect {rreg, wreg, escape}
+function addrWrapper(addr, accessType, width) =
+  {
+    ddc    = capRegToCapStruct(DDC);
+    checkDDCPerms(ddc, accessType);
+    cursor = getCapCursor(ddc);
     vAddr  = (cursor + unsigned(addr)) % pow2(64);
     size   = wordWidthBytes(width);
-    base   = getCapBase(cap);
-    top    = getCapTop(cap);
+    base   = getCapBase(ddc);
+    top    = getCapTop(ddc);
     if ((vAddr + size) > top) then
-      (raise_c2_exception(CapEx_LengthViolation, capno))
+      (raise_c2_exception(CapEx_LengthViolation, 0b00000))
     else if (vAddr < base) then
-      (raise_c2_exception(CapEx_LengthViolation, capno))
+      (raise_c2_exception(CapEx_LengthViolation, 0b00000))
+    else
+      to_bits(64, vAddr);
+  }
+
+val addrWrapperUnaligned : (bits(64), MemAccessType, WordTypeUnaligned) -> bits(64) effect {rreg, wreg, escape}
+function addrWrapperUnaligned(addr, accessType, width) =
+  {
+    ddc    = capRegToCapStruct(DDC);
+    checkDDCPerms(ddc, accessType);
+    cursor = getCapCursor(ddc);
+    vAddr  = (cursor + unsigned(addr)) % pow2(64);
+    woffset = vAddr % 4;
+    doffset = vAddr % 8;
+    /* Compute the address and size of the bytes touched -- this depends on alignment. */
+    let (waddr, size) : (int, int) = match width {
+      WL => (vAddr, 4 - woffset),
+      WR => (vAddr - woffset, woffset + 1),
+      DL => (vAddr, 8 - doffset),
+      DR => (vAddr - doffset, doffset + 1)
+    };
+    base   = getCapBase(ddc);
+    top    = getCapTop(ddc);
+    if ((waddr + size) > top) then
+      (raise_c2_exception(CapEx_LengthViolation, 0b00000))
+    else if (waddr < base) then
+      (raise_c2_exception(CapEx_LengthViolation, 0b00000))
     else
       to_bits(64, vAddr);
   }
diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail
index 2f6b0153..84136e66 100644
--- a/mips/mips_insts.sail
+++ b/mips/mips_insts.sail
@@ -1210,8 +1210,7 @@ function clause decode(0b100010 @ base : regno @ rt : regno @ offset : imm16) =
       Some(LWL(base, rt, offset))
 function clause execute(LWL(base, rt, offset)) =
       {
-        /* XXX length check not quite right, but conservative */
-        vAddr = addrWrapper(sign_extend(offset) + rGPR(base), LoadData, W);
+        vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, WL);
         let pAddr = (TLBTranslate(vAddr, LoadData)) in
           {
             mem_val = MEMr_wrapper (pAddr[63..2] @ 0b00, 4); /* read word of interest */
@@ -1231,8 +1230,7 @@ function clause decode(0b100110 @ base : regno @ rt : regno @ offset : imm16) =
       Some(LWR(base, rt, offset))
 function clause execute(LWR(base, rt, offset)) =
       {
-        /* XXX length check not quite right, but conservative */
-        vAddr = addrWrapper(sign_extend(offset) + rGPR(base), LoadData, W);
+        vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, WR);
         let pAddr = (TLBTranslate(vAddr, LoadData)) in
           {
             mem_val = MEMr_wrapper(pAddr[63..2] @ 0b00, 4); /* read word of interest */
@@ -1254,8 +1252,7 @@ function clause decode(0b101010 @ base : regno @ rt : regno @ offset : imm16) =
       Some(SWL(base, rt, offset))
 function clause execute(SWL(base, rt, offset)) =
       {
-        /* XXX length check not quite right, but conservative */
-        vAddr = addrWrapper(sign_extend(offset) + rGPR(base), StoreData, W);
+        vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, WL);
         let pAddr = TLBTranslate(vAddr, StoreData) in
           {
             reg_val = rGPR(rt);
@@ -1274,8 +1271,7 @@ function clause decode(0b101110 @ base : regno @ rt : regno @ offset : imm16) =
       Some(SWR(base, rt, offset))
 function clause execute(SWR(base, rt, offset)) =
       {
-        /* XXX length check not quite right, but conservative */
-        vAddr = addrWrapper(sign_extend(offset) + rGPR(base), StoreData, W);
+        vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, WR);
         let pAddr = TLBTranslate(vAddr, StoreData) in
           {
             wordAddr = pAddr[63..2] @ 0b00;
@@ -1296,8 +1292,7 @@ function clause decode(0b011010 @ base : regno @ rt : regno @ offset : imm16) =
   Some(LDL(base, rt, offset))
 function clause execute(LDL(base, rt, offset)) =
   {
-    /* XXX length check not quite right, but conservative */
-    vAddr = addrWrapper(sign_extend(offset) + rGPR(base), LoadData, D);
+    vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, DL);
     let pAddr = TLBTranslate(vAddr, LoadData) in
       {
         mem_val = MEMr_wrapper(pAddr[63..3] @ 0b000, 8); /* read double of interest */
@@ -1322,8 +1317,7 @@ function clause decode(0b011011 @ base : regno @ rt : regno @ offset : imm16) =
   Some(LDR(base, rt, offset))
 function clause execute(LDR(base, rt, offset)) =
   {
-    /* XXX length check not quite right, but conservative */
-    vAddr = addrWrapper(sign_extend(offset) + rGPR(base), LoadData, D);
+    vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, DR);
     let pAddr = TLBTranslate(vAddr, LoadData) in
       {
         mem_val = MEMr_wrapper(pAddr[63..3] @ 0b000, 8); /* read double of interest */
@@ -1348,8 +1342,7 @@ function clause decode(0b101100 @ base : regno @ rt : regno @ offset : imm16) =
       Some(SDL(base, rt, offset))
 function clause execute(SDL(base, rt, offset)) =
       {
-        /* XXX length check not quite right, but conservative */
-        vAddr = addrWrapper(sign_extend(offset) + rGPR(base), StoreData, D);
+        vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, DL);
         let pAddr = TLBTranslate(vAddr, StoreData) in
           {
             reg_val = rGPR(rt);
@@ -1374,8 +1367,7 @@ function clause decode(0b101101 @ base : regno @ rt : regno @ offset : imm16) =
       Some(SDR(base, rt, offset))
 function clause execute(SDR(base, rt, offset)) =
   {
-        /* XXX length check not quite right, but conservative */
-        vAddr = addrWrapper(sign_extend(offset) + rGPR(base), StoreData, D);
+        vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, DR);
         let pAddr = TLBTranslate(vAddr, StoreData) in
           {
             reg_val = rGPR(rt);
diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail
index fbbe74ee..76a05791 100644
--- a/mips/mips_prelude.sail
+++ b/mips/mips_prelude.sail
@@ -565,6 +565,7 @@ function compare (cmp, valA, valB) =
     LTU  => valA <_u  valB
   }
 enum WordType = { B, H, W, D}
+enum WordTypeUnaligned = { WL, WR, DL, DR }
 
 val wordWidthBytes : WordType -> range(1, 8)
 function wordWidthBytes(w) =
diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail
index 0cc098a5..43e759b9 100644
--- a/mips/mips_wrappers.sail
+++ b/mips/mips_wrappers.sail
@@ -60,6 +60,10 @@ val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64)
 function addrWrapper(addr, accessType, width) =
     addr
 
+val addrWrapperUnaligned : (bits(64), MemAccessType, WordTypeUnaligned) -> bits(64)
+function addrWrapperUnaligned(addr, accessType, width) =
+    addr
+
 $ifdef _MIPS_TLB_STUB
 val TranslatePC : bits(64) -> bits(64) effect {rreg, wreg, escape}
 $else
-- 
cgit v1.2.3


From 53959905b8e4bfd4877c1e052195391d89bdb0d6 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Tue, 3 Jul 2018 19:06:03 +0100
Subject: Fix a bug in foreach loops

We should test before the first iteration in case 'to' starts out as
less than 'from'.
---
 src/c_backend.ml           | 15 +++++++--------
 test/c/foreach_none.expect |  1 +
 test/c/foreach_none.sail   | 11 +++++++++++
 3 files changed, 19 insertions(+), 8 deletions(-)
 create mode 100644 test/c/foreach_none.expect
 create mode 100644 test/c/foreach_none.sail

diff --git a/src/c_backend.ml b/src/c_backend.ml
index 8a41df67..4335e98e 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -1215,6 +1215,7 @@ let rec compile_aexp ctx (AE_aux (aexp_aux, env, l)) =
      in
 
      let loop_start_label = label "for_start_" in
+     let loop_end_label = label "for_end_" in
      let body_setup, _, body_call, body_cleanup = compile_aexp ctx body in
      let body_gs = gensym () in
 
@@ -1223,17 +1224,15 @@ let rec compile_aexp ctx (AE_aux (aexp_aux, env, l)) =
      @ variable_init step_gs step_setup step_ctyp step_call step_cleanup
      @ [iblock ([idecl CT_int64 loop_var;
                  icopy (CL_id loop_var) (F_id from_gs, CT_int64);
-                 ilabel loop_start_label;
                  idecl CT_unit body_gs;
-                 iblock (body_setup
+                 iblock ([ilabel loop_start_label]
+                         @ [ijump (F_op (F_id loop_var, (if is_inc then ">" else "<"), F_id to_gs), CT_bool) loop_end_label]
+                         @ body_setup
                          @ [body_call (CL_id body_gs)]
                          @ body_cleanup
-                         @ if is_inc then
-                             [icopy (CL_id loop_var) (F_op (F_id loop_var, "+", F_id step_gs), CT_int64);
-                              ijump (F_op (F_id loop_var, "<=", F_id to_gs), CT_bool) loop_start_label]
-                           else
-                             [icopy (CL_id loop_var) (F_op (F_id loop_var, "-", F_id step_gs), CT_int64);
-                              ijump (F_op (F_id loop_var, ">=", F_id to_gs), CT_bool) loop_start_label])])],
+                         @ [icopy (CL_id loop_var) (F_op (F_id loop_var, (if is_inc then "+" else "-"), F_id step_gs), CT_int64)]
+                         @ [igoto loop_start_label]);
+                 ilabel loop_end_label])],
      CT_unit,
      (fun clexp -> icopy clexp unit_fragment),
      []
diff --git a/test/c/foreach_none.expect b/test/c/foreach_none.expect
new file mode 100644
index 00000000..9766475a
--- /dev/null
+++ b/test/c/foreach_none.expect
@@ -0,0 +1 @@
+ok
diff --git a/test/c/foreach_none.sail b/test/c/foreach_none.sail
new file mode 100644
index 00000000..bc960b85
--- /dev/null
+++ b/test/c/foreach_none.sail
@@ -0,0 +1,11 @@
+
+val "print" : string -> unit
+
+val main : unit -> unit
+
+function main() = {
+  foreach (i from 0 to -1 by 1 in inc) {
+    print("unreachable\n");
+  };
+  print("ok\n")
+}
\ No newline at end of file
-- 
cgit v1.2.3


From edc516ff87fa45fd812dd5d7025d5d94c44a80ee Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Tue, 3 Jul 2018 14:47:59 -0700
Subject: Allow the riscv htif_tohost mmio port to be readable, and ack writes
 to that port.

---
 riscv/platform_impl.ml    |  2 +-
 riscv/riscv_platform.sail | 53 ++++++++++++++++++++++++++++++++++-------------
 riscv/riscv_step.sail     |  2 ++
 3 files changed, 42 insertions(+), 15 deletions(-)

diff --git a/riscv/platform_impl.ml b/riscv/platform_impl.ml
index aab272f8..5c238a1e 100644
--- a/riscv/platform_impl.ml
+++ b/riscv/platform_impl.ml
@@ -107,7 +107,7 @@ let cpu_hz = 1000000000;;
 let insns_per_tick = 100;;
 
 let mems = [ { addr = dram_base;
-	       size = dram_size } ];;
+               size = dram_size } ];;
 let dts = spike_dts "rv64imac" cpu_hz insns_per_tick mems;;
 
 let bytes_to_string bytes =
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail
index bf0e5020..e7ca9418 100644
--- a/riscv/riscv_platform.sail
+++ b/riscv/riscv_platform.sail
@@ -57,9 +57,8 @@ function within_clint(addr : xlenbits, width : atom('n)) -> forall 'n. bool =
 function within_htif_writable(addr : xlenbits, width : atom('n)) -> forall 'n. bool =
     plat_htif_tohost() == addr
 
-/* TODO */
 function within_htif_readable(addr : xlenbits, width : atom('n)) -> forall 'n. bool =
-    false
+    plat_htif_tohost() == addr
 
 /* CLINT (Core Local Interruptor), based on Spike. */
 
@@ -158,22 +157,37 @@ bitfield htif_cmd : bits(64) = {
   payload : 47 .. 0
 }
 
-register htif_done : bool
+register htif_tohost : xlenbits
+register htif_done   : bool
 register htif_exit_code : xlenbits
 
-val htif_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))
-function htif_load(addr, width) = MemValue(EXTZ(0b0))
 
-/* FIXME: The wreg effect is an artifact of using 'register' to implement device state. */
+/* since the htif tohost port is only available at a single address,
+ * we'll assume here that physical memory model has correctly
+ * dispatched the address.
+ */
+
+val htif_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg}
+function htif_load(addr, width) = {
+  print("htif[" ^ BitStr(addr) ^ "] -> " ^ BitStr(htif_tohost));
+  /* FIXME: For now, only allow the expected access widths. */
+  if width == 8
+  then MemValue(zero_extend(htif_tohost, 64))  /* FIXME: Redundant zero_extend currently required by Lem backend */
+  else MemException(E_Load_Access_Fault)
+}
+
+/* The wreg effect is an artifact of using 'register' to implement device state. */
 val htif_store: forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wreg}
 function htif_store(addr, width, data) = {
-  // since htif is only available at a single address, we'll assume here that physical memory
-  // model has correctly dispatched the address.
+  print("htif[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
+  /* Store the written value so that we can ack it later. */
   let cbits : xlenbits = EXTZ(data);
+  htif_tohost = cbits;
+  /* Process the cmd immediately; this is needed for terminal output. */
   let cmd = Mk_htif_cmd(cbits);
   match cmd.device() {
     0x00 => { /* syscall-proxy */
-      print("htif-syscall-proxy[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
+      print("htif-syscall-proxy cmd: " ^ BitStr(cmd.payload()));
       if cmd.payload()[0] == 0b1
       then {
            htif_done = true;
@@ -182,18 +196,24 @@ function htif_store(addr, width, data) = {
       else ()
     },
     0x01 => { /* terminal */
-      print("htif-term[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
+      print("htif-term cmd: " ^ BitStr(cmd.payload()));
       match cmd.cmd() {
         0x00 => /* TODO: terminal input handling */ (),
         0x01 => plat_term_write(cmd.payload()[7..0]),
         c    => print("Unknown term cmd: " ^ BitStr(c))
       }
     },
-    d => print("htif-????[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data))
+    d => print("htif-???? cmd: " ^ BitStr(data))
   };
   MemValue(())
 }
 
+val htif_tick : unit -> unit effect {rreg, wreg}
+function htif_tick() = {
+  print("htif::tick " ^ BitStr(htif_tohost));
+  htif_tohost = EXTZ(0b0)  /* htif ack */
+}
+
 /* Top-level MMIO dispatch */
 
 function within_mmio_readable(addr : xlenbits, width : atom('n)) -> forall 'n. bool =
@@ -216,9 +236,14 @@ function mmio_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> fo
   then htif_store(addr, width, data)
   else MemException(E_SAMO_Access_Fault)
 
-/* Platform initialization */
+/* Platform initialization and ticking. */
 
 function init_platform() -> unit = {
-  htif_done = false;
-  htif_exit_code = EXTZ(0b0);
+  htif_tohost = EXTZ(0b0);
+  htif_done   = false;
+  htif_exit_code = EXTZ(0b0)
+}
+
+function tick_platform() -> unit = {
+  htif_tick()
 }
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index 2ac80cc6..af41c098 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -114,6 +114,8 @@ function loop () = {
     i = i + 1;
     if i == insns_per_tick then {
       tick_clock();
+      /* for now, we drive the platform i/o at every clock tick. */
+      tick_platform();
       i = 0;
     }
   }
-- 
cgit v1.2.3


From c093e0d61eda7b076492e565995649ad0c04919c Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Tue, 3 Jul 2018 15:08:50 -0700
Subject: Add htif tohost to the riscv tracecmp tool.

---
 riscv/tracecmp.ml | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/riscv/tracecmp.ml b/riscv/tracecmp.ml
index c4f718a2..7f70478c 100644
--- a/riscv/tracecmp.ml
+++ b/riscv/tracecmp.ml
@@ -27,6 +27,10 @@ type tick = {
   time : int64
 }
 
+type htif = {
+  tohost : int64
+}
+
 type line =
   | L_none
   | L_inst of inst
@@ -34,6 +38,7 @@ type line =
   | L_csr_read of csr_read
   | L_csr_write of csr_write
   | L_tick of tick
+  | L_htif of htif
 
 let inst_count = ref 0
 
@@ -123,6 +128,20 @@ let parse_tick l =
 let sprint_tick t =
   Printf.sprintf "clint::tick mtime <- 0x%Lx" t.time
 
+(* htif tick
+   htif::tick 0x1
+ *)
+
+let parse_htif l =
+  try Scanf.sscanf l " htif::tick 0x%Lx"
+                   (fun tohost -> L_htif { tohost })
+  with
+    | Scanf.Scan_failure _ -> L_none
+    | End_of_file -> L_none
+
+let sprint_htif t =
+  Printf.sprintf "htif::tick 0x%Lx" t.tohost
+
 (* scanners *)
 
 let popt p l = function
@@ -131,7 +150,7 @@ let popt p l = function
 
 let parse_line l =
   parse_csr_read l |> popt parse_csr_write l
-  |> popt parse_reg_write l |> popt parse_tick l
+  |> popt parse_reg_write l |> popt parse_tick l |> popt parse_htif l
 
 let parse_sail_line l =
   parse_line l |> popt parse_sail_inst l
@@ -147,6 +166,7 @@ let sprint_line = function
   | L_csr_read  r -> Printf.sprintf "<%d> %s" !inst_count (sprint_csr_read r)
   | L_csr_write r -> Printf.sprintf "<%d> %s" !inst_count (sprint_csr_write r)
   | L_tick t      -> Printf.sprintf "<%d> %s" !inst_count (sprint_tick t)
+  | L_htif t      -> Printf.sprintf "<%d> %s" !inst_count (sprint_htif t)
 
 (* file processing *)
 
-- 
cgit v1.2.3


From 0e9828b2aea47e54b4f692da5e5e09036e58cc91 Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Tue, 3 Jul 2018 15:13:29 +0100
Subject: AArch64 Prelude: Move cycle count primop to prelude

---
 aarch64/elfmain.sail | 2 --
 aarch64/prelude.sail | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index 44b6c14a..24579b79 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -13,8 +13,6 @@ let CNT_IRQ  = [0x0000_000d,       0x0000_000a,        0x0000_03ff,        0x000
 // SGI Interrupts are 0-15, PPI interrupts are 16-31, so SPI interrupts have an offset of 32.
 let SPI_OFFSET = 32
 
-val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem}
-
 // Advance CPU by one cycle
 val Step_CPU : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem}
 
diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail
index 73a084c4..6ce47ae3 100755
--- a/aarch64/prelude.sail
+++ b/aarch64/prelude.sail
@@ -358,3 +358,5 @@ val __Sleeping = {ocaml: "sleeping", lem: "sleeping", smt: "sleeping", interpret
 
 val __GetVerbosity = {c: "sail_get_verbosity"}: unit -> bits(64) effect {rreg, undef}
 
+val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem}
+
-- 
cgit v1.2.3


From eb306a0d3e3abc96d5227b9f240666c5bff6869f Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Wed, 4 Jul 2018 17:10:12 +0100
Subject: mips: move rmem integration instructions into separate file (disabled
 for now) to avoid coverage noise.

---
 mips/mips_insts.sail | 14 +-------------
 mips/mips_rmem.sail  | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 13 deletions(-)
 create mode 100644 mips/mips_rmem.sail

diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail
index 84136e66..3e3f4c39 100644
--- a/mips/mips_insts.sail
+++ b/mips/mips_insts.sail
@@ -1005,19 +1005,7 @@ function clause execute (BCMPZ(rs, imm, cmp, link, likely)) =
 /* SYSCALL/BREAK/WAIT/Trap                                                            */
 /**************************************************************************************/
 
-/* Co-opt syscall 0xfffff for use as thread start in pccmem  */
-union clause ast = SYSCALL_THREAD_START : unit
-function clause decode (0b000000 @ 0xfffff @ 0b001100) =
-  Some(SYSCALL_THREAD_START())
-function clause execute (SYSCALL_THREAD_START()) = ()
-
-
-/* fake stop fetching instruction for ppcmem, execute doesn't do anything,
-   decode never produces it */
-
-union clause ast = ImplementationDefinedStopFetching : unit
-function clause execute (ImplementationDefinedStopFetching()) = ()
-
+/* $include mips_rmem.sail */
 
 union clause ast = SYSCALL : unit
 function clause decode (0b000000 @ code : bits(20) @ 0b001100) =
diff --git a/mips/mips_rmem.sail b/mips/mips_rmem.sail
new file mode 100644
index 00000000..1bc47337
--- /dev/null
+++ b/mips/mips_rmem.sail
@@ -0,0 +1,15 @@
+/* These instructions are used for RMEM integration only */
+
+/* Co-opt syscall 0xfffff for use as thread start in pccmem  */
+union clause ast = SYSCALL_THREAD_START : unit
+function clause decode (0b000000 @ 0xfffff @ 0b001100) =
+  Some(SYSCALL_THREAD_START())
+function clause execute (SYSCALL_THREAD_START()) = ()
+
+
+/* fake stop fetching instruction for ppcmem, execute doesn't do anything,
+   decode never produces it */
+
+union clause ast = ImplementationDefinedStopFetching : unit
+function clause execute (ImplementationDefinedStopFetching()) = ()
+
-- 
cgit v1.2.3


From c080665a6fbd8c88b66440a7bddc31a9634741cf Mon Sep 17 00:00:00 2001
From: Jon French
Date: Thu, 5 Jul 2018 13:09:41 +0100
Subject: restore missing RISC-V fence types in sail2; ignore io bits in fences
 more cleanly

---
 lib/regfp.sail                       |  4 +++
 riscv/riscv.sail                     | 55 +++++++++++++++---------------------
 riscv/riscv_extras.lem               |  4 +++
 riscv/riscv_extras_sequential.lem    |  4 +++
 riscv/riscv_mem.sail                 |  4 +++
 riscv/riscv_types.sail               |  2 +-
 src/lem_interp/sail2_instr_kinds.lem | 16 +++++++++--
 7 files changed, 54 insertions(+), 35 deletions(-)

diff --git a/lib/regfp.sail b/lib/regfp.sail
index b8cffb98..fcf10850 100644
--- a/lib/regfp.sail
+++ b/lib/regfp.sail
@@ -75,6 +75,10 @@ enum barrier_kind = {
   Barrier_RISCV_r_r,
   Barrier_RISCV_rw_w,
   Barrier_RISCV_w_w,
+  Barrier_RISCV_w_rw,
+  Barrier_RISCV_rw_r,
+  Barrier_RISCV_r_w,
+  Barrier_RISCV_w_r,
   Barrier_RISCV_i,
   Barrier_x86_MFENCE
 }
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 87f1b7ca..b50c9225 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -707,19 +707,17 @@ mapping clause encdec = FENCE(pred, succ) <-> 0b0000 @ pred @ succ @ 0b00000 @ 0
 
 function clause execute (FENCE(pred, succ)) = {
   match (pred, succ) {
-    (0b0011, 0b0011) => MEM_fence_rw_rw(),
-    (0b0010, 0b0011) => MEM_fence_r_rw(),
-    (0b0010, 0b0010) => MEM_fence_r_r(),
-    (0b0011, 0b0001) => MEM_fence_rw_w(),
-    (0b0001, 0b0001) => MEM_fence_w_w(),
-
-    (0b1111, 0b1111) => MEM_fence_rw_rw(),
-    (0b1110, 0b1111) => MEM_fence_r_rw(),
-    (0b1110, 0b1110) => MEM_fence_r_r(),
-    (0b1111, 0b1101) => MEM_fence_rw_w(),
-    (0b1101, 0b1101) => MEM_fence_w_w(),
-
-    (0b0000, 0b0000) => (),
+    (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => MEM_fence_rw_rw(),
+    (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => MEM_fence_r_rw(),
+    (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => MEM_fence_r_r(),
+    (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => MEM_fence_rw_w(),
+    (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => MEM_fence_w_w(),
+    (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => MEM_fence_w_rw(),
+    (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => MEM_fence_rw_r(),
+    (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => MEM_fence_r_w(),
+    (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => MEM_fence_w_r(),
+
+    (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (),
 
     _ => { print("FIXME: unsupported fence");
            () }
@@ -1936,25 +1934,18 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
       FENCE(pred, succ) => {
              ik =
                match (pred, succ) {
-                 (0b0011, 0b0011) => IK_barrier (Barrier_RISCV_rw_rw),
-                 (0b0010, 0b0011) => IK_barrier (Barrier_RISCV_r_rw),
-                 (0b0010, 0b0010) => IK_barrier (Barrier_RISCV_r_r),
-                 (0b0011, 0b0001) => IK_barrier (Barrier_RISCV_rw_w),
-                 (0b0001, 0b0001) => IK_barrier (Barrier_RISCV_w_w),
-
-                 (0b1111, 0b1111) => IK_barrier (Barrier_RISCV_rw_rw),
-                 (0b1110, 0b1111) => IK_barrier (Barrier_RISCV_r_rw),
-                 (0b1110, 0b1110) => IK_barrier (Barrier_RISCV_r_r),
-                 (0b1111, 0b1101) => IK_barrier (Barrier_RISCV_rw_w),
-                 (0b1101, 0b1101) => IK_barrier (Barrier_RISCV_w_w),
-
-                 // (0b0001, 0b0011) => IK_barrier (Barrier_RISCV_w_rw),
-                 // (0b0011, 0b0010) => IK_barrier (Barrier_RISCV_rw_r),
-                 // (0b0010, 0b0001) => IK_barrier (Barrier_RISCV_r_w),
-                 // (0b0001, 0b0010) => IK_barrier (Barrier_RISCV_w_r),
-
-
-                 (0b0000, 0b0000) => IK_simple (),
+                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw),
+                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw),
+                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r),
+                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w),
+                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w),
+                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw),
+                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r),
+                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w),
+                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r),
+
+
+                 (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (),
 
                  _ => internal_error("barrier type not implemented in initial_analysis")
   //               case (FM_NORMAL, _, _) -> exit "not implemented"
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 601f5008..b29fe545 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -13,6 +13,10 @@ let MEM_fence_r_rw  () = barrier Barrier_RISCV_r_rw
 let MEM_fence_r_r   () = barrier Barrier_RISCV_r_r
 let MEM_fence_rw_w  () = barrier Barrier_RISCV_rw_w
 let MEM_fence_w_w   () = barrier Barrier_RISCV_w_w
+let MEM_fence_w_rw  () = barrier Barrier_RISCV_w_rw
+let MEM_fence_rw_r  () = barrier Barrier_RISCV_rw_r
+let MEM_fence_r_w   () = barrier Barrier_RISCV_r_w
+let MEM_fence_w_r   () = barrier Barrier_RISCV_w_r
 let MEM_fence_i     () = barrier Barrier_RISCV_i
 
 val MEMea                            : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index 601f5008..b29fe545 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -13,6 +13,10 @@ let MEM_fence_r_rw  () = barrier Barrier_RISCV_r_rw
 let MEM_fence_r_r   () = barrier Barrier_RISCV_r_r
 let MEM_fence_rw_w  () = barrier Barrier_RISCV_rw_w
 let MEM_fence_w_w   () = barrier Barrier_RISCV_w_w
+let MEM_fence_w_rw  () = barrier Barrier_RISCV_w_rw
+let MEM_fence_rw_r  () = barrier Barrier_RISCV_rw_r
+let MEM_fence_r_w   () = barrier Barrier_RISCV_r_w
+let MEM_fence_w_r   () = barrier Barrier_RISCV_w_r
 let MEM_fence_i     () = barrier Barrier_RISCV_i
 
 val MEMea                            : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail
index bdbb72bf..9ead3aeb 100644
--- a/riscv/riscv_mem.sail
+++ b/riscv/riscv_mem.sail
@@ -140,4 +140,8 @@ val MEM_fence_r_rw  = {ocaml: "skip", lem: "MEM_fence_r_rw"}  : unit -> unit eff
 val MEM_fence_r_r   = {ocaml: "skip", lem: "MEM_fence_r_r"}   : unit -> unit effect {barr}
 val MEM_fence_rw_w  = {ocaml: "skip", lem: "MEM_fence_rw_w"}  : unit -> unit effect {barr}
 val MEM_fence_w_w   = {ocaml: "skip", lem: "MEM_fence_w_w"}   : unit -> unit effect {barr}
+val MEM_fence_w_rw  = {ocaml: "skip", lem: "MEM_fence_w_rw"}  : unit -> unit effect {barr}
+val MEM_fence_rw_r  = {ocaml: "skip", lem: "MEM_fence_rw_r"}  : unit -> unit effect {barr}
+val MEM_fence_r_w   = {ocaml: "skip", lem: "MEM_fence_r_w"}   : unit -> unit effect {barr}
+val MEM_fence_w_r   = {ocaml: "skip", lem: "MEM_fence_w_r"}   : unit -> unit effect {barr}
 val MEM_fence_i     = {ocaml: "skip", lem: "MEM_fence_i"}     : unit -> unit effect {barr}
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index 2991377d..e2341a8a 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -468,7 +468,7 @@ mapping reg_name = {
 }
 
 val sep : unit <-> string
-mapping sep = {
+mapping sep : unit <-> string = {
   () <-> opt_spc() ^ "," ^ def_spc()
 }
 
diff --git a/src/lem_interp/sail2_instr_kinds.lem b/src/lem_interp/sail2_instr_kinds.lem
index 13e5304e..938b693d 100644
--- a/src/lem_interp/sail2_instr_kinds.lem
+++ b/src/lem_interp/sail2_instr_kinds.lem
@@ -151,6 +151,10 @@ type barrier_kind =
   | Barrier_RISCV_r_r
   | Barrier_RISCV_rw_w
   | Barrier_RISCV_w_w
+  | Barrier_RISCV_w_rw
+  | Barrier_RISCV_rw_r
+  | Barrier_RISCV_r_w
+  | Barrier_RISCV_w_r
   | Barrier_RISCV_i
   (* X86 *)
   | Barrier_x86_MFENCE
@@ -176,6 +180,10 @@ instance (Show barrier_kind)
     | Barrier_RISCV_r_r   -> "Barrier_RISCV_r_r"
     | Barrier_RISCV_rw_w  -> "Barrier_RISCV_rw_w"
     | Barrier_RISCV_w_w   -> "Barrier_RISCV_w_w"
+    | Barrier_RISCV_w_rw  -> "Barrier_RISCV_w_rw"
+    | Barrier_RISCV_rw_r  -> "Barrier_RISCV_rw_r"
+    | Barrier_RISCV_r_w   -> "Barrier_RISCV_r_w"
+    | Barrier_RISCV_w_r   -> "Barrier_RISCV_w_r"
     | Barrier_RISCV_i     -> "Barrier_RISCV_i"
     | Barrier_x86_MFENCE  -> "Barrier_x86_MFENCE"
   end
@@ -288,7 +296,11 @@ instance (EnumerationType barrier_kind)
     | Barrier_RISCV_r_r -> 15
     | Barrier_RISCV_rw_w -> 16
     | Barrier_RISCV_w_w -> 17
-    | Barrier_RISCV_i -> 18
-    | Barrier_x86_MFENCE -> 19
+    | Barrier_RISCV_w_rw -> 18
+    | Barrier_RISCV_rw_r -> 19
+    | Barrier_RISCV_r_w -> 20
+    | Barrier_RISCV_w_r -> 21
+    | Barrier_RISCV_i -> 22
+    | Barrier_x86_MFENCE -> 23
   end
 end
-- 
cgit v1.2.3


From 0f0824741374ace62915eace4a91c77ba1bf3b33 Mon Sep 17 00:00:00 2001
From: Jon French
Date: Thu, 5 Jul 2018 14:00:50 +0100
Subject: print to stdout not stderr to stop upsetting rmem regression tests

---
 riscv/prelude.sail                | 8 ++++----
 riscv/riscv_extras.lem            | 8 +++++++-
 riscv/riscv_extras_sequential.lem | 8 +++++++-
 3 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/riscv/prelude.sail b/riscv/prelude.sail
index 412dcfc7..9ec1d86d 100644
--- a/riscv/prelude.sail
+++ b/riscv/prelude.sail
@@ -217,7 +217,7 @@ function cast_unit_vec b = match b {
   bitone  => 0b1
 }
 
-val print = "prerr_endline" : string -> unit
+val print = "print_endline" : string -> unit
 
 val putchar = "putchar" : forall ('a : Type). 'a -> unit
 
@@ -402,9 +402,9 @@ val slice = "slice" : forall ('n : Int) ('m : Int), 'm >= 0 & 'n >= 0.
 
 val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n)
 
-val print_int = "prerr_int" : (string, int) -> unit
-val print_bits = "prerr_bits" : forall 'n. (string, bits('n)) -> unit
-val print_string = "prerr_string" : (string, string) -> unit
+val print_int = "print_int" : (string, int) -> unit
+val print_bits = "print_bits" : forall 'n. (string, bits('n)) -> unit
+val print_string = "print_string" : (string, string) -> unit
 
 val "sign_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m)
 val "zero_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m)
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index b29fe545..b3d84df6 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -101,7 +101,13 @@ val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvecto
 let shift_bits_left v m = shiftl v (uint m)
 
 val print_string : string -> string -> unit
-let print_string msg s = prerr_endline (msg ^ s)
+let print_string msg s = print_endline (msg ^ s)
+
+val prerr_string : string -> string -> unit
+let prerr_string msg s = prerr_endline (msg ^ s)
 
 val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
 let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
+
+val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
+let print_bits msg bs = print_endline (msg ^ (show_bitlist (bits_of bs)))
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index b29fe545..b3d84df6 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -101,7 +101,13 @@ val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvecto
 let shift_bits_left v m = shiftl v (uint m)
 
 val print_string : string -> string -> unit
-let print_string msg s = prerr_endline (msg ^ s)
+let print_string msg s = print_endline (msg ^ s)
+
+val prerr_string : string -> string -> unit
+let prerr_string msg s = prerr_endline (msg ^ s)
 
 val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
 let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
+
+val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
+let print_bits msg bs = print_endline (msg ^ (show_bitlist (bits_of bs)))
-- 
cgit v1.2.3


From 35ecc1210857dc9e3791483910be4c6e47325b76 Mon Sep 17 00:00:00 2001
From: Jon French
Date: Thu, 5 Jul 2018 14:01:08 +0100
Subject: support acquire/release loads/stores in RISCV initial_analysis

---
 riscv/riscv.sail | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index b50c9225..d97b99c6 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -1899,8 +1899,8 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
              ik =
                match (aq, rl) {
                  (false, false) => IK_mem_read (Read_plain),
-                 //(true,  false) -> IK_mem_read (Read_RISCV_acquire_RCpc)
-                 //(true,  true)  -> IK_mem_read (Read_RISCV_acquire_RCsc)
+                 (true,  false) => IK_mem_read (Read_RISCV_acquire),
+                 (true,  true)  => IK_mem_read (Read_RISCV_strong_acquire),
 
                  _  => internal_error("LOAD type not implemented in initial_analysis")
                }
@@ -1912,8 +1912,8 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
              ik =
                match (aq, rl) {
                  (false, false) => IK_mem_write (Write_plain),
-                 //case (false, true)  -> IK_mem_write (Write_RISCV_release_RCpc)
-                 //case (true,  true)  -> IK_mem_write (Write_RISCV_release_RCsc)
+                 (false, true)  => IK_mem_write (Write_RISCV_release),
+                 (true,  true)  => IK_mem_write (Write_RISCV_strong_release),
 
                  _ => internal_error("STORE type not implemented in initial_analysis")
                }
-- 
cgit v1.2.3


From 86194c561fbb9ea24b28f413f16211d5920bb362 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 5 Jul 2018 16:17:01 +0100
Subject: make many generated c functions static -- this gives the compiler a
 chance to notice if they are dead or inline them if appropriate, cleaning up
 coverage reports and potentially improving execution speed.

---
 src/c_backend.ml | 66 ++++++++++++++++++++++++++++----------------------------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/src/c_backend.ml b/src/c_backend.ml
index 4335e98e..eeb3390e 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -2086,7 +2086,7 @@ let codegen_type_def ctx = function
   | CTD_enum (id, ids) ->
      let codegen_eq =
        let name = sgen_id id in
-       string (Printf.sprintf "bool eq_%s(enum %s op1, enum %s op2) { return op1 == op2; }" name name name)
+       string (Printf.sprintf "static bool eq_%s(enum %s op1, enum %s op2) { return op1 == op2; }" name name name)
      in
      string (Printf.sprintf "// enum %s" (string_of_id id)) ^^ hardline
      ^^ separate space [string "enum"; codegen_id id; lbrace; separate_map (comma ^^ space) upper_codegen_id ids; rbrace ^^ semi]
@@ -2102,7 +2102,7 @@ let codegen_type_def ctx = function
          string (Printf.sprintf "COPY(%s)(&rop->%s, op.%s);" (sgen_ctyp_name ctyp) (sgen_id id) (sgen_id id))
      in
      let codegen_setter id ctors =
-       string (let n = sgen_id id in Printf.sprintf "void COPY(%s)(struct %s *rop, const struct %s op)" n n n) ^^ space
+       string (let n = sgen_id id in Printf.sprintf "static void COPY(%s)(struct %s *rop, const struct %s op)" n n n) ^^ space
        ^^ surround 2 0 lbrace
                    (separate_map hardline codegen_set (Bindings.bindings ctors))
                    rbrace
@@ -2114,13 +2114,13 @@ let codegen_type_def ctx = function
        else []
      in
      let codegen_init f id ctors =
-       string (let n = sgen_id id in Printf.sprintf "void %s(%s)(struct %s *op)" f n n) ^^ space
+       string (let n = sgen_id id in Printf.sprintf "static void %s(%s)(struct %s *op)" f n n) ^^ space
        ^^ surround 2 0 lbrace
                    (separate hardline (Bindings.bindings ctors |> List.map (codegen_field_init f) |> List.concat))
                    rbrace
      in
      let codegen_eq =
-       string (Printf.sprintf "bool eq_%s(struct %s op1, struct %s op2) { return true; }" (sgen_id id) (sgen_id id) (sgen_id id))
+       string (Printf.sprintf "static bool eq_%s(struct %s op1, struct %s op2) { return true; }" (sgen_id id) (sgen_id id) (sgen_id id))
      in
      (* Generate the struct and add the generated functions *)
      let codegen_ctor (id, ctyp) =
@@ -2161,7 +2161,7 @@ let codegen_type_def ctx = function
      let codegen_init =
        let n = sgen_id id in
        let ctor_id, ctyp = List.hd tus in
-       string (Printf.sprintf "void CREATE(%s)(struct %s *op)" n n)
+       string (Printf.sprintf "static void CREATE(%s)(struct %s *op)" n n)
        ^^ hardline
        ^^ surround 2 0 lbrace
                    (string (Printf.sprintf "op->kind = Kind_%s;" (sgen_id ctor_id)) ^^ hardline
@@ -2172,7 +2172,7 @@ let codegen_type_def ctx = function
      in
      let codegen_reinit =
        let n = sgen_id id in
-       string (Printf.sprintf "void RECREATE(%s)(struct %s *op) {}" n n)
+       string (Printf.sprintf "static void RECREATE(%s)(struct %s *op) {}" n n)
      in
      let clear_field v ctor_id ctyp =
        if is_stack_ctyp ctyp then
@@ -2182,7 +2182,7 @@ let codegen_type_def ctx = function
      in
      let codegen_clear =
        let n = sgen_id id in
-       string (Printf.sprintf "void KILL(%s)(struct %s *op)" n n) ^^ hardline
+       string (Printf.sprintf "static void KILL(%s)(struct %s *op)" n n) ^^ hardline
        ^^ surround 2 0 lbrace
                    (each_ctor "op->" (clear_field "op") tus ^^ semi)
                    rbrace
@@ -2203,7 +2203,7 @@ let codegen_type_def ctx = function
             ^^ separate hardline (List.mapi tuple_set ctyps) ^^ hardline
          | ctyp -> Printf.sprintf "%s op" (sgen_ctyp ctyp), empty
        in
-       string (Printf.sprintf "void %s(struct %s *rop, %s)" (sgen_id ctor_id) (sgen_id id) ctor_args) ^^ hardline
+       string (Printf.sprintf "static void %s(struct %s *rop, %s)" (sgen_id ctor_id) (sgen_id id) ctor_args) ^^ hardline
        ^^ surround 2 0 lbrace
                    (tuple
                     ^^ each_ctor "rop->" (clear_field "rop") tus ^^ hardline
@@ -2224,7 +2224,7 @@ let codegen_type_def ctx = function
            string (Printf.sprintf "CREATE(%s)(&rop->%s);" (sgen_ctyp_name ctyp) (sgen_id ctor_id))
            ^^ string (Printf.sprintf " COPY(%s)(&rop->%s, op.%s);" (sgen_ctyp_name ctyp) (sgen_id ctor_id) (sgen_id ctor_id))
        in
-       string (Printf.sprintf "void COPY(%s)(struct %s *rop, struct %s op)" n n n) ^^ hardline
+       string (Printf.sprintf "static void COPY(%s)(struct %s *rop, struct %s op)" n n n) ^^ hardline
        ^^ surround 2 0 lbrace
                    (each_ctor "rop->" (clear_field "rop") tus
                     ^^ semi ^^ hardline
@@ -2306,10 +2306,10 @@ let codegen_node id ctyp =
   ^^ string (Printf.sprintf "typedef struct node_%s *%s;" (sgen_id id) (sgen_id id))
 
 let codegen_list_init id =
-  string (Printf.sprintf "void CREATE(%s)(%s *rop) { *rop = NULL; }" (sgen_id id) (sgen_id id))
+  string (Printf.sprintf "static void CREATE(%s)(%s *rop) { *rop = NULL; }" (sgen_id id) (sgen_id id))
 
 let codegen_list_clear id ctyp =
-  string (Printf.sprintf "void KILL(%s)(%s *rop) {\n" (sgen_id id) (sgen_id id))
+  string (Printf.sprintf "static void KILL(%s)(%s *rop) {\n" (sgen_id id) (sgen_id id))
   ^^ string (Printf.sprintf "  if (*rop == NULL) return;")
   ^^ (if is_stack_ctyp ctyp then empty
       else string (Printf.sprintf "  KILL(%s)(&(*rop)->hd);\n" (sgen_ctyp_name ctyp)))
@@ -2318,7 +2318,7 @@ let codegen_list_clear id ctyp =
   ^^ string "}"
 
 let codegen_list_set id ctyp =
-  string (Printf.sprintf "void internal_set_%s(%s *rop, const %s op) {\n" (sgen_id id) (sgen_id id) (sgen_id id))
+  string (Printf.sprintf "static void internal_set_%s(%s *rop, const %s op) {\n" (sgen_id id) (sgen_id id) (sgen_id id))
   ^^ string "  if (op == NULL) { *rop = NULL; return; };\n"
   ^^ string (Printf.sprintf "  *rop = malloc(sizeof(struct node_%s));\n" (sgen_id id))
   ^^ (if is_stack_ctyp ctyp then
@@ -2329,14 +2329,14 @@ let codegen_list_set id ctyp =
   ^^ string (Printf.sprintf "  internal_set_%s(&(*rop)->tl, op->tl);\n" (sgen_id id))
   ^^ string "}"
   ^^ twice hardline
-  ^^ string (Printf.sprintf "void COPY(%s)(%s *rop, const %s op) {\n" (sgen_id id) (sgen_id id) (sgen_id id))
+  ^^ string (Printf.sprintf "static void COPY(%s)(%s *rop, const %s op) {\n" (sgen_id id) (sgen_id id) (sgen_id id))
   ^^ string (Printf.sprintf "  KILL(%s)(rop);\n" (sgen_id id))
   ^^ string (Printf.sprintf "  internal_set_%s(rop, op);\n" (sgen_id id))
   ^^ string "}"
 
 let codegen_cons id ctyp =
   let cons_id = mk_id ("cons#" ^ string_of_ctyp ctyp) in
-  string (Printf.sprintf "void %s(%s *rop, const %s x, const %s xs) {\n" (sgen_id cons_id) (sgen_id id) (sgen_ctyp ctyp) (sgen_id id))
+  string (Printf.sprintf "static void %s(%s *rop, const %s x, const %s xs) {\n" (sgen_id cons_id) (sgen_id id) (sgen_ctyp ctyp) (sgen_id id))
   ^^ string (Printf.sprintf "  *rop = malloc(sizeof(struct node_%s));\n" (sgen_id id))
   ^^ (if is_stack_ctyp ctyp then
         string "  (*rop)->hd = x;\n"
@@ -2348,9 +2348,9 @@ let codegen_cons id ctyp =
 
 let codegen_pick id ctyp =
   if is_stack_ctyp ctyp then
-    string (Printf.sprintf "%s pick_%s(const %s xs) { return xs->hd; }" (sgen_ctyp ctyp) (sgen_ctyp_name ctyp) (sgen_id id))
+    string (Printf.sprintf "static %s pick_%s(const %s xs) { return xs->hd; }" (sgen_ctyp ctyp) (sgen_ctyp_name ctyp) (sgen_id id))
   else
-    string (Printf.sprintf "void pick_%s(%s *x, const %s xs) { COPY(%s)(x, xs->hd); }" (sgen_ctyp_name ctyp) (sgen_ctyp ctyp) (sgen_id id) (sgen_ctyp_name ctyp))
+    string (Printf.sprintf "static void pick_%s(%s *x, const %s xs) { COPY(%s)(x, xs->hd); }" (sgen_ctyp_name ctyp) (sgen_ctyp ctyp) (sgen_id id) (sgen_ctyp_name ctyp))
 
 let codegen_list ctx ctyp =
   let id = mk_id (string_of_ctyp (CT_list ctyp)) in
@@ -2378,10 +2378,10 @@ let codegen_vector ctx (direction, ctyp) =
       ^^ string (Printf.sprintf "typedef struct %s %s;" (sgen_id id) (sgen_id id))
     in
     let vector_init =
-      string (Printf.sprintf "void CREATE(%s)(%s *rop) {\n  rop->len = 0;\n  rop->data = NULL;\n}" (sgen_id id) (sgen_id id))
+      string (Printf.sprintf "static void CREATE(%s)(%s *rop) {\n  rop->len = 0;\n  rop->data = NULL;\n}" (sgen_id id) (sgen_id id))
     in
     let vector_set =
-      string (Printf.sprintf "void COPY(%s)(%s *rop, %s op) {\n" (sgen_id id) (sgen_id id) (sgen_id id))
+      string (Printf.sprintf "static void COPY(%s)(%s *rop, %s op) {\n" (sgen_id id) (sgen_id id) (sgen_id id))
       ^^ string (Printf.sprintf "  KILL(%s)(rop);\n" (sgen_id id))
       ^^ string "  rop->len = op.len;\n"
       ^^ string (Printf.sprintf "  rop->data = malloc((rop->len) * sizeof(%s));\n" (sgen_ctyp ctyp))
@@ -2394,7 +2394,7 @@ let codegen_vector ctx (direction, ctyp) =
       ^^ string "}"
     in
     let vector_clear =
-      string (Printf.sprintf "void KILL(%s)(%s *rop) {\n" (sgen_id id) (sgen_id id))
+      string (Printf.sprintf "static void KILL(%s)(%s *rop) {\n" (sgen_id id) (sgen_id id))
       ^^ (if is_stack_ctyp ctyp then empty
          else
            string "  for (int i = 0; i < (rop->len); i++) {\n"
@@ -2404,7 +2404,7 @@ let codegen_vector ctx (direction, ctyp) =
       ^^ string "}"
     in
     let vector_update =
-      string (Printf.sprintf "void vector_update_%s(%s *rop, %s op, mpz_t n, %s elem) {\n" (sgen_id id) (sgen_id id) (sgen_id id) (sgen_ctyp ctyp))
+      string (Printf.sprintf "static void vector_update_%s(%s *rop, %s op, mpz_t n, %s elem) {\n" (sgen_id id) (sgen_id id) (sgen_id id) (sgen_ctyp ctyp))
       ^^ string "  int m = mpz_get_ui(n);\n"
       ^^ string "  if (rop->data == op.data) {\n"
       ^^ string (if is_stack_ctyp ctyp then
@@ -2421,7 +2421,7 @@ let codegen_vector ctx (direction, ctyp) =
       ^^ string "}"
     in
     let internal_vector_update =
-      string (Printf.sprintf "void internal_vector_update_%s(%s *rop, %s op, const int64_t n, %s elem) {\n" (sgen_id id) (sgen_id id) (sgen_id id) (sgen_ctyp ctyp))
+      string (Printf.sprintf "static void internal_vector_update_%s(%s *rop, %s op, const int64_t n, %s elem) {\n" (sgen_id id) (sgen_id id) (sgen_id id) (sgen_ctyp ctyp))
       ^^ string (if is_stack_ctyp ctyp then
                    "  rop->data[n] = elem;\n"
                  else
@@ -2430,24 +2430,24 @@ let codegen_vector ctx (direction, ctyp) =
     in
     let vector_access =
       if is_stack_ctyp ctyp then
-        string (Printf.sprintf "%s vector_access_%s(%s op, mpz_t n) {\n" (sgen_ctyp ctyp) (sgen_id id) (sgen_id id))
+        string (Printf.sprintf "static %s vector_access_%s(%s op, mpz_t n) {\n" (sgen_ctyp ctyp) (sgen_id id) (sgen_id id))
         ^^ string "  int m = mpz_get_ui(n);\n"
         ^^ string "  return op.data[m];\n"
         ^^ string "}"
       else
-        string (Printf.sprintf "void vector_access_%s(%s *rop, %s op, mpz_t n) {\n" (sgen_id id) (sgen_ctyp ctyp) (sgen_id id))
+        string (Printf.sprintf "static void vector_access_%s(%s *rop, %s op, mpz_t n) {\n" (sgen_id id) (sgen_ctyp ctyp) (sgen_id id))
         ^^ string "  int m = mpz_get_ui(n);\n"
         ^^ string (Printf.sprintf "  COPY(%s)(rop, op.data[m]);\n" (sgen_ctyp_name ctyp))
         ^^ string "}"
     in
     let internal_vector_init =
-      string (Printf.sprintf "void internal_vector_init_%s(%s *rop, const int64_t len) {\n" (sgen_id id) (sgen_id id))
+      string (Printf.sprintf "static void internal_vector_init_%s(%s *rop, const int64_t len) {\n" (sgen_id id) (sgen_id id))
       ^^ string "  rop->len = len;\n"
       ^^ string (Printf.sprintf "  rop->data = malloc(len * sizeof(%s));\n" (sgen_ctyp ctyp))
       ^^ string "}"
     in
     let vector_undefined =
-      string (Printf.sprintf "void undefined_vector_%s(%s *rop, mpz_t len, %s elem) {\n" (sgen_id id) (sgen_id id) (sgen_ctyp ctyp))
+      string (Printf.sprintf "static void undefined_vector_%s(%s *rop, mpz_t len, %s elem) {\n" (sgen_id id) (sgen_id id) (sgen_ctyp ctyp))
       ^^ string (Printf.sprintf "  rop->len = mpz_get_ui(len);\n")
       ^^ string (Printf.sprintf "  rop->data = malloc((rop->len) * sizeof(%s));\n" (sgen_ctyp ctyp))
       ^^ string "  for (int i = 0; i < (rop->len); i++) {\n"
@@ -2495,9 +2495,9 @@ let codegen_def' ctx = function
      if Env.is_extern id ctx.tc_env "c" then
        empty
      else if is_stack_ctyp ret_ctyp then
-       string (Printf.sprintf "%s %s(%s);" (sgen_ctyp ret_ctyp) (sgen_id id) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
+       string (Printf.sprintf "static %s %s(%s);" (sgen_ctyp ret_ctyp) (sgen_id id) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
      else
-       string (Printf.sprintf "void %s(%s *rop, %s);" (sgen_id id) (sgen_ctyp ret_ctyp) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
+       string (Printf.sprintf "static void %s(%s *rop, %s);" (sgen_id id) (sgen_ctyp ret_ctyp) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
 
   | CDEF_fundef (id, ret_arg, args, instrs) as def ->
      if !opt_ddump_flow_graphs then make_dot id (instrs_graph instrs) else ();
@@ -2521,10 +2521,10 @@ let codegen_def' ctx = function
        match ret_arg with
        | None ->
           assert (is_stack_ctyp ret_ctyp);
-          string (sgen_ctyp ret_ctyp) ^^ space ^^ codegen_id id ^^ parens (string args) ^^ hardline
+          string "static " ^^ string (sgen_ctyp ret_ctyp) ^^ space ^^ codegen_id id ^^ parens (string args) ^^ hardline
        | Some gs ->
           assert (not (is_stack_ctyp ret_ctyp));
-          string "void" ^^ space ^^ codegen_id id
+          string "static void" ^^ space ^^ codegen_id id
           ^^ parens (string (sgen_ctyp ret_ctyp ^ " *" ^ sgen_id gs ^ ", ") ^^ string args)
           ^^ hardline
      in
@@ -2537,7 +2537,7 @@ let codegen_def' ctx = function
      codegen_type_def ctx ctype_def
 
   | CDEF_startup (id, instrs) ->
-     let startup_header = string (Printf.sprintf "void startup_%s(void)" (sgen_id id)) in
+     let startup_header = string (Printf.sprintf "static void startup_%s(void)" (sgen_id id)) in
      separate_map hardline codegen_decl instrs
      ^^ twice hardline
      ^^ startup_header ^^ hardline
@@ -2546,7 +2546,7 @@ let codegen_def' ctx = function
      ^^ string "}"
 
   | CDEF_finish (id, instrs) ->
-     let finish_header = string (Printf.sprintf "void finish_%s(void)" (sgen_id id)) in
+     let finish_header = string (Printf.sprintf "static void finish_%s(void)" (sgen_id id)) in
      separate_map hardline codegen_decl (List.filter is_decl instrs)
      ^^ twice hardline
      ^^ finish_header ^^ hardline
@@ -2563,12 +2563,12 @@ let codegen_def' ctx = function
        List.concat (List.map (fun (id, ctyp) -> [iclear ctyp id]) bindings)
      in
      separate_map hardline (fun (id, ctyp) -> string (Printf.sprintf "%s %s;" (sgen_ctyp ctyp) (sgen_id id))) bindings
-     ^^ hardline ^^ string (Printf.sprintf "void create_letbind_%d(void) " number)
+     ^^ hardline ^^ string (Printf.sprintf "static void create_letbind_%d(void) " number)
      ^^ string "{"
      ^^ jump 0 2 (separate_map hardline codegen_alloc setup) ^^ hardline
      ^^ jump 0 2 (separate_map hardline (codegen_instr (mk_id "let") { ctx with no_raw = true }) instrs) ^^ hardline
      ^^ string "}"
-     ^^ hardline ^^ string (Printf.sprintf "void kill_letbind_%d(void) " number)
+     ^^ hardline ^^ string (Printf.sprintf "static void kill_letbind_%d(void) " number)
      ^^ string "{"
      ^^ jump 0 2 (separate_map hardline (codegen_instr (mk_id "let") ctx) cleanup) ^^ hardline
      ^^ string "}"
-- 
cgit v1.2.3


From e5654331c24391e984484e590993887b499af9f8 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 5 Jul 2018 16:30:31 +0100
Subject: mips: ignore unused functions warnings caused by making some
 functions static.

---
 mips/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mips/Makefile b/mips/Makefile
index d3a21957..f8b7588f 100644
--- a/mips/Makefile
+++ b/mips/Makefile
@@ -18,7 +18,7 @@ mips: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS) $(MIPS_MAIN) ../sail
 mips.c: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS) $(MIPS_MAIN) Makefile ../sail
 	$(SAIL) -O -memo_z3 -c $(filter %.sail, $^) 1> $@
 
-C_WARNINGS=-Wall -Wno-unused-but-set-variable -Wno-unused-label -Wno-maybe-uninitialized -Wno-return-type
+C_WARNINGS=-Wall -Wno-unused-but-set-variable -Wno-unused-label -Wno-unused-function -Wno-maybe-uninitialized -Wno-return-type
 C_OPT=-O2
 GCOV_FLAGS=
 mips_c: mips.c ../lib/sail.h ../lib/*.c Makefile 
-- 
cgit v1.2.3


From 9a0cbbedbe281807f70bf2206756624315096642 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Thu, 5 Jul 2018 19:09:26 +0100
Subject: Fix CHERI test that was failing when compiled to C

Non bitvector literals for decreasing vectors were not being reversed
correctly, so the list of capability registers was effectively in
reverse order.

Added a test case to test/c/ based on this aspect of CHERI
---
 src/c_backend.ml           |   2 +-
 test/c/cheri_capreg.expect |  10 ++
 test/c/cheri_capreg.sail   | 254 +++++++++++++++++++++++++++++++++++++++++++++
 test/c/gvectorlit.expect   |   4 +-
 4 files changed, 267 insertions(+), 3 deletions(-)
 create mode 100644 test/c/cheri_capreg.expect
 create mode 100644 test/c/cheri_capreg.sail

diff --git a/src/c_backend.ml b/src/c_backend.ml
index eeb3390e..6f1379e3 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -691,7 +691,7 @@ let rec compile_aval ctx = function
      in
      [idecl vector_ctyp gs;
       iextern (CL_id gs) (mk_id "internal_vector_init") [(F_lit (V_int (Big_int.of_int len)), CT_int64)] vector_ctyp]
-     @ List.concat (List.mapi aval_set avals),
+     @ List.concat (List.mapi aval_set (if direction then List.rev avals else avals)),
      (F_id gs, vector_ctyp),
      [iclear vector_ctyp gs]
 
diff --git a/test/c/cheri_capreg.expect b/test/c/cheri_capreg.expect
new file mode 100644
index 00000000..6e46a0e8
--- /dev/null
+++ b/test/c/cheri_capreg.expect
@@ -0,0 +1,10 @@
+default_cap = 0b10000000000000000000000000000000011111111111111110000111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
+null_cap = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
+C03 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+C02 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+C01 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+DDC = 0b10000000000000000000000000000000011111111111111110000111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
+C03 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
+C02 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
+C01 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
+DDC = 0b10000000000000000000000000000000011111111111111110000111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111
diff --git a/test/c/cheri_capreg.sail b/test/c/cheri_capreg.sail
new file mode 100644
index 00000000..d9933a5d
--- /dev/null
+++ b/test/c/cheri_capreg.sail
@@ -0,0 +1,254 @@
+default Order dec
+
+/* this is here because if we don't have it before including vector_dec
+   we get infinite loops caused by interaction with bool/bit casts */
+val eq_bit2 = "eq_bit" : (bit, bit) -> bool
+overload operator == = {eq_bit2}
+
+$include <vector_dec.sail>
+
+val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg}
+/* sneaky deref with no effect necessary for bitfield writes */
+val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a
+
+val zeros_0 = "zeros" : forall 'n. int('n) -> bits('n)
+
+val zeros : forall 'n. unit -> bits('n)
+function zeros() = zeros_0('n)
+
+val ones : forall 'n, 'n >= 0 . unit -> bits('n)
+function ones() = replicate_bits (0b1,'n)
+
+val xor_vec = {c: "xor_bits" , _: "xor_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n)
+
+val int_power = {ocaml: "int_power", lem: "pow", coq: "Z.pow"} : (int, int) -> int
+
+overload operator ^ = {xor_vec, int_power}
+
+val cast bool_to_bits : bool -> bits(1)
+function bool_to_bits x = if x then 0b1 else 0b0
+
+val cast bit_to_bool : bit -> bool
+function bit_to_bool b = match b {
+  bitone => true,
+  bitzero => false
+}
+
+val to_bits : forall 'l, 'l >= 0 .(atom('l), int) -> bits('l)
+function to_bits (l, n) = get_slice_int(l, n, 0)
+
+/* 256 bit cap + tag */
+type CapReg = bits(257)
+
+struct CapStruct = {
+  tag                     : bool    ,
+  padding                 : bits(8) ,
+  otype                   : bits(24),
+  uperms                  : bits(16),
+  perm_reserved11_14      : bits(4) ,
+  access_system_regs      : bool    ,
+  permit_unseal           : bool    ,
+  permit_ccall            : bool    ,
+  permit_seal             : bool    ,
+  permit_store_local_cap  : bool    ,
+  permit_store_cap        : bool    ,
+  permit_load_cap         : bool    ,
+  permit_store            : bool    ,
+  permit_load             : bool    ,
+  permit_execute          : bool    ,
+  global                  : bool    ,
+  sealed                  : bool    ,
+  address                 : bits(64),
+  base                    : bits(64),
+  length                  : bits(64),
+}
+
+let null_cap : CapStruct = struct {
+  tag = false,
+  padding = zeros(),
+  otype = zeros(),
+  uperms = zeros(),
+  perm_reserved11_14 = zeros(),
+  access_system_regs = false,
+  permit_unseal = false,
+  permit_ccall = false,
+  permit_seal = false,
+  permit_store_local_cap = false,
+  permit_store_cap = false,
+  permit_load_cap = false,
+  permit_store = false,
+  permit_load = false,
+  permit_execute = false,
+  global = false,
+  sealed = false,
+  address = zeros(),
+  base = zeros(),
+  length = 0xffffffffffffffff
+}
+
+let default_cap : CapStruct = struct {
+  tag = true,
+  padding = zeros(),
+  otype = zeros(),
+  uperms = ones(),
+  perm_reserved11_14 = zeros(),
+  access_system_regs = true,
+  permit_unseal = true,
+  permit_ccall = true,
+  permit_seal = true,
+  permit_store_local_cap = true,
+  permit_store_cap = true,
+  permit_load_cap = true,
+  permit_store = true,
+  permit_load = true,
+  permit_execute = true,
+  global = true,
+  sealed = false,
+  address = zeros(),
+  base = zeros(),
+  length = 0xffffffffffffffff
+}
+
+let null_cap : CapStruct = struct {
+  tag = false,
+  padding = zeros(),
+  otype = zeros(),
+  uperms = zeros(),
+  perm_reserved11_14 = zeros(),
+  access_system_regs = false,
+  permit_unseal = false,
+  permit_ccall = false,
+  permit_seal = false,
+  permit_store_local_cap = false,
+  permit_store_cap = false,
+  permit_load_cap = false,
+  permit_store = false,
+  permit_load = false,
+  permit_execute = false,
+  global = false,
+  sealed = false,
+  address = zeros(),
+  base = zeros(),
+  length = 0xffffffffffffffff
+}
+
+let 'cap_size = 32
+
+function capRegToCapStruct(capReg) : CapReg -> CapStruct =
+  struct {
+    tag                        = capReg[256],
+    padding                    = capReg[255..248],
+    otype                      = capReg[247..224],
+    uperms                     = capReg[223..208],
+    perm_reserved11_14         = capReg[207..204],
+    access_system_regs         = capReg[203],
+    permit_unseal              = capReg[202],
+    permit_ccall               = capReg[201],
+    permit_seal                = capReg[200],
+    permit_store_local_cap     = capReg[199],
+    permit_store_cap           = capReg[198],
+    permit_load_cap            = capReg[197],
+    permit_store               = capReg[196],
+    permit_load                = capReg[195],
+    permit_execute             = capReg[194],
+    global                     = capReg[193],
+    sealed                     = capReg[192],
+    address                    = capReg[191..128],
+    base                       = capReg[127..64],
+    length                     = capReg[63..0]
+  }
+
+function getCapPerms(cap) : CapStruct -> bits(31) = 
+  (
+    cap.uperms
+      @ cap.perm_reserved11_14
+      @ cap.access_system_regs
+      @ cap.permit_unseal
+      @ cap.permit_ccall
+      @ cap.permit_seal
+      @ cap.permit_store_local_cap
+      @ cap.permit_store_cap
+      @ cap.permit_load_cap
+      @ cap.permit_store
+      @ cap.permit_load
+      @ cap.permit_execute
+      @ cap.global
+  )
+
+
+/* Function to convert capabilities to in-memory format. */
+function capStructToMemBits256(cap) : CapStruct -> bits(256) =
+  (
+        cap.padding
+      @ cap.otype
+      @ getCapPerms(cap)
+      @ cap.sealed
+      @ cap.address
+      @ cap.base
+      @ cap.length
+  )
+
+
+/* When saving/restoring capabilities xor them with bits of null_cap --
+   this ensures that canonical null_cap is always all-zeros in memory
+   even though it may have bits set logically (e.g. length or exponent) */
+
+let null_cap_bits : bits(256) = capStructToMemBits256(null_cap)
+
+function capStructToMemBits(cap) : CapStruct -> bits(256)=
+  capStructToMemBits256(cap) ^ null_cap_bits
+
+function memBitsToCapBits(tag, b) : (bool, bits(256)) -> bits(257)  =
+  tag @ (b ^ null_cap_bits)
+
+function capStructToCapReg(cap) : CapStruct -> CapReg = cap.tag @ capStructToMemBits256(cap)
+
+register DDC : CapReg
+register C01 : CapReg
+register C02 : CapReg
+register C03 : CapReg
+
+let CapRegs : vector(4, dec, register(CapReg)) =
+  [
+    ref C03,
+    ref C02,
+    ref C01,
+    ref DDC
+  ]
+
+val readCapReg : bits(2) -> CapStruct effect {rreg}
+function readCapReg(n) =
+  if (n == 0b00) then
+    default_cap
+  else
+    let i = unsigned(n) in
+    capRegToCapStruct(reg_deref(CapRegs[i]))
+
+function writeCapReg(n, cap) : (bits(2), CapStruct) -> unit =
+  if (n == 0b00) then
+    ()
+  else
+    let i = unsigned(n) in
+    (*CapRegs[i]) = capStructToCapReg(cap) 
+
+val "print_bits" : forall 'n. (string, bits('n)) -> unit
+
+val main : unit -> unit effect {rreg, wreg}
+
+function main() = {
+  print_bits("default_cap = ", capStructToCapReg(default_cap));
+  print_bits("null_cap = ", capStructToCapReg(null_cap));
+  DDC = capStructToCapReg(default_cap);
+  print_bits("C03 = ", C03);
+  print_bits("C02 = ", C02);
+  print_bits("C01 = ", C01);
+  print_bits("DDC = ", DDC);
+  foreach(i from 1 to 3) {
+    let idx = to_bits(2, i) in
+    writeCapReg(idx, null_cap)
+  };
+  print_bits("C03 = ", C03);
+  print_bits("C02 = ", C02);
+  print_bits("C01 = ", C01);
+  print_bits("DDC = ", DDC);
+}
\ No newline at end of file
diff --git a/test/c/gvectorlit.expect b/test/c/gvectorlit.expect
index d3a1e9ab..9328600c 100644
--- a/test/c/gvectorlit.expect
+++ b/test/c/gvectorlit.expect
@@ -1,2 +1,2 @@
-x[0] = 0xAB
-x[1] = 0xCD
+x[0] = 0xCD
+x[1] = 0xAB
-- 
cgit v1.2.3


From f62edee6988476ed8ba78424c870461ac8d44256 Mon Sep 17 00:00:00 2001
From: Alasdair
Date: Thu, 5 Jul 2018 20:57:44 +0100
Subject: Fix equality comparisons for structs

Add a test case in test/c/eq_struct.sail. Ensure that the macro EQUAL(type) will always give a valid equality function for any
builtin type in sail.h.
---
 lib/sail.c              | 22 +++++++++++++++++++---
 lib/sail.h              | 10 +++++++---
 src/c_backend.ml        | 14 +++++++++++++-
 test/c/eq_struct.expect |  1 +
 test/c/eq_struct.sail   | 38 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 78 insertions(+), 7 deletions(-)
 create mode 100644 test/c/eq_struct.expect
 create mode 100644 test/c/eq_struct.sail

diff --git a/lib/sail.c b/lib/sail.c
index 4e033c2a..b41cacd3 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -35,7 +35,7 @@ void cleanup_library(void)
   mpq_clear(sail_lib_tmp_real);
 }
 
-bool eq_unit(const unit a, const unit b)
+bool EQUAL(unit)(const unit a, const unit b)
 {
   return true;
 }
@@ -63,7 +63,7 @@ bool not(const bool b) {
   return !b;
 }
 
-bool eq_bool(const bool a, const bool b) {
+bool EQUAL(bool)(const bool a, const bool b) {
   return a == b;
 }
 
@@ -117,6 +117,11 @@ bool eq_string(const sail_string str1, const sail_string str2)
   return strcmp(str1, str2) == 0;
 }
 
+bool EQUAL(sail_string)(const sail_string str1, const sail_string str2)
+{
+  return strcmp(str1, str2) == 0;
+}
+
 void undefined_string(sail_string *str, const unit u) {}
 
 void concat_str(sail_string *stro, const sail_string str1, const sail_string str2)
@@ -197,6 +202,12 @@ bool eq_int(const sail_int op1, const sail_int op2)
   return !abs(mpz_cmp(op1, op2));
 }
 
+inline
+bool EQUAL(sail_int)(const sail_int op1, const sail_int op2)
+{
+  return !abs(mpz_cmp(op1, op2));
+}
+
 inline
 bool lt(const sail_int op1, const sail_int op2)
 {
@@ -533,6 +544,11 @@ bool eq_bits(const sail_bits op1, const sail_bits op2)
   return true;
 }
 
+bool EQUAL(sail_bits)(const sail_bits op1, const sail_bits op2)
+{
+  return eq_bits(op1, op2);
+}
+
 bool neq_bits(const sail_bits op1, const sail_bits op2)
 {
   assert(op1.len == op2.len);
@@ -928,7 +944,7 @@ void to_real(real *rop, const sail_int op)
   mpq_canonicalize(*rop);
 }
 
-bool eq_real(const real op1, const real op2)
+bool EQUAL(real)(const real op1, const real op2)
 {
   return mpq_cmp(op1, op2) == 0;
 }
diff --git a/lib/sail.h b/lib/sail.h
index dce4eea0..dfff7872 100644
--- a/lib/sail.h
+++ b/lib/sail.h
@@ -30,6 +30,7 @@ void cleanup_library(void);
 #define COPY(type) copy_ ## type
 #define KILL(type) kill_ ## type
 #define UNDEFINED(type) undefined_ ## type
+#define EQUAL(type) eq_ ## type
 
 #define SAIL_BUILTIN_TYPE(type)\
   void create_ ## type(type *);\
@@ -44,7 +45,7 @@ typedef int unit;
 #define UNIT 0
 
 unit UNDEFINED(unit)(const unit);
-bool eq_unit(const unit, const unit);
+bool EQUAL(unit)(const unit, const unit);
 
 unit skip(const unit);
 
@@ -55,7 +56,7 @@ unit skip(const unit);
  * short-circuiting evaluation.
  */
 bool not(const bool);
-bool eq_bool(const bool, const bool);
+bool EQUAL(bool)(const bool, const bool);
 bool UNDEFINED(bool)(const unit);
 
 /* ***** Sail strings ***** */
@@ -73,6 +74,7 @@ void hex_str(sail_string *str, const mpz_t n);
 void undefined_string(sail_string *str, const unit u);
 
 bool eq_string(const sail_string, const sail_string);
+bool EQUAL(sail_string)(const sail_string, const sail_string);
 
 void concat_str(sail_string *stro, const sail_string str1, const sail_string str2);
 
@@ -114,6 +116,7 @@ typedef __int128 sail_int;
  * Comparison operators for integers
  */
 bool eq_int(const sail_int, const sail_int);
+bool EQUAL(sail_int)(const sail_int, const sail_int);
 
 bool lt(const sail_int, const sail_int);
 bool gt(const sail_int, const sail_int);
@@ -218,6 +221,7 @@ void sign_extend(sail_bits *rop, const sail_bits op, const sail_int len);
 void length_sail_bits(sail_int *rop, const sail_bits op);
 
 bool eq_bits(const sail_bits op1, const sail_bits op2);
+bool EQUAL(sail_bits)(const sail_bits op1, const sail_bits op2);
 bool neq_bits(const sail_bits op1, const sail_bits op2);
 
 void vector_subrange_sail_bits(sail_bits *rop,
@@ -292,7 +296,7 @@ void round_down(sail_int *rop, const real op);
 
 void to_real(real *rop, const sail_int op);
 
-bool eq_real(const real op1, const real op2);
+bool EQUAL(real)(const real op1, const real op2);
 
 bool lt_real(const real op1, const real op2);
 bool gt_real(const real op1, const real op2);
diff --git a/src/c_backend.ml b/src/c_backend.ml
index 6f1379e3..6097e996 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -2120,7 +2120,19 @@ let codegen_type_def ctx = function
                    rbrace
      in
      let codegen_eq =
-       string (Printf.sprintf "static bool eq_%s(struct %s op1, struct %s op2) { return true; }" (sgen_id id) (sgen_id id) (sgen_id id))
+       let codegen_eq_test (id, ctyp) =
+         if is_stack_ctyp ctyp then
+           string (Printf.sprintf "op1.%s == op2.%s" (sgen_id id) (sgen_id id))
+         else
+           string (Printf.sprintf "EQUAL(%s)(op1.%s, op2.%s)" (sgen_ctyp_name ctyp) (sgen_id id) (sgen_id id))
+       in
+       string (Printf.sprintf "static bool EQUAL(%s)(struct %s op1, struct %s op2)" (sgen_id id) (sgen_id id) (sgen_id id))
+       ^^ space
+       ^^ surround 2 0 lbrace
+            (string "return" ^^ space
+             ^^ separate_map (string " && ") codegen_eq_test ctors
+             ^^ string ";")
+            rbrace
      in
      (* Generate the struct and add the generated functions *)
      let codegen_ctor (id, ctyp) =
diff --git a/test/c/eq_struct.expect b/test/c/eq_struct.expect
new file mode 100644
index 00000000..9766475a
--- /dev/null
+++ b/test/c/eq_struct.expect
@@ -0,0 +1 @@
+ok
diff --git a/test/c/eq_struct.sail b/test/c/eq_struct.sail
new file mode 100644
index 00000000..b4258569
--- /dev/null
+++ b/test/c/eq_struct.sail
@@ -0,0 +1,38 @@
+default Order dec
+
+$include <flow.sail>
+$include <exception_basic.sail>
+
+val eq = "eq_anything" : forall ('a : Type). ('a, 'a) -> bool
+
+overload operator == = {eq}
+
+val neq : forall ('a : Type). ('a, 'a) -> bool
+
+overload operator != = {neq}
+
+overload ~ = {not_bool}
+
+function neq(x, y) = ~(eq(x, y))
+
+struct S = {
+  field1: int,
+  field2: vector(8, dec, bit)
+}
+
+val "print" : string -> unit
+
+val main : unit -> unit effect {escape}
+
+function main() = {
+  let s : S = struct {
+    field1 = 4,
+    field2 = 0xFF
+  };
+  assert(s == s, "1");
+  assert(~(s == { s with field2 = 0xAB }), "2");
+  assert(s != { s with field1 = 5}, "3");
+  assert(s == { s with field2 = 0xFF });
+  assert({ s with field1 = 0} == {s with field1 = 0});
+  print("ok\n")
+}
\ No newline at end of file
-- 
cgit v1.2.3


From b909248ac4599401312d121fc434f0520770454b Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 5 Jul 2018 21:26:21 +0100
Subject: Coq: get index_list right

---
 lib/coq/Sail2_values.v | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index d1f6e560..0fdaa7aa 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -1236,15 +1236,17 @@ end.
 (*declare {isabelle} termination_argument foreach = automatic
 
 val index_list : Z -> Z -> Z -> list Z*)
-Fixpoint index_list' from step n :=
-  match n with
-  | O => []
-  | S n => from :: index_list' (from + step) step n
-  end.
+Fixpoint index_list' from to step n :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    match n with
+    | O => []
+    | S n => from :: index_list' (from + step) to step n
+    end
+  else [].
 
 Definition index_list from to step :=
   if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
-    index_list' from step (S (Z.abs_nat (from - to)))
+    index_list' from to step (S (Z.abs_nat (from - to)))
   else [].
 
 (*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
-- 
cgit v1.2.3


From 79c9c884536cb522ac54c51aad70ab810ea4a420 Mon Sep 17 00:00:00 2001
From: Alasdair
Date: Thu, 5 Jul 2018 21:34:23 +0100
Subject: Fix equality comparisons for variants in C

Makes sure equality comparisons for variants are compiled correctly. Needed for CHERI and mips, which have structs containing
variants. Also make sure that struct equality works for structs containing other structs.
---
 lib/sail.c       | 11 +++++++++++
 lib/sail.h       |  4 ++++
 src/c_backend.ml | 22 ++++++++++++++++++----
 3 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/lib/sail.c b/lib/sail.c
index b41cacd3..4cb9cdc1 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -134,6 +134,12 @@ void concat_str(sail_string *stro, const sail_string str1, const sail_string str
 
 /* ***** Sail integers ***** */
 
+inline
+bool EQUAL(mach_int)(const mach_int op1, const mach_int op2)
+{
+  return op1 == op2;
+}
+
 #ifndef USE_INT128
 
 inline
@@ -341,6 +347,11 @@ void pow2(sail_int *rop, const sail_int exp) {
 
 /* ***** Sail bitvectors ***** */
 
+bool EQUAL(mach_bits)(const mach_bits op1, const mach_bits op2)
+{
+  return op1 == op2;
+}
+
 void CREATE(sail_bits)(sail_bits *rop)
 {
   rop->bits = malloc(sizeof(mpz_t));
diff --git a/lib/sail.h b/lib/sail.h
index dfff7872..bbdccd09 100644
--- a/lib/sail.h
+++ b/lib/sail.h
@@ -82,6 +82,8 @@ void concat_str(sail_string *stro, const sail_string str1, const sail_string str
 
 typedef int64_t mach_int;
 
+bool EQUAL(mach_int)(const mach_int, const mach_int);
+
 /*
  * Integers can be either stack-allocated as 128-bit integers if
  * __int128 is available, or use GMP arbitrary precision
@@ -165,6 +167,8 @@ typedef uint64_t mach_bits;
 
 bool eq_bit(const mach_bits a, const mach_bits b);
 
+bool EQUAL(mach_bits)(const mach_bits, const mach_bits);
+
 typedef struct {
   mp_bitcnt_t len;
   mpz_t *bits;
diff --git a/src/c_backend.ml b/src/c_backend.ml
index 6097e996..09501ce9 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -2121,10 +2121,7 @@ let codegen_type_def ctx = function
      in
      let codegen_eq =
        let codegen_eq_test (id, ctyp) =
-         if is_stack_ctyp ctyp then
-           string (Printf.sprintf "op1.%s == op2.%s" (sgen_id id) (sgen_id id))
-         else
-           string (Printf.sprintf "EQUAL(%s)(op1.%s, op2.%s)" (sgen_ctyp_name ctyp) (sgen_id id) (sgen_id id))
+         string (Printf.sprintf "EQUAL(%s)(op1.%s, op2.%s)" (sgen_ctyp_name ctyp) (sgen_id id) (sgen_id id))
        in
        string (Printf.sprintf "static bool EQUAL(%s)(struct %s op1, struct %s op2)" (sgen_id id) (sgen_id id) (sgen_id id))
        ^^ space
@@ -2245,6 +2242,21 @@ let codegen_type_def ctx = function
                     ^^ each_ctor "op." set_field tus)
                    rbrace
      in
+     let codegen_eq =
+       let codegen_eq_test ctor_id ctyp =
+         string (Printf.sprintf "return EQUAL(%s)(op1.%s, op2.%s);" (sgen_ctyp_name ctyp) (sgen_id ctor_id) (sgen_id ctor_id))
+       in
+       let rec codegen_eq_tests = function
+         | [] -> string "return false;"
+         | (ctor_id, ctyp) :: ctors ->
+            string (Printf.sprintf "if (op1.kind == Kind_%s && op2.kind == Kind_%s) " (sgen_id ctor_id) (sgen_id ctor_id)) ^^ lbrace ^^ hardline
+            ^^ jump 0 2 (codegen_eq_test ctor_id ctyp)
+            ^^ hardline ^^ rbrace ^^ string " else " ^^ codegen_eq_tests ctors
+       in
+       let n = sgen_id id in
+       string (Printf.sprintf "static bool EQUAL(%s)(struct %s op1, struct %s op2) " n n n)
+       ^^ surround 2 0 lbrace (codegen_eq_tests tus) rbrace
+     in
      string (Printf.sprintf "// union %s" (string_of_id id)) ^^ hardline
      ^^ string "enum" ^^ space
      ^^ string ("kind_" ^ sgen_id id) ^^ space
@@ -2272,6 +2284,8 @@ let codegen_type_def ctx = function
      ^^ twice hardline
      ^^ codegen_setter
      ^^ twice hardline
+     ^^ codegen_eq
+     ^^ twice hardline
      ^^ separate_map (twice hardline) codegen_ctor tus
      (* If this is the exception type, then we setup up some global variables to deal with exceptions. *)
      ^^ if string_of_id id = "exception" then
-- 
cgit v1.2.3


From 26145fc774c859b34c6ca24b339ec2e94255ccc0 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Thu, 5 Jul 2018 14:51:30 -0700
Subject: Fix printing of aq/rl flags in risc-v lr/sc.

---
 riscv/riscv.sail | 38 ++++++++++++++++++++++----------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index d97b99c6..35f3c625 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -889,6 +889,25 @@ function clause print_insn (SFENCE_VMA(rs1, rs2)) =
 
 mapping clause assembly = SFENCE_VMA(rs1, rs2) <-> "sfence.vma" ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
+/* ****************************************************************** */
+// Some print utils for lr/sc.
+
+function aqrl_str(aq : bool, rl : bool) -> string =
+  match (aq, rl) {
+    (false, false) => "",
+    (false, true)  => ".rl",
+    (true, false)  => ".aq",
+    (true, true)   => ".aqrl"
+  }
+
+function lrsc_width_str(width : word_width) -> string =
+  match (width) {
+    BYTE   => ".b",
+    HALF   => ".h",
+    WORD   => ".w",
+    DOUBLE => ".d"
+  }
+
 /* ****************************************************************** */
 union clause ast = LOADRES : (bool, bool, regbits, word_width, regbits)
 
@@ -908,15 +927,9 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) =
       }
   }
 
-/* FIXME */
+
 function clause print_insn (LOADRES(aq, rl, rs1, width, rd)) =
-  let insn : string =
-    match (width) {
-      WORD   => "lr.w  ",
-      DOUBLE => "lr.d  ",
-      _      => "lr.bad "
-    } in
-  insn ^ rd ^ ", " ^ rs1
+  "lr" ^ lrsc_width_str(width) ^ aqrl_str(aq, rl) ^ " " ^ rd ^ ", " ^ rs1
 
 mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) <-> "lr." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)
 
@@ -961,15 +974,8 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
   }
 }
 
-/* FIXME */
 function clause print_insn (STORECON(aq, rl, rs2, rs1, width, rd)) =
-  let insn : string =
-    match (width) {
-      WORD   => "sc.w  ",
-      DOUBLE => "sc.d  ",
-      _      => "sc.bad "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
+  "sc" ^ lrsc_width_str(width) ^ aqrl_str(aq, rl) ^ " " ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
-- 
cgit v1.2.3


From 80d281efffabc4d3dc4a759764ab8d785af10511 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Fri, 6 Jul 2018 15:05:53 +0100
Subject: changes to increase MIPS coverage -- remove optional/unused PREF
 instruction and unused cases in ll/sc match

---
 mips/mips_insts.sail | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail
index 3e3f4c39..63c380de 100644
--- a/mips/mips_insts.sail
+++ b/mips/mips_insts.sail
@@ -1124,10 +1124,9 @@ function clause execute (Load(width, sign, linked, base, rt, offset)) =
                   CP0LLBit  = 0b1;
                   CP0LLAddr = pAddr;
                   match width {
-                   B => extendLoad(MEMr_reserve_wrapper(pAddr, 1), sign),
-                   H => extendLoad(MEMr_reserve_wrapper(pAddr, 2), sign),
                    W => extendLoad(MEMr_reserve_wrapper(pAddr, 4), sign),
-                   D => extendLoad(MEMr_reserve_wrapper(pAddr, 8), sign)
+                   D => extendLoad(MEMr_reserve_wrapper(pAddr, 8), sign),
+                   _ => throw(Error_internal_error()) /* there is no llbc or llhc */
                   }
                 }
               else
@@ -1173,10 +1172,9 @@ function clause execute (Store(width, conditional, base, rt, offset)) =
                   {
 		    success : bool = if (CP0LLBit[0]) then match width
                     {
-                      B  => MEMw_conditional_wrapper(pAddr, 1, rt_val[7..0]),
-                      H  => MEMw_conditional_wrapper(pAddr, 2, rt_val[15..0]),
                       W  => MEMw_conditional_wrapper(pAddr, 4, rt_val[31..0]),
-                      D  => MEMw_conditional_wrapper(pAddr, 8, rt_val)
+                      D  => MEMw_conditional_wrapper(pAddr, 8, rt_val),
+                      _  => throw(Error_internal_error()) /* there is no sbc or shc */
                     } else false;
 		    wGPR(rt) = zero_extend(success)
                   }
@@ -1382,7 +1380,7 @@ function clause decode (0b101111 @ base : regno @ op : regno @ imm : imm16) =
 function clause execute (CACHE(base, op, imm)) =
   checkCP0Access () /* pretty much a NOP because no caches */
 
-/* PREF - prefetching into (non-existent) caches */
+/* PREF - prefetching into (non-existent) caches 
 
 union clause ast = PREF : (regno, regno, bits(16))
 function clause decode (0b110011 @ base : regno @ op : regno @ imm : imm16) =
@@ -1390,6 +1388,7 @@ function clause decode (0b110011 @ base : regno @ op : regno @ imm : imm16) =
 function clause execute (PREF(base, op, imm)) =
   () /* XXX NOP */
 
+*/
 
 /* SYNC  - Memory barrier */
 union clause ast = SYNC : unit
-- 
cgit v1.2.3


From 2593b91c60fff908493ebc7924edb480a0c1b3f6 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Fri, 6 Jul 2018 15:33:27 +0100
Subject: add gcov option for cheri_c. Add cheri128_c target.

---
 cheri/Makefile | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/cheri/Makefile b/cheri/Makefile
index 419fa4e1..f3a0b7e7 100644
--- a/cheri/Makefile
+++ b/cheri/Makefile
@@ -38,8 +38,18 @@ coverage_report: bisect*.out
 cheri.c: $(CHERI_SAILS) $(CHERI_MAIN)
 	$(SAIL) -memo_z3 -O -c $^ 1> $@
 
+C_OPT=-O2
+GCOV_FLAGS=
 cheri_c: cheri.c ../lib/sail.h Makefile
-	gcc -O2 $< ../lib/*.c -lgmp -lz -I ../lib/ -o $@
+	gcc $(C_OPT) $(GCOV_FLAGS) $< ../lib/*.c -lgmp -lz -I ../lib/ -o $@
+
+# Note that for coverage purposes O1 appears optimal. O0 means lots of obviously dead code but O2 risks reducing granularity too much.
+cheri_c_gcov: C_OPT=-O1
+cheri_c_gcov: GCOV_FLAGS=-fprofile-arcs -ftest-coverage
+cheri_c_gcov: cheri_c
+
+gcovr:
+	gcovr -r . --html --html-detail -o index.html
 
 latex_128: $(MIPS_SAIL_DIR)/prelude.sail $(CHERI_SAIL_DIR)/cheri_types.sail $(CHERI_SAIL_DIR)/cheri_prelude_128.sail
 	rm -rf sail_latexcc
@@ -57,6 +67,17 @@ cheri128: $(CHERI128_SAILS) $(CHERI_MAIN)
 cheri128_trace: $(CHERI128_SAILS) $(CHERI_MAIN)
 	$(SAIL) -ocaml_trace -o $@ $^
 
+cheri128.c: $(CHERI128_SAILS) $(CHERI_MAIN)
+	$(SAIL) -memo_z3 -O -c $^ 1> $@
+
+cheri128_c: cheri128.c ../lib/sail.h Makefile
+	gcc $(C_OPT) $(GCOV_FLAGS) $< ../lib/*.c -lgmp -lz -I ../lib/ -o $@
+
+# Note that for coverage purposes O1 appears optimal. O0 means lots of obviously dead code but O2 risks reducing granularity too much.
+cheri128_c_gcov: C_OPT=-O1
+cheri128_c_gcov: GCOV_FLAGS=-fprofile-arcs -ftest-coverage
+cheri128_c_gcov: cheri128_c
+
 LOC_FILES:=$(CHERI_SAILS) $(CHERI_MAIN)
 include ../etc/loc.mk
 
-- 
cgit v1.2.3


From 626f81f2dd15cf26584ee0a723cbea63a094f763 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Fri, 6 Jul 2018 16:34:36 +0100
Subject: Change HighestSetBit into a form that can be handled by c backend.
 There are still a few builtins missing before cheri128 will work.

---
 cheri/cheri_prelude_128.sail | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/cheri/cheri_prelude_128.sail b/cheri/cheri_prelude_128.sail
index 263dae43..da761c91 100644
--- a/cheri/cheri_prelude_128.sail
+++ b/cheri/cheri_prelude_128.sail
@@ -291,11 +291,11 @@ function incCapOffset(c, delta) : (CapStruct, bits(64)) -> (bool, CapStruct) =
 
 /** FUNCTION:integer HighestSetBit(bits(N) x) */
 
-val HighestSetBit : forall 'N , 'N >= 2. bits('N) -> {'n, 0 <= 'n < 'N . option(atom('n))}
+val HighestSetBit : forall 'N , 'N >= 2. bits('N) -> {'n, 0 <= 'n < 'N . (bool, atom('n))}
 function HighestSetBit x = {
   foreach (i from ('N - 1) to 0 by 1 in dec)
-    if [x[i]] == 0b1 then return Some(i);
-  return None() : option(atom(0))
+    if [x[i]] == 0b1 then return (true, i);
+  return (false, 0)
 }
 
 /* hw rounds up E to multiple of 4 */
@@ -306,12 +306,12 @@ function roundUp(e) : range(0, 45) -> range(0, 48) =
     else (e - r + 4)
 
 function computeE (rlength) : bits(65) -> range(0, 48) =
-    let 'msb = HighestSetBit((rlength + (rlength >> 6)) >> 19) in
-    match msb {
-      None()   => 0,
+    let (nonzero, 'msb) = HighestSetBit((rlength + (rlength >> 6)) >> 19) in
+    if nonzero then 
       /* above will always return <= 45 because 19 bits of zero are shifted in from right */
-      Some('b) => {assert(0 <= b & b <= 45); roundUp (min(b,45)) }
-      }
+      {assert(0 <= msb & msb <= 45); roundUp (min(msb,45)) }
+    else 
+      0
 
 function setCapBounds(cap, base, top) : (CapStruct, bits(64), bits(65)) -> (bool, CapStruct) =
     /* {cap with base=base; length=(bits(64)) length; offset=0} */
-- 
cgit v1.2.3


From d2ddaad22f25a152d5fd53c11b3e1698747bd9c5 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Wed, 4 Jul 2018 11:43:06 +0100
Subject: Coq: turn off partial support for dropping true constraints, fix
 strings

---
 src/pretty_print_coq.ml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 78507577..6df8c5df 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -424,7 +424,7 @@ let doc_typ, doc_atomic_typ =
            List.fold_left add_tyvar tpp kids
         | None ->
            match nc with
-           | NC_aux (NC_true,_) -> List.fold_left add_tyvar (string "Z") (List.tl kids)
+(*           | NC_aux (NC_true,_) -> List.fold_left add_tyvar (string "Z") (List.tl kids)*)
            | _ -> List.fold_left add_tyvar (doc_arithfact ctx nc) kids
       end
     and doc_typ_arg (Typ_arg_aux(t,_)) = match t with
@@ -1839,6 +1839,8 @@ try
           (fun lib -> separate space [string "Require Import";string lib] ^^ dot) defs_modules;hardline;
         string "Import ListNotations.";
         hardline;
+        string "Open Scope string.";
+        hardline;
         (* Put the body into a Section so that we can define some values with
            Let to put them into the local context, where tactics can see them *)
         string "Section Content.";
-- 
cgit v1.2.3


From e4c43d45c6fe5267ad72a1be64d6328470f2a18e Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 5 Jul 2018 17:02:03 +0100
Subject: Coq: missing existential building for ranges

---
 src/pretty_print_coq.ml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 6df8c5df..5f4d349c 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -946,6 +946,9 @@ let doc_exp_lem, doc_let_lem =
               (* TODO: more sophisticated check *)
               match destruct_exist env arg_ty, destruct_exist env typ_from_fn with
               | Some _, None -> parens (string "projT1 " ^^ arg_pp)
+              (* Usually existentials have already been built elsewhere, but this
+                 is useful for (e.g.) ranges *)
+              | None, Some _ -> parens (string "build_ex " ^^ arg_pp)
               | _, _ -> arg_pp
             in
             let epp = hang 2 (flow (break 1) (call :: List.map2 doc_arg args arg_typs)) in
-- 
cgit v1.2.3


From cd3a1f9a5ac8c7e64489a1d92dc4dea595ed8a2b Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 6 Jul 2018 10:14:51 +0100
Subject: Coq: reduce use of sumbool_of_bool to relevant constraints

---
 src/pretty_print_coq.ml | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 5f4d349c..dc0b5036 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -708,6 +708,21 @@ let similar_nexps n1 n2 =
     | _ -> false
   in if same_nexp_shape n1 n2 then true else false
 
+let constraint_fns = ["Z.leb"; "Z.geb"; "Z.ltb"; "Z.gtb"; "Z.eqb"]
+
+let condition_produces_constraint exp =
+  (* Cheat a little - this isn't quite the right environment for subexpressions
+     but will have all of the relevant functions in it. *)
+  let env = env_of exp in
+  Rewriter.fold_exp
+    { (Rewriter.pure_exp_alg false (||)) with
+      Rewriter.e_app = fun (f,bs) ->
+        List.exists (fun x -> x) bs ||
+        (Env.is_extern f env "coq" &&
+           let f' = Env.get_extern f env "coq" in
+           List.exists (fun id -> String.compare f' id == 0) constraint_fns)
+    } exp
+
 let prefix_recordtype = true
 let report = Reporting_basic.err_unreachable
 let doc_exp_lem, doc_let_lem =
@@ -1191,7 +1206,9 @@ let doc_exp_lem, doc_let_lem =
       | _ -> prefix 2 1 (string "else") (top_exp ctxt false e)
     in
     (prefix 2 1
-      (soft_surround 2 1 if_pp (string "sumbool_of_bool" ^^ space ^^ parens (top_exp ctxt true c)) (string "then"))
+      (soft_surround 2 1 if_pp
+         ((if condition_produces_constraint c then string "sumbool_of_bool" ^^ space else empty)
+          ^^ parens (top_exp ctxt true c)) (string "then"))
       (top_exp ctxt false t)) ^^
     break 1 ^^
     else_pp
-- 
cgit v1.2.3


From 2c47d06c669ab303666da861824bf2cdae683c06 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 6 Jul 2018 16:29:02 +0100
Subject: Coq: use List.In predicates in constraint solving; make other bits
 robust

---
 lib/coq/Sail2_values.v | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 0fdaa7aa..990817e6 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -848,6 +848,20 @@ Class ReasonableSize (a : Z) : Prop := {
 Hint Resolve -> Z.gtb_lt Z.geb_le Z.ltb_lt Z.leb_le : zbool.
 Hint Resolve <- Z.ge_le_iff Z.gt_lt_iff : zbool.
 
+(* Omega doesn't know about In, but can handle disjunctions. *)
+Ltac unfold_In :=
+repeat match goal with
+| H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H
+| H:context [In ?x []] |- _ => change (In x []) with False in H
+end.
+
+(* Definitions in the context that involve proof for other constraints can
+   break some of the constraint solving tactics, so prune definition bodies
+   down to integer types. *)
+Ltac not_Z ty := match ty with Z => fail 1 | _ => idtac end.
+Ltac clear_non_Z_defns := 
+  repeat match goal with H := _ : ?X |- _ => not_Z X; clearbody H end.
+
 Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0).
 constructor.
 destruct a.
@@ -856,7 +870,7 @@ auto using Z.le_ge, Zle_0_pos.
 destruct w.
 Qed.
 Ltac unwrap_ArithFacts :=
-  repeat match goal with H:(ArithFact _) |- _ => apply use_ArithFact in H end.
+  repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H'] end.
 Ltac unbool_comparisons :=
   repeat match goal with
   | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H
@@ -901,14 +915,23 @@ Ltac reduce_pow :=
     let r := (eval cbn in (Z.pow X Y)) in
     change (Z.pow X Y) with r
   end.
+Ltac dump_context :=
+  repeat match goal with
+  | H:=?X |- _ => idtac H ":=" X; fail
+  | H:?X |- _ => idtac H ":" X; fail end;
+  match goal with |- ?X => idtac "Goal:" X end.
 Ltac solve_arithfact :=
+(*dump_context;*)
+ clear_non_Z_defns;
  extract_properties;
  repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end;
  unwrap_ArithFacts;
+ unfold_In;
  autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *)
  unbool_comparisons;
  reduce_list_lengths;
  reduce_pow;
+(*dump_context;*)
  solve [apply ArithFact_mword; assumption
        | constructor; omega with Z
          (* The datatypes hints give us some list handling, esp In *)
-- 
cgit v1.2.3


From f1f3c68878406ae5029881e20b839d2b6f535280 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 6 Jul 2018 17:00:05 +0100
Subject: Coq: feed assertions into the context

---
 src/pretty_print_coq.ml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index dc0b5036..9cc85601 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1149,7 +1149,7 @@ let doc_exp_lem, doc_let_lem =
        if aexp_needed then parens (align epp) else align epp
     | E_exit e -> liftR (separate space [string "exit"; expY e])
     | E_assert (e1,e2) ->
-       let epp = liftR (separate space [string "assert_exp"; expY e1; expY e2]) in
+       let epp = liftR (separate space [string "assert_exp'"; expY e1; expY e2]) in
        if aexp_needed then parens (align epp) else align epp
     | E_app_infix (e1,id,e2) ->
        raise (Reporting_basic.err_unreachable l
@@ -1161,6 +1161,9 @@ let doc_exp_lem, doc_let_lem =
          let b = match e1 with E_aux (E_if _,_) -> true | _ -> false in
          let middle =
            match fst (untyp_pat pat) with
+           | P_aux (P_wild,_) | P_aux (P_typ (_, P_aux (P_wild, _)), _)
+             when (match e1 with E_aux (E_assert _,_) -> true | _ -> false) ->
+              string ">>= fun _ =>"
            | P_aux (P_wild,_) | P_aux (P_typ (_, P_aux (P_wild, _)), _) ->
               string ">>"
            | P_aux (P_id id,_) ->
-- 
cgit v1.2.3


From a41ca0c0ed6acdb17362886c4c9650c4c353afef Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 6 Jul 2018 17:36:33 +0100
Subject: Coq: Avoid clashes with the monad name, M

---
 src/pretty_print_coq.ml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 9cc85601..1eb62193 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -136,6 +136,7 @@ let rec fix_id remove_tick name = match name with
   | "EQ"
   | "Z"
   | "mod"
+  | "M"
     -> name ^ "'"
   | _ ->
      if String.contains name '#' then
@@ -146,7 +147,7 @@ let rec fix_id remove_tick name = match name with
        fix_id remove_tick (String.concat "__" (Util.split_on_char '^' name))
      else if name.[0] = '\'' then
        let var = String.sub name 1 (String.length name - 1) in
-       if remove_tick then var else (var ^ "'")
+       if remove_tick then fix_id remove_tick var else (var ^ "'")
      else if is_number_char(name.[0]) then
        ("v" ^ name ^ "'")
      else name
-- 
cgit v1.2.3


From 3c5d11d7536c1f0f1d3c899b5daac7e35f1f369a Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 6 Jul 2018 18:26:41 +0100
Subject: Coq: avoid nexp simplification when deciding whether a cast is needed

---
 src/pretty_print_coq.ml | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 1eb62193..a85e8782 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -987,9 +987,11 @@ let doc_exp_lem, doc_let_lem =
                 | t1, t2 -> false,false,t1,t2
               in
               let autocast =
-                match destruct_vector env in_typ, destruct_vector env out_typ with
-                | Some (n1,_,t1), Some (n2,_,t2) 
-                  when is_bit_typ t1 && is_bit_typ t2 ->
+                (* Avoid using helper functions which simplify the nexps *)
+                is_bitvector_typ in_typ && is_bitvector_typ out_typ &&
+                match in_typ, out_typ with
+                | Typ_aux (Typ_app (_,[Typ_arg_aux (Typ_arg_nexp n1,_);_;_]),_),
+                  Typ_aux (Typ_app (_,[Typ_arg_aux (Typ_arg_nexp n2,_);_;_]),_) ->
                    not (similar_nexps n1 n2)
                 | _ -> false
               in unpack,build_ex,autocast
-- 
cgit v1.2.3


From 7c36a2c621ce64e3a181bf72f7b0434f42450092 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 6 Jul 2018 21:28:35 +0100
Subject: Coq: support assertions inside and outside of blocks

---
 src/pretty_print_coq.ml | 46 ++++++++++++++++++++++++++--------------------
 1 file changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index a85e8782..7d8d0e5a 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1152,7 +1152,7 @@ let doc_exp_lem, doc_let_lem =
        if aexp_needed then parens (align epp) else align epp
     | E_exit e -> liftR (separate space [string "exit"; expY e])
     | E_assert (e1,e2) ->
-       let epp = liftR (separate space [string "assert_exp'"; expY e1; expY e2]) in
+       let epp = liftR (separate space [string "assert_exp"; expY e1; expY e2]) in
        if aexp_needed then parens (align epp) else align epp
     | E_app_infix (e1,id,e2) ->
        raise (Reporting_basic.err_unreachable l
@@ -1160,25 +1160,31 @@ let doc_exp_lem, doc_let_lem =
     | E_var(lexp, eq_exp, in_exp) ->
        raise (report l "E_vars should have been removed before pretty-printing")
     | E_internal_plet (pat,e1,e2) ->
-       let epp =
-         let b = match e1 with E_aux (E_if _,_) -> true | _ -> false in
-         let middle =
-           match fst (untyp_pat pat) with
-           | P_aux (P_wild,_) | P_aux (P_typ (_, P_aux (P_wild, _)), _)
-             when (match e1 with E_aux (E_assert _,_) -> true | _ -> false) ->
-              string ">>= fun _ =>"
-           | P_aux (P_wild,_) | P_aux (P_typ (_, P_aux (P_wild, _)), _) ->
-              string ">>"
-           | P_aux (P_id id,_) ->
-              separate space [string ">>= fun"; doc_id id; bigarrow]
-           | P_aux (P_typ (typ, P_aux (P_id id,_)),_) ->
-              separate space [string ">>= fun"; doc_id id; colon; doc_typ ctxt typ; bigarrow]
-           | _ ->
-              separate space [string ">>= fun"; squote ^^ doc_pat ctxt true (pat, typ_of e1); bigarrow]
-         in
-         infix 0 1 middle (expV b e1) (expN e2)
-       in
-       if aexp_needed then parens (align epp) else epp
+       begin
+         match pat, e1 with
+         | (P_aux (P_wild,_) | P_aux (P_typ (_, P_aux (P_wild, _)), _)),
+           (E_aux (E_assert (assert_e1,assert_e2),_)) ->
+            let epp = liftR (separate space [string "assert_exp'"; expY assert_e1; expY assert_e2]) in
+            let epp = infix 0 1 (string ">>= fun _ =>") epp (expN e2) in
+            if aexp_needed then parens (align epp) else align epp
+         | _ ->
+            let epp =
+              let b = match e1 with E_aux (E_if _,_) -> true | _ -> false in
+              let middle =
+                match fst (untyp_pat pat) with
+                | P_aux (P_wild,_) | P_aux (P_typ (_, P_aux (P_wild, _)), _) ->
+                   string ">>"
+                | P_aux (P_id id,_) ->
+                   separate space [string ">>= fun"; doc_id id; bigarrow]
+                | P_aux (P_typ (typ, P_aux (P_id id,_)),_) ->
+                   separate space [string ">>= fun"; doc_id id; colon; doc_typ ctxt typ; bigarrow]
+                | _ ->
+                   separate space [string ">>= fun"; squote ^^ doc_pat ctxt true (pat, typ_of e1); bigarrow]
+              in
+              infix 0 1 middle (expV b e1) (expN e2)
+            in
+            if aexp_needed then parens (align epp) else epp
+       end
     | E_internal_return (e1) ->
        wrap_parens (align (separate space [string "returnm"; expY e1]))
     | E_sizeof nexp ->
-- 
cgit v1.2.3


From 2a2f38f46735a81a921891bf0bf9e35a7cc4a347 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Sat, 7 Jul 2018 15:17:20 +0100
Subject: Coq: eq_range should take proofs

---
 lib/coq/Sail2_values.v | 2 ++
 lib/flow.sail          | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 990817e6..db0339d8 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -1368,6 +1368,8 @@ Definition abs_with_eq n   : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.ab
 
 (* Similarly, for ranges (currently in MIPS) *)
 
+Definition eq_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) : bool :=
+  (projT1 l) =? (projT1 r).
 Definition add_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
   : {x & ArithFact (n+o <= x <= m+p)} :=
   build_ex ((projT1 l) + (projT1 r)).
diff --git a/lib/flow.sail b/lib/flow.sail
index c4ffd75a..304f14bc 100644
--- a/lib/flow.sail
+++ b/lib/flow.sail
@@ -27,7 +27,7 @@ val lteq_atom_range = {coq: "leb_range_r", _: "lteq"} : forall 'n 'm 'o. (atom('
 val gt_atom_range = {coq: "gtb_range_r", _: "gt"}     : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool
 val gteq_atom_range = {coq: "geb_range_r", _: "gteq"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool
 
-val eq_range = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool
+val eq_range = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "eq_range"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool
 val eq_int = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : (int, int) -> bool
 val eq_bool = {ocaml: "eq_bool", lem: "eq", c: "eq_bool", coq: "Bool.eqb"} : (bool, bool) -> bool
 
-- 
cgit v1.2.3


From a7e3bad39b771cb18b989da05528e6e6f2788147 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Sat, 7 Jul 2018 16:34:42 +0100
Subject: Coq: supply index constraint in for loops

---
 lib/coq/Sail2_prompt.v  | 21 +++++++++++++++++++++
 src/pretty_print_coq.ml | 24 +++++++++++++-----------
 2 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/lib/coq/Sail2_prompt.v b/lib/coq/Sail2_prompt.v
index 336ca8de..6448e81b 100644
--- a/lib/coq/Sail2_prompt.v
+++ b/lib/coq/Sail2_prompt.v
@@ -30,6 +30,27 @@ match l with
   foreachM xs vars body
 end.
 
+Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+  if sumbool_of_bool (from + off <=? to) then
+    match n with
+    | O => returnm vars
+    | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_up' from to step (off + step) n vars body
+    end
+  else returnm vars.
+
+Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+  if sumbool_of_bool (to <=? from + off) then
+    match n with
+    | O => returnm vars
+    | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_down' from to step (off - step) n vars body
+    end
+  else returnm vars.
+
+Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+    foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+    foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
 (*declare {isabelle} termination_argument foreachM = automatic*)
 
 (*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 7d8d0e5a..38395b07 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -831,7 +831,7 @@ let doc_exp_lem, doc_let_lem =
        | Id_aux (Id "foreach", _) ->
           begin
             match args with
-            | [exp1; exp2; exp3; ord_exp; vartuple; body] ->
+            | [from_exp; to_exp; step_exp; ord_exp; vartuple; body] ->
                let loopvar, body = match body with
                  | E_aux (E_let (LB_aux (LB_val (_, _), _),
                    E_aux (E_let (LB_aux (LB_val (_, _), _),
@@ -842,13 +842,13 @@ let doc_exp_lem, doc_let_lem =
                      | (P_aux (P_id id, _))), _), _),
                      body), _), _), _)), _)), _) -> id, body
                  | _ -> raise (Reporting_basic.err_unreachable l ("Unable to find loop variable in " ^ string_of_exp body)) in
-               let step = match ord_exp with
-                 | E_aux (E_lit (L_aux (L_false, _)), _) ->
-                    parens (separate space [string "integerNegate"; expY exp3])
-                 | _ -> expY exp3
+               let dir = match ord_exp with
+                 | E_aux (E_lit (L_aux (L_false, _)), _) -> "_down"
+                 | E_aux (E_lit (L_aux (L_true, _)), _) -> "_up"
+                 | _ -> raise (Reporting_basic.err_unreachable l ("Unexpected loop direction " ^ string_of_exp ord_exp))
                in
-               let combinator = if effectful (effect_of body) then "foreachM" else "foreach" in
-               let indices_pp = parens (separate space [string "index_list"; expY exp1; expY exp2; step]) in
+               let combinator = if effectful (effect_of body) then "foreach_ZM" else "foreach_Z" in
+               let combinator = combinator ^ dir in
                let used_vars_body = find_e_ids body in
                let body_lambda =
                  (* Work around indentation issues in Lem when translating
@@ -856,18 +856,20 @@ let doc_exp_lem, doc_let_lem =
                  match fst (uncast_exp vartuple) with
                    | E_aux (E_tuple _, _)
                      when not (IdSet.mem (mk_id "varstup") used_vars_body)->
-                      separate space [string "fun"; doc_id loopvar; string "varstup"; bigarrow]
+                      separate space [string "fun"; doc_id loopvar; string "_"; string "varstup"; bigarrow]
                       ^^ break 1 ^^
                       separate space [string "let"; expY vartuple; string ":= varstup in"]
                    | E_aux (E_lit (L_aux (L_unit, _)), _)
                      when not (IdSet.mem (mk_id "unit_var") used_vars_body) ->
-                      separate space [string "fun"; doc_id loopvar; string "unit_var"; bigarrow]
+                      separate space [string "fun"; doc_id loopvar; string "_"; string "unit_var"; bigarrow]
                    | _ ->
-                      separate space [string "fun"; doc_id loopvar; expY vartuple; bigarrow]
+                      separate space [string "fun"; doc_id loopvar; string "_"; expY vartuple; bigarrow]
                in
                parens (
                    (prefix 2 1)
-                     ((separate space) [string combinator; indices_pp; expY vartuple])
+                     ((separate space) [string combinator;
+                                        expY from_exp; expY to_exp; expY step_exp;
+                                        expY vartuple])
                      (parens
                         (prefix 2 1 (group body_lambda) (expN body))
                      )
-- 
cgit v1.2.3


From 979d88fec8a5c611ee61be15ce45ae81b4a52317 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Sat, 7 Jul 2018 16:36:04 +0100
Subject: Coq: precise generic vectors (probably still some pattern matching to
 do, but I don't think the models use that)

---
 lib/coq/Sail2_values.v  | 187 +++++++++++++++++++++++++++++++++++++++++++++++-
 lib/vector_dec.sail     |   6 +-
 mips/mips_extras.v      |   2 +-
 src/pretty_print_coq.ml |   6 +-
 src/state.ml            |   8 +--
 5 files changed, 197 insertions(+), 12 deletions(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index db0339d8..ee193865 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -124,9 +124,29 @@ Fixpoint repeat' {a} (xs : list a) n :=
   | O => []
   | S n => xs ++ repeat' xs n
   end.
+Lemma repeat'_length {a} {xs : list a} {n : nat} : List.length (repeat' xs n) = (n * List.length xs)%nat.
+induction n.
+* reflexivity.
+* simpl.
+  rewrite app_length.
+  auto with arith.
+Qed.
 Definition repeat {a} (xs : list a) (n : Z) :=
   if n <=? 0 then []
   else repeat' xs (Z.to_nat n).
+Lemma repeat_length {a} {xs : list a} {n : Z} (H : n >= 0) : length_list (repeat xs n) = n * length_list xs.
+unfold length_list, repeat.
+destruct n.
++ reflexivity. 
++ simpl (List.length _).
+  rewrite repeat'_length.
+  rewrite Nat2Z.inj_mul.
+  rewrite positive_nat_Z.
+  reflexivity.  
++ exfalso.
+  auto with zarith.
+Qed.
+
 (*declare {isabelle} termination_argument repeat = automatic
 
 Definition duplicate_to_list bit length := repeat [bit] length
@@ -187,6 +207,32 @@ lemma just_list_spec:
   ((forall xs. (just_list xs = None) <-> List.elem None xs) &&
    (forall xs es. (just_list xs = Some es) <-> (xs = List.map Some es)))*)
 
+Lemma just_list_length {A} : forall (l : list (option A)) (l' : list A),
+  Some l' = just_list l -> List.length l = List.length l'.
+induction l.
+* intros.
+  simpl in H.
+  inversion H.
+  reflexivity.
+* intros.
+  destruct a; simplify_eq H.
+  simpl in *.
+  destruct (just_list l); simplify_eq H.
+  intros.
+  subst.
+  simpl.
+  f_equal.
+  apply IHl.
+  reflexivity.
+Qed.
+
+Lemma just_list_length_Z {A} : forall (l : list (option A)) l', Some l' = just_list l -> length_list l = length_list l'.
+unfold length_list.
+intros.
+f_equal.
+auto using just_list_length.
+Qed.
+
 (*** Bits *)
 Inductive bitU := B0 | B1 | BU.
 
@@ -641,10 +687,10 @@ Definition update_list {A} (is_inc : bool) (xs : list A) n x :=
   | [] => failwith "extract_only_element called for empty list"
   | [e] => e
   | _ => failwith "extract_only_element called for list with more elements"
-end
+end*)
 
 (*** Machine words *)
-*)
+
 Definition mword (n : Z) :=
   match n with
   | Zneg _ => False
@@ -1272,6 +1318,38 @@ Definition index_list from to step :=
     index_list' from to step (S (Z.abs_nat (from - to)))
   else [].
 
+Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Vars) : Vars :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    match n with
+    | O => vars
+    | S n => let vars := body from vars in foreach_Z' (from + step) to step n vars body
+    end
+  else vars.
+
+Definition foreach_Z {Vars} from to step vars body :=
+  foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body.
+
+Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars :=
+  if sumbool_of_bool (from + off <=? to) then
+    match n with
+    | O => vars
+    | S n => let vars := body (from + off) _ vars in foreach_Z_up' from to step (off + step) n vars body
+    end
+  else vars.
+
+Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars :=
+  if sumbool_of_bool (to <=? from + off) then
+    match n with
+    | O => vars
+    | S n => let vars := body (from + off) _ vars in foreach_Z_down' from to step (off - step) n vars body
+    end
+  else vars.
+
+Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+    foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+    foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
 (*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
 Fixpoint while vars cond body :=
   if cond vars then while (body vars) cond body else vars
@@ -1385,3 +1463,108 @@ Definition min_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c <=
 Definition max_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c >= a /\ c >= b)} :=
   build_ex (Z.max a b).
 
+
+(*** Generic vectors *)
+
+Definition vec (T:Type) (n:Z) := { l : list T & length_list l = n }.
+Definition vec_length {T n} (v : vec T n) := n.
+Definition vec_access_dec {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+  access_list_dec (projT1 v) m.
+Definition vec_access_inc {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+  access_list_inc (projT1 v) m.
+
+Program Definition vec_init {T} (t : T) (n : Z) `{ArithFact (n >= 0)} : vec T n :=
+  existT _ (repeat [t] n) _.
+Next Obligation.
+rewrite repeat_length; auto using fact.
+unfold length_list.
+simpl.
+auto with zarith.
+Qed.
+
+Lemma skipn_length {A n} {l: list A} : (n <= List.length l -> List.length (skipn n l) = List.length l - n)%nat.
+revert l.
+induction n.
+* simpl. auto with arith.
+* intros l H.
+  destruct l.
+  + inversion H.
+  + simpl in H.
+    simpl.
+    rewrite IHn; auto with arith.
+Qed.
+Lemma update_list_inc_length {T} {l:list T} {m x} : 0 <= m < length_list l -> length_list (update_list_inc l m x) = length_list l.
+unfold update_list_inc, list_update, length_list.
+intro H.
+f_equal.
+assert ((0 <= Z.to_nat m < Datatypes.length l)%nat).
+{ destruct H as [H1 H2].
+  split.
+  + change 0%nat with (Z.to_nat 0).
+    apply Z2Nat.inj_le; auto with zarith.
+  + rewrite <- Nat2Z.id.
+    apply Z2Nat.inj_lt; auto with zarith.
+}
+rewrite app_length.
+rewrite firstn_length_le; only 2:omega.
+cbn -[skipn].
+rewrite skipn_length;
+omega.
+Qed.
+
+Program Definition vec_update_dec {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_dec (projT1 v) m t) _.
+Next Obligation.
+unfold update_list_dec.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+  destruct v. simpl (projT1 _). rewrite e.
+  omega.
+Qed.
+
+Program Definition vec_update_inc {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_inc (projT1 v) m t) _.
+Next Obligation.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+  destruct v. simpl (projT1 _). rewrite e.
+  omega.
+Qed.
+
+Program Definition vec_map {S T} (f : S -> T) {n} (v : vec S n) : vec T n := existT _ (List.map f (projT1 v)) _.
+Next Obligation.
+destruct v as [l H].
+cbn.
+unfold length_list.
+rewrite map_length.
+apply H.
+Qed.
+
+Program Definition just_vec {A n} (v : vec (option A) n) : option (vec A n) :=
+  match just_list (projT1 v) with
+  | None => None
+  | Some v' => Some (existT _ v' _)
+  end.
+Next Obligation.
+rewrite <- (just_list_length_Z _ _ Heq_anonymous).
+destruct v.
+assumption.
+Qed.
+
+Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v.
+
+Program Definition vec_of_list {A} n (l : list A) : option (vec A n) :=
+  if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None.
+Next Obligation.
+symmetry.
+apply Z.eqb_eq.
+assumption.
+Qed.
+
+Definition vec_of_list_len {A} (l : list A) : vec A (length_list l) := existT _ l (eq_refl _).
+
+Definition map_bind {A B} (f : A -> option B) (a : option A) : option B :=
+match a with
+| Some a' => f a'
+| None => None
+end.
\ No newline at end of file
diff --git a/lib/vector_dec.sail b/lib/vector_dec.sail
index 86bbe601..8abcd218 100644
--- a/lib/vector_dec.sail
+++ b/lib/vector_dec.sail
@@ -22,7 +22,7 @@ val vector_length = {
   ocaml: "length",
   lem: "length_list",
   c: "length",
-  coq: "length_list"
+  coq: "vec_length"
 } : forall 'n ('a : Type). vector('n, dec, 'a) -> atom('n)
 
 overload length = {bitvector_length, vector_length}
@@ -68,7 +68,7 @@ val bitvector_access = {
 val plain_vector_access = {
   ocaml: "access",
   lem: "access_list_dec",
-  coq: "access_list_dec",
+  coq: "vec_access_dec",
   c: "vector_access"
 } : forall ('n : Int) ('m : Int) ('a : Type), 0 <= 'm < 'n. (vector('n, dec, 'a), atom('m)) -> 'a
 
@@ -84,7 +84,7 @@ val bitvector_update = {
 val plain_vector_update = {
   ocaml: "update",
   lem: "update_list_dec",
-  coq: "update_list_dec",
+  coq: "vec_update_dec",
   c: "vector_update"
 } : forall 'n ('a : Type). (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a)
 
diff --git a/mips/mips_extras.v b/mips/mips_extras.v
index 49899107..cc905f11 100644
--- a/mips/mips_extras.v
+++ b/mips/mips_extras.v
@@ -107,7 +107,7 @@ Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%st
 Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
 Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
 (*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
-Definition undefined_vector {rv a e} len (u : a) : monad rv (list a) e := returnm (repeat u len).
+Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len).
 (*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
 Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
 (*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 38395b07..e68a6dd9 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -382,7 +382,7 @@ let doc_typ, doc_atomic_typ =
          let tpp = match elem_typ with
            | Typ_aux (Typ_id (Id_aux (Id "bit",_)),_) ->
              string "mword " ^^ doc_nexp ctx (nexp_simp m)
-           | _ -> string "list" ^^ space ^^ typ elem_typ in
+           | _ -> string "vec" ^^ space ^^ typ elem_typ ^^ space ^^ doc_nexp ctx (nexp_simp m) in
          if atyp_needed then parens tpp else tpp
       | Typ_app(Id_aux (Id "register", _), [Typ_arg_aux (Typ_arg_typ etyp, _)]) ->
          let tpp = string "register_ref regstate register_value " ^^ typ etyp in
@@ -1122,7 +1122,9 @@ let doc_exp_lem, doc_let_lem =
          if is_bit_typ etyp then
            let bepp = string "vec_of_bits" ^^ space ^^ align epp in
            (align (group (prefix 0 1 bepp (doc_tannot_lem ctxt (env_of full_exp) false t))), true)
-         else (epp,aexp_needed) in
+         else
+           let vepp = string "vec_of_list_len" ^^ space ^^ align epp in
+           (vepp,aexp_needed) in
        if aexp_needed then parens (align epp) else epp
     | E_vector_update(v,e1,e2) ->
        raise (Reporting_basic.err_unreachable l
diff --git a/src/state.ml b/src/state.ml
index c591f753..e788ab6a 100644
--- a/src/state.ml
+++ b/src/state.ml
@@ -411,7 +411,7 @@ let rec regval_convs_coq (Typ_aux (t, _) as typ) = match t with
      let size = string_of_nexp (nexp_simp size) in
      let is_inc = if is_order_inc ord then "true" else "false" in
      let etyp_of, of_etyp = regval_convs_coq etyp in
-     "(fun v => vector_of_regval " ^ etyp_of ^ " v)",
+     "(fun v => vector_of_regval " ^ size ^ " " ^ etyp_of ^ " v)",
      "(fun v => regval_of_vector " ^ of_etyp ^ " " ^ size ^ " " ^ is_inc ^ " v)"
   | Typ_app (id, [Typ_arg_aux (Typ_arg_typ etyp, _)])
     when string_of_id id = "list" ->
@@ -430,12 +430,12 @@ let rec regval_convs_coq (Typ_aux (t, _) as typ) = match t with
 let register_refs_coq registers =
   let generic_convs =
     separate_map hardline string [
-      "Definition vector_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with";
-      "  | Regval_vector (_, _, v) => just_list (List.map of_regval v)";
+      "Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with";
+      "  | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None";
       "  | _ => None";
       "end.";
       "";
-      "Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : list a) : register_value := Regval_vector (size, is_inc, List.map regval_of xs).";
+      "Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)).";
       "";
       "Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with";
       "  | Regval_list v => just_list (List.map of_regval v)";
-- 
cgit v1.2.3


From 5ee9dfaf970de672aa379ea466bf48292bcd41cf Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Sat, 7 Jul 2018 16:37:00 +0100
Subject: Coq: bbv have reorganised their repository

---
 lib/coq/Makefile      | 2 +-
 lib/coq/_CoqProject   | 2 ++
 mips/Makefile         | 2 +-
 mips/_CoqProject      | 2 ++
 test/coq/run_tests.sh | 2 +-
 5 files changed, 7 insertions(+), 3 deletions(-)
 create mode 100644 lib/coq/_CoqProject
 create mode 100644 mips/_CoqProject

diff --git a/lib/coq/Makefile b/lib/coq/Makefile
index 816a6c3d..97869e3c 100644
--- a/lib/coq/Makefile
+++ b/lib/coq/Makefile
@@ -1,4 +1,4 @@
-BBV_DIR=../../../bbv
+BBV_DIR=../../../bbv/theories
 
 SRC=Sail2_prompt_monad.v  Sail2_prompt.v  Sail2_impl_base.v  Sail2_instr_kinds.v  Sail2_operators_bitlists.v  Sail2_operators_mwords.v  Sail2_operators.v  Sail2_values.v  Sail2_state_monad.v  Sail2_state.v
 
diff --git a/lib/coq/_CoqProject b/lib/coq/_CoqProject
new file mode 100644
index 00000000..9f5d26b8
--- /dev/null
+++ b/lib/coq/_CoqProject
@@ -0,0 +1,2 @@
+-R . Sail
+-R ../../../bbv/theories bbv
diff --git a/mips/Makefile b/mips/Makefile
index f8b7588f..062ccd8b 100644
--- a/mips/Makefile
+++ b/mips/Makefile
@@ -48,7 +48,7 @@ mips.v: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS)
 mips_types.v: mips.v
 
 MIPS_COQ = mips_types.v mips_extras.v mips.v
-COQ_LIBS = -R ../../bbv bbv -R ../lib/coq Sail
+COQ_LIBS = -R ../../bbv/theories bbv -R ../lib/coq Sail
 
 %.vo: %.v
 	coqc $(COQ_LIBS) $<
diff --git a/mips/_CoqProject b/mips/_CoqProject
new file mode 100644
index 00000000..ad38d28d
--- /dev/null
+++ b/mips/_CoqProject
@@ -0,0 +1,2 @@
+-R ../../bbv/theories bbv
+-R ../lib/coq Sail
\ No newline at end of file
diff --git a/test/coq/run_tests.sh b/test/coq/run_tests.sh
index 2be5e535..5a723a06 100755
--- a/test/coq/run_tests.sh
+++ b/test/coq/run_tests.sh
@@ -5,7 +5,7 @@ DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
 SAILDIR="$DIR/../.."
 TYPECHECKTESTSDIR="$DIR/../typecheck/pass"
 EXTRATESTSDIR="$DIR/pass"
-BBVDIR="$DIR/../../../bbv"
+BBVDIR="$DIR/../../../bbv/theories"
 
 RED='\033[0;31m'
 GREEN='\033[0;32m'
-- 
cgit v1.2.3


From 7f7e71da17b9d6a447f3b3950d4d4c7198dadaa7 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Fri, 6 Jul 2018 09:35:05 -0700
Subject: Add some tracing to riscv address translation.

---
 riscv/riscv_types.sail |  2 +-
 riscv/riscv_vmem.sail  | 50 +++++++++++++++++++++++++++++++++++++++-----------
 2 files changed, 40 insertions(+), 12 deletions(-)

diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index e2341a8a..ddce0615 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -309,7 +309,7 @@ function exceptionType_to_bits(e) =
 val cast exceptionType_to_str : ExceptionType -> string
 function exceptionType_to_str(e) =
   match (e) {
-    E_Fetch_Addr_Align => "fisaligned-fetch",
+    E_Fetch_Addr_Align => "misaligned-fetch",
     E_Fetch_Access_Fault => "fetch-access-fault",
     E_Illegal_Instr => "illegal-instruction",
     E_Breakpoint => "breakpoint",
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index 9d0f42d1..36650705 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -61,21 +61,33 @@ enum PTW_Error = {
   PTW_Misaligned,   /* misaligned superpage */
   PTW_PTE_Update    /* PTE update needed but not enabled */
 }
+val cast ptw_error_to_str : PTW_Error -> string
+function ptw_error_to_str(e) =
+  match (e) {
+    PTW_Access        => "mem-access-error",
+    PTW_Invalid_PTE   => "invalid-pte",
+    PTW_No_Permission => "no-permission",
+    PTW_Misaligned    => "misaligned-superpage",
+    PTW_PTE_Update    => "pte-update-needed"
+  }
 
 /* conversion of these translation/PTW failures into architectural exceptions */
-function translationException(a : AccessType, f : PTW_Error) -> ExceptionType =
+function translationException(a : AccessType, f : PTW_Error) -> ExceptionType = {
+  let e : ExceptionType =
   match (a, f) {
-    (Read, PTW_Access)  => E_Load_Access_Fault,
-    (Read, _)           => E_Load_Page_Fault,
-    (Write, PTW_Access) => E_SAMO_Access_Fault,
-    (Write, _)          => E_SAMO_Page_Fault,
-    (Fetch, PTW_Access) => E_Fetch_Access_Fault,
-    (Fetch, _)          => E_Fetch_Page_Fault,
-    /* atomics never raise Load exceptions */
     (ReadWrite, PTW_Access) => E_SAMO_Access_Fault,
-    (ReadWrite, _)          => E_SAMO_Page_Fault
+    (ReadWrite, _)          => E_SAMO_Page_Fault,
+    (Read, PTW_Access)      => E_Load_Access_Fault,
+    (Read, _)               => E_Load_Page_Fault,
+    (Write, PTW_Access)     => E_SAMO_Access_Fault,
+    (Write, _)              => E_SAMO_Page_Fault,
+    (Fetch, PTW_Access)     => E_Fetch_Access_Fault,
+    (Fetch, _)              => E_Fetch_Page_Fault
+  } in {
+    print("translationException(" ^ a ^ ", " ^ f ^ ") -> " ^ e);
+    e
   }
-
+}
 /* address translation: Sv39 */
 
 let SV39_LEVEL_BITS = 9
@@ -133,18 +145,32 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
   let pte_addr = ptb + pt_ofs;
   /* FIXME: we assume here that walks only access memory-backed addresses. */
   match (phys_mem_read(Data, EXTZ(pte_addr), 8)) {
-    MemException(_) => PTW_Failure(PTW_Access),
+    MemException(_) => {
+      print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
+            ^ " pt_base=" ^ BitStr(ptb)
+            ^ " pt_ofs=" ^ BitStr(pt_ofs)
+            ^ " pte_addr=" ^ BitStr(pte_addr)
+            ^ ": invalid pte address");
+      PTW_Failure(PTW_Access)
+    },
     MemValue(v) => {
       let pte = Mk_SV39_PTE(v);
       let pbits = pte.BITS();
       let pattr = Mk_PTE_Bits(pbits);
       let is_global = global | (pattr.G() == true);
+/*    print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
+            ^ " pt_base=" ^ BitStr(ptb)
+            ^ " pt_ofs=" ^ BitStr(pt_ofs)
+            ^ " pte_addr=" ^ BitStr(pte_addr)
+            ^ " pte=" ^ BitStr(v)); */
       if isInvalidPTE(pbits) then {
+/*      print("walk39: invalid pte"); */
         PTW_Failure(PTW_Invalid_PTE)
       } else {
         if isPTEPtr(pbits) then {
           if level == 0 then {
             /* last-level PTE contains a pointer instead of a leaf */
+/*          print("walk39: last-level pte contains a ptr"); */
             PTW_Failure(PTW_Invalid_PTE)
           } else {
             /* walk down the pointer to the next level */
@@ -152,6 +178,7 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
           }
         } else { /* leaf PTE */
           if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pattr)) then {
+/*          print("walk39: pte permission check failure"); */
             PTW_Failure(PTW_No_Permission)
           } else {
             if level > 0 then { /* superpage */
@@ -159,6 +186,7 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
               let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV39_LEVEL_BITS) - 1;
               if (pte.PPNi() & mask) != EXTZ(0b0) then {
                 /* misaligned superpage mapping */
+/*              print("walk39: misaligned superpage mapping"); */
                 PTW_Failure(PTW_Misaligned)
               } else {
                 /* add the appropriate bits of the VPN to the superpage PPN */
-- 
cgit v1.2.3


From 89771ed18298be5665f742f8cccc408284cc2939 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Fri, 6 Jul 2018 15:07:27 -0700
Subject: An initial fix to riscv lr/sc, needs a review.

This uses a stronger model than the version in Sail-1 in order to
perform address alignment checks.  The reservation is kept on virtual
addresses, and maintained in the platform model, but now the lr/sc
definitions need calls to externs to update this state.  An
alternative was to reserve physical addresses, but that appeared to be
more complicated without a lot more changes.  Ideally, the model
should be parameterizable over both options.
---
 riscv/platform.ml                 |  17 ++++++
 riscv/riscv.sail                  | 117 ++++++++++++++++++++++++++------------
 riscv/riscv_extras.lem            |   7 ++-
 riscv/riscv_extras_sequential.lem |   7 ++-
 riscv/riscv_mem.sail              |   3 +-
 riscv/riscv_sys.sail              |  24 +++++++-
 6 files changed, 133 insertions(+), 42 deletions(-)

diff --git a/riscv/platform.ml b/riscv/platform.ml
index 0366e601..ddae4840 100644
--- a/riscv/platform.ml
+++ b/riscv/platform.ml
@@ -97,7 +97,24 @@ let clint_size () = bits_of_int64 P.clint_size
 
 let insns_per_tick () = Big_int.of_int P.insns_per_tick
 
+(* load reservation *)
+
+let reservation = ref "none"  (* shouldn't match any valid address *)
+
+let load_reservation addr =
+  Printf.eprintf "reservation <- %s\n" (!reservation);
+  reservation := string_of_bits addr
+
+let match_reservation addr =
+  Printf.eprintf "reservation: %s, key=%s\n" (!reservation) (string_of_bits addr);
+  string_of_bits addr = !reservation
+
+let cancel_reservation () =
+  Printf.eprintf "reservation <- none\n";
+  reservation := "none"
+
 (* terminal I/O *)
+
 let term_write char_bits =
   let big_char = Big_int.bitwise_and (uint char_bits) (Big_int.of_int 255) in
   P.term_write (char_of_int (Big_int.to_int big_char))
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 35f3c625..687531c1 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -328,7 +328,7 @@ function extend_value(is_unsigned, value) = match (value) {
 
 val process_load : forall 'n, 0 < 'n <= 8. (regbits, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> bool effect {escape, rreg, wreg}
 function process_load(rd, addr, value, is_unsigned) =
-  match (extend_value(is_unsigned, value)) {
+  match extend_value(is_unsigned, value) {
     MemValue(result) => { X(rd) = result; true },
     MemException(e)  => { handle_mem_exception(addr, e); false }
   }
@@ -913,20 +913,43 @@ union clause ast = LOADRES : (bool, bool, regbits, word_width, regbits)
 
 mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111
 
-val process_loadres : forall 'n, 0 < 'n <= 8. (regbits, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> unit
+/* We could set load-reservations on physical or virtual addresses.
+ * For now we set them on virtual addresses, since it makes the
+ * sequential model of SC a bit simpler, at the cost of an explicit
+ * call to load_reservation in LR and cancel_reservation in SC.
+ */
 
-function clause execute(LOADRES(aq, rl, rs1, width, rd)) =
-  let vaddr : xlenbits = X(rs1) in
-  match translateAddr(vaddr, Read, Data) {
-    TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
-    TR_Address(addr) =>
-      match width {
-        WORD   => process_load(rd, addr, mem_read(addr, 4, aq, rl, true), false),
-        DOUBLE => process_load(rd, addr, mem_read(addr, 8, aq, rl, true), false),
-        _      => internal_error("LOADRES expected WORD or DOUBLE")
-      }
+val process_loadres : forall 'n, 0 < 'n <= 8. (regbits, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> bool effect {escape, rreg, wreg}
+function process_loadres(rd, addr, value, is_unsigned) =
+  match extend_value(is_unsigned, value) {
+    MemValue(result) => { X(rd) = result; load_reservation(addr); true },
+    MemException(e)  => { handle_mem_exception(addr, e); false }
   }
 
+function clause execute(LOADRES(aq, rl, rs1, width, rd)) =
+  let vaddr : xlenbits = X(rs1) in
+  let aligned : bool =
+    /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt
+     * to treat them as valid here; otherwise we'd need to throw an internal_error.
+     * May need to revisit for latex output.
+     */
+    match width {
+      BYTE   => true,
+      HALF   => vaddr[0]    == 0b0,
+      WORD   => vaddr[1..0] == 0b00,
+      DOUBLE => vaddr[2..0] == 0b000
+    } in
+  if (~ (aligned))
+  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false }
+  else match translateAddr(vaddr, Read, Data) {
+         TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
+         TR_Address(addr) =>
+           match width {
+             WORD   => process_loadres(rd, vaddr, mem_read(addr, 4, aq, rl, true), false),
+             DOUBLE => process_loadres(rd, vaddr, mem_read(addr, 8, aq, rl, true), false),
+             _      => internal_error("LOADRES expected WORD or DOUBLE")
+           }
+       }
 
 function clause print_insn (LOADRES(aq, rl, rs1, width, rd)) =
   "lr" ^ lrsc_width_str(width) ^ aqrl_str(aq, rl) ^ " " ^ rd ^ ", " ^ rs1
@@ -941,31 +964,51 @@ mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) <-> 0b00011 @ bool_
 /* NOTE: Currently, we only EA if address translation is successful.
    This may need revisiting. */
 function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
-  status : bits(1) = if speculate_conditional_success() then 0b0 else 0b1;
-  X(rd) = EXTZ(status);
-
-  if status == 0b1 then true else {
-    vaddr : xlenbits = X(rs1);
-    match translateAddr(vaddr, Write, Data) {
-      TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
-      TR_Address(addr) => {
-        let eares : MemoryOpResult(unit) = match width {
-          WORD   => mem_write_ea(addr, 4, aq, rl, true),
-          DOUBLE => mem_write_ea(addr, 8, aq, rl, true),
-          _      => internal_error("STORECON expected word or double")
-        };
-        match (eares) {
-          MemException(e)  => { handle_mem_exception(addr, e); false },
-          MemValue(_) => {
-            rs2_val = X(rs2);
-            let res : MemoryOpResult(unit) = match width {
-              WORD   => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, true),
-              DOUBLE => mem_write_value(addr, 8, rs2_val,        aq, rl, true),
-              _      => internal_error("STORECON expected word or double")
-            } in
-            match (res) {
-              MemValue(_)     => true,
-              MemException(e) => { handle_mem_exception(addr, e); false }
+  /* RMEM FIXME:  This definition differs from the Sail1 version:
+   * rs1 is read *before* speculate_conditional_success
+   * (called via match_reservation), partly due to the current api of
+   * match_reservation.  Reverting back to the weaker Sail1 version
+   * will require changes to the API for the ghost reservation state.
+   */
+  vaddr : xlenbits = X(rs1);
+  let aligned : bool =
+    /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt
+     * to treat them as valid here; otherwise we'd need to throw an internal_error.
+     * May need to revisit for latex output.
+     */
+    match width {
+      BYTE   => true,
+      HALF   => vaddr[0]    == 0b0,
+      WORD   => vaddr[1..0] == 0b00,
+      DOUBLE => vaddr[2..0] == 0b000
+    } in
+  if (~ (aligned))
+  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false }
+  else {
+    if match_reservation(vaddr) == false
+    then { X(rd) = EXTZ(0b1); true }
+    else {
+      match translateAddr(vaddr, Write, Data) {
+        TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
+        TR_Address(addr) => {
+          let eares : MemoryOpResult(unit) = match width {
+            WORD   => mem_write_ea(addr, 4, aq, rl, true),
+            DOUBLE => mem_write_ea(addr, 8, aq, rl, true),
+            _      => internal_error("STORECON expected word or double")
+          };
+          match (eares) {
+            MemException(e)  => { handle_mem_exception(addr, e); false },
+            MemValue(_) => {
+              rs2_val = X(rs2);
+              let res : MemoryOpResult(unit) = match width {
+                WORD   => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, true),
+                DOUBLE => mem_write_value(addr, 8, rs2_val,        aq, rl, true),
+                _      => internal_error("STORECON expected word or double")
+              };
+              match (res) {
+                MemValue(_)     => { X(rd) = EXTZ(0b0); cancel_reservation(); true },
+                MemException(e) => { handle_mem_exception(addr, e); false }
+              }
             }
           }
         }
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index b3d84df6..88ac3e6f 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -45,7 +45,12 @@ val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
 let read_ram addrsize size hexRAM address =
   read_mem Read_plain address size
 
-let speculate_conditional_success () = excl_result ()
+val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit
+let load_reservation addr = ()
+
+let speculate_conditional_success _ = excl_result ()
+
+let cancel_reservation () = ()
 
 val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a
 let plat_ram_base () = wordFromInteger 0
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index b3d84df6..88ac3e6f 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -45,7 +45,12 @@ val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
 let read_ram addrsize size hexRAM address =
   read_mem Read_plain address size
 
-let speculate_conditional_success () = excl_result ()
+val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit
+let load_reservation addr = ()
+
+let speculate_conditional_success _ = excl_result ()
+
+let cancel_reservation () = ()
 
 val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a
 let plat_ram_base () = wordFromInteger 0
diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail
index 9ead3aeb..008c1642 100644
--- a/riscv/riscv_mem.sail
+++ b/riscv/riscv_mem.sail
@@ -92,6 +92,7 @@ function phys_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -
   else MemException(E_SAMO_Access_Fault)
 }
 
+// dispatches to MMIO regions or physical memory regions depending on physical memory map
 function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n, 'n > 0. MemoryOpResult(unit) =
   if   within_mmio_writable(addr, width)
   then mmio_write(addr, width, data)
@@ -133,8 +134,6 @@ function mem_write_value (addr, width, value, aq, rl, con) = {
   }
 }
 
-val "speculate_conditional_success" : unit -> bool effect {exmem}
-
 val MEM_fence_rw_rw = {ocaml: "skip", lem: "MEM_fence_rw_rw"} : unit -> unit effect {barr}
 val MEM_fence_r_rw  = {ocaml: "skip", lem: "MEM_fence_r_rw"}  : unit -> unit effect {barr}
 val MEM_fence_r_r   = {ocaml: "skip", lem: "MEM_fence_r_r"}   : unit -> unit effect {barr}
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index bb3d13db..e8128edf 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -363,7 +363,6 @@ function legalize_sedeleg(s : Sedeleg, v : xlenbits) -> Sedeleg = {
   Mk_Sedeleg(EXTZ(v[8..0]))
 }
 
-/* TODO: handle views for interrupt delegation */
 bitfield Sinterrupts : bits(64) = {
   SEI : 9,  /* external interrupts */
   UEI : 8,
@@ -670,6 +669,24 @@ function check_CSR(csr : csreg, p : Privilege, isWrite : bool) -> bool =
   & check_TVM_SATP(csr, p)
   & check_Counteren(csr, p)
 
+/* Reservation handling for LR/SC.
+ *
+ * The reservation state is maintained external to the model since the
+ * reservation behavior is platform-specific anyway and maintaining
+ * this state outside the model simplifies the concurrency analysis.
+ *
+ * These are externs are defined here in the system module since
+ * we currently perform reservation cancellation on privilege level
+ * transition.  Ideally, the platform should get more visibility into
+ * where cancellation can be performed.
+ */
+
+val load_reservation = {ocaml: "Platform.load_reservation", lem: "load_reservation"} : xlenbits -> unit
+
+val match_reservation = {ocaml: "Platform.match_reservation", lem: "speculate_conditional_success"} : xlenbits -> bool effect {exmem}
+
+val cancel_reservation = {ocaml: "Platform.cancel_reservation", lem: "cancel_reservation"} : unit -> unit
+
 /* Exception delegation: given an exception and the privilege at which
  * it occured, returns the privilege at which it should be handled.
  */
@@ -776,6 +793,7 @@ union ctl_result = {
 function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits))
                     -> xlenbits = {
   print("handling " ^ (if intr then "int#" else "exc#") ^ BitStr(c) ^ " at priv " ^ del_priv ^ " with tval " ^ BitStr(tval(info)));
+  cancel_reservation();
   match (del_priv) {
     Machine => {
        mcause->IsInterrupt() = intr;
@@ -840,6 +858,8 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       cur_privilege   = privLevel_of_bits(mstatus.MPP());
       mstatus->MPP()  = privLevel_to_bits(User);
 
+      cancel_reservation();
+
       print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
       mepc
@@ -851,6 +871,8 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       cur_privilege   = if mstatus.SPP() == true then Supervisor else User;
       mstatus->SPP()  = false;
 
+      cancel_reservation();
+
       print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
       sepc
-- 
cgit v1.2.3


From 1f60d65d5817c7eb897197568525469163eb7cea Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Fri, 6 Jul 2018 16:53:57 -0700
Subject: Add the lrsc tests from riscv-tests.

---
 test/riscv/tests/rv64ua-p-lrsc.elf | Bin 0 -> 14632 bytes
 test/riscv/tests/rv64ua-v-lrsc.elf | Bin 0 -> 19816 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100755 test/riscv/tests/rv64ua-p-lrsc.elf
 create mode 100755 test/riscv/tests/rv64ua-v-lrsc.elf

diff --git a/test/riscv/tests/rv64ua-p-lrsc.elf b/test/riscv/tests/rv64ua-p-lrsc.elf
new file mode 100755
index 00000000..0fb5b44e
Binary files /dev/null and b/test/riscv/tests/rv64ua-p-lrsc.elf differ
diff --git a/test/riscv/tests/rv64ua-v-lrsc.elf b/test/riscv/tests/rv64ua-v-lrsc.elf
new file mode 100755
index 00000000..3f49c87c
Binary files /dev/null and b/test/riscv/tests/rv64ua-v-lrsc.elf differ
-- 
cgit v1.2.3


From 03acdbccf2793cf7105fdd365df6f876681a99b2 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Sat, 7 Jul 2018 15:24:23 -0700
Subject: Cancel riscv reservation before i/o scheduling, tweak reservation
 tracing.

---
 riscv/platform.ml         |  2 +-
 riscv/riscv.sail          |  6 ++----
 riscv/riscv_platform.sail |  3 ++-
 riscv/riscv_sys.sail      | 14 +++++++++-----
 4 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/riscv/platform.ml b/riscv/platform.ml
index ddae4840..092df80f 100644
--- a/riscv/platform.ml
+++ b/riscv/platform.ml
@@ -102,7 +102,7 @@ let insns_per_tick () = Big_int.of_int P.insns_per_tick
 let reservation = ref "none"  (* shouldn't match any valid address *)
 
 let load_reservation addr =
-  Printf.eprintf "reservation <- %s\n" (!reservation);
+  Printf.eprintf "reservation <- %s\n" (string_of_bits addr);
   reservation := string_of_bits addr
 
 let match_reservation addr =
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 687531c1..7f51ba85 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -868,9 +868,7 @@ union clause ast = SFENCE_VMA : (regbits, regbits)
 mapping clause encdec = SFENCE_VMA(rs1, rs2) <-> 0b0001001 @ rs2 @ rs1 @ 0b000 @ 0b00000 @ 0b1110011
 
 function clause execute SFENCE_VMA(rs1, rs2) = {
-  /* FIXME: spec leaves unspecified what happens if this is executed in M-mode.
-     We assume it is the same as S-mode, which is definitely wrong.
-   */
+  /* TODO: handle PMP/TLB synchronization when executed in M-mode. */
   if cur_privilege == User then { handle_illegal(); false }
   else match (architecture(mstatus.SXL()), mstatus.TVM()) {
     (Some(RV64), true)  => { handle_illegal(); false },
@@ -922,7 +920,7 @@ mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) <-> 0b00010 @ bool_bits(a
 val process_loadres : forall 'n, 0 < 'n <= 8. (regbits, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> bool effect {escape, rreg, wreg}
 function process_loadres(rd, addr, value, is_unsigned) =
   match extend_value(is_unsigned, value) {
-    MemValue(result) => { X(rd) = result; load_reservation(addr); true },
+    MemValue(result) => { load_reservation(addr); X(rd) = result; true },
     MemException(e)  => { handle_mem_exception(addr, e); false }
   }
 
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail
index e7ca9418..6b903e70 100644
--- a/riscv/riscv_platform.sail
+++ b/riscv/riscv_platform.sail
@@ -245,5 +245,6 @@ function init_platform() -> unit = {
 }
 
 function tick_platform() -> unit = {
-  htif_tick()
+  cancel_reservation();
+  htif_tick();
 }
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index e8128edf..3152b95c 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -793,7 +793,7 @@ union ctl_result = {
 function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits))
                     -> xlenbits = {
   print("handling " ^ (if intr then "int#" else "exc#") ^ BitStr(c) ^ " at priv " ^ del_priv ^ " with tval " ^ BitStr(tval(info)));
-  cancel_reservation();
+
   match (del_priv) {
     Machine => {
        mcause->IsInterrupt() = intr;
@@ -809,6 +809,8 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
 
        print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
 
+       cancel_reservation();
+
        match tvec_addr(mtvec, mcause) {
          Some(epc) => epc,
          None()    => internal_error("Invalid mtvec mode")
@@ -832,6 +834,8 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
 
        print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
 
+       cancel_reservation();
+
        match tvec_addr(stvec, scause) {
          Some(epc) => epc,
          None()    => internal_error("Invalid stvec mode")
@@ -858,10 +862,10 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       cur_privilege   = privLevel_of_bits(mstatus.MPP());
       mstatus->MPP()  = privLevel_to_bits(User);
 
-      cancel_reservation();
-
       print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
+
+      cancel_reservation();
       mepc
     },
     (_, CTL_SRET())  => {
@@ -871,10 +875,10 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       cur_privilege   = if mstatus.SPP() == true then Supervisor else User;
       mstatus->SPP()  = false;
 
-      cancel_reservation();
-
       print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
+
+      cancel_reservation();
       sepc
     }
   }
-- 
cgit v1.2.3


From d819af50c403935cb6825afa914e03c816e156cb Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Sat, 7 Jul 2018 15:59:36 -0700
Subject: Add reservation traces to riscv tracecmp tool.

---
 riscv/tracecmp.ml | 47 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/riscv/tracecmp.ml b/riscv/tracecmp.ml
index 7f70478c..64a918d5 100644
--- a/riscv/tracecmp.ml
+++ b/riscv/tracecmp.ml
@@ -31,6 +31,11 @@ type htif = {
   tohost : int64
 }
 
+type ld_res =
+  | Res_make of int64
+  | Res_match of int64 * int64
+  | Res_cancel
+
 type line =
   | L_none
   | L_inst of inst
@@ -39,6 +44,7 @@ type line =
   | L_csr_write of csr_write
   | L_tick of tick
   | L_htif of htif
+  | L_ld_res of ld_res
 
 let inst_count = ref 0
 
@@ -142,6 +148,43 @@ let parse_htif l =
 let sprint_htif t =
   Printf.sprintf "htif::tick 0x%Lx" t.tohost
 
+(* Load reservations:
+   make:   reservation <- 0x80002008
+   match:  reservation: 0xffffffffffffffff, key=0x80002008
+   cancel: reservation <- none
+
+ *)
+let parse_ldres_match l =
+  try Scanf.sscanf
+        l " reservation: 0x%Lx, key=0x%Lx"
+                   (fun res key -> L_ld_res (Res_match (res, key)))
+  with
+    | Scanf.Scan_failure _ -> L_none
+    | End_of_file -> L_none
+
+let parse_ldres_match_sail l =
+  try Scanf.sscanf
+        l " reservation: none, key=0x%Lx"
+                   (fun key -> L_ld_res (Res_match (Int64.minus_one, key)))
+  with
+    | Scanf.Scan_failure _ -> L_none
+    | End_of_file -> L_none
+
+let parse_ldres_change l =
+  try if l = "reservation <- none"
+      then L_ld_res Res_cancel
+      else Scanf.sscanf
+             l " reservation <- 0x%Lx"
+             (fun res -> L_ld_res (Res_make res))
+  with
+    | Scanf.Scan_failure _ -> L_none
+    | End_of_file -> L_none
+
+let sprint_ldres = function
+  | Res_make res         -> Printf.sprintf "reservation <- 0x%Lx" res
+  | Res_match (res, key) -> Printf.sprintf "reservation: 0x%Lx, key=0x%Lx" res key
+  | Res_cancel           -> Printf.sprintf "reservation <- none"
+
 (* scanners *)
 
 let popt p l = function
@@ -151,9 +194,10 @@ let popt p l = function
 let parse_line l =
   parse_csr_read l |> popt parse_csr_write l
   |> popt parse_reg_write l |> popt parse_tick l |> popt parse_htif l
+  |> popt parse_ldres_change l  |> popt parse_ldres_match l
 
 let parse_sail_line l =
-  parse_line l |> popt parse_sail_inst l
+  parse_line l |> popt parse_sail_inst l  |> popt parse_ldres_match_sail l
 
 let parse_spike_line l =
   parse_line l |> popt parse_spike_inst l
@@ -167,6 +211,7 @@ let sprint_line = function
   | L_csr_write r -> Printf.sprintf "<%d> %s" !inst_count (sprint_csr_write r)
   | L_tick t      -> Printf.sprintf "<%d> %s" !inst_count (sprint_tick t)
   | L_htif t      -> Printf.sprintf "<%d> %s" !inst_count (sprint_htif t)
+  | L_ld_res r    -> Printf.sprintf "<%d> %s" !inst_count (sprint_ldres r)
 
 (* file processing *)
 
-- 
cgit v1.2.3


From 8286993fe02b151dc1daa808b422f1ba97e05602 Mon Sep 17 00:00:00 2001
From: Alasdair
Date: Sun, 8 Jul 2018 14:19:23 +0100
Subject: Add -static flag that controls whether generated C functions are
 static

By default generated functions are non-static, using the -static flag makes them static which is useful for measuring coverage using generated code. Some utility helper functions will always be static, but the compiled versions of sail functions won't be unless this flag is set.
---
 src/c_backend.ml | 7 +++++--
 src/sail.ml      | 3 +++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/c_backend.ml b/src/c_backend.ml
index 09501ce9..e92ca1a6 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -63,6 +63,7 @@ module Big_int = Nat_big_num
 let c_verbosity = ref 0
 let opt_ddump_flow_graphs = ref false
 let opt_trace = ref false
+let opt_static = ref false
 
 (* Optimization flags *)
 let optimize_primops = ref false
@@ -2547,10 +2548,12 @@ let codegen_def' ctx = function
        match ret_arg with
        | None ->
           assert (is_stack_ctyp ret_ctyp);
-          string "static " ^^ string (sgen_ctyp ret_ctyp) ^^ space ^^ codegen_id id ^^ parens (string args) ^^ hardline
+          (if !opt_static then string "static " else empty)
+          ^^ string (sgen_ctyp ret_ctyp) ^^ space ^^ codegen_id id ^^ parens (string args) ^^ hardline
        | Some gs ->
           assert (not (is_stack_ctyp ret_ctyp));
-          string "static void" ^^ space ^^ codegen_id id
+          (if !opt_static then string "static " else empty)
+          ^^ string "void" ^^ space ^^ codegen_id id
           ^^ parens (string (sgen_ctyp ret_ctyp ^ " *" ^ sgen_id gs ^ ", ") ^^ string args)
           ^^ hardline
      in
diff --git a/src/sail.ml b/src/sail.ml
index 046445d1..64e60c23 100644
--- a/src/sail.ml
+++ b/src/sail.ml
@@ -121,6 +121,9 @@ let options = Arg.align ([
   ( "-Oconstant_fold",
     Arg.Set Constant_fold.optimize_constant_fold,
     " Apply constant folding optimizations");
+  ( "-static",
+    Arg.Set C_backend.opt_static,
+    " Make generated C functions static");
   ( "-trace",
     Arg.Tuple [Arg.Set C_backend.opt_trace; Arg.Set Ocaml_backend.opt_trace_ocaml],
     " Instrument ouput with tracing");
-- 
cgit v1.2.3


From a6e9d1a5bc28073d0d0257cefae5e4b1d59bb71d Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Sun, 8 Jul 2018 21:31:09 -0700
Subject: Add a riscv coverage target using bisect-ppx.

---
 riscv/Makefile     | 14 +++++++++++++-
 riscv/_tags.bisect |  3 +++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 riscv/_tags.bisect

diff --git a/riscv/Makefile b/riscv/Makefile
index 22f80338..621754b8 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -17,9 +17,21 @@ _sbuild/platform_main.native: _sbuild/riscv.ml _tags $(PLATFORM_OCAML_SRCS) Make
 	cp _tags $(PLATFORM_OCAML_SRCS) _sbuild
 	cd _sbuild && ocamlbuild -use-ocamlfind platform_main.native
 
+_sbuild/coverage.native: _sbuild/riscv.ml _tags.bisect $(PLATFORM_OCAML_SRCS) Makefile
+	cp $(PLATFORM_OCAML_SRCS) _sbuild
+	cp _tags.bisect _sbuild/_tags
+	cd _sbuild && ocamlbuild -use-ocamlfind platform_main.native && cp -L platform_main.native coverage.native
+
 platform: _sbuild/platform_main.native
 	rm -f $@ && ln -s $^ $@
 
+coverage: _sbuild/coverage.native
+	rm -f platform && ln -s $^ platform # since the test scripts runs this file
+	rm -rf bisect*.out bisect coverage
+	../test/riscv/run_tests.sh # this will generate bisect*.out files in this directory
+	mkdir bisect && mv bisect*.out bisect/
+	mkdir coverage && bisect-ppx-report -html coverage/ -I _sbuild/ bisect/bisect*.out
+
 tracecmp: tracecmp.ml
 	ocamlfind ocamlopt -annot -linkpkg -package unix $^ -o $@
 
@@ -69,6 +81,6 @@ clean:
 		Riscv_extras.thy
 	-rm -f Riscv_duopod.thy Riscv_duopod_types.thy riscv_duopod.lem riscv_duopod_types.lem
 	-rm -f riscvScript.sml riscv_typesScript.sml riscv_extrasScript.sml
-	-rm -f platform_main.native platform
+	-rm -f platform_main.native platform coverage.native
 	-Holmake cleanAll
 	ocamlbuild -clean
diff --git a/riscv/_tags.bisect b/riscv/_tags.bisect
new file mode 100644
index 00000000..d3b996f2
--- /dev/null
+++ b/riscv/_tags.bisect
@@ -0,0 +1,3 @@
+<**/*.ml>: bin_annot, annot
+<*.m{l,li}>: package(lem), package(linksem), package(zarith), package(bisect_ppx)
+<platform_main.native>: package(lem), package(linksem), package(zarith), package(bisect_ppx)
-- 
cgit v1.2.3


From 24860b61c062175fc4db391c8bb5113a108ea82f Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Sun, 8 Jul 2018 21:32:53 -0700
Subject: Move the riscv analysis function into its own file for coverage
 purposes.

---
 riscv/riscv.sail          | 183 ----------------------------------------------
 riscv/riscv_analysis.sail | 182 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 182 insertions(+), 183 deletions(-)
 create mode 100644 riscv/riscv_analysis.sail

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 7f51ba85..0b651f04 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -1866,186 +1866,3 @@ end assembly
 end encdec
 
 function decode bv = Some(encdec(bv))
-
-$include <regfp.sail>
-
-/* in reverse order because inc vectors don't seem to work (bug) */
-let GPRstr : vector(32, dec, string) = [ "x31", "x30", "x29", "x28", "x27", "x26", "x25", "x24", "x23", "x22", "x21",
-  "x20", "x19", "x18", "x17", "x16", "x15", "x14", "x13", "x12", "x21",
-  "x10", "x9", "x8", "x7", "x6", "x5", "x4", "x3", "x2", "x1", "x0"
-  ]
-
-
-let CIA_fp = RFull("CIA")
-let NIA_fp = RFull("NIA")
-
-function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = {
-  iR = [| |] : regfps;
-  oR = [| |] : regfps;
-  aR = [| |] : regfps;
-  ik = IK_simple() : instruction_kind;
-  Nias = [| NIAFP_successor() |] : niafps;
-  Dia = DIAFP_none() : diafp;
-
-  match instr {
-     EBREAK() => (),
-     UTYPE(imm, rd, op) => {
-            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-     },
-     RISCV_JAL(imm, rd) => {
-            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-            let offset : bits(64) = EXTS(imm) in
-            Nias = [| NIAFP_concrete_address (PC + offset) |];
-            ik = IK_branch();
-     },
-     RISCV_JALR(imm, rs, rd) => {
-            if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
-            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-            let offset : bits(64) = EXTS(imm) in
-            Nias = [| NIAFP_indirect_address() |];
-            ik = IK_branch();
-     },
-     BTYPE(imm, rs2, rs1, op) => {
-            if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-            if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-            ik = IK_branch();
-            let offset : bits(64) = EXTS(imm) in
-            Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |];
-      },
-      ITYPE(imm, rs, rd, op) => {
-            if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
-            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-      },
-      SHIFTIOP(imm, rs, rd, op) => {
-             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
-             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-      },
-      RTYPE(rs2, rs1, rd, op) => {
-             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-      },
-      CSR(csr, rs1, rd, is_imm, op) => {
-               let isWrite : bool = match op {
-                   CSRRW  => true,
-                   _      => if is_imm then unsigned(rs1) != 0 else unsigned(rs1) != 0
-               };
-               iR = RFull(csr_name(csr)) :: iR;
-               if ~(is_imm) then {
-                  iR = RFull(GPRstr[rs1]) :: iR;
-               };
-               if isWrite then {
-                  oR = RFull(csr_name(csr)) :: oR;
-               };
-               oR = RFull(GPRstr[rd]) :: oR;
-      },
-      LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX "unsigned" causes name conflict in lem shallow embedding... */
-             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
-             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-             aR = iR;
-             ik =
-               match (aq, rl) {
-                 (false, false) => IK_mem_read (Read_plain),
-                 (true,  false) => IK_mem_read (Read_RISCV_acquire),
-                 (true,  true)  => IK_mem_read (Read_RISCV_strong_acquire),
-
-                 _  => internal_error("LOAD type not implemented in initial_analysis")
-               }
-      },
-      STORE(imm, rs2, rs1, width, aq, rl) => {
-             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-             if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
-             ik =
-               match (aq, rl) {
-                 (false, false) => IK_mem_write (Write_plain),
-                 (false, true)  => IK_mem_write (Write_RISCV_release),
-                 (true,  true)  => IK_mem_write (Write_RISCV_strong_release),
-
-                 _ => internal_error("STORE type not implemented in initial_analysis")
-               }
-      },
-      ADDIW(imm, rs, rd) => {
-             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
-             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-      },
-      SHIFTW(imm, rs, rd, op) => {
-             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
-             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-      },
-      RTYPEW(rs2, rs1, rd, op) => {
-             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-      },
-      FENCE(pred, succ) => {
-             ik =
-               match (pred, succ) {
-                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw),
-                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw),
-                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r),
-                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w),
-                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w),
-                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw),
-                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r),
-                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w),
-                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r),
-
-
-                 (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (),
-
-                 _ => internal_error("barrier type not implemented in initial_analysis")
-  //               case (FM_NORMAL, _, _) -> exit "not implemented"
-
-  //               case (FM_TSO, 0b0011, 0b0011) -> IK_barrier (Barrier_RISCV_tso)
-  //               case (FM_TSO, _, _) -> exit "not implemented"
-               };
-      },
-     FENCEI() => {
-              ik = IK_barrier (Barrier_RISCV_i);
-     },
-  //    LOADRES(aq, rl, rs1, width, rd) => {
-  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-  //           aR = iR;
-  //           ik = match (aq, rl) {
-  //             (false, false) => IK_mem_read (Read_RISCV_reserved)
-  //             (true,  false) => IK_mem_read (Read_RISCV_reserved_acquire_RCsc)
-  //             (true,  true)  => IK_mem_read (Read_RISCV_reserved_acquire_release)
-
-  //             (false, true)  => exit "not implemented"
-  //           };
-  //    },
-  //    STORECON(aq, rl, rs2, rs1, width, rd) => {
-  //           if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-  //           if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
-  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-
-  //           ik = switch (aq, rl) {
-  //             case (false, false) -> IK_mem_write (Write_RISCV_conditional)
-  //             case (false, true)  -> IK_mem_write (Write_RISCV_conditional_release_RCsc)
-  //             case (true,  true)  -> IK_mem_write (Write_RISCV_conditional_acquire_release)
-
-  //             case (true,  false) -> exit "not implemented"
-  //           };
-  //    }
-  //    AMO(op, aq, rl, rs2, rs1, width, rd) => {
-  //           if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-  //           if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
-  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-
-  //           ik = switch (aq, rl) {
-  //             (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional)
-  //             (false, true)  => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release_RCsc)
-  //             (true,  false) => IK_mem_rmw (Read_RISCV_reserved_acquire_RCsc,
-  //                                                                     Write_RISCV_conditional)
-  //             (true,  true)  => IK_mem_rmw (Read_RISCV_reserved_acquire_RCsc,
-  //                                                                     Write_RISCV_conditional_release_RCsc)
-  //           };
-  //    }
-        _ => ()
-  };
-  (iR,oR,aR,Nias,Dia,ik)
-}
diff --git a/riscv/riscv_analysis.sail b/riscv/riscv_analysis.sail
new file mode 100644
index 00000000..616d8669
--- /dev/null
+++ b/riscv/riscv_analysis.sail
@@ -0,0 +1,182 @@
+$include <regfp.sail>
+
+/* in reverse order because inc vectors don't seem to work (bug) */
+let GPRstr : vector(32, dec, string) = [ "x31", "x30", "x29", "x28", "x27", "x26", "x25", "x24", "x23", "x22", "x21",
+  "x20", "x19", "x18", "x17", "x16", "x15", "x14", "x13", "x12", "x21",
+  "x10", "x9", "x8", "x7", "x6", "x5", "x4", "x3", "x2", "x1", "x0"
+  ]
+
+
+let CIA_fp = RFull("CIA")
+let NIA_fp = RFull("NIA")
+
+function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = {
+  iR = [| |] : regfps;
+  oR = [| |] : regfps;
+  aR = [| |] : regfps;
+  ik = IK_simple() : instruction_kind;
+  Nias = [| NIAFP_successor() |] : niafps;
+  Dia = DIAFP_none() : diafp;
+
+  match instr {
+     EBREAK() => (),
+     UTYPE(imm, rd, op) => {
+            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+     },
+     RISCV_JAL(imm, rd) => {
+            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+            let offset : bits(64) = EXTS(imm) in
+            Nias = [| NIAFP_concrete_address (PC + offset) |];
+            ik = IK_branch();
+     },
+     RISCV_JALR(imm, rs, rd) => {
+            if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
+            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+            let offset : bits(64) = EXTS(imm) in
+            Nias = [| NIAFP_indirect_address() |];
+            ik = IK_branch();
+     },
+     BTYPE(imm, rs2, rs1, op) => {
+            if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+            if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+            ik = IK_branch();
+            let offset : bits(64) = EXTS(imm) in
+            Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |];
+      },
+      ITYPE(imm, rs, rd, op) => {
+            if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
+            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+      },
+      SHIFTIOP(imm, rs, rd, op) => {
+             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+      },
+      RTYPE(rs2, rs1, rd, op) => {
+             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+      },
+      CSR(csr, rs1, rd, is_imm, op) => {
+               let isWrite : bool = match op {
+                   CSRRW  => true,
+                   _      => if is_imm then unsigned(rs1) != 0 else unsigned(rs1) != 0
+               };
+               iR = RFull(csr_name(csr)) :: iR;
+               if ~(is_imm) then {
+                  iR = RFull(GPRstr[rs1]) :: iR;
+               };
+               if isWrite then {
+                  oR = RFull(csr_name(csr)) :: oR;
+               };
+               oR = RFull(GPRstr[rd]) :: oR;
+      },
+      LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX "unsigned" causes name conflict in lem shallow embedding... */
+             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+             aR = iR;
+             ik =
+               match (aq, rl) {
+                 (false, false) => IK_mem_read (Read_plain),
+                 (true,  false) => IK_mem_read (Read_RISCV_acquire),
+                 (true,  true)  => IK_mem_read (Read_RISCV_strong_acquire),
+
+                 _  => internal_error("LOAD type not implemented in initial_analysis")
+               }
+      },
+      STORE(imm, rs2, rs1, width, aq, rl) => {
+             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+             if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
+             ik =
+               match (aq, rl) {
+                 (false, false) => IK_mem_write (Write_plain),
+                 (false, true)  => IK_mem_write (Write_RISCV_release),
+                 (true,  true)  => IK_mem_write (Write_RISCV_strong_release),
+
+                 _ => internal_error("STORE type not implemented in initial_analysis")
+               }
+      },
+      ADDIW(imm, rs, rd) => {
+             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+      },
+      SHIFTW(imm, rs, rd, op) => {
+             if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+      },
+      RTYPEW(rs2, rs1, rd, op) => {
+             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+      },
+      FENCE(pred, succ) => {
+             ik =
+               match (pred, succ) {
+                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw),
+                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw),
+                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r),
+                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w),
+                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w),
+                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw),
+                 (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r),
+                 (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w),
+                 (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r),
+
+
+                 (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (),
+
+                 _ => internal_error("barrier type not implemented in initial_analysis")
+  //               case (FM_NORMAL, _, _) -> exit "not implemented"
+
+  //               case (FM_TSO, 0b0011, 0b0011) -> IK_barrier (Barrier_RISCV_tso)
+  //               case (FM_TSO, _, _) -> exit "not implemented"
+               };
+      },
+     FENCEI() => {
+              ik = IK_barrier (Barrier_RISCV_i);
+     },
+  //    LOADRES(aq, rl, rs1, width, rd) => {
+  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+  //           aR = iR;
+  //           ik = match (aq, rl) {
+  //             (false, false) => IK_mem_read (Read_RISCV_reserved)
+  //             (true,  false) => IK_mem_read (Read_RISCV_reserved_acquire_RCsc)
+  //             (true,  true)  => IK_mem_read (Read_RISCV_reserved_acquire_release)
+
+  //             (false, true)  => exit "not implemented"
+  //           };
+  //    },
+  //    STORECON(aq, rl, rs2, rs1, width, rd) => {
+  //           if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+  //           if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
+  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+
+  //           ik = switch (aq, rl) {
+  //             case (false, false) -> IK_mem_write (Write_RISCV_conditional)
+  //             case (false, true)  -> IK_mem_write (Write_RISCV_conditional_release_RCsc)
+  //             case (true,  true)  -> IK_mem_write (Write_RISCV_conditional_acquire_release)
+
+  //             case (true,  false) -> exit "not implemented"
+  //           };
+  //    }
+  //    AMO(op, aq, rl, rs2, rs1, width, rd) => {
+  //           if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+  //           if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
+  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+
+  //           ik = switch (aq, rl) {
+  //             (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional)
+  //             (false, true)  => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release_RCsc)
+  //             (true,  false) => IK_mem_rmw (Read_RISCV_reserved_acquire_RCsc,
+  //                                                                     Write_RISCV_conditional)
+  //             (true,  true)  => IK_mem_rmw (Read_RISCV_reserved_acquire_RCsc,
+  //                                                                     Write_RISCV_conditional_release_RCsc)
+  //           };
+  //    }
+        _ => ()
+  };
+  (iR,oR,aR,Nias,Dia,ik)
+}
-- 
cgit v1.2.3


From b9d6151e8671a03eb58f2065e85367fff0a27cf0 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Sun, 8 Jul 2018 21:36:09 -0700
Subject: Make the riscv fetch-execute loop return instead of exiting when
 done.

---
 riscv/riscv_step.sail | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index af41c098..a095c9cb 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -94,7 +94,7 @@ function loop () = {
   let insns_per_tick = plat_insns_per_tick();
   i : int = 0;
   step_no : int = 0;
-  while true do {
+  while (~ (htif_done)) do {
     minstret_written = false;     /* see note for minstret */
     let (retired, stepped) = step(step_no);
     PC = nextPC;
@@ -107,16 +107,15 @@ function loop () = {
       let exit_val = unsigned(htif_exit_code);
       if exit_val == 0 then print("SUCCESS")
       else print_int("FAILURE: ", exit_val);
-      exit(());
-    };
-
-    /* update time */
-    i = i + 1;
-    if i == insns_per_tick then {
-      tick_clock();
-      /* for now, we drive the platform i/o at every clock tick. */
-      tick_platform();
-      i = 0;
+    } else {
+      /* update time */
+      i = i + 1;
+      if i == insns_per_tick then {
+        tick_clock();
+        /* for now, we drive the platform i/o at every clock tick. */
+        tick_platform();
+        i = 0;
+      }
     }
   }
 }
-- 
cgit v1.2.3


From 2c1dfb042ecc10c0ca7868ab186ff8235926d8d3 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Mon, 9 Jul 2018 00:15:20 -0700
Subject: Support writes to misa.C in riscv.

---
 riscv/riscv.sail     |  4 ++--
 riscv/riscv_sys.sail | 18 +++++++++++++-----
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 0b651f04..7ba02a77 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -1159,7 +1159,7 @@ function readCSR csr : csreg -> xlenbits =
     0x305 => mtvec.bits(),
     0x306 => EXTZ(mcounteren.bits()),
     0x340 => mscratch,
-    0x341 => mepc,
+    0x341 => mepc & pc_alignment_mask(),
     0x342 => mcause.bits(),
     0x343 => mtval,
     0x344 => mip.bits(),
@@ -1175,7 +1175,7 @@ function readCSR csr : csreg -> xlenbits =
     0x105 => stvec.bits(),
     0x106 => EXTZ(scounteren.bits()),
     0x140 => sscratch,
-    0x141 => sepc,
+    0x141 => sepc & pc_alignment_mask(),
     0x142 => scause.bits(),
     0x143 => stval,
     0x144 => lower_mip(mip, mideleg).bits(),
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 3152b95c..36942eed 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -40,9 +40,14 @@ bitfield Misa : bits(64) = {
 }
 register misa : Misa
 
-function legalize_misa(m : Misa, v : xlenbits) -> Misa =
-  /* Ignore all writes for now. */
-  m
+function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
+  /* Allow modifications to C. */
+  let v = Mk_Misa(v);
+  // Suppress changing C if nextPC would become misaligned.
+  if v.C() == false & nextPC[1] == true
+  then m
+  else update_C(m, v.C())
+}
 
 bitfield Mstatus : bits(64) = {
   SD   : 63,
@@ -112,6 +117,9 @@ function haveRVC()     -> bool = { misa.C() == true }
 function haveMulDiv()  -> bool = { misa.M() == true }
 function haveFP()      -> bool = { misa.F() == true | misa.D() == true }
 
+function pc_alignment_mask() -> xlenbits =
+  ~(EXTZ(if misa.C() == true then 0b00 else 0b10))
+
 /* interrupt registers */
 
 bitfield Minterrupts : bits(64) = {
@@ -866,7 +874,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
 
       cancel_reservation();
-      mepc
+      mepc & pc_alignment_mask()
     },
     (_, CTL_SRET())  => {
       let prev_priv = cur_privilege;
@@ -879,7 +887,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
 
       cancel_reservation();
-      sepc
+      sepc & pc_alignment_mask()
     }
   }
 }
-- 
cgit v1.2.3


From 0ebe1cc6e52ccc28b8629b0cdfa4a00ed1b60988 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Sat, 7 Jul 2018 23:30:45 +0100
Subject: Bits for bits of aarch64 in coq

---
 aarch64/_CoqProject      |   2 +
 aarch64/aarch64_extras.v | 111 +++++++++++++++++++++++++++++++++++++++++++++++
 aarch64/prelude.sail     |   4 +-
 lib/coq/Sail2_values.v   |   1 +
 4 files changed, 116 insertions(+), 2 deletions(-)
 create mode 100644 aarch64/_CoqProject
 create mode 100644 aarch64/aarch64_extras.v

diff --git a/aarch64/_CoqProject b/aarch64/_CoqProject
new file mode 100644
index 00000000..f08bc79e
--- /dev/null
+++ b/aarch64/_CoqProject
@@ -0,0 +1,2 @@
+-R ../../bbv/theories bbv
+-R ../lib/coq Sail
diff --git a/aarch64/aarch64_extras.v b/aarch64/aarch64_extras.v
new file mode 100644
index 00000000..7d5020ec
--- /dev/null
+++ b/aarch64/aarch64_extras.v
@@ -0,0 +1,111 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_bitlists.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+
+Axiom real : Type.
+Axiom slice : forall {m} (_ : mword m) (_ : Z) (n : Z) `{ArithFact (m >= 0)} `{ArithFact (n >= 0)}, mword n.
+Axiom set_slice : forall (n : Z) (m : Z), mword n -> Z -> mword m -> mword n.
+Definition length {n} (x : mword n) := length_mword x.
+Hint Unfold length : sail.
+
+(*
+let hexchar_to_bool_list c =
+  if c = #'0' then      Just ([false;false;false;false])
+  else if c = #'1' then Just ([false;false;false;true ])
+  else if c = #'2' then Just ([false;false;true; false])
+  else if c = #'3' then Just ([false;false;true; true ])
+  else if c = #'4' then Just ([false;true; false;false])
+  else if c = #'5' then Just ([false;true; false;true ])
+  else if c = #'6' then Just ([false;true; true; false])
+  else if c = #'7' then Just ([false;true; true; true ])
+  else if c = #'8' then Just ([true; false;false;false])
+  else if c = #'9' then Just ([true; false;false;true ])
+  else if c = #'A' then Just ([true; false;true; false])
+  else if c = #'a' then Just ([true; false;true; false])
+  else if c = #'B' then Just ([true; false;true; true ])
+  else if c = #'b' then Just ([true; false;true; true ])
+  else if c = #'C' then Just ([true; true; false;false])
+  else if c = #'c' then Just ([true; true; false;false])
+  else if c = #'D' then Just ([true; true; false;true ])
+  else if c = #'d' then Just ([true; true; false;true ])
+  else if c = #'E' then Just ([true; true; true; false])
+  else if c = #'e' then Just ([true; true; true; false])
+  else if c = #'F' then Just ([true; true; true; true ])
+  else if c = #'f' then Just ([true; true; true; true ])
+  else Nothing
+
+let hexstring_to_bools s =
+  match (toCharList s) with
+    | z :: x :: hs ->
+       let str = if (z = #'0' && x = #'x') then hs else z :: x :: hs in
+       Maybe.map List.concat (just_list (List.map hexchar_to_bool_list str))
+    | _ -> Nothing
+  end
+
+val hex_slice : forall 'rv 'e. string -> integer -> integer -> monad 'rv (list bitU) 'e
+let hex_slice v len lo =
+  match hexstring_to_bools v with
+    | Just bs ->
+       let hi = len + lo - 1 in
+       let bs = ext_list false (len + lo) bs in
+       return (of_bools (subrange_list false bs hi lo))
+    | Nothing -> Fail "hex_slice"
+  end
+*)
+Axiom hex_slice : forall {rv e}, string -> forall n m, monad rv (mword (n - m)) e.
+
+Definition internal_pick {rv a e} (vs : list a) : monad rv a e :=
+match vs with
+| (h::_) => returnm h
+| _ => Fail "empty list in internal_pick"
+end.
+Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string.
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+Definition undefined_vector {rv a e} len (u : a) : monad rv (list a) e := returnm (repeat (cons u nil) len).
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bits {rv e} := @undefined_bitvector rv e.
+Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU.
+(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*)
+Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i).
+Definition undefined_atom {rv e} i : monad rv Z e := returnm i.
+Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+
+(*
+(* Use constants for undefined values for now *)
+let undefined_string () = return ""
+let undefined_unit () = return ()
+let undefined_int () = return (0:ii)
+val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e
+let undefined_vector len u = return (repeat [u] len)
+val undefined_bitvector : forall 'rv 'e. integer -> monad 'rv (list bitU) 'e
+let undefined_bitvector len = return (of_bools (repeat [false] len))
+val undefined_bits : forall 'rv 'e. integer -> monad 'rv (list bitU) 'e
+let undefined_bits = undefined_bitvector
+let undefined_bit () = return B0
+let undefined_real () = return (realFromFrac 0 1)
+let undefined_range i j = return i
+let undefined_atom i = return i
+let undefined_nat () = return (0:ii)
+
+val write_ram : forall 'rv 'e.
+  integer -> integer -> list bitU -> list bitU -> list bitU -> monad 'rv unit 'e*)
+Definition write_ram {rv e} addrsize size (hexRAM : mword addrsize) (address : mword addrsize) (value : mword (8 * size)) : monad rv unit e :=
+  write_mem_ea Write_plain address size >>
+  write_mem_val value >>= fun _ =>
+  returnm tt.
+
+(*val read_ram : forall 'rv 'e.
+  integer -> integer -> list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+Definition read_ram {rv e} addrsize size `{ArithFact (size >= 0)} (hexRAM : mword addrsize) (address : mword addrsize) : monad rv (mword (8 * size)) e :=
+  read_mem Read_plain address size.
+
+(*val elf_entry : unit -> integer*)
+Definition elf_entry (_:unit) := 0.
+(*declare ocaml target_rep function elf_entry = `Elf_loader.elf_entry`
+*)
\ No newline at end of file
diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail
index 6ce47ae3..6837c366 100755
--- a/aarch64/prelude.sail
+++ b/aarch64/prelude.sail
@@ -151,9 +151,9 @@ val __SetSlice_int = "set_slice_int" : forall 'w. (atom('w), int, int, bits('w))
 
 val __raw_SetSlice_int : forall 'w. (atom('w), int, int, bits('w)) -> int
 
-val __raw_GetSlice_int = "get_slice_int" : forall 'w. (atom('w), int, int) -> bits('w)
+val __raw_GetSlice_int = "get_slice_int" : forall 'w, 'w >= 0. (atom('w), int, int) -> bits('w)
 
-val __GetSlice_int : forall 'n. (atom('n), int, int) -> bits('n)
+val __GetSlice_int : forall 'n, 'n >= 0. (atom('n), int, int) -> bits('n)
 
 function __GetSlice_int (n, m, o) = __raw_GetSlice_int(n, m, o)
 
diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index ee193865..d18b17bb 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -928,6 +928,7 @@ Ltac unbool_comparisons :=
   | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H
   | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H
   | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H
+  | H:context [andb _ _ = true] |- _ => apply andb_prop in H
   | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H
   | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H
   | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H
-- 
cgit v1.2.3


From af8cb2e2f6a7606b891fb07b3d668e22cc3c759e Mon Sep 17 00:00:00 2001
From: Jon French
Date: Mon, 9 Jul 2018 14:23:19 +0100
Subject: add LOADRES, STORECON, AMO to analysis

---
 riscv/riscv_analysis.sail | 77 +++++++++++++++++++++++------------------------
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/riscv/riscv_analysis.sail b/riscv/riscv_analysis.sail
index 616d8669..84934a25 100644
--- a/riscv/riscv_analysis.sail
+++ b/riscv/riscv_analysis.sail
@@ -135,47 +135,44 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
      FENCEI() => {
               ik = IK_barrier (Barrier_RISCV_i);
      },
-  //    LOADRES(aq, rl, rs1, width, rd) => {
-  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-  //           aR = iR;
-  //           ik = match (aq, rl) {
-  //             (false, false) => IK_mem_read (Read_RISCV_reserved)
-  //             (true,  false) => IK_mem_read (Read_RISCV_reserved_acquire_RCsc)
-  //             (true,  true)  => IK_mem_read (Read_RISCV_reserved_acquire_release)
-
-  //             (false, true)  => exit "not implemented"
-  //           };
-  //    },
-  //    STORECON(aq, rl, rs2, rs1, width, rd) => {
-  //           if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-  //           if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
-  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
-
-  //           ik = switch (aq, rl) {
-  //             case (false, false) -> IK_mem_write (Write_RISCV_conditional)
-  //             case (false, true)  -> IK_mem_write (Write_RISCV_conditional_release_RCsc)
-  //             case (true,  true)  -> IK_mem_write (Write_RISCV_conditional_acquire_release)
-
-  //             case (true,  false) -> exit "not implemented"
-  //           };
-  //    }
-  //    AMO(op, aq, rl, rs2, rs1, width, rd) => {
-  //           if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
-  //           if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
-  //           if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
-  //           if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+     LOADRES(aq, rl, rs1, width, rd) => {
+            if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+            aR = iR;
+            ik = match (aq, rl) {
+              (false, false) => IK_mem_read (Read_RISCV_reserved),
+              (true,  false) => IK_mem_read (Read_RISCV_reserved_acquire),
+              (true,  true)  => IK_mem_read (Read_RISCV_reserved_strong_acquire),
+              (false, true)  => internal_error("LOADRES type not implemented in initial_analysis")
+            };
+     },
+     STORECON(aq, rl, rs2, rs1, width, rd) => {
+            if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+            if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+            if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
+            if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+             ik = match (aq, rl) {
+               (false, false) => IK_mem_write (Write_RISCV_conditional),
+               (false, true)  => IK_mem_write (Write_RISCV_conditional_release),
+               (true,  true)  => IK_mem_write (Write_RISCV_conditional_strong_release),
 
-  //           ik = switch (aq, rl) {
-  //             (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional)
-  //             (false, true)  => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release_RCsc)
-  //             (true,  false) => IK_mem_rmw (Read_RISCV_reserved_acquire_RCsc,
-  //                                                                     Write_RISCV_conditional)
-  //             (true,  true)  => IK_mem_rmw (Read_RISCV_reserved_acquire_RCsc,
-  //                                                                     Write_RISCV_conditional_release_RCsc)
-  //           };
-  //    }
+               (true,  false) => internal_error("STORECON type not implemented in initial_analysis")
+             };
+      },
+      AMO(op, aq, rl, rs2, rs1, width, rd) => {
+             if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
+             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+             if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
+             if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+             ik = match (aq, rl) {
+               (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional),
+               (false, true)  => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release),
+               (true,  false) => IK_mem_rmw (Read_RISCV_reserved_acquire,
+                                                                       Write_RISCV_conditional),
+               (true,  true)  => IK_mem_rmw (Read_RISCV_reserved_acquire,
+                                                                       Write_RISCV_conditional_release)
+             };
+      },
         _ => ()
   };
   (iR,oR,aR,Nias,Dia,ik)
-- 
cgit v1.2.3


From a6770dbaf3231a8a8050cea588eb186ab8b36a77 Mon Sep 17 00:00:00 2001
From: Jon French
Date: Mon, 9 Jul 2018 14:24:19 +0100
Subject: add riscv_analysis.sail to SAIL_SRCS

---
 riscv/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/Makefile b/riscv/Makefile
index 621754b8..68272112 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -1,4 +1,4 @@
-SAIL_SRCS = prelude.sail riscv_types.sail riscv_sys.sail riscv_platform.sail riscv_mem.sail riscv_vmem.sail riscv.sail riscv_step.sail
+SAIL_SRCS = prelude.sail riscv_types.sail riscv_sys.sail riscv_platform.sail riscv_mem.sail riscv_vmem.sail riscv.sail riscv_step.sail riscv_analysis.sail
 PLATFORM_OCAML_SRCS = platform.ml platform_impl.ml platform_main.ml
 SAIL_DIR ?= $(realpath ..)
 SAIL ?= $(SAIL_DIR)/sail
-- 
cgit v1.2.3


From edc2be164fcf53c333796e55b93f94bf6c9ed152 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Fri, 22 Jun 2018 19:03:02 +0100
Subject: Simplify treating of undefined_bool in Lem library

Use nondeterministic choice by default instead of a deterministic bitstream
generator in the state, which is slightly awkward to reason about, because
every use of undefined_boolS changes the state.  The previous behaviour can be
implemented as Sail code, if desired.

Also add a default implementation of internal_pick that nondeterministically
chooses an element from a list.
---
 aarch64/aarch64_extras.lem                     |  2 -
 aarch64/mono/aarch64_extras.lem                |  4 +-
 lib/hol/prompt.lem                             |  8 ++--
 lib/isabelle/Hoare.thy                         | 20 +++++++++
 lib/isabelle/Sail2_operators_mwords_lemmas.thy | 38 ++++++++--------
 lib/isabelle/Sail2_prompt_monad_lemmas.thy     |  4 +-
 lib/isabelle/Sail2_state_lemmas.thy            | 34 +++++++++++++-
 lib/isabelle/Sail2_state_monad_lemmas.thy      |  3 ++
 lib/isabelle/manual/Manual.thy                 |  7 +--
 mips/mips_extras.lem                           |  1 -
 src/gen_lib/sail2_operators_bitlists.lem       | 56 +++++++++++------------
 src/gen_lib/sail2_operators_mwords.lem         | 62 +++++++++++++-------------
 src/gen_lib/sail2_prompt.lem                   | 32 ++++++++-----
 src/gen_lib/sail2_prompt_monad.lem             |  1 +
 src/gen_lib/sail2_state.lem                    | 32 ++++++++-----
 src/gen_lib/sail2_state_monad.lem              | 18 +++-----
 test/builtins/test_extras.lem                  |  3 --
 test/hol/test_raw_addScript.sml                |  6 +--
 test/isabelle/Aarch64_code.thy                 |  2 +-
 19 files changed, 195 insertions(+), 138 deletions(-)

diff --git a/aarch64/aarch64_extras.lem b/aarch64/aarch64_extras.lem
index a8bc6431..d22ece00 100644
--- a/aarch64/aarch64_extras.lem
+++ b/aarch64/aarch64_extras.lem
@@ -58,8 +58,6 @@ let hex_slice v len lo =
     | Nothing -> Fail "hex_slice"
   end
 
-let internal_pick vs = return (head vs)
-
 (* Use constants for undefined values for now *)
 let undefined_string () = return ""
 let undefined_unit () = return ()
diff --git a/aarch64/mono/aarch64_extras.lem b/aarch64/mono/aarch64_extras.lem
index 1e91dd31..ffc8baf0 100644
--- a/aarch64/mono/aarch64_extras.lem
+++ b/aarch64/mono/aarch64_extras.lem
@@ -61,9 +61,7 @@ let hex_slice v len lo =
 val BigEndianReverse : forall 'rv 'n 'e. Size 'n => mword 'n -> monad 'rv (mword 'n) 'e
 let BigEndianReverse w = return (reverse_endianness w)
 
-let internal_pick vs = return (head vs)
-
-(* Use constants for undefined values for now *)
+(* Use constants for some undefined values for now *)
 let undefined_string () = return ""
 let undefined_unit () = return ()
 let undefined_int () = return (0:ii)
diff --git a/lib/hol/prompt.lem b/lib/hol/prompt.lem
index edbd3752..3597fa06 100644
--- a/lib/hol/prompt.lem
+++ b/lib/hol/prompt.lem
@@ -3,12 +3,12 @@ open import State_monad
 open import State
 
 let inline undefined_bool = undefined_boolS
-let inline bool_of_bitU_oracle = bool_of_bitU_oracleS
+let inline bool_of_bitU_nondet = bool_of_bitU_nondetS
 let inline bool_of_bitU_fail = bool_of_bitU_fail
-let inline bools_of_bits_oracle = bools_of_bits_oracleS
-let inline of_bits_oracle = of_bits_oracleS
+let inline bools_of_bits_nondet = bools_of_bits_nondetS
+let inline of_bits_nondet = of_bits_nondetS
 let inline of_bits_fail = of_bits_failS
-let inline mword_oracle = mword_oracleS
+let inline mword_nondet = mword_nondetS
 let inline reg_deref = read_regS
 
 let inline foreachM = foreachS
diff --git a/lib/isabelle/Hoare.thy b/lib/isabelle/Hoare.thy
index 5c77c5e7..afa953be 100644
--- a/lib/isabelle/Hoare.thy
+++ b/lib/isabelle/Hoare.thy
@@ -363,4 +363,24 @@ lemma PrePostE_foreachS_invariant:
   using assms unfolding PrePostE_def
   by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto
 
+lemma PrePostE_bool_of_bitU_nondetS_any:
+  "PrePostE (\<lambda>s. \<forall>b. Q b s) (bool_of_bitU_nondetS b) Q E"
+  unfolding bool_of_bitU_nondetS_def undefined_boolS_def
+  by (cases b; simp; rule PrePostE_strengthen_pre, rule PrePostE_atomI) auto
+
+lemma PrePostE_bools_of_bits_nondetS_any:
+  "PrePostE (\<lambda>s. \<forall>bs. Q bs s) (bools_of_bits_nondetS bs) Q E"
+  unfolding bools_of_bits_nondetS_def
+  by (rule PrePostE_weaken_post[where B = "\<lambda>_ s. \<forall>bs. Q bs s"], rule PrePostE_strengthen_pre,
+      (rule PrePostE_foreachS_invariant[OF PrePostE_strengthen_pre] PrePostE_bindS PrePostE_returnS
+            PrePostE_bool_of_bitU_nondetS_any)+)
+     auto
+
+lemma PrePostE_internal_pick:
+  "xs \<noteq> [] \<Longrightarrow> PrePostE (\<lambda>s. \<forall>x \<in> set xs. Q x s) (internal_pickS xs) Q E"
+  unfolding internal_pickS_def Let_def
+  by (rule PrePostE_strengthen_pre,
+      (rule PrePostE_compositeI PrePostE_atomI PrePostE_bools_of_bits_nondetS_any)+)
+     (auto split: option.splits)
+
 end
diff --git a/lib/isabelle/Sail2_operators_mwords_lemmas.thy b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
index ae8802f2..2a6272c2 100644
--- a/lib/isabelle/Sail2_operators_mwords_lemmas.thy
+++ b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
@@ -2,14 +2,14 @@ theory Sail2_operators_mwords_lemmas
   imports Sail2_operators_mwords
 begin
 
-lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_oracle_def
-lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_oracle_def
+lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_nondet_def
+lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_nondet_def
 
-lemma bools_of_bits_oracle_just_list[simp]:
+lemma bools_of_bits_nondet_just_list[simp]:
   assumes "just_list (map bool_of_bitU bus) = Some bs"
-  shows "bools_of_bits_oracle bus = return bs"
+  shows "bools_of_bits_nondet bus = return bs"
 proof -
-  have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_oracle b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)"
+  have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_nondet b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)"
     if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools
   proof (use that in \<open>induction bus arbitrary: bs bools\<close>)
     case (Cons bu bus bs)
@@ -17,26 +17,26 @@ proof -
       using Cons.prems by (cases bu) (auto split: option.splits)
     then show ?case
       using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"]
-      by (cases bu) (auto simp: bool_of_bitU_oracle_def split: option.splits)
+      by (cases bu) (auto simp: bool_of_bitU_nondet_def split: option.splits)
   qed auto
-  then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_oracle_def
+  then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_nondet_def
     by auto
 qed
 
 lemma of_bits_mword_return_of_bl[simp]:
   assumes "just_list (map bool_of_bitU bus) = Some bs"
-  shows "of_bits_oracle BC_mword bus = return (of_bl bs)"
+  shows "of_bits_nondet BC_mword bus = return (of_bl bs)"
     and "of_bits_fail BC_mword bus = return (of_bl bs)"
-  by (auto simp: of_bits_oracle_def of_bits_fail_def maybe_fail_def assms BC_mword_defs)
+  by (auto simp: of_bits_nondet_def of_bits_fail_def maybe_fail_def assms BC_mword_defs)
 
 lemma vec_of_bits_of_bl[simp]:
   assumes "just_list (map bool_of_bitU bus) = Some bs"
   shows "vec_of_bits_maybe bus = Some (of_bl bs)"
     and "vec_of_bits_fail bus = return (of_bl bs)"
-    and "vec_of_bits_oracle bus = return (of_bl bs)"
+    and "vec_of_bits_nondet bus = return (of_bl bs)"
     and "vec_of_bits_failwith bus = of_bl bs"
     and "vec_of_bits bus = of_bl bs"
-  unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_oracle_def
+  unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_nondet_def
             vec_of_bits_failwith_def vec_of_bits_def
   by (auto simp: assms)
 
@@ -53,10 +53,10 @@ lemma bool_of_bitU_monadic_simps[simp]:
   "bool_of_bitU_fail B0 = return False"
   "bool_of_bitU_fail B1 = return True"
   "bool_of_bitU_fail BU = Fail ''bool_of_bitU''"
-  "bool_of_bitU_oracle B0 = return False"
-  "bool_of_bitU_oracle B1 = return True"
-  "bool_of_bitU_oracle BU = undefined_bool ()"
-  unfolding bool_of_bitU_fail_def bool_of_bitU_oracle_def
+  "bool_of_bitU_nondet B0 = return False"
+  "bool_of_bitU_nondet B1 = return True"
+  "bool_of_bitU_nondet BU = undefined_bool ()"
+  unfolding bool_of_bitU_fail_def bool_of_bitU_nondet_def
   by auto
 
 lemma update_vec_dec_simps[simp]:
@@ -66,12 +66,12 @@ lemma update_vec_dec_simps[simp]:
   "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)"
   "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)"
   "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''"
-  "update_vec_dec_oracle w i B0 = return (set_bit w (nat i) False)"
-  "update_vec_dec_oracle w i B1 = return (set_bit w (nat i) True)"
-  "update_vec_dec_oracle w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))"
+  "update_vec_dec_nondet w i B0 = return (set_bit w (nat i) False)"
+  "update_vec_dec_nondet w i B1 = return (set_bit w (nat i) True)"
+  "update_vec_dec_nondet w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))"
   "update_vec_dec w i B0 = set_bit w (nat i) False"
   "update_vec_dec w i B1 = set_bit w (nat i) True"
-  unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_oracle_def update_vec_dec_def
+  unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_nondet_def update_vec_dec_def
   by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def)
 
 lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]:
diff --git a/lib/isabelle/Sail2_prompt_monad_lemmas.thy b/lib/isabelle/Sail2_prompt_monad_lemmas.thy
index 08c9b33c..3ca1729f 100644
--- a/lib/isabelle/Sail2_prompt_monad_lemmas.thy
+++ b/lib/isabelle/Sail2_prompt_monad_lemmas.thy
@@ -64,7 +64,7 @@ inductive_set T :: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a, '
 | Barrier: "((Barrier bk k), e_barrier bk, k) \<in> T"
 | Read_reg: "((Read_reg r k), e_read_reg r v, k v) \<in> T"
 | Write_reg: "((Write_reg r v k), e_write_reg r v, k) \<in> T"
-| Undefined : "((Undefined k), e_undefined v, k v) \<in> T"
+| Undefined: "((Undefined k), e_undefined v, k v) \<in> T"
 | Print: "((Print msg k), e_print msg, k) \<in> T"
 
 inductive_set Traces :: "(('rv, 'a, 'e) monad \<times> 'rv event list \<times> ('rv, 'a, 'e) monad) set" where
@@ -95,7 +95,7 @@ lemma Traces_cases:
   | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = e_write_ea wk addr s # t'" and "(k, t', m') \<in> Traces"
   | (Footprint) k t' where "m = Footprint k" and "t = e_footprint # t'" and "(k, t', m') \<in> Traces"
   | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = e_write_reg reg v # t'" and "(k, t', m') \<in> Traces"
-  | (Undefined) v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces"
+  | (Undefined) xs v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces"
   | (Print) msg k t' where "m = Print msg k" and "t = e_print msg # t'" and "(k, t', m') \<in> Traces"
 proof (use Run in \<open>cases m t m' set: Traces\<close>)
   case Nil
diff --git a/lib/isabelle/Sail2_state_lemmas.thy b/lib/isabelle/Sail2_state_lemmas.thy
index 124722ab..8f04e850 100644
--- a/lib/isabelle/Sail2_state_lemmas.thy
+++ b/lib/isabelle/Sail2_state_lemmas.thy
@@ -23,6 +23,22 @@ lemma Value_liftState_Run:
 
 lemmas liftState_if_distrib[liftState_simp] = if_distrib[where f = "liftState ra" for ra]
 
+lemma member_set_nth:
+  assumes "x \<in> set xs"
+  obtains n where "x = xs ! n" and "n < length xs"
+proof (use assms in \<open>induction xs arbitrary: thesis\<close>)
+  case (Cons a xs) print_cases
+  show ?case proof cases
+    assume "x = a"
+    then show ?thesis using Cons(2)[where n = 0] Cons(3) by auto
+  next
+    assume "x \<noteq> a"
+    then obtain n where "x = xs ! n" and "n < length xs" using Cons by auto
+    then show ?thesis using Cons(2)[of "Suc n"] by auto
+  qed
+qed auto
+
+
 lemma liftState_throw[liftState_simp]: "liftState r (throw e) = throwS e"
   by (auto simp: throw_def)
 lemma liftState_assert[liftState_simp]: "liftState r (assert_exp c msg) = assert_expS c msg"
@@ -66,6 +82,10 @@ lemma liftState_try_catchR[liftState_simp]:
   "liftState r (try_catchR m h) = try_catchRS (liftState r m) (liftState r \<circ> h)"
   by (auto simp: try_catchR_def try_catchRS_def sum.case_distrib liftState_simp cong: sum.case_cong)
 
+lemma liftState_bool_of_bitU_nondet[liftState_simp]:
+  "liftState r (bool_of_bitU_nondet b) = bool_of_bitU_nondetS b"
+  by (cases b; auto simp: bool_of_bitU_nondet_def bool_of_bitU_nondetS_def liftState_simp)
+
 lemma liftState_read_mem_BC:
   assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a"
   shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz"
@@ -87,7 +107,7 @@ lemma liftState_write_mem_ea[liftState_simp]:
   "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)"
   by (auto simp: liftState_write_mem_ea_BC)
 
-lemma liftState_write_mem_val:
+lemma liftState_write_mem_val[liftState_simp]:
   "liftState r (write_mem_val BC v) = write_mem_valS BC v"
   by (auto simp: write_mem_val_def write_mem_valS_def liftState_simp split: option.splits)
 
@@ -126,6 +146,18 @@ lemma liftState_foreachM[liftState_simp]:
   by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct)
      (auto simp: liftState_simp cong: bindS_cong)
 
+lemma liftState_bools_of_bits_nondet[liftState_simp]:
+  "liftState r (bools_of_bits_nondet bs) = bools_of_bits_nondetS bs"
+  unfolding bools_of_bits_nondet_def bools_of_bits_nondetS_def
+  by (auto simp: liftState_simp comp_def)
+
+lemma liftState_internal_pick[liftState_simp]:
+  "liftState r (internal_pick xs) = internal_pickS xs"
+  by (auto simp: internal_pick_def internal_pickS_def liftState_simp comp_def
+                 option.case_distrib[where h = "liftState r"]
+           simp del: repeat.simps
+           cong: option.case_cong)
+
 lemma whileS_dom_step:
   assumes "whileS_dom (vars, cond, body, s)"
     and "(Value True, s') \<in> cond vars s"
diff --git a/lib/isabelle/Sail2_state_monad_lemmas.thy b/lib/isabelle/Sail2_state_monad_lemmas.thy
index b705de4c..91e4c17e 100644
--- a/lib/isabelle/Sail2_state_monad_lemmas.thy
+++ b/lib/isabelle/Sail2_state_monad_lemmas.thy
@@ -35,6 +35,9 @@ lemma bindS_updateS: "bindS (updateS f) m = (\<lambda>s. m () (f s))"
 lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()"
   by (auto simp: assert_expS_def)
 
+lemma bindS_chooseS_returnS[simp]: "bindS (chooseS xs) (\<lambda>x. returnS (f x)) = chooseS (f ` xs)"
+  by (intro ext) (auto simp: bindS_def chooseS_def returnS_def)
+
 
 lemma result_cases:
   fixes r :: "('a, 'e) result"
diff --git a/lib/isabelle/manual/Manual.thy b/lib/isabelle/manual/Manual.thy
index 6cd90a9a..0d67f6c5 100644
--- a/lib/isabelle/manual/Manual.thy
+++ b/lib/isabelle/manual/Manual.thy
@@ -168,8 +168,8 @@ following variants:
   \<^item> @{term quot_vec_maybe} returns an option type, with
     @{lemma "quot_vec_maybe w 0 = None" by (auto simp: quot_vec_maybe_def quot_bv_def arith_op_bv_no0_def)}.
   \<^item> @{term quot_vec_fail} is monadic and either returns the result or raises an exception.
-  \<^item> @{term quot_vec_oracle} is monadic and uses the @{term Undefined} effect in the exception case
-    to fill the result with bits drawn from a bitstream oracle.
+  \<^item> @{term quot_vec_nondet} is monadic and uses the @{term Undefined} effect in the exception case
+    to fill the result with bits chosen nondeterministically.
   \<^item> @{term quot_vec} is pure and returns an arbitrary (but fixed) value in the exception case,
     currently defined as follows:  For the bitlist representation of bitvectors,
     @{term "quot_vec w 0"} returns a list filled with @{term BU}, while for the machine word
@@ -263,9 +263,6 @@ The @{type sequential_state} record has the following fields:
     of the last announced memory write, if any.
   \<^item> The @{term last_exclusive_operation_was_load} flag is used to determine whether exclusive
     operations can succeed.
-  \<^item> The function stored in the @{term next_bool} field together with the seed in the @{term seed}
-    field are used as a random bit generator for undefined values.  The @{term next_bool}
-    function takes the current seed as an argument and returns a @{type bool} and the next seed.
 
 The library defines several combinators and wrappers in addition to the standard monadic bind and
 return (called @{term bindS} and @{term returnS} here, where the suffix @{term S} differentiates them
diff --git a/mips/mips_extras.lem b/mips/mips_extras.lem
index 2e07586c..86e78586 100644
--- a/mips/mips_extras.lem
+++ b/mips/mips_extras.lem
@@ -90,7 +90,6 @@ let shift_bits_right_arith v n =
   maybe_fail "shift_bits_right_arith" r
 
 (* Use constants for undefined values for now *)
-let internal_pick vs = return (head vs)
 let undefined_string () = return ""
 let undefined_unit () = return ()
 let undefined_int () = return (0:ii)
diff --git a/src/gen_lib/sail2_operators_bitlists.lem b/src/gen_lib/sail2_operators_bitlists.lem
index 3f8b7510..0c833e90 100644
--- a/src/gen_lib/sail2_operators_bitlists.lem
+++ b/src/gen_lib/sail2_operators_bitlists.lem
@@ -10,16 +10,16 @@ open import Sail2_prompt
 val uint_maybe : list bitU -> maybe integer
 let uint_maybe v = unsigned v
 let uint_fail v = maybe_fail "uint" (unsigned v)
-let uint_oracle v =
-  bools_of_bits_oracle v >>= (fun bs ->
+let uint_nondet v =
+  bools_of_bits_nondet v >>= (fun bs ->
   return (int_of_bools false bs))
 let uint v = maybe_failwith (uint_maybe v)
 
 val sint_maybe : list bitU -> maybe integer
 let sint_maybe v = signed v
 let sint_fail v = maybe_fail "sint" (signed v)
-let sint_oracle v =
-  bools_of_bits_oracle v >>= (fun bs ->
+let sint_nondet v =
+  bools_of_bits_nondet v >>= (fun bs ->
   return (int_of_bools true bs))
 let sint v = maybe_failwith (sint_maybe v)
 
@@ -43,13 +43,13 @@ let vector_truncate bs len = extz_bv len bs
 
 val vec_of_bits_maybe    : list bitU -> maybe (list bitU)
 val vec_of_bits_fail     : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e
-val vec_of_bits_oracle   : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e
+val vec_of_bits_nondet   : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e
 val vec_of_bits_failwith : list bitU -> list bitU
 val vec_of_bits          : list bitU -> list bitU
 let inline vec_of_bits bits = bits
 let inline vec_of_bits_maybe bits = Just bits
 let inline vec_of_bits_fail bits = return bits
-let inline vec_of_bits_oracle bits = return bits
+let inline vec_of_bits_nondet bits = return bits
 let inline vec_of_bits_failwith bits = bits
 
 val access_vec_inc : list bitU -> integer -> bitU
@@ -62,13 +62,13 @@ val update_vec_inc : list bitU -> integer -> bitU -> list bitU
 let update_vec_inc = update_bv_inc
 let update_vec_inc_maybe v i b = Just (update_vec_inc v i b)
 let update_vec_inc_fail v i b = return (update_vec_inc v i b)
-let update_vec_inc_oracle v i b = return (update_vec_inc v i b)
+let update_vec_inc_nondet v i b = return (update_vec_inc v i b)
 
 val update_vec_dec : list bitU -> integer -> bitU -> list bitU
 let update_vec_dec = update_bv_dec
 let update_vec_dec_maybe v i b = Just (update_vec_dec v i b)
 let update_vec_dec_fail v i b = return (update_vec_dec v i b)
-let update_vec_dec_oracle v i b = return (update_vec_dec v i b)
+let update_vec_dec_nondet v i b = return (update_vec_dec v i b)
 
 val subrange_vec_inc : list bitU -> integer -> integer -> list bitU
 let subrange_vec_inc = subrange_bv_inc
@@ -89,19 +89,19 @@ val cons_vec : bitU -> list bitU -> list bitU
 let cons_vec = cons_bv
 let cons_vec_maybe b v = Just (cons_vec b v)
 let cons_vec_fail b v = return (cons_vec b v)
-let cons_vec_oracle b v = return (cons_vec b v)
+let cons_vec_nondet b v = return (cons_vec b v)
 
 val cast_unit_vec : bitU -> list bitU
 let cast_unit_vec = cast_unit_bv
 let cast_unit_vec_maybe b = Just (cast_unit_vec b)
 let cast_unit_vec_fail b = return (cast_unit_vec b)
-let cast_unit_vec_oracle b = return (cast_unit_vec b)
+let cast_unit_vec_nondet b = return (cast_unit_vec b)
 
 val vec_of_bit : integer -> bitU -> list bitU
 let vec_of_bit = bv_of_bit
 let vec_of_bit_maybe len b = Just (vec_of_bit len b)
 let vec_of_bit_fail len b = return (vec_of_bit len b)
-let vec_of_bit_oracle len b = return (vec_of_bit len b)
+let vec_of_bit_nondet len b = return (vec_of_bit len b)
 
 val msb : list bitU -> bitU
 let msb = most_significant
@@ -109,7 +109,7 @@ let msb = most_significant
 val int_of_vec_maybe : bool -> list bitU -> maybe integer
 let int_of_vec_maybe = int_of_bv
 let int_of_vec_fail sign v = maybe_fail "int_of_vec" (int_of_vec_maybe sign v)
-let int_of_vec_oracle sign v = bools_of_bits_oracle v >>= (fun v -> return (int_of_bools sign v))
+let int_of_vec_nondet sign v = bools_of_bits_nondet v >>= (fun v -> return (int_of_bools sign v))
 let int_of_vec sign v = maybe_failwith (int_of_vec_maybe sign v)
 
 val string_of_bits : list bitU -> string
@@ -179,25 +179,25 @@ val subs_vec_bit     : list bitU -> bitU -> list bitU
 let add_vec_bool       l r = arith_op_bv_bool integerAdd false l r
 let add_vec_bit_maybe  l r = arith_op_bv_bit integerAdd false l r
 let add_vec_bit_fail   l r = maybe_fail "add_vec_bit" (add_vec_bit_maybe l r)
-let add_vec_bit_oracle l r = bool_of_bitU_oracle r >>= (fun r -> return (add_vec_bool l r))
+let add_vec_bit_nondet l r = bool_of_bitU_nondet r >>= (fun r -> return (add_vec_bool l r))
 let add_vec_bit        l r = fromMaybe (repeat [BU] (length l)) (add_vec_bit_maybe l r)
 
 let adds_vec_bool       l r = arith_op_bv_bool integerAdd true l r
 let adds_vec_bit_maybe  l r = arith_op_bv_bit integerAdd true l r
 let adds_vec_bit_fail   l r = maybe_fail "adds_vec_bit" (adds_vec_bit_maybe l r)
-let adds_vec_bit_oracle l r = bool_of_bitU_oracle r >>= (fun r -> return (adds_vec_bool l r))
+let adds_vec_bit_nondet l r = bool_of_bitU_nondet r >>= (fun r -> return (adds_vec_bool l r))
 let adds_vec_bit        l r = fromMaybe (repeat [BU] (length l)) (adds_vec_bit_maybe l r)
 
 let sub_vec_bool        l r = arith_op_bv_bool integerMinus false l r
 let sub_vec_bit_maybe   l r = arith_op_bv_bit integerMinus false l r
 let sub_vec_bit_fail    l r = maybe_fail "sub_vec_bit" (sub_vec_bit_maybe l r)
-let sub_vec_bit_oracle  l r = bool_of_bitU_oracle r >>= (fun r -> return (sub_vec_bool l r))
+let sub_vec_bit_nondet  l r = bool_of_bitU_nondet r >>= (fun r -> return (sub_vec_bool l r))
 let sub_vec_bit         l r = fromMaybe (repeat [BU] (length l)) (sub_vec_bit_maybe l r)
 
 let subs_vec_bool       l r = arith_op_bv_bool integerMinus true l r
 let subs_vec_bit_maybe  l r = arith_op_bv_bit integerMinus true l r
 let subs_vec_bit_fail   l r = maybe_fail "sub_vec_bit" (subs_vec_bit_maybe l r)
-let subs_vec_bit_oracle l r = bool_of_bitU_oracle r >>= (fun r -> return (subs_vec_bool l r))
+let subs_vec_bit_nondet l r = bool_of_bitU_nondet r >>= (fun r -> return (subs_vec_bool l r))
 let subs_vec_bit        l r = fromMaybe (repeat [BU] (length l)) (subs_vec_bit_maybe l r)
 
 (*val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
@@ -236,47 +236,47 @@ let rotr         = rotr_bv
 val mod_vec        : list bitU -> list bitU -> list bitU
 val mod_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)
 val mod_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
-val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
+val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
 let mod_vec        l r = fromMaybe (repeat [BU] (length l)) (mod_bv l r)
 let mod_vec_maybe  l r = mod_bv l r
 let mod_vec_fail   l r = maybe_fail "mod_vec" (mod_bv l r)
-let mod_vec_oracle l r = of_bits_oracle (mod_vec l r)
+let mod_vec_nondet l r = of_bits_nondet (mod_vec l r)
 
 val quot_vec        : list bitU -> list bitU -> list bitU
 val quot_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)
 val quot_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
-val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
+val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
 let quot_vec        l r = fromMaybe (repeat [BU] (length l)) (quot_bv l r)
 let quot_vec_maybe  l r = quot_bv l r
 let quot_vec_fail   l r = maybe_fail "quot_vec" (quot_bv l r)
-let quot_vec_oracle l r = of_bits_oracle (quot_vec l r)
+let quot_vec_nondet l r = of_bits_nondet (quot_vec l r)
 
 val quots_vec        : list bitU -> list bitU -> list bitU
 val quots_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)
 val quots_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
-val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
+val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e
 let quots_vec        l r = fromMaybe (repeat [BU] (length l)) (quots_bv l r)
 let quots_vec_maybe  l r = quots_bv l r
 let quots_vec_fail   l r = maybe_fail "quots_vec" (quots_bv l r)
-let quots_vec_oracle l r = of_bits_oracle (quots_vec l r)
+let quots_vec_nondet l r = of_bits_nondet (quots_vec l r)
 
 val mod_vec_int        : list bitU -> integer -> list bitU
 val mod_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)
 val mod_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e
-val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e
+val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e
 let mod_vec_int        l r = fromMaybe (repeat [BU] (length l)) (mod_bv_int l r)
 let mod_vec_int_maybe  l r = mod_bv_int l r
 let mod_vec_int_fail   l r = maybe_fail "mod_vec_int" (mod_bv_int l r)
-let mod_vec_int_oracle l r = of_bits_oracle (mod_vec_int l r)
+let mod_vec_int_nondet l r = of_bits_nondet (mod_vec_int l r)
 
 val quot_vec_int        : list bitU -> integer -> list bitU
 val quot_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)
 val quot_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e
-val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e
+val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e
 let quot_vec_int        l r = fromMaybe (repeat [BU] (length l)) (quot_bv_int l r)
 let quot_vec_int_maybe  l r = quot_bv_int l r
 let quot_vec_int_fail   l r = maybe_fail "quot_vec_int" (quot_bv_int l r)
-let quot_vec_int_oracle l r = of_bits_oracle (quot_vec_int l r)
+let quot_vec_int_nondet l r = of_bits_nondet (quot_vec_int l r)
 
 val replicate_bits : list bitU -> integer -> list bitU
 let replicate_bits = replicate_bits_bv
@@ -285,8 +285,8 @@ val duplicate : bitU -> integer -> list bitU
 let duplicate = duplicate_bit_bv
 let duplicate_maybe b n = Just (duplicate b n)
 let duplicate_fail b n = return (duplicate b n)
-let duplicate_oracle b n =
-  bool_of_bitU_oracle b >>= (fun b ->
+let duplicate_nondet b n =
+  bool_of_bitU_nondet b >>= (fun b ->
   return (duplicate (bitU_of_bool b) n))
 
 val reverse_endianness : list bitU -> list bitU
diff --git a/src/gen_lib/sail2_operators_mwords.lem b/src/gen_lib/sail2_operators_mwords.lem
index 1e4d63ba..61048ac5 100644
--- a/src/gen_lib/sail2_operators_mwords.lem
+++ b/src/gen_lib/sail2_operators_mwords.lem
@@ -10,21 +10,21 @@ open import Sail2_prompt
 let inline uint v = unsignedIntegerFromWord v
 let uint_maybe v = Just (uint v)
 let uint_fail v = return (uint v)
-let uint_oracle v = return (uint v)
+let uint_nondet v = return (uint v)
 
 let inline sint v = signedIntegerFromWord v
 let sint_maybe v = Just (sint v)
 let sint_fail v = return (sint v)
-let sint_oracle v = return (sint v)
+let sint_nondet v = return (sint v)
 
 val vec_of_bits_maybe    : forall 'a. Size 'a => list bitU -> maybe (mword 'a)
 val vec_of_bits_fail     : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e
-val vec_of_bits_oracle   : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e
+val vec_of_bits_nondet   : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e
 val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a
 val vec_of_bits          : forall 'a. Size 'a => list bitU -> mword 'a
 let vec_of_bits_maybe bits = of_bits bits
 let vec_of_bits_fail bits = of_bits_fail bits
-let vec_of_bits_oracle bits = of_bits_oracle bits
+let vec_of_bits_nondet bits = of_bits_nondet bits
 let vec_of_bits_failwith bits = of_bits_failwith bits
 let vec_of_bits bits = of_bits_failwith bits
 
@@ -38,8 +38,8 @@ let update_vec_dec_maybe w i b = update_mword_dec w i b
 let update_vec_dec_fail w i b =
   bool_of_bitU_fail b >>= (fun b ->
   return (update_mword_bool_dec w i b))
-let update_vec_dec_oracle w i b =
-  bool_of_bitU_oracle b >>= (fun b ->
+let update_vec_dec_nondet w i b =
+  bool_of_bitU_nondet b >>= (fun b ->
   return (update_mword_bool_dec w i b))
 let update_vec_dec w i b = maybe_failwith (update_vec_dec_maybe w i b)
 
@@ -47,8 +47,8 @@ let update_vec_inc_maybe w i b = update_mword_inc w i b
 let update_vec_inc_fail w i b =
   bool_of_bitU_fail b >>= (fun b ->
   return (update_mword_bool_inc w i b))
-let update_vec_inc_oracle w i b =
-  bool_of_bitU_oracle b >>= (fun b ->
+let update_vec_inc_nondet w i b =
+  bool_of_bitU_nondet b >>= (fun b ->
   return (update_mword_bool_inc w i b))
 let update_vec_inc w i b = maybe_failwith (update_vec_inc_maybe w i b)
 
@@ -89,21 +89,21 @@ val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mwo
 let cons_vec_bool b w = wordFromBitlist (b :: bitlistFromWord w)
 let cons_vec_maybe b w = Maybe.map (fun b -> cons_vec_bool b w) (bool_of_bitU b)
 let cons_vec_fail b w = bool_of_bitU_fail b >>= (fun b -> return (cons_vec_bool b w))
-let cons_vec_oracle b w = bool_of_bitU_oracle b >>= (fun b -> return (cons_vec_bool b w))
+let cons_vec_nondet b w = bool_of_bitU_nondet b >>= (fun b -> return (cons_vec_bool b w))
 let cons_vec b w = maybe_failwith (cons_vec_maybe b w)
 
 val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a
 let vec_of_bool _ b = wordFromBitlist [b]
 let vec_of_bit_maybe len b = Maybe.map (vec_of_bool len) (bool_of_bitU b)
 let vec_of_bit_fail len b = bool_of_bitU_fail b >>= (fun b -> return (vec_of_bool len b))
-let vec_of_bit_oracle len b = bool_of_bitU_oracle b >>= (fun b -> return (vec_of_bool len b))
+let vec_of_bit_nondet len b = bool_of_bitU_nondet b >>= (fun b -> return (vec_of_bool len b))
 let vec_of_bit len b = maybe_failwith (vec_of_bit_maybe len b)
 
 val cast_bool_vec : bool -> mword ty1
 let cast_bool_vec b = vec_of_bool 1 b
 let cast_unit_vec_maybe b = vec_of_bit_maybe 1 b
 let cast_unit_vec_fail b = bool_of_bitU_fail b >>= (fun b -> return (cast_bool_vec b))
-let cast_unit_vec_oracle b = bool_of_bitU_oracle b >>= (fun b -> return (cast_bool_vec b))
+let cast_unit_vec_nondet b = bool_of_bitU_nondet b >>= (fun b -> return (cast_bool_vec b))
 let cast_unit_vec b = maybe_failwith (cast_unit_vec_maybe b)
 
 val msb : forall 'a. Size 'a => mword 'a -> bitU
@@ -176,25 +176,25 @@ val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a
 let add_vec_bool        l r = arith_op_bv_bool integerAdd false l r
 let add_vec_bit_maybe   l r = Maybe.map (add_vec_bool l) (bool_of_bitU r)
 let add_vec_bit_fail    l r = bool_of_bitU_fail r >>= (fun r -> return (add_vec_bool l r))
-let add_vec_bit_oracle  l r = bool_of_bitU_oracle r >>= (fun r -> return (add_vec_bool l r))
+let add_vec_bit_nondet  l r = bool_of_bitU_nondet r >>= (fun r -> return (add_vec_bool l r))
 let add_vec_bit         l r = maybe_failwith (add_vec_bit_maybe  l r)
 
 let adds_vec_bool       l r = arith_op_bv_bool integerAdd true  l r
 let adds_vec_bit_maybe  l r = Maybe.map (adds_vec_bool l) (bool_of_bitU r)
 let adds_vec_bit_fail   l r = bool_of_bitU_fail r >>= (fun r -> return (adds_vec_bool l r))
-let adds_vec_bit_oracle l r = bool_of_bitU_oracle r >>= (fun r -> return (adds_vec_bool l r))
+let adds_vec_bit_nondet l r = bool_of_bitU_nondet r >>= (fun r -> return (adds_vec_bool l r))
 let adds_vec_bit        l r = maybe_failwith (adds_vec_bit_maybe l r)
 
 let sub_vec_bool        l r = arith_op_bv_bool integerMinus false l r
 let sub_vec_bit_maybe   l r = Maybe.map (sub_vec_bool l) (bool_of_bitU r)
 let sub_vec_bit_fail    l r = bool_of_bitU_fail r >>= (fun r -> return (sub_vec_bool l r))
-let sub_vec_bit_oracle  l r = bool_of_bitU_oracle r >>= (fun r -> return (sub_vec_bool l r))
+let sub_vec_bit_nondet  l r = bool_of_bitU_nondet r >>= (fun r -> return (sub_vec_bool l r))
 let sub_vec_bit         l r = maybe_failwith (sub_vec_bit_maybe  l r)
 
 let subs_vec_bool       l r = arith_op_bv_bool integerMinus true  l r
 let subs_vec_bit_maybe  l r = Maybe.map (subs_vec_bool l) (bool_of_bitU r)
 let subs_vec_bit_fail   l r = bool_of_bitU_fail r >>= (fun r -> return (subs_vec_bool l r))
-let subs_vec_bit_oracle l r = bool_of_bitU_oracle r >>= (fun r -> return (subs_vec_bool l r))
+let subs_vec_bit_nondet l r = bool_of_bitU_nondet r >>= (fun r -> return (subs_vec_bool l r))
 let subs_vec_bit        l r = maybe_failwith (subs_vec_bit_maybe  l r)
 
 (* TODO
@@ -238,66 +238,66 @@ let rotr         = rotr_mword
 val mod_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
 val mod_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)
 val mod_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
-val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
+val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
 let mod_vec        l r = mod_mword l r
 let mod_vec_maybe  l r = mod_bv l r
 let mod_vec_fail   l r = maybe_fail "mod_vec" (mod_bv l r)
-let mod_vec_oracle l r =
+let mod_vec_nondet l r =
   match (mod_bv l r) with
     | Just w -> return w
-    | Nothing -> mword_oracle ()
+    | Nothing -> mword_nondet ()
   end
 
 val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
 val quot_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)
 val quot_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
-val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
+val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
 let quot_vec        l r = quot_mword l r
 let quot_vec_maybe  l r = quot_bv l r
 let quot_vec_fail   l r = maybe_fail "quot_vec" (quot_bv l r)
-let quot_vec_oracle l r =
+let quot_vec_nondet l r =
   match (quot_bv l r) with
     | Just w -> return w
-    | Nothing -> mword_oracle ()
+    | Nothing -> mword_nondet ()
   end
 
 val quots_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
 val quots_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)
 val quots_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
-val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
+val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e
 let quots_vec        l r = quots_mword l r
 let quots_vec_maybe  l r = quots_bv l r
 let quots_vec_fail   l r = maybe_fail "quots_vec" (quots_bv l r)
-let quots_vec_oracle l r =
+let quots_vec_nondet l r =
   match (quots_bv l r) with
     | Just w -> return w
-    | Nothing -> mword_oracle ()
+    | Nothing -> mword_nondet ()
   end
 
 val mod_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
 val mod_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)
 val mod_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e
-val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e
+val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e
 let mod_vec_int        l r = mod_mword_int l r
 let mod_vec_int_maybe  l r = mod_bv_int l r
 let mod_vec_int_fail   l r = maybe_fail "mod_vec_int" (mod_bv_int l r)
-let mod_vec_int_oracle l r =
+let mod_vec_int_nondet l r =
   match (mod_bv_int l r) with
     | Just w -> return w
-    | Nothing -> mword_oracle ()
+    | Nothing -> mword_nondet ()
   end
 
 val quot_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
 val quot_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)
 val quot_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e
-val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e
+val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e
 let quot_vec_int        l r = quot_mword_int l r
 let quot_vec_int_maybe  l r = quot_bv_int l r
 let quot_vec_int_fail   l r = maybe_fail "quot_vec_int" (quot_bv_int l r)
-let quot_vec_int_oracle l r =
+let quot_vec_int_nondet l r =
   match (quot_bv_int l r) with
     | Just w -> return w
-    | Nothing -> mword_oracle ()
+    | Nothing -> mword_nondet ()
   end
 
 val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
@@ -307,7 +307,7 @@ val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a
 let duplicate_bool   b n = wordFromBitlist (repeat [b] n)
 let duplicate_maybe  b n = Maybe.map (fun b -> duplicate_bool b n) (bool_of_bitU b)
 let duplicate_fail   b n = bool_of_bitU_fail b >>= (fun b -> return (duplicate_bool b n))
-let duplicate_oracle b n = bool_of_bitU_oracle b >>= (fun b -> return (duplicate_bool b n))
+let duplicate_nondet b n = bool_of_bitU_nondet b >>= (fun b -> return (duplicate_bool b n))
 let duplicate        b n = maybe_failwith (duplicate_maybe b n)
 
 val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a
diff --git a/src/gen_lib/sail2_prompt.lem b/src/gen_lib/sail2_prompt.lem
index 08a47052..e01cc051 100644
--- a/src/gen_lib/sail2_prompt.lem
+++ b/src/gen_lib/sail2_prompt.lem
@@ -51,31 +51,31 @@ let bool_of_bitU_fail = function
   | BU -> Fail "bool_of_bitU"
 end
 
-val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e
-let bool_of_bitU_oracle = function
+val bool_of_bitU_nondet : forall 'rv 'e. bitU -> monad 'rv bool 'e
+let bool_of_bitU_nondet = function
   | B0 -> return false
   | B1 -> return true
   | BU -> undefined_bool ()
 end
 
-val bools_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e
-let bools_of_bits_oracle bits =
+val bools_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e
+let bools_of_bits_nondet bits =
   foreachM bits []
     (fun b bools ->
-      bool_of_bitU_oracle b >>= (fun b ->
+      bool_of_bitU_nondet b >>= (fun b ->
       return (bools ++ [b])))
 
-val of_bits_oracle : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e
-let of_bits_oracle bits =
-  bools_of_bits_oracle bits >>= (fun bs ->
+val of_bits_nondet : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e
+let of_bits_nondet bits =
+  bools_of_bits_nondet bits >>= (fun bs ->
   return (of_bools bs))
 
 val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e
 let of_bits_fail bits = maybe_fail "of_bits" (of_bits bits)
 
-val mword_oracle : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e
-let mword_oracle () =
-  bools_of_bits_oracle (repeat [BU] (integerFromNat size)) >>= (fun bs ->
+val mword_nondet : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e
+let mword_nondet () =
+  bools_of_bits_nondet (repeat [BU] (integerFromNat size)) >>= (fun bs ->
   return (wordFromBitlist bs))
 
 val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
@@ -93,6 +93,16 @@ let rec untilM vars cond body =
   cond vars >>= fun cond_val ->
   if cond_val then return vars else untilM vars cond body
 
+val internal_pick : forall 'rv 'a 'e. list 'a -> monad 'rv 'a 'e
+let internal_pick xs =
+  (* Use sufficiently many undefined bits and convert into an index into the list *)
+  bools_of_bits_nondet (repeat [BU] (length_list xs)) >>= fun bs ->
+  let idx = (natFromNatural (nat_of_bools bs)) mod List.length xs in
+  match index xs idx with
+    | Just x -> return x
+    | Nothing -> Fail "internal_pick"
+  end
+
 (*let write_two_regs r1 r2 vec =
   let is_inc =
     let is_inc_r1 = is_inc_of_reg r1 in
diff --git a/src/gen_lib/sail2_prompt_monad.lem b/src/gen_lib/sail2_prompt_monad.lem
index 745589e2..78b1615e 100644
--- a/src/gen_lib/sail2_prompt_monad.lem
+++ b/src/gen_lib/sail2_prompt_monad.lem
@@ -29,6 +29,7 @@ type monad 'regval 'a 'e =
   | Read_reg of register_name * ('regval -> monad 'regval 'a 'e)
   (* Request to write register *)
   | Write_reg of register_name * 'regval * monad 'regval 'a 'e
+  (* Request to choose a Boolean, e.g. to resolve an undefined bit *)
   | Undefined of (bool -> monad 'regval 'a 'e)
   (* Print debugging or tracing information *)
   | Print of string * monad 'regval 'a 'e
diff --git a/src/gen_lib/sail2_state.lem b/src/gen_lib/sail2_state.lem
index 82ac35d8..f703dead 100644
--- a/src/gen_lib/sail2_state.lem
+++ b/src/gen_lib/sail2_state.lem
@@ -41,31 +41,31 @@ let bool_of_bitU_fail = function
   | BU -> failS "bool_of_bitU"
 end
 
-val bool_of_bitU_oracleS : forall 'rv 'e. bitU -> monadS 'rv bool 'e
-let bool_of_bitU_oracleS = function
+val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e
+let bool_of_bitU_nondetS = function
   | B0 -> returnS false
   | B1 -> returnS true
   | BU -> undefined_boolS ()
 end
 
-val bools_of_bits_oracleS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e
-let bools_of_bits_oracleS bits =
+val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e
+let bools_of_bits_nondetS bits =
   foreachS bits []
     (fun b bools ->
-      bool_of_bitU_oracleS b >>$= (fun b ->
+      bool_of_bitU_nondetS b >>$= (fun b ->
       returnS (bools ++ [b])))
 
-val of_bits_oracleS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e
-let of_bits_oracleS bits =
-  bools_of_bits_oracleS bits >>$= (fun bs ->
+val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e
+let of_bits_nondetS bits =
+  bools_of_bits_nondetS bits >>$= (fun bs ->
   returnS (of_bools bs))
 
 val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e
 let of_bits_failS bits = maybe_failS "of_bits" (of_bits bits)
 
-val mword_oracleS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e
-let mword_oracleS () =
-  bools_of_bits_oracleS (repeat [BU] (integerFromNat size)) >>$= (fun bs ->
+val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e
+let mword_nondetS () =
+  bools_of_bits_nondetS (repeat [BU] (integerFromNat size)) >>$= (fun bs ->
   returnS (wordFromBitlist bs))
 
 
@@ -83,3 +83,13 @@ let rec untilS vars cond body s =
   (body vars >>$= (fun vars s' ->
   (cond vars >>$= (fun cond_val s'' ->
   if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s
+
+val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e
+let internal_pickS xs =
+  (* Use sufficiently many undefined bits and convert into an index into the list *)
+  bools_of_bits_nondetS (repeat [BU] (length_list xs)) >>$= fun bs ->
+  let idx = (natFromNatural (nat_of_bools bs)) mod List.length xs in
+  match index xs idx with
+    | Just x -> returnS x
+    | Nothing -> failS "internal_pick"
+  end
diff --git a/src/gen_lib/sail2_state_monad.lem b/src/gen_lib/sail2_state_monad.lem
index f207699f..30b296cc 100644
--- a/src/gen_lib/sail2_state_monad.lem
+++ b/src/gen_lib/sail2_state_monad.lem
@@ -13,20 +13,15 @@ type sequential_state 'regs =
      memstate : memstate;
      tagstate : tagstate;
      write_ea : maybe (write_kind * integer * integer);
-     last_exclusive_operation_was_load : bool;
-     (* Random bool generator for use as an undefined bit oracle *)
-     next_bool : nat -> (bool * nat);
-     seed : nat |>
+     last_exclusive_operation_was_load : bool |>
 
-val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs
-let init_state regs o s =
+val init_state : forall 'regs. 'regs -> sequential_state 'regs
+let init_state regs =
   <| regstate = regs;
      memstate = Map.empty;
      tagstate = Map.empty;
      write_ea = Nothing;
-     last_exclusive_operation_was_load = false;
-     next_bool = o;
-     seed = s |>
+     last_exclusive_operation_was_load = false |>
 
 type ex 'e =
   | Failure of string
@@ -69,10 +64,7 @@ val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e
 let failS msg s = {(Ex (Failure msg), s)}
 
 val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e
-let undefined_boolS () =
-  readS (fun s -> s.next_bool (s.seed)) >>$= (fun (b, seed) ->
-  updateS (fun s -> <| s with seed = seed |>) >>$
-  returnS b)
+let undefined_boolS () = chooseS {false; true}
 
 val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e
 let exitS () = failS "exit"
diff --git a/test/builtins/test_extras.lem b/test/builtins/test_extras.lem
index 136f680e..ae3ed1ba 100644
--- a/test/builtins/test_extras.lem
+++ b/test/builtins/test_extras.lem
@@ -17,6 +17,3 @@ let undefined_bitvector len = return (zeros(len))
 
 val undefined_unit : forall 'rv 'e. unit -> monad 'rv unit 'e
 let undefined_unit () = return ()
-
-val internal_pick : forall 'rv 'a 'e. list 'a -> monad 'rv 'a 'e
-let internal_pick xs = return (List_extra.head xs)
diff --git a/test/hol/test_raw_addScript.sml b/test/hol/test_raw_addScript.sml
index 1eb90ef8..20465eb2 100644
--- a/test/hol/test_raw_addScript.sml
+++ b/test/hol/test_raw_addScript.sml
@@ -783,7 +783,7 @@ val () = computeLib.extend_compset [
   ]
 ]  cs;
 
-val empty_state = ``init_state initial_regstate bool_oracle seed``;
+val empty_state = ``init_state initial_regstate``;
 
 val init_registers_result =
   ``init_registers vinitPC s``
@@ -927,7 +927,7 @@ install_code_result
 
 val test_raw_add_thm = Q.store_thm("test_raw_add_thm",
   `PrePost
-      (λs. s = init_state initial_regstate bool_oracle seed)
+      (λs. s = init_state initial_regstate)
       (install_and_run test_raw_add_insts 40)
       (λ_ s.  test_raw_add_post s)`,
   rw[PrePost_def]
@@ -1378,7 +1378,7 @@ computeLib.CBV_CONV cs ``decode (EL 1 test_raw_add_insts)``
 
 val th1 = EVAL ``THE (decode (EL 1 test_raw_add_insts))``
 
-val s1 = EVAL ``init_cp0_state () (init_state (regs:regstate) o1 seed)``
+val s1 = EVAL ``init_cp0_state () (init_state (regs:regstate))``
 
 val th2 = ``execute ^(rhs(concl th1)) ^s1``
   |> SIMP_CONV(srw_ss())[execute_def]
diff --git a/test/isabelle/Aarch64_code.thy b/test/isabelle/Aarch64_code.thy
index 05e5bb2e..8a0e1795 100644
--- a/test/isabelle/Aarch64_code.thy
+++ b/test/isabelle/Aarch64_code.thy
@@ -52,7 +52,7 @@ fun write_char_mem :: "int \<Rightarrow> char \<Rightarrow> (regstate, unit, exc
      bindS (write_mem_valS BC_bitU_list (bits_of_nat 8 (nat_of_char c))) (\<lambda>_.
      returnS ()))"
 
-definition "initial_state \<equiv> init_state initial_regstate (\<lambda>seed. (False, seed)) 0"
+definition "initial_state \<equiv> init_state initial_regstate"
 
 code_printing constant elf_entry \<rightharpoonup> (OCaml) "(Int'_of'_integer (Elf'_loader.elf'_entry _))"
 termination BigEndianReverse sorry
-- 
cgit v1.2.3


From 90ea9c794ffe47365b7e856eba4ee8af0aefa0ca Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Sat, 7 Jul 2018 22:20:51 +0100
Subject: Patch some potential uses of uninitialised variables in AArch64

---
 aarch64/mono/demo/aarch64_no_vector/spec.sail | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/aarch64/mono/demo/aarch64_no_vector/spec.sail b/aarch64/mono/demo/aarch64_no_vector/spec.sail
index 19a06c57..ecb3a050 100644
--- a/aarch64/mono/demo/aarch64_no_vector/spec.sail
+++ b/aarch64/mono/demo/aarch64_no_vector/spec.sail
@@ -5713,6 +5713,11 @@ function AArch64_TranslationTableWalk (ipaddress, vaddress, acctype, iswrite, se
     outputaddress = (slice(desc, 12, 4) @ slice(desc, asb, negate(asb) + 48)) @ slice(inputaddr, 0, asb)
   else
     outputaddress = ZeroExtend(slice(desc, asb, negate(asb) + 48) @ slice(inputaddr, 0, asb));
+  __tmp_33 : DescriptorUpdate = result.descupdate;
+  __tmp_33.AF = false;
+  __tmp_33.AP = false;
+  __tmp_33.descaddr = descaddr;
+  result.descupdate = __tmp_33;
   if [desc[10]] == 0b0 then
     if ~(update_AF) then {
       __tmp_29 : AddressDescriptor = result.addrdesc;
@@ -5738,9 +5743,6 @@ function AArch64_TranslationTableWalk (ipaddress, vaddress, acctype, iswrite, se
       result.descupdate = __tmp_32
     } else ()
   else ();
-  __tmp_33 : DescriptorUpdate = result.descupdate;
-  __tmp_33.descaddr = descaddr;
-  result.descupdate = __tmp_33;
   xn : bits(1) = undefined;
   pxn : bits(1) = undefined;
   if apply_nvnv1_effect then {
@@ -6715,7 +6717,7 @@ function AArch64_SecondStageTranslate (S1, vaddress, acctype, iswrite, wasaligne
 function AArch64_CheckAndUpdateDescriptor (result, fault, secondstage, vaddress, acctype, iswrite, s2fs1walk, hwupdatewalk__arg) = {
   hwupdatewalk = hwupdatewalk__arg;
   hw_update_AF : bool = undefined;
-  if result.AF then if fault.typ == Fault_None then hw_update_AF = true else if ConstrainUnpredictable(Unpredictable_AFUPDATE) == Constraint_TRUE then hw_update_AF = true else hw_update_AF = false else ();
+  if result.AF then if fault.typ == Fault_None then hw_update_AF = true else if ConstrainUnpredictable(Unpredictable_AFUPDATE) == Constraint_TRUE then hw_update_AF = true else hw_update_AF = false else hw_update_AF = false;
   hw_update_AP : bool = undefined;
   write_perm_req : bool = undefined;
   if result.AP & fault.typ == Fault_None then {
-- 
cgit v1.2.3


From 2529f5a65d70dfffe40ead73ae49aaa4d78fefb4 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Sat, 7 Jul 2018 22:47:28 +0100
Subject: Add some syntactic sugar for Isabelle

---
 lib/isabelle/Hoare.thy                    | 4 ++--
 lib/isabelle/Sail2_state_monad_lemmas.thy | 3 +++
 src/state.ml                              | 6 +++---
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/lib/isabelle/Hoare.thy b/lib/isabelle/Hoare.thy
index afa953be..88807c7c 100644
--- a/lib/isabelle/Hoare.thy
+++ b/lib/isabelle/Hoare.thy
@@ -13,7 +13,7 @@ subsection \<open>Hoare triples\<close>
 
 type_synonym 'regs predS = "'regs sequential_state \<Rightarrow> bool"
 
-definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool"
+definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_\<rbrace>")
   where "PrePost P f Q \<equiv> (\<forall>s. P s \<longrightarrow> (\<forall>(r, s') \<in> f s. Q r s'))"
 
 lemma PrePostI:
@@ -211,7 +211,7 @@ there is an exception.
 [1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’,
 in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\<close>
 
-definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool"
+definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_ \<bar> _\<rbrace>")
   where "PrePostE P f Q E \<equiv> PrePost P f (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)"
 
 lemmas PrePost_defs = PrePost_def PrePostE_def
diff --git a/lib/isabelle/Sail2_state_monad_lemmas.thy b/lib/isabelle/Sail2_state_monad_lemmas.thy
index 91e4c17e..3a286c10 100644
--- a/lib/isabelle/Sail2_state_monad_lemmas.thy
+++ b/lib/isabelle/Sail2_state_monad_lemmas.thy
@@ -8,6 +8,9 @@ begin
   notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp]
 begin*)
 
+notation bindS (infixr "\<bind>\<^sub>S" 54)
+notation seqS (infixr "\<then>\<^sub>S" 54)
+
 lemma bindS_ext_cong[fundef_cong]:
   assumes m: "m1 s = m2 s"
     and f: "\<And>a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
diff --git a/src/state.ml b/src/state.ml
index e788ab6a..245d450c 100644
--- a/src/state.ml
+++ b/src/state.ml
@@ -367,15 +367,15 @@ let generate_isa_lemmas mwords (Defs defs : tannot defs) =
     let id' = remove_trailing_underscores id in
     separate_map hardline string [
       "lemma liftS_read_reg_" ^ id ^ "[liftState_simp]:";
-      "  \"liftS (read_reg " ^ id ^ "_ref) = readS (" ^ id' ^ " \\<circ> regstate)\"";
+      "  \"\\<lbrakk>read_reg " ^ id ^ "_ref\\<rbrakk>\\<^sub>S = readS (" ^ id' ^ " \\<circ> regstate)\"";
       "  by (auto simp: liftState_read_reg_readS register_defs)";
       "";
       "lemma liftS_write_reg_" ^ id ^ "[liftState_simp]:";
-      "  \"liftS (write_reg " ^ id ^ "_ref v) = updateS (regstate_update (" ^ id' ^ "_update (\\<lambda>_. v)))\"";
+      "  \"\\<lbrakk>write_reg " ^ id ^ "_ref v\\<rbrakk>\\<^sub>S = updateS (regstate_update (" ^ id' ^ "_update (\\<lambda>_. v)))\"";
       "  by (auto simp: liftState_write_reg_updateS register_defs)"
     ]
   in
-  string "abbreviation \"liftS \\<equiv> liftState (get_regval, set_regval)\"" ^^
+  string "abbreviation liftS (\"\\<lbrakk>_\\<rbrakk>\\<^sub>S\") where \"liftS \\<equiv> liftState (get_regval, set_regval)\"" ^^
   hardline ^^ hardline ^^
   register_defs ^^
   hardline ^^ hardline ^^
-- 
cgit v1.2.3


From 5d862dc23d4641a0e7d89cd747bc2ba4007ee8f5 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Sat, 7 Jul 2018 22:47:57 +0100
Subject: Update CHERI code generation from Isabelle

---
 test/isabelle/Cheri_code.thy | 2 +-
 test/isabelle/run_cheri.ml   | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/test/isabelle/Cheri_code.thy b/test/isabelle/Cheri_code.thy
index cfd01413..13884ad5 100644
--- a/test/isabelle/Cheri_code.thy
+++ b/test/isabelle/Cheri_code.thy
@@ -50,7 +50,7 @@ fun write_char_mem :: "int \<Rightarrow> char \<Rightarrow> (regstate, unit, exc
      bindS (write_mem_valS BC_bitU_list (bits_of_nat 8 (nat_of_char c))) (\<lambda>_.
      returnS ()))"
 
-definition "initial_state \<equiv> init_state initial_regstate (\<lambda>seed. (False, seed)) 0"
+definition "initial_state \<equiv> init_state initial_regstate"
 
 code_printing constant elf_entry \<rightharpoonup> (OCaml) "(Arith.Int'_of'_integer (Elf'_loader.elf'_entry _))"
 code_printing constant get_time_ns \<rightharpoonup> (OCaml) "(Arith.Int'_of'_integer (Big'_int.big'_int'_of'_int (Pervasives.int'_of'_float (1e9 *. Unix.gettimeofday _))))"
diff --git a/test/isabelle/run_cheri.ml b/test/isabelle/run_cheri.ml
index f51ef4dd..283e4283 100644
--- a/test/isabelle/run_cheri.ml
+++ b/test/isabelle/run_cheri.ml
@@ -63,8 +63,8 @@ let usage_msg = "Sail OCaml RTS options:"
 let () =
   Arg.parse options (fun s -> opt_file_arguments := !opt_file_arguments @ [s]) usage_msg
 
-let (>>) = State_monad.bindS
-let liftS = State_lifting.liftState (Cheri_types.get_regval, Cheri_types.set_regval)
+let (>>) = Sail2_state_monad.bindS
+let liftS = Sail2_state_lifting.liftState (Cheri_types.get_regval, Cheri_types.set_regval)
 
 let load_elf_segment seg =
   let open Elf_interpreted_segment in
@@ -78,7 +78,7 @@ let load_elf_segment seg =
   prerr_endline ("Segment base address: " ^ Big_int.string_of_big_int base);
   prerr_endline ("Segment physical address: " ^ Big_int.string_of_big_int paddr);
   print_segment seg;
-  State.iteriS writer (Byte_sequence.char_list_of_byte_sequence bs)
+  Sail2_state.iteriS writer (Byte_sequence.char_list_of_byte_sequence bs)
 
 let _ =
   Random.self_init ();
@@ -88,5 +88,5 @@ let _ =
   in
   (* State_monad.prerr_results *)
     (Cheri_code.initial_state |>
-    (State.iterS load_elf_segment elf_segments >> (fun _ ->
+    (Sail2_state.iterS load_elf_segment elf_segments >> (fun _ ->
     liftS (Cheri.main ()))));
-- 
cgit v1.2.3


From 946898cca35080989e88c14d7d6028d580ee6836 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Sat, 7 Jul 2018 22:48:39 +0100
Subject: Add explanatory comment to guard rewriting

---
 src/rewrites.ml | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/rewrites.ml b/src/rewrites.ml
index c2bf0835..67fb807e 100644
--- a/src/rewrites.ml
+++ b/src/rewrites.ml
@@ -1168,6 +1168,25 @@ let case_exp e t cs =
     (* let efr = union_effs (List.map effect_of_pexp ps) in *)
     fix_eff_exp (annot_exp (E_case (e,ps)) l env t)
 
+(* Rewrite guarded patterns into a combination of if-expressions and
+   unguarded pattern matches
+
+   Strategy:
+   - Split clauses into groups where the first pattern subsumes all the
+     following ones
+   - Translate the groups in reverse order, using the next group as a
+     fall-through target, if there is one
+   - Within a group,
+     - translate the sequence of clauses to an if-then-else cascade using the
+       guards as long as the patterns are equivalent modulo substitution, or
+     - recursively translate the remaining clauses to a pattern match if
+       there is a difference in the patterns.
+
+  TODO: Compare this more closely with the algorithm in the CPP'18 paper of
+  Spector-Zabusky et al, who seem to use the opposite grouping and merging
+  strategy to ours: group *mutually exclusive* clauses, and try to merge them
+  into a pattern match first instead of an if-then-else cascade.
+*)
 let rewrite_guarded_clauses l cs =
   let rec group fallthrough clauses =
     let add_clause (pat,cls,annot) c = (pat,cls @ [c],annot) in
-- 
cgit v1.2.3


From 4eab8dcb613e5eb07414930d715d8b9340fa99f9 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Sat, 7 Jul 2018 22:49:19 +0100
Subject: Tweak rewriting of literal patterns for Lem

---
 src/rewrites.ml | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/rewrites.ml b/src/rewrites.ml
index 67fb807e..481a1c25 100644
--- a/src/rewrites.ml
+++ b/src/rewrites.ml
@@ -3324,8 +3324,15 @@ let rewrite_defs_mapping_patterns =
   in
   pexp_rewriters rewrite_pexp
 
+let rewrite_lit_lem (L_aux (lit, _)) = match lit with
+  | L_num _ | L_string _ | L_hex _ | L_bin _ | L_real _ -> true
+  | _ -> false
+
+let rewrite_no_strings (L_aux (lit, _)) = match lit with
+  | L_string _ -> false
+  | _ -> true
 
-let rewrite_defs_pat_lits =
+let rewrite_defs_pat_lits rewrite_lit =
   let rewrite_pexp (Pat_aux (pexp_aux, annot) as pexp) =
     let guards = ref [] in
     let counter = ref 0 in
@@ -3333,7 +3340,7 @@ let rewrite_defs_pat_lits =
     let rewrite_pat = function
       (* HACK: ignore strings for now *)
       | P_lit (L_aux (L_string _, _)) as p_aux, p_annot -> P_aux (p_aux, p_annot)
-      | P_lit lit, p_annot ->
+      | P_lit lit, p_annot when rewrite_lit lit ->
          let env = env_of_annot p_annot in
          let typ = typ_of_annot p_annot in
          let id = mk_id ("p" ^ string_of_int !counter ^ "#") in
@@ -4004,7 +4011,7 @@ let rewrite_defs_lem = [
   ("remove_mapping_valspecs", remove_mapping_valspecs);
   ("pat_string_append", rewrite_defs_pat_string_append);
   ("mapping_builtins", rewrite_defs_mapping_patterns);
-  ("pat_lits", rewrite_defs_pat_lits);
+  ("pat_lits", rewrite_defs_pat_lits rewrite_lit_lem);
   ("vector_concat_assignments", rewrite_vector_concat_assignments);
   ("tuple_assignments", rewrite_tuple_assignments);
   ("simple_assignments", rewrite_simple_assignments);
@@ -4042,7 +4049,7 @@ let rewrite_defs_ocaml = [
   ("realise_mappings", rewrite_defs_realise_mappings);
   ("pat_string_append", rewrite_defs_pat_string_append);
   ("mapping_builtins", rewrite_defs_mapping_patterns);
-  ("pat_lits", rewrite_defs_pat_lits);
+  ("pat_lits", rewrite_defs_pat_lits rewrite_no_strings);
   ("vector_concat_assignments", rewrite_vector_concat_assignments);
   ("tuple_assignments", rewrite_tuple_assignments);
   ("simple_assignments", rewrite_simple_assignments);
@@ -4064,7 +4071,7 @@ let rewrite_defs_c = [
   ("realise_mappings", rewrite_defs_realise_mappings);
   ("pat_string_append", rewrite_defs_pat_string_append);
   ("mapping_builtins", rewrite_defs_mapping_patterns);
-  ("pat_lits", rewrite_defs_pat_lits);
+  ("pat_lits", rewrite_defs_pat_lits rewrite_no_strings);
   ("vector_concat_assignments", rewrite_vector_concat_assignments);
   ("tuple_assignments", rewrite_tuple_assignments);
   ("simple_assignments", rewrite_simple_assignments);
-- 
cgit v1.2.3


From 3334e0f9de700ed918e5f8c461f8cf08d23e7fd3 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Sat, 7 Jul 2018 22:49:42 +0100
Subject: Fix bug in rewriting of try-catch-blocks with variable updates

---
 src/rewrites.ml | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/rewrites.ml b/src/rewrites.ml
index 481a1c25..fad1f4d2 100644
--- a/src/rewrites.ml
+++ b/src/rewrites.ml
@@ -3539,11 +3539,12 @@ let rec rewrite_var_updates ((E_aux (expaux,((l,_) as annot))) as exp) =
          let eff = union_eff_exps [c;e1;e2] in
          let v = E_aux (E_if (c,e1,e2), (gen_loc el, Some (env, typ, eff))) in
          Added_vars (v, tuple_pat (if overwrite then varpats else pat :: varpats))
-    | E_case (e1,ps) ->
-       (* after rewrite_defs_letbind_effects e1 needs no rewriting *)
+    | E_case (e1,ps) | E_try (e1, ps) ->
+       let is_case = match expaux with E_case _ -> true | _ -> false in
        let vars, varpats =
-         ps
-         |> List.map (fun (Pat_aux ((Pat_exp (_,e)|Pat_when (_,_,e)),_)) -> e)
+         (* for E_case, e1 needs no rewriting after rewrite_defs_letbind_effects *)
+         ((if is_case then [] else [e1]) @
+         List.map (fun (Pat_aux ((Pat_exp (_,e)|Pat_when (_,_,e)),_)) -> e) ps)
          |> List.map find_updated_vars
          |> List.fold_left IdSet.union IdSet.empty
          |> IdSet.inter used_vars
@@ -3554,8 +3555,10 @@ let rec rewrite_var_updates ((E_aux (expaux,((l,_) as annot))) as exp) =
              Pat_aux (Pat_exp (p,rewrite_var_updates e),a)
            | Pat_aux (Pat_when (p,g,e),a) ->
              Pat_aux (Pat_when (p,g,rewrite_var_updates e),a)) ps in
-         Same_vars (E_aux (E_case (e1,ps),annot))
+         let expaux = if is_case then E_case (e1, ps) else E_try (e1, ps) in
+         Same_vars (E_aux (expaux, annot))
        else
+         let e1 = if is_case then e1 else rewrite_var_updates (add_vars overwrite e1 vars) in
          let rewrite_pexp (Pat_aux (pexp, (l, _))) = match pexp with
            | Pat_exp (pat, exp) ->
              let exp = rewrite_var_updates (add_vars overwrite exp vars) in
@@ -3564,10 +3567,12 @@ let rec rewrite_var_updates ((E_aux (expaux,((l,_) as annot))) as exp) =
            | Pat_when _ ->
              raise (Reporting_basic.err_unreachable l
                "Guarded patterns should have been rewritten already") in
+         let ps = List.map rewrite_pexp ps in
+         let expaux = if is_case then E_case (e1, ps) else E_try (e1, ps) in
          let typ = match ps with
            | Pat_aux ((Pat_exp (_,first)|Pat_when (_,_,first)),_) :: _ -> typ_of first
            | _ -> unit_typ in
-         let v = fix_eff_exp (annot_exp (E_case (e1, List.map rewrite_pexp ps)) pl env typ) in
+         let v = fix_eff_exp (annot_exp expaux pl env typ) in
          Added_vars (v, tuple_pat (if overwrite then varpats else pat :: varpats))
     | E_assign (lexp,vexp) ->
        let mk_id_pat id = match Env.lookup_id id env with
-- 
cgit v1.2.3


From d829021b5f64d3c6b4ad39c69a5f36475d8e7071 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Mon, 9 Jul 2018 13:53:19 +0100
Subject: Update gitignore

---
 lib/isabelle/.gitignore | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/lib/isabelle/.gitignore b/lib/isabelle/.gitignore
index 0d595f3c..ed83cdc1 100644
--- a/lib/isabelle/.gitignore
+++ b/lib/isabelle/.gitignore
@@ -1,13 +1,13 @@
-PromptAuxiliary.thy
-Prompt_monadAuxiliary.thy
-Prompt_monad.thy
-Prompt.thy
-Sail_instr_kinds.thy
-Sail_operators_bitlists.thy
-Sail_operators_mwords.thy
-Sail_operators.thy
-Sail_valuesAuxiliary.thy
-Sail_values.thy
-StateAuxiliary.thy
-State_monad.thy
-State.thy
+Sail2_promptAuxiliary.thy
+Sail2_prompt_monadAuxiliary.thy
+Sail2_prompt_monad.thy
+Sail2_prompt.thy
+Sail2_instr_kinds.thy
+Sail2_operators_bitlists.thy
+Sail2_operators_mwords.thy
+Sail2_operators.thy
+Sail2_valuesAuxiliary.thy
+Sail2_values.thy
+Sail2_stateAuxiliary.thy
+Sail2_state_monad.thy
+Sail2_state.thy
-- 
cgit v1.2.3


From 8139ae498b4809833394b3e0548757426ff912cc Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Mon, 9 Jul 2018 14:50:16 +0100
Subject: Support building an anonymised version of manual. Fix sail example in
 manual. Remove incomplete types chapter from manual per AA's recommendation.

---
 Makefile                            | 11 +++++++++++
 doc/Makefile                        | 10 +++++++---
 doc/examples/my_replicate_bits.sail |  4 ++++
 doc/introduction.tex                |  6 +++---
 doc/manual.tex                      |  9 ++++++++-
 5 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index bfbf6bef..9a6dd42a 100644
--- a/Makefile
+++ b/Makefile
@@ -53,6 +53,17 @@ apply_header:
 	headache -c etc/headache_config -h LICENCE `ls src/lem_interp/*.lem`
 	$(MAKE) -C arm apply_header
 
+anon_dist:
+	$(MAKE) clean
+	headache -c etc/headache_config -h etc/anon_header `ls mips/*.sail`
+	headache -c etc/headache_config -h etc/anon_header `ls cheri/*.sail`
+	headache -c etc/headache_config -h etc/anon_header `ls src/Makefile*`
+	headache -c etc/headache_config -h etc/anon_header `ls src/*.ml*`
+	headache -c etc/headache_config -h etc/anon_header `ls src/lem_interp/*.ml`
+	headache -c etc/headache_config -h etc/anon_header `ls src/lem_interp/*.lem`
+	headache -c etc/headache_config -h etc/anon_header `ls arm/*.sail`
+	tar cvzf sail.tar.gz .
+
 clean:
 	for subdir in src arm ; do\
 	  $(MAKE) -C "$$subdir" clean;\
diff --git a/doc/Makefile b/doc/Makefile
index b5a74dd6..ae542571 100644
--- a/doc/Makefile
+++ b/doc/Makefile
@@ -65,11 +65,15 @@ code_myreplicatebits.tex: examples/my_replicate_bits.sail
 grammar.tex: ../language/sail.ott
 	ott -pp_grammar -tex_wrap false -tex_suppress_category I -tex_suppress_category D -tex_suppress_ntr terminals -tex_suppress_ntr formula -tex_suppress_ntr judgement -tex_suppress_ntr user_syntax -tex_suppress_ntr dec_comm -sort false -generate_aux_rules false  -picky_multiple_parses true -i ../language/sail.ott -o grammar.tex
 
+LATEXARG=manual.tex
 manual.pdf: grammar.tex introduction.tex usage.tex types.tex code_riscv.tex riscv.tex manual.tex manual.bib tutorial.tex code_myreplicatebits.tex
-	pdflatex manual.tex
+	pdflatex ${LATEXARG}
 	bibtex manual
-	pdflatex manual.tex
-	pdflatex manual.tex
+	pdflatex ${LATEXARG}
+	pdflatex ${LATEXARG}
+
+anon_man: LATEXARG='\def\ANON{}\input{manual.tex}'
+anon_man: manual.pdf
 
 clean:
 	-rm manual.pdf
diff --git a/doc/examples/my_replicate_bits.sail b/doc/examples/my_replicate_bits.sail
index c9972cd6..8c3c9458 100644
--- a/doc/examples/my_replicate_bits.sail
+++ b/doc/examples/my_replicate_bits.sail
@@ -17,10 +17,14 @@ val operator >> = {
 
 val "or_vec" : forall 'n. (bits('n), bits('n)) -> bits('n)
 
+val zero_extend = "zero_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m)
+
 overload operator | = {or_vec}
 
 val my_replicate_bits : forall 'n 'm, 'm >= 1 & 'n >= 1. (int('n), bits('m)) -> bits('n * 'm)
 
+val zeros = "zeros" : forall 'n. atom('n) -> bits('n)
+
 function my_replicate_bits(n, xs) = {
   ys = zeros(n * length(xs));
   foreach (i from 1 to n) {
diff --git a/doc/introduction.tex b/doc/introduction.tex
index 5969f34f..9e268de5 100644
--- a/doc/introduction.tex
+++ b/doc/introduction.tex
@@ -114,12 +114,12 @@ except vector, float, and load-multiple instructions, without
 exceptions; for ARMv8 this is for the A64 fragment.
 
 The ARMv8 (hand) model is hand-written based on the ARMv8-A
-specification document~\cite{armarmv8,FGP16}, principally by Flur.
+specification document~\cite{armarmv8,FGP16}, principally by \anonymise{Flur}.
 
 The Power model is based on an automatic extraction of pseudocode and
 decoding data from an XML export of the Framemaker document source of
 the IBM Power manual~\cite{Power2.06,micro2015}, with manual patching
-as necessary, principally by Kerneis and Gray.
+as necessary, principally by \anonymise{Kerneis and Gray}.
 
 The ARMv8 (ASL) model is based on an automatic translation of ARM's
 machine-readable public v8.3 ASL specification\footnote{ARM v8-A
@@ -135,7 +135,7 @@ which in turn drew on MIPS4000 and MIPS32~\cite{MIPS4000,MIPS32-I}.
 %
 The CHERI model is based on that and the CHERI ISA reference manual
 version~5~\cite{UCAM-CL-TR-891}. These two are both principally by
-Norton-Wright; they cover all basic user and kernel mode MIPS features
+\anonymise{Norton-Wright}; they cover all basic user and kernel mode MIPS features
 sufficient to boot FreeBSD, including a TLB, exceptions and a basic
 UART for console interaction. ISA extensions such as floating point
 are not covered. The CHERI model supports either 256-bit capabilities
diff --git a/doc/manual.tex b/doc/manual.tex
index 3b75b26a..d28719a4 100644
--- a/doc/manual.tex
+++ b/doc/manual.tex
@@ -64,9 +64,15 @@
 
 \title{The Sail instruction-set semantics specification language}
 
+\ifdefined\ANON
+\author{Anonymous}
+\newcommand\anonymise[1]{\emph{redacted}}
+\else
 \author{Alasdair Armstrong \and Thomas Bauereiss \and Brian Campbell \and
   Shaked Flur \and Kathryn E. Gray \and Robert Norton-Wright \and Christopher Pulte \and
   Peter Sewell}
+\newcommand\anonymise[1]{#1}
+\fi
 
 \maketitle
 
@@ -80,7 +86,8 @@
 
 \include{tutorial}
 
-\include{types}
+% Remove for now since incomplete
+%\include{types}
 
 \bibliographystyle{unsrt}
 \bibliography{manual}
-- 
cgit v1.2.3


From 0bb45311868aff5ce34d29ec4b0a410bc1e319dd Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 9 Jul 2018 15:35:25 +0100
Subject: Coq: remove some unnecessary casts

---
 src/pretty_print_coq.ml | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index e68a6dd9..efcf3851 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -688,6 +688,27 @@ let typ_id_of (Typ_aux (typ, l)) = match typ with
   | Typ_app (id, _) -> id
   | _ -> raise (Reporting_basic.err_unreachable l "failed to get type id")
 
+(* TODO: maybe Nexp_exp, division? *)
+(* Evaluation of constant nexp subexpressions, because Coq will be able to do those itself *)
+let rec nexp_const_eval (Nexp_aux (n,l) as nexp) =
+  let binop f re l n1 n2 =
+  match nexp_const_eval n1, nexp_const_eval n2 with
+  | Nexp_aux (Nexp_constant c1,_), Nexp_aux (Nexp_constant c2,_) ->
+     Nexp_aux (Nexp_constant (f c1 c2),l)
+  | n1', n2' -> Nexp_aux (re n1' n2',l)
+  in
+  let unop f re l n1 =
+  match nexp_const_eval n1 with
+  | Nexp_aux (Nexp_constant c1,_) -> Nexp_aux (Nexp_constant (f c1),l)
+  | n1' -> Nexp_aux (re n1',l)
+  in
+  match n with
+  | Nexp_times (n1,n2) -> binop Big_int.mul (fun n1 n2 -> Nexp_times (n1,n2)) l n1 n2
+  | Nexp_sum (n1,n2) -> binop Big_int.add (fun n1 n2 -> Nexp_sum (n1,n2)) l n1 n2
+  | Nexp_minus (n1,n2) -> binop Big_int.sub (fun n1 n2 -> Nexp_minus (n1,n2)) l n1 n2
+  | Nexp_neg n1 -> unop Big_int.negate (fun n -> Nexp_neg n) l n1
+  | _ -> nexp
+
 (* Decide whether two nexps used in a vector size are similar; if not
    a cast will be inserted *)
 let similar_nexps n1 n2 =
@@ -707,7 +728,7 @@ let similar_nexps n1 n2 =
     | Nexp_neg n1, Nexp_neg n2
       -> same_nexp_shape n1 n2
     | _ -> false
-  in if same_nexp_shape n1 n2 then true else false
+  in if same_nexp_shape (nexp_const_eval n1) (nexp_const_eval n2) then true else false
 
 let constraint_fns = ["Z.leb"; "Z.geb"; "Z.ltb"; "Z.gtb"; "Z.eqb"]
 
-- 
cgit v1.2.3


From 6c04e4bf31b7632283c69a30c30f3869e9146874 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 9 Jul 2018 16:24:05 +0100
Subject: Tweak bit casting definitions in MIPS to avoid non-exhaustive
 patterns Recent change made them proper matches rather than conditionals, and
 Coq rejects incomplete matches. (Will need a proper solution later...)

---
 mips/prelude.sail | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mips/prelude.sail b/mips/prelude.sail
index 697ef74a..037819bc 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -44,7 +44,7 @@ val cast cast_unit_vec : bit -> bits(1)
 
 function cast_unit_vec b = match b {
   bitzero => 0b0,
-  bitone => 0b1
+  _ => 0b1
 }
 
 val print = "print_endline" : string -> unit
@@ -186,7 +186,7 @@ function bool_to_bits x = if x then 0b1 else 0b0
 val cast bit_to_bool : bit -> bool
 function bit_to_bool b = match b {
   bitone => true,
-  bitzero => false
+  _ => false
 }
 
 val cast bits_to_bool : bits(1) -> bool
-- 
cgit v1.2.3


From 936f1beb2bbc9db6182ba8b706668e146c3657d9 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Mon, 9 Jul 2018 16:30:06 +0100
Subject: Changes for anonymisation. Ensure headers are in correct format.
 Remove some redundant files.

---
 Makefile                        |  8 +++++--
 etc/anon_header                 |  2 ++
 etc/headache_config             |  4 +++-
 lib/main.ml                     |  1 -
 src/test/lib/run_test_interp.ml | 51 -----------------------------------------
 src/value2.lem                  |  4 ++--
 6 files changed, 13 insertions(+), 57 deletions(-)
 create mode 100644 etc/anon_header
 delete mode 100644 src/test/lib/run_test_interp.ml

diff --git a/Makefile b/Makefile
index 9a6dd42a..c7fbd951 100644
--- a/Makefile
+++ b/Makefile
@@ -54,15 +54,19 @@ apply_header:
 	$(MAKE) -C arm apply_header
 
 anon_dist:
-	$(MAKE) clean
 	headache -c etc/headache_config -h etc/anon_header `ls mips/*.sail`
 	headache -c etc/headache_config -h etc/anon_header `ls cheri/*.sail`
+	headache -c etc/headache_config -h etc/anon_header `ls riscv/*.sail`
+	headache -c etc/headache_config -h etc/anon_header `ls riscv/*.ml`
+	headache -c etc/headache_config -h etc/anon_header `ls lib/*.ml`
+	headache -c etc/headache_config -h etc/anon_header `ls lib/coq/*.v`
 	headache -c etc/headache_config -h etc/anon_header `ls src/Makefile*`
 	headache -c etc/headache_config -h etc/anon_header `ls src/*.ml*`
+	headache -c etc/headache_config -h etc/anon_header `ls src/*.lem`
 	headache -c etc/headache_config -h etc/anon_header `ls src/lem_interp/*.ml`
 	headache -c etc/headache_config -h etc/anon_header `ls src/lem_interp/*.lem`
 	headache -c etc/headache_config -h etc/anon_header `ls arm/*.sail`
-	tar cvzf sail.tar.gz .
+	tar czf sail.tar.gz aarch64 cheri mips riscv language lib src snapshots
 
 clean:
 	for subdir in src arm ; do\
diff --git a/etc/anon_header b/etc/anon_header
new file mode 100644
index 00000000..c3173e6a
--- /dev/null
+++ b/etc/anon_header
@@ -0,0 +1,2 @@
+Copyright (2018) Sail contributors.
+This material is provided for anonymous review purposes only.
\ No newline at end of file
diff --git a/etc/headache_config b/etc/headache_config
index e8745fee..4a68f1ef 100644
--- a/etc/headache_config
+++ b/etc/headache_config
@@ -1,3 +1,5 @@
   ".*\\.mllib"  -> frame open:"(*" line:"=" close:"*)"
 |  ".*\\.lem"    -> frame open:"(*" line:"=" close:"*)"
-|  ".*\\.sail"   -> frame open:"(*" line:"=" close:"*)"
+|  ".*\\.v"      -> frame open:"(*" line:"=" close:"*)"
+|  ".*\\.sail"   -> frame open:"/*" line:"=" close:"*/"
+
diff --git a/lib/main.ml b/lib/main.ml
index e9dcb4e0..c1b6fcae 100644
--- a/lib/main.ml
+++ b/lib/main.ml
@@ -1,4 +1,3 @@
-
 (**************************************************************************)
 (*     Sail                                                               *)
 (*                                                                        *)
diff --git a/src/test/lib/run_test_interp.ml b/src/test/lib/run_test_interp.ml
deleted file mode 100644
index 5f2ace1b..00000000
--- a/src/test/lib/run_test_interp.ml
+++ /dev/null
@@ -1,51 +0,0 @@
-(**************************************************************************)
-(*     Sail                                                               *)
-(*                                                                        *)
-(*  Copyright (c) 2013-2017                                               *)
-(*    Kathyrn Gray                                                        *)
-(*    Shaked Flur                                                         *)
-(*    Stephen Kell                                                        *)
-(*    Gabriel Kerneis                                                     *)
-(*    Robert Norton-Wright                                                *)
-(*    Christopher Pulte                                                   *)
-(*    Peter Sewell                                                        *)
-(*                                                                        *)
-(*  All rights reserved.                                                  *)
-(*                                                                        *)
-(*  This software was developed by the University of Cambridge Computer   *)
-(*  Laboratory as part of the Rigorous Engineering of Mainstream Systems  *)
-(*  (REMS) project, funded by EPSRC grant EP/K008528/1.                   *)
-(*                                                                        *)
-(*  Redistribution and use in source and binary forms, with or without    *)
-(*  modification, are permitted provided that the following conditions    *)
-(*  are met:                                                              *)
-(*  1. Redistributions of source code must retain the above copyright     *)
-(*     notice, this list of conditions and the following disclaimer.      *)
-(*  2. Redistributions in binary form must reproduce the above copyright  *)
-(*     notice, this list of conditions and the following disclaimer in    *)
-(*     the documentation and/or other materials provided with the         *)
-(*     distribution.                                                      *)
-(*                                                                        *)
-(*  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''    *)
-(*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     *)
-(*  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A       *)
-(*  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR   *)
-(*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,          *)
-(*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      *)
-(*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF      *)
-(*  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   *)
-(*  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,    *)
-(*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    *)
-(*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    *)
-(*  SUCH DAMAGE.                                                          *)
-(**************************************************************************)
-
-open Interp_interface ;;
-open Interp_inter_imp ;;
-open Sail_impl_base ;;
-
-let doit () =
-  let context = build_context false Test_lem_ast.defs [] [] [] [] [] [] [] None [] in
-  translate_address context E_little_endian "run" None (address_of_integer (Nat_big_num.of_int 0));;
-
-doit () ;;
diff --git a/src/value2.lem b/src/value2.lem
index d9fd1263..e8a8262a 100644
--- a/src/value2.lem
+++ b/src/value2.lem
@@ -1,4 +1,4 @@
-(**************************************************************************)
+(*========================================================================*)
 (*     Sail                                                               *)
 (*                                                                        *)
 (*  Copyright (c) 2013-2017                                               *)
@@ -46,7 +46,7 @@
 (*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    *)
 (*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    *)
 (*  SUCH DAMAGE.                                                          *)
-(**************************************************************************)
+(*========================================================================*)
 
 open import Pervasives
 open import Assert_extra
-- 
cgit v1.2.3


From c0cace93c93260a5ba2ff8e4df962797247d5a60 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 9 Jul 2018 17:15:56 +0100
Subject: Remove awkward constraints on GetSlice_int for now

---
 aarch64/prelude.sail | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail
index 6837c366..65109485 100755
--- a/aarch64/prelude.sail
+++ b/aarch64/prelude.sail
@@ -151,9 +151,9 @@ val __SetSlice_int = "set_slice_int" : forall 'w. (atom('w), int, int, bits('w))
 
 val __raw_SetSlice_int : forall 'w. (atom('w), int, int, bits('w)) -> int
 
-val __raw_GetSlice_int = "get_slice_int" : forall 'w, 'w >= 0. (atom('w), int, int) -> bits('w)
+val __raw_GetSlice_int = "get_slice_int" : forall 'w /*, 'w >= 0*/. (atom('w), int, int) -> bits('w)
 
-val __GetSlice_int : forall 'n, 'n >= 0. (atom('n), int, int) -> bits('n)
+val __GetSlice_int : forall 'n /*, 'n >= 0*/. (atom('n), int, int) -> bits('n)
 
 function __GetSlice_int (n, m, o) = __raw_GetSlice_int(n, m, o)
 
-- 
cgit v1.2.3


From 4116dd12aaed92365043bb7b1d6b537c9e161eec Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Mon, 9 Jul 2018 17:34:01 +0100
Subject: anonymise github link in sail manual.

---
 doc/riscv.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/riscv.tex b/doc/riscv.tex
index 2ecc69df..299a7bdd 100644
--- a/doc/riscv.tex
+++ b/doc/riscv.tex
@@ -137,4 +137,4 @@ end execute
 
 The actual code for this example, as well as our more complete
 \riscv\ specification can be found on our github at
-\url{https://github.com/rems-project/sail/blob/sail2/riscv/riscv_duopod.sail}.
+\anonymise{\url{https://github.com/rems-project/sail/blob/sail2/riscv/riscv_duopod.sail}}.
-- 
cgit v1.2.3


From c2b19f7a89df122daf56b22fa25a53202eddaab0 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Mon, 9 Jul 2018 17:37:42 +0100
Subject: anonymise another github link.

---
 doc/usage.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/usage.tex b/doc/usage.tex
index b7a47934..09d4b903 100644
--- a/doc/usage.tex
+++ b/doc/usage.tex
@@ -91,7 +91,7 @@ We have a separate document detailing how to generate Isabelle
 theories from Sail models, and how to work with those models in
 Isabelle, see:
 \begin{center}
-\url{https://github.com/rems-project/sail/raw/sail2/snapshots/isabelle/Manual.pdf}
+\anonymise{\url{https://github.com/rems-project/sail/raw/sail2/snapshots/isabelle/Manual.pdf}}
 \end{center}
 Currently there are generated Isabelle snapshots for some of our
 models in \verb+snapshots/isabelle+ in the Sail repository. These
-- 
cgit v1.2.3


From b71a0574ee9b9ae1d80e91a13915b16fbdf0f405 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Mon, 9 Jul 2018 17:44:07 +0100
Subject: Add no_devices.sail to be compatible with latest AArch64 prelude and
 update aarch64 model

---
 aarch64/full.sail       |  1 +
 aarch64/no_devices.sail | 35 +++++++++++++++++++++++++++++++++++
 aarch64/no_vector.sail  |  1 +
 3 files changed, 37 insertions(+)
 create mode 100644 aarch64/no_devices.sail

diff --git a/aarch64/full.sail b/aarch64/full.sail
index b05b1829..b02b8333 100644
--- a/aarch64/full.sail
+++ b/aarch64/full.sail
@@ -1,6 +1,7 @@
 
 // Prelude
 $include "prelude.sail"
+$include "no_devices.sail"
 
 // Specification
 $include "full/spec.sail"
diff --git a/aarch64/no_devices.sail b/aarch64/no_devices.sail
new file mode 100644
index 00000000..882aa6b3
--- /dev/null
+++ b/aarch64/no_devices.sail
@@ -0,0 +1,35 @@
+
+val ___WriteRAM = "write_ram" : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+
+val __InitRAM : forall 'm. (atom('m), int, bits('m), bits(8)) -> unit
+
+function __InitRAM (_, _, _, _) = ()
+
+val ___ReadRAM = "read_ram" : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __ReadRAM : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+function __ReadRAM(addr_length, bytes, hex_ram, addr) =
+{
+  ___ReadRAM(addr_length, bytes, hex_ram, addr)
+}
+
+val __TraceMemoryWrite : forall 'n 'm.
+  (atom('n), bits('m), bits(8 * 'n)) -> unit
+
+val __WriteRAM : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+
+function __WriteRAM(addr_length, bytes, hex_ram, addr, data) =
+{
+  ___WriteRAM(addr_length, bytes, hex_ram, addr, data)
+}
+
+function __TraceMemoryWrite(bytes, addr, data) = ()
+
+val __TraceMemoryRead : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit
+
+function __TraceMemoryRead(bytes, addr, data) = ()
\ No newline at end of file
diff --git a/aarch64/no_vector.sail b/aarch64/no_vector.sail
index 61fc7b4f..6c96d070 100644
--- a/aarch64/no_vector.sail
+++ b/aarch64/no_vector.sail
@@ -1,6 +1,7 @@
 
 // Prelude
 $include "prelude.sail"
+$include "no_devices.sail"
 
 // Specification
 $include "no_vector/spec.sail"
-- 
cgit v1.2.3


From 53ce89769a10be9a47af72b5fb440afa74bb4d02 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 9 Jul 2018 18:48:17 +0100
Subject: Lem: prefer type variables to constants when looking for equivalent
 nexps If we have an nexp that we can't print, look for an equivalent type
 variable before looking for a constant - the constant may only be valid
 locally (e.g., under an if) while the type variable will be valid throughout
 the function. Fixes a problem with aget_Mem on aarch64.

---
 src/pretty_print_lem.ml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/pretty_print_lem.ml b/src/pretty_print_lem.ml
index c872d420..9897bb7c 100644
--- a/src/pretty_print_lem.ml
+++ b/src/pretty_print_lem.ml
@@ -334,14 +334,14 @@ let replace_typ_size ctxt env (Typ_aux (t,a)) =
        let mk_typ nexp = 
          Some (Typ_aux (Typ_app (id, [Typ_arg_aux (Typ_arg_nexp nexp,Parse_ast.Unknown);ord;typ']),a))
        in
-       match Type_check.solve env size with
-       | Some n -> mk_typ (nconstant n)
-       | None ->
-          let is_equal nexp =
-            prove env (NC_aux (NC_equal (size,nexp),Parse_ast.Unknown))
-          in match List.find is_equal (NexpSet.elements ctxt.bound_nexps) with
-          | nexp -> mk_typ nexp
-          | exception Not_found -> None
+       let is_equal nexp =
+         prove env (NC_aux (NC_equal (size,nexp),Parse_ast.Unknown))
+       in match List.find is_equal (NexpSet.elements ctxt.bound_nexps) with
+       | nexp -> mk_typ nexp
+       | exception Not_found ->
+          match Type_check.solve env size with
+          | Some n -> mk_typ (nconstant n)
+          | None -> None
      end
   | _ -> None
 
-- 
cgit v1.2.3


From 1f950bdf4f6f80b472ec06eb07a3144666840126 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Mon, 9 Jul 2018 15:20:36 -0700
Subject: Log some timing info at the end of riscv execution.

---
 riscv/platform_main.ml | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/riscv/platform_main.ml b/riscv/platform_main.ml
index 8dd47547..4c33e24d 100644
--- a/riscv/platform_main.ml
+++ b/riscv/platform_main.ml
@@ -87,11 +87,7 @@ let elf_arg =
       | _ -> (prerr_endline "Please provide an ELF file."; exit 0)
   )
 
-let () =
-  Random.self_init ();
-
-  let pc = Platform.init elf_arg in
-
+let run pc =
   sail_call
     (fun r ->
       try ( zinit_platform (); (* devices *)
@@ -105,3 +101,22 @@ let () =
         | ZError_internal_error (_) ->
               prerr_endline "Error: internal error"
     )
+
+let show_times init_s init_e run_e insts =
+  let init_time = init_e.Unix.tms_utime -. init_s.Unix.tms_utime in
+  let exec_time = run_e.Unix.tms_utime -. init_e.Unix.tms_utime in
+  Printf.eprintf "\nInitialization: %g secs\n" init_time;
+  Printf.eprintf "Execution: %g secs\n" exec_time;
+  Printf.eprintf "Instructions retired: %Ld\n" insts;
+  Printf.eprintf "Perf: %g ips\n" ((Int64.to_float insts) /. exec_time)
+
+let () =
+  Random.self_init ();
+
+  let init_start = Unix.times () in
+  let pc = Platform.init elf_arg in
+  let init_end = Unix.times () in
+  let _ = run pc in
+  let run_end = Unix.times () in
+  let insts = Big_int.to_int64 (uint (!Riscv.zminstret)) in
+  show_times init_start init_end run_end insts
-- 
cgit v1.2.3


From 85def9a2d488cc2d74394663f9f6323258e5fa59 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Mon, 9 Jul 2018 16:49:31 -0700
Subject: Initialize fresh memory to 0 in the OCaml backend. This makes it
 consistent with the C backend, and also makes it easier to compare traces
 across execution re-runs.

---
 src/sail_lib.ml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/sail_lib.ml b/src/sail_lib.ml
index ab621342..63260c17 100644
--- a/src/sail_lib.ml
+++ b/src/sail_lib.ml
@@ -419,7 +419,7 @@ let get_mem_page p =
   try
     Mem.find p !mem_pages
   with Not_found -> 
-    let new_page = Bytes.create page_size_bytes in
+    let new_page = Bytes.make page_size_bytes '\000' in
     mem_pages := Mem.add p new_page !mem_pages;
     new_page
 
-- 
cgit v1.2.3


From 58836205da846571afdb7994a9d5915f6fbae09f Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 10 Jul 2018 11:40:28 +0100
Subject: Aarch64 mono script update

---
 aarch64/mono/demo/mk         | 2 +-
 aarch64/mono/demo/mk.hol     | 2 +-
 src/gen_lib/sail2_values.lem | 2 ++
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/aarch64/mono/demo/mk b/aarch64/mono/demo/mk
index 64abea6f..b7513edd 100755
--- a/aarch64/mono/demo/mk
+++ b/aarch64/mono/demo/mk
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -ex
-../../../sail ../../prelude.sail ../mono_rewrites.sail \
+../../../sail ../../prelude.sail ../../no_devices.sail ../mono_rewrites.sail \
      aarch64_no_vector/spec.sail aarch64_no_vector/decode_start.sail aarch64_no_vector/decode.sail aarch64_no_vector/decode_end.sail \
      -no_lexp_bounds_check -memo_z3 -undefined_gen \
      -auto_mono -mono_rewrites -dall_split_errors -dmono_continue \
diff --git a/aarch64/mono/demo/mk.hol b/aarch64/mono/demo/mk.hol
index ac20717f..cd9f84fc 100755
--- a/aarch64/mono/demo/mk.hol
+++ b/aarch64/mono/demo/mk.hol
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -ex
-../../../sail ../../prelude.sail ../mono_rewrites.sail \
+../../../sail ../../prelude.sail ../../no_devices.sail ../mono_rewrites.sail \
      aarch64_no_vector/spec.sail aarch64_no_vector/decode_start.sail aarch64_no_vector/decode.sail aarch64_no_vector/decode_end.sail \
      -no_lexp_bounds_check -memo_z3 -undefined_gen \
      -auto_mono -mono_rewrites -dall_split_errors -dmono_continue \
diff --git a/src/gen_lib/sail2_values.lem b/src/gen_lib/sail2_values.lem
index 0f384cab..003eedc7 100644
--- a/src/gen_lib/sail2_values.lem
+++ b/src/gen_lib/sail2_values.lem
@@ -53,6 +53,8 @@ val prerr_endline : string -> unit
 let prerr_endline _ = ()
 declare ocaml target_rep function prerr_endline = `prerr_endline`
 
+let prerr x = prerr_endline x
+
 val print_int : string -> integer -> unit
 let print_int msg i = print_endline (msg ^ (stringFromInteger i))
 
-- 
cgit v1.2.3


From ca40c5ae8f89aa3268bdc69125107c62c9240a4c Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 10 Jul 2018 12:20:01 +0100
Subject: further anonymisation work.

---
 Makefile            | 4 +++-
 etc/headache_config | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index c7fbd951..a22e19df 100644
--- a/Makefile
+++ b/Makefile
@@ -66,7 +66,9 @@ anon_dist:
 	headache -c etc/headache_config -h etc/anon_header `ls src/lem_interp/*.ml`
 	headache -c etc/headache_config -h etc/anon_header `ls src/lem_interp/*.lem`
 	headache -c etc/headache_config -h etc/anon_header `ls arm/*.sail`
-	tar czf sail.tar.gz aarch64 cheri mips riscv language lib src snapshots
+	headache -c etc/headache_config -h etc/anon_header `ls snapshots/isabelle/lib/sail/*.thy`
+	headache -c etc/headache_config -h etc/anon_header `ls snapshots/isabelle/lib/lem/*.thy`
+	headache -c etc/headache_config -h etc/anon_header `ls snapshots/hol4/lem/hol-lib/*.sml`
 
 clean:
 	for subdir in src arm ; do\
diff --git a/etc/headache_config b/etc/headache_config
index 4a68f1ef..23bed5ea 100644
--- a/etc/headache_config
+++ b/etc/headache_config
@@ -1,5 +1,7 @@
   ".*\\.mllib"  -> frame open:"(*" line:"=" close:"*)"
 |  ".*\\.lem"    -> frame open:"(*" line:"=" close:"*)"
 |  ".*\\.v"      -> frame open:"(*" line:"=" close:"*)"
+|  ".*\\.thy"      -> frame open:"(*" line:"=" close:"*)"
+|  ".*\\.sml"      -> frame open:"(*" line:"=" close:"*)"
 |  ".*\\.sail"   -> frame open:"/*" line:"=" close:"*/"
 
-- 
cgit v1.2.3


From 6d159446ce0cddae7184cb64d58657557c1d7b25 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 10 Jul 2018 12:35:26 +0100
Subject: Tweak to anonymous copyright header.

---
 etc/anon_header | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/etc/anon_header b/etc/anon_header
index c3173e6a..5db38447 100644
--- a/etc/anon_header
+++ b/etc/anon_header
@@ -1,2 +1,2 @@
-Copyright (2018) Sail contributors.
+Copyright (c) 2018 Sail contributors.
 This material is provided for anonymous review purposes only.
\ No newline at end of file
-- 
cgit v1.2.3


From 0fe23222243bcadf6393d899e235ac35aaf57d63 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Tue, 10 Jul 2018 13:56:08 +0100
Subject: Add more Isabelle lemmas to library

---
 lib/isabelle/Hoare.thy                         | 131 +++++++++++++++++++++++
 lib/isabelle/Sail2_operators_mwords_lemmas.thy |  57 ++++++++++
 lib/isabelle/Sail2_prompt_monad_lemmas.thy     |  41 ++++++++
 lib/isabelle/Sail2_state_lemmas.thy            | 109 ++++++++++++++++---
 lib/isabelle/Sail2_values_lemmas.thy           | 140 ++++++++++++++++++++++++-
 5 files changed, 460 insertions(+), 18 deletions(-)

diff --git a/lib/isabelle/Hoare.thy b/lib/isabelle/Hoare.thy
index 88807c7c..76750117 100644
--- a/lib/isabelle/Hoare.thy
+++ b/lib/isabelle/Hoare.thy
@@ -253,6 +253,27 @@ lemma PrePostE_weaken_post:
 named_theorems PrePostE_compositeI
 named_theorems PrePostE_atomI
 
+lemma PrePostE_conj_conds:
+  assumes "PrePostE P1 m Q1 E1"
+    and "PrePostE P2 m Q2 E2"
+  shows "PrePostE (\<lambda>s. P1 s \<and> P2 s) m (\<lambda>r s. Q1 r s \<and> Q2 r s) (\<lambda>e s. E1 e s \<and> E2 e s)"
+  using assms by (auto intro: PrePostE_I elim: PrePostE_elim)
+
+lemmas PrePostE_conj_conds_consequence = PrePostE_conj_conds[THEN PrePostE_consequence]
+
+lemma PrePostE_post_mp:
+  assumes "PrePostE P m Q' E"
+    and "PrePostE P m (\<lambda>r s. Q' r s \<longrightarrow> Q r s) E"
+  shows "PrePostE P m Q E"
+  using PrePostE_conj_conds[OF assms] by (auto intro: PrePostE_weaken_post)
+
+lemma PrePostE_cong:
+  assumes "\<And>s. P1 s \<longleftrightarrow> P2 s" and "\<And>s. P1 s \<Longrightarrow> m1 s = m2 s" and "\<And>r s. Q1 r s \<longleftrightarrow> Q2 r s"
+    and "\<And>e s. E1 e s \<longleftrightarrow> E2 e s"
+  shows "PrePostE P1 m1 Q1 E1 \<longleftrightarrow> PrePostE P2 m2 Q2 E2"
+  using assms unfolding PrePostE_def PrePost_def
+  by (auto split: result.splits)
+
 lemma PrePostE_True_post[PrePostE_atomI, intro, simp]:
   "PrePostE P m (\<lambda>_ _. True) (\<lambda>_ _. True)"
   unfolding PrePost_defs by (auto split: result.splits)
@@ -320,6 +341,11 @@ lemma PrePostE_option_cases[PrePostE_compositeI]:
   shows "PrePostE (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q E"
   using assms by (auto split: option.splits)
 
+lemma PrePostE_sum_cases[PrePostE_compositeI]:
+  assumes "\<And>a. PrePostE (Pl a) (l a) Q E" and "\<And>b. PrePostE (Pr b) (r b) Q E"
+  shows "PrePostE (case x of Inl a \<Rightarrow> Pl a | Inr b \<Rightarrow> Pr b) (case x of Inl a \<Rightarrow> l a | Inr b \<Rightarrow> r b) Q E"
+  using assms by (auto split: sum.splits)
+
 lemma PrePostE_let[PrePostE_compositeI]:
   assumes "PrePostE P (m y) Q E"
   shows "PrePostE P (let x = y in m x) Q E"
@@ -347,10 +373,51 @@ lemma PrePostE_failS[PrePostE_atomI, intro]:
   "PrePostE (E (Failure msg)) (failS msg) Q E"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
+lemma PrePostE_maybe_failS[PrePostE_atomI]:
+  "PrePostE (\<lambda>s. case v of Some v \<Rightarrow> Q v s | None \<Rightarrow> E (Failure msg) s) (maybe_failS msg v) Q E"
+  by (auto simp: maybe_failS_def split: option.splits)
+
+lemma PrePostE_exitS[PrePostE_atomI, intro]: "PrePostE (E (Failure ''exit'')) (exitS msg) Q E"
+  unfolding exitS_def PrePostE_def PrePost_def failS_def by auto
+
 lemma PrePostE_chooseS[intro, PrePostE_atomI]:
   "PrePostE (\<lambda>s. \<forall>x \<in> xs. Q x s) (chooseS xs) Q E"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
+lemma PrePostE_throwS[PrePostE_atomI]: "PrePostE (E (Throw e)) (throwS e) Q E"
+  by (intro PrePostE_I) (auto simp: throwS_def)
+
+lemma PrePostE_try_catchS[PrePostE_compositeI]:
+  assumes Ph: "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<Longrightarrow> PrePostE (Ph e) (h e) Q E"
+    and m: "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> Ph e | Failure msg \<Rightarrow> E (Failure msg))"
+  shows "PrePostE P (try_catchS m h) Q E"
+  unfolding PrePostE_def
+proof (intro PrePostI)
+  fix s r s'
+  assume "(r, s') \<in> try_catchS m h s" and P: "P s"
+  then show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'" using m
+  proof (cases rule: try_catchS_cases)
+    case (h e s'')
+    then have "Ph e s''" using P m by (auto elim!: PrePostE_elim)
+    then show ?thesis using Ph[OF h(1)] h(2) by (auto elim!: PrePostE_elim)
+  qed (auto elim!: PrePostE_elim)
+qed
+
+lemma PrePostE_catch_early_returnS[PrePostE_compositeI]:
+  assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw (Inl a) \<Rightarrow> Q a | Throw (Inr e) \<Rightarrow> E (Throw e) | Failure msg \<Rightarrow> E (Failure msg))"
+  shows "PrePostE P (catch_early_returnS m) Q E"
+  unfolding catch_early_returnS_def
+  by (rule PrePostE_try_catchS, rule PrePostE_sum_cases[OF PrePostE_returnS PrePostE_throwS])
+     (auto intro: assms)
+
+lemma PrePostE_early_returnS[PrePostE_atomI]: "PrePostE (E (Throw (Inl r))) (early_returnS r) Q E"
+  by (auto simp: early_returnS_def intro: PrePostE_throwS)
+
+lemma PrePostE_liftRS[PrePostE_compositeI]:
+  assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> E (Throw (Inr e)) | Failure msg \<Rightarrow> E (Failure msg))"
+  shows "PrePostE P (liftRS m) Q E"
+  using assms unfolding liftRS_def by (intro PrePostE_try_catchS[OF PrePostE_throwS])
+
 lemma PrePostE_foreachS_Cons:
   assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePostE (Q vars') (foreachS xs vars' body) Q E"
     and "PrePostE (Q vars) (body x vars) Q E"
@@ -363,6 +430,70 @@ lemma PrePostE_foreachS_invariant:
   using assms unfolding PrePostE_def
   by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto
 
+lemma PrePostE_untilS:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, cond, body, s)"
+    and cond: "\<And>vars. PrePostE (Inv' Q vars) (cond vars) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (Inv' Q) E"
+  shows "PrePostE (Inv Q vars) (untilS vars cond body) Q E"
+proof (unfold PrePostE_def, rule PrePostI)
+  fix s r s'
+  assume Inv_s: "Inv Q vars s" and r: "(r, s') \<in> untilS vars cond body s"
+  with dom[OF Inv_s] cond body
+  show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'"
+  proof (induction vars cond body s rule: untilS.pinduct[case_names Step])
+    case (Step vars cond body s)
+    consider
+        (Value) vars' c sb sc where "(Value vars', sb) \<in> body vars s" and "(Value c, sc) \<in> cond vars' sb"
+                                and "if c then r = Value vars' \<and> s' = sc else (r, s') \<in> untilS vars' cond body sc"
+      | (Ex) e where "(Ex e, s') \<in> bindS (body vars) cond s" and "r = Ex e"
+      using Step(1,6)
+      by (auto simp: untilS.psimps returnS_def Ex_bindS_iff elim!: bindS_cases split: if_splits; fastforce)
+    then show ?case
+    proof cases
+      case Value
+      then show ?thesis using Step.IH[OF Value(1,2) _ Step(3,4)] Step(3,4,5)
+        by (auto split: if_splits elim: PrePostE_elim)
+    next
+      case Ex
+      then show ?thesis using Step(3,4,5) by (auto elim!: bindS_cases PrePostE_elim)
+    qed
+  qed
+qed
+
+lemma PrePostE_untilS_pure_cond:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, returnS \<circ> cond, body, s)"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E"
+  shows "PrePostE (Inv Q vars) (untilS vars (returnS \<circ> cond) body) Q E"
+  using assms by (intro PrePostE_untilS) (auto simp: comp_def)
+
+lemma PrePostE_liftState_untilM:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, cond, body)"
+    and cond: "\<And>vars. PrePostE (Inv' Q vars) (liftState r (cond vars)) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (Inv' Q) E"
+  shows "PrePostE (Inv Q vars) (liftState r (untilM vars cond body)) Q E"
+proof -
+  have domS: "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" if "Inv Q vars s" for s
+    using dom that by (intro untilM_dom_untilS_dom)
+  then have "PrePostE (Inv Q vars) (untilS vars (liftState r \<circ> cond) (liftState r \<circ> body)) Q E"
+    using cond body by (auto intro: PrePostE_untilS simp: comp_def)
+  moreover have "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+    if "Inv Q vars s" for s
+    unfolding liftState_untilM[OF domS[OF that] dom[OF that]] ..
+  ultimately show ?thesis by (auto cong: PrePostE_cong)
+qed
+
+lemma PrePostE_liftState_untilM_pure_cond:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, return \<circ> cond, body)"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E"
+  shows "PrePostE (Inv Q vars) (liftState r (untilM vars (return \<circ> cond) body)) Q E"
+  using assms by (intro PrePostE_liftState_untilM) (auto simp: comp_def liftState_simp)
+
+lemma PrePostE_undefined_boolS[PrePostE_atomI]:
+  "PrePostE (\<lambda>s. \<forall>b. Q b s)
+            (undefined_boolS unit) Q E"
+  unfolding undefined_boolS_def seqS_def
+  by (auto intro: PrePostE_strengthen_pre PrePostE_chooseS)
+
 lemma PrePostE_bool_of_bitU_nondetS_any:
   "PrePostE (\<lambda>s. \<forall>b. Q b s) (bool_of_bitU_nondetS b) Q E"
   unfolding bool_of_bitU_nondetS_def undefined_boolS_def
diff --git a/lib/isabelle/Sail2_operators_mwords_lemmas.thy b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
index 2a6272c2..fd54c93a 100644
--- a/lib/isabelle/Sail2_operators_mwords_lemmas.thy
+++ b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
@@ -78,6 +78,57 @@ lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]:
   "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)"
   by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq)
 
+declare subrange_vec_dec_def[simp]
+
+lemma update_subrange_vec_dec_update_subrange_list_dec:
+  assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)"
+  shows "update_subrange_vec_dec (w :: 'a::len word) i j w' =
+         of_bl (update_subrange_list_dec (to_bl w) i j (to_bl w'))"
+  using assms
+  unfolding update_subrange_vec_dec_def update_subrange_list_dec_def update_subrange_list_inc_def
+  by (auto simp: word_update_def split_at_def Let_def nat_diff_distrib min_def)
+
+lemma subrange_vec_dec_subrange_list_dec:
+  assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)" and "int LENGTH('b) = i - j + 1"
+  shows "subrange_vec_dec (w :: 'a::len word) i j = (of_bl (subrange_list_dec (to_bl w) i j) :: 'b::len word)"
+  using assms unfolding subrange_vec_dec_def
+  by (auto simp: subrange_list_dec_drop_take slice_take of_bl_drop')
+
+lemma slice_simp[simp]: "slice w lo len = Word.slice (nat lo) w"
+  by (auto simp: slice_def)
+
+declare slice_id[simp]
+
+lemma of_bools_of_bl[simp]: "of_bools_method BC_mword = of_bl"
+  by (auto simp: BC_mword_defs)
+
+lemma of_bl_bin_word_of_int:
+  "len = LENGTH('a) \<Longrightarrow> of_bl (bin_to_bl_aux len n []) = (word_of_int n :: ('a::len) word)"
+  by (auto simp: of_bl_def bin_bl_bin')
+
+lemma get_slice_int_0_bin_to_bl[simp]:
+  "len > 0 \<Longrightarrow> get_slice_int len n 0 = of_bl (bin_to_bl (nat len) n)"
+  unfolding get_slice_int_def get_slice_int_bv_def subrange_list_def
+  by (auto simp: subrange_list_dec_drop_take len_bin_to_bl_aux)
+
+lemma to_bl_of_bl[simp]:
+  fixes bl :: "bool list"
+  defines w: "w \<equiv> of_bl bl :: 'a::len word"
+  assumes len: "length bl = LENGTH('a)"
+  shows "to_bl w = bl"
+  using len unfolding w by (intro word_bl.Abs_inverse) auto
+
+lemma reverse_endianness_byte[simp]:
+  "LENGTH('a) = 8 \<Longrightarrow> reverse_endianness (w :: 'a::len word) = w"
+  unfolding reverse_endianness_def by (auto simp: reverse_endianness_list_simps)
+
+lemma reverse_reverse_endianness[simp]:
+  "8 dvd LENGTH('a) \<Longrightarrow> reverse_endianness (reverse_endianness w) = (w :: 'a::len word)"
+  unfolding reverse_endianness_def by (simp)
+
+lemma replicate_bits_zero[simp]: "replicate_bits 0 n = 0"
+  by (intro word_eqI) (auto simp: replicate_bits_def test_bit_of_bl rev_nth nth_repeat simp del: repeat.simps)
+
 declare extz_vec_def[simp]
 declare exts_vec_def[simp]
 declare concat_vec_def[simp]
@@ -109,4 +160,10 @@ lemma arith_vec_int_simps[simp]:
   unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
   by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
 
+lemma shiftl_simp[simp]: "shiftl w l = w << (nat l)"
+  by (auto simp: shiftl_def shiftl_mword_def)
+
+lemma shiftr_simp[simp]: "shiftr w l = w >> (nat l)"
+  by (auto simp: shiftr_def shiftr_mword_def)
+
 end
diff --git a/lib/isabelle/Sail2_prompt_monad_lemmas.thy b/lib/isabelle/Sail2_prompt_monad_lemmas.thy
index 3ca1729f..25eb9f52 100644
--- a/lib/isabelle/Sail2_prompt_monad_lemmas.thy
+++ b/lib/isabelle/Sail2_prompt_monad_lemmas.thy
@@ -129,6 +129,16 @@ lemma bind_T_cases:
   | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T"
   using assms by (cases; blast elim: bind.elims)
 
+lemma Run_bindI:
+  fixes m :: "('r, 'a, 'e) monad"
+  assumes "Run m t1 a1"
+    and "Run (f a1) t2 a2"
+  shows "Run (m \<bind> f) (t1 @ t2) a2"
+proof (use assms in \<open>induction m t1 "Done a1 :: ('r, 'a, 'e) monad" rule: Traces.induct\<close>)
+  case (Step s e s'' t)
+  then show ?case by (elim T.cases) auto
+qed auto
+
 lemma Run_bindE:
   fixes m :: "('rv, 'b, 'e) monad" and a :: 'a
   assumes "Run (bind m f) t a"
@@ -161,6 +171,31 @@ lemma Run_DoneE:
 lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a"
   by (auto elim: Run_DoneE)
 
+lemma Run_bindE_ignore_trace:
+  assumes "Run (m \<bind> f) t a"
+  obtains tm tf am where "Run m tm am" and "Run (f am) tf a"
+  using assms by (elim Run_bindE)
+
+lemma Run_letE:
+  assumes "Run (let x = y in f x) t a"
+  obtains "Run (f y) t a"
+  using assms by auto
+
+lemma Run_ifE:
+  assumes "Run (if b then f else g) t a"
+  obtains "b" and "Run f t a" | "\<not>b" and "Run g t a"
+  using assms by (auto split: if_splits)
+
+lemma Run_returnE:
+  assumes "Run (return x) t a"
+  obtains "t = []" and "a = x"
+  using assms by (auto simp: return_def)
+
+lemma Run_early_returnE:
+  assumes "Run (early_return x) t a"
+  shows P
+  using assms by (auto simp: early_return_def throw_def elim: Traces_cases)
+
 lemma bind_cong[fundef_cong]:
   assumes m: "m1 = m2"
     and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a"
@@ -168,4 +203,10 @@ lemma bind_cong[fundef_cong]:
   unfolding m using f
   by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast)
 
+lemma liftR_read_reg[simp]: "liftR (read_reg reg) = read_reg reg" by (auto simp: read_reg_def liftR_def split: option.splits)
+lemma try_catch_return[simp]: "try_catch (return x) h = return x" by (auto simp: return_def)
+lemma liftR_return[simp]: "liftR (return x) = return x" by (auto simp: liftR_def)
+lemma liftR_undefined_bool[simp]: "liftR (undefined_bool ()) = undefined_bool ()" by (auto simp: undefined_bool_def liftR_def)
+lemma assert_exp_True_return[simp]: "assert_exp True msg = return ()" by (auto simp: assert_exp_def return_def)
+
 end
diff --git a/lib/isabelle/Sail2_state_lemmas.thy b/lib/isabelle/Sail2_state_lemmas.thy
index 8f04e850..ba69d0d8 100644
--- a/lib/isabelle/Sail2_state_lemmas.thy
+++ b/lib/isabelle/Sail2_state_lemmas.thy
@@ -23,21 +23,13 @@ lemma Value_liftState_Run:
 
 lemmas liftState_if_distrib[liftState_simp] = if_distrib[where f = "liftState ra" for ra]
 
-lemma member_set_nth:
-  assumes "x \<in> set xs"
-  obtains n where "x = xs ! n" and "n < length xs"
-proof (use assms in \<open>induction xs arbitrary: thesis\<close>)
-  case (Cons a xs) print_cases
-  show ?case proof cases
-    assume "x = a"
-    then show ?thesis using Cons(2)[where n = 0] Cons(3) by auto
-  next
-    assume "x \<noteq> a"
-    then obtain n where "x = xs ! n" and "n < length xs" using Cons by auto
-    then show ?thesis using Cons(2)[of "Suc n"] by auto
-  qed
-qed auto
+lemma Value_bindS_iff:
+  "(Value b, s'') \<in> bindS m f s \<longleftrightarrow> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Value b, s'') \<in> f a s')"
+  by (auto elim!: bindS_cases intro: bindS_intros)
 
+lemma Ex_bindS_iff:
+  "(Ex e, s'') \<in> bindS m f s \<longleftrightarrow> (Ex e, s'') \<in> m s \<or> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Ex e, s'') \<in> f a s')"
+  by (auto elim!: bindS_cases intro: bindS_intros)
 
 lemma liftState_throw[liftState_simp]: "liftState r (throw e) = throwS e"
   by (auto simp: throw_def)
@@ -67,7 +59,7 @@ lemma liftState_try_catch[liftState_simp]:
   by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw)
 
 lemma liftState_early_return[liftState_simp]:
-  "liftState r (early_return r) = early_returnS r"
+  "liftState r (early_return x) = early_returnS x"
   by (auto simp: early_return_def early_returnS_def liftState_simp)
 
 lemma liftState_catch_early_return[liftState_simp]:
@@ -158,6 +150,68 @@ lemma liftState_internal_pick[liftState_simp]:
            simp del: repeat.simps
            cong: option.case_cong)
 
+lemma liftRS_returnS[simp]: "liftRS (returnS x) = returnS x"
+  by (auto simp: liftRS_def)
+
+lemma liftRS_bindS:
+  fixes m :: "('regs, 'a, 'e) monadS" and f :: "'a \<Rightarrow> ('regs, 'b, 'e) monadS"
+  shows "(liftRS (bindS m f) :: ('regs, 'b, 'r, 'e) monadRS) = bindS (liftRS m) (liftRS \<circ> f)"
+proof (intro ext set_eqI iffI)
+  fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state"
+  assume lhs: "rs' \<in> liftRS (bindS m f) s"
+  then show "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s"
+    by (cases rs')
+       (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases
+                  intro: bindS_intros try_catchS_intros)
+next
+  fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state"
+  assume "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s"
+  then show "rs' \<in> liftRS (bindS m f) s"
+    by (cases rs')
+       (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases
+                  intro: bindS_intros try_catchS_intros)
+qed
+
+lemma liftRS_assert_expS_True[simp]: "liftRS (assert_expS True msg) = returnS ()"
+  by (auto simp: liftRS_def assert_expS_def)
+
+lemma untilM_domI:
+  fixes V :: "'vars \<Rightarrow> nat"
+  assumes "Inv vars"
+    and "\<And>vars t vars' t'. \<lbrakk>Inv vars; Run (body vars) t vars'; Run (cond vars') t' False\<rbrakk> \<Longrightarrow> V vars' < V vars \<and> Inv vars'"
+  shows "untilM_dom (vars, cond, body)"
+  using assms
+  by (induction vars rule: measure_induct_rule[where f = V])
+     (auto intro: untilM.domintros)
+
+lemma untilM_dom_untilS_dom:
+  assumes "untilM_dom (vars, cond, body)"
+  shows "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+  using assms
+  by (induction vars cond body arbitrary: s rule: untilM.pinduct)
+     (rule untilS.domintros, auto elim!: Value_liftState_Run)
+
+lemma measure2_induct:
+  fixes f :: "'a \<Rightarrow> 'b \<Rightarrow> nat"
+  assumes "\<And>x1 y1. (\<And>x2 y2. f x2 y2 < f x1 y1 \<Longrightarrow> P x2 y2) \<Longrightarrow> P x1 y1"
+  shows "P x y"
+proof -
+  have "P (fst x) (snd x)" for x
+    by (induction x rule: measure_induct_rule[where f = "\<lambda>x. f (fst x) (snd x)"]) (auto intro: assms)
+  then show ?thesis by auto
+qed
+
+lemma untilS_domI:
+  fixes V :: "'vars \<Rightarrow> 'regs sequential_state \<Rightarrow> nat"
+  assumes "Inv vars s"
+    and "\<And>vars s vars' s' s''.
+           \<lbrakk>Inv vars s; (Value vars', s') \<in> body vars s; (Value False, s'') \<in> cond vars' s'\<rbrakk>
+            \<Longrightarrow> V vars' s'' < V vars s \<and> Inv vars' s''"
+  shows "untilS_dom (vars, cond, body, s)"
+  using assms
+  by (induction vars s rule: measure2_induct[where f = V])
+     (auto intro: untilS.domintros)
+
 lemma whileS_dom_step:
   assumes "whileS_dom (vars, cond, body, s)"
     and "(Value True, s') \<in> cond vars s"
@@ -262,6 +316,9 @@ lemma and_boolM_return_if:
   "and_boolM (return b) y = (if b then y else return False)"
   by (auto simp: and_boolM_def)
 
+lemma and_boolM_return_return_and[simp]: "and_boolM (return l) (return r) = return (l \<and> r)"
+  by (auto simp: and_boolM_def)
+
 lemmas and_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolM x y" for y]
 
 lemma or_boolM_simps[simp]:
@@ -275,6 +332,9 @@ lemma or_boolM_return_if:
   "or_boolM (return b) y = (if b then return True else y)"
   by (auto simp: or_boolM_def)
 
+lemma or_boolM_return_return_or[simp]: "or_boolM (return l) (return r) = return (l \<or> r)"
+  by (auto simp: or_boolM_def)
+
 lemmas or_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolM x y" for y]
 
 lemma if_returnS_returnS[simp]: "(if a then returnS True else returnS False) = returnS a" by auto
@@ -292,8 +352,12 @@ lemma and_boolS_returnS_if:
 
 lemmas and_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolS x y" for y]
 
+lemma and_boolS_returnS_True[simp]: "and_boolS (returnS True) c = c"
+  by (auto simp: and_boolS_def)
+
 lemma or_boolS_simps[simp]:
   "or_boolS (returnS b) (returnS c) = returnS (b \<or> c)"
+  "or_boolS (returnS False) m = m"
   "or_boolS x (returnS True) = bindS x (\<lambda>_. returnS True)"
   "or_boolS x (returnS False) = x"
   "\<And>x y z. or_boolS (bindS x y) z = (bindS x (\<lambda>r. or_boolS (y r) z))"
@@ -305,4 +369,19 @@ lemma or_boolS_returnS_if:
 
 lemmas or_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolS x y" for y]
 
+lemma Run_or_boolM_E:
+  assumes "Run (or_boolM l r) t a"
+  obtains "Run l t True" and "a"
+  | tl tr where "Run l tl False" and "Run r tr a" and "t = tl @ tr"
+  using assms by (auto simp: or_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma Run_and_boolM_E:
+  assumes "Run (and_boolM l r) t a"
+  obtains "Run l t False" and "\<not>a"
+  | tl tr where "Run l tl True" and "Run r tr a" and "t = tl @ tr"
+  using assms by (auto simp: and_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma maybe_failS_Some[simp]: "maybe_failS msg (Some v) = returnS v"
+  by (auto simp: maybe_failS_def)
+
 end
diff --git a/lib/isabelle/Sail2_values_lemmas.thy b/lib/isabelle/Sail2_values_lemmas.thy
index b50d8942..576cd8ea 100644
--- a/lib/isabelle/Sail2_values_lemmas.thy
+++ b/lib/isabelle/Sail2_values_lemmas.thy
@@ -2,18 +2,135 @@ theory Sail2_values_lemmas
   imports Sail2_values
 begin
 
+lemma while_domI:
+  fixes V :: "'vars \<Rightarrow> nat"
+  assumes "\<And>vars. cond vars \<Longrightarrow> V (body vars) < V vars"
+  shows "while_dom (vars, cond, body)"
+  by (induction vars rule: measure_induct_rule[where f = V])
+     (use assms in \<open>auto intro: while.domintros\<close>)
+
 lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def)
 
 termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def)
+declare reverse_endianness_list.simps[simp del]
+declare take_list_def[simp]
+declare drop_list_def[simp]
+
+function take_chunks :: "nat \<Rightarrow> 'a list \<Rightarrow> 'a list list" where
+  "take_chunks n [] = []"
+| "take_chunks 0 xs = []"
+| "take_chunks n xs = take n xs # take_chunks n (drop n xs)" if "n > 0" and "xs \<noteq> []"
+  by auto blast
+termination by lexicographic_order
+
+lemma take_chunks_length_leq_n: "length xs \<le> n \<Longrightarrow> xs \<noteq> [] \<Longrightarrow> take_chunks n xs = [xs]"
+  by (cases n) auto
+
+lemma take_chunks_append: "n dvd length a \<Longrightarrow> take_chunks n (a @ b) = take_chunks n a @ take_chunks n b"
+  by (induction n a rule: take_chunks.induct) (auto simp: dvd_imp_le)
+
+lemma Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x"
+  by auto
+
+lemma byte_chunks_take_chunks_8:
+  assumes "8 dvd length xs"
+  shows "byte_chunks xs = Some (take_chunks 8 xs)"
+proof -
+  have Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x" for x
+    by auto
+  from assms show ?thesis
+    by (induction xs rule: byte_chunks.induct) (auto simp: Suc8_plus8 nat_dvd_not_less)
+qed
+
+lemma reverse_endianness_list_rev_take_chunks:
+  "reverse_endianness_list bits = List.concat (rev (take_chunks 8 bits))"
+  by (induction "8 :: nat" bits rule: take_chunks.induct)
+     (auto simp: reverse_endianness_list.simps)
+
+lemma reverse_endianness_list_simps:
+  "length bits \<le> 8 \<Longrightarrow> reverse_endianness_list bits = bits"
+  "length bits > 8 \<Longrightarrow> reverse_endianness_list bits = reverse_endianness_list (drop 8 bits) @ take 8 bits"
+  by (cases bits; auto simp: reverse_endianness_list_rev_take_chunks)+
+
+lemma reverse_endianness_list_append:
+  assumes "8 dvd length a"
+  shows "reverse_endianness_list (a @ b) = reverse_endianness_list b @ reverse_endianness_list a"
+  using assms by (auto simp: reverse_endianness_list_rev_take_chunks take_chunks_append)
+
+lemma length_reverse_endianness_list[simp]:
+  "length (reverse_endianness_list l) = length l"
+  by (induction l rule: reverse_endianness_list.induct) (auto simp: reverse_endianness_list.simps)
+
+lemma reverse_endianness_list_take_8[simp]:
+  "reverse_endianness_list (take 8 bits) = take 8 bits"
+  by (auto simp: reverse_endianness_list_simps)
+
+lemma reverse_reverse_endianness_list[simp]:
+  assumes "8 dvd length l"
+  shows "reverse_endianness_list (reverse_endianness_list l) = l"
+proof (use assms in \<open>induction l rule: reverse_endianness_list.induct[case_names Step]\<close>)
+  case (Step bits)
+  then show ?case
+    by (auto simp: reverse_endianness_list.simps[of bits] reverse_endianness_list_append)
+qed
+
+declare repeat.simps[simp del]
+
+lemma length_repeat[simp]: "length (repeat xs n) = nat n * length xs"
+proof (induction xs n rule: repeat.induct[case_names Step])
+  case (Step xs n)
+  then show ?case unfolding repeat.simps[of xs n]
+    by (auto simp del: mult_Suc simp: mult_Suc[symmetric])
+qed
+
+lemma nth_repeat:
+  assumes "i < nat n * length xs"
+  shows "repeat xs n ! i = xs ! (i mod length xs)"
+proof (use assms in \<open>induction xs n arbitrary: i rule: repeat.induct[case_names Step]\<close>)
+  case (Step xs n i)
+  show ?case
+    using Step.prems Step.IH[of "i - length xs"]
+    unfolding repeat.simps[of xs n]
+    by (auto simp: nth_append mod_geq[symmetric] nat_diff_distrib diff_mult_distrib)
+qed
 
 termination index_list
   by (relation "measure (\<lambda>(i, j, step). nat ((j - i + step) * sgn step))") auto
 
+lemma index_list_Zero[simp]: "index_list i j 0 = []"
+  by auto
+
+lemma index_list_singleton[simp]: "n \<noteq> 0 \<Longrightarrow> index_list i i n = [i]"
+  by auto
+
+lemma index_list_simps:
+  "0 < step \<Longrightarrow> from \<le> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step"
+  "0 < step \<Longrightarrow> from > to \<Longrightarrow> index_list from to step = []"
+  "0 > step \<Longrightarrow> from \<ge> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step"
+  "0 > step \<Longrightarrow> from < to \<Longrightarrow> index_list from to step = []"
+  by auto
+
+lemma index_list_step1_upto[simp]: "index_list i j 1 = [i..j]"
+  by (induction i j "1 :: int" rule: index_list.induct)
+     (auto simp: index_list_simps upto.simps)
+
+lemma length_upto[simp]: "i \<le> j \<Longrightarrow> length [i..j] = nat (j - i + 1)"
+  by (induction i j rule: upto.induct) (auto simp: upto.simps)
+
+lemma nth_upto[simp]: "i + int n \<le> j \<Longrightarrow> [i..j] ! n = i + int n"
+  by (induction i j arbitrary: n rule: upto.induct)
+     (auto simp: upto.simps nth_Cons split: nat.splits)
+
+declare index_list.simps[simp del]
+
 lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto
 
 lemma just_list_None_iff[simp]: "just_list xs = None \<longleftrightarrow> None \<in> set xs"
   by (induction xs) (auto split: option.splits)
 
+lemma just_list_None_member_None: "None \<in> set xs \<Longrightarrow> just_list xs = None"
+  by auto
+
 lemma just_list_Some_iff[simp]: "just_list xs = Some ys \<longleftrightarrow> xs = map Some ys"
   by (induction xs arbitrary: ys) (auto split: option.splits)
 
@@ -28,10 +145,10 @@ lemma repeat_singleton_replicate[simp]:
 proof (induction n)
   case (nonneg n)
   have "nat (1 + int m) = Suc m" for m by auto
-  then show ?case by (induction n) auto
+  then show ?case by (induction n) (auto simp: repeat.simps)
 next
   case (neg n)
-  then show ?case by auto
+  then show ?case by (auto simp: repeat.simps)
 qed
 
 lemma bool_of_bitU_simps[simp]:
@@ -102,6 +219,15 @@ lemma unsigned_bits_of_mword[simp]:
   "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)"
   by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def)
 
+definition mem_bytes_of_word :: "'a::len word \<Rightarrow> bitU list list" where
+  "mem_bytes_of_word w = rev (take_chunks 8 (map bitU_of_bool (to_bl w)))"
+
+lemma mem_bytes_of_bits_mem_bytes_of_word[simp]:
+  assumes "8 dvd LENGTH('a)"
+  shows "mem_bytes_of_bits BC_mword (w :: 'a::len word) = Some (mem_bytes_of_word w)"
+  using assms
+  by (auto simp: mem_bytes_of_bits_def bytes_of_bits_def BC_mword_defs byte_chunks_take_chunks_8 mem_bytes_of_word_def)
+
 lemma bits_of_bitU_list[simp]:
   "bits_of_method BC_bitU_list v = v"
   "of_bits_method BC_bitU_list v = Some v"
@@ -158,6 +284,14 @@ lemma update_list_dec_update[simp]:
   "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]"
   by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int)
 
+lemma update_list_dec_update_rev:
+  "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> update_list_dec xs n x = rev ((rev xs)[nat n := x])"
+  by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int rev_update)
+
+lemma access_list_dec_update_list_dec[simp]:
+  "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> access_list_dec (update_list_dec xs n x) n = x"
+  by (auto simp: access_list_dec_rev_nth update_list_dec_update_rev)
+
 lemma bools_of_nat_aux_simps[simp]:
   "\<And>len. len \<le> 0 \<Longrightarrow> bools_of_nat_aux len x acc = acc"
   "\<And>len. bools_of_nat_aux (int (Suc len)) x acc =
@@ -200,7 +334,7 @@ proof (induction len arbitrary: n acc)
 qed auto
 
 lemma bools_of_int_bin_to_bl[simp]:
-  "bools_of_int (int len) n = bin_to_bl len n"
+  "bools_of_int len n = bin_to_bl (nat len) n"
   by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def])
 
 end
-- 
cgit v1.2.3


From f652ae23b6cbaa3d70ae38f8942d6ae61af2c1d6 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Tue, 10 Jul 2018 13:57:17 +0100
Subject: Another AArch64 patch

Makes CheckAndUpdateDescriptor respect endianness
---
 aarch64/mono/demo/aarch64_no_vector/spec.sail | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/aarch64/mono/demo/aarch64_no_vector/spec.sail b/aarch64/mono/demo/aarch64_no_vector/spec.sail
index ecb3a050..1cd6fdbd 100644
--- a/aarch64/mono/demo/aarch64_no_vector/spec.sail
+++ b/aarch64/mono/demo/aarch64_no_vector/spec.sail
@@ -6715,6 +6715,7 @@ function AArch64_SecondStageTranslate (S1, vaddress, acctype, iswrite, wasaligne
 }
 
 function AArch64_CheckAndUpdateDescriptor (result, fault, secondstage, vaddress, acctype, iswrite, s2fs1walk, hwupdatewalk__arg) = {
+  let reversedescriptors = (aget_SCTLR()[25] == bitone);
   hwupdatewalk = hwupdatewalk__arg;
   hw_update_AF : bool = undefined;
   if result.AF then if fault.typ == Fault_None then hw_update_AF = true else if ConstrainUnpredictable(Unpredictable_AFUPDATE) == Constraint_TRUE then hw_update_AF = true else hw_update_AF = false else hw_update_AF = false;
@@ -6735,8 +6736,10 @@ function AArch64_CheckAndUpdateDescriptor (result, fault, secondstage, vaddress,
     };
     accdesc = CreateAccessDescriptor(AccType_ATOMICRW);
     desc = aget__Mem(descaddr2, 8, accdesc);
+    if reversedescriptors then desc = BigEndianReverse(desc) else ();
     if hw_update_AF then desc = __SetSlice_bits(64, 1, desc, 10, 0b1) else ();
     if hw_update_AP then desc = __SetSlice_bits(64, 1, desc, 7, if secondstage then 0b1 else 0b0) else ();
+    if reversedescriptors then desc = BigEndianReverse(desc) else ();
     aset__Mem(descaddr2, 8, accdesc, desc)
   } else ();
   return(fault)
-- 
cgit v1.2.3


From adadda8dfc80d0b7e6a967ceeda98624198800c1 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 10 Jul 2018 14:05:36 +0100
Subject: Update HOL setup

---
 aarch64/mono/demo/mk.hol                |   4 +-
 lib/hol/Holmakefile                     |   9 ++-
 lib/hol/Makefile                        |  31 +++----
 lib/hol/prompt.lem                      |  18 -----
 lib/hol/prompt_monad.lem                |  49 -----------
 lib/hol/sail2_prompt.lem                |  19 +++++
 lib/hol/sail2_prompt_monad.lem          |  49 +++++++++++
 lib/hol/sail2_stateAuxiliaryScript.sml  |  61 ++++++++++++++
 lib/hol/sail2_valuesAuxiliaryScript.sml | 139 ++++++++++++++++++++++++++++++++
 lib/hol/sail_valuesAuxiliaryScript.sml  | 139 --------------------------------
 lib/hol/stateAuxiliaryScript.sml        |  61 --------------
 11 files changed, 293 insertions(+), 286 deletions(-)
 delete mode 100644 lib/hol/prompt.lem
 delete mode 100644 lib/hol/prompt_monad.lem
 create mode 100644 lib/hol/sail2_prompt.lem
 create mode 100644 lib/hol/sail2_prompt_monad.lem
 create mode 100644 lib/hol/sail2_stateAuxiliaryScript.sml
 create mode 100644 lib/hol/sail2_valuesAuxiliaryScript.sml
 delete mode 100644 lib/hol/sail_valuesAuxiliaryScript.sml
 delete mode 100644 lib/hol/stateAuxiliaryScript.sml

diff --git a/aarch64/mono/demo/mk.hol b/aarch64/mono/demo/mk.hol
index cd9f84fc..3aa142a3 100755
--- a/aarch64/mono/demo/mk.hol
+++ b/aarch64/mono/demo/mk.hol
@@ -5,5 +5,7 @@ set -ex
      -no_lexp_bounds_check -memo_z3 -undefined_gen \
      -auto_mono -mono_rewrites -dall_split_errors -dmono_continue \
      -lem -lem_mwords -lem_sequential -lem_lib Aarch64_extras -o aarch64_mono
-lem -hol -outdir . -lib ../../../lib/hol -lib ../../../src/gen_lib/ -lib ../../../src/lem_interp ../aarch64_extras.lem aarch64_mono_types.lem aarch64_mono.lem 
+# Explicitly include replacement prompt files, as Lem's choice of file depends
+# on some internal dependency ordering
+lem -hol -outdir . -lib ../../../lib/hol ../../../lib/hol/sail2_prompt_monad.lem ../../../lib/hol/sail2_prompt.lem -lib ../../../src/gen_lib/ -lib ../../../src/lem_interp ../aarch64_extras.lem aarch64_mono_types.lem aarch64_mono.lem 
 Holmake
diff --git a/lib/hol/Holmakefile b/lib/hol/Holmakefile
index eac4fec8..8e8403f3 100644
--- a/lib/hol/Holmakefile
+++ b/lib/hol/Holmakefile
@@ -1,11 +1,12 @@
-LEM_SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \
-  sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \
-  state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml
+LEM_SCRIPTS = sail2_instr_kindsScript.sml sail2_valuesScript.sml sail2_operatorsScript.sml \
+  sail2_operators_mwordsScript.sml sail2_operators_bitlistsScript.sml \
+  sail2_state_monadScript.sml sail2_stateScript.sml sail2_promptScript.sml sail2_prompt_monadScript.sml \
+  sail2_stringScript.sml
 
 LEM_CLEANS = $(LEM_SCRIPTS)
 
 SCRIPTS = $(LEM_SCRIPTS) \
-  sail_valuesAuxiliaryScript.sml stateAuxiliaryScript.sml
+  sail2_valuesAuxiliaryScript.sml sail2_stateAuxiliaryScript.sml
 
 THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
 
diff --git a/lib/hol/Makefile b/lib/hol/Makefile
index 065f887a..783ef23d 100644
--- a/lib/hol/Makefile
+++ b/lib/hol/Makefile
@@ -1,22 +1,25 @@
 LEMSRC =  \
-  ../../src/lem_interp/sail_instr_kinds.lem \
-  ../../src/gen_lib/sail_values.lem \
-  ../../src/gen_lib/sail_operators.lem \
-  ../../src/gen_lib/sail_operators_mwords.lem \
-  ../../src/gen_lib/sail_operators_bitlists.lem \
-  ../../src/gen_lib/state_monad.lem \
-  ../../src/gen_lib/state.lem \
-  prompt_monad.lem \
-  prompt.lem
+  ../../src/lem_interp/sail2_instr_kinds.lem \
+  ../../src/gen_lib/sail2_values.lem \
+  ../../src/gen_lib/sail2_operators.lem \
+  ../../src/gen_lib/sail2_operators_mwords.lem \
+  ../../src/gen_lib/sail2_operators_bitlists.lem \
+  ../../src/gen_lib/sail2_state_monad.lem \
+  ../../src/gen_lib/sail2_state.lem \
+  ../../src/gen_lib/sail2_string.lem \
+  sail2_prompt_monad.lem \
+  sail2_prompt.lem
 
-SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \
-  sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \
-  state_monadScript.sml stateScript.sml \
-  prompt_monadScript.sml promptScript.sml
+SCRIPTS = sail2_instr_kindsScript.sml sail2_valuesScript.sml sail2_operatorsScript.sml \
+  sail2_operators_mwordsScript.sml sail2_operators_bitlistsScript.sml \
+  sail2_state_monadScript.sml sail2_stateScript.sml \
+  sail2_prompt_monadScript.sml sail2_promptScript.sml \
+  sail2_stringScript.sml
 
 THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
 
 all: sail-heap $(THYS)
+all-scripts: $(SCRIPTS)
 
 $(SCRIPTS): $(LEMSRC)
 	lem -hol -outdir . -auxiliary_level none -lib ../../src/lem_interp -lib ../../src/gen_lib $(LEMSRC)
@@ -28,4 +31,4 @@ $(THYS) sail-heap: $(SCRIPTS)
 clean:
 	Holmake cleanAll
 
-.PHONY: all clean
+.PHONY: all all-scripts clean
diff --git a/lib/hol/prompt.lem b/lib/hol/prompt.lem
deleted file mode 100644
index 3597fa06..00000000
--- a/lib/hol/prompt.lem
+++ /dev/null
@@ -1,18 +0,0 @@
-open import Prompt_monad
-open import State_monad
-open import State
-
-let inline undefined_bool = undefined_boolS
-let inline bool_of_bitU_nondet = bool_of_bitU_nondetS
-let inline bool_of_bitU_fail = bool_of_bitU_fail
-let inline bools_of_bits_nondet = bools_of_bits_nondetS
-let inline of_bits_nondet = of_bits_nondetS
-let inline of_bits_fail = of_bits_failS
-let inline mword_nondet = mword_nondetS
-let inline reg_deref = read_regS
-
-let inline foreachM = foreachS
-let inline whileM = whileS
-let inline untilM = untilS
-let inline and_boolM = and_boolS
-let inline or_boolM = or_boolS
diff --git a/lib/hol/prompt_monad.lem b/lib/hol/prompt_monad.lem
deleted file mode 100644
index 8fcd645a..00000000
--- a/lib/hol/prompt_monad.lem
+++ /dev/null
@@ -1,49 +0,0 @@
-open import Pervasives_extra
-open import Sail_instr_kinds
-open import Sail_values
-open import State_monad
-
-(* Fake interface of the prompt monad by redirecting to the state monad, since
-   the former is not currently supported by HOL4 *)
-
-type monad 'rv 'a 'e = monadS 'rv 'a 'e
-type monadR 'rv 'a 'e 'r = monadRS 'rv 'a 'e 'r
-
-(* We need to use a target_rep for these because HOL doesn't handle unused
-   type parameters well. *)
-
-type base_monad 'regval 'regstate 'a 'e = monad 'regstate 'a 'e
-declare hol target_rep type base_monad 'regval 'regstate 'a 'e = `monad` 'regstate 'a 'e
-type base_monadR 'regval 'regstate 'a 'r 'e = monadR 'regstate 'a 'r 'e
-declare hol target_rep type base_monadR 'regval 'regstate 'a 'r 'e = `monadR` 'regstate 'a 'r 'e
-
-let inline return = returnS
-let inline bind = bindS
-let inline (>>=) = (>>$=)
-let inline (>>) = (>>$)
-
-let inline exit = exitS
-
-let inline throw = throwS
-let inline try_catch = try_catchS
-
-let inline catch_early_return = catch_early_returnS
-let inline early_return = early_returnS
-let inline liftR = liftRS
-let inline try_catchR = try_catchRS
-
-let inline maybe_fail = maybe_failS
-
-let inline read_mem_bytes = read_mem_bytesS
-let inline read_reg = read_regS
-let inline reg_deref = read_regS
-let inline read_mem = read_memS
-let inline read_tag = read_tagS
-let inline excl_result = excl_resultS
-let inline write_reg = write_regS
-let inline write_tag = write_tagS
-let inline write_mem_ea wk addr sz = write_mem_eaS wk addr (nat_of_int sz)
-let inline write_mem_val = write_mem_valS
-let barrier _ = return ()
-
-let inline assert_exp = assert_expS
diff --git a/lib/hol/sail2_prompt.lem b/lib/hol/sail2_prompt.lem
new file mode 100644
index 00000000..674d4e34
--- /dev/null
+++ b/lib/hol/sail2_prompt.lem
@@ -0,0 +1,19 @@
+open import Sail2_prompt_monad
+open import Sail2_state_monad
+open import Sail2_state
+
+let inline undefined_bool = undefined_boolS
+let inline bool_of_bitU_nondet = bool_of_bitU_nondetS
+let inline bool_of_bitU_fail = bool_of_bitU_fail
+let inline bools_of_bits_nondet = bools_of_bits_nondetS
+let inline of_bits_nondet = of_bits_nondetS
+let inline of_bits_fail = of_bits_failS
+let inline mword_nondet = mword_nondetS
+let inline reg_deref = read_regS
+let inline internal_pick = internal_pickS
+
+let inline foreachM = foreachS
+let inline whileM = whileS
+let inline untilM = untilS
+let inline and_boolM = and_boolS
+let inline or_boolM = or_boolS
diff --git a/lib/hol/sail2_prompt_monad.lem b/lib/hol/sail2_prompt_monad.lem
new file mode 100644
index 00000000..3af931a5
--- /dev/null
+++ b/lib/hol/sail2_prompt_monad.lem
@@ -0,0 +1,49 @@
+open import Pervasives_extra
+open import Sail2_instr_kinds
+open import Sail2_values
+open import Sail2_state_monad
+
+(* Fake interface of the prompt monad by redirecting to the state monad, since
+   the former is not currently supported by HOL4 *)
+
+type monad 'rv 'a 'e = monadS 'rv 'a 'e
+type monadR 'rv 'a 'e 'r = monadRS 'rv 'a 'e 'r
+
+(* We need to use a target_rep for these because HOL doesn't handle unused
+   type parameters well. *)
+
+type base_monad 'regval 'regstate 'a 'e = monad 'regstate 'a 'e
+declare hol target_rep type base_monad 'regval 'regstate 'a 'e = `monad` 'regstate 'a 'e
+type base_monadR 'regval 'regstate 'a 'r 'e = monadR 'regstate 'a 'r 'e
+declare hol target_rep type base_monadR 'regval 'regstate 'a 'r 'e = `monadR` 'regstate 'a 'r 'e
+
+let inline return = returnS
+let inline bind = bindS
+let inline (>>=) = (>>$=)
+let inline (>>) = (>>$)
+
+let inline exit = exitS
+
+let inline throw = throwS
+let inline try_catch = try_catchS
+
+let inline catch_early_return = catch_early_returnS
+let inline early_return = early_returnS
+let inline liftR = liftRS
+let inline try_catchR = try_catchRS
+
+let inline maybe_fail = maybe_failS
+
+let inline read_mem_bytes = read_mem_bytesS
+let inline read_reg = read_regS
+let inline reg_deref = read_regS
+let inline read_mem = read_memS
+let inline read_tag = read_tagS
+let inline excl_result = excl_resultS
+let inline write_reg = write_regS
+let inline write_tag = write_tagS
+let inline write_mem_ea wk addr sz = write_mem_eaS wk addr (nat_of_int sz)
+let inline write_mem_val = write_mem_valS
+let barrier _ = return ()
+
+let inline assert_exp = assert_expS
diff --git a/lib/hol/sail2_stateAuxiliaryScript.sml b/lib/hol/sail2_stateAuxiliaryScript.sml
new file mode 100644
index 00000000..4d70b033
--- /dev/null
+++ b/lib/hol/sail2_stateAuxiliaryScript.sml
@@ -0,0 +1,61 @@
+(*Generated by Lem from ../../src/gen_lib/state.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory sail2_stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "sail2_stateAuxiliary"
+
+
+(****************************************************)
+(*                                                  *)
+(* Termination Proofs                               *)
+(*                                                  *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (iterS_aux_def, iterS_aux_ind) *)
+val (iterS_aux_rw, iterS_aux_ind_rw) =
+  Defn.tprove_no_defn ((iterS_aux_def, iterS_aux_ind),
+    WF_REL_TAC`measure (LENGTH o SND o SND)` \\ rw[]
+  )
+val iterS_aux_rw = save_thm ("iterS_aux_rw", iterS_aux_rw);
+val iterS_aux_ind_rw = save_thm ("iterS_aux_ind_rw", iterS_aux_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (foreachS_def, foreachS_ind) *)
+val (foreachS_rw, foreachS_ind_rw) =
+  Defn.tprove_no_defn ((foreachS_def, foreachS_ind),
+    WF_REL_TAC`measure (LENGTH o FST)` \\ rw[]
+  )
+val foreachS_rw = save_thm ("foreachS_rw", foreachS_rw);
+val foreachS_ind_rw = save_thm ("foreachS_ind_rw", foreachS_ind_rw);
+
+
+(*
+These are unprovable.
+
+(* val gst = Defn.tgoal_no_defn (whileS_def, whileS_ind) *)
+val (whileS_rw, whileS_ind_rw) =
+  Defn.tprove_no_defn ((whileS_def, whileS_ind),
+    cheat (* the termination proof *)
+  )
+val whileS_rw = save_thm ("whileS_rw", whileS_rw);
+val whileS_ind_rw = save_thm ("whileS_ind_rw", whileS_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (untilS_def, untilS_ind) *)
+val (untilS_rw, untilS_ind_rw) =
+  Defn.tprove_no_defn ((untilS_def, untilS_ind),
+    cheat (* the termination proof *)
+  )
+val untilS_rw = save_thm ("untilS_rw", untilS_rw);
+val untilS_ind_rw = save_thm ("untilS_ind_rw", untilS_ind_rw);
+*)
+
+
+val _ = export_theory()
+
diff --git a/lib/hol/sail2_valuesAuxiliaryScript.sml b/lib/hol/sail2_valuesAuxiliaryScript.sml
new file mode 100644
index 00000000..b475c5ea
--- /dev/null
+++ b/lib/hol/sail2_valuesAuxiliaryScript.sml
@@ -0,0 +1,139 @@
+(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory;
+open intLib;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "sail2_valuesAuxiliary"
+
+
+(****************************************************)
+(*                                                  *)
+(* Termination Proofs                               *)
+(*                                                  *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (shr_int_def, shr_int_ind) *)
+val (shr_int_rw, shr_int_ind_rw) =
+  Defn.tprove_no_defn ((shr_int_def, shr_int_ind),
+    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+  )
+val shr_int_rw = save_thm ("shr_int_rw", shr_int_rw);
+val shr_int_ind_rw = save_thm ("shr_int_ind_rw", shr_int_ind_rw);
+val () = computeLib.add_persistent_funs["shr_int_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (shl_int_def, shl_int_ind) *)
+val (shl_int_rw, shl_int_ind_rw) =
+  Defn.tprove_no_defn ((shl_int_def, shl_int_ind),
+    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+  )
+val shl_int_rw = save_thm ("shl_int_rw", shl_int_rw);
+val shl_int_ind_rw = save_thm ("shl_int_ind_rw", shl_int_ind_rw);
+val () = computeLib.add_persistent_funs["shl_int_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (repeat_def, repeat_ind) *)
+val (repeat_rw, repeat_ind_rw) =
+  Defn.tprove_no_defn ((repeat_def, repeat_ind),
+    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+  )
+val repeat_rw = save_thm ("repeat_rw", repeat_rw);
+val repeat_ind_rw = save_thm ("repeat_ind_rw", repeat_ind_rw);
+val () = computeLib.add_persistent_funs["repeat_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (bools_of_nat_aux_def, bools_of_nat_aux_ind) *)
+val (bools_of_nat_aux_rw, bools_of_nat_aux_ind_rw) =
+  Defn.tprove_no_defn ((bools_of_nat_aux_def, bools_of_nat_aux_ind),
+    WF_REL_TAC`measure (Num o FST)` \\ COOPER_TAC
+  )
+val bools_of_nat_aux_rw = save_thm ("bools_of_nat_aux_rw", bools_of_nat_aux_rw);
+val bools_of_nat_aux_ind_rw = save_thm ("bools_of_nat_aux_ind_rw", bools_of_nat_aux_ind_rw);
+val () = computeLib.add_persistent_funs["bools_of_nat_aux_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (pad_list_def, pad_list_ind) *)
+val (pad_list_rw, pad_list_ind_rw) =
+  Defn.tprove_no_defn ((pad_list_def, pad_list_ind),
+    WF_REL_TAC`measure (Num o SND o SND)` \\ COOPER_TAC
+  )
+val pad_list_rw = save_thm ("pad_list_rw", pad_list_rw);
+val pad_list_ind_rw = save_thm ("pad_list_ind_rw", pad_list_ind_rw);
+val () = computeLib.add_persistent_funs["pad_list_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (reverse_endianness_list_def, reverse_endianness_list_ind) *)
+val (reverse_endianness_list_rw, reverse_endianness_list_ind_rw) =
+  Defn.tprove_no_defn ((reverse_endianness_list_def, reverse_endianness_list_ind),
+    WF_REL_TAC`measure LENGTH` \\ rw[drop_list_def,nat_of_int_def]
+  )
+val reverse_endianness_list_rw = save_thm ("reverse_endianness_list_rw", reverse_endianness_list_rw);
+val reverse_endianness_list_ind_rw = save_thm ("reverse_endianness_list_ind_rw", reverse_endianness_list_ind_rw);
+val () = computeLib.add_persistent_funs["reverse_endianness_list_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (index_list_def, index_list_ind) *)
+val (index_list_rw, index_list_ind_rw) =
+  Defn.tprove_no_defn ((index_list_def, index_list_ind),
+    WF_REL_TAC`measure (λ(x,y,z). Num(1+(if z > 0 then int_max (-1) (y - x) else int_max (-1) (x - y))))`
+    \\ rw[integerTheory.INT_MAX]
+    \\ intLib.COOPER_TAC
+  )
+val index_list_rw = save_thm ("index_list_rw", index_list_rw);
+val index_list_ind_rw = save_thm ("index_list_ind_rw", index_list_ind_rw);
+val () = computeLib.add_persistent_funs["index_list_rw"];
+
+
+(*
+(* val gst = Defn.tgoal_no_defn (while_def, while_ind) *)
+val (while_rw, while_ind_rw) =
+  Defn.tprove_no_defn ((while_def, while_ind),
+    cheat (* the termination proof *)
+  )
+val while_rw = save_thm ("while_rw", while_rw);
+val while_ind_rw = save_thm ("while_ind_rw", while_ind_rw);
+*)
+
+
+(*
+(* val gst = Defn.tgoal_no_defn (until_def, until_ind) *)
+val (until_rw, until_ind_rw) =
+  Defn.tprove_no_defn ((until_def, until_ind),
+    cheat (* the termination proof *)
+  )
+val until_rw = save_thm ("until_rw", until_rw);
+val until_ind_rw = save_thm ("until_ind_rw", until_ind_rw);
+*)
+
+
+(****************************************************)
+(*                                                  *)
+(* Lemmata                                          *)
+(*                                                  *)
+(****************************************************)
+
+val just_list_spec = store_thm("just_list_spec",
+``((! xs. (just_list xs = NONE) <=> MEM NONE xs) /\
+   (! xs es. (just_list xs = SOME es) <=> (xs = MAP SOME es)))``,
+  (* Theorem: just_list_spec*)
+  conj_tac
+  \\ ho_match_mp_tac just_list_ind
+  \\ Cases \\ rw[]
+  \\ rw[Once just_list_def]
+  >- ( CASE_TAC \\ fs[] \\ CASE_TAC )
+  >- PROVE_TAC[]
+  \\ Cases_on`es` \\ fs[]
+  \\ CASE_TAC \\ fs[]
+  \\ CASE_TAC \\ fs[]
+);
+
+
+
+val _ = export_theory()
+
diff --git a/lib/hol/sail_valuesAuxiliaryScript.sml b/lib/hol/sail_valuesAuxiliaryScript.sml
deleted file mode 100644
index aa169979..00000000
--- a/lib/hol/sail_valuesAuxiliaryScript.sml
+++ /dev/null
@@ -1,139 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory;
-open intLib;
-
-val _ = numLib.prefer_num();
-
-
-
-open lemLib;
-(* val _ = lemLib.run_interactive := true; *)
-val _ = new_theory "sail_valuesAuxiliary"
-
-
-(****************************************************)
-(*                                                  *)
-(* Termination Proofs                               *)
-(*                                                  *)
-(****************************************************)
-
-(* val gst = Defn.tgoal_no_defn (shr_int_def, shr_int_ind) *)
-val (shr_int_rw, shr_int_ind_rw) =
-  Defn.tprove_no_defn ((shr_int_def, shr_int_ind),
-    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
-  )
-val shr_int_rw = save_thm ("shr_int_rw", shr_int_rw);
-val shr_int_ind_rw = save_thm ("shr_int_ind_rw", shr_int_ind_rw);
-val () = computeLib.add_persistent_funs["shr_int_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (shl_int_def, shl_int_ind) *)
-val (shl_int_rw, shl_int_ind_rw) =
-  Defn.tprove_no_defn ((shl_int_def, shl_int_ind),
-    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
-  )
-val shl_int_rw = save_thm ("shl_int_rw", shl_int_rw);
-val shl_int_ind_rw = save_thm ("shl_int_ind_rw", shl_int_ind_rw);
-val () = computeLib.add_persistent_funs["shl_int_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (repeat_def, repeat_ind) *)
-val (repeat_rw, repeat_ind_rw) =
-  Defn.tprove_no_defn ((repeat_def, repeat_ind),
-    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
-  )
-val repeat_rw = save_thm ("repeat_rw", repeat_rw);
-val repeat_ind_rw = save_thm ("repeat_ind_rw", repeat_ind_rw);
-val () = computeLib.add_persistent_funs["repeat_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (bools_of_nat_aux_def, bools_of_nat_aux_ind) *)
-val (bools_of_nat_aux_rw, bools_of_nat_aux_ind_rw) =
-  Defn.tprove_no_defn ((bools_of_nat_aux_def, bools_of_nat_aux_ind),
-    WF_REL_TAC`measure (Num o FST)` \\ COOPER_TAC
-  )
-val bools_of_nat_aux_rw = save_thm ("bools_of_nat_aux_rw", bools_of_nat_aux_rw);
-val bools_of_nat_aux_ind_rw = save_thm ("bools_of_nat_aux_ind_rw", bools_of_nat_aux_ind_rw);
-val () = computeLib.add_persistent_funs["bools_of_nat_aux_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (pad_list_def, pad_list_ind) *)
-val (pad_list_rw, pad_list_ind_rw) =
-  Defn.tprove_no_defn ((pad_list_def, pad_list_ind),
-    WF_REL_TAC`measure (Num o SND o SND)` \\ COOPER_TAC
-  )
-val pad_list_rw = save_thm ("pad_list_rw", pad_list_rw);
-val pad_list_ind_rw = save_thm ("pad_list_ind_rw", pad_list_ind_rw);
-val () = computeLib.add_persistent_funs["pad_list_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (reverse_endianness_list_def, reverse_endianness_list_ind) *)
-val (reverse_endianness_list_rw, reverse_endianness_list_ind_rw) =
-  Defn.tprove_no_defn ((reverse_endianness_list_def, reverse_endianness_list_ind),
-    WF_REL_TAC`measure LENGTH` \\ rw[drop_list_def,nat_of_int_def]
-  )
-val reverse_endianness_list_rw = save_thm ("reverse_endianness_list_rw", reverse_endianness_list_rw);
-val reverse_endianness_list_ind_rw = save_thm ("reverse_endianness_list_ind_rw", reverse_endianness_list_ind_rw);
-val () = computeLib.add_persistent_funs["reverse_endianness_list_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (index_list_def, index_list_ind) *)
-val (index_list_rw, index_list_ind_rw) =
-  Defn.tprove_no_defn ((index_list_def, index_list_ind),
-    WF_REL_TAC`measure (λ(x,y,z). Num(1+(if z > 0 then int_max (-1) (y - x) else int_max (-1) (x - y))))`
-    \\ rw[integerTheory.INT_MAX]
-    \\ intLib.COOPER_TAC
-  )
-val index_list_rw = save_thm ("index_list_rw", index_list_rw);
-val index_list_ind_rw = save_thm ("index_list_ind_rw", index_list_ind_rw);
-val () = computeLib.add_persistent_funs["index_list_rw"];
-
-
-(*
-(* val gst = Defn.tgoal_no_defn (while_def, while_ind) *)
-val (while_rw, while_ind_rw) =
-  Defn.tprove_no_defn ((while_def, while_ind),
-    cheat (* the termination proof *)
-  )
-val while_rw = save_thm ("while_rw", while_rw);
-val while_ind_rw = save_thm ("while_ind_rw", while_ind_rw);
-*)
-
-
-(*
-(* val gst = Defn.tgoal_no_defn (until_def, until_ind) *)
-val (until_rw, until_ind_rw) =
-  Defn.tprove_no_defn ((until_def, until_ind),
-    cheat (* the termination proof *)
-  )
-val until_rw = save_thm ("until_rw", until_rw);
-val until_ind_rw = save_thm ("until_ind_rw", until_ind_rw);
-*)
-
-
-(****************************************************)
-(*                                                  *)
-(* Lemmata                                          *)
-(*                                                  *)
-(****************************************************)
-
-val just_list_spec = store_thm("just_list_spec",
-``((! xs. (just_list xs = NONE) <=> MEM NONE xs) /\
-   (! xs es. (just_list xs = SOME es) <=> (xs = MAP SOME es)))``,
-  (* Theorem: just_list_spec*)
-  conj_tac
-  \\ ho_match_mp_tac just_list_ind
-  \\ Cases \\ rw[]
-  \\ rw[Once just_list_def]
-  >- ( CASE_TAC \\ fs[] \\ CASE_TAC )
-  >- PROVE_TAC[]
-  \\ Cases_on`es` \\ fs[]
-  \\ CASE_TAC \\ fs[]
-  \\ CASE_TAC \\ fs[]
-);
-
-
-
-val _ = export_theory()
-
diff --git a/lib/hol/stateAuxiliaryScript.sml b/lib/hol/stateAuxiliaryScript.sml
deleted file mode 100644
index c8269750..00000000
--- a/lib/hol/stateAuxiliaryScript.sml
+++ /dev/null
@@ -1,61 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/state.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_valuesTheory state_monadTheory stateTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-open lemLib;
-(* val _ = lemLib.run_interactive := true; *)
-val _ = new_theory "stateAuxiliary"
-
-
-(****************************************************)
-(*                                                  *)
-(* Termination Proofs                               *)
-(*                                                  *)
-(****************************************************)
-
-(* val gst = Defn.tgoal_no_defn (iterS_aux_def, iterS_aux_ind) *)
-val (iterS_aux_rw, iterS_aux_ind_rw) =
-  Defn.tprove_no_defn ((iterS_aux_def, iterS_aux_ind),
-    WF_REL_TAC`measure (LENGTH o SND o SND)` \\ rw[]
-  )
-val iterS_aux_rw = save_thm ("iterS_aux_rw", iterS_aux_rw);
-val iterS_aux_ind_rw = save_thm ("iterS_aux_ind_rw", iterS_aux_ind_rw);
-
-
-(* val gst = Defn.tgoal_no_defn (foreachS_def, foreachS_ind) *)
-val (foreachS_rw, foreachS_ind_rw) =
-  Defn.tprove_no_defn ((foreachS_def, foreachS_ind),
-    WF_REL_TAC`measure (LENGTH o FST)` \\ rw[]
-  )
-val foreachS_rw = save_thm ("foreachS_rw", foreachS_rw);
-val foreachS_ind_rw = save_thm ("foreachS_ind_rw", foreachS_ind_rw);
-
-
-(*
-These are unprovable.
-
-(* val gst = Defn.tgoal_no_defn (whileS_def, whileS_ind) *)
-val (whileS_rw, whileS_ind_rw) =
-  Defn.tprove_no_defn ((whileS_def, whileS_ind),
-    cheat (* the termination proof *)
-  )
-val whileS_rw = save_thm ("whileS_rw", whileS_rw);
-val whileS_ind_rw = save_thm ("whileS_ind_rw", whileS_ind_rw);
-
-
-(* val gst = Defn.tgoal_no_defn (untilS_def, untilS_ind) *)
-val (untilS_rw, untilS_ind_rw) =
-  Defn.tprove_no_defn ((untilS_def, untilS_ind),
-    cheat (* the termination proof *)
-  )
-val untilS_rw = save_thm ("untilS_rw", untilS_rw);
-val untilS_ind_rw = save_thm ("untilS_ind_rw", untilS_ind_rw);
-*)
-
-
-val _ = export_theory()
-
-- 
cgit v1.2.3


From f6a49e32fc943444a5a38088abe9ff6a5cabed75 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 10 Jul 2018 14:54:27 +0100
Subject: remove obsolete files from language directory.

---
 language/Makefile                |   54 --
 language/l2_parse.ott            | 1407 -------------------------------------
 language/l2_parse2.ott           | 1424 --------------------------------------
 language/l2_rules.ott            |  424 ------------
 language/l2_terminals_non_tt.ott |   31 -
 language/l2_terminals_tt.ott     |   31 -
 language/l2_typ.ott              |  382 ----------
 language/primitive_doc.ott       |  130 ----
 language/type_system.tex         |  117 ----
 9 files changed, 4000 deletions(-)
 delete mode 100644 language/Makefile
 delete mode 100644 language/l2_parse.ott
 delete mode 100644 language/l2_parse2.ott
 delete mode 100644 language/l2_rules.ott
 delete mode 100644 language/l2_terminals_non_tt.ott
 delete mode 100644 language/l2_terminals_tt.ott
 delete mode 100644 language/l2_typ.ott
 delete mode 100644 language/primitive_doc.ott
 delete mode 100644 language/type_system.tex

diff --git a/language/Makefile b/language/Makefile
deleted file mode 100644
index 759523b7..00000000
--- a/language/Makefile
+++ /dev/null
@@ -1,54 +0,0 @@
-#OTT=../../../rsem/ott/bin/ott
-# this is the binary that gets rebuilt by make in ott/src:
-OTT=../../ott/src/ott
-OTTLIB=$(dir $(shell which ott))../hol
-
-.PHONY: all
-all: l2.ml l2_parse.ml l2.lem l2_parse2.ml l2_parse2_parser.mly
-
-docs: l2.pdf l2_parse.pdf 
-
-%.pdf: %.tex
-	pdflatex $<
-
-%Theory.uo: %Script.sml
-	Holmake --qof -I $(OTTLIB) $@
-
-type_system.pdf: doc_in.tex type_system.tex
-	pdflatex type_system.tex
-	pdflatex type_system.tex
-
-l2.tex: l2.ott  l2_rules.ott # l2_terminals_non_tt.ott  l2_typ.ott l2_rules.ott
-	$(OTT) -sort false -generate_aux_rules false -o $@ -picky_multiple_parses true $^
-
-doc_in.tex: l2.ott primitive_doc.ott l2_terminals_tt.ott l2_typ.ott l2_rules.ott
-	$(OTT) -sort false -generate_aux_rules false -tex_wrap false -o $@ -picky_multiple_parses true $^
-
-%.tex: %.ott
-	$(OTT) -sort false -generate_aux_rules false -o $@ -picky_multiple_parses true $^
-
-%.ml: %.ott
-	$(OTT) -sort false -generate_aux_rules true -o $@ -picky_multiple_parses true $^
-
-%Script.sml: %.ott
-	$(OTT) -sort false -generate_aux_rules true -o $@ -picky_multiple_parses true $^
-
-l2.lem: l2.ott
-	$(OTT) -sort false -generate_aux_rules true -o $@ -picky_multiple_parses true $^
-
-ROOT=l2_parse2
-# generate the ocaml AST type, ocamllex lexer, menhir parser, and ocaml pretty printers for the AST, all from the Ott soruce
-$(ROOT)_ast.ml  $(ROOT)_lexer.mll $(ROOT)_parser.mly $(ROOT)_parser_pp.ml $(ROOT)_ast.tex : $(ROOT).ott Makefile
-	$(OTT) -quotient_rules false -generate_aux_rules false -i $(ROOT).ott  -o $(ROOT)_parser.mly -o $(ROOT)_lexer.mll -o $(ROOT)_ast.ml -o $(ROOT).tex
-
-
-clean:
-	rm -rf *~
-	rm -rf *.uo *.ui *.sig *.sml .HOLMK
-	rm -f *.aux *.log *.dvi *.ps *.pdf *.toc
-	rm -rf l2.pdf l2_parse.pdf 
-	rm -rf l2.tex doc_in.tex
-
-realclean:
-	$(MAKE) clean
-	rm -rf l2.ml l2_parse.ml l2.lem
diff --git a/language/l2_parse.ott b/language/l2_parse.ott
deleted file mode 100644
index 49df4908..00000000
--- a/language/l2_parse.ott
+++ /dev/null
@@ -1,1407 +0,0 @@
-indexvar n , i , j , k ::=
-  {{ phantom }}
-  {{ com Index variables for meta-lists }}
-
-metavar num ::=
-  {{ phantom }}
-  {{ lex numeric }}
-  {{ ocaml int }}
-  {{ hol num }}
-  {{ lem integer }}
-  {{ com Numeric literals }}
-
-metavar hex ::=
-  {{ phantom }}
-  {{ lex numeric }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ com Bit vector literal, specified by C-style hex number }}
-  
-metavar bin ::=
-  {{ phantom }}
-  {{ lex numeric }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ com Bit vector literal, specified by C-style binary number }}  
-
-metavar string ::=
-  {{ phantom }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ com String literals }}
-
-metavar regexp ::=
-  {{ phantom }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ com Regular expresions, as a string literal }}
-
-embed
-{{ ocaml
-
-type l =
-  | Unknown
-  | Int of string * l option
-  | Generated of l
-  | Range of Lexing.position * Lexing.position
-
-type 'a annot = l * 'a
-
-exception Parse_error_locn of l * string
-
-}}
-
-embed
-{{ lem
-open import Map
-open import Maybe
-open import Pervasives
-
-type l =
-  | Unknown
-  | Trans of string * maybe l
-  | Range of nat * nat
-
-val duplicates : forall 'a. list 'a -> list 'a
-
-val union_map : forall 'a 'b. map 'a 'b -> map 'a 'b -> map 'a 'b
-
-val set_from_list : forall 'a. list 'a -> set 'a
-
-val subst : forall 'a. list 'a -> list 'a -> bool
-
-}}
-
-metavar x , y , z ::=
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ com identifier }}
-  {{ ocamlvar "[[x]]" }}
-  {{ lemvar "[[x]]" }}
-
-metavar ix ::=
-  {{ lex alphanum }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ com infix identifier }}
-  {{ ocamlvar "[[ix]]" }}
-  {{ lemvar "[[ix]]" }}
-
-
-
-grammar
-
-l :: '' ::=                                     {{ phantom }}
-                                                {{ ocaml l }}
-                                                {{ lem l }}
-                                                {{ hol unit }}
-  {{ com Source location }}
-  |                                             :: :: Unknown
-    {{ ocaml Unknown }}
-    {{ lem Unknown }}
-    {{ hol () }}
-
-
-id :: '' ::=
-  {{ com Identifier }}
-  {{ aux _ l }}
-  | x                           :: :: id
-  | ( deinfix x )                       :: :: deIid {{ com remove infix status }}
-
-
-kid :: '' ::=
-  {{ com identifiers with kind, ticked to differntiate from program variables }}
-  {{ aux _ l }}
-  | ' x                       :: :: var
-
-% Note: we have just a single namespace. We don't want the same
-% identifier to be reused as a type name or variable, expression
-% variable, and field name.  We don't enforce any lexical convention
-% on type variables (or variables of other kinds)
-% We don't enforce a lexical convention on infix operators, as some of the 
-% targets use alphabetical infix operators. 
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Kinds and Types                                              %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-grammar
-
-base_kind :: 'BK_' ::=  
-  {{ com base kind}}
-  {{ aux _ l }}
-  | Type                                       :: :: type    {{ com kind of types  }} 
-  | Nat                                        :: :: nat     {{ com kind of natural number size expressions  }} 
-  | Order                                     :: :: order  {{ com kind of vector order specifications  }} 
-  | Effect                                    :: :: effect {{ com kind of effect sets  }} 
-
-kind :: 'K_' ::=  
-  {{ com kinds}}
-  {{ aux _ l }}
-  | base_kind1 -> ... -> base_kindn            :: :: kind 
-% we'll never use  ...-> Nat
-
-base_effect :: 'BE_' ::=
-  {{ com effect }}
-  {{ aux _ l }}  
-  | rreg                                :: :: rreg {{ com read register }}
-  | wreg                                :: :: wreg {{ com write register }}
-  | rmem                                :: :: rmem {{ com read memory }}
-  | wmem                                :: :: wmem {{ com write memory }}
-  | wmv					:: :: wmv {{ com write memory value }}
-  | eamem				:: :: eamem {{ com address for write signaled }}
-  | barr                                :: :: barr {{ com memory barrier }}
-  | depend				:: :: depend {{ com dynmically dependent footprint }}
-  | undef                               :: :: undef {{ com undefined-instruction exception }}
-  | unspec                              :: :: unspec {{ com unspecified values }}
-  | nondet                              :: :: nondet {{ com nondeterminism from intra-instruction parallelism }}
-  | escape                              :: :: escape
-
-atyp :: 'ATyp_' ::=
-  {{ com expressions of all kinds, to be translated to types, nats, orders, and effects after parsing }}
-  {{ aux _ l }}
-  | id                                  :: :: id          {{ com identifier }}
-  | kid                                 :: :: var         {{ com ticked variable }}
-  | num                                 :: :: constant     {{ com constant }}
-  | atyp1 * atyp2                       :: :: times        {{ com product }}
-  | atyp1 + atyp2                       :: :: sum          {{ com sum }}
-  | atyp1 - atyp2                        :: :: minus	     {{ com subtraction }}
-  | 2** atyp                            :: :: exp         {{ com exponential }}
-  | neg atyp				:: :: neg	  {{ com Internal (but not M as I want a datatype constructor) negative nexp }}
-  | ( atyp )                            :: S :: paren  {{ icho [[atyp]] }}
-
-  | inc                                 :: :: inc  {{ com increasing (little-endian) }}
-  | dec                                 :: :: dec  {{ com decreasing (big-endian) }}
-  | defaultOrd                          :: :: default_ord {{ com default order for increasing or decreasing signficant bits }}
-  | { base_effect1 , .. , base_effectn }           :: :: set {{ com effect set }}
-  | pure                                 :: M :: pure {{ com sugar for empty effect set }} {{ icho [] }}
-  | atyp1 -> atyp2 effect atyp3                        :: :: fn
-    {{ com Function type (first-order only in user code), last atyp is an effect }}
-  | ( atyp1 , .... , atypn )                        :: :: tup
-    {{ com Tuple type }}
-  | id < atyp1 , .. , atypn >                    :: :: app
-  {{ com type constructor application }}
-
-
-% plus more for l-value/r-value pairs, as introduced by the L3 'compound' declarations   ... ref typ
-
-%typ_lib :: 'Typ_lib_' ::=
-%  {{ com library types and syntactic sugar for them }}
-%  {{ aux _ l }} %{{ auxparam 'a }}
-% boring base types:
-%  | unit :: :: unit {{ com unit type with value $()$ }}
-%  | bool :: :: bool {{ com booleans $[[true]]$ and $[[false]]$ }}
-%  | bit :: :: bit  {{ com pure bit values (not mutable bits) }}
-% experimentally trying with two distinct types of bool and bit ...
-%  | nat :: :: nat {{ com natural numbers 0,1,2,... }}
-%  | string :: :: string {{ com UTF8 strings }}
-% finite subranges of nat
-%  | enum nexp1 nexp2 order :: :: enum  {{ com natural numbers [[atyp2]] .. [[atyp2]]+[[atyp1]]-1, ordered by order }}
-%  | [ nexp ]             :: :: enum1 {{ com sugar for \texttt{enum nexp 0 inc} }}
-%  | [ nexp : nexp' ]  :: :: enum2 {{ com sugar for \texttt{enum (nexp'-nexp+1) nexp inc} or \texttt{enum (nexp-nexp'+1) nexp' dec} }}
-% use .. not - to avoid ambiguity with nexp -
-% total maps and vectors indexed by finite subranges of nat
-%  | vector nexp1 nexp2 order atyp :: :: vector {{ com vector of [[atyp]], indexed by natural range }}
-% probably some sugar for vector types, using [ ] similarly to enums:
-% (but with .. not : in the former, to avoid confusion...)
-%  | atyp [ nexp ]  :: :: vector2 {{ com sugar for vector indexed by [ [[atyp]] ] }}
-%  | atyp [ nexp : nexp' ] :: :: vector3 {{ com sugar for vector indexed by [ [[atyp]]..[[atyp']] ] }}
-% ...so bit [ nexp ] etc is just an instance of that
-%  | list atyp :: :: list {{ com list of [[atyp]] }}
-%  | set atyp  :: :: set  {{ com finite set of [[atyp]] }}
-%  | reg atyp  :: :: reg  {{ com mutable register components holding [[atyp]] }}
-% "reg t" is basically the ML "t ref" 
-% not sure how first-class it should be, though
-% use "reg word32" etc for the types of vanilla registers 
-
-parsing
-
-ATyp_tup <= ATyp_tup
-ATyp_fn right ATyp_fn
-ATyp_fn <= ATyp_tup
-
-grammar
-
-n_constraint :: 'NC_' ::=
-  {{ com constraint over kind $[[Nat]]$ }}
-  {{ aux _ l }}
-  | atyp = atyp'                                :: :: fixed
-  | atyp >= atyp'                               :: :: bounded_ge
-  | atyp '<=' atyp'                             :: :: bounded_le
-  | kid 'IN' { num1 , ... , numn }               :: :: nat_set_bounded
-
-% Note only id on the left and constants on the right in a
-% finite-set-bound, as we don't think we need anything more
-
-kinded_id :: 'KOpt_' ::=
-  {{ com optionally kind-annotated identifier }}
-  {{ aux _ l }}
-  | kid	 	    		   	      :: :: none {{ com identifier }}
-  | kind kid				      :: :: kind {{ com kind-annotated variable }}
-
-quant_item :: 'QI_' ::=
-  {{ com Either a kinded identifier or a nexp constraint for a typquant }}
-  {{ aux _ l }}
-  | kinded_id 	  	 	       	      :: :: id {{ com An optionally kinded identifier }}
-  | n_constraint			      :: :: const {{ com A constraint for this type }}
-
-typquant :: 'TypQ_' ::= 
-  {{ com type quantifiers and constraints}}
-  {{ aux _ l }}
-  | forall quant_item1 , ... , quant_itemn . :: :: tq {{ texlong }}
-  |                           ::  ::  no_forall     {{ com sugar, omitting quantifier and constraints }}
-
-typschm :: 'TypSchm_' ::=
-  {{ com type scheme  }}
-  {{ aux _ l }}
-  |  typquant atyp                                                       :: :: ts
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Type definitions                                             %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-grammar
-%ctor_def :: 'CT_' ::=
-%  {{ com Datatype constructor definition clause }}
-%  {{ aux _ l }}
-%  | id : typschm                                       :: :: ct
-% but we could get away with disallowing constraints in typschm, we
-% think - if it's useful to do that
-
- name_scm_opt :: 'Name_sect_' ::=
-   {{ com Optional variable-naming-scheme specification for variables of defined type }} 
-   {{ aux _ l }}
-   |                                                   :: :: none
-   | [ name = regexp ]                                 :: :: some
-
-type_union :: 'Tu_' ::=
-  {{ com Type union constructors }}
-  {{ aux _ l }}
-  | id                                                  :: :: id
-  | atyp id                                             :: :: ty_id
-
-type_def :: 'TD_' ::=
-  {{ com Type definition body }}
-  {{ aux _ l }}
-  | typedef id name_scm_opt = typschm                                        :: :: abbrev
-    {{ com type abbreviation }} {{ texlong }}
-  | typedef id name_scm_opt = const struct typquant { atyp1 id1 ; ... ; atypn idn semi_opt }     :: :: record
-    {{ com struct type definition }} {{ texlong }}
-  | typedef id name_scm_opt = const union typquant { type_union1 ; ... ; type_unionn semi_opt }   :: :: variant
-    {{ com union type definition}} {{ texlong }}
-  | typedef id name_scm_opt = enumerate { id1 ; ... ; idn semi_opt }   :: :: enum
-    {{ com enumeration type definition}} {{ texlong }}
-
-  | typedef id = register bits [ atyp : atyp' ] { index_range1 : id1 ; ... ; index_rangen : idn } 
-:: :: register {{ com register mutable bitfield type definition }} {{ texlong }}
-
-kind_def :: 'KD_' ::=
-  {{ com Definition body for elements of kind; many are shorthands for type\_defs }}
-  {{ aux _ l }}
-  | Def kind id name_scm_opt = typschm                                        :: :: abbrev
-    {{ com type abbreviation }} {{ texlong }}
-  | Def kind id name_scm_opt = const struct typquant { atyp1 id1 ; ... ; atypn idn semi_opt }     :: :: record
-    {{ com struct type definition }} {{ texlong }}
-  | Def kind id name_scm_opt = const union typquant { type_union1 ; ... ; type_unionn semi_opt }   :: :: variant
-    {{ com union type definition}} {{ texlong }}
-  | Def kind id name_scm_opt = enumerate { id1 ; ... ; idn semi_opt }   :: :: enum
-    {{ com enumeration type definition}} {{ texlong }}
-
-  | Def kind id = register bits [ atyp : atyp' ] { index_range1 : id1 ; ... ; index_rangen : idn } 
-:: :: register {{ com register mutable bitfield type definition }} {{ texlong }}
-
-
-% also sugar [  nexp ] 
-
-
-index_range :: 'BF_' ::= {{ com index specification, for bitfields in register types}} 
-  {{ aux _ l }}
-  | num :: :: 'single'  {{ com single index }}
-  | num1 : num2 :: :: range {{ com index range }}
-  | index_range1 , index_range2 :: :: concat {{ com concatenation of index ranges }}
-
-% 
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Literals                                                     %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-grammar
-
-lit :: 'L_' ::=
-  {{ com Literal constant }}
-  {{ aux _ l }}
-  | ( )                                                 :: :: unit  {{ com $() : [[unit]]$ }}
-%Presumably we want to remove bitzero and bitone ?
-  | bitzero                                             :: :: zero {{ com $[[bitzero]] : [[bit]]$ }}
-  | bitone                                              :: :: one {{ com $[[bitone]] : [[bit]]$ }}
-  | true                                                :: :: true  {{ com $[[true]] : [[bool]]$ }}
-  | false                                               :: :: false {{ com $[[false]] : [[bool]]$ }}
-  | num                                         :: :: num  {{ com natural number constant }}
-  | hex                                         :: :: hex  {{ com bit vector constant, C-style }}
-  {{ com hex and bin are constant bit vectors, C-style }}
-  | bin                                         :: :: bin  {{ com bit vector constant, C-style }}
-  | undefined					:: :: undef {{ com undefined value }}
-  | string                                              :: :: string {{ com string constant }}
-
-semi_opt {{ tex \ottnt{;}^{?} }} :: 'semi_' ::=         {{ phantom }}
-                                                        {{ ocaml bool }}
-                                                        {{ lem bool }}
-                                                        {{ hol bool }}
-  {{ com Optional semi-colon }}
-  |                                                     :: :: no  
-    {{ hol F }}
-    {{ ocaml false }}
-    {{ lem false }}
-  | ';'                                                 :: :: yes
-    {{ hol T }}
-    {{ ocaml true }}
-    {{ lem true }}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Patterns                                                     %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-pat :: 'P_' ::= 
-  {{ com Pattern }}
-  {{ aux _ l }}
-  | lit                                                 :: :: lit
-    {{ com literal constant pattern }}
-  | _                                                   :: :: wild  
-    {{ com wildcard }}
-  | ( pat as id )                                      :: :: as
-    {{ com named pattern }}
-  | ( atyp ) pat                                       :: :: typ
-    {{ com typed pattern }}
-
-  | id                                      :: :: id
-    {{ com identifier  }}
-
-  | id ( pat1 , .. , patn )                                     :: :: app
-    {{ com union constructor pattern }}
-
-  | { fpat1 ; ... ; fpatn semi_opt }                  :: :: record
-    {{ com struct pattern }}
-
-  | [ pat1 , .. , patn  ]                     :: :: vector
-   {{ com vector pattern }}
-
-  | [ num1 = pat1 , .. , numn = patn  ]                     :: :: vector_indexed
-   {{ com vector pattern (with explicit indices) }}
-
-  |  pat1 : .... : patn                                   :: :: vector_concat
-  {{ com concatenated vector pattern }} 
-
-  | ( pat1 , .... , patn )                              :: :: tup
-    {{ com tuple pattern }}
-  | [|| pat1 , .. , patn ||]	                        :: :: list
-    {{ com list pattern }}
-  | ( pat )                                             :: S :: paren
-{{ ichlo [[pat]] }}
-
-fpat :: 'FP_' ::=
-  {{ com Field pattern }}
-  {{ aux _ l }}
-  | id = pat                                            :: :: Fpat
-
-parsing
-P_app <= P_app
-P_app <= P_as
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Expressions                                                  %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-
-grammar
-
-exp :: 'E_' ::=
-  {{ com Expression }}
-  {{ aux _ l }}
-
-  | { exp1 ; ... ; expn }                               :: :: block {{ com block (parsing conflict with structs?) }}
-% maybe we really should have indentation-sensitive syntax :-)  (given that some of the targets do)
-
-  | nondet { exp1 ; ... ; expn }                        :: :: nondet {{ com block that can evaluate the contained expressions in any ordering }}
-
-  | id                                                  :: :: id
-    {{ com identifier }}
-
-  | lit                                                 :: :: lit
-    {{ com literal constant }}
-
-  | ( atyp ) exp                                         :: :: cast
-    {{ com cast }}
-
-
-  | id exp                                               :: S :: tup_app {{ ichlo [[id ( exp ) ]] }} {{ com No extra parens needed when exp is a tuple }}
-  | id ( exp1 , .. , expn )                                   :: :: app
-    {{ com function application }}
-% Note: fully applied function application only
-
-  | exp1 id exp2                                        :: :: app_infix
-    {{ com infix function application }}
- 
-  | ( exp1 , .... , expn )                              :: :: tuple
-    {{ com tuple }}
-
-  | if exp1 then exp2 else exp3                         :: :: if
-    {{ com conditional }}
-
-  | if exp1 then exp2                                   :: S :: ifnoelse {{ icho [[ if exp1 then exp2 else unit ]] }}
-
-  | foreach id from exp1 to exp2 by exp3 in atyp exp4   ::   :: for {{ com loop }}
-  | foreach id from exp1 to exp2 by exp3 exp4           :: S :: forup {{ ichlo [[ foreach id from exp1 to exp2 by exp3 in inc exp4 ]] }}
-  | foreach id from exp1 to exp2 exp3                   :: S :: forupbyone  {{ icho [[ foreach id from exp1 to exp2 by 1 exp4 ]] }}
-  | foreach id from exp1 downto exp2 by exp3 exp4       :: S :: fordown {{ icho [[ foreach id from exp1 to exp2 by ( - exp3 ) exp4 ]] }}
-  | foreach id from exp1 downto exp2 exp3               :: S :: fordownbyone  {{ icho [[ foreach id from exp1 downto exp2 by 1 exp4 ]] }}
-
-% vectors
-  | [ exp1 , ... , expn ]                             :: :: vector {{ com vector (indexed from 0) }}
-% order comes from global command-line option???
-% here the expi are of type 'a and the result is a vector of 'a, whereas in exp1 : ... : expn 
-% the expi and the result are both of type vector of 'a 
-
-  | [ exp1 , ... , expn opt_default ]               :: :: vector_indexed {{ com vector (indexed consecutively) }}
-% num1 .. numn must be a consecutive list of naturals
-
-% we pick [ ] not { } for vector literals for consistency with their
-% array-like access syntax, in contrast to the C which has funny
-% syntax for array literals.  We don't have to preserve [ ] for lists
-% as we don't expect to use lists very much. 
-
-  | exp [ exp' ]                                      :: :: vector_access
-  {{ com vector access }}
-
-  | exp [ exp1 '..' exp2 ]                               :: :: vector_subrange
-  {{ com subvector extraction }}
-  % do we want to allow a comma-separated list of such thingies?  
-
-  | [ exp with exp1 = exp2 ]                          :: :: vector_update 
-  {{ com vector functional update }}
-
-  | [ exp with exp1 : exp2 = exp3 ]                   :: :: vector_update_subrange
-  {{ com vector subrange update (with vector)}}
-  % do we want a functional update form with a comma-separated list of such?
-
-  | exp : exp2                                        :: :: vector_append
-  {{ com vector concatenation }}
-
-% lists 
-  | [|| exp1 , ..  , expn ||]                           :: :: list
-  {{ com list }}
-  | exp1 '::' exp2                                    :: :: cons
-    {{ com cons }}
-
-
-% const unions
-
-% const structs
-
-% TODO
-
-  | { fexps }                                         :: :: record
-    {{ com struct }}
-  | { exp with exp1 ; .. ; expn }                                :: :: record_update
-    {{ com functional update of struct }}
-  | exp . id                                          :: :: field
-    {{ com field projection from struct  }}
-
-%Expressions for creating and accessing vectors
-
-
-
-%  map : forall 'x 'y ''N.  ('x -> 'y) -> vector ''N 'x -> vector ''N 'y
-%  zip : forall 'x 'y ''N.  vector ''N 'x  -> vector ''N 'y -> vector ''N ('x*'y) 
-%  foldl : forall 'x 'y ''N. ('x 'y -> 'y) -> vector ''N 'x -> 'y -> 'y
-% foldr : forall 'x 'y ''N. ('x 'y -> 'y) -> 'y -> vector ''N 'x -> 'y
-% foldmap : forall 'x 'y 'z ''N. ((x,y) -> (x,z)) -> x -> vector ''N y -> vector ''N z
-%(or unzip)
-
-%  and maybe with nice syntax
-
-  | switch exp { case pexp1  ... case pexpn } :: :: case
-    {{ com pattern matching }}
-  | letbind in exp                                  :: :: let
-    {{ com let expression }}
-
-  | exp := exp'                                      :: :: assign
-    {{ com imperative assignment }}
-
-  | sizeof atyp                                         :: :: sizeof
-  | exit exp						:: :: exit
-  | return exp                                          :: :: return
-  | assert ( exp , exp' )                               :: :: assert
-
-  | ( exp )                                             :: S :: paren {{ ichlo [[exp]] }}
-
-
-lexp :: 'LEXP_' ::= {{ com lvalue expression, can't occur out of the parser }}
-    {{ aux _ l }}
-%    {{ aux _ annot }} {{ auxparam 'a }}
-    | id                                                  :: :: id
-    {{ com identifier }}
-    | id ( exp1 , .. , expn )				  :: :: mem
-    | id exp	       	    				  :: S :: mem_tup {{ ichlo [[id (exp)]] }}
-    | lexp [ exp ]  :: ::                         vector  {{ com vector element }}
-    | lexp [ exp1 : exp2 ]  :: ::              vector_range {{ com subvector }}
-    % maybe comma-sep such lists too
-    | lexp . id :: :: field                        {{ com struct field }}
-
-
-fexp :: 'FE_' ::=
-  {{ com Field-expression }}
-  {{ aux _ l }} 
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | id = exp                                            :: :: Fexp
-
-fexps :: 'FES_' ::=
-  {{ com Field-expression list }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | fexp1 ; ... ; fexpn semi_opt                        :: :: Fexps
-
-opt_default :: 'Def_val_' ::=
-  {{ com Optional default value for indexed vectors, to define a defualt value for any unspecified positions in a sparse map }}
-  {{ aux _ l }} 
-  |                                                     :: :: empty
-  | ; default = exp                                       :: :: dec
-
-pexp :: 'Pat_' ::=
-  {{ com Pattern match }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | pat -> exp                                  :: :: exp
-% apparently could use -> or => for this.
-
-%% % psexp :: 'Pats' ::=
-%% %   {{ com Multi-pattern matches }}
-%% %   {{ aux _ l }}
-%% %   | pat1 ... patn -> exp                                :: :: exp
-
-
-parsing
-
-%P_app right LB_Let_val
-
-%%P_app <= Fun
-
-%%Fun right App
-%%Function right App
-E_case right E_app
-E_let right E_app
-
-%%Fun <= Field
-%%Function <= Field
-E_app <= E_field
-E_case <= E_field
-E_let <= E_field
-
-E_app left E_app
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Function definitions                                         %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-%%%% old Lem style %%%%%%
-grammar
-%% % lem_tannot_opt_aux :: 'LEM_Typ_annot_' ::=
-%% %   {{ com Optional type annotations }}
-%% %   |                                                     :: :: none
-%% %   | : typ                                               :: :: some 
-%% % 
-%% % lem_tannot_opt {{ tex \ottnt{tannot}^? }} :: 'LEM_Typ_annot_' ::=
-%% %   {{ com location-annotated optional type annotations }}
-%% %   | tannot_opt_aux l                                    :: :: aux
-%% % 
-%% % lem_funcl :: 'LEM_FCL' ::=
-%% %   {{ com Function clauses }}
-%% %   {{ aux _ l }}
-%% %   | id pat1 ... patn tannot_opt = exp                   :: :: Funcl
-%% % 
-%% % lem_letbind :: 'LEM_LB_' ::=
-%% %   {{ com Let bindings }}
-%% %   {{ aux _ l }}
-%% %   | pat tannot_opt = exp                                :: :: Let_val
-%% %     {{ com Value bindings }}
-%% %   | lem_funcl                                           :: :: Let_fun
-%% %     {{ com Function bindings }}
-%% % 
-%% % 
-%% % grammar
-%% % lem_val_def :: 'LEM_VD' ::= 
-%% %   {{ com Value definitions }}
-%% %   {{ aux _ l }}
-%% %   | let lem_letbind                                     :: :: Let_def
-%% %     {{ com Non-recursive value definitions }}
-%% %   | let rec  lem_funcl1 and ... and lem_funcln          :: :: Let_rec
-%% %     {{ com Recursive function definitions }}
-%% % 
-%% % lem_val_spec :: 'LEM_VS' ::=
-%% %   {{ com Value type specifications }} 
-%% %   {{ aux _ l }}
-%% %   | val x_l : typschm                                           :: :: Val_spec
-
-%%%%% C-ish style %%%%%%%%%%
-
-tannot_opt :: 'Typ_annot_opt_' ::=
-  {{ com Optional type annotation for functions}}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  |                                             :: :: none
-  | typquant atyp                               :: :: some 
-
-rec_opt :: 'Rec_' ::=
-  {{ com Optional recursive annotation for functions }}
-  {{ aux _ l }}
-  |                                             :: :: nonrec {{ com non-recursive }}
-  | rec                                         :: :: rec {{ com recursive }}
-
-effect_opt :: 'Effect_opt_' ::=
-  {{ com Optional effect annotation for functions }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  |                                             :: :: pure {{ com sugar for empty effect set }}
-  | effectkw atyp                                     :: :: effect
-
-funcl :: 'FCL_' ::=
-  {{ com Function clause }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | id pat = exp                   :: :: Funcl
-
-
-fundef :: 'FD_' ::=
-  {{ com Function definition}}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | function rec_opt tannot_opt effect_opt funcl1 and ... and funcln :: :: function {{ texlong }}  
-% {{ com function definition }}
-% TODO note that the typ in the tannot_opt is the *result* type, not
-%  the type of the whole function.  The argument type comes from the
-%  pattern in the funcl
-% TODO the above is ok for single functions, but not for mutually
-%  recursive functions - the tannot_opt scopes over all the funcli,
-%  which is ok for the typ_quant part but not for the typ part
-
-letbind :: 'LB_' ::=
-  {{ com Let binding }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | let typschm pat = exp                                :: :: val_explicit
-    {{ com value binding, explicit type ([[pat]] must be total)}}
-  | let pat = exp                                    :: :: val_implicit
-    {{ com value binding, implicit type ([[pat]] must be total)}}
-
-
-val_spec :: 'VS_' ::=
-  {{ com Value type specification }} 
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | val typschm id                                  :: :: val_spec
-  | val extern typschm id                           :: :: extern_no_rename
-  | val extern typschm id = string                  :: :: extern_spec
-
-default_typing_spec :: 'DT_' ::=
-  {{ com Default kinding or typing assumption, and default order for literal vectors and vector shorthands }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | default base_kind kid    :: :: kind
-  | default base_kind atyp   :: :: order
-  | default typschm id      :: :: typ
-% The intended semantics of these is that if an id in binding position
-% doesn't have a kind or type annotation, then we look through the
-% default regexps (in order from the beginning) and pick the first
-% assumption for which id matches the regexp, if there is one.
-% Otherwise we try to infer.  Perhaps warn if there are multiple matches.
-% For example, we might often have default Type ['alphanum]
-
-scattered_def :: 'SD_' ::=
-  {{ com Function and type union definitions that can be spread across
-         a file. Each one must end in $[[end id]]$ }}
-  {{ aux _ l }} 
-  | scattered function rec_opt tannot_opt effect_opt id   :: :: scattered_function {{ texlong }} {{ com scattered function definition header }}
-
-  | function clause funcl  :: :: scattered_funcl  
-{{ com scattered function definition clause }}
-
-  | scattered typedef id name_scm_opt = const union typquant :: :: scattered_variant {{ texlong }} {{ com scattered union definition header }}
-
-  | union id member type_union  :: :: scattered_unioncl {{ com scattered union definition member }}
-  | end id  :: :: scattered_end
-{{ com scattered definition end }}
-
-dec_spec :: 'DEC_' ::=
-  {{ com Register declarations }}
-  {{ aux _ l }}
-  | register atyp id                                             :: :: reg
-  | register alias id = exp	      	 			 :: :: alias
-  | register alias atyp id = exp	  			 :: :: typ_alias
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Top-level definitions                                        %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-def :: 'DEF_' ::=
-  {{ com Top-level definition }}
-  | kind_def                                                    :: :: kind
-    {{ com definition of named kind identifiers }}
-  | type_def                                                    :: :: type
-    {{ com type definition }}
-  | fundef                                                   :: :: fundef
-    {{ com function definition }}
-  | letbind                                                   :: :: val
-    {{ com value definition }}
-  | val_spec                                                    :: :: spec
-    {{ com top-level type constraint }}
-  | default_typing_spec                                         :: :: default
-    {{ com default kind and type assumptions }}
-  | scattered_def					:: :: scattered
-    {{ com scattered definition }} 
-  | dec_spec                                            :: :: reg_dec
-    {{ com register declaration }}
-
-defs :: '' ::=
-  {{ com Definition sequence }}
-  | def1  .. defn                 :: :: Defs
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Machinery for typing rules                                   %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-%% %% 
-%% %% 
-%% %% grammar
-%% %% 
-%% %% 
-%% %% p :: 'Path_' ::=
-%% %%   {{ com Unique paths }}
-%% %%   | x1 . .. xn . x                              :: :: def
-%% %%   | __list                                      :: :: list      
-%% %%     {{ tex \ottkw{\_\_list}  }}
-%% %%   | __bool                                      :: :: bool
-%% %%     {{ tex \ottkw{\_\_bool}  }}
-%% %%   | __num                                       :: :: num
-%% %%     {{ tex \ottkw{\_\_num}  }}
-%% %%   | __set                                       :: :: set
-%% %%     {{ tex \ottkw{\_\_set}  }}
-%% %%   | __string                                    :: :: string
-%% %%     {{ tex \ottkw{\_\_string}  }}
-%% %%   | __unit                                      :: :: unit
-%% %%     {{ tex \ottkw{\_\_unit}  }}
-%% %%   | __bit                                       :: :: bit
-%% %%     {{ tex \ottkw{\_\_bit}  }}
-%% %%   | __vector                            :: :: vector
-%% %%     {{ tex \ottkw{\_\_vector} }}                
-%% %% %TODO morally, delete the above - but what are the __ things for?
-%% %% % cleaner to declare early in the library?
-%% %% 
-%% %% t_subst {{ tex \ensuremath{\sigma} }} :: '' ::= {{ phantom }}
-%% %%                                                 {{ hol (a # t) list }}
-%% %%                                                 {{ lem list (tnvar * t) }}
-%% %%   {{ com Type variable substitutions }}
-%% %%   | { tnvar1 |-> t1 .. tnvarn |-> tn }                  :: :: T_subst
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ lem ([[tnvar1 t1 .. tnvarn tn]]) }}
-%% %%     {{ hol ([[tnvar1 t1 .. tnvarn tn]]) }}
-%% %% 
-%% %% t , u :: 'T_' ::=
-%% %%   {{ com Internal types }}
-%% %%   | a                                           :: :: var
-%% %%   | t1 -> t2                                    :: :: fn
-%% %%   | t1 * .... * tn                              :: :: tup
-%% %%   | p t_args                                    :: :: app 
-%% %%   | ne                                          :: :: len
-%% %%   | t_subst ( t )                               :: M :: subst_app
-%% %%     {{ com Multiple substitutions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (t_subst_t [[t_subst]] [[t]]) }}
-%% %%     {{ lem (t_subst_t [[t_subst]] [[t]]) }}
-%% %%   | t_subst ( tnv )                     :: M :: var_subst_app
-%% %%     {{ com Single variable substitution }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (t_subst_tnv [[t_subst]] [[tnv]]) }}
-%% %%     {{ lem (t_subst_tnv [[t_subst]] [[tnv]]) }}
-%% %%   | curry ( t_multi ,  t )                      :: M :: multifn
-%% %%     {{ com Curried, multiple argument functions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (FOLDR T_fn [[t]] [[t_multi]]) }}
-%% %%     {{ lem (List.fold_right T_fn [[t_multi]] [[t]]) }}
-%% %% 
-%% %% ne :: 'Ne_' ::=
-%% %%   {{ com internal numeric expressions }}
-%% %%   | N                                           :: :: var
-%% %%   | nat                                 :: :: const
-%% %%   | ne1 * ne2                           :: :: mult
-%% %%   | ne1 + ne2                           :: :: add
-%% %%   | ( - ne )                            :: :: unary
-%% %%   | normalize ( ne )                    :: M :: normalize
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (normalize [[ne]] ) }}
-%% %%   | ne1 + ... + nen                     :: M :: addmany
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (sumation_nes [[ne1...nen]]) }}
-%% %%   | bitlength ( bin )                   :: M :: cbin
-%% %%     {{ ocaml (asssert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (blength [[bin]]) }}
-%% %%   | bitlength ( hex )                   :: M :: chex
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (hlength [[hex]]) }}
-%% %%   | length ( pat1 ... patn )            :: M :: cpat
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (Ne_const (List.length [[pat1...patn]])) }}
-%% %%   | length ( exp1 ... expn )            :: M :: cexp
-%% %%     {{ hol ARB }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ lem (Ne_const (List.length [[exp1...expn]])) }}
-%% %% 
-%% %% t_args :: '' ::=
-%% %%   {{ com Lists of types }}
-%% %%   | t1 .. tn                            :: :: T_args
-%% %%   | t_subst ( t_args )                          :: M :: T_args_subst_app
-%% %%     {{ com Multiple substitutions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (t_subst_t_args [[t_subst]] [[t_args]]) }}
-%% %%     {{ lem (t_subst_t_args [[t_subst]] [[t_args]]) }}
-%% %% 
-%% %% t_multi :: '' ::=                               {{ phantom }}
-%% %%                                                 {{ hol t list }}
-%% %%                                                 {{ ocaml t list }}
-%% %%                                                 {{ lem list t }}
-%% %%   {{ com Lists of types }}
-%% %%   | ( t1 * .. * tn )                            :: :: T_multi
-%% %%     {{ hol [[t1..tn]] }}
-%% %%     {{ lem [[t1..tn]] }}
-%% %%   | t_subst ( t_multi )                         :: M :: T_multi_subst_app
-%% %%     {{ com Multiple substitutions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (MAP (t_subst_t [[t_subst]]) [[t_multi]]) }}
-%% %%     {{ lem (List.map (t_subst_t [[t_subst]]) [[t_multi]]) }}
-%% %% 
-%% %% nec :: '' ::=
-%% %%   {{ com Numeric expression constraints }}
-%% %%   | ne < nec            :: :: lessthan
-%% %%   | ne = nec            :: :: eq
-%% %%   | ne <= nec           :: :: lteq
-%% %%   | ne                          :: :: base
-%% %% 
-%% %% parsing
-%% %% T_fn right T_fn
-%% %% T_tup <= T_multi
-%% %% 
-%% %% embed
-%% %% {{ lem
-%% %% 
-%% %% val t_subst_t : list (tnv * t) -> t -> t 
-%% %% val t_subst_tnv : list (tnv * t) -> tnv -> t
-%% %% val ftv_t : t -> list tnv
-%% %% val ftv_tm : list t -> list tnv
-%% %% val ftv_s : list (p*tnv) -> list tnv
-%% %% val compatible_overlap : list (x*t) -> bool
-%% %% 
-%% %% (*TODO Should this normalize following the implementation? And blength and hlength need a means of implementation*)
-%% %% let normalize n = n
-%% %% 
-%% %% let blength (_,bit) = Ne_const 8
-%% %% let hlength (_,bit) = Ne_const 8
-%% %% 
-%% %% let rec sumation_nes nes = match nes with
-%% %%   | [ a; b] -> Ne_add a b 
-%% %%   | x :: y -> Ne_add x (sumation_nes y)
-%% %% end
-%% %% 
-%% %% }}
-%% %% 
-%% %% grammar
-%% %% 
-%% %% 
-%% %% names :: '' ::=                                 {{ phantom }}
-%% %%                                                 {{ hol x set }}
-%% %%                                                 {{ lem set x }}
-%% %%                                                 {{ ocaml Set.Make(String).t }}
-%% %%   {{ com Sets of names }}
-%% %%   | { x1 , .. , xn }                            :: :: Names
-%% %%     {{ hol (LIST_TO_SET [[x1..xn]]) }}
-%% %%     {{ lem (set_from_list [[x1..xn]]) }}
-%% %% 
-%% %% semC {{ tex \ensuremath{\mathcal{C} } }} :: '' ::=
-%% %%                                                                 {{ hol (p#tnv) list }}
-%% %%                                                                 {{ lem list (p*tnv)  }}
-%% %% %   {{ com Typeclass constraint lists }}
-%% %% %   | ( p1 tnv1 ) .. ( pn tnvn )                                        :: :: SemC_concrete
-%% %% %     {{ hol ([[p1 tnv1..pn tnvn]]) }}
-%% %% %     {{ lem ([[p1 tnv1..pn tnvn]]) }}
-%% %% 
-%% %% env_tag :: '' ::=
-%% %%   {{ com Tags for the (non-constructor) value descriptions }}
-%% %% %  | method                                                     :: :: method
-%% %% %    {{ com Bound to a method }}
-%% %%   | val                                                         :: :: spec
-%% %%     {{ com Specified with val }}
-%% %%   | let                                                         :: :: def
-%% %%     {{ com Defined with let or indreln }}
-%% %% 
-%% %% v_desc :: 'V_' ::=
-%% %%   {{ com Value descriptions }}
-%% %%   | < forall tnvs . t_multi -> p , ( x of names ) >             :: :: constr
-%% %%     {{ com Constructors }}
-%% %%   | < forall tnvs . semC => t , env_tag >                       :: :: val
-%% %%     {{ com Values }}
-%% %% 
-%% %% f_desc :: 'F_' ::=
-%% %%   | < forall tnvs . p -> t , ( x of names ) >                   :: :: field
-%% %%     {{ com Fields }}
-%% %% 
-%% %% embed
-%% %% {{ hol
-%% %% load "fmaptreeTheory";
-%% %% val _ = 
-%% %%   Hol_datatype 
-%% %%     `env_body = <| env_p : x|->p; env_f : x|->f_desc; env_v : x|->v_desc |>`;
-%% %% 
-%% %% val _ = Define `
-%% %%   env_union e1 e2 =
-%% %%     let i1 = item e1 in
-%% %%     let m1 = map e1 in
-%% %%     let i2 = item e2 in
-%% %%     let m2 = map e2 in
-%% %%       FTNode <| env_p:=FUNION i1.env_p i2.env_p; 
-%% %%                 env_f:=FUNION i1.env_f i2.env_f;
-%% %%                 env_v:=FUNION i1.env_v i2.env_v |>
-%% %%              (FUNION m1 m2)`;
-%% %% }}
-%% %% {{ lem
-%% %% type env =
-%% %%   | EnvEmp 
-%% %%   | Env of (map x env) * (map x p) * (map x f_desc) * (map x v_desc)
-%% %% 
-%% %% val env_union : env -> env -> env
-%% %% let env_union e1 e2 =
-%% %%   match (e1,e2) with
-%% %%    | (EnvEmp,e2) -> e2
-%% %%    | (e1,EnvEmp) -> e1
-%% %%    | ((Env Em1 Ep1 Ef1 Ev1),(Env Em2 Ep2 Ef2 Ev2)) ->
-%% %%      Env(union_map Em1 Em2) (union_map Ep1 Ep2) (union_map Ef1 Ef2) (union_map Ev1 Ev2)
-%% %% end
-%% %% 
-%% %% }}
-%% %% 
-%% %% grammar
-%% %% 
-%% %% xs :: '' ::=                                    {{ phantom }}
-%% %%                                                 {{ hol string list }}
-%% %%                                                 {{ lem list string }}
-%% %%   | x1 .. xn                                    :: :: Xs
-%% %%     {{ hol [[x1..xn]] }}
-%% %%     {{ lem [[x1..xn]] }}
-%% %% 
-%% %% %TODO: no clue what the following are:
-%% %% S_c {{ tex {\ensuremath{ {\Sigma}^{\mathcal{C} } } } }} :: '' ::=                       {{ phantom }}
-%% %%                                                                 {{ hol (p#t) list }}
-%% %%                                                                 {{ lem list (p*t) }}
-%% %%   {{ com Typeclass constraints }}
-%% %%   | { ( p1 t1 ) , .. , ( pn tn ) }                              :: :: S_concrete
-%% %%     {{ hol [[p1 t1 .. pn tn]] }}
-%% %%     {{ lem [[p1 t1 .. pn tn]] }}
-%% %%   | S_c1 union .. union S_cn                                    :: M :: S_union
-%% %%     {{ hol (FLAT [[S_c1..S_cn]]) }}
-%% %%     {{ lem (List.flatten [[S_c1..S_cn]]) }}
-%% %%     {{ ocaml assert false }}
-%% %% 
-%% %% S_N {{ tex { \ensuremath{ {\Sigma}^{\mathcal{N} } } } }} :: '' ::= {{ phantom }}
-%% %%                                                                    {{ hol nec list }}
-%% %%                                                                    {{ lem list nec }}
-%% %%    {{ com nexp constraint lists }}
-%% %%    | { nec1 , .. ,  necn }                              :: :: Sn_concrete
-%% %%      {{ hol [[nec1 .. necn]] }}
-%% %%      {{ lem [[nec1 .. necn]] }}
-%% %%    | S_N1 union .. union S_Nn                   :: M :: SN_union
-%% %%      {{ hol (FLAT [[S_N1..S_Nn]]) }}
-%% %%      {{ lem (List.flatten [[S_N1..S_Nn]]) }}
-%% %%      {{ ocaml assert false }}
-%% %% 
-%% %% 
-%% %% E :: '' ::=                                                     {{ phantom }}
-%% %%                                                                 {{ hol ((string,env_body) fmaptree) }}
-%% %% 
-%% %% 
-%% %% %TODO: simplify by removing E_m throughout?  And E_p??
-%% %%                                                                 {{ lem env }}
-%% %%   {{ com Environments }}
-%% %%   | < E_m , E_p , E_f , E_x >                                           :: :: E
-%% %%     {{ hol (FTNode <|env_p:=[[E_p]]; env_f:=[[E_f]]; env_v:=[[E_x]]|> ([[E_m]])) }}
-%% %%     {{ lem (Env [[E_m]] [[E_p]] [[E_f]] [[E_x]]) }}
-%% %%   | E1 u+ E2                                                    :: M :: E_union
-%% %%     {{ hol (env_union [[E1]] [[E2]]) }}
-%% %%     {{ lem (env_union [[E1]] [[E2]]) }}
-%% %%     {{ ocaml assert false }}
-%% %%   | empty                                                       :: M :: E_empty
-%% %%     {{ hol (FTNode <|env_p:=FEMPTY; env_f:=FEMPTY; env_v:=FEMPTY|> FEMPTY) }}
-%% %%     {{ lem EnvEmp }}
-%% %%     {{ ocaml assert false }}
-%% %% 
-%% %% E_x {{ tex \ottnt{E}^{\textsc{x} } }} :: 'E_x_' ::=             {{ phantom }}
-%% %%                                                                 {{ hol (x|-> v_desc) }}
-%% %%                                                                 {{ lem map x v_desc }}
-%% %%   {{ com Value environments }}
-%% %%   | { x1 |-> v_desc1 , .. , xn |-> v_descn }    :: :: concrete
-%% %%     {{ hol (FOLDR (\(k1,k2) E. E |+ (k1,k2)) FEMPTY [[x1 v_desc1 .. xn v_descn]]) }}
-%% %%     {{ lem (List.fold_right (fun (x,v) m -> Pmap.add x v m) [[x1 v_desc1 .. xn v_descn]] Pmap.empty) }} 
-%% %%   | E_x1 u+ .. u+ E_xn                                          :: M :: union
-%% %%     {{ hol (FOLDR FUNION FEMPTY [[E_x1..E_xn]]) }}
-%% %%     {{ lem (List.fold_right union_map [[E_x1..E_xn]] Pmap.empty) }}
-%% %%     {{ ocaml (assert false) }}
-%% %% 
-%% %% E_f {{ tex \ottnt{E}^{\textsc{f} } }} :: 'E_f_' ::=             {{ phantom }}
-%% %%                                                                 {{ hol (x |-> f_desc) }}
-%% %%                                                                 {{ lem map x f_desc }}
-%% %%   {{ com Field environments }}
-%% %%   | { x1 |-> f_desc1 , .. , xn |-> f_descn }                    :: :: concrete
-%% %%     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 f_desc1 .. xn f_descn]]) }}
-%% %%     {{ lem (List.fold_right (fun (x,f) m -> Pmap.add x f m) [[x1 f_desc1 .. xn f_descn]] Pmap.empty) }} 
-%% %%   | E_f1 u+ .. u+ E_fn                                          :: M :: union
-%% %%     {{ hol (FOLDR FUNION FEMPTY [[E_f1..E_fn]]) }}
-%% %%     {{ lem (List.fold_right union_map [[E_f1..E_fn]] Pmap.empty) }}
-%% %%     {{ ocaml (assert false) }}
-%% %% 
-%% %% E_m {{ tex \ottnt{E}^{\textsc{m} } }} :: 'E_m_' ::=             {{ phantom }}
-%% %%                                                                 {{ hol (string |-> (string,env_body) fmaptree) }}
-%% %%                                                                 {{ lem map x env }} 
-%% %% %  {{ com Module environments }}
-%% %% %  | { x1 |-> E1 , .. , xn |-> En }                             :: :: concrete
-%% %% %    {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 E1 .. xn En]]) }}
-%% %% %    {{ lem (List.fold_right (fun (x,e) m -> Pmap.add x e m) [[x1 E1 .. xn En]] Pmap.empty) }} 
-%% %% % 
-%% %% % _p {{ tex \ottnt{E}^{\textsc{p} } }} :: 'E_p_' ::=            {{ phantom }}
-%% %% %                                                               {{ hol (x |-> p) }}
-%% %% %                                                               {{ lem map x p }}
-%% %% %  {{ com Path environments }}
-%% %% %  | { x1 |-> p1 , .. , xn |-> pn }                             :: :: concrete
-%% %% %    {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 p1 .. xn pn]]) }}
-%% %% %    {{ lem (List.fold_right (fun (x,p) m -> Pmap.add x p m) [[x1 p1 .. xn pn]] Pmap.empty) }} 
-%% %% %  | E_p1 u+ .. u+ E_pn                                         :: M :: union
-%% %% %    {{ hol (FOLDR FUNION FEMPTY [[E_p1..E_pn]]) }}
-%% %% %    {{ lem (List.fold_right union_map [[E_p1..E_pn]] Pmap.empty) }}
-%% %% % 
-%% %% %    {{ ocaml (assert false) }}
-%% %%  E_l {{ tex \ottnt{E}^{\textsc{l} } }} :: 'E_l_' ::=            {{ phantom }}
-%% %%                                                                 {{ hol (x |-> t) }}
-%% %%                                                                 {{ lem map x t }}
-%% %%   {{ com Lexical bindings }}
-%% %%   | { x1 |-> t1 , .. , xn |-> tn }                              :: :: concrete
-%% %%     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 t1 .. xn tn]]) }}
-%% %%     {{ lem (List.fold_right (fun (x,t) m -> Pmap.add x t m) [[x1 t1 .. xn tn]] Pmap.empty) }} 
-%% %%   | E_l1 u+ .. u+ E_ln                                          :: M :: union
-%% %%     {{ hol (FOLDR FUNION FEMPTY [[E_l1..E_ln]]) }}
-%% %%     {{ lem (List.fold_right union_map [[E_l1..E_ln]] Pmap.empty) }}
-%% %%    {{ ocaml (assert false) }}
-%% %% 
-%% %% tc_abbrev :: 'Tc_abbrev_' ::=                                   {{ phantom }}
-%% %%                                                                 {{ hol t option }}
-%% %%                                                                 {{ lem option t }}
-%% %%                                                                 {{ ocaml t option }}
-%% %%   {{ com Type abbreviations }}
-%% %%   | . t                                                         :: :: some
-%% %%     {{ hol (SOME [[t]]) }}
-%% %%     {{ lem (Some [[t]]) }}
-%% %%   |                                                             :: :: none
-%% %%     {{ hol NONE }}
-%% %%     {{ lem None }}
-%% %% 
-%% %% tc_def :: '' ::=
-%% %%   {{ com Type and class constructor definitions }} 
-%% %%   | tnvs tc_abbrev                                              :: :: Tc_def
-%% %%     {{ com Type constructors }}
-%% %% 
-%% %% TD {{ tex \ensuremath{\Delta} }} :: 'TD_' ::=                   {{ phantom }}
-%% %%                                                                 {{ hol p |-> tc_def }}
-%% %%                                                                 {{ lem map p tc_def }}
-%% %%   {{ com Type constructor definitions }}
-%% %%   | { p1 |-> tc_def1 , .. , pn |-> tc_defn }                    :: :: concrete
-%% %%     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[p1 tc_def1 .. pn tc_defn]]) }}
-%% %%     {{ lem (List.fold_right (fun (p,t) m -> Pmap.add p t m) [[p1 tc_def1 .. pn tc_defn]] Pmap.empty) }} 
-%% %%     {{ ocaml (assert false) }}
-%% %%   | TD1 u+ TD2                                                  :: M :: union
-%% %%     {{ hol (FUNION [[TD1]] [[TD2]]) }}
-%% %%     {{ lem (union_map [[TD1]] [[TD2]]) }}
-%% %%     {{ ocaml (assert false) }}
-%% %% 
-%% %% 
-%% %% 
-%% %% D :: 'D_' ::=                                                   {{ phantom }}
-%% %%                                                                 {{ hol ((p |-> tc_def) # (p |-> x list) # (inst list)) }}
-%% %%                                                                 {{ lem tdefs}}
-%% %%   {{ com Global type definition store }}
-%% %%   | < TD , TC , I >                                                     :: :: concrete
-%% %%     {{ hol ([[TD]], [[TC]], [[I]]) }}
-%% %%     {{ lem (D [[TD]] [[TC]] [[I]]) }}
-%% %%   | D1 u+ D2                                                    :: M :: union
-%% %%     {{ hol (case ([[D1]],[[D2]]) of ((x1,x2,x3),(y1,y2,y3)) => (FUNION x1 y1, FUNION x2 y2, x3 ++ y3)) }}
-%% %%     {{ lem (union_tcdefs [[D1]] [[D2]]) }}
-%% %%     {{ ocaml (assert false) }}
-%% %%   | empty                                                       :: M :: empty
-%% %%     {{ hol (FEMPTY, FEMPTY, []) }}
-%% %%     {{ lem DEmp }}
-%% %%     {{ ocaml assert false }}
-%% %% 
-%% %% parsing
-%% %% E_union left E_union
-%% %% 
-%% %% embed
-%% %% {{ lem
-%% %% type tdefs =
-%% %%   | DEmp
-%% %%   | D of (map p tc_def) * (map p (list x)) * (set inst)
-%% %% 
-%% %% val union_tcdefs : tdefs -> tdefs -> tdefs
-%% %% 
-%% %% }}
-
-grammar
-
-terminals :: '' ::=
-  | **                                  :: :: starstar
-    {{ tex \ensuremath{\mathop{\mathord{*}\mathord{*} } } }}
-    {{ com \texttt{**} }}
-  | >=                                  :: :: geq
-    {{ tex \ensuremath{\geq} }}
-    {{ com \texttt{>=} }}
-  | '<='                                        :: :: leq
-    {{ tex \ensuremath{\leq} }}
-    {{ com \texttt{<=} }}
-  | ->                                  :: :: arrow
-    {{ tex \ensuremath{\rightarrow} }}
-    {{ com \texttt{->} }}
-  | ==>                                 :: :: Longrightarrow
-    {{ tex \ensuremath{\Longrightarrow} }}
-    {{ com \texttt{==>} }}
-  | <|                                  :: :: startrec
-    {{ tex \ensuremath{\langle|} }}
-    {{ com \texttt{<|} }}
-  | |>                                  :: :: endrec
-    {{ tex \ensuremath{|\rangle} }}
-    {{ com \texttt{|>} }}
-  | inter                               :: :: inter
-    {{ tex \ensuremath{\cap} }}
-%  | union                               :: :: union
-%    {{ tex \ensuremath{\cup} }}
-  | u+                                  :: :: uplus
-    {{ tex \ensuremath{\uplus} }}
-  | NOTIN                               :: :: notin
-    {{ tex \ensuremath{\not\in} }}
-  | SUBSET                              :: :: subset
-    {{ tex \ensuremath{\subset} }}
-  | NOTEQ                               :: :: noteq
-    {{ tex \ensuremath{\not=} }}
-  | emptyset                            :: :: emptyset
-    {{ tex \ensuremath{\emptyset} }}
-  | <                                   :: :: lt
-    {{ tex \ensuremath{\langle} }}
-  | >                                   :: :: gt
-    {{ tex \ensuremath{\rangle} }}
-  | |-                                  :: :: vdash
-    {{ tex \ensuremath{\vdash} }}
-  | '                                   :: :: quote
-    {{ tex \mbox{'} }}
-  | |->                                 :: :: mapsto
-    {{ tex \ensuremath{\mapsto} }}
-  | gives                               :: :: gives
-    {{ tex \ensuremath{\triangleright} }}
-  | ~>                                  :: :: leadsto
-    {{ tex \ensuremath{\leadsto} }}
-  | =>                                  :: :: Rightarrow
-    {{ tex \ensuremath{\Rightarrow} }}
-  | --                                  :: :: dashdash
-    {{ tex \mbox{--} }}
-  | empty                               :: :: empty
-    {{ tex \ensuremath{\epsilon} }}
-  | effectkw			        :: :: effectkw
-    {{ tex \ottkw{effect} }}
- 
-
-formula :: formula_ ::=
-  | judgement                                                   :: :: judgement
-
-  | formula1 .. formulan                                        :: :: dots
-
-%   | E_m ( x ) gives E                                         :: :: lookup_m
-%     {{ com Module lookup }}
-%     {{ hol (FLOOKUP [[E_m]] [[x]] = SOME [[E]]) }}
-%     {{ lem (Pmap.find [[x]] [[E_m]]) = [[E]] }} 
-% 
-%   | E_p ( x ) gives p                                         :: :: lookup_p
-%     {{ com Path lookup }}
-%     {{ hol (FLOOKUP [[E_p]] [[x]] = SOME [[p]]) }}
-%     {{ lem Pmap.find [[x]] [[E_p]] = [[p]] }} 
-
-%% %%   | E_f ( x ) gives f_desc                                      :: :: lookup_f
-%% %%     {{ com Field lookup }}
-%% %%     {{ hol (FLOOKUP [[E_f]] [[x]] = SOME [[f_desc]]) }}
-%% %%     {{ lem Pmap.find [[x]] [[E_f]] = [[f_desc]] }} 
-%% %% 
-%% %%   | E_x ( x ) gives v_desc                                      :: :: lookup_v
-%% %%     {{ com Value lookup }}
-%% %%     {{ hol (FLOOKUP [[E_x]] [[x]] = SOME [[v_desc]]) }}
-%% %%     {{ lem Pmap.find [[x]] [[E_x]] = [[v_desc]] }} 
-%% %% 
-%% %%   | E_l ( x ) gives t                                           :: :: lookup_l
-%% %%     {{ com Lexical binding lookup }}
-%% %%     {{ hol (FLOOKUP [[E_l]] [[x]] = SOME [[t]]) }}
-%% %%     {{ lem Pmap.find [[x]] [[E_l]] = [[t]] }} 
-%% %% 
-%% %% %   | TD ( p ) gives tc_def                                     :: :: lookup_tc
-%% %% %     {{ com Type constructor lookup }}
-%% %% %     {{ hol (FLOOKUP [[TD]] [[p]] = SOME [[tc_def]]) }}
-%% %% %     {{ lem Pmap.find [[p]] [[TD]] = [[tc_def]] }} 
-%% %% % 
-%% %% %   | TC ( p ) gives xs                                         :: :: lookup_class
-%% %% %     {{ com Type constructor lookup }}
-%% %% %     {{ hol (FLOOKUP [[TC]] [[p]] = SOME [[xs]]) }}
-%% %% %     {{ lem Pmap.find [[p]] [[TC]] = [[xs]] }} 
-%% %% 
-%% %%   | dom ( E_m1 ) inter dom ( E_m2 ) = emptyset                  :: :: E_m_disjoint
-%% %%     {{ hol (DISJOINT (FDOM [[E_m1]]) (FDOM [[E_m2]])) }}
-%% %%     {{ lem disjoint (Pmap.domain [[E_m1]]) (Pmap.domain [[E_m2]]) }} 
-%% %% 
-%% %%   | dom ( E_x1 ) inter dom ( E_x2 ) = emptyset                  :: :: E_x_disjoint
-%% %%     {{ hol (DISJOINT (FDOM [[E_x1]]) (FDOM [[E_x2]])) }}
-%% %%     {{ lem disjoint (Pmap.domain [[E_x1]]) (Pmap.domain [[E_x2]])  }} 
-%% %%     
-%% %%   | dom ( E_f1 ) inter dom ( E_f2 ) = emptyset                  :: :: E_f_disjoint
-%% %%     {{ hol (DISJOINT (FDOM [[E_f1]]) (FDOM [[E_f2]])) }}
-%% %%     {{ lem disjoint (Pmap.domain [[E_f1]]) (Pmap.domain [[E_f2]]) }} 
-%% %% 
-%% %% %   | dom ( E_p1 ) inter dom ( E_p2 ) = emptyset                        :: :: E_p_disjoint
-%% %% %     {{ hol (DISJOINT (FDOM [[E_p1]]) (FDOM [[E_p2]])) }}
-%% %% %     {{ lem disjoint (Pmap.domain [[E_p1]]) (Pmap.domain [[E_p2]]) }} 
-%% %% % 
-%% %%   | disjoint doms ( E_l1 , .... , E_ln )                        :: :: E_l_disjoint
-%% %%     {{ hol (FOLDR (\E b. case b of NONE => NONE | SOME s => if DISJOINT (FDOM
-%% %% E) s then SOME (FDOM E UNION s) else NONE) (SOME {}) [[E_l1....E_ln]] <> NONE) }}
-%% %%     {{ lem disjoint_all (List.map Pmap.domain [[E_l1 .... E_ln]]) }}
-%% %%     {{ com Pairwise disjoint domains }}
-%% %% 
-%% %%   | disjoint doms ( E_x1 , .... , E_xn )                        :: :: E_x_disjoint_many
-%% %%     {{ hol (FOLDR (\E b. case b of NONE => NONE | SOME s => if DISJOINT (FDOM
-%% %% E) s then SOME (FDOM E UNION s) else NONE) (SOME {}) [[E_x1....E_xn]] <> NONE) }}
-%% %%     {{ lem disjoint_all (List.map Pmap.domain [[E_x1 .... E_xn]]) }}
-%% %%     {{ com Pairwise disjoint domains }}
-%% %% 
-%% %%   | compatible overlap ( x1 |-> t1 , .. , xn |-> tn )           :: :: E_l_compat
-%% %%     {{ hol (!__n __m. MEM __m [[x1 t1 .. xn tn]] /\ MEM __n [[x1 t1..xn tn]] /\ (FST __m  = FST __n) ==> (SND __m = SND __n)) }}
-%% %%     {{ lem (compatible_overlap [[x1 t1 .. xn tn]]) }} 
-%% %%     {{ com $(\ottnt{x}_i = \ottnt{x}_j) \ensuremath{\Longrightarrow} (\ottnt{t}_i = \ottnt{t}_j)$ }}
-%% %% 
-%% %%   | duplicates ( tnvs ) = emptyset                              :: :: no_dups_tnvs
-%% %%     {{ hol (ALL_DISTINCT [[tnvs]]) }}
-%% %%     {{ lem (duplicates [[tnvs]]) = [ ] }} 
-%% %% 
-%% %%   | duplicates ( x1 , .. , xn ) = emptyset                      :: :: no_dups
-%% %%     {{ hol (ALL_DISTINCT [[x1..xn]]) }}
-%% %%     {{ lem (duplicates [[x1..xn]]) = [ ] }} 
-%% %% 
-%% %%   | x NOTIN dom ( E_l )                                         :: :: notin_dom_l
-%% %%     {{ hol ([[x]] NOTIN FDOM [[E_l]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[x]] [[E_l]]) }} 
-%% %% 
-%% %%   | x NOTIN dom ( E_x )                                         :: :: notin_dom_v
-%% %%     {{ hol ([[x]] NOTIN FDOM [[E_x]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[x]] [[E_x]]) }} 
-%% %% 
-%% %%   | x NOTIN dom ( E_f )                                         :: :: notin_dom_f
-%% %%     {{ hol ([[x]] NOTIN FDOM [[E_f]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[x]] [[E_f]]) }} 
-%% %% 
-%% %% %   | p NOTIN dom ( TC )                                                :: :: notin_dom_tc
-%% %% %     {{ hol ([[p]] NOTIN FDOM [[TC]]) }}
-%% %% %     {{ lem Pervasives.not (Pmap.mem [[p]] [[TC]]) }} 
-%% %% 
-%% %%   | p NOTIN dom ( TD )                                          :: :: notin_dom_td
-%% %%     {{ hol ([[p]] NOTIN FDOM [[TD]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[p]] [[TD]]) }} 
-%% %% 
-%% %%   | FV ( t ) SUBSET tnvs                                                :: :: FV_t
-%% %%     {{ com Free type variables }}
-%% %%     {{ hol (LIST_TO_SET (ftv_t [[t]]) SUBSET LIST_TO_SET [[tnvs]]) }}
-%% %%     {{ lem subst (ftv_t [[t]]) [[tnvs]]  }} 
-%% %% 
-%% %%   | FV ( t_multi ) SUBSET tnvs                                  :: :: FV_t_multi
-%% %%     {{ com Free type variables }}
-%% %%     {{ hol (LIST_TO_SET (FLAT (MAP ftv_t [[t_multi]])) SUBSET LIST_TO_SET [[tnvs]]) }}
-%% %%     {{ lem subst (ftv_tm [[t_multi]]) [[tnvs]]  }} 
-%% %% 
-%% %%   | FV ( semC ) SUBSET tnvs                                     :: :: FV_semC
-%% %%     {{ com Free type variables }}
-%% %%     {{ hol (LIST_TO_SET (MAP SND [[semC]]) SUBSET LIST_TO_SET [[tnvs]]) }}
-%% %%     {{ lem subst (ftv_s [[semC]]) [[tnvs]] }} 
-%% %% 
-%% %%   | inst 'IN' I                                                 :: :: inst_in
-%% %%     {{ hol (MEM [[inst]] [[I]]) }}
-%% %%     {{ lem ([[inst]] IN [[I]]) }}
-%% %% 
-%% %%   | ( p t ) NOTIN I                                             :: :: notin_I
-%% %%     {{ hol (~?__semC__. MEM (Inst __semC__ [[p]] [[t]]) [[I]]) }}
-%% %%     {{ lem (Pervasives.not ((Inst [] [[p]] [[t]]) IN [[I]])) }}
-%% %% 
-%% %%   | E_l1 = E_l2                                                 :: :: E_l_eqn
-%% %%     {{ ichl ([[E_l1]] = [[E_l2]]) }}
-%% %% 
-%% %%   | E_x1 = E_x2                                                 :: :: E_x_eqn
-%% %%     {{ ichl ([[E_x1]] = [[E_x2]]) }}
-%% %% 
-%% %%   | E_f1 = E_f2                                                 :: :: E_f_eqn
-%% %%     {{ ichl ([[E_f1]] = [[E_f2]]) }}
-%% %% 
-%% %%   | E1 = E2                                                     :: :: E_eqn
-%% %%     {{ ichl ([[E1]] = [[E2]]) }}
-%% %% 
-%% %%   | TD1 = TD2                                                   :: :: TD_eqn
-%% %%     {{ ichl ([[TD1]] = [[TD2]]) }}
-%% %% 
-%% %%   | TC1 = TC2                                                   :: :: TC_eqn
-%% %%     {{ ichl ([[TC1]] = [[TC2]]) }}
-%% %% 
-%% %%   | I1 = I2                                                     :: :: I_eqn
-%% %%     {{ ichl ([[I1]] = [[I2]]) }}
-%% %% 
-%% %%   | names1 = names2                                             :: :: names_eq
-%% %%     {{ ichl ([[names1]] = [[names2]]) }}
-%% %% 
-%% %%   | t1 = t2                                                     :: :: t_eq
-%% %%     {{ ichl ([[t1]] = [[t2]]) }}
-%% %% 
-%% %%   | t_subst1 = t_subst2                                         :: :: t_subst_eq
-%% %%     {{ ichl ([[t_subst1]] = [[t_subst2]]) }}
-%% %% 
-%% %%   | p1 = p2                                                     :: :: p_eq
-%% %%     {{ ichl ([[p1]] = [[p2]]) }}
-%% %% 
-%% %%   | xs1 = xs2                                                   :: :: xs_eq
-%% %%     {{ ichl ([[xs1]] = [[xs2]]) }}
-%% %% 
-%% %%   | tnvs1 = tnvs2                                                       :: :: tnvs_eq
-%% %%     {{ ichl ([[tnvs1]] = [[tnvs2]]) }}
-
diff --git a/language/l2_parse2.ott b/language/l2_parse2.ott
deleted file mode 100644
index 0f8dc8e7..00000000
--- a/language/l2_parse2.ott
+++ /dev/null
@@ -1,1424 +0,0 @@
-indexvar n , i , j , k ::=
-  {{ phantom }}
-  {{ com Index variables for meta-lists }}
-
-metavar num ::=
-  {{ phantom }}
-  {{ lex numeric }}
-  {{ ocaml int }}
-  {{ hol num }}
-  {{ lem integer }}
-  {{ com Numeric literals }}
-  {{ ocamllex ['0'-'9']+  }}
-
-metavar hex ::=
-  {{ phantom }}
-  {{ lex numeric }}
-  {{ ocaml string }}
-  {{ lem string }}
-{{ ocamllex '0''x'['0'-'9' 'A' - 'F' 'a'-'f' '_']+  }}
-  {{ com Bit vector literal, specified by C-style hex number }}
-  
-metavar bin ::=
-  {{ phantom }}
-  {{ lex numeric }}
-  {{ ocaml string }}
-  {{ lem string }}
-{{ ocamllex '\'' ['0' '1'     ' ']* '\''  }}
-  {{ com Bit vector literal, specified by C-style binary number }}  
-
-metavar string ::=
-  {{ phantom }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ ocamllex "a"  }} {{ phantom }}
-  {{ com String literals }}
-
-metavar regexp ::=
-  {{ phantom }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ ocamllex "a"  }} {{ phantom }}
-  {{ com Regular expresions, as a string literal }}
-
-embed
-{{ ocaml
-
-type l =
-  | Unknown
-  | Int of string * l option
-  | Generated of l
-  | Range of Lexing.position * Lexing.position
-
-type 'a annot = l * 'a
-
-exception Parse_error_locn of l * string
-
-}}
-
-embed
-{{ lem
-open import Map
-open import Maybe
-open import Pervasives
-
-type l =
-  | Unknown
-  | Trans of string * maybe l
-  | Range of nat * nat
-
-val duplicates : forall 'a. list 'a -> list 'a
-
-val union_map : forall 'a 'b. map 'a 'b -> map 'a 'b -> map 'a 'b
-
-val set_from_list : forall 'a. list 'a -> set 'a
-
-val subst : forall 'a. list 'a -> list 'a -> bool
-
-}}
-
-metavar x , y , z ::=
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ com identifier }}
-  {{ ocamlvar "[[x]]" }}
-  {{ lemvar "[[x]]" }}
-  {{ ocamllex "a"  }} {{ phantom }}
-
-metavar ix ::=
-  {{ lex alphanum }}
-  {{ ocaml string }}
-  {{ lem string }}
-  {{ hol string }}
-  {{ com infix identifier }}
-  {{ ocamlvar "[[ix]]" }}
-  {{ lemvar "[[ix]]" }}
-  {{ ocamllex "a"  }} {{ phantom }}
-
-
-grammar
-
-l :: '' ::=                                     {{ phantom }}
-                                                {{ ocaml l }}
-                                                {{ lem l }}
-                                                {{ hol unit }}
-  {{ com Source location }}
-  |                                             :: :: Unknown
-    {{ ocaml Unknown }}
-    {{ lem Unknown }}
-    {{ hol () }}
-
-
-id :: '' ::=
-  {{ com Identifier }}
-  {{ aux _ l }}
-  | x                           :: :: id
-  | op x                        :: :: deIid {{ com remove infix status }}
-
-
-kid :: '' ::=
-  {{ com identifiers with kind, ticked to differntiate from program variables }}
-  {{ aux _ l }}
-  | ' x                       :: :: var
-
-% Note: we have just a single namespace. We don't want the same
-% identifier to be reused as a type name or variable, expression
-% variable, and field name.  We don't enforce any lexical convention
-% on type variables (or variables of other kinds)
-% We don't enforce a lexical convention on infix operators, as some of the 
-% targets use alphabetical infix operators. 
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Kinds and Types                                              %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-grammar
-
-base_kind :: 'BK_' ::=  
-  {{ com base kind}}
-  {{ aux _ l }}
-  | Type                                       :: :: type    {{ com kind of types  }} 
-  | Nat                                        :: :: nat     {{ com kind of natural number size expressions  }} 
-  | Order                                     :: :: order  {{ com kind of vector order specifications  }} 
-  | Effect                                    :: :: effect {{ com kind of effect sets  }} 
-
-kind :: 'K_' ::=  
-  {{ com kinds}}
-  {{ aux _ l }}
-  | base_kind1 -> ... -> base_kindn            :: :: kind 
-% we'll never use  ...-> Nat
-
-base_effect :: 'BE_' ::=
-  {{ com effect }}
-  {{ aux _ l }}  
-  | rreg                                :: :: rreg {{ com read register }}
-  | wreg                                :: :: wreg {{ com write register }}
-  | rmem                                :: :: rmem {{ com read memory }}
-  | wmem                                :: :: wmem {{ com write memory }}
-  | wmv					:: :: wmv {{ com write memory value }}
-  | eamem				:: :: eamem {{ com address for write signaled }}
-  | barr                                :: :: barr {{ com memory barrier }}
-  | depend				:: :: depend {{ com dynmically dependent footprint }}
-  | undef                               :: :: undef {{ com undefined-instruction exception }}
-  | unspec                              :: :: unspec {{ com unspecified values }}
-  | nondet                              :: :: nondet {{ com nondeterminism from intra-instruction parallelism }}
-  | escape                              :: :: escape
-
-
-
-atomic_typ :: 'ATyp_' ::= 
-  {{ quotient-with atyp }}
-  | id :: :: id
-  | kid :: :: var
-  | num :: :: constant
-  | dec :: :: dec
-  | inc :: :: inc
-  | id ( atyp1 , ... , atypn ) :: :: app
-  | ( atyp ) :: S :: paren {{ ocaml [[atyp]] }} 
-  | ( atyp1 , .... , atypn ) :: :: tup
-  | {| num_list |} :: S :: existential_set {{ ocaml   
-    { let v = mk_kid "n" $startpos $endpos in
-      let atom_id = mk_id (Id "atom") $startpos $endpos in
-      let atom_of_v = mk_typ (ATyp_app (atom_id, [mk_typ (ATyp_var v) $startpos $endpos])) $startpos $endpos in
-      mk_typ (ATyp_exist ([v], NC_aux (NC_set (v, [[num_list]]), loc $startpos($2) $endpos($2)), atom_of_v)) $startpos $endpos } }}
-  | { kid_list .  atyp } :: S :: existential_true {{ ocaml
-    { mk_typ (ATyp_exist ([[kid_list]], NC_aux (NC_true, loc $startpos $endpos), [[atyp]])) $startpos $endpos } }}
-  | { kid_list ,  nc . atyp } :: :: exist 
-  | { base_effect1 , .. , base_effectn }           :: :: set {{ com effect set }}
-  | pure                                 :: M :: pure {{ com sugar for empty effect set }} {{ icho [] }}
-
-
-atyp :: 'ATyp_' ::= 
-  {{ com expressions of all kinds, to be translated to types, nats, orders, and effects after parsing }}
-  {{ aux _ l }}
-  | atomic_typ                          :: S :: atomic {{ ocaml [[atomic_typ]] }} {{ quotient-remove }}
-  | atyp1 * atyp2                       :: :: times        {{ com product }}
-  | atyp1 + atyp2                       :: :: sum          {{ com sum }}
-  | atyp1 - atyp2                        :: :: minus	     {{ com subtraction }}
-  | 2** atyp                            :: :: exp         {{ com exponential }}
-  | neg atyp				:: :: neg	  {{ com Internal (but not M as I want a datatype constructor) negative nexp }}
-  | atyp1 -> atyp2 effect atyp3                        :: :: fn
-    {{ com Function type (first-order only in user code), last atyp is an effect }}
-
-
-% plus more for l-value/r-value pairs, as introduced by the L3 'compound' declarations   ... ref typ
-
-%typ_lib :: 'Typ_lib_' ::=
-%  {{ com library types and syntactic sugar for them }}
-%  {{ aux _ l }} %{{ auxparam 'a }}
-% boring base types:
-%  | unit :: :: unit {{ com unit type with value $()$ }}
-%  | bool :: :: bool {{ com booleans $[[true]]$ and $[[false]]$ }}
-%  | bit :: :: bit  {{ com pure bit values (not mutable bits) }}
-% experimentally trying with two distinct types of bool and bit ...
-%  | nat :: :: nat {{ com natural numbers 0,1,2,... }}
-%  | string :: :: string {{ com UTF8 strings }}
-% finite subranges of nat
-%  | enum nexp1 nexp2 order :: :: enum  {{ com natural numbers [[atyp2]] .. [[atyp2]]+[[atyp1]]-1, ordered by order }}
-%  | [ nexp ]             :: :: enum1 {{ com sugar for \texttt{enum nexp 0 inc} }}
-%  | [ nexp : nexp' ]  :: :: enum2 {{ com sugar for \texttt{enum (nexp'-nexp+1) nexp inc} or \texttt{enum (nexp-nexp'+1) nexp' dec} }}
-% use .. not - to avoid ambiguity with nexp -
-% total maps and vectors indexed by finite subranges of nat
-%  | vector nexp1 nexp2 order atyp :: :: vector {{ com vector of [[atyp]], indexed by natural range }}
-% probably some sugar for vector types, using [ ] similarly to enums:
-% (but with .. not : in the former, to avoid confusion...)
-%  | atyp [ nexp ]  :: :: vector2 {{ com sugar for vector indexed by [ [[atyp]] ] }}
-%  | atyp [ nexp : nexp' ] :: :: vector3 {{ com sugar for vector indexed by [ [[atyp]]..[[atyp']] ] }}
-% ...so bit [ nexp ] etc is just an instance of that
-%  | list atyp :: :: list {{ com list of [[atyp]] }}
-%  | set atyp  :: :: set  {{ com finite set of [[atyp]] }}
-%  | reg atyp  :: :: reg  {{ com mutable register components holding [[atyp]] }}
-% "reg t" is basically the ML "t ref" 
-% not sure how first-class it should be, though
-% use "reg word32" etc for the types of vanilla registers 
-
-% parsing
-% 
-% ATyp_tup <= ATyp_tup
-% ATyp_fn right ATyp_fn
-% ATyp_fn <= ATyp_tup
-
-grammar
-
-n_constraint :: 'NC_' ::=
-  {{ com constraint over kind $[[Nat]]$ }}
-  {{ aux _ l }}
-  | atyp = atyp'                                :: :: fixed
-  | atyp >= atyp'                               :: :: bounded_ge
-  | atyp '<=' atyp'                             :: :: bounded_le
-  | kid 'IN' { num1 , ... , numn }               :: :: nat_set_bounded
-
-% Note only id on the left and constants on the right in a
-% finite-set-bound, as we don't think we need anything more
-
-kinded_id :: 'KOpt_' ::=
-  {{ com optionally kind-annotated identifier }}
-  {{ aux _ l }}
-  | kid	 	    		   	      :: :: none {{ com identifier }}
-  | kind kid				      :: :: kind {{ com kind-annotated variable }}
-
-quant_item :: 'QI_' ::=
-  {{ com Either a kinded identifier or a nexp constraint for a typquant }}
-  {{ aux _ l }}
-  | kinded_id 	  	 	       	      :: :: id {{ com An optionally kinded identifier }}
-  | n_constraint			      :: :: const {{ com A constraint for this type }}
-
-typquant :: 'TypQ_' ::= 
-  {{ com type quantifiers and constraints}}
-  {{ aux _ l }}
-  | forall quant_item1 , ... , quant_itemn . :: :: tq {{ texlong }}
-  |                           ::  ::  no_forall     {{ com sugar, omitting quantifier and constraints }}
-
-typschm :: 'TypSchm_' ::=
-  {{ com type scheme  }}
-  {{ aux _ l }}
-  |  typquant atyp                                                       :: :: ts
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Type definitions                                             %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-grammar
-%ctor_def :: 'CT_' ::=
-%  {{ com Datatype constructor definition clause }}
-%  {{ aux _ l }}
-%  | id : typschm                                       :: :: ct
-% but we could get away with disallowing constraints in typschm, we
-% think - if it's useful to do that
-
- name_scm_opt :: 'Name_sect_' ::=
-   {{ com Optional variable-naming-scheme specification for variables of defined type }} 
-   {{ aux _ l }}
-   |                                                   :: :: none
-   | [ name = regexp ]                                 :: :: some
-
-type_union :: 'Tu_' ::=
-  {{ com Type union constructors }}
-  {{ aux _ l }}
-  | id                                                  :: :: id
-  | atyp id                                             :: :: ty_id
-
-type_def :: 'TD_' ::=
-  {{ com Type definition body }}
-  {{ aux _ l }}
-  | typedef id name_scm_opt = typschm                                        :: :: abbrev
-    {{ com type abbreviation }} {{ texlong }}
-  | typedef id name_scm_opt = const struct typquant { atyp1 id1 ; ... ; atypn idn semi_opt }     :: :: record
-    {{ com struct type definition }} {{ texlong }}
-  | typedef id name_scm_opt = const union typquant { type_union1 ; ... ; type_unionn semi_opt }   :: :: variant
-    {{ com union type definition}} {{ texlong }}
-  | typedef id name_scm_opt = enumerate { id1 ; ... ; idn semi_opt }   :: :: enum
-    {{ com enumeration type definition}} {{ texlong }}
-
-  | typedef id = register bits [ atyp : atyp' ] { index_range1 : id1 ; ... ; index_rangen : idn } 
-:: :: register {{ com register mutable bitfield type definition }} {{ texlong }}
-
-kind_def :: 'KD_' ::=
-  {{ com Definition body for elements of kind; many are shorthands for type\_defs }}
-  {{ aux _ l }}
-  | Def kind id name_scm_opt = typschm                                        :: :: abbrev
-    {{ com type abbreviation }} {{ texlong }}
-  | Def kind id name_scm_opt = const struct typquant { atyp1 id1 ; ... ; atypn idn semi_opt }     :: :: record
-    {{ com struct type definition }} {{ texlong }}
-  | Def kind id name_scm_opt = const union typquant { type_union1 ; ... ; type_unionn semi_opt }   :: :: variant
-    {{ com union type definition}} {{ texlong }}
-  | Def kind id name_scm_opt = enumerate { id1 ; ... ; idn semi_opt }   :: :: enum
-    {{ com enumeration type definition}} {{ texlong }}
-
-  | Def kind id = register bits [ atyp : atyp' ] { index_range1 : id1 ; ... ; index_rangen : idn } 
-:: :: register {{ com register mutable bitfield type definition }} {{ texlong }}
-
-
-% also sugar [  nexp ] 
-
-
-index_range :: 'BF_' ::= {{ com index specification, for bitfields in register types}} 
-  {{ aux _ l }}
-  | num :: :: 'single'  {{ com single index }}
-  | num1 : num2 :: :: range {{ com index range }}
-  | index_range1 , index_range2 :: :: concat {{ com concatenation of index ranges }}
-
-% 
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Literals                                                     %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-grammar
-
-lit :: 'L_' ::=
-  {{ com Literal constant }}
-  {{ aux _ l }}
-  | ( )                                                 :: :: unit  {{ com $() : [[unit]]$ }}
-%Presumably we want to remove bitzero and bitone ?
-  | bitzero                                             :: :: zero {{ com $[[bitzero]] : [[bit]]$ }}
-  | bitone                                              :: :: one {{ com $[[bitone]] : [[bit]]$ }}
-  | true                                                :: :: true  {{ com $[[true]] : [[bool]]$ }}
-  | false                                               :: :: false {{ com $[[false]] : [[bool]]$ }}
-  | num                                         :: :: num  {{ com natural number constant }}
-  | hex                                         :: :: hex  {{ com bit vector constant, C-style }}
-  {{ com hex and bin are constant bit vectors, C-style }}
-  | bin                                         :: :: bin  {{ com bit vector constant, C-style }}
-  | undefined					:: :: undef {{ com undefined value }}
-  | string                                              :: :: string {{ com string constant }}
-
-semi_opt {{ tex \ottnt{;}^{?} }} :: 'semi_' ::=         {{ phantom }}
-                                                        {{ ocaml bool }}
-                                                        {{ lem bool }}
-                                                        {{ hol bool }}
-  {{ com Optional semi-colon }}
-  |                                                     :: :: no  
-    {{ hol F }}
-    {{ ocaml false }}
-    {{ lem false }}
-  | ';'                                                 :: :: yes
-    {{ hol T }}
-    {{ ocaml true }}
-    {{ lem true }}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Patterns                                                     %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-pat :: 'P_' ::= 
-  {{ com Pattern }}
-  {{ aux _ l }}
-  | lit                                                 :: :: lit
-    {{ com literal constant pattern }}
-  | _                                                   :: :: wild  
-    {{ com wildcard }}
-  | ( pat as id )                                      :: :: as
-    {{ com named pattern }}
-  | ( atyp ) pat                                       :: :: typ
-    {{ com typed pattern }}
-
-  | id                                      :: :: id
-    {{ com identifier  }}
-
-  | id ( pat1 , .. , patn )                                     :: :: app
-    {{ com union constructor pattern }}
-
-  | { fpat1 ; ... ; fpatn semi_opt }                  :: :: record
-    {{ com struct pattern }}
-
-  | [ pat1 , .. , patn  ]                     :: :: vector
-   {{ com vector pattern }}
-
-  | [ num1 = pat1 , .. , numn = patn  ]                     :: :: vector_indexed
-   {{ com vector pattern (with explicit indices) }}
-
-  |  pat1 : .... : patn                                   :: :: vector_concat
-  {{ com concatenated vector pattern }} 
-
-  | ( pat1 , .... , patn )                              :: :: tup
-    {{ com tuple pattern }}
-  | [|| pat1 , .. , patn ||]	                        :: :: list
-    {{ com list pattern }}
-  | ( pat )                                             :: S :: paren
-{{ ichlo [[pat]] }}
-
-fpat :: 'FP_' ::=
-  {{ com Field pattern }}
-  {{ aux _ l }}
-  | id = pat                                            :: :: Fpat
-
-parsing
-P_app <= P_app
-P_app <= P_as
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Expressions                                                  %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-
-grammar
-
-exp :: 'E_' ::=
-  {{ com Expression }}
-  {{ aux _ l }}
-
-  | { exp1 ; ... ; expn }                               :: :: block {{ com block (parsing conflict with structs?) }}
-% maybe we really should have indentation-sensitive syntax :-)  (given that some of the targets do)
-
-  | nondet { exp1 ; ... ; expn }                        :: :: nondet {{ com block that can evaluate the contained expressions in any ordering }}
-
-  | id                                                  :: :: id
-    {{ com identifier }}
-
-  | lit                                                 :: :: lit
-    {{ com literal constant }}
-
-  | ( atyp ) exp                                         :: :: cast
-    {{ com cast }}
-
-
-  | id exp                                               :: S :: tup_app {{ ichlo [[id]] ( [[exp]] ) }} {{ com No extra parens needed when exp is a tuple }}
-  | id ( exp1 , .. , expn )                                   :: :: app
-    {{ com function application }}
-% Note: fully applied function application only
-
-  | exp1 id exp2                                        :: :: app_infix
-    {{ com infix function application }}
- 
-  | ( exp1 , .... , expn )                              :: :: tuple
-    {{ com tuple }}
-
-  | if exp1 then exp2 else exp3                         :: :: if
-    {{ com conditional }}
-
-  | if exp1 then exp2                                   :: S :: ifnoelse {{ icho [[ if exp1 then exp2 else unit ]] }}
-
-  | foreach id from exp1 to exp2 by exp3 in atyp exp4   ::   :: for {{ com loop }}
-  | foreach id from exp1 to exp2 by exp3 exp4           :: S :: forup {{ ichlo [[ foreach id from exp1 to exp2 by exp3 in inc exp4 ]] }}
-  | foreach id from exp1 to exp2 exp3                   :: S :: forupbyone  {{ icho [[ foreach id from exp1 to exp2 by 1 exp4 ]] }}
-  | foreach id from exp1 downto exp2 by exp3 exp4       :: S :: fordown {{ icho [[ foreach id from exp1 to exp2 by ( - exp3 ) exp4 ]] }}
-  | foreach id from exp1 downto exp2 exp3               :: S :: fordownbyone  {{ icho [[ foreach id from exp1 downto exp2 by 1 exp4 ]] }}
-
-% vectors
-  | [ exp1 , ... , expn ]                             :: :: vector {{ com vector (indexed from 0) }}
-% order comes from global command-line option???
-% here the expi are of type 'a and the result is a vector of 'a, whereas in exp1 : ... : expn 
-% the expi and the result are both of type vector of 'a 
-
-  | [ exp1 , ... , expn opt_default ]               :: :: vector_indexed {{ com vector (indexed consecutively) }}
-% num1 .. numn must be a consecutive list of naturals
-
-% we pick [ ] not { } for vector literals for consistency with their
-% array-like access syntax, in contrast to the C which has funny
-% syntax for array literals.  We don't have to preserve [ ] for lists
-% as we don't expect to use lists very much. 
-
-  | exp [ exp' ]                                      :: :: vector_access
-  {{ com vector access }}
-
-  | exp [ exp1 '..' exp2 ]                               :: :: vector_subrange
-  {{ com subvector extraction }}
-  % do we want to allow a comma-separated list of such thingies?  
-
-  | [ exp with exp1 = exp2 ]                          :: :: vector_update 
-  {{ com vector functional update }}
-
-  | [ exp with exp1 : exp2 = exp3 ]                   :: :: vector_update_subrange
-  {{ com vector subrange update (with vector)}}
-  % do we want a functional update form with a comma-separated list of such?
-
-  | exp : exp2                                        :: :: vector_append
-  {{ com vector concatenation }}
-
-% lists 
-  | [|| exp1 , ..  , expn ||]                           :: :: list
-  {{ com list }}
-  | exp1 '::' exp2                                    :: :: cons
-    {{ com cons }}
-
-
-% const unions
-
-% const structs
-
-% TODO
-
-  | { fexps }                                         :: :: record
-    {{ com struct }}
-  | { exp with exp1 ; .. ; expn }                                :: :: record_update
-    {{ com functional update of struct }}
-  | exp . id                                          :: :: field
-    {{ com field projection from struct  }}
-
-%Expressions for creating and accessing vectors
-
-
-
-%  map : forall 'x 'y ''N.  ('x -> 'y) -> vector ''N 'x -> vector ''N 'y
-%  zip : forall 'x 'y ''N.  vector ''N 'x  -> vector ''N 'y -> vector ''N ('x*'y) 
-%  foldl : forall 'x 'y ''N. ('x 'y -> 'y) -> vector ''N 'x -> 'y -> 'y
-% foldr : forall 'x 'y ''N. ('x 'y -> 'y) -> 'y -> vector ''N 'x -> 'y
-% foldmap : forall 'x 'y 'z ''N. ((x,y) -> (x,z)) -> x -> vector ''N y -> vector ''N z
-%(or unzip)
-
-%  and maybe with nice syntax
-
-  | switch exp { case pexp1  ... case pexpn } :: :: case
-    {{ com pattern matching }}
-  | letbind in exp                                  :: :: let
-    {{ com let expression }}
-
-  | exp := exp'                                      :: :: assign
-    {{ com imperative assignment }}
-
-  | sizeof atyp                                         :: :: sizeof
-  | exit exp						:: :: exit
-  | return exp                                          :: :: return
-  | assert ( exp , exp' )                               :: :: assert
-
-  | ( exp )                                             :: S :: paren {{ ichlo [[exp]] }}
-
-
-lexp :: 'LEXP_' ::= {{ com lvalue expression, can't occur out of the parser }}
-    {{ aux _ l }}
-%    {{ aux _ annot }} {{ auxparam 'a }}
-    | id                                                  :: :: id
-    {{ com identifier }}
-    | id ( exp1 , .. , expn )				  :: :: mem
-    | id exp	       	    				  :: S :: mem_tup {{ ichlo [[id (exp)]] }}
-    | lexp [ exp ]  :: ::                         vector  {{ com vector element }}
-    | lexp [ exp1 : exp2 ]  :: ::              vector_range {{ com subvector }}
-    % maybe comma-sep such lists too
-    | lexp . id :: :: field                        {{ com struct field }}
-
-
-fexp :: 'FE_' ::=
-  {{ com Field-expression }}
-  {{ aux _ l }} 
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | id = exp                                            :: :: Fexp
-
-fexps :: 'FES_' ::=
-  {{ com Field-expression list }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | fexp1 ; ... ; fexpn semi_opt                        :: :: Fexps
-
-opt_default :: 'Def_val_' ::=
-  {{ com Optional default value for indexed vectors, to define a defualt value for any unspecified positions in a sparse map }}
-  {{ aux _ l }} 
-  |                                                     :: :: empty
-  | ; default = exp                                       :: :: dec
-
-pexp :: 'Pat_' ::=
-  {{ com Pattern match }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | pat -> exp                                  :: :: exp
-% apparently could use -> or => for this.
-
-%% % psexp :: 'Pats' ::=
-%% %   {{ com Multi-pattern matches }}
-%% %   {{ aux _ l }}
-%% %   | pat1 ... patn -> exp                                :: :: exp
-
-
-parsing
-
-%P_app right LB_Let_val
-
-%%P_app <= Fun
-
-%%Fun right App
-%%Function right App
-E_case right E_app
-E_let right E_app
-
-%%Fun <= Field
-%%Function <= Field
-E_app <= E_field
-E_case <= E_field
-E_let <= E_field
-
-E_app left E_app
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Function definitions                                         %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-%%%% old Lem style %%%%%%
-grammar
-%% % lem_tannot_opt_aux :: 'LEM_Typ_annot_' ::=
-%% %   {{ com Optional type annotations }}
-%% %   |                                                     :: :: none
-%% %   | : typ                                               :: :: some 
-%% % 
-%% % lem_tannot_opt {{ tex \ottnt{tannot}^? }} :: 'LEM_Typ_annot_' ::=
-%% %   {{ com location-annotated optional type annotations }}
-%% %   | tannot_opt_aux l                                    :: :: aux
-%% % 
-%% % lem_funcl :: 'LEM_FCL' ::=
-%% %   {{ com Function clauses }}
-%% %   {{ aux _ l }}
-%% %   | id pat1 ... patn tannot_opt = exp                   :: :: Funcl
-%% % 
-%% % lem_letbind :: 'LEM_LB_' ::=
-%% %   {{ com Let bindings }}
-%% %   {{ aux _ l }}
-%% %   | pat tannot_opt = exp                                :: :: Let_val
-%% %     {{ com Value bindings }}
-%% %   | lem_funcl                                           :: :: Let_fun
-%% %     {{ com Function bindings }}
-%% % 
-%% % 
-%% % grammar
-%% % lem_val_def :: 'LEM_VD' ::= 
-%% %   {{ com Value definitions }}
-%% %   {{ aux _ l }}
-%% %   | let lem_letbind                                     :: :: Let_def
-%% %     {{ com Non-recursive value definitions }}
-%% %   | let rec  lem_funcl1 and ... and lem_funcln          :: :: Let_rec
-%% %     {{ com Recursive function definitions }}
-%% % 
-%% % lem_val_spec :: 'LEM_VS' ::=
-%% %   {{ com Value type specifications }} 
-%% %   {{ aux _ l }}
-%% %   | val x_l : typschm                                           :: :: Val_spec
-
-%%%%% C-ish style %%%%%%%%%%
-
-tannot_opt :: 'Typ_annot_opt_' ::=
-  {{ com Optional type annotation for functions}}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  |                                             :: :: none
-  | typquant atyp                               :: :: some 
-
-rec_opt :: 'Rec_' ::=
-  {{ com Optional recursive annotation for functions }}
-  {{ aux _ l }}
-  |                                             :: :: nonrec {{ com non-recursive }}
-  | rec                                         :: :: rec {{ com recursive }}
-
-effect_opt :: 'Effect_opt_' ::=
-  {{ com Optional effect annotation for functions }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  |                                             :: :: pure {{ com sugar for empty effect set }}
-  | effectkw atyp                                     :: :: effect
-
-funcl :: 'FCL_' ::=
-  {{ com Function clause }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | id pat = exp                   :: :: Funcl
-
-
-fundef :: 'FD_' ::=
-  {{ com Function definition}}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | function rec_opt tannot_opt effect_opt funcl1 and ... and funcln :: :: function {{ texlong }}  
-% {{ com function definition }}
-% TODO note that the typ in the tannot_opt is the *result* type, not
-%  the type of the whole function.  The argument type comes from the
-%  pattern in the funcl
-% TODO the above is ok for single functions, but not for mutually
-%  recursive functions - the tannot_opt scopes over all the funcli,
-%  which is ok for the typ_quant part but not for the typ part
-
-letbind :: 'LB_' ::=
-  {{ com Let binding }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | let typschm pat = exp                                :: :: val_explicit
-    {{ com value binding, explicit type ([[pat]] must be total)}}
-  | let pat = exp                                    :: :: val_implicit
-    {{ com value binding, implicit type ([[pat]] must be total)}}
-
-
-val_spec :: 'VS_' ::=
-  {{ com Value type specification }} 
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | val typschm id                                  :: :: val_spec
-  | val extern typschm id                           :: :: extern_no_rename
-  | val extern typschm id = string                  :: :: extern_spec
-
-default_typing_spec :: 'DT_' ::=
-  {{ com Default kinding or typing assumption, and default order for literal vectors and vector shorthands }}
-  {{ aux _ l }}
-%  {{ aux _ annot }} {{ auxparam 'a }}
-  | default base_kind kid    :: :: kind
-  | default base_kind atyp   :: :: order
-  | default typschm id      :: :: typ
-% The intended semantics of these is that if an id in binding position
-% doesn't have a kind or type annotation, then we look through the
-% default regexps (in order from the beginning) and pick the first
-% assumption for which id matches the regexp, if there is one.
-% Otherwise we try to infer.  Perhaps warn if there are multiple matches.
-% For example, we might often have default Type ['alphanum]
-
-scattered_def :: 'SD_' ::=
-  {{ com Function and type union definitions that can be spread across
-         a file. Each one must end in $[[end id]]$ }}
-  {{ aux _ l }} 
-  | scattered function rec_opt tannot_opt effect_opt id   :: :: scattered_function {{ texlong }} {{ com scattered function definition header }}
-
-  | function clause funcl  :: :: scattered_funcl  
-{{ com scattered function definition clause }}
-
-  | scattered typedef id name_scm_opt = const union typquant :: :: scattered_variant {{ texlong }} {{ com scattered union definition header }}
-
-  | union id member type_union  :: :: scattered_unioncl {{ com scattered union definition member }}
-  | end id  :: :: scattered_end
-{{ com scattered definition end }}
-
-dec_spec :: 'DEC_' ::=
-  {{ com Register declarations }}
-  {{ aux _ l }}
-  | register atyp id                                             :: :: reg
-  | register alias id = exp	      	 			 :: :: alias
-  | register alias atyp id = exp	  			 :: :: typ_alias
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Top-level definitions                                        %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-def :: 'DEF_' ::=
-  {{ com Top-level definition }}
-  | kind_def                                                    :: :: kind
-    {{ com definition of named kind identifiers }}
-  | type_def                                                    :: :: type
-    {{ com type definition }}
-  | fundef                                                   :: :: fundef
-    {{ com function definition }}
-  | letbind                                                   :: :: val
-    {{ com value definition }}
-  | val_spec                                                    :: :: spec
-    {{ com top-level type constraint }}
-  | default_typing_spec                                         :: :: default
-    {{ com default kind and type assumptions }}
-  | scattered_def					:: :: scattered
-    {{ com scattered definition }} 
-  | dec_spec                                            :: :: reg_dec
-    {{ com register declaration }}
-
-defs :: '' ::=
-  {{ com Definition sequence }}
-  | def1  .. defn                 :: :: Defs
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Machinery for typing rules                                   %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-%% %% 
-%% %% 
-%% %% grammar
-%% %% 
-%% %% 
-%% %% p :: 'Path_' ::=
-%% %%   {{ com Unique paths }}
-%% %%   | x1 . .. xn . x                              :: :: def
-%% %%   | __list                                      :: :: list      
-%% %%     {{ tex \ottkw{\_\_list}  }}
-%% %%   | __bool                                      :: :: bool
-%% %%     {{ tex \ottkw{\_\_bool}  }}
-%% %%   | __num                                       :: :: num
-%% %%     {{ tex \ottkw{\_\_num}  }}
-%% %%   | __set                                       :: :: set
-%% %%     {{ tex \ottkw{\_\_set}  }}
-%% %%   | __string                                    :: :: string
-%% %%     {{ tex \ottkw{\_\_string}  }}
-%% %%   | __unit                                      :: :: unit
-%% %%     {{ tex \ottkw{\_\_unit}  }}
-%% %%   | __bit                                       :: :: bit
-%% %%     {{ tex \ottkw{\_\_bit}  }}
-%% %%   | __vector                            :: :: vector
-%% %%     {{ tex \ottkw{\_\_vector} }}                
-%% %% %TODO morally, delete the above - but what are the __ things for?
-%% %% % cleaner to declare early in the library?
-%% %% 
-%% %% t_subst {{ tex \ensuremath{\sigma} }} :: '' ::= {{ phantom }}
-%% %%                                                 {{ hol (a # t) list }}
-%% %%                                                 {{ lem list (tnvar * t) }}
-%% %%   {{ com Type variable substitutions }}
-%% %%   | { tnvar1 |-> t1 .. tnvarn |-> tn }                  :: :: T_subst
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ lem ([[tnvar1 t1 .. tnvarn tn]]) }}
-%% %%     {{ hol ([[tnvar1 t1 .. tnvarn tn]]) }}
-%% %% 
-%% %% t , u :: 'T_' ::=
-%% %%   {{ com Internal types }}
-%% %%   | a                                           :: :: var
-%% %%   | t1 -> t2                                    :: :: fn
-%% %%   | t1 * .... * tn                              :: :: tup
-%% %%   | p t_args                                    :: :: app 
-%% %%   | ne                                          :: :: len
-%% %%   | t_subst ( t )                               :: M :: subst_app
-%% %%     {{ com Multiple substitutions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (t_subst_t [[t_subst]] [[t]]) }}
-%% %%     {{ lem (t_subst_t [[t_subst]] [[t]]) }}
-%% %%   | t_subst ( tnv )                     :: M :: var_subst_app
-%% %%     {{ com Single variable substitution }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (t_subst_tnv [[t_subst]] [[tnv]]) }}
-%% %%     {{ lem (t_subst_tnv [[t_subst]] [[tnv]]) }}
-%% %%   | curry ( t_multi ,  t )                      :: M :: multifn
-%% %%     {{ com Curried, multiple argument functions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (FOLDR T_fn [[t]] [[t_multi]]) }}
-%% %%     {{ lem (List.fold_right T_fn [[t_multi]] [[t]]) }}
-%% %% 
-%% %% ne :: 'Ne_' ::=
-%% %%   {{ com internal numeric expressions }}
-%% %%   | N                                           :: :: var
-%% %%   | nat                                 :: :: const
-%% %%   | ne1 * ne2                           :: :: mult
-%% %%   | ne1 + ne2                           :: :: add
-%% %%   | ( - ne )                            :: :: unary
-%% %%   | normalize ( ne )                    :: M :: normalize
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (normalize [[ne]] ) }}
-%% %%   | ne1 + ... + nen                     :: M :: addmany
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (sumation_nes [[ne1...nen]]) }}
-%% %%   | bitlength ( bin )                   :: M :: cbin
-%% %%     {{ ocaml (asssert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (blength [[bin]]) }}
-%% %%   | bitlength ( hex )                   :: M :: chex
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (hlength [[hex]]) }}
-%% %%   | length ( pat1 ... patn )            :: M :: cpat
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol ARB }}
-%% %%     {{ lem (Ne_const (List.length [[pat1...patn]])) }}
-%% %%   | length ( exp1 ... expn )            :: M :: cexp
-%% %%     {{ hol ARB }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ lem (Ne_const (List.length [[exp1...expn]])) }}
-%% %% 
-%% %% t_args :: '' ::=
-%% %%   {{ com Lists of types }}
-%% %%   | t1 .. tn                            :: :: T_args
-%% %%   | t_subst ( t_args )                          :: M :: T_args_subst_app
-%% %%     {{ com Multiple substitutions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (t_subst_t_args [[t_subst]] [[t_args]]) }}
-%% %%     {{ lem (t_subst_t_args [[t_subst]] [[t_args]]) }}
-%% %% 
-%% %% t_multi :: '' ::=                               {{ phantom }}
-%% %%                                                 {{ hol t list }}
-%% %%                                                 {{ ocaml t list }}
-%% %%                                                 {{ lem list t }}
-%% %%   {{ com Lists of types }}
-%% %%   | ( t1 * .. * tn )                            :: :: T_multi
-%% %%     {{ hol [[t1..tn]] }}
-%% %%     {{ lem [[t1..tn]] }}
-%% %%   | t_subst ( t_multi )                         :: M :: T_multi_subst_app
-%% %%     {{ com Multiple substitutions }}
-%% %%     {{ ocaml (assert false) }}
-%% %%     {{ hol (MAP (t_subst_t [[t_subst]]) [[t_multi]]) }}
-%% %%     {{ lem (List.map (t_subst_t [[t_subst]]) [[t_multi]]) }}
-%% %% 
-%% %% nec :: '' ::=
-%% %%   {{ com Numeric expression constraints }}
-%% %%   | ne < nec            :: :: lessthan
-%% %%   | ne = nec            :: :: eq
-%% %%   | ne <= nec           :: :: lteq
-%% %%   | ne                          :: :: base
-%% %% 
-%% %% parsing
-%% %% T_fn right T_fn
-%% %% T_tup <= T_multi
-%% %% 
-%% %% embed
-%% %% {{ lem
-%% %% 
-%% %% val t_subst_t : list (tnv * t) -> t -> t 
-%% %% val t_subst_tnv : list (tnv * t) -> tnv -> t
-%% %% val ftv_t : t -> list tnv
-%% %% val ftv_tm : list t -> list tnv
-%% %% val ftv_s : list (p*tnv) -> list tnv
-%% %% val compatible_overlap : list (x*t) -> bool
-%% %% 
-%% %% (*TODO Should this normalize following the implementation? And blength and hlength need a means of implementation*)
-%% %% let normalize n = n
-%% %% 
-%% %% let blength (_,bit) = Ne_const 8
-%% %% let hlength (_,bit) = Ne_const 8
-%% %% 
-%% %% let rec sumation_nes nes = match nes with
-%% %%   | [ a; b] -> Ne_add a b 
-%% %%   | x :: y -> Ne_add x (sumation_nes y)
-%% %% end
-%% %% 
-%% %% }}
-%% %% 
-%% %% grammar
-%% %% 
-%% %% 
-%% %% names :: '' ::=                                 {{ phantom }}
-%% %%                                                 {{ hol x set }}
-%% %%                                                 {{ lem set x }}
-%% %%                                                 {{ ocaml Set.Make(String).t }}
-%% %%   {{ com Sets of names }}
-%% %%   | { x1 , .. , xn }                            :: :: Names
-%% %%     {{ hol (LIST_TO_SET [[x1..xn]]) }}
-%% %%     {{ lem (set_from_list [[x1..xn]]) }}
-%% %% 
-%% %% semC {{ tex \ensuremath{\mathcal{C} } }} :: '' ::=
-%% %%                                                                 {{ hol (p#tnv) list }}
-%% %%                                                                 {{ lem list (p*tnv)  }}
-%% %% %   {{ com Typeclass constraint lists }}
-%% %% %   | ( p1 tnv1 ) .. ( pn tnvn )                                        :: :: SemC_concrete
-%% %% %     {{ hol ([[p1 tnv1..pn tnvn]]) }}
-%% %% %     {{ lem ([[p1 tnv1..pn tnvn]]) }}
-%% %% 
-%% %% env_tag :: '' ::=
-%% %%   {{ com Tags for the (non-constructor) value descriptions }}
-%% %% %  | method                                                     :: :: method
-%% %% %    {{ com Bound to a method }}
-%% %%   | val                                                         :: :: spec
-%% %%     {{ com Specified with val }}
-%% %%   | let                                                         :: :: def
-%% %%     {{ com Defined with let or indreln }}
-%% %% 
-%% %% v_desc :: 'V_' ::=
-%% %%   {{ com Value descriptions }}
-%% %%   | < forall tnvs . t_multi -> p , ( x of names ) >             :: :: constr
-%% %%     {{ com Constructors }}
-%% %%   | < forall tnvs . semC => t , env_tag >                       :: :: val
-%% %%     {{ com Values }}
-%% %% 
-%% %% f_desc :: 'F_' ::=
-%% %%   | < forall tnvs . p -> t , ( x of names ) >                   :: :: field
-%% %%     {{ com Fields }}
-%% %% 
-%% %% embed
-%% %% {{ hol
-%% %% load "fmaptreeTheory";
-%% %% val _ = 
-%% %%   Hol_datatype 
-%% %%     `env_body = <| env_p : x|->p; env_f : x|->f_desc; env_v : x|->v_desc |>`;
-%% %% 
-%% %% val _ = Define `
-%% %%   env_union e1 e2 =
-%% %%     let i1 = item e1 in
-%% %%     let m1 = map e1 in
-%% %%     let i2 = item e2 in
-%% %%     let m2 = map e2 in
-%% %%       FTNode <| env_p:=FUNION i1.env_p i2.env_p; 
-%% %%                 env_f:=FUNION i1.env_f i2.env_f;
-%% %%                 env_v:=FUNION i1.env_v i2.env_v |>
-%% %%              (FUNION m1 m2)`;
-%% %% }}
-%% %% {{ lem
-%% %% type env =
-%% %%   | EnvEmp 
-%% %%   | Env of (map x env) * (map x p) * (map x f_desc) * (map x v_desc)
-%% %% 
-%% %% val env_union : env -> env -> env
-%% %% let env_union e1 e2 =
-%% %%   match (e1,e2) with
-%% %%    | (EnvEmp,e2) -> e2
-%% %%    | (e1,EnvEmp) -> e1
-%% %%    | ((Env Em1 Ep1 Ef1 Ev1),(Env Em2 Ep2 Ef2 Ev2)) ->
-%% %%      Env(union_map Em1 Em2) (union_map Ep1 Ep2) (union_map Ef1 Ef2) (union_map Ev1 Ev2)
-%% %% end
-%% %% 
-%% %% }}
-%% %% 
-%% %% grammar
-%% %% 
-%% %% xs :: '' ::=                                    {{ phantom }}
-%% %%                                                 {{ hol string list }}
-%% %%                                                 {{ lem list string }}
-%% %%   | x1 .. xn                                    :: :: Xs
-%% %%     {{ hol [[x1..xn]] }}
-%% %%     {{ lem [[x1..xn]] }}
-%% %% 
-%% %% %TODO: no clue what the following are:
-%% %% S_c {{ tex {\ensuremath{ {\Sigma}^{\mathcal{C} } } } }} :: '' ::=                       {{ phantom }}
-%% %%                                                                 {{ hol (p#t) list }}
-%% %%                                                                 {{ lem list (p*t) }}
-%% %%   {{ com Typeclass constraints }}
-%% %%   | { ( p1 t1 ) , .. , ( pn tn ) }                              :: :: S_concrete
-%% %%     {{ hol [[p1 t1 .. pn tn]] }}
-%% %%     {{ lem [[p1 t1 .. pn tn]] }}
-%% %%   | S_c1 union .. union S_cn                                    :: M :: S_union
-%% %%     {{ hol (FLAT [[S_c1..S_cn]]) }}
-%% %%     {{ lem (List.flatten [[S_c1..S_cn]]) }}
-%% %%     {{ ocaml assert false }}
-%% %% 
-%% %% S_N {{ tex { \ensuremath{ {\Sigma}^{\mathcal{N} } } } }} :: '' ::= {{ phantom }}
-%% %%                                                                    {{ hol nec list }}
-%% %%                                                                    {{ lem list nec }}
-%% %%    {{ com nexp constraint lists }}
-%% %%    | { nec1 , .. ,  necn }                              :: :: Sn_concrete
-%% %%      {{ hol [[nec1 .. necn]] }}
-%% %%      {{ lem [[nec1 .. necn]] }}
-%% %%    | S_N1 union .. union S_Nn                   :: M :: SN_union
-%% %%      {{ hol (FLAT [[S_N1..S_Nn]]) }}
-%% %%      {{ lem (List.flatten [[S_N1..S_Nn]]) }}
-%% %%      {{ ocaml assert false }}
-%% %% 
-%% %% 
-%% %% E :: '' ::=                                                     {{ phantom }}
-%% %%                                                                 {{ hol ((string,env_body) fmaptree) }}
-%% %% 
-%% %% 
-%% %% %TODO: simplify by removing E_m throughout?  And E_p??
-%% %%                                                                 {{ lem env }}
-%% %%   {{ com Environments }}
-%% %%   | < E_m , E_p , E_f , E_x >                                           :: :: E
-%% %%     {{ hol (FTNode <|env_p:=[[E_p]]; env_f:=[[E_f]]; env_v:=[[E_x]]|> ([[E_m]])) }}
-%% %%     {{ lem (Env [[E_m]] [[E_p]] [[E_f]] [[E_x]]) }}
-%% %%   | E1 u+ E2                                                    :: M :: E_union
-%% %%     {{ hol (env_union [[E1]] [[E2]]) }}
-%% %%     {{ lem (env_union [[E1]] [[E2]]) }}
-%% %%     {{ ocaml assert false }}
-%% %%   | empty                                                       :: M :: E_empty
-%% %%     {{ hol (FTNode <|env_p:=FEMPTY; env_f:=FEMPTY; env_v:=FEMPTY|> FEMPTY) }}
-%% %%     {{ lem EnvEmp }}
-%% %%     {{ ocaml assert false }}
-%% %% 
-%% %% E_x {{ tex \ottnt{E}^{\textsc{x} } }} :: 'E_x_' ::=             {{ phantom }}
-%% %%                                                                 {{ hol (x|-> v_desc) }}
-%% %%                                                                 {{ lem map x v_desc }}
-%% %%   {{ com Value environments }}
-%% %%   | { x1 |-> v_desc1 , .. , xn |-> v_descn }    :: :: concrete
-%% %%     {{ hol (FOLDR (\(k1,k2) E. E |+ (k1,k2)) FEMPTY [[x1 v_desc1 .. xn v_descn]]) }}
-%% %%     {{ lem (List.fold_right (fun (x,v) m -> Pmap.add x v m) [[x1 v_desc1 .. xn v_descn]] Pmap.empty) }} 
-%% %%   | E_x1 u+ .. u+ E_xn                                          :: M :: union
-%% %%     {{ hol (FOLDR FUNION FEMPTY [[E_x1..E_xn]]) }}
-%% %%     {{ lem (List.fold_right union_map [[E_x1..E_xn]] Pmap.empty) }}
-%% %%     {{ ocaml (assert false) }}
-%% %% 
-%% %% E_f {{ tex \ottnt{E}^{\textsc{f} } }} :: 'E_f_' ::=             {{ phantom }}
-%% %%                                                                 {{ hol (x |-> f_desc) }}
-%% %%                                                                 {{ lem map x f_desc }}
-%% %%   {{ com Field environments }}
-%% %%   | { x1 |-> f_desc1 , .. , xn |-> f_descn }                    :: :: concrete
-%% %%     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 f_desc1 .. xn f_descn]]) }}
-%% %%     {{ lem (List.fold_right (fun (x,f) m -> Pmap.add x f m) [[x1 f_desc1 .. xn f_descn]] Pmap.empty) }} 
-%% %%   | E_f1 u+ .. u+ E_fn                                          :: M :: union
-%% %%     {{ hol (FOLDR FUNION FEMPTY [[E_f1..E_fn]]) }}
-%% %%     {{ lem (List.fold_right union_map [[E_f1..E_fn]] Pmap.empty) }}
-%% %%     {{ ocaml (assert false) }}
-%% %% 
-%% %% E_m {{ tex \ottnt{E}^{\textsc{m} } }} :: 'E_m_' ::=             {{ phantom }}
-%% %%                                                                 {{ hol (string |-> (string,env_body) fmaptree) }}
-%% %%                                                                 {{ lem map x env }} 
-%% %% %  {{ com Module environments }}
-%% %% %  | { x1 |-> E1 , .. , xn |-> En }                             :: :: concrete
-%% %% %    {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 E1 .. xn En]]) }}
-%% %% %    {{ lem (List.fold_right (fun (x,e) m -> Pmap.add x e m) [[x1 E1 .. xn En]] Pmap.empty) }} 
-%% %% % 
-%% %% % _p {{ tex \ottnt{E}^{\textsc{p} } }} :: 'E_p_' ::=            {{ phantom }}
-%% %% %                                                               {{ hol (x |-> p) }}
-%% %% %                                                               {{ lem map x p }}
-%% %% %  {{ com Path environments }}
-%% %% %  | { x1 |-> p1 , .. , xn |-> pn }                             :: :: concrete
-%% %% %    {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 p1 .. xn pn]]) }}
-%% %% %    {{ lem (List.fold_right (fun (x,p) m -> Pmap.add x p m) [[x1 p1 .. xn pn]] Pmap.empty) }} 
-%% %% %  | E_p1 u+ .. u+ E_pn                                         :: M :: union
-%% %% %    {{ hol (FOLDR FUNION FEMPTY [[E_p1..E_pn]]) }}
-%% %% %    {{ lem (List.fold_right union_map [[E_p1..E_pn]] Pmap.empty) }}
-%% %% % 
-%% %% %    {{ ocaml (assert false) }}
-%% %%  E_l {{ tex \ottnt{E}^{\textsc{l} } }} :: 'E_l_' ::=            {{ phantom }}
-%% %%                                                                 {{ hol (x |-> t) }}
-%% %%                                                                 {{ lem map x t }}
-%% %%   {{ com Lexical bindings }}
-%% %%   | { x1 |-> t1 , .. , xn |-> tn }                              :: :: concrete
-%% %%     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[x1 t1 .. xn tn]]) }}
-%% %%     {{ lem (List.fold_right (fun (x,t) m -> Pmap.add x t m) [[x1 t1 .. xn tn]] Pmap.empty) }} 
-%% %%   | E_l1 u+ .. u+ E_ln                                          :: M :: union
-%% %%     {{ hol (FOLDR FUNION FEMPTY [[E_l1..E_ln]]) }}
-%% %%     {{ lem (List.fold_right union_map [[E_l1..E_ln]] Pmap.empty) }}
-%% %%    {{ ocaml (assert false) }}
-%% %% 
-%% %% tc_abbrev :: 'Tc_abbrev_' ::=                                   {{ phantom }}
-%% %%                                                                 {{ hol t option }}
-%% %%                                                                 {{ lem option t }}
-%% %%                                                                 {{ ocaml t option }}
-%% %%   {{ com Type abbreviations }}
-%% %%   | . t                                                         :: :: some
-%% %%     {{ hol (SOME [[t]]) }}
-%% %%     {{ lem (Some [[t]]) }}
-%% %%   |                                                             :: :: none
-%% %%     {{ hol NONE }}
-%% %%     {{ lem None }}
-%% %% 
-%% %% tc_def :: '' ::=
-%% %%   {{ com Type and class constructor definitions }} 
-%% %%   | tnvs tc_abbrev                                              :: :: Tc_def
-%% %%     {{ com Type constructors }}
-%% %% 
-%% %% TD {{ tex \ensuremath{\Delta} }} :: 'TD_' ::=                   {{ phantom }}
-%% %%                                                                 {{ hol p |-> tc_def }}
-%% %%                                                                 {{ lem map p tc_def }}
-%% %%   {{ com Type constructor definitions }}
-%% %%   | { p1 |-> tc_def1 , .. , pn |-> tc_defn }                    :: :: concrete
-%% %%     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[p1 tc_def1 .. pn tc_defn]]) }}
-%% %%     {{ lem (List.fold_right (fun (p,t) m -> Pmap.add p t m) [[p1 tc_def1 .. pn tc_defn]] Pmap.empty) }} 
-%% %%     {{ ocaml (assert false) }}
-%% %%   | TD1 u+ TD2                                                  :: M :: union
-%% %%     {{ hol (FUNION [[TD1]] [[TD2]]) }}
-%% %%     {{ lem (union_map [[TD1]] [[TD2]]) }}
-%% %%     {{ ocaml (assert false) }}
-%% %% 
-%% %% 
-%% %% 
-%% %% D :: 'D_' ::=                                                   {{ phantom }}
-%% %%                                                                 {{ hol ((p |-> tc_def) # (p |-> x list) # (inst list)) }}
-%% %%                                                                 {{ lem tdefs}}
-%% %%   {{ com Global type definition store }}
-%% %%   | < TD , TC , I >                                                     :: :: concrete
-%% %%     {{ hol ([[TD]], [[TC]], [[I]]) }}
-%% %%     {{ lem (D [[TD]] [[TC]] [[I]]) }}
-%% %%   | D1 u+ D2                                                    :: M :: union
-%% %%     {{ hol (case ([[D1]],[[D2]]) of ((x1,x2,x3),(y1,y2,y3)) => (FUNION x1 y1, FUNION x2 y2, x3 ++ y3)) }}
-%% %%     {{ lem (union_tcdefs [[D1]] [[D2]]) }}
-%% %%     {{ ocaml (assert false) }}
-%% %%   | empty                                                       :: M :: empty
-%% %%     {{ hol (FEMPTY, FEMPTY, []) }}
-%% %%     {{ lem DEmp }}
-%% %%     {{ ocaml assert false }}
-%% %% 
-%% %% parsing
-%% %% E_union left E_union
-%% %% 
-%% %% embed
-%% %% {{ lem
-%% %% type tdefs =
-%% %%   | DEmp
-%% %%   | D of (map p tc_def) * (map p (list x)) * (set inst)
-%% %% 
-%% %% val union_tcdefs : tdefs -> tdefs -> tdefs
-%% %% 
-%% %% }}
-
-grammar
-
-terminals :: '' ::=
-  | **                                  :: :: starstar
-    {{ tex \ensuremath{\mathop{\mathord{*}\mathord{*} } } }}
-    {{ com \texttt{**} }}
-  | >=                                  :: :: geq
-    {{ tex \ensuremath{\geq} }}
-    {{ com \texttt{>=} }}
-  | '<='                                        :: :: leq
-    {{ tex \ensuremath{\leq} }}
-    {{ com \texttt{<=} }}
-  | ->                                  :: :: arrow
-    {{ tex \ensuremath{\rightarrow} }}
-    {{ com \texttt{->} }}
-  | ==>                                 :: :: Longrightarrow
-    {{ tex \ensuremath{\Longrightarrow} }}
-    {{ com \texttt{==>} }}
-  | <|                                  :: :: startrec
-    {{ tex \ensuremath{\langle|} }}
-    {{ com \texttt{<|} }}
-  | |>                                  :: :: endrec
-    {{ tex \ensuremath{|\rangle} }}
-    {{ com \texttt{|>} }}
-  | inter                               :: :: inter
-    {{ tex \ensuremath{\cap} }}
-%  | union                               :: :: union
-%    {{ tex \ensuremath{\cup} }}
-  | u+                                  :: :: uplus
-    {{ tex \ensuremath{\uplus} }}
-  | NOTIN                               :: :: notin
-    {{ tex \ensuremath{\not\in} }}
-  | SUBSET                              :: :: subset
-    {{ tex \ensuremath{\subset} }}
-  | NOTEQ                               :: :: noteq
-    {{ tex \ensuremath{\not=} }}
-  | emptyset                            :: :: emptyset
-    {{ tex \ensuremath{\emptyset} }}
-  | <                                   :: :: lt
-    {{ tex \ensuremath{\langle} }}
-  | >                                   :: :: gt
-    {{ tex \ensuremath{\rangle} }}
-  | |-                                  :: :: vdash
-    {{ tex \ensuremath{\vdash} }}
-  | '                                   :: :: quote
-    {{ tex \mbox{'} }}
-  | |->                                 :: :: mapsto
-    {{ tex \ensuremath{\mapsto} }}
-  | gives                               :: :: gives
-    {{ tex \ensuremath{\triangleright} }}
-  | ~>                                  :: :: leadsto
-    {{ tex \ensuremath{\leadsto} }}
-  | =>                                  :: :: Rightarrow
-    {{ tex \ensuremath{\Rightarrow} }}
-  | --                                  :: :: dashdash
-    {{ tex \mbox{--} }}
-  | empty                               :: :: empty
-    {{ tex \ensuremath{\epsilon} }}
-  | effectkw			        :: :: effectkw
-    {{ tex \ottkw{effect} }}
- 
-
-formula :: formula_ ::=
-  | judgement                                                   :: :: judgement
-
-  | formula1 .. formulan                                        :: :: dots
-
-%   | E_m ( x ) gives E                                         :: :: lookup_m
-%     {{ com Module lookup }}
-%     {{ hol (FLOOKUP [[E_m]] [[x]] = SOME [[E]]) }}
-%     {{ lem (Pmap.find [[x]] [[E_m]]) = [[E]] }} 
-% 
-%   | E_p ( x ) gives p                                         :: :: lookup_p
-%     {{ com Path lookup }}
-%     {{ hol (FLOOKUP [[E_p]] [[x]] = SOME [[p]]) }}
-%     {{ lem Pmap.find [[x]] [[E_p]] = [[p]] }} 
-
-%% %%   | E_f ( x ) gives f_desc                                      :: :: lookup_f
-%% %%     {{ com Field lookup }}
-%% %%     {{ hol (FLOOKUP [[E_f]] [[x]] = SOME [[f_desc]]) }}
-%% %%     {{ lem Pmap.find [[x]] [[E_f]] = [[f_desc]] }} 
-%% %% 
-%% %%   | E_x ( x ) gives v_desc                                      :: :: lookup_v
-%% %%     {{ com Value lookup }}
-%% %%     {{ hol (FLOOKUP [[E_x]] [[x]] = SOME [[v_desc]]) }}
-%% %%     {{ lem Pmap.find [[x]] [[E_x]] = [[v_desc]] }} 
-%% %% 
-%% %%   | E_l ( x ) gives t                                           :: :: lookup_l
-%% %%     {{ com Lexical binding lookup }}
-%% %%     {{ hol (FLOOKUP [[E_l]] [[x]] = SOME [[t]]) }}
-%% %%     {{ lem Pmap.find [[x]] [[E_l]] = [[t]] }} 
-%% %% 
-%% %% %   | TD ( p ) gives tc_def                                     :: :: lookup_tc
-%% %% %     {{ com Type constructor lookup }}
-%% %% %     {{ hol (FLOOKUP [[TD]] [[p]] = SOME [[tc_def]]) }}
-%% %% %     {{ lem Pmap.find [[p]] [[TD]] = [[tc_def]] }} 
-%% %% % 
-%% %% %   | TC ( p ) gives xs                                         :: :: lookup_class
-%% %% %     {{ com Type constructor lookup }}
-%% %% %     {{ hol (FLOOKUP [[TC]] [[p]] = SOME [[xs]]) }}
-%% %% %     {{ lem Pmap.find [[p]] [[TC]] = [[xs]] }} 
-%% %% 
-%% %%   | dom ( E_m1 ) inter dom ( E_m2 ) = emptyset                  :: :: E_m_disjoint
-%% %%     {{ hol (DISJOINT (FDOM [[E_m1]]) (FDOM [[E_m2]])) }}
-%% %%     {{ lem disjoint (Pmap.domain [[E_m1]]) (Pmap.domain [[E_m2]]) }} 
-%% %% 
-%% %%   | dom ( E_x1 ) inter dom ( E_x2 ) = emptyset                  :: :: E_x_disjoint
-%% %%     {{ hol (DISJOINT (FDOM [[E_x1]]) (FDOM [[E_x2]])) }}
-%% %%     {{ lem disjoint (Pmap.domain [[E_x1]]) (Pmap.domain [[E_x2]])  }} 
-%% %%     
-%% %%   | dom ( E_f1 ) inter dom ( E_f2 ) = emptyset                  :: :: E_f_disjoint
-%% %%     {{ hol (DISJOINT (FDOM [[E_f1]]) (FDOM [[E_f2]])) }}
-%% %%     {{ lem disjoint (Pmap.domain [[E_f1]]) (Pmap.domain [[E_f2]]) }} 
-%% %% 
-%% %% %   | dom ( E_p1 ) inter dom ( E_p2 ) = emptyset                        :: :: E_p_disjoint
-%% %% %     {{ hol (DISJOINT (FDOM [[E_p1]]) (FDOM [[E_p2]])) }}
-%% %% %     {{ lem disjoint (Pmap.domain [[E_p1]]) (Pmap.domain [[E_p2]]) }} 
-%% %% % 
-%% %%   | disjoint doms ( E_l1 , .... , E_ln )                        :: :: E_l_disjoint
-%% %%     {{ hol (FOLDR (\E b. case b of NONE => NONE | SOME s => if DISJOINT (FDOM
-%% %% E) s then SOME (FDOM E UNION s) else NONE) (SOME {}) [[E_l1....E_ln]] <> NONE) }}
-%% %%     {{ lem disjoint_all (List.map Pmap.domain [[E_l1 .... E_ln]]) }}
-%% %%     {{ com Pairwise disjoint domains }}
-%% %% 
-%% %%   | disjoint doms ( E_x1 , .... , E_xn )                        :: :: E_x_disjoint_many
-%% %%     {{ hol (FOLDR (\E b. case b of NONE => NONE | SOME s => if DISJOINT (FDOM
-%% %% E) s then SOME (FDOM E UNION s) else NONE) (SOME {}) [[E_x1....E_xn]] <> NONE) }}
-%% %%     {{ lem disjoint_all (List.map Pmap.domain [[E_x1 .... E_xn]]) }}
-%% %%     {{ com Pairwise disjoint domains }}
-%% %% 
-%% %%   | compatible overlap ( x1 |-> t1 , .. , xn |-> tn )           :: :: E_l_compat
-%% %%     {{ hol (!__n __m. MEM __m [[x1 t1 .. xn tn]] /\ MEM __n [[x1 t1..xn tn]] /\ (FST __m  = FST __n) ==> (SND __m = SND __n)) }}
-%% %%     {{ lem (compatible_overlap [[x1 t1 .. xn tn]]) }} 
-%% %%     {{ com $(\ottnt{x}_i = \ottnt{x}_j) \ensuremath{\Longrightarrow} (\ottnt{t}_i = \ottnt{t}_j)$ }}
-%% %% 
-%% %%   | duplicates ( tnvs ) = emptyset                              :: :: no_dups_tnvs
-%% %%     {{ hol (ALL_DISTINCT [[tnvs]]) }}
-%% %%     {{ lem (duplicates [[tnvs]]) = [ ] }} 
-%% %% 
-%% %%   | duplicates ( x1 , .. , xn ) = emptyset                      :: :: no_dups
-%% %%     {{ hol (ALL_DISTINCT [[x1..xn]]) }}
-%% %%     {{ lem (duplicates [[x1..xn]]) = [ ] }} 
-%% %% 
-%% %%   | x NOTIN dom ( E_l )                                         :: :: notin_dom_l
-%% %%     {{ hol ([[x]] NOTIN FDOM [[E_l]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[x]] [[E_l]]) }} 
-%% %% 
-%% %%   | x NOTIN dom ( E_x )                                         :: :: notin_dom_v
-%% %%     {{ hol ([[x]] NOTIN FDOM [[E_x]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[x]] [[E_x]]) }} 
-%% %% 
-%% %%   | x NOTIN dom ( E_f )                                         :: :: notin_dom_f
-%% %%     {{ hol ([[x]] NOTIN FDOM [[E_f]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[x]] [[E_f]]) }} 
-%% %% 
-%% %% %   | p NOTIN dom ( TC )                                                :: :: notin_dom_tc
-%% %% %     {{ hol ([[p]] NOTIN FDOM [[TC]]) }}
-%% %% %     {{ lem Pervasives.not (Pmap.mem [[p]] [[TC]]) }} 
-%% %% 
-%% %%   | p NOTIN dom ( TD )                                          :: :: notin_dom_td
-%% %%     {{ hol ([[p]] NOTIN FDOM [[TD]]) }}
-%% %%     {{ lem Pervasives.not (Pmap.mem [[p]] [[TD]]) }} 
-%% %% 
-%% %%   | FV ( t ) SUBSET tnvs                                                :: :: FV_t
-%% %%     {{ com Free type variables }}
-%% %%     {{ hol (LIST_TO_SET (ftv_t [[t]]) SUBSET LIST_TO_SET [[tnvs]]) }}
-%% %%     {{ lem subst (ftv_t [[t]]) [[tnvs]]  }} 
-%% %% 
-%% %%   | FV ( t_multi ) SUBSET tnvs                                  :: :: FV_t_multi
-%% %%     {{ com Free type variables }}
-%% %%     {{ hol (LIST_TO_SET (FLAT (MAP ftv_t [[t_multi]])) SUBSET LIST_TO_SET [[tnvs]]) }}
-%% %%     {{ lem subst (ftv_tm [[t_multi]]) [[tnvs]]  }} 
-%% %% 
-%% %%   | FV ( semC ) SUBSET tnvs                                     :: :: FV_semC
-%% %%     {{ com Free type variables }}
-%% %%     {{ hol (LIST_TO_SET (MAP SND [[semC]]) SUBSET LIST_TO_SET [[tnvs]]) }}
-%% %%     {{ lem subst (ftv_s [[semC]]) [[tnvs]] }} 
-%% %% 
-%% %%   | inst 'IN' I                                                 :: :: inst_in
-%% %%     {{ hol (MEM [[inst]] [[I]]) }}
-%% %%     {{ lem ([[inst]] IN [[I]]) }}
-%% %% 
-%% %%   | ( p t ) NOTIN I                                             :: :: notin_I
-%% %%     {{ hol (~?__semC__. MEM (Inst __semC__ [[p]] [[t]]) [[I]]) }}
-%% %%     {{ lem (Pervasives.not ((Inst [] [[p]] [[t]]) IN [[I]])) }}
-%% %% 
-%% %%   | E_l1 = E_l2                                                 :: :: E_l_eqn
-%% %%     {{ ichl ([[E_l1]] = [[E_l2]]) }}
-%% %% 
-%% %%   | E_x1 = E_x2                                                 :: :: E_x_eqn
-%% %%     {{ ichl ([[E_x1]] = [[E_x2]]) }}
-%% %% 
-%% %%   | E_f1 = E_f2                                                 :: :: E_f_eqn
-%% %%     {{ ichl ([[E_f1]] = [[E_f2]]) }}
-%% %% 
-%% %%   | E1 = E2                                                     :: :: E_eqn
-%% %%     {{ ichl ([[E1]] = [[E2]]) }}
-%% %% 
-%% %%   | TD1 = TD2                                                   :: :: TD_eqn
-%% %%     {{ ichl ([[TD1]] = [[TD2]]) }}
-%% %% 
-%% %%   | TC1 = TC2                                                   :: :: TC_eqn
-%% %%     {{ ichl ([[TC1]] = [[TC2]]) }}
-%% %% 
-%% %%   | I1 = I2                                                     :: :: I_eqn
-%% %%     {{ ichl ([[I1]] = [[I2]]) }}
-%% %% 
-%% %%   | names1 = names2                                             :: :: names_eq
-%% %%     {{ ichl ([[names1]] = [[names2]]) }}
-%% %% 
-%% %%   | t1 = t2                                                     :: :: t_eq
-%% %%     {{ ichl ([[t1]] = [[t2]]) }}
-%% %% 
-%% %%   | t_subst1 = t_subst2                                         :: :: t_subst_eq
-%% %%     {{ ichl ([[t_subst1]] = [[t_subst2]]) }}
-%% %% 
-%% %%   | p1 = p2                                                     :: :: p_eq
-%% %%     {{ ichl ([[p1]] = [[p2]]) }}
-%% %% 
-%% %%   | xs1 = xs2                                                   :: :: xs_eq
-%% %%     {{ ichl ([[xs1]] = [[xs2]]) }}
-%% %% 
-%% %%   | tnvs1 = tnvs2                                                       :: :: tnvs_eq
-%% %%     {{ ichl ([[tnvs1]] = [[tnvs2]]) }}
-
diff --git a/language/l2_rules.ott b/language/l2_rules.ott
deleted file mode 100644
index 9e1b79fb..00000000
--- a/language/l2_rules.ott
+++ /dev/null
@@ -1,424 +0,0 @@
-
-
-grammar
-
-mut :: 'mut_' ::=
-  |  immutable :: :: immutable
-  |  mutable :: :: mutable
-
-lvar :: 'lvar_' ::=
-  | register typ :: :: register
-  | enum typ     :: :: enum
-  | local mut typ :: :: local
-  | union typquant typ :: :: union
-  | unbound :: :: unbound
-  
-
-
-G {{ tex \Gamma }}, D {{ tex \Delta }} :: 'G_' ::=  {{ com Type environment }} 
-   | empty                              :: :: empty {{ tex \epsilon }} {{ com Empty context }}
-   | G , x1 : typ1 , .. , xn : typn     :: :: type_list  {{ com List of variables and their types }}
-%   | G , x1 : k1 , .. , xn : kn         :: :: kind_list  {{ com List of variables and their kinds }}
-   | G , kid1 , .. , kidn               :: :: kid_list
-%   | G , quant_item1 , .. , quant_itemn :: :: quant_list
-%   | G , { nec1 , .. , necn }           :: :: constraint_list {{ com Constraints }}
-   | G , G1 .. Gn                       :: :: merge {{ com Merge or disjoint union }}
-   | G , id : lvar                       :: :: add_local
-
-
-formula :: formula_ ::=
-  | judgement                                                   :: :: judgement
-  | formula1 .. formulan                                        :: :: dots
-  | G ( id ) = lvar                                             :: :: lookup_id
-  | G ( typ1 , id ) = typ2                                      :: :: lookup_record_field
-  | G ( typ1 ) = typ2                                           :: :: lookup_typ
-  |  nexp = length [|| exp , exp1 , .. , expn ||]               :: :: vector_length
-  | order_inc                                                   :: :: default_order_inc
-  | order_dec                                                   :: :: default_order_dec
-  |  G |= nexp1 <= nexp2  :: :: prove_lteq
-
-defns
-  declarative :: '' ::=
-
-defn
- G |- typ1  ~< typ2   :: :: subtype :: subtype_
- {{ com $[[typ1]]$ is a subtype of $[[typ2]]$  }}
- {{ tex [[G]] \vdash [[typ1]]  \preccurlyeq [[typ2]] }}
-by
-
-
------------------ :: refl
-G |- typ ~< typ
-
---------------------- :: wild
-G |- _ ~< _
-
-
-
-------------- :: id
-G |- id ~< id
-
-G |- typ1 ~< typ'1 .. G |- typn ~< typ'n
---------------------------------------------------- :: tuple
-G |- (typ1 , .. , typn ) ~< (typ'1, .. , typ'n)
-
-
-defn
-G |-l lit => typ  :: :: infer_lit :: infer_lit_
-{{ com Infer that type of $[[lit]]$ is $[[typ]]$ }}
-{{ tex [[G]] \vdash_l [[lit]] \Rightarrow [[typ]] }}
-by
-
-
------------------------------ :: unit
-G |-l () => unit
-
--------------------- :: zero
-G |-l bitzero => bit
-
--------------------- :: one
-G |-l bitone => bit
-
-
----------------------- :: num
-G |-l num => atom < num >
-
-
----------------------- :: true
-G |-l true => bool
-
-
----------------------- :: false
-G |-l false => bool
-
-defn
-G |- lexp := exp => typ -| D :: :: bind_assignment :: bind_assignment_
-{{ com Bind assignment returning updated environment  }}
-{{ tex [[G]] \vdash [[lexp]] := [[exp]] \Rightarrow [[typ]] \dashv [[D]] }}
-by
-
-
-G |- exp => typ
-G |- id <= typ -| D
-------------------------------- :: id
-G |- id := exp => unit -| D
-
-defn
-G |- pat <= typ -| D :: :: bind_pat :: bind_pat_
-{{ tex [[G]] \vdash [[pat]] \Leftarrow [[typ]] \dashv [[D]] }}
-by
-
-G |- lit <= typ
--------------------     :: lit
-G |- lit <= typ -| G
-
-%% FIXME do add_local
-G(id) = local mutable typ'
----------------------- :: local
-G |- id <= typ -| G
-
-G(id) = unbound
----------------------- :: unbound
-G |- id <= typ -| G
-
-
-G(id) = enum typ'
-G |- typ' ~< typ
----------------------- :: enum
-G |- id <= typ -| G
-
-
----------------------- :: wild
-G |- _ <= typ -| G
-
-
-%% FIXME Should be fold?
-G |- pat1 <= typ1 -| G1 .. G |- patn <= typn -| Gn
-------------------------------------------------------- :: tup
-G |- (pat1 , .. , patn ) <= (typ1 , .. , typn ) -| G , G1 .. Gn
-
-
-
-defn
-G |- pat => typ -| D :: :: infer_pat :: infer_pat_
-{{ tex [[G]] \vdash [[pat]] \Leftarrow [[typ]] \dashv [[D]] }}
-by
-
-G(id) = enum typ 
--------------------- ::  id
-G |- id => typ -| G
-
-
-G |- pat <= typ -| D
-------------------------------- :: typ
-G |- (typ) pat => typ -| D
-
-
-G |-l lit => typ
------------------------  :: lit
-G |- lit => typ -| G
-
-
-defn
-G |-i id => typ :: :: infer_id :: infer_id_
-{{ com Infer type of indentifier }}
-{{ tex [[G]] \vdash_i [[id]] \Rightarrow [[typ]] }}
-by
-
-
-G(id) = local mut typ
----------------------- :: local
-G |-i id => typ
-
-
-G(id) = enum typ
----------------------- :: enum
-G |-i id => typ
-
-
-G(id) = register typ
----------------------- :: register
-G |-i id => typ
-
-
-G(id) = union typquant typ
-------------------------------------- :: union
-G |-i id => typ
-
-defn
-G |-f exp . id => typ :: :: infer_field :: infer_field_
-{{ tex [[G]] \vdash_f [[exp]] . [[id]] \Rightarrow [[typ]] }}
-by
-
-
-G |- exp => typ1
-G ( typ1 ) = register [ id2 ]
-G ( id2 ) = (base,top,ranges)
-ranges ( id ) = vec_typ
----------------------------- :: register
-G |-f exp . id => vec_typ
-
-
-
-G |- exp => typ1
-G ( typ1 , id ) = typ
----------------------------- :: record
-G |-f exp . id => typ
-
-
-defn
-G |- exp1 => n_constraint :: :: infer_flow :: infer_flow_
-by
-
-
-G |- x => atom < nexp1 >
-G |- y => atom < nexp2 >
----------------------------- :: lteq
-G |- :E_app: lteq_atom_atom ( x , y ) =>  nexp1 <= nexp2
-
-
-G |- x => atom < nexp1 >
-G |- y => atom < nexp2 >
----------------------------- :: gteq
-G |- :E_app: gteq_atom_atom ( x , y ) =>  nexp1 >= nexp2
-
-G |- x => atom < nexp1 >
-G |- y => atom < nexp2 >
----------------------------- :: lt
-G |- :E_app: lt_atom_atom ( x , y ) =>  nexp1 + numOne <= nexp2
-
-G |- x => atom < nexp1 >
-G |- y => atom < nexp2 >
----------------------------- :: gt
-G |- :E_app: lteq_atom_atom ( x , y ) =>  nexp1 >= nexp2 + numOne
-
-
-G |- id => range <nexp1 , nexp2 >
-G |- y => atom < nexp >
-------------------------------------------------------------------------------- :: lt_range_atom
-G |- :E_app: lt_range_atom ( id , y ) => range < nexp1 , min (nexp - 1 , nexp2 ) >
-
-
-
-
-defn
- G |- exp => typ :: :: infer_exp :: infer_exp_
-{{ com Infer that type of $[[exp]]$ is $[[typ]]$ }}
-{{ tex [[G]] \vdash [[exp]] \Rightarrow [[typ]]  }}
-by
-
-
-G |- exp1 <= unit ... G |- expn <= unit
------------------------------------------- :: nondet
-G |- nondet { exp1 ; ... ; expn } => unit
-
-
-G |-i id => typ
----------------- :: id
-G |- id => typ
-
-
-G |-l lit => typ
----------------- :: lit
-G |- lit => typ
-
-
------------------------------------ :: sizeof
-G |- sizeof nexp => atom < nexp >
-
-
--------------------------------------------- :: constraint
-G |- constraint n_constraint => bool
-
-G |-f exp . id => typ
------------------------- :: field
-G |- exp . id => typ
-
-
-G |- exp1 => typ1 .... G |- expn => typn
----------------------------------------------------------- :: tuple
-G |- ( exp1 , .... , expn ) => (typ1 , .... , typn )
-
-
-
-
-G |- lexp := exp => typ -| D
--------------------- :: assign
-G |- lexp := exp => typ
-
-
-
----------------------------- :: record_update
-G |- lexp . id := exp => typ
-
-
-G |- exp <= typ
------------------------ :: cast
-G |- ( typ ) exp => typ
-
-
-
-G |- :E_app: id ( exp1 , exp2 ) => typ
--------------------------------- :: app_infix
-G |- exp1 id exp2 => typ
-
-
---------------------------------------- :: app
-G |- :E_app: id (exp1 , .. , expn ) => typ
-
-
-
-G |- exp1 => bool
-G |- exp2 => unit
-------------------------------- :: while_loop
-G |- while exp1 do exp2 => unit
-
-G |- exp1 => unit
-G |- exp2 => bool
-------------------------------- :: until_loop
-G |- repeat exp1 until exp2 => unit
-
-G |- exp1 => range <nexp1,nexp1'>
-G |- exp2 => range <nexp2,nexp2'>
-G |= nexp1' <= nexp2
-G |- exp3 <= int
-G |- exp4 => unit
------------------------------------------------------------------------ :: for_inc
-G |-  foreach ( id from exp1 to exp2 by exp3 in inc ) exp4 => unit
-
-G |- exp1 => range <nexp1,nexp1'>
-G |- exp2 => range <nexp2,nexp2'>
-G |= nexp2' <= nexp1
-G |- exp3 <= int
-G |- exp4 => unit
------------------------------------------------------------------------ :: for_dec
-G |-  foreach ( id from exp1 to exp2 by exp3 in dec ) exp4 => unit
-
-
-G |- foreach ( id from exp1 to exp2 by exp3 in inc) exp4 => typ
------------------------------------------------------------------------ :: forup
-G |- foreach ( id from exp1 to exp2 by exp3 ) exp4 => typ
-
-
-G |- foreach ( id from exp1 to exp2 by numOne in inc) exp3 => typ
------------------------------------------------------------------------ :: forupbyone
-G |- foreach ( id from exp1 to exp2 ) exp3 => typ
-
-
-G |- foreach ( id from exp1 to exp2 by exp3 in dec) exp4   => typ
---------------------------------------------------------------------------- :: fordown
-G |- foreach ( id from exp1 downto exp2 by exp3 ) exp4   => typ
-
-G |- foreach ( id from exp1 to exp2 by numOne in dec) exp3  => typ
-------------------------------------------------------------------------- :: fordownbyone
-G |- foreach ( id from exp1 downto exp2 ) exp3  => typ
-
-
-G |- exp1 => n_constraint
-%G , flows , constrs |- exp2 => typ
-%G , flows , negate constrs |- exp3 <= typ
--------------------------------------------- :: if
-G |- if exp1 then exp2 else exp3 => typ
-
-G |- :E_app: vector_access ( exp , exp' ) => typ
------------------------------- :: vector_access
-G |- exp [ exp' ] => typ
-
-
-G |- :E_app: vector_subrange ( exp , exp1 , exp2 ) => typ
---------------------------- :: vector_subrange
-G |- exp [ exp1 .. exp2 ] => typ
-
-
-G |- :E_app: vector_update ( exp , exp1 , exp2 ) => typ
----------------------------------- :: vector_update
-G |- :E_vector_update: [ exp with exp1 = exp2] => typ
-
-
-G |- :E_app: vector_update_subrange ( exp , exp1 , exp2 , exp3 ) => typ
------------------------------------------- ::  vector_update_subrange
-G |- :E_vector_update_subrange: [  exp with exp1 : exp2 = exp3 ] => typ
-
-
-G |- :E_app: vector_append ( exp1 , exp2 ) => typ
------------------------------------ ::   vector_append
-G |- exp1 : exp2  => typ
-
-
-order_inc
-G |- exp => typ
-G |- exp1 <= typ .. G |- expn <= typ
-nexp = length [|| exp , exp1 , .. , expn ||]
--------------------------------------------- :: vector_inc
-G |- [|| exp , exp1 , .. , expn ||] => typ [ numZero <: nexp ]
-
-order_dec
-G |- exp => typ
-G |- exp1 <= typ .. G |- expn <= typ
-nexp = length [|| exp , exp1 , .. , expn ||]
--------------------------------------------- :: vector_dec
-G |- [|| exp , exp1 , .. , expn ||] => typ [ nexp :> numZero ]
-
-
-G |- exp1 <= bool
-G |- exp2 <= string
------------------------------------ :: assert
-G |- assert (exp1, exp2 ) => unit
-
-
-defn
- G |- exp <= typ :: :: check_exp :: check_exp_
-{{ com Check that type of $[[exp]]$ is $[[typ]]$ }}
-{{ tex [[G]] \vdash [[exp]] \Leftarrow [[typ]]  }}
-by
-
-
-G |- exp1 <= unit ... G |- expn <= unit
-G |- exp <= typ
------------------------------------ :: block
-G |- { exp1; ... ; expn ; exp } <= typ
-
-
-
- 
-
diff --git a/language/l2_terminals_non_tt.ott b/language/l2_terminals_non_tt.ott
deleted file mode 100644
index 2c466b8b..00000000
--- a/language/l2_terminals_non_tt.ott
+++ /dev/null
@@ -1,31 +0,0 @@
-grammar 
-terminals :: '' ::=
-  | <                                   :: :: lt
-    {{ tex \ensuremath{\langle} }}
-%    {{ tex \ottsym{<} }}
-  | >                                   :: :: gt
-    {{ tex \ensuremath{\rangle} }}
-%    {{ tex \ottsym{>} }}
-
-%   | [| :: :: range_start
-%     {{ tex \mbox{$\ottsym{[\textbar}$} }}       
-%   | |] :: :: range_end       
-%     {{ tex \mbox{$\ottsym{\textbar]}$} }}       
-%   | [|| :: :: list_start
-%     {{ tex \mbox{$\ottsym{[\textbar\textbar}$} }}       
-%   | ||] :: :: list_end       
-%     {{ tex \mbox{$\ottsym{\textbar\textbar]}$} }}       
-
-  | ->                                  :: :: arrow
-    {{ tex \ensuremath{\rightarrow} }}
-%    {{ tex \ottsym{-\textgreater} }}
-    {{ com \texttt{->} }}
-
-  | >=                                  :: :: geq
-    {{ tex \ensuremath{\geq} }}
-%    {{ tex \ottsym{\textgreater=} }}
-    {{ com \texttt{>=} }}
-  | '<='                                        :: :: leq
-    {{ tex \ensuremath{\leq} }}
-%    {{ tex \ottsym{\textless=} }}
-    {{ com \texttt{<=} }}
diff --git a/language/l2_terminals_tt.ott b/language/l2_terminals_tt.ott
deleted file mode 100644
index c6bc8d34..00000000
--- a/language/l2_terminals_tt.ott
+++ /dev/null
@@ -1,31 +0,0 @@
-grammar 
-terminals :: '' ::=
-  | <                                   :: :: lt
-%    {{ tex \ensuremath{\langle} }}
-    {{ tex \ottsym{<} }}
-  | >                                   :: :: gt
-%    {{ tex \ensuremath{\rangle} }}
-    {{ tex \ottsym{>} }}
-
-  | [| :: :: range_start
-    {{ tex \mbox{$\ottsym{[\textbar}$} }}       
-  | |] :: :: range_end       
-    {{ tex \mbox{$\ottsym{\textbar]}$} }}       
-  | [|| :: :: list_start
-    {{ tex \mbox{$\ottsym{[\textbar\textbar}$} }}       
-  | ||] :: :: list_end       
-    {{ tex \mbox{$\ottsym{\textbar\textbar]}$} }}       
-
-  | ->                                  :: :: arrow
-%    {{ tex \ensuremath{\rightarrow} }}
-    {{ tex \ottsym{-\textgreater} }}
-    {{ com \texttt{->} }}
-
-  | >=                                  :: :: geq
-%    {{ tex \ensuremath{\geq} }}
-    {{ tex \ottsym{\textgreater=} }}
-    {{ com \texttt{>=} }}
-  | '<='                                        :: :: leq
-%    {{ tex \ensuremath{\leq} }}
-    {{ tex \ottsym{\textless=} }}
-    {{ com \texttt{<=} }}
diff --git a/language/l2_typ.ott b/language/l2_typ.ott
deleted file mode 100644
index 43077d60..00000000
--- a/language/l2_typ.ott
+++ /dev/null
@@ -1,382 +0,0 @@
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Machinery for typing rules                                   %
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-embed
-{{ lem
-
-let rec remove_one i l =
-  match l with
-  | [] -> []
-  | i2::l2 -> if i2 = i then l2 else i2::(remove_one i l2)
-end
-
-let rec remove_from l l2 =
-  match l2 with 
-  | [] -> l
-  | i::l2' -> remove_from (remove_one i l) l2'
-end
-
-let disjoint s1 s2 = Set.null (s1 inter s2)
-
-let rec disjoint_all sets =
-  match sets with
-  | [] -> true
-  | s1::[] -> true
-  | s1::s2::sets -> (disjoint s1 s2) && (disjoint_all (s2::sets))
-end
-}}
-
- 
-grammar 
-
-k :: 'Ki_' ::=
-{{ com Internal kinds }}
-   | K_Typ                                             :: :: typ
-   | K_Nat                                             :: :: nat
-   | K_Ord                                             :: :: ord
-   | K_Efct                                             :: :: efct
-   | K_Lam ( k0 .. kn -> k' )                  :: :: ctor
-   | K_infer                                           :: :: infer {{ com Representing an unknown kind, inferred by context }}
-
-t , u :: 'T_' ::=                                
-{{ com Internal types }}
-   | x                                            :: :: id
-   | ' x                                          :: :: var
-   | t1 -> t2 effect                        :: :: fn 
-   | ( t1 , .... , tn )                           :: :: tup
-   | x < t_args >                           :: :: app 
-   | t |-> t1                                   :: :: abbrev
-   | register < t_arg >                  :: S :: reg_app {{ ichlo T_app "register" [[t_arg]] }}
-   | range < ne ne' > 			  :: S :: range_app {{ ichlo T_app "range" [[ [ ne ; ne' ] ]] }}
-   | atom < ne >    			  :: S :: atom_app {{ ichlo T_app "atom" [ [[ne]] ] }}
-   | vector < ne ne' order t >           :: S :: vector_app {{ ichlo T_app "vector" [[ [ ne; ne'; ord; t ] ]] }} 
-   | list < t >      	     		 :: S :: list_app {{ ichlo T_app "list" [[t]] }}
-   | reg < t >				 :: S :: box_app {{ ichlo T_app "reg" [[t]] }}
-   | implicit < ne >                      :: S :: implicit_app {{ ichlo T_app "implicit" [[ne]] }}
-   | bit      	     	   	       	          :: S :: bit_typ {{ ichlo T_id "bit" }}
-   | string                                    :: S :: string_typ {{ ichlo T_id "string" }}
-   | unit                                       :: S :: unit_typ {{ ichlo T_id "unit" }} 
-   | t [ t_arg1 / tid1 .. t_argn / tidn ]  :: M :: subst {{ ichlo "todo" }}
-
-optx :: '' ::= {{ phantom }} {{ lem maybe string }} {{ ocaml string option }}
-  | x                                            ::  :: optx_x
-  {{ lem (Just [[x]]) }} {{ ocaml (Some [[x]]) }}
-  |                                              :: :: optx_none
-  {{ lem Nothing }} {{ ocaml None }}
-
-
-tag :: 'Tag_' ::=                                 
-{{ com Data indicating where the identifier arises and thus information necessary in compilation }}
-   | None                                 :: :: empty
-   | Intro                                :: :: intro {{ com Denotes an assignment and lexp that introduces a binding }}
-   | Set                                  :: :: set {{ com Denotes an expression that mutates a local variable }}
-   | Tuple                                :: :: tuple_assign {{ com Denotes an assignment with a tuple lexp }}
-   | Global				  :: :: global {{ com Globally let-bound or enumeration based value/variable }} 
-   | Ctor                                 :: :: ctor {{ com Data constructor from a type union }}
-   | Extern optx                          :: :: extern {{ com External function, specied only with a val statement }}
-   | Default                              :: :: default {{ com Type has come from default declaration, identifier may not be bound locally }}
-   | Spec				  :: :: spec
-   | Enum num				  :: :: enum
-   | Alias				  :: :: alias
-   | Unknown_path optx			  :: :: unknown {{ com Tag to distinguish an unknown path from a non-analysis non deterministic path}}
-
-ne :: 'Ne_' ::=
- {{ com internal numeric expressions }}
-   | x                                   :: :: id
-   | ' x                                 :: :: var
-   | num                                 :: :: const
-   | infinity                            :: :: inf
-   | ne1 * ne2                           :: :: mult
-   | ne1 + ... + nen                     :: :: add
-   | ne1 - ne2 	 		       :: :: minus
-   | 2 ** ne				 :: :: exp
-   | ( - ne )                            :: :: unary
-   | zero   				 :: S :: zero
-     {{ lem (Ne_const 0) }}
-   | one				 :: S :: one
-     {{ lem (Ne_const 1) }}
-   | bitlength ( bin )                   :: M :: cbin
-     {{ ocaml (asssert false) }}
-     {{ hol ARB }}
-     {{ lem (blength [[bin]]) }}
-   | bitlength ( hex )                   :: M :: chex
-     {{ ocaml (assert false) }}
-     {{ hol ARB }}
-     {{ lem (hlength [[hex]]) }}
-   | count ( num0 ... numi )                :: M :: length {{ichlo "todo" }}
-   | length ( pat1 ... patn )            :: M :: cpat
-     {{ ocaml (assert false) }}
-     {{ hol ARB }}
-     {{ lem (Ne_const (List.length [[pat1...patn]])) }}
-   | length ( exp1 ... expn )            :: M :: cexp
-     {{ hol ARB }}
-     {{ ocaml (assert false) }}
-     {{ lem (Ne_const (List.length [[exp1...expn]])) }}
- 
- t_arg :: 't_arg_' ::=  
- {{ com Argument to type constructors }}
- | t :: :: typ
- | ne :: :: nexp
- | effect :: :: effect
- | order :: :: order
- | fresh :: M :: freshvar {{ lem T_arg (T_var "fresh") }}
-
- t_args :: '' ::=   {{ lem list t_arg }}
-  {{ com Arguments to type constructors }}
-   | t_arg1 ... t_argn                            :: :: T_args
-
- nec :: 'Nec_' ::=
-   {{ com Numeric expression constraints }}
-   | ne <= ne'            :: :: lteq
-   | ne = ne'            :: :: eq
-   | ne >= ne'           :: :: gteq
-   | ' x 'IN' { num1 , ... , numn } :: :: in
-   | nec0 .. necn -> nec'0 ... nec'm :: :: cond
-   | nec0 ... necn                   :: :: branch
-
-S_N {{ tex {\Sigma^{\textsc{N} } } }} :: '' ::= {{ phantom }}
-                                                                    {{ hol nec list }}
-                                                                    {{ lem list nec }}
-    {{ com nexp constraint lists }}
-    | { nec1 , .. ,  necn }                              :: :: Sn_concrete
-      {{ hol [[nec1 .. necn]] }}
-      {{ lem [[nec1 .. necn]] }}
-   | S_N1 u+ .. u+ S_Nn                                                    :: M :: SN_union
-     {{ hol (FOLDR FUNION FEMPTY [[S_N1..S_Nn]]) }}
-     {{ lem (List.foldr (++) [] [[S_N1..S_Nn]]) }}
-     {{ ocaml (assert false) }}
-   | consistent_increase ne1 ne'1 ... nen ne'n                    :: M :: SN_increasing
-     {{ com Generates constraints from  pairs of constraints, where the first of each pair is always larger than the sum of the previous pair }}
-     {{ ocaml (assert false) }}
-     {{ ichl todo }}
-   | consistent_decrease ne1 ne'1 ... nen ne'n                      :: M :: SN_decreasing
-     {{ com Generates constraints from  pairs of constraints, where the first of each pair is always smaller than the difference of the previous pair }}
-     {{ ocaml assert false }}
-     {{ ichl todo }}
-   | resolve ( S_N )                                                :: :: resolution
-     {{ lem [[S_N]] (* Write constraint solver *) }}
- 
-
- E_d {{ tex {\ottnt{E}^{\textsc{d} } } }} :: 'E_d_' ::=  {{ phantom }}
-                                                         {{ lem definition_env }}
- {{ com Environments storing top level information, such as defined abbreviations, records, enumerations, and kinds }}
- | < E_k , E_a , E_r , E_e >	     	       		    	 :: :: base
-   {{ hol arb }}
-   {{ lem (Denv [[E_k]] [[E_r]] [[E_e]]) }}
- | empty       	     					 :: :: empty
-   {{ hol arb }}
-   {{ lem DenvEmp }}
- | E_d u+ E_d'						 :: :: union
-   {{ hol arb }}
-   {{ lem (denv_union [[E_d]] [[E_d']]) }}
- 
- kinf :: 'kinf_' ::=
-   {{ com Whether a kind is default or from a local binding }}
-   | k                                        :: :: k
-   | k default                                :: :: def
-
- tid :: 'tid_' ::=
-   {{ com A type identifier or type variable }}
-   | id                                      :: :: id
-   | kid                                     :: :: var
-
- E_k {{ tex {\ottnt{E}^{\textsc{k} } } }} :: 'E_k_' ::=             {{ phantom }}
-                                                                 {{ hol (tid-> kinf) }}
-                                                                 {{ lem (map tid kinf) }}
-   {{ com Kind environments }}
-   | { tid1 |-> kinf1 , .. , tidn |-> kinfn }    :: :: concrete
-     {{ hol (FOLDR (\(k1,k2) E. E |+ (k1,k2)) FEMPTY [[tid1 kinf1 .. tidn kinfn]]) }}
-     {{ lem (List.foldr (fun (x,v) m -> Map.insert x v m) Map.empty [[tid1 kinf1 .. tidn kinfn]]) }} 
-   | E_k1 u+ .. u+ E_kn                                          :: M :: union
-     {{ com In a unioning kinf, {k default} u {k} results in {k} (i.e. the default is locally forgotten) }} 
-     {{ hol (FOLDR FUNION FEMPTY [[E_k1..E_kn]]) }}
-     {{ lem (List.foldr (union) Map.empty [[E_k1..E_kn]]) }}
-     {{ ocaml (assert false) }}
-   | E_k u- E_k1 .. E_kn                                            :: M :: multi_set_minus
-     {{ hol arb }} 
-     {{ lem (Map.fromList (remove_from (Set_extra.toList (Map.toSet [[E_k]]))
-                                       (Set_extra.toList (Map.toSet (List.foldr (union) Map.empty [[E_k1..E_kn]]))))) }} 
-     {{ ocaml assert false }}
-
- tinf :: 'tinf_' ::=                                                 
-    {{ com Type variables, type, and constraints, bound to an identifier }}
-    | t                                                 :: :: typ
-    | E_k , S_N , tag , t         :: :: quant_typ                                                             
-
-tinflist :: 'tinfs_' ::=
-  {{ com In place so that a list of tinfs can be referred to without the dot form }}
-  | empty :: :: empty
-  | tinf1 ... tinfn  :: :: ls
-
-conformsto :: 'conformsto_' ::=
-  {{ com how much conformance does overloading need }}
- | full :: :: full
- | parm :: :: parm
-
-widenvec :: 'widenvec_' ::=
-  | vectors :: :: widen
-  | none    :: :: dont
-  | _       :: :: dontcare
-
-widennum :: 'widennum_' ::=
-  | nums  :: :: widen
-  | none  :: :: dont
-  | _     :: :: dontcare
-
-widening :: 'widening_' ::=
-  {{ com Should we widen vector start locations, should we widen atoms and ranges }}
-  | ( widennum , widenvec ) :: :: w
-
- E_a {{ tex \ottnt{E}^{\textsc{a} } }} :: 'E_a_' ::=   {{ phantom }}
-                                                                            {{ hol tid |-> tinf}}
-                                                                            {{ lem map tid tinf }} 
-   | { tid1 |-> tinf1 , .. , tidn |-> tinfn } :: :: concrete
-   | E_a1 u+ .. u+ E_an	               :: :: union
-
- field_typs :: 'FT_' ::=     {{ phantom }}
-                             {{ lem list (id * t) }}
- {{ com Record fields }}
- | id1 : t1 , .. , idn : tn :: :: fields
-   {{ lem [[id1 t1..idn tn]] }}
-
- E_r {{ tex \ottnt{E}^{\textsc{r} } }} :: 'E_r_' ::=             {{ phantom }}
-                                                                 {{ hol (id*t) |-> tinf) }}
-                                                                 {{ lem map (list (id*t)) tinf }}
-   {{ com Record environments }}
-   | { { field_typs1 } |-> tinf1 , .. , { field_typsn } |-> tinfn }                    :: :: concrete
-     {{ hol (FOLDR (\x E. E |+ x) FEMPTY) }}
-     {{ lem (List.foldr (fun (x,f) m -> Map.insert x f m) Map.empty [[field_typs1 tinf1..field_typsn tinfn]]) }} 
-   | E_r1 u+ .. u+ E_rn                                          :: M :: union
-     {{ hol (FOLDR FUNION FEMPTY [[E_r1..E_rn]]) }}
-     {{ lem (List.foldr (union) Map.empty [[E_r1..E_rn]]) }}
-     {{ ocaml (assert false) }}
-
-  enumerate_map :: '' ::=                                        {{ phantom }}
-                                                                 {{ lem (list (nat*id)) }}
-   | { num1 |-> id1 ... numn |-> idn }                           :: :: enum_map
-    {{ lem [[num1 id1...numn idn]] }}
-
-  E_e {{ tex \ottnt{E}^{\textsc{e} } }} :: 'E_e_' ::=            {{ phantom }}
-                                                                 {{ lem (map t (list (nat*id))) }}
-   {{ com Enumeration environments }}
-   | { t1 |-> enumerate_map1 , .. , tn |-> enumerate_mapn }     :: :: base
-     {{ lem (List.foldr (fun (x,f) m -> Map.insert x f m) Map.empty [[t1 enumerate_map1..tn enumerate_mapn]]) }} 
-   | E_e1 u+ .. u+ E_en                                         :: :: union
-     {{ lem (List.foldr (union) Map.empty [[E_e1..E_en]]) }}
-
-    
-embed
-{{ lem
- type definition_env =
-   | DenvEmp
-   | Denv of (map tid kinf) * (map (list (id*t)) tinf) * (map t (list (nat*id)))
-
-}}
-
-grammar
-
- E_t {{ tex {\ottnt{E}^{\textsc{t} } } }} :: 'E_t_' ::=          {{ phantom }}
-                                                                 {{ hol (id |-> tinf) }}
-                                                                 {{ lem map id tinf }}
-   {{ com Type environments }}
-   | { id1 |-> tinf1 , .. , idn |-> tinfn }                    :: :: base
-     {{ hol (FOLDR (\x E. E |+ x) FEMPTY [[id1 tinf1 .. idn tinfn]]) }}
-     {{ lem (List.foldr (fun (x,f) m -> Map.insert x f m) Map.empty [[id1 tinf1 .. idn tinfn]]) }} 
-   | { id |-> overload tinf conformsto : tinf1 , ... , tinfn }        :: :: overload
-   | ( E_t1 u+ .... u+ E_tn )                                         :: M :: union
-     {{ hol (FOLDR FUNION FEMPTY [[E_t1....E_tn]]) }}
-     {{ lem (List.foldr (union) Map.empty [[E_t1....E_tn]]) }}
-     {{ ocaml (assert false) }}
-   | u+ E_t1 .. E_tn                                            :: M :: multi_union
-     {{ hol arb }}
-     {{ lem (List.foldr (union) Map.empty [[E_t1..E_tn]]) }}
-     {{ ocaml assert false }}
-   | E_t u- id1 .. idn                                            :: M :: multi_set_minus
-     {{ hol arb }} 
-     {{ lem (Map.fromList (remove_from (Set_extra.toList (Map.toSet [[E_t]]))
-                                       (Set_extra.toList (Map.toSet (List.foldr (union) Map.empty [[id1..idn]]))))) }} 
-     {{ ocaml assert false }}
-   | ( E_t1 inter .... inter E_tn )                                  :: M :: intersect
-     {{ hol arb }}
-     {{ lem (List.foldr (fun a b -> (Map.fromList (Set_extra.toList ((Map.toSet a) inter (Map.toSet b)))))  Map.empty [[E_t1....E_tn]]) }} 
-     {{ ocaml (assert false) }}
-   | inter E_t1 .. E_tn                                            :: M :: multi_inter
-     {{ hol arb }}
-     {{ lem (List.foldr (fun a b -> (Map.fromList (Set_extra.toList ((Map.toSet a) inter (Map.toSet b))))) Map.empty [[E_t1..E_tn]]) }}
-     {{ ocaml assert false }}
-
-
-ts :: ts_ ::=                                     {{ phantom }}
-                                                  {{ lem list t }}
-  | t1 , .. , tn :: :: lst 
-
-embed
-{{ lem
-let blength (bit) = Ne_const 8
-let hlength (bit) = Ne_const 8
-
- type env =
-   | EnvEmp 
-   | Env of (map id tinf) * definition_env
-
- type inf = 
-   | Iemp
-   | Inf of (list nec) * effect
-
- val denv_union : definition_env -> definition_env -> definition_env
- let denv_union de1 de2 = 
-  match (de1,de2) with
-   | (DenvEmp,de2) -> de2
-   | (de1,DenvEmp) -> de1
-   | ((Denv ke1 re1 ee1),(Denv ke2 re2 ee2)) ->
-      Denv (ke1 union ke2) (re1 union re2) (ee1 union ee2)
-   end
-
- val env_union : env -> env -> env
- let env_union e1 e2 =
-   match (e1,e2) with
-    | (EnvEmp,e2) -> e2
-    | (e1,EnvEmp) -> e1
-    | ((Env te1 de1),(Env te2 de2)) ->
-      Env (te1 union te2) (denv_union de1 de2)
- end
-
-let inf_union i1 i2 =
-  match (i1,i2) with 
- | (Iemp,i2) -> i2
- | (i1,Iemp) -> i1
- | (Inf n1 e1,Inf n2 e2) -> (Inf (n1++n2) (effect_union e1 e2))
- end
-
-let fresh_kid denv = Var "x" (*TODO When strings can be manipulated, this should actually build a fresh string*)
-
-}}
-
-grammar
-
- E :: '' ::=                                                     
-                                                                 {{ hol ((string,env_body) fmaptree) }}
-                                                                 {{ lem env }}
- {{ com Definition environment and lexical environment }}
- | < E_t , E_d >                                           :: :: E
-  {{ hol arb }}
-  {{ lem (Env [[E_t]] [[E_d]])  }}
- | empty                                                       :: M :: E_empty
-   {{ hol arb }}
-   {{ lem EnvEmp }}
-   {{ ocaml assert false }}
- | E u+ E'                                                      :: :: E_union
-   {{ lem (env_union [[E]] [[E']]) }}
-
- I :: '' ::=                                                     {{ lem inf }}
-  {{ com Information given by type checking an expression }}
-  | < S_N , effect >                                      :: :: I
-    {{ lem (Inf [[S_N]] [[effect]]) }}
-  | Ie                                                           :: :: Iempty {{ com Empty constraints, effect }} {{ tex {\ottnt{I}_{\epsilon} } }}
-    {{ lem Iemp }}
-  | ( I1 u+ I2 ) :: :: singleunion {{ tex [[I1]] [[u+]] [[I2]] }}
-  | I1 u+ .. u+ In                                               :: :: Iunion {{ com Unions the constraints and effect }}
-    {{ lem (List.foldr inf_union Iemp [[I1..In]]) }}
-
diff --git a/language/primitive_doc.ott b/language/primitive_doc.ott
deleted file mode 100644
index a53f62fe..00000000
--- a/language/primitive_doc.ott
+++ /dev/null
@@ -1,130 +0,0 @@
-grammar 
-
-built_in_types :: '' ::=
-  {{ com Type  Kind }}
-  | bit : Typ :: :: bitDesc
-  | unit : Typ :: :: unitDesc
-  | forall Nat 'n. Nat 'm. range <'n, 'm> : Nat -> Nat -> Typ :: :: rangeDesc
-  | forall Nat 'n. atom <'n> : Nat -> Typ :: :: atomDesc {{ com singleton number, instead of range$< 'n,'n >$ }}
-  | forall Nat 'n, Nat 'm, Order 'o, Typ 't. vector < 'n, 'm, 'o, 't > : Nat -> Nat -> Order -> Typ :: :: vectorDesc
-  | forall Typ 'a. option < 'a > : Typ -> Typ :: :: optCtors
-  | forall Typ 't. register < 't > : Typ -> Typ :: :: registerDec
-  | forall Typ 't. reg < 't > : Typ -> Typ :: :: regDec
-    {{ com internal reference cell }}
-  | forall Nat 'n . implicit <'n> : Nat -> Typ :: :: implicitDesc
-    {{ com To add to a function val specification indicating that n relies on call site expected value }}
-
-built_in_type_abbreviations :: '' ::=
-  | bool => bit :: :: boolDesc
-  | nat => [| 0 '..' pos_infinity |] :: :: natDesc
-  | int  => [| neg_infinity '..' pos_infinity |] :: :: intDesc 
-  | uint8 => [| 0 '..' 2**8 |] :: :: uinteightDesc
-  | uint16 => [| 0 '..' 2**16 |] :: :: uintsixteenDesc
-  | uint32 => [| 0 '..' 2**32 |] :: :: uintthirtytwoDesc
-  | uint64 => [| 0 '..' 2**64 |] :: :: uintsixtyfourDesc
-
-
-functions :: '' ::=
-  {{ com Built-in functions: all have effect pure, all order polymorphic }}
-  | val forall Typ 'a  . 'a -> unit : ignore :: :: ignore
-  | val forall Typ 'a . 'a -> option < 'a > : Some :: :: some
-  | val forall Typ 'a . unit -> option < 'a > : None :: :: none
-  | val ( [: 'n :] , [: 'm :] ) -> [| 'n + 'm |] : + :: :: plusbase
-  {{ com arithmetic addition }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit [ 'n ] : + :: :: plusvec
-  {{ com unsigned vector addition }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ]) -> ( bit [ 'n ] , bit , bit ) : + :: :: plusoverflow
-  {{ com unsigned vector addition with overflow, carry out }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit [ 'n ] : +_s :: :: plusvecS
-  {{ com signed vector addition }}
-  | val forall Nat 'n . (bit [ 'n ] , bit [ 'n ] ) -> ( bit [ 'n ] , bit , bit ) : +_s :: :: plusoverflowS
-  {{ com signed vector addition with overflow, carry out }}
-  | val ( [| 'n '..' 'm |] , [| 'o '..' 'p |] ) -> [| 'n - 'o '..' 'm - 'p |] : - :: :: minusbase
-  {{ com arithmetic subtraction }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit [ 'n ] : - :: :: minusvec
-  {{ com unsigned vector subtraction }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ] ) -> ( bit [ 'n ] , bit , bit ) : - :: :: minusoverflow
-  {{ com unsigned vector subtraction with overflow, carry out }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit [ 'n ] : -_s :: :: minusvecS
-  {{ com signed vector subtraction }}
-  | val forall Nat 'n . (bit [ 'n ] , bit [ 'n ] ) -> ( bit [ 'n ] , bit , bit ) : -_s :: :: minusoverflowS
-  {{ com signed vector subtraction with overflow, carry out }}
-  | val ( [| 'n '..' 'm |] , [| 'o '..' 'p |] ) -> [| 'n * 'o '..' 'm * 'p |] : * :: :: multbase
-  {{ com arithmetic multiplication }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit [ 2*'n ] : * :: :: multvec
-  {{ com unsigned vector multiplication }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit [ 2*'n ] : *_s :: :: multvecS
-  {{ com signed vector multiplication }}
-  | val ( [| 'n '..' 'm |] , [| 1 '..' 'p |] ) -> [| 0 '..' 'p - 1 |] : mod :: :: modbase
-  {{ com arithmetic modulo }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ] ) -> bit [ 'n ] : mod :: :: modvec
-  {{ com unsigned vector modulo }}
-  | val ( [| 'n '..' 'm |] , [| 1 '..' 'p |] ) -> [| 'q '..' 'r |] : quot :: :: quotbase
-  {{ com arithmetic integer division }}
-  | val forall Nat 'n , Nat 'm . ( bit [ 'n ] , bit [ 'm ] ) -> bit [ 'n ] : quot :: :: quotvec
-  {{ com unsigned vector division }}
-  | val forall Nat 'n , Nat 'm . ( bit [ 'n ] , bit [ 'm ] ) -> bit [ 'n ] : quot_s :: :: quotvecS
-  {{ com signed vector division }}
-  | val forall Typ 'a , Nat 'n . ( 'a [' n]  -> [: 'n :] ) : length :: :: len
-  | val forall Typ 'a , Nat 'n , Nat 'm , 'n <= 'm . ( implicit < 'm > , 'a [ 'n ] ) -> 'a [ 'm ] : mask :: :: mask
-  {{ com reduce size of vector, dropping MSBits. Type system supplies implicit parameter, uses may require a cast }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ] ) -> bit : == :: :: vecEQ
-  {{ com vector equality }}
-  | val forall Typ 'a , Typ 'b . ( 'a , 'b ) -> bit : == :: :: EQ
-  | val forall Typ 'a , Typ 'b . ( 'a , 'b ) -> bit : !=  :: :: NEQ
-  | val ( [| 'n '..' 'm |] , [| 'o '..' 'p |] ) -> bit : < :: :: ltbase
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : < :: :: ltvec
-  {{ com unsigned less than }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : <_s :: :: ltvecS
-  | val ( [| 'n '..' 'm |] , [| 'o '..' 'p |] ) -> bit : > :: :: gtbase
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : > :: :: gtvec
-  {{ com unsigned greater than }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : >_s :: :: gtvecS
- | val ( [| 'n '..' 'm |] , [| 'o '..' 'p |] ) -> bit : <= :: :: lteqbase
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : <= :: :: lteqvec
-  {{ com unsigned less than or eq }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : <=_s :: :: lteqvecS
-  | val ( [| 'n '..' 'm |] , [| 'o '..' 'p |] ) -> bit : >= :: :: gteqbase
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : >= :: :: gteqvec
-  {{ com unsigned greater than or eq }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit ['n] ) -> bit : >=_s :: :: gteqvecS
-  | val bit -> bit : ~ :: :: neg
-  {{ com bit negation }}
-  | val forall Nat 'n . bit [ 'n ] -> bit [ 'n ] : ~ :: :: negvec
-  {{ com bitwise negation }}
-  | val ( bit , bit ) -> bit : | :: :: or
-  {{ com bitwise or }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ] ) -> bit [ 'n ] : | :: :: orvec
-  | val ( bit , bit ) -> bit : & :: :: and
-  {{ com bitwise and }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ] ) -> bit [ 'n ] : & :: :: andvec
-  | val ( bit , bit ) -> bit : ^ :: :: xor
-  {{ com bitwise xor }}
-  | val forall Nat 'n . ( bit [ 'n ] , bit [ 'n ] ) -> bit [ 'n ] : '^' :: :: xorvec
-  | val forall Nat 'n . ( bit ,  [| 'n |] ) -> bit [ 'n ] : '^^' :: :: duplicate
-  {{ com duplicate bit into a vector }}
-  | val forall Nat 'n , Nat 'm , 'm <= 'n . ( bit [ 'n ] , [| 'm |] ) -> bit [ 'n ] : << :: :: lshift
-  {{ com left shift }}
-  | val forall Nat 'n , Nat 'm , 'm <= 'n . ( bit [ 'n ] , [| 'm |] ) -> bit [ 'n ] : >> :: :: rshift
-  {{ com right shift }}
-  | val forall Nat 'n , Nat 'm , 'm <= 'n . ( bit [ 'n ] , [| 'm |] ) -> bit [ 'n ] : <<< :: :: rotate
-  {{ com rotate }}
-
-
-functions_with_coercions :: '' ::=
-  | val forall Nat 'n . (bit [ 'n ] , bit [ 'n ]) -> [| 2 ** 'n |] : + :: :: plusvecRange
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( bit [ 'n ] , [| 'o '..' 'p |] ) -> bit [ 'n ] : + :: :: plusvecrange
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( [| 'o '..' 'p |] , bit ['n] ) -> bit [ 'n ] : + :: :: plusrangevec
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( bit [ 'n ] , [| 'o '..' 'p |] ) -> [| 'o '..' 'p + 2** 'n |] : + :: :: plusvecrangeRange
-  | val forall Nat 'n ( bit [ 'n ] , bit ) -> bit [ 'n ] : + :: :: plusvecbit
-  | val forall Nat 'n ( bit , bit [ 'n ]  ) -> bit [ 'n ] : + :: :: plusbitvec
-  | val forall Nat 'n . (bit [ 'n ] , bit [ 'n ]) -> [| 2 ** 'n |] : +_s :: :: plusvecRangeS
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( bit [ 'n ] , [| 'o '..' 'p |] ) -> bit [ 'n ] : +_s :: :: plusvecrangeS
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( [| 'o '..' 'p |] , bit ['n] ) -> bit [ 'n ] : +_s :: :: plusrangevecS
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( bit [ 'n ] , [| 'o '..' 'p |] ) -> [| 'o '..' 'p + 2** 'n |] : +_s :: :: plusvecrangeRangeS
-  | val forall Nat 'n ( bit [ 'n ] , bit ) -> bit [ 'n ] : +_s :: :: plusvecbitS
-  | val forall Nat 'n ( bit , bit [ 'n ]  ) -> bit [ 'n ] : +_s :: :: plusbitvecS
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( bit [ 'n ] , [| 'o '..' 'p |] ) -> bit [ 'n ] : - :: :: minusvecrange
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( [| 'o '..' 'p |] , bit ['n] ) -> bit [ 'n ] : - :: :: minusrangevec
-  | val forall Nat 'n, Nat 'o, Nat 'p. ( bit [ 'n ] , [| 'o '..' 'p |] ) -> [| 'o '..' 'p + 2** 'n |] : - :: :: minusvecrangeRange
-
diff --git a/language/type_system.tex b/language/type_system.tex
deleted file mode 100644
index afb9fb88..00000000
--- a/language/type_system.tex
+++ /dev/null
@@ -1,117 +0,0 @@
-\documentclass[11pt]{article}
-
-\usepackage{amsmath,amssymb,supertabular,geometry,fullpage}
-\geometry{a4paper,twoside,landscape,left=10.5mm,right=10.5mm,top=20mm,bottom=30mm}
-\usepackage{color}
-
-\begin{document}
-
-\input{doc_in}
-
-\title{Sail Type System}
-\author{Kathryn E Gray, Gabriel Kerneis, Peter Sewell}
-
-\maketitle
-
-\tableofcontents
-
-\newpage
-
-\section{Sail syntax}
-
-\ottgrammartabular{
-\ottl\ottinterrule
-\ottannot\ottinterrule
-\ottid\ottinterrule
-\ottkid\ottinterrule
-\ottbaseXXkind\ottinterrule
-\ottkind\ottinterrule
-\ottnexp\ottinterrule
-\ottorder\ottinterrule
-\ottbaseXXeffect\ottinterrule
-\otteffect\ottinterrule
-\otttyp\ottinterrule
-\otttypXXarg\ottinterrule
-\ottnXXconstraint\ottinterrule
-\ottkindedXXid\ottinterrule
-\ottquantXXitem\ottinterrule
-\otttypquant\ottinterrule
-\otttypschm\ottinterrule
-\ottnameXXscmXXopt\ottinterrule
-\otttypeXXdef\ottinterrule
-\otttypeXXunion\ottinterrule
-\ottindexXXrange\ottinterrule
-\ottlit\ottinterrule
-\ottsemiXXopt\ottinterrule
-\ottpat\ottinterrule
-\ottfpat\ottinterrule
-\ottexp\ottinterrule
-\ottlexp\ottinterrule
-\ottfexp\ottinterrule
-\ottfexps\ottinterrule
-\ottoptXXdefault\ottinterrule
-\ottpexp\ottinterrule
-\otttannotXXopt\ottinterrule
-\ottrecXXopt\ottinterrule
-\otteffectXXopt\ottinterrule
-\ottfuncl\ottinterrule
-\ottfundef\ottinterrule
-\ottletbind\ottinterrule
-\ottvalXXspec\ottinterrule
-\ottdefaultXXspec\ottinterrule
-\ottscatteredXXdef\ottinterrule
-\ottregXXid\ottinterrule
-\ottaliasXXspec\ottinterrule
-\ottdecXXspec\ottinterrule
-\ottdef\ottinterrule
-\ottdefs\ottinterrule}
-
-\newpage
-\section{Sail primitive types and functions}
-
-\ottgrammartabular{
-\ottbuiltXXinXXtypes\ottinterrule}
-
-\ottgrammartabular{
-\ottbuiltXXinXXtypeXXabbreviations\ottinterrule
-\ottfunctions\ottinterrule
-\ottfunctionsXXwithXXcoercions\ottinterrule}
-\newpage
-
-\section{Sail type system}
-
-\subsection{Internal type syntax}
-
-\ottgrammartabular{
-\ottk\ottinterrule
-\ottt\ottinterrule
-\ottoptx\ottinterrule
-\otttag\ottinterrule
-\ottne\ottinterrule
-\otttXXarg\ottinterrule
-\otttXXargs\ottinterrule
-\ottnec\ottinterrule
-\ottSXXN\ottinterrule
-\ottEXXd\ottinterrule
-\ottkinf\ottinterrule
-\otttid\ottinterrule
-\ottEXXk\ottinterrule
-\otttinf\ottinterrule
-\ottEXXa\ottinterrule
-\ottfieldXXtyps\ottinterrule
-\ottEXXr\ottinterrule
-\ottenumerateXXmap\ottinterrule
-\ottEXXe\ottinterrule
-\ottEXXt\ottinterrule
-\ottts\ottinterrule
-\ottE\ottinterrule
-\ottI\ottinterrule
-\ottformula\ottinterrule}
-
-
-\subsection{ Type relations }
-\ottdefnss
-
-\section{Sail operational semantics \{TODO\}}
-
-\end{document}
-- 
cgit v1.2.3


From 472097b3fb486d474a427427c1c38298a2ee1fc3 Mon Sep 17 00:00:00 2001
From: Jon French
Date: Tue, 10 Jul 2018 15:00:25 +0100
Subject: disable printing when compiling to Lem to keep rmem happy

---
 riscv/riscv_extras.lem       | 4 ++--
 src/gen_lib/sail2_values.lem | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 88ac3e6f..60b635da 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -106,7 +106,7 @@ val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvecto
 let shift_bits_left v m = shiftl v (uint m)
 
 val print_string : string -> string -> unit
-let print_string msg s = print_endline (msg ^ s)
+let print_string msg s = () (* print_endline (msg ^ s) *)
 
 val prerr_string : string -> string -> unit
 let prerr_string msg s = prerr_endline (msg ^ s)
@@ -115,4 +115,4 @@ val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
 let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
 
 val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
-let print_bits msg bs = print_endline (msg ^ (show_bitlist (bits_of bs)))
+let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
diff --git a/src/gen_lib/sail2_values.lem b/src/gen_lib/sail2_values.lem
index 003eedc7..fd742fb1 100644
--- a/src/gen_lib/sail2_values.lem
+++ b/src/gen_lib/sail2_values.lem
@@ -47,7 +47,7 @@ let power_real b e = realPowInteger b e*)
 
 val print_endline : string -> unit
 let print_endline _ = ()
-declare ocaml target_rep function print_endline = `print_endline`
+(* declare ocaml target_rep function print_endline = `print_endline` *)
 
 val prerr_endline : string -> unit
 let prerr_endline _ = ()
-- 
cgit v1.2.3


From 88a9d6b1d884bd23c03c778faaa3580c4f284f2a Mon Sep 17 00:00:00 2001
From: Jon French
Date: Tue, 10 Jul 2018 15:00:44 +0100
Subject: correct pretty-printing using mappings

---
 riscv/riscv.sail     | 196 ++-------------------------------------------------
 riscv/riscv_sys.sail |  36 +++++++++-
 2 files changed, 38 insertions(+), 194 deletions(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 7ba02a77..44ba8e0f 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -38,12 +38,6 @@ function clause execute UTYPE(imm, rd, op) =
       true
     }
 
-function clause print_insn UTYPE(imm, rd, op) =
-  match (op) {
-    RISCV_LUI   => "lui   " ^ rd ^ ", " ^ BitStr(imm),
-    RISCV_AUIPC => "auipc " ^ rd ^ ", " ^ BitStr(imm)
-  }
-
 mapping utype_mnemonic : uop <-> string = {
   RISCV_LUI   <-> "lui",
   RISCV_AUIPC <-> "auipc"
@@ -77,9 +71,6 @@ function clause execute (RISCV_JAL(imm, rd)) = {
     true
 }
 
-function clause print_insn (RISCV_JAL(imm, rd)) =
-  "jal   " ^ rd ^ ", " ^ BitStr(imm)
-
 /* TODO: handle 2-byte-alignment in mappings */
 
 mapping clause assembly = RISCV_JAL(imm, rd) <-> "jal" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_21(imm)
@@ -97,9 +88,6 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
     true
 }
 
-function clause print_insn (RISCV_JALR(imm, rs1, rd)) =
-  "jalr  " ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(imm)
-
 mapping clause assembly = RISCV_JALR(imm, rs1, rd) <-> "jalr" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
 /* ****************************************************************** */
@@ -132,17 +120,6 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) =
     true
   }
 
-function clause print_insn (BTYPE(imm, rs2, rs1, op)) =
-  let insn : string =
-    match (op) {
-      RISCV_BEQ  => "beq   ",
-      RISCV_BNE  => "bne   ",
-      RISCV_BLT  => "blt   ",
-      RISCV_BGE  => "bge   ",
-      RISCV_BLTU => "bltu  ",
-      RISCV_BGEU => "bgeu  "
-    } in
-  insn ^ rs1 ^ ", " ^ rs2 ^ ", " ^ BitStr(imm)
 
 mapping btype_mnemonic : bop <-> string = {
   RISCV_BEQ  <-> "beq",
@@ -185,17 +162,6 @@ function clause execute (ITYPE (imm, rs1, rd, op)) =
     true
   }
 
-function clause print_insn (ITYPE(imm, rs1, rd, op)) =
-  let insn : string =
-    match (op) {
-      RISCV_ADDI  => "addi  ",
-      RISCV_SLTI  => "slti  ",
-      RISCV_SLTIU => "sltiu ",
-      RISCV_XORI  => "xori  ",
-      RISCV_ORI   => "ori   ",
-      RISCV_ANDI  => "andi  "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(imm)
 
 mapping itype_mnemonic : iop <-> string = {
   RISCV_ADDI  <-> "addi",
@@ -232,14 +198,6 @@ function clause execute (SHIFTIOP(shamt, rs1, rd, op)) =
       true
     }
 
-function clause print_insn (SHIFTIOP(shamt, rs1, rd, op)) =
-  let insn : string =
-    match (op) {
-      RISCV_SLLI => "slli  ",
-      RISCV_SRLI => "srli  ",
-      RISCV_SRAI => "srai  "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(shamt)
 
 mapping shiftiop_mnemonic : sop <-> string = {
   RISCV_SLLI <-> "slli",
@@ -282,21 +240,6 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) =
     true
   }
 
-function clause print_insn (RTYPE(rs2, rs1, rd, op)) =
-  let insn : string =
-    match (op) {
-      RISCV_ADD  => "add   ",
-      RISCV_SUB  => "sub   ",
-      RISCV_SLL  => "sll   ",
-      RISCV_SLT  => "slt   ",
-      RISCV_SLTU => "sltu  ",
-      RISCV_XOR  => "xor   ",
-      RISCV_SRL  => "srl   ",
-      RISCV_SRA  => "sra   ",
-      RISCV_OR   => "or    ",
-      RISCV_AND  => "and   "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping rtype_mnemonic : rop <-> string = {
   RISCV_ADD  <-> "add",
@@ -357,20 +300,6 @@ function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) =
         }
     }
 
-/* FIXME: aq/rl are getting dropped */
-function clause print_insn (LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) =
-  let insn : string =
-    match (width, is_unsigned) {
-      (BYTE,   false) => "lb    ",
-      (BYTE,   true)  => "lbu   ",
-      (HALF,   false) => "lh    ",
-      (HALF,   true)  => "lhu   ",
-      (WORD,   false) => "lw    ",
-      (WORD,   true)  => "lwu   ",
-      (DOUBLE, false) => "ld    ",
-      (DOUBLE, true)  => "ldu   "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(imm)
 
 /* TODO FIXME: is this the actual aq/rl syntax? */
 val maybe_aq : bool <-> string
@@ -433,16 +362,6 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) =
         }
     }
 
-/* FIXME: aq/rl are getting dropped */
-function clause print_insn (STORE(imm, rs2, rs1, width, aq, rl)) =
-  let insn : string =
-    match (width) {
-      BYTE   => "sb    ",
-      HALF   => "sh    ",
-      WORD   => "sw    ",
-      DOUBLE => "sd    "
-    } in
-  insn ^ rs2 ^ ", " ^ rs1 ^ ", " ^ BitStr(imm)
 
 mapping clause assembly = STORE(imm, rs1, rd, size, aq, rl) <-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
@@ -458,8 +377,6 @@ function clause execute (ADDIW(imm, rs1, rd)) = {
   true
 }
 
-function clause print_insn (ADDIW(imm, rs1, rd)) =
-  "addiw " ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(imm)
 
 mapping clause assembly = ADDIW(imm, rs1, rd) <-> "addiw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
@@ -481,14 +398,6 @@ function clause execute (SHIFTW(shamt, rs1, rd, op)) =
       true
     }
 
-function clause print_insn (SHIFTW(shamt, rs1, rd, op)) =
-  let insn : string =
-    match (op) {
-      RISCV_SLLI => "slli  ",
-      RISCV_SRLI => "srli  ",
-      RISCV_SRAI => "srai  "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(shamt)
 
 mapping shiftw_mnemonic : sop <-> string = {
   RISCV_SLLI <-> "slli",
@@ -521,16 +430,6 @@ function clause execute (RTYPEW(rs2, rs1, rd, op)) =
     true
   }
 
-function clause print_insn (RTYPEW(rs2, rs1, rd, op)) =
-  let insn : string =
-    match (op) {
-      RISCV_ADDW => "addw  ",
-      RISCV_SUBW => "subw  ",
-      RISCV_SLLW => "sllw  ",
-      RISCV_SRLW => "srlw  ",
-      RISCV_SRAW => "sraw  "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping rtypew_mnemonic : ropw <-> string = {
   RISCV_ADDW <-> "addw",
@@ -567,16 +466,6 @@ function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) =
     true
   }
 
-function clause print_insn (MUL(rs2, rs1, rd, high, signed1, signed2)) =
-  let insn : string =
-    match (high, signed1, signed2) {
-      (false, true, true)  => "mul   ",
-      (true,  true, true)  => "mulh  ",
-      (true,  true, false) => "mulhsu ",
-      (true, false, false) => "mulhu"
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
-
 mapping mul_mnemonic : (bool, bool, bool) <-> string = {
   (false, true, true)  <-> "mul",
   (true, true, true)   <-> "mulh",
@@ -602,9 +491,6 @@ function clause execute (DIV(rs2, rs1, rd, s)) =
     true
   }
 
-function clause print_insn (DIV(rs2, rs1, rd, s)) =
-  let insn : string = if s then "div   " else "divu  " in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping maybe_not_u : bool <-> string = {
   false <-> "u",
@@ -629,10 +515,6 @@ function clause execute (REM(rs2, rs1, rd, s)) =
     true
   }
 
-function clause print_insn (REM(rs2, rs1, rd, s)) =
-  let insn : string = if s then "rem   " else "remu  " in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
-
 mapping clause assembly = REM(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
@@ -651,8 +533,6 @@ function clause execute (MULW(rs2, rs1, rd)) =
     true
   }
 
-function clause print_insn (MULW(rs2, rs1, rd)) =
-  "mulw  " ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping clause assembly = MULW(rs2, rs1, rd) <->  "mulw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
@@ -672,9 +552,6 @@ function clause execute (DIVW(rs2, rs1, rd, s)) =
     true
   }
 
-function clause print_insn (DIVW(rs2, rs1, rd, s)) =
-  let insn : string = if s then "divw  " else "divuw " in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping clause assembly = DIVW(rs2, rs1, rd, s) <-> "div" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
@@ -694,9 +571,6 @@ function clause execute (REMW(rs2, rs1, rd, s)) =
     true
   }
 
-function clause print_insn (REMW(rs2, rs1, rd, s)) =
-  let insn : string = if s then "remw  " else "remuw " in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping clause assembly = REMW(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
@@ -725,10 +599,6 @@ function clause execute (FENCE(pred, succ)) = {
   true
 }
 
-/* FIXME */
-function clause print_insn (FENCE(pred, succ)) =
-  "fence"
-
 mapping bit_maybe_r : bits(1) <-> string = {
   0b1 <-> "r",
   0b0 <-> ""
@@ -762,8 +632,6 @@ mapping clause encdec = FENCEI() <-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000
 
 function clause execute FENCEI() = { MEM_fence_i(); true }
 
-function clause print_insn (FENCEI()) =
-  "fence.i"
 
 mapping clause assembly = FENCEI() <-> "fence.i"
 
@@ -784,8 +652,6 @@ function clause execute ECALL() =
     false
   }
 
-function clause print_insn (ECALL()) =
-  "ecall"
 
 mapping clause assembly = ECALL() <-> "ecall"
 
@@ -802,9 +668,6 @@ function clause execute MRET() = {
   false
 }
 
-function clause print_insn (MRET()) =
-  "mret"
-
 mapping clause assembly = MRET() <-> "mret"
 
 /* ****************************************************************** */
@@ -823,9 +686,6 @@ function clause execute SRET() = {
   false
 }
 
-function clause print_insn (SRET()) =
-  "sret"
-
 mapping clause assembly = SRET() <-> "sret"
 
 /* ****************************************************************** */
@@ -838,9 +698,6 @@ function clause execute EBREAK() = {
   false
 }
 
-function clause print_insn (EBREAK()) =
-  "ebreak"
-
 mapping clause assembly = EBREAK() <-> "ebreak"
 
 /* ****************************************************************** */
@@ -857,9 +714,6 @@ function clause execute WFI() =
     User       => { handle_illegal(); false }
   }
 
-function clause print_insn (WFI()) =
-  "wfi"
-
 mapping clause assembly = WFI() <-> "wfi"
 
 /* ****************************************************************** */
@@ -882,9 +736,6 @@ function clause execute SFENCE_VMA(rs1, rs2) = {
   }
 }
 
-function clause print_insn (SFENCE_VMA(rs1, rs2)) =
-  "sfence.vma " ^ rs1 ^ ", " ^ rs2
-
 mapping clause assembly = SFENCE_VMA(rs1, rs2) <-> "sfence.vma" ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
@@ -949,9 +800,6 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) =
            }
        }
 
-function clause print_insn (LOADRES(aq, rl, rs1, width, rd)) =
-  "lr" ^ lrsc_width_str(width) ^ aqrl_str(aq, rl) ^ " " ^ rd ^ ", " ^ rs1
-
 mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) <-> "lr." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)
 
 /* ****************************************************************** */
@@ -1015,9 +863,6 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
   }
 }
 
-function clause print_insn (STORECON(aq, rl, rs2, rs1, width, rd)) =
-  "sc" ^ lrsc_width_str(width) ^ aqrl_str(aq, rl) ^ " " ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
-
 mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
@@ -1093,30 +938,6 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
   }
 }
 
-function clause print_insn (AMO(op, aq, rl, rs2, rs1, width, rd)) =
-  let insn : string =
-    match (op, width) {
-      (AMOSWAP, WORD) => "amoswap.w ",
-      (AMOADD , WORD) => "amoadd.w  ",
-      (AMOXOR , WORD) => "amoxor.w  ",
-      (AMOAND , WORD) => "amoand.w  ",
-      (AMOOR  , WORD) => "amoor.w   ",
-      (AMOMIN , WORD) => "amomin.w  ",
-      (AMOMAX , WORD) => "amomax.w  ",
-      (AMOMINU, WORD) => "amominu.w ",
-      (AMOMAXU, WORD) => "amomaxu.w ",
-      (AMOSWAP, DOUBLE) => "amoswap.d ",
-      (AMOADD , DOUBLE) => "amoadd.d  ",
-      (AMOXOR , DOUBLE) => "amoxor.d  ",
-      (AMOAND , DOUBLE) => "amoand.d  ",
-      (AMOOR  , DOUBLE) => "amoor.d   ",
-      (AMOMIN , DOUBLE) => "amomin.d  ",
-      (AMOMAX , DOUBLE) => "amomax.d  ",
-      (AMOMINU, DOUBLE) => "amominu.d ",
-      (AMOMAXU, DOUBLE) => "amomaxu.d ",
-      (_, _)            => "amo.bad "
-    } in
-  insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
 
 mapping amo_mnemonic : amoop <-> string = {
   AMOSWAP <-> "amoswap",
@@ -1267,18 +1088,6 @@ function clause execute CSR(csr, rs1, rd, is_imm, op) =
     true
   }
 
-function clause print_insn (CSR(csr, rs1, rd, is_imm, op)) =
-  let insn : string =
-    match (op, is_imm) {
-      (CSRRW, true)  => "csrrwi ",
-      (CSRRW, false) => "csrrw  ",
-      (CSRRS, true)  => "csrrsi ",
-      (CSRRS, false) => "csrrs  ",
-      (CSRRC, true)  => "csrrci ",
-      (CSRRC, false) => "csrrc  "
-    } in
-  let rs1_str : string = if is_imm then BitStr(rs1) else reg_name_abi(rs1) in
-  insn ^ rd ^ ", " ^ rs1_str ^ ", " ^ csr_name(csr)
 
 mapping maybe_i : bool <-> string = {
   true  <-> "i",
@@ -1861,8 +1670,11 @@ function clause decodeCompressed _ = None()
 end ast
 end decodeCompressed
 end execute
-end print_insn
 end assembly
 end encdec
 
+function clause print_insn insn = assembly(insn)
+
+end print_insn
+
 function decode bv = Some(encdec(bv))
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 36942eed..9153c3cb 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -534,6 +534,12 @@ mapping csr_name_map : csreg <-> string = {
     0x000  <-> "ustatus",
     0x004  <-> "uie",
     0x005  <-> "utvec",
+    /* user trap handling */
+    0x040  <-> "uscratch",
+    0x041  <-> "uepc",
+    0x042  <-> "ucause",
+    0x043  <-> "utval",
+    0x044  <-> "uip",
     /* user floating-point context */
     0x001  <-> "fflags",
     0x002  <-> "frm",
@@ -580,7 +586,27 @@ mapping csr_name_map : csreg <-> string = {
     0x342  <-> "mcause",
     0x343  <-> "mtval",
     0x344  <-> "mip",
-    /* TODO: machine protection and translation */
+    /* machine protection and translation */
+    0x3A0  <-> "pmpcfg0",
+    0x3A1  <-> "pmpcfg1",
+    0x3A2  <-> "pmpcfg2",
+    0x3A3  <-> "pmpcfg3",
+    0x3B0  <-> "pmpaddr0",
+    0x3B1  <-> "pmpaddr1",
+    0x3B2  <-> "pmpaddr2",
+    0x3B3  <-> "pmpaddr3",
+    0x3B4  <-> "pmpaddr4",
+    0x3B5  <-> "pmpaddr5",
+    0x3B6  <-> "pmpaddr6",
+    0x3B7  <-> "pmpaddr7",
+    0x3B8  <-> "pmpaddr8",
+    0x3B9  <-> "pmpaddr9",
+    0x3BA  <-> "pmpaddr10",
+    0x3BB  <-> "pmpaddr11",
+    0x3BC  <-> "pmpaddr12",
+    0x3BD  <-> "pmpaddr13",
+    0x3BE  <-> "pmpaddr14",
+    0x3BF  <-> "pmpaddr15",
     /* machine counters/timers */
     0xB00  <-> "mcycle",
     0xB02  <-> "minstret",
@@ -588,7 +614,13 @@ mapping csr_name_map : csreg <-> string = {
     0xB82  <-> "minstreth",
     /* TODO: other hpm counters and events */
     /* trigger/debug */
-    0x7a0  <-> "tselect"
+    0x7a0  <-> "tselect",
+    0x7a1  <-> "tdata1",
+    0x7a2  <-> "tdata2",
+    0x7a3  <-> "tdata3"
+
+    /* numeric fallback */
+    /* reg    <-> hex_bits_12(reg) */
  }
 
 
-- 
cgit v1.2.3


From b34725b4d168984c505bb691735be96961499830 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Tue, 10 Jul 2018 15:48:17 +0100
Subject: Only put static qualifier on valspecs when -static flag is used

---
 src/c_backend.ml | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/c_backend.ml b/src/c_backend.ml
index e92ca1a6..e4bbd393 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -2519,12 +2519,13 @@ let codegen_def' ctx = function
      ^^ string (Printf.sprintf "%s %s;" (sgen_ctyp ctyp) (sgen_id id))
 
   | CDEF_spec (id, arg_ctyps, ret_ctyp) ->
+     let static = if !opt_static then "static " else "" in
      if Env.is_extern id ctx.tc_env "c" then
        empty
      else if is_stack_ctyp ret_ctyp then
-       string (Printf.sprintf "static %s %s(%s);" (sgen_ctyp ret_ctyp) (sgen_id id) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
+       string (Printf.sprintf "%s%s %s(%s);" static (sgen_ctyp ret_ctyp) (sgen_id id) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
      else
-       string (Printf.sprintf "static void %s(%s *rop, %s);" (sgen_id id) (sgen_ctyp ret_ctyp) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
+       string (Printf.sprintf "%svoid %s(%s *rop, %s);" static (sgen_id id) (sgen_ctyp ret_ctyp) (Util.string_of_list ", " sgen_ctyp arg_ctyps))
 
   | CDEF_fundef (id, ret_arg, args, instrs) as def ->
      if !opt_ddump_flow_graphs then make_dot id (instrs_graph instrs) else ();
@@ -2566,7 +2567,8 @@ let codegen_def' ctx = function
      codegen_type_def ctx ctype_def
 
   | CDEF_startup (id, instrs) ->
-     let startup_header = string (Printf.sprintf "static void startup_%s(void)" (sgen_id id)) in
+     let static = if !opt_static then "static " else "" in
+     let startup_header = string (Printf.sprintf "%svoid startup_%s(void)" static (sgen_id id)) in
      separate_map hardline codegen_decl instrs
      ^^ twice hardline
      ^^ startup_header ^^ hardline
@@ -2575,7 +2577,8 @@ let codegen_def' ctx = function
      ^^ string "}"
 
   | CDEF_finish (id, instrs) ->
-     let finish_header = string (Printf.sprintf "static void finish_%s(void)" (sgen_id id)) in
+     let static = if !opt_static then "static " else "" in
+     let finish_header = string (Printf.sprintf "%svoid finish_%s(void)" static (sgen_id id)) in
      separate_map hardline codegen_decl (List.filter is_decl instrs)
      ^^ twice hardline
      ^^ finish_header ^^ hardline
-- 
cgit v1.2.3


From 115c33129aa7dc3f0f0f6232c8e5fd892c79eb87 Mon Sep 17 00:00:00 2001
From: Jon French
Date: Tue, 10 Jul 2018 16:35:18 +0100
Subject: fix constructor typo

---
 src/lem_interp/sail2_instr_kinds.lem | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lem_interp/sail2_instr_kinds.lem b/src/lem_interp/sail2_instr_kinds.lem
index 938b693d..3d238676 100644
--- a/src/lem_interp/sail2_instr_kinds.lem
+++ b/src/lem_interp/sail2_instr_kinds.lem
@@ -219,7 +219,7 @@ instance (Show instruction_kind)
     | IK_mem_read read_kind   -> "IK_mem_read " ^ (show read_kind)
     | IK_mem_write write_kind -> "IK_mem_write " ^ (show write_kind)
     | IK_mem_rmw (r, w)       -> "IK_mem_rmw " ^ (show r) ^ " " ^ (show w)
-    | IK_branch               -> "IK_branch"
+    | IK_branch ()            -> "IK_branch"
     | IK_trans trans_kind     -> "IK_trans " ^ (show trans_kind)
     | IK_simple ()            -> "IK_simple"
   end
-- 
cgit v1.2.3


From 6bc52192841d712cb8d582841b0a73d2b7f59df6 Mon Sep 17 00:00:00 2001
From: Jon French
Date: Tue, 10 Jul 2018 16:36:16 +0100
Subject: RISCV load-acquire in Lem (-> rmem)

---
 riscv/prelude.sail                | 31 ++++++++++++++++++++++++++++---
 riscv/riscv_extras.lem            | 14 ++++++++++++++
 riscv/riscv_extras_sequential.lem | 18 ++++++++++++++++--
 riscv/riscv_mem.sail              | 18 +++++++++---------
 riscv/riscv_vmem.sail             |  2 +-
 5 files changed, 68 insertions(+), 15 deletions(-)

diff --git a/riscv/prelude.sail b/riscv/prelude.sail
index 9ec1d86d..d99581a7 100644
--- a/riscv/prelude.sail
+++ b/riscv/prelude.sail
@@ -366,11 +366,36 @@ function __RISCV_write (addr, width, data) = {
 val __TraceMemoryWrite : forall 'n 'm.
   (atom('n), bits('m), bits(8 * 'n)) -> unit
 
-val __ReadRAM = "read_ram" : forall 'n 'm.
+val __ReadRAM = { lem: "MEMr", _ : "read_ram" } : forall 'n 'm.
   (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
 
-val __RISCV_read : forall 'n. (bits(64), atom('n)) -> option(bits(8 * 'n)) effect {rmem}
-function __RISCV_read (addr, width) = Some(__ReadRAM(64, width, 0x0000_0000_0000_0000, addr))
+val __ReadRAM_acquire = { lem: "MEMr_acquire", _ : "read_ram" } : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __ReadRAM_strong_acquire = { lem: "MEMr_strong_acquire", _ : "read_ram" } : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __ReadRAM_reserved = { lem: "MEMr_reserved", _ : "read_ram" } : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __ReadRAM_reserved_acquire = { lem: "MEMr_reserved_acquire", _ : "read_ram" } : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __ReadRAM_reserved_strong_acquire = { lem: "MEMr_reserved_strong_acquire", _ : "read_ram" } : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __RISCV_read : forall 'n. (bits(64), atom('n), bool, bool, bool) -> option(bits(8 * 'n)) effect {rmem}
+function __RISCV_read (addr, width, aq, rl, res) =
+  match (aq, rl, res) {
+    (false, false, false) => Some(__ReadRAM(64, width, 0x0000_0000_0000_0000, addr)),
+    (true,  false, false) => Some(__ReadRAM_acquire(64, width, 0x0000_0000_0000_0000, addr)),
+    (true,  true,  false) => Some(__ReadRAM_strong_acquire(64, width, 0x0000_0000_0000_0000, addr)),
+    (false, false, true)  => Some(__ReadRAM_reserved(64, width, 0x0000_0000_0000_0000, addr)),
+    (true,  false, true)  => Some(__ReadRAM_reserved_acquire(64, width, 0x0000_0000_0000_0000, addr)),
+    (true,  true,  true)  => Some(__ReadRAM_reserved_strong_acquire(64, width, 0x0000_0000_0000_0000, addr)),
+    (false, true,  false) => None(),
+    (false, true,  true)  => None()
+  }
 
 val __TraceMemoryRead : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit
 
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 60b635da..60468a4e 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -34,6 +34,20 @@ let MEMea_conditional_release addr size  = write_mem_ea Write_RISCV_conditional_
 let MEMea_conditional_strong_release addr size
                                           = write_mem_ea Write_RISCV_conditional_strong_release addr size
 
+val MEMr                         : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_acquire                 : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_strong_acquire          : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved                : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_acquire        : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+
+let MEMr addrsize size hexRAM addr                         = read_mem Read_plain addr size
+let MEMr_acquire addrsize size hexRAM addr                 = read_mem Read_RISCV_acquire addr size
+let MEMr_strong_acquire addrsize size hexRAM addr          = read_mem Read_RISCV_strong_acquire addr size
+let MEMr_reserved addrsize size hexRAM addr                = read_mem Read_RISCV_reserved addr size
+let MEMr_reserved_acquire addrsize size hexRAM addr        = read_mem Read_RISCV_reserved_acquire addr size
+let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size
+
 val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e
 let write_ram addrsize size hexRAM address value =
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index 88ac3e6f..60468a4e 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -34,6 +34,20 @@ let MEMea_conditional_release addr size  = write_mem_ea Write_RISCV_conditional_
 let MEMea_conditional_strong_release addr size
                                           = write_mem_ea Write_RISCV_conditional_strong_release addr size
 
+val MEMr                         : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_acquire                 : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_strong_acquire          : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved                : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_acquire        : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+
+let MEMr addrsize size hexRAM addr                         = read_mem Read_plain addr size
+let MEMr_acquire addrsize size hexRAM addr                 = read_mem Read_RISCV_acquire addr size
+let MEMr_strong_acquire addrsize size hexRAM addr          = read_mem Read_RISCV_strong_acquire addr size
+let MEMr_reserved addrsize size hexRAM addr                = read_mem Read_RISCV_reserved addr size
+let MEMr_reserved_acquire addrsize size hexRAM addr        = read_mem Read_RISCV_reserved_acquire addr size
+let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size
+
 val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e
 let write_ram addrsize size hexRAM address value =
@@ -106,7 +120,7 @@ val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvecto
 let shift_bits_left v m = shiftl v (uint m)
 
 val print_string : string -> string -> unit
-let print_string msg s = print_endline (msg ^ s)
+let print_string msg s = () (* print_endline (msg ^ s) *)
 
 val prerr_string : string -> string -> unit
 let prerr_string msg s = prerr_endline (msg ^ s)
@@ -115,4 +129,4 @@ val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
 let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
 
 val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
-let print_bits msg bs = print_endline (msg ^ (show_bitlist (bits_of bs)))
+let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail
index 008c1642..cb60851a 100644
--- a/riscv/riscv_mem.sail
+++ b/riscv/riscv_mem.sail
@@ -4,8 +4,8 @@ function is_aligned_addr (addr : xlenbits, width : atom('n)) -> forall 'n. bool
   unsigned(addr) % width == 0
 
 // only used for actual memory regions, to avoid MMIO effects
-function phys_mem_read(t : ReadType, addr : xlenbits, width : atom('n)) -> forall 'n. MemoryOpResult(bits(8 * 'n)) =
-  match (t, __RISCV_read(addr, width)) {
+function phys_mem_read(t : ReadType, addr : xlenbits, width : atom('n), aq : bool, rl: bool, res : bool) -> forall 'n. MemoryOpResult(bits(8 * 'n)) =
+  match (t, __RISCV_read(addr, width, aq, rl, res)) {
     (Instruction, None()) => MemException(E_Fetch_Access_Fault),
     (Data, None())        => MemException(E_Load_Access_Fault),
     (_, Some(v))          => { print("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v));
@@ -17,7 +17,7 @@ function checked_mem_read(t : ReadType, addr : xlenbits, width : atom('n)) -> fo
   if   t == Data & within_mmio_readable(addr, width)
   then mmio_read(addr, width)
   else if within_phys_mem(addr, width)
-  then phys_mem_read(t, addr, width)
+  then phys_mem_read(t, addr, width, false, false, false)
   else MemException(E_Load_Access_Fault)
 
 /* FIXME: We assume atomic accesses are only done to memory-backed regions.  MMIO is not modeled. */
@@ -29,12 +29,12 @@ val MEMr_reserved                : forall 'n. (xlenbits, atom('n)) -> MemoryOpRe
 val MEMr_reserved_acquire        : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
 val MEMr_reserved_strong_acquire : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
 
-function MEMr                         (addr, width) = phys_mem_read(Data, addr, width)
-function MEMr_acquire                 (addr, width) = phys_mem_read(Data, addr, width)
-function MEMr_strong_acquire          (addr, width) = phys_mem_read(Data, addr, width)
-function MEMr_reserved                (addr, width) = phys_mem_read(Data, addr, width)
-function MEMr_reserved_acquire        (addr, width) = phys_mem_read(Data, addr, width)
-function MEMr_reserved_strong_acquire (addr, width) = phys_mem_read(Data, addr, width)
+function MEMr                         (addr, width) = phys_mem_read(Data, addr, width, false, false, false)
+function MEMr_acquire                 (addr, width) = phys_mem_read(Data, addr, width, true,  false, false)
+function MEMr_strong_acquire          (addr, width) = phys_mem_read(Data, addr, width, true,  true,  false)
+function MEMr_reserved                (addr, width) = phys_mem_read(Data, addr, width, false, false, true)
+function MEMr_reserved_acquire        (addr, width) = phys_mem_read(Data, addr, width, true,  false, true)
+function MEMr_reserved_strong_acquire (addr, width) = phys_mem_read(Data, addr, width, true,  true,  true)
 
 /* NOTE: The rreg effect is due to MMIO. */
 val mem_read : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg, escape}
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index 36650705..fc9e7eb5 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -144,7 +144,7 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
                                 PTE39_LOG_SIZE);
   let pte_addr = ptb + pt_ofs;
   /* FIXME: we assume here that walks only access memory-backed addresses. */
-  match (phys_mem_read(Data, EXTZ(pte_addr), 8)) {
+  match (phys_mem_read(Data, EXTZ(pte_addr), 8, false, false, false)) {
     MemException(_) => {
       print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
             ^ " pt_base=" ^ BitStr(ptb)
-- 
cgit v1.2.3


From 497c8bf636619988203f8a868806fb04903db2dd Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 10 Jul 2018 16:50:06 +0100
Subject: Make HOL build properly again for all of the models

---
 aarch64/mono/demo/mk.hol | 2 +-
 cheri/Makefile           | 2 +-
 mips/Makefile            | 2 +-
 riscv/Makefile           | 3 ++-
 4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/aarch64/mono/demo/mk.hol b/aarch64/mono/demo/mk.hol
index 3aa142a3..d55f2289 100755
--- a/aarch64/mono/demo/mk.hol
+++ b/aarch64/mono/demo/mk.hol
@@ -7,5 +7,5 @@ set -ex
      -lem -lem_mwords -lem_sequential -lem_lib Aarch64_extras -o aarch64_mono
 # Explicitly include replacement prompt files, as Lem's choice of file depends
 # on some internal dependency ordering
-lem -hol -outdir . -lib ../../../lib/hol ../../../lib/hol/sail2_prompt_monad.lem ../../../lib/hol/sail2_prompt.lem -lib ../../../src/gen_lib/ -lib ../../../src/lem_interp ../aarch64_extras.lem aarch64_mono_types.lem aarch64_mono.lem 
+lem -hol -outdir . -lib ../../../lib/hol -i ../../../lib/hol/sail2_prompt_monad.lem -i ../../../lib/hol/sail2_prompt.lem -lib ../../../src/gen_lib/ -lib ../../../src/lem_interp ../aarch64_extras.lem aarch64_mono_types.lem aarch64_mono.lem 
 Holmake
diff --git a/cheri/Makefile b/cheri/Makefile
index f3a0b7e7..0d207391 100644
--- a/cheri/Makefile
+++ b/cheri/Makefile
@@ -107,7 +107,7 @@ C%.thy: c%.lem c%_types.lem $(MIPS_SAIL_DIR)/mips_extras.lem
 	sed -i 's/datatype ast/datatype (plugins only: size) ast/' C$*_types.thy
 
 %Script.sml: %.lem %_types.lem $(MIPS_SAIL_DIR)/mips_extras.lem
-	lem -hol -outdir . -lib $(SAIL_DIR)/lib/hol -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^
+	lem -hol -outdir . -lib $(SAIL_DIR)/lib/hol -i $(SAIL_DIR)/lib/hol/sail2_prompt_monad.lem -i $(SAIL_DIR)/lib/hol/sail2_prompt.lem -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^
 
 %Theory.uo: %Script.sml
 	Holmake $@
diff --git a/mips/Makefile b/mips/Makefile
index 062ccd8b..9fdda4d3 100644
--- a/mips/Makefile
+++ b/mips/Makefile
@@ -59,7 +59,7 @@ M%.thy: m%.lem m%_types.lem mips_extras.lem
 	sed -i 's/datatype ast/datatype (plugins only: size) ast/' M$*_types.thy
 
 %Script.sml: %.lem %_types.lem $(MIPS_SAIL_DIR)/mips_extras.lem
-	lem -hol -outdir . -lib $(SAIL_DIR)/lib/hol -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^
+	lem -hol -outdir . -lib $(SAIL_DIR)/lib/hol -i $(SAIL_DIR)/lib/hol/sail2_prompt_monad.lem -i $(SAIL_DIR)/lib/hol/sail2_prompt.lem -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^
 
 %Theory.uo: %Script.sml
 	Holmake $@
diff --git a/riscv/Makefile b/riscv/Makefile
index 68272112..9633f0d4 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -62,7 +62,8 @@ riscv_sequential.lem: $(SAIL_SRCS) Makefile
 	$(SAIL_DIR)/sail -lem -lem_sequential -o riscv_sequential -lem_mwords -lem_lib Riscv_extras_sequential $(SAIL_SRCS)
 
 riscvScript.sml : riscv.lem riscv_extras.lem
-	lem -hol -outdir . -lib ../lib/hol -lib ../src/lem_interp -lib ../src/gen_lib \
+	lem -hol -outdir . -lib ../lib/hol -i ../lib/hol/sail2_prompt_monad.lem -i ../lib/hol/sail2_prompt.lem \
+	    -lib ../src/lem_interp -lib ../src/gen_lib \
 		riscv_extras.lem \
 		riscv_types.lem \
 		riscv.lem
-- 
cgit v1.2.3


From defeb0288cf2c4b5315a11a20de142318d921fc7 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Tue, 10 Jul 2018 17:17:11 +0100
Subject: remove sim.dts when anonymising.

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index a22e19df..40040a11 100644
--- a/Makefile
+++ b/Makefile
@@ -69,6 +69,7 @@ anon_dist:
 	headache -c etc/headache_config -h etc/anon_header `ls snapshots/isabelle/lib/sail/*.thy`
 	headache -c etc/headache_config -h etc/anon_header `ls snapshots/isabelle/lib/lem/*.thy`
 	headache -c etc/headache_config -h etc/anon_header `ls snapshots/hol4/lem/hol-lib/*.sml`
+	rm mips/sim.dts
 
 clean:
 	for subdir in src arm ; do\
-- 
cgit v1.2.3


From 1b99f1bcb57b1ae1eae08129e579e3618253a321 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Tue, 10 Jul 2018 10:08:12 -0700
Subject: Support riscv atomic accesses to mmio regions, used by linux to
 access device registers.

---
 riscv/riscv_mem.sail | 60 ++++++++++++++++++++++++++--------------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail
index cb60851a..2322a0ad 100644
--- a/riscv/riscv_mem.sail
+++ b/riscv/riscv_mem.sail
@@ -20,21 +20,21 @@ function checked_mem_read(t : ReadType, addr : xlenbits, width : atom('n)) -> fo
   then phys_mem_read(t, addr, width, false, false, false)
   else MemException(E_Load_Access_Fault)
 
-/* FIXME: We assume atomic accesses are only done to memory-backed regions.  MMIO is not modeled. */
-
-val MEMr                         : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
-val MEMr_acquire                 : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
-val MEMr_strong_acquire          : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
-val MEMr_reserved                : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
-val MEMr_reserved_acquire        : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
-val MEMr_reserved_strong_acquire : forall 'n. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem}
-
-function MEMr                         (addr, width) = phys_mem_read(Data, addr, width, false, false, false)
-function MEMr_acquire                 (addr, width) = phys_mem_read(Data, addr, width, true,  false, false)
-function MEMr_strong_acquire          (addr, width) = phys_mem_read(Data, addr, width, true,  true,  false)
-function MEMr_reserved                (addr, width) = phys_mem_read(Data, addr, width, false, false, true)
-function MEMr_reserved_acquire        (addr, width) = phys_mem_read(Data, addr, width, true,  false, true)
-function MEMr_reserved_strong_acquire (addr, width) = phys_mem_read(Data, addr, width, true,  true,  true)
+/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */
+
+val MEMr                         : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg}
+val MEMr_acquire                 : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg}
+val MEMr_strong_acquire          : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg}
+val MEMr_reserved                : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg}
+val MEMr_reserved_acquire        : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg}
+val MEMr_reserved_strong_acquire : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg}
+
+function MEMr                         (addr, width) = checked_mem_read(Data, addr, width)
+function MEMr_acquire                 (addr, width) = checked_mem_read(Data, addr, width)
+function MEMr_strong_acquire          (addr, width) = checked_mem_read(Data, addr, width)
+function MEMr_reserved                (addr, width) = checked_mem_read(Data, addr, width)
+function MEMr_reserved_acquire        (addr, width) = checked_mem_read(Data, addr, width)
+function MEMr_reserved_strong_acquire (addr, width) = checked_mem_read(Data, addr, width)
 
 /* NOTE: The rreg effect is due to MMIO. */
 val mem_read : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg, escape}
@@ -100,21 +100,21 @@ function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)
   then phys_mem_write(addr, width, data)
   else MemException(E_SAMO_Access_Fault)
 
-/* FIXME: We assume atomic accesses are only done to memory-backed regions.  MMIO is not modeled. */
-
-val MEMval                            : forall 'n. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv}
-val MEMval_release                    : forall 'n. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv}
-val MEMval_strong_release             : forall 'n. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv}
-val MEMval_conditional                : forall 'n. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv}
-val MEMval_conditional_release        : forall 'n. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv}
-val MEMval_conditional_strong_release : forall 'n. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv}
-
-function MEMval                            (addr, width, data) = phys_mem_write(addr, width, data)
-function MEMval_release                    (addr, width, data) = phys_mem_write(addr, width, data)
-function MEMval_strong_release             (addr, width, data) = phys_mem_write(addr, width, data)
-function MEMval_conditional                (addr, width, data) = phys_mem_write(addr, width, data)
-function MEMval_conditional_release        (addr, width, data) = phys_mem_write(addr, width, data)
-function MEMval_conditional_strong_release (addr, width, data) = phys_mem_write(addr, width, data)
+/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */
+
+val MEMval                            : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+val MEMval_release                    : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+val MEMval_strong_release             : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+val MEMval_conditional                : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+val MEMval_conditional_release        : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+val MEMval_conditional_strong_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+
+function MEMval                            (addr, width, data) = checked_mem_write(addr, width, data)
+function MEMval_release                    (addr, width, data) = checked_mem_write(addr, width, data)
+function MEMval_strong_release             (addr, width, data) = checked_mem_write(addr, width, data)
+function MEMval_conditional                (addr, width, data) = checked_mem_write(addr, width, data)
+function MEMval_conditional_release        (addr, width, data) = checked_mem_write(addr, width, data)
+function MEMval_conditional_strong_release (addr, width, data) = checked_mem_write(addr, width, data)
 
 /* NOTE: The wreg effect is due to MMIO, the rreg is due to checking mtime. */
 val mem_write_value : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(unit) effect {wmv, rreg, wreg, escape}
-- 
cgit v1.2.3


From 705ce9aa335f221267b6c8f005b2037b45a6dbe9 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Tue, 10 Jul 2018 10:53:35 -0700
Subject: Start adding c-backend bits for riscv.

---
 riscv/Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/riscv/Makefile b/riscv/Makefile
index 9633f0d4..4a396048 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -32,6 +32,9 @@ coverage: _sbuild/coverage.native
 	mkdir bisect && mv bisect*.out bisect/
 	mkdir coverage && bisect-ppx-report -html coverage/ -I _sbuild/ bisect/bisect*.out
 
+riscv.c: $(SAIL_SRCS) Makefile
+	$(SAIL) -O -memo_z3 -c $(SAIL_SRCS) 1> $@
+
 tracecmp: tracecmp.ml
 	ocamlfind ocamlopt -annot -linkpkg -package unix $^ -o $@
 
-- 
cgit v1.2.3


From a63b240d23701338e326a420bcaadc83f4370af0 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 10 Jul 2018 19:54:38 +0100
Subject: Coq MIPS snapshot

---
 snapshots/coq/README                             |    2 +
 snapshots/coq/build                              |   19 +
 snapshots/coq/clean                              |   11 +
 snapshots/coq/lib/coq/Makefile                   |   24 +
 snapshots/coq/lib/coq/Sail2_impl_base.v          | 1058 ++++
 snapshots/coq/lib/coq/Sail2_instr_kinds.v        |  253 +
 snapshots/coq/lib/coq/Sail2_operators.v          |  237 +
 snapshots/coq/lib/coq/Sail2_operators_bitlists.v |  187 +
 snapshots/coq/lib/coq/Sail2_operators_mwords.v   |  438 ++
 snapshots/coq/lib/coq/Sail2_prompt.v             |  122 +
 snapshots/coq/lib/coq/Sail2_prompt_monad.v       |  252 +
 snapshots/coq/lib/coq/Sail2_state.v              |   74 +
 snapshots/coq/lib/coq/Sail2_state_monad.v        |  258 +
 snapshots/coq/lib/coq/Sail2_values.v             | 1576 ++++++
 snapshots/coq/lib/coq/_CoqProject                |    2 +
 snapshots/coq/mips/_CoqProject                   |    2 +
 snapshots/coq/mips/mips.v                        | 5890 ++++++++++++++++++++++
 snapshots/coq/mips/mips_extras.v                 |  162 +
 snapshots/coq/mips/mips_types.v                  | 1441 ++++++
 19 files changed, 12008 insertions(+)
 create mode 100644 snapshots/coq/README
 create mode 100755 snapshots/coq/build
 create mode 100755 snapshots/coq/clean
 create mode 100644 snapshots/coq/lib/coq/Makefile
 create mode 100644 snapshots/coq/lib/coq/Sail2_impl_base.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_instr_kinds.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_operators.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_operators_bitlists.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_operators_mwords.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_prompt.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_prompt_monad.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_state.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_state_monad.v
 create mode 100644 snapshots/coq/lib/coq/Sail2_values.v
 create mode 100644 snapshots/coq/lib/coq/_CoqProject
 create mode 100644 snapshots/coq/mips/_CoqProject
 create mode 100644 snapshots/coq/mips/mips.v
 create mode 100644 snapshots/coq/mips/mips_extras.v
 create mode 100644 snapshots/coq/mips/mips_types.v

diff --git a/snapshots/coq/README b/snapshots/coq/README
new file mode 100644
index 00000000..bd7f12d0
--- /dev/null
+++ b/snapshots/coq/README
@@ -0,0 +1,2 @@
+Check out a copy of https://github.com/mit-plv/bbv in the parent directory and
+build it.  Then run ./build.
diff --git a/snapshots/coq/build b/snapshots/coq/build
new file mode 100755
index 00000000..e672912e
--- /dev/null
+++ b/snapshots/coq/build
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+if [ ! -d mips ]; then
+  echo Run clean from the coq directory
+  exit 1
+fi
+
+if [ ! -d ../bbv ]; then
+  echo 'Check out a copy of https://github.com/mit-plv/bbv in the parent directory and build it.'
+  exit 1
+fi
+
+set -ex
+cd lib/coq
+make
+cd ../../mips
+coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_extras.v
+coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_types.v
+coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips.v
diff --git a/snapshots/coq/clean b/snapshots/coq/clean
new file mode 100755
index 00000000..0d6f8785
--- /dev/null
+++ b/snapshots/coq/clean
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+if [ ! -d mips ]; then
+  echo Run clean from the coq directory
+  exit 1
+fi
+
+set -ex 
+rm -f mips/*.vo
+cd lib/coq
+make clean
diff --git a/snapshots/coq/lib/coq/Makefile b/snapshots/coq/lib/coq/Makefile
new file mode 100644
index 00000000..97869e3c
--- /dev/null
+++ b/snapshots/coq/lib/coq/Makefile
@@ -0,0 +1,24 @@
+BBV_DIR=../../../bbv/theories
+
+SRC=Sail2_prompt_monad.v  Sail2_prompt.v  Sail2_impl_base.v  Sail2_instr_kinds.v  Sail2_operators_bitlists.v  Sail2_operators_mwords.v  Sail2_operators.v  Sail2_values.v  Sail2_state_monad.v  Sail2_state.v
+
+COQ_LIBS = -R . Sail -R "$(BBV_DIR)" bbv
+
+TARGETS=$(SRC:.v=.vo)
+
+.PHONY: all clean *.ide
+
+all: $(TARGETS)
+clean:
+	rm -f -- $(TARGETS) $(TARGETS:.vo=.glob) $(TARGETS:%.vo=.%.aux) deps
+
+%.vo: %.v
+	coqc $(COQ_LIBS) $<
+
+%.ide: %.v
+	coqide $(COQ_LIBS) $<
+
+deps: $(SRC)
+	coqdep $(COQ_LIBS) $(SRC) > deps
+
+-include deps
diff --git a/snapshots/coq/lib/coq/Sail2_impl_base.v b/snapshots/coq/lib/coq/Sail2_impl_base.v
new file mode 100644
index 00000000..639083f6
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_impl_base.v
@@ -0,0 +1,1058 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_instr_kinds.
+
+(*
+class ( EnumerationType 'a ) 
+  val toNat : 'a -> nat
+end
+
+
+val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering
+let ~{ocaml} enumeration_typeCompare e1 e2 =
+  compare (toNat e1) (toNat e2)
+let inline {ocaml} enumeration_typeCompare = defaultCompare
+
+ 
+default_instance forall 'a. EnumerationType 'a => (Ord 'a)
+  let compare = enumeration_typeCompare
+  let (<)  r1 r2 = (enumeration_typeCompare r1 r2) = LT
+  let (<=) r1 r2 = (enumeration_typeCompare r1 r2) <> GT
+  let (>)  r1 r2 = (enumeration_typeCompare r1 r2) = GT
+  let (>=) r1 r2 = (enumeration_typeCompare r1 r2) <> LT
+end
+
+
+
+(* maybe isn't a member of type Ord - this should be in the Lem standard library*)
+instance forall 'a. Ord 'a => (Ord (maybe 'a))
+  let compare = maybeCompare compare
+  let (<)  r1 r2 = (maybeCompare compare r1 r2) = LT
+  let (<=) r1 r2 = (maybeCompare compare r1 r2) <> GT
+  let (>)  r1 r2 = (maybeCompare compare r1 r2) = GT
+  let (>=) r1 r2 = (maybeCompare compare r1 r2) <> LT
+end
+
+type word8 = nat (* bounded at a byte, for when lem supports it*)
+
+type end_flag =
+  | E_big_endian
+  | E_little_endian
+
+type bit =
+  | Bitc_zero
+  | Bitc_one
+
+type bit_lifted = 
+  | Bitl_zero
+  | Bitl_one
+  | Bitl_undef    (* used for modelling h/w arch unspecified bits *)
+  | Bitl_unknown  (* used for interpreter analysis exhaustive execution *)
+
+type direction = 
+  | D_increasing
+  | D_decreasing
+
+let dir_of_bool is_inc = if is_inc then D_increasing else D_decreasing
+let bool_of_dir = function
+  | D_increasing -> true
+  | D_decreasing -> false
+  end
+
+(* at some point this should probably not mention bit_lifted anymore *)
+type register_value = <| 
+    rv_bits: list bit_lifted (* MSB first, smallest index number *); 
+    rv_dir: direction; 
+    rv_start: nat ;
+    rv_start_internal: nat; 
+    (*when dir is increasing, rv_start = rv_start_internal. 
+      Otherwise, tells interpreter how to reconstruct a proper decreasing value*)
+    |>
+
+type byte_lifted = Byte_lifted of list bit_lifted (* of length 8 *) (*MSB first everywhere*)
+
+type instruction_field_value = list bit
+
+type byte = Byte of list bit (* of length 8 *)  (*MSB first everywhere*) 
+
+type address_lifted = Address_lifted of list byte_lifted (* of length 8 for 64bit machines*) * maybe integer
+(* for both values of end_flag, MSBy first *)
+
+type memory_byte = byte_lifted (* of length 8 *) (*MSB first everywhere*)
+
+type memory_value = list memory_byte
+(* the list is of length >=1 *)
+(* the head of the list is the byte stored at the lowest address;
+when calling a Sail function with a wmv effect, the least significant 8
+bits of the bit vector passed to the function will be interpreted as
+the lowest address byte; similarly, when calling a Sail function with
+rmem effect, the lowest address byte will be placed in the least
+significant 8 bits of the bit vector returned by the function; this
+behaviour is consistent with little-endian. *)
+
+
+(* not sure which of these is more handy yet *)
+type address = Address of list byte (* of length 8 *) * integer
+(* type address = Address of integer *)
+
+type opcode = Opcode of list byte (* of length 4 *)
+
+(** typeclass instantiations *)
+
+instance (EnumerationType bit)
+  let toNat = function
+    | Bitc_zero -> 0
+    | Bitc_one -> 1
+  end
+end
+
+instance (EnumerationType bit_lifted)
+  let toNat = function
+    | Bitl_zero -> 0
+    | Bitl_one -> 1
+    | Bitl_undef -> 2
+    | Bitl_unknown -> 3
+  end
+end
+
+let ~{ocaml} byte_liftedCompare (Byte_lifted b1) (Byte_lifted b2) = compare b1 b2
+let inline {ocaml} byte_liftedCompare = defaultCompare
+
+let ~{ocaml} byte_liftedLess b1 b2      = byte_liftedCompare b1 b2 =  LT
+let ~{ocaml} byte_liftedLessEq b1 b2    = byte_liftedCompare b1 b2 <> GT
+let ~{ocaml} byte_liftedGreater b1 b2   = byte_liftedCompare b1 b2 =  GT
+let ~{ocaml} byte_liftedGreaterEq b1 b2 = byte_liftedCompare b1 b2 <> LT
+
+let inline {ocaml} byte_liftedLess      = defaultLess
+let inline {ocaml} byte_liftedLessEq    = defaultLessEq
+let inline {ocaml} byte_liftedGreater   = defaultGreater
+let inline {ocaml} byte_liftedGreaterEq = defaultGreaterEq
+
+instance (Ord byte_lifted)
+  let compare = byte_liftedCompare
+  let (<)  = byte_liftedLess
+  let (<=) = byte_liftedLessEq
+  let (>)  = byte_liftedGreater
+  let (>=) = byte_liftedGreaterEq
+end
+
+let ~{ocaml} byteCompare (Byte b1) (Byte b2) = compare b1 b2
+let inline {ocaml} byteCompare = defaultCompare
+
+let ~{ocaml} byteLess b1 b2      = byteCompare b1 b2 =  LT
+let ~{ocaml} byteLessEq b1 b2    = byteCompare b1 b2 <> GT
+let ~{ocaml} byteGreater b1 b2   = byteCompare b1 b2 =  GT
+let ~{ocaml} byteGreaterEq b1 b2 = byteCompare b1 b2 <> LT
+
+let inline {ocaml} byteLess      = defaultLess
+let inline {ocaml} byteLessEq    = defaultLessEq
+let inline {ocaml} byteGreater   = defaultGreater
+let inline {ocaml} byteGreaterEq = defaultGreaterEq
+
+instance (Ord byte)
+  let compare = byteCompare
+  let (<)  = byteLess
+  let (<=) = byteLessEq
+  let (>)  = byteGreater
+  let (>=) = byteGreaterEq
+end
+
+
+
+
+
+let ~{ocaml} opcodeCompare (Opcode o1) (Opcode o2) =
+  compare o1 o2
+let {ocaml} opcodeCompare = defaultCompare
+
+let ~{ocaml} opcodeLess b1 b2      = opcodeCompare b1 b2 =  LT
+let ~{ocaml} opcodeLessEq b1 b2    = opcodeCompare b1 b2 <> GT
+let ~{ocaml} opcodeGreater b1 b2   = opcodeCompare b1 b2 =  GT
+let ~{ocaml} opcodeGreaterEq b1 b2 = opcodeCompare b1 b2 <> LT
+
+let inline {ocaml} opcodeLess      = defaultLess
+let inline {ocaml} opcodeLessEq    = defaultLessEq
+let inline {ocaml} opcodeGreater   = defaultGreater
+let inline {ocaml} opcodeGreaterEq = defaultGreaterEq
+
+instance (Ord opcode)
+  let compare = opcodeCompare
+  let (<)  = opcodeLess
+  let (<=) = opcodeLessEq
+  let (>)  = opcodeGreater
+  let (>=) = opcodeGreaterEq
+end
+
+let addressCompare (Address b1 i1) (Address b2 i2) = compare i1 i2
+(* this cannot be defaultCompare for OCaml because addresses contain big ints *)
+
+let addressLess b1 b2      = addressCompare b1 b2 =  LT
+let addressLessEq b1 b2    = addressCompare b1 b2 <> GT
+let addressGreater b1 b2   = addressCompare b1 b2 =  GT
+let addressGreaterEq b1 b2 = addressCompare b1 b2 <> LT
+
+instance (SetType address)
+  let setElemCompare = addressCompare
+end
+
+instance (Ord address)
+  let compare = addressCompare
+  let (<)  = addressLess
+  let (<=) = addressLessEq
+  let (>)  = addressGreater
+  let (>=) = addressGreaterEq
+end
+
+let {coq; ocaml} addressEqual a1 a2 = (addressCompare a1 a2) = EQ
+let inline {hol; isabelle} addressEqual = unsafe_structural_equality
+
+let {coq; ocaml} addressInequal a1 a2 = not (addressEqual a1 a2)
+let inline {hol; isabelle} addressInequal = unsafe_structural_inequality
+
+instance  (Eq address)
+  let (=)  = addressEqual
+  let (<>) = addressInequal
+end
+
+let ~{ocaml} directionCompare d1 d2 =
+  match (d1, d2) with
+  | (D_decreasing, D_increasing) -> GT
+  | (D_increasing, D_decreasing) -> LT
+  | _ -> EQ
+  end
+let inline {ocaml} directionCompare = defaultCompare
+
+let ~{ocaml} directionLess b1 b2      = directionCompare b1 b2 =  LT
+let ~{ocaml} directionLessEq b1 b2    = directionCompare b1 b2 <> GT
+let ~{ocaml} directionGreater b1 b2   = directionCompare b1 b2 =  GT
+let ~{ocaml} directionGreaterEq b1 b2 = directionCompare b1 b2 <> LT
+
+let inline {ocaml} directionLess      = defaultLess
+let inline {ocaml} directionLessEq    = defaultLessEq
+let inline {ocaml} directionGreater   = defaultGreater
+let inline {ocaml} directionGreaterEq = defaultGreaterEq
+
+instance (Ord direction)
+  let compare = directionCompare
+  let (<)  = directionLess
+  let (<=) = directionLessEq
+  let (>)  = directionGreater
+  let (>=) = directionGreaterEq
+end
+
+instance (Show direction)
+  let show = function D_increasing -> "D_increasing" | D_decreasing  -> "D_decreasing" end
+end
+
+let ~{ocaml} register_valueCompare rv1 rv2 =
+  compare (rv1.rv_bits, rv1.rv_dir, rv1.rv_start, rv1.rv_start_internal)
+          (rv2.rv_bits, rv2.rv_dir, rv2.rv_start, rv2.rv_start_internal)
+let inline {ocaml} register_valueCompare = defaultCompare
+
+let ~{ocaml} register_valueLess b1 b2      = register_valueCompare b1 b2 =  LT
+let ~{ocaml} register_valueLessEq b1 b2    = register_valueCompare b1 b2 <> GT
+let ~{ocaml} register_valueGreater b1 b2   = register_valueCompare b1 b2 =  GT
+let ~{ocaml} register_valueGreaterEq b1 b2 = register_valueCompare b1 b2 <> LT
+
+let inline {ocaml} register_valueLess      = defaultLess
+let inline {ocaml} register_valueLessEq    = defaultLessEq
+let inline {ocaml} register_valueGreater   = defaultGreater
+let inline {ocaml} register_valueGreaterEq = defaultGreaterEq
+
+instance (Ord register_value)
+  let compare = register_valueCompare
+  let (<)  = register_valueLess
+  let (<=) = register_valueLessEq
+  let (>)  = register_valueGreater
+  let (>=) = register_valueGreaterEq
+end
+
+let address_liftedCompare (Address_lifted b1 i1) (Address_lifted b2 i2) =
+  compare (i1,b1) (i2,b2)
+(* this cannot be defaultCompare for OCaml because address_lifteds contain big
+   ints *)
+
+let address_liftedLess b1 b2      = address_liftedCompare b1 b2 =  LT
+let address_liftedLessEq b1 b2    = address_liftedCompare b1 b2 <> GT
+let address_liftedGreater b1 b2   = address_liftedCompare b1 b2 =  GT
+let address_liftedGreaterEq b1 b2 = address_liftedCompare b1 b2 <> LT
+
+instance (Ord address_lifted)
+  let compare = address_liftedCompare
+  let (<)  = address_liftedLess
+  let (<=) = address_liftedLessEq
+  let (>)  = address_liftedGreater
+  let (>=) = address_liftedGreaterEq
+end
+
+(* Registers *)
+type slice = (nat * nat)
+
+type reg_name = 
+  (* do we really need this here if ppcmem already has this information by itself? *)
+| Reg of string * nat * nat * direction
+(*Name of the register, accessing the entire register, the start and size of this register, and its direction *)
+
+| Reg_slice of string * nat * direction * slice 
+(* Name of the register, accessing from the bit indexed by the first
+to the bit indexed by the second integer of the slice, inclusive. For
+machineDef* the first is a smaller number or equal to the second, adjusted
+to reflect the correct span direction in the interpreter side.  *)
+
+| Reg_field of string * nat * direction * string * slice 
+(*Name of the register, start and direction, and name of the field of the register
+accessed. The slice specifies where this field is in the register*)
+
+| Reg_f_slice of string * nat * direction * string * slice * slice 
+(* The first four components are as in Reg_field; the final slice
+specifies a part of the field, indexed w.r.t. the register as a whole *)
+
+let register_base_name : reg_name -> string = function
+  | Reg s _ _ _             -> s
+  | Reg_slice s _ _ _       -> s
+  | Reg_field s _ _ _ _     -> s
+  | Reg_f_slice s _ _ _ _ _ -> s
+  end
+
+let slice_of_reg_name : reg_name -> slice = function
+  | Reg _ start width D_increasing -> (start, start + width -1)
+  | Reg _ start width D_decreasing -> (start - width - 1, start)
+  | Reg_slice _ _ _ sl             -> sl
+  | Reg_field _ _ _ _ sl           -> sl
+  | Reg_f_slice _ _ _ _ _ sl       -> sl
+  end
+
+let width_of_reg_name (r: reg_name) : nat =
+  let width_of_slice (i, j) = (* j - i + 1 in *)
+
+    (integerFromNat j) - (integerFromNat i) + 1
+    $> abs $> natFromInteger
+  in
+  match r with
+  | Reg _ _ width _          -> width
+  | Reg_slice _ _ _ sl       -> width_of_slice sl
+  | Reg_field _ _ _ _ sl     -> width_of_slice sl
+  | Reg_f_slice _ _ _ _ _ sl -> width_of_slice sl
+  end
+
+let reg_name_non_empty_intersection (r: reg_name) (r': reg_name) : bool = 
+  register_base_name r = register_base_name r' &&
+  let (i1,  i2)  = slice_of_reg_name r in
+  let (i1', i2') = slice_of_reg_name r' in
+  i1' <= i2 && i2' >= i1
+
+let reg_nameCompare r1 r2 = 
+  compare (register_base_name r1,slice_of_reg_name r1)
+          (register_base_name r2,slice_of_reg_name r2)
+
+let reg_nameLess b1 b2      = reg_nameCompare b1 b2 =  LT
+let reg_nameLessEq b1 b2    = reg_nameCompare b1 b2 <> GT
+let reg_nameGreater b1 b2   = reg_nameCompare b1 b2 =  GT
+let reg_nameGreaterEq b1 b2 = reg_nameCompare b1 b2 <> LT
+
+instance (Ord reg_name)
+  let compare = reg_nameCompare
+  let (<)  = reg_nameLess
+  let (<=) = reg_nameLessEq
+  let (>)  = reg_nameGreater
+  let (>=) = reg_nameGreaterEq
+end
+
+let {coq;ocaml} reg_nameEqual a1 a2 = (reg_nameCompare a1 a2) = EQ
+let {hol;isabelle} reg_nameEqual = unsafe_structural_equality
+let {coq;ocaml} reg_nameInequal a1 a2 = not (reg_nameEqual a1 a2)
+let {hol;isabelle} reg_nameInequal = unsafe_structural_inequality
+
+instance (Eq reg_name)
+  let (=)  = reg_nameEqual
+  let (<>) = reg_nameInequal
+end
+
+instance (SetType reg_name)
+  let setElemCompare = reg_nameCompare
+end
+
+let direction_of_reg_name r = match r with
+  | Reg _ _ _ d -> d
+  | Reg_slice _ _ d _ -> d
+  | Reg_field _ _ d _ _ -> d
+  | Reg_f_slice _ _ d _ _ _ -> d
+ end
+
+let start_of_reg_name r = match r with
+  | Reg _ start _ _ -> start
+  | Reg_slice _ start _ _ -> start
+  | Reg_field _ start _ _ _ -> start
+  | Reg_f_slice _ start _ _ _ _ -> start
+end
+
+(* Data structures for building up instructions *)
+
+(* read_kind, write_kind, barrier_kind, trans_kind and instruction_kind have
+   been moved to sail_instr_kinds.lem.  This removes the dependency of the
+   shallow embedding on the rest of sail_impl_base.lem, and helps avoid name
+   clashes between the different monad types. *)
+
+type event = 
+  | E_read_mem of read_kind * address_lifted * nat * maybe (list reg_name)
+  | E_read_memt of read_kind * address_lifted * nat * maybe (list reg_name)
+  | E_write_mem of write_kind * address_lifted * nat * maybe (list reg_name) * memory_value * maybe (list reg_name)
+  | E_write_ea of write_kind * address_lifted * nat * maybe (list reg_name)
+  | E_excl_res
+  | E_write_memv of maybe address_lifted * memory_value * maybe (list reg_name)
+  | E_write_memvt of maybe address_lifted * (bit_lifted * memory_value) * maybe (list reg_name)
+  | E_barrier of barrier_kind
+  | E_footprint 
+  | E_read_reg of reg_name
+  | E_write_reg of reg_name * register_value
+  | E_escape
+  | E_error of string 
+
+
+let eventCompare e1 e2 = 
+  match (e1,e2) with
+  | (E_read_mem rk1 v1 i1 tr1, E_read_mem rk2 v2 i2 tr2) ->
+     compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2)) 
+  | (E_read_memt rk1 v1 i1 tr1, E_read_memt rk2 v2 i2 tr2) ->
+     compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2)) 
+  | (E_write_mem wk1 v1 i1 tr1 v1' tr1', E_write_mem wk2 v2 i2 tr2 v2' tr2') -> 
+    compare ((wk1,v1,i1),(tr1,v1',tr1'))  ((wk2,v2,i2),(tr2,v2',tr2')) 
+  | (E_write_ea wk1 a1 i1 tr1, E_write_ea wk2 a2 i2 tr2) ->
+    compare (wk1, (a1, i1, tr1)) (wk2, (a2, i2, tr2))
+  | (E_excl_res, E_excl_res) -> EQ
+  | (E_write_memv _ mv1 tr1, E_write_memv _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2)
+  | (E_write_memvt _ mv1 tr1, E_write_memvt _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2)
+  | (E_barrier bk1, E_barrier bk2) -> compare bk1 bk2
+  | (E_read_reg r1, E_read_reg r2) -> compare r1 r2
+  | (E_write_reg r1 v1, E_write_reg r2 v2) -> compare (r1,v1) (r2,v2)
+  | (E_error s1, E_error s2) -> compare s1 s2
+  | (E_escape,E_escape) -> EQ
+  | (E_read_mem _ _ _ _, _) -> LT
+  | (E_write_mem _ _ _ _ _ _, _) -> LT
+  | (E_write_ea _ _ _ _, _) -> LT
+  | (E_excl_res, _) -> LT
+  | (E_write_memv _ _ _, _) -> LT
+  | (E_barrier _, _) -> LT
+  | (E_read_reg _, _) -> LT
+  | (E_write_reg _ _, _) -> LT
+  | _ -> GT
+  end
+
+let eventLess b1 b2      = eventCompare b1 b2 =  LT
+let eventLessEq b1 b2    = eventCompare b1 b2 <> GT
+let eventGreater b1 b2   = eventCompare b1 b2 =  GT
+let eventGreaterEq b1 b2 = eventCompare b1 b2 <> LT
+
+instance (Ord event)
+  let compare = eventCompare
+  let (<)  = eventLess
+  let (<=) = eventLessEq
+  let (>)  = eventGreater
+  let (>=) = eventGreaterEq
+end
+
+instance (SetType event)
+  let setElemCompare = compare
+end
+
+
+(* the address_lifted types should go away here and be replaced by address *)
+type with_aux 'o = 'o * maybe ((unit -> (string * string)) * ((list (reg_name * register_value)) -> list event))
+type outcome 'a 'e =
+  (* Request to read memory, value is location to read, integer is size to read,
+     followed by registers that were used in computing that size *)
+  | Read_mem of (read_kind * address_lifted * nat) * (memory_value -> with_aux (outcome 'a 'e))
+  (* Tell the system a write is imminent, at address lifted, of size nat *)
+  | Write_ea of (write_kind * address_lifted * nat) * (with_aux (outcome 'a 'e))
+  (* Request the result of store-exclusive *)
+  | Excl_res of (bool -> with_aux (outcome 'a 'e))
+  (* Request to write memory at last signalled address. Memory value should be 8
+     times the size given in ea signal *)
+  | Write_memv of memory_value * (bool -> with_aux (outcome 'a 'e))
+  (* Request a memory barrier *)
+  | Barrier of barrier_kind * with_aux (outcome 'a 'e)
+  (* Tell the system to dynamically recalculate dependency footprint *)
+  | Footprint of with_aux (outcome 'a 'e)
+  (* Request to read register, will track dependency when mode.track_values *)
+  | Read_reg of reg_name * (register_value -> with_aux (outcome 'a 'e))
+  (* Request to write register *)
+  | Write_reg of (reg_name * register_value) * with_aux (outcome 'a 'e)
+  | Escape of maybe string
+  (*Result of a failed assert with possible error message to report*)
+  | Fail of maybe string
+  (* Exception of type 'e *)
+  | Exception of 'e
+  | Internal of (maybe string * maybe (unit -> string)) * with_aux (outcome 'a 'e)
+  | Done of 'a
+  | Error of string
+
+type outcome_s 'a 'e = with_aux (outcome 'a 'e)
+(* first string : output of instruction_stack_to_string
+   second string: output of local_variables_to_string *)
+
+(** operations and coercions on basic values *)
+
+val word8_to_bitls : word8 -> list bit_lifted
+val bitls_to_word8 : list bit_lifted -> word8
+
+val integer_of_word8_list : list word8 -> integer
+val word8_list_of_integer : integer -> integer -> list word8 
+
+val concretizable_bitl : bit_lifted -> bool
+val concretizable_bytl : byte_lifted -> bool
+val concretizable_bytls : list byte_lifted -> bool
+
+let concretizable_bitl = function
+  | Bitl_zero -> true
+  | Bitl_one -> true
+  | Bitl_undef -> false
+  | Bitl_unknown -> false
+end 
+
+let concretizable_bytl (Byte_lifted bs) = List.all concretizable_bitl bs
+let concretizable_bytls = List.all concretizable_bytl
+
+(* constructing values *)
+
+val build_register_value : list bit_lifted -> direction -> nat -> nat -> register_value
+let build_register_value bs dir width start_index =
+  <| rv_bits = bs;
+     rv_dir = dir; (* D_increasing for Power, D_decreasing for ARM *)
+     rv_start_internal = start_index; 
+     rv_start = if dir = D_increasing
+       then start_index
+       else (start_index+1) - width; (* Smaller index, as in Power, for external interaction *)
+  |>
+
+val register_value : bit_lifted -> direction -> nat -> nat -> register_value
+let register_value b dir width start_index = 
+  build_register_value (List.replicate width b) dir width start_index
+
+val register_value_zeros : direction -> nat -> nat -> register_value
+let register_value_zeros dir width start_index = 
+  register_value Bitl_zero dir width start_index
+
+val register_value_ones : direction -> nat -> nat -> register_value
+let register_value_ones dir width start_index = 
+  register_value Bitl_one dir width start_index
+
+val register_value_for_reg : reg_name -> list bit_lifted -> register_value
+let register_value_for_reg r bs : register_value =
+  let () = ensure (width_of_reg_name r = List.length bs)
+      ("register_value_for_reg (\"" ^ show (register_base_name r) ^ "\") length mismatch: "
+          ^ show (width_of_reg_name r) ^ " vs " ^ show (List.length bs))
+  in
+  let (j1, j2) = slice_of_reg_name r in
+  let d = direction_of_reg_name r in
+  <|  rv_bits = bs;
+      rv_dir = d;
+      rv_start_internal = if d = D_increasing then j1 else (start_of_reg_name r) - j1;
+      rv_start = j1;
+  |>
+
+val byte_lifted_undef : byte_lifted
+let byte_lifted_undef = Byte_lifted (List.replicate 8 Bitl_undef)
+
+val byte_lifted_unknown : byte_lifted
+let byte_lifted_unknown = Byte_lifted (List.replicate 8 Bitl_unknown)
+  
+val memory_value_unknown : nat (*the number of bytes*) -> memory_value
+let memory_value_unknown (width:nat) : memory_value = 
+  List.replicate width byte_lifted_unknown 
+
+val memory_value_undef : nat (*the number of bytes*) -> memory_value
+let memory_value_undef (width:nat) : memory_value = 
+  List.replicate width byte_lifted_undef 
+
+val match_endianness : forall 'a. end_flag -> list 'a -> list 'a
+let match_endianness endian l =
+  match endian with
+  | E_little_endian -> List.reverse l
+  | E_big_endian    -> l
+  end
+
+(* lengths *)  
+
+val memory_value_length : memory_value -> nat
+let memory_value_length (mv:memory_value) = List.length mv
+
+
+(* aux fns *)
+
+val maybe_all : forall 'a.  list (maybe 'a) -> maybe (list 'a)
+let rec maybe_all' xs acc = 
+  match xs with
+  | [] -> Just (List.reverse acc)
+  | Nothing :: _ -> Nothing
+  | (Just y)::xs' -> maybe_all' xs' (y::acc)
+  end
+let maybe_all xs = maybe_all' xs [] 
+
+(** coercions *)
+
+(* bits and bytes *)
+
+let bit_to_bool = function (* TODO: rename bool_of_bit *)
+  | Bitc_zero -> false
+  | Bitc_one -> true
+end
+
+
+val bit_lifted_of_bit : bit -> bit_lifted
+let bit_lifted_of_bit b = 
+  match b with
+  | Bitc_zero -> Bitl_zero
+  | Bitc_one -> Bitl_one
+  end
+
+val bit_of_bit_lifted : bit_lifted -> maybe bit
+let bit_of_bit_lifted bl =
+  match bl with
+  | Bitl_zero -> Just Bitc_zero
+  | Bitl_one -> Just Bitc_one
+  | Bitl_undef -> Nothing
+  | Bitl_unknown -> Nothing
+  end
+
+
+val byte_lifted_of_byte : byte -> byte_lifted
+let byte_lifted_of_byte (Byte bs) : byte_lifted = Byte_lifted (List.map bit_lifted_of_bit bs)
+
+val byte_of_byte_lifted : byte_lifted -> maybe byte
+let byte_of_byte_lifted bl = 
+  match bl with
+  | Byte_lifted bls -> 
+      match maybe_all (List.map bit_of_bit_lifted bls) with
+      | Nothing -> Nothing
+      | Just bs -> Just (Byte bs)
+      end
+  end
+
+
+val bytes_of_bits : list bit -> list byte (*assumes (length bits) mod 8 = 0*)
+let rec bytes_of_bits bits = match bits with
+  | [] -> []
+  | b0::b1::b2::b3::b4::b5::b6::b7::bits -> 
+    (Byte [b0;b1;b2;b3;b4;b5;b6;b7])::(bytes_of_bits bits)
+  | _ -> failwith "bytes_of_bits not given bits divisible by 8"
+end
+
+val byte_lifteds_of_bit_lifteds : list bit_lifted -> list byte_lifted (*assumes (length bits) mod 8 = 0*)
+let rec byte_lifteds_of_bit_lifteds bits = match bits with
+  | [] -> []
+  | b0::b1::b2::b3::b4::b5::b6::b7::bits -> 
+    (Byte_lifted [b0;b1;b2;b3;b4;b5;b6;b7])::(byte_lifteds_of_bit_lifteds bits)
+  | _ -> failwith "byte_lifteds of bit_lifteds not given bits divisible by 8"
+end
+
+
+val byte_of_memory_byte : memory_byte -> maybe byte
+let byte_of_memory_byte = byte_of_byte_lifted
+
+val memory_byte_of_byte : byte -> memory_byte
+let memory_byte_of_byte = byte_lifted_of_byte
+
+
+(* to and from nat *)
+
+(* this natFromBoolList could move to the Lem word.lem library *)
+val natFromBoolList : list bool -> nat
+let rec natFromBoolListAux (acc : nat) (bl : list bool) = 
+  match bl with 
+    | [] -> acc
+    | (true :: bl') -> natFromBoolListAux ((acc * 2) + 1) bl'
+    | (false :: bl') -> natFromBoolListAux (acc * 2) bl'
+  end
+let natFromBoolList bl = 
+  natFromBoolListAux 0 (List.reverse bl)
+
+
+val nat_of_bit_list : list bit -> nat 
+let nat_of_bit_list b =
+  natFromBoolList (List.reverse (List.map bit_to_bool b))
+  (* natFromBoolList takes a list with LSB first, for consistency with rest of Lem word library, so we reverse it. twice. *)
+
+
+(* to and from integer *)
+
+val integer_of_bit_list : list bit -> integer 
+let integer_of_bit_list b =
+  integerFromBoolList (false,(List.reverse (List.map bit_to_bool b)))
+  (* integerFromBoolList takes a list with LSB first, so we reverse it *)
+
+val bit_list_of_integer : nat -> integer -> list bit 
+let bit_list_of_integer len b = 
+  List.map (fun b -> if b then Bitc_one else Bitc_zero) 
+    (reverse (boolListFrombitSeq len (bitSeqFromInteger Nothing b)))
+
+val integer_of_byte_list : list byte -> integer 
+let integer_of_byte_list bytes = integer_of_bit_list (List.concatMap (fun (Byte bs) -> bs) bytes)
+
+val byte_list_of_integer : nat -> integer -> list byte 
+let byte_list_of_integer (len:nat) (a:integer):list byte = 
+  let bits = bit_list_of_integer (len * 8) a in bytes_of_bits bits
+
+
+val integer_of_address : address -> integer 
+let integer_of_address (a:address):integer = 
+  match a with
+  | Address bs i -> i 
+  end
+
+val address_of_integer : integer -> address 
+let address_of_integer (i:integer):address =
+  Address (byte_list_of_integer 8 i) i
+
+(* to and from signed-integer *)
+
+val signed_integer_of_bit_list : list bit -> integer
+let signed_integer_of_bit_list b =
+  match b with
+  | [] -> failwith "empty bit list"
+  | Bitc_zero :: b' ->
+      integerFromBoolList (false,(List.reverse (List.map bit_to_bool b)))
+  | Bitc_one :: b' ->
+      let b'_val = integerFromBoolList (false,(List.reverse (List.map bit_to_bool b'))) in
+      (* integerFromBoolList takes a list with LSB first, so we reverse it *)
+      let msb_val = integerPow 2 ((List.length b) - 1) in
+      b'_val - msb_val
+  end
+
+
+(* regarding a list of int as a list of bytes in memory, MSB lowest-address first, convert to an integer *)
+val integer_address_of_int_list : list int -> integer
+let rec integerFromIntListAux (acc: integer) (is: list int) = 
+  match is with 
+  | [] -> acc
+  | (i :: is') -> integerFromIntListAux ((acc * 256) + integerFromInt i) is'
+  end
+let integer_address_of_int_list (is: list int) =
+  integerFromIntListAux 0 is
+
+val address_of_byte_list : list byte -> address 
+let address_of_byte_list bs = 
+  if List.length bs <> 8 then failwith "address_of_byte_list given list not of length 8" else 
+  Address bs (integer_of_byte_list bs)
+
+let address_of_byte_lifted_list bls =
+  match maybe_all (List.map byte_of_byte_lifted bls) with
+  | Nothing -> Nothing
+  | Just bs -> Just (address_of_byte_list bs)
+  end
+
+(* operations on addresses *)
+
+val add_address_nat : address -> nat -> address 
+let add_address_nat (a:address) (i:nat) : address = 
+  address_of_integer ((integer_of_address a) + (integerFromNat i))
+
+val clear_low_order_bits_of_address : address -> address 
+let clear_low_order_bits_of_address a = 
+  match a with 
+  | Address [b0;b1;b2;b3;b4;b5;b6;b7] i -> 
+      match b7 with
+      | Byte [bt0;bt1;bt2;bt3;bt4;bt5;bt6;bt7] -> 
+          let b7' = Byte [bt0;bt1;bt2;bt3;bt4;bt5;Bitc_zero;Bitc_zero] in
+	  let bytes = [b0;b1;b2;b3;b4;b5;b6;b7'] in
+          Address bytes (integer_of_byte_list bytes)
+      | _ -> failwith "Byte does not contain 8 bits"
+      end
+  | _ -> failwith "Address does not contain 8 bytes"
+  end
+
+
+
+val byte_list_of_memory_value : end_flag -> memory_value -> maybe (list byte)
+let byte_list_of_memory_value endian mv =
+  match_endianness endian mv
+  $> List.map byte_of_memory_byte
+  $> maybe_all
+
+
+val integer_of_memory_value : end_flag -> memory_value -> maybe integer
+let integer_of_memory_value endian (mv:memory_value):maybe integer =
+  match byte_list_of_memory_value endian mv with
+  | Just bs -> Just (integer_of_byte_list bs)
+  | Nothing -> Nothing 
+  end
+
+val memory_value_of_integer : end_flag  -> nat -> integer -> memory_value
+let memory_value_of_integer endian (len:nat) (i:integer):memory_value =
+  List.map byte_lifted_of_byte (byte_list_of_integer len i)
+  $> match_endianness endian
+
+
+val integer_of_register_value : register_value -> maybe integer 
+let integer_of_register_value (rv:register_value):maybe integer = 
+  match maybe_all (List.map bit_of_bit_lifted rv.rv_bits) with
+  | Nothing -> Nothing
+  | Just bs -> Just (integer_of_bit_list bs)
+  end
+
+(* NOTE: register_value_for_reg_of_integer might be easier to use *)
+val register_value_of_integer : nat -> nat -> direction -> integer -> register_value 
+let register_value_of_integer (len:nat) (start:nat) (dir:direction) (i:integer):register_value =
+  let bs = bit_list_of_integer len i in
+  build_register_value (List.map bit_lifted_of_bit bs) dir len start
+
+val register_value_for_reg_of_integer : reg_name -> integer -> register_value
+let register_value_for_reg_of_integer (r: reg_name) (i:integer) : register_value =
+  register_value_of_integer (width_of_reg_name r) (start_of_reg_name r) (direction_of_reg_name r) i
+
+(* *)
+
+val opcode_of_bytes : byte -> byte -> byte -> byte -> opcode
+let opcode_of_bytes b0 b1 b2 b3 : opcode = Opcode [b0;b1;b2;b3]
+
+val register_value_of_address : address -> direction -> register_value   
+let register_value_of_address (Address bytes _) dir : register_value = 
+  let bits = List.concatMap (fun (Byte bs) -> List.map bit_lifted_of_bit bs) bytes in
+   <| rv_bits = bits;
+      rv_dir = dir;
+      rv_start = 0; 
+      rv_start_internal = if dir = D_increasing then 0 else (List.length bits) - 1
+   |>
+
+val register_value_of_memory_value : memory_value -> direction -> register_value
+let register_value_of_memory_value bytes dir : register_value =
+  let bitls = List.concatMap (fun (Byte_lifted bs) -> bs) bytes in
+  <| rv_bits = bitls;
+     rv_dir = dir;
+     rv_start = 0;
+     rv_start_internal = if dir = D_increasing then 0 else (List.length bitls) - 1
+   |>                                                     
+
+val memory_value_of_register_value: register_value -> memory_value
+let memory_value_of_register_value r =
+  (byte_lifteds_of_bit_lifteds r.rv_bits)
+   
+val address_lifted_of_register_value : register_value -> maybe address_lifted
+(* returning Nothing iff the register value is not 64 bits wide, but
+allowing Bitl_undef and Bitl_unknown *)
+let address_lifted_of_register_value (rv:register_value) : maybe address_lifted = 
+  if List.length rv.rv_bits <> 64 then Nothing
+  else 
+    Just (Address_lifted (byte_lifteds_of_bit_lifteds rv.rv_bits)
+                         (if List.all concretizable_bitl rv.rv_bits 
+			  then match (maybe_all (List.map bit_of_bit_lifted rv.rv_bits)) with
+                              | (Just(bits)) -> Just (integer_of_bit_list bits)
+                              | Nothing -> Nothing end
+			  else Nothing))
+
+val address_of_address_lifted : address_lifted -> maybe address
+(* returning Nothing iff the address contains any Bitl_undef or Bitl_unknown *)
+let address_of_address_lifted (al:address_lifted): maybe address =
+  match al with
+  | Address_lifted bls (Just i)-> 
+      match maybe_all ((List.map byte_of_byte_lifted) bls) with
+      | Nothing -> Nothing
+      | Just bs -> Just (Address bs i)
+      end
+  | _ -> Nothing
+end
+
+val address_of_register_value : register_value -> maybe address
+(* returning Nothing iff the register value is not 64 bits wide, or contains Bitl_undef or Bitl_unknown *)
+let address_of_register_value (rv:register_value) : maybe address = 
+  match address_lifted_of_register_value rv with
+  | Nothing -> Nothing
+  | Just al -> 
+      match address_of_address_lifted al with
+      | Nothing -> Nothing
+      | Just a -> Just a
+      end
+  end
+
+let address_of_memory_value (endian: end_flag) (mv:memory_value) : maybe address =
+  match byte_list_of_memory_value endian mv with
+  | Nothing -> Nothing
+  | Just bs -> 
+      if List.length bs <> 8 then Nothing else
+      Just (address_of_byte_list bs)
+  end 
+
+val byte_of_int : int -> byte
+let byte_of_int (i:int) : byte = 
+  Byte (bit_list_of_integer 8 (integerFromInt i))
+
+val memory_byte_of_int : int -> memory_byte
+let memory_byte_of_int (i:int) : memory_byte = 
+  memory_byte_of_byte (byte_of_int i)
+
+(*
+val int_of_memory_byte : int -> maybe memory_byte
+let int_of_memory_byte (mb:memory_byte) : int = 
+  failwith "TODO"
+*)
+
+
+
+val memory_value_of_address_lifted : end_flag -> address_lifted -> memory_value
+let memory_value_of_address_lifted endian (Address_lifted bs _ :address_lifted) =
+  match_endianness endian bs
+
+val byte_list_of_address : address -> list byte
+let byte_list_of_address (Address bs _) : list byte = bs
+
+val memory_value_of_address : end_flag -> address -> memory_value
+let memory_value_of_address endian (Address bs _) =
+  match_endianness endian bs
+  $> List.map byte_lifted_of_byte
+
+val byte_list_of_opcode : opcode -> list byte
+let byte_list_of_opcode (Opcode bs) : list byte = bs
+
+(** ****************************************** *)
+(** show type class instantiations             *)
+(** ****************************************** *)
+
+(* matching printing_functions.ml *)
+val stringFromReg_name : reg_name -> string
+let stringFromReg_name r =
+  let norm_sl start dir (first,second) = (first,second)
+    (* match dir with
+      | D_increasing -> (first,second)
+      | D_decreasing -> (start - first, start - second)
+    end *)
+  in
+  match r with
+  | Reg s start size dir -> s
+  | Reg_slice s start dir sl ->
+      let (first,second) = norm_sl start dir sl in
+      s ^ "[" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]"
+  | Reg_field s start dir f sl ->
+      let (first,second) = norm_sl start dir sl in
+      s ^ "." ^ f ^ " (" ^ (show start) ^ ", " ^ (show dir) ^ ", " ^ (show first) ^ ", " ^ (show second) ^ ")"
+  | Reg_f_slice s start dir f (first1,second1) (first,second) ->
+      let (first,second) =
+        match dir with
+        | D_increasing -> (first,second)
+        | D_decreasing -> (start - first, start - second)
+        end in
+      s ^ "." ^ f ^ "]" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]"
+  end
+
+instance (Show reg_name)
+  let show = stringFromReg_name
+end
+
+
+(* hex pp of integers, adapting the Lem string_extra.lem code *)
+val stringFromNaturalHexHelper : natural -> list char -> list char
+let rec stringFromNaturalHexHelper n acc =
+  if n = 0 then
+    acc
+  else
+    stringFromNaturalHexHelper (n / 16) (String_extra.chr (natFromNatural (let nd = n mod 16 in if nd <=9 then nd + 48 else nd - 10 + 97)) :: acc)
+
+val stringFromNaturalHex : natural -> string
+let (*~{ocaml;hol}*) stringFromNaturalHex n = 
+  if n = 0 then "0" else toString (stringFromNaturalHexHelper n [])
+
+val stringFromIntegerHex : integer -> string
+let (*~{ocaml}*) stringFromIntegerHex i = 
+  if i < 0 then 
+    "-" ^ stringFromNaturalHex (naturalFromInteger i)
+  else
+    stringFromNaturalHex (naturalFromInteger i)
+
+
+let stringFromAddress (Address bs i) = 
+  let i' = integer_of_byte_list bs in
+  if i=i' then
+(*TODO: ideally this should be made to match the src/pp.ml pp_address; the following very roughly matches what's used in the ppcmem UI, enough to make exceptions readable *)
+    if i < 65535 then 
+      show i 
+    else
+      stringFromIntegerHex i
+  else
+    "stringFromAddress bytes and integer mismatch"
+
+instance (Show address)
+  let show = stringFromAddress
+end
+
+let stringFromByte_lifted bl =
+  match byte_of_byte_lifted bl with
+  | Nothing -> "u?"  
+  | Just (Byte bits) -> 
+      let i = integer_of_bit_list bits in
+      show i
+  end
+
+instance (Show byte_lifted)
+  let show = stringFromByte_lifted
+end
+
+(* possible next instruction address options *)
+type nia = 
+  | NIA_successor
+  | NIA_concrete_address of address
+  | NIA_indirect_address
+
+let niaCompare n1 n2 = match (n1,n2) with
+  | (NIA_successor, NIA_successor) -> EQ
+  | (NIA_successor, _) -> LT
+  | (_, NIA_successor) -> GT
+  | (NIA_concrete_address a1, NIA_concrete_address a2) -> compare a1 a2
+  | (NIA_concrete_address _, _) -> LT
+  | (_, NIA_concrete_address _) -> GT
+  | (NIA_indirect_address, NIA_indirect_address) -> EQ
+  (* | (NIA_indirect_address, _) -> LT
+  | (_, NIA_indirect_address) -> GT *)
+  end
+
+instance (Ord nia)
+  let compare = niaCompare
+  let (<)  n1 n2 = (niaCompare n1 n2) = LT
+  let (<=) n1 n2 = (niaCompare n1 n2) <> GT
+  let (>)  n1 n2 = (niaCompare n1 n2) = GT
+  let (>=) n1 n2 = (niaCompare n1 n2) <> LT
+end
+
+let stringFromNia = function
+  | NIA_successor          -> "NIA_successor"
+  | NIA_concrete_address a -> "NIA_concrete_address " ^ show a
+  | NIA_indirect_address   -> "NIA_indirect_address"
+end
+
+instance (Show nia)
+  let show = stringFromNia
+end
+
+type dia =
+  | DIA_none
+  | DIA_concrete_address of address
+  | DIA_register of reg_name
+
+let diaCompare d1 d2 = match (d1, d2) with
+  | (DIA_none, DIA_none) -> EQ
+  | (DIA_none, _) -> LT
+  | (DIA_concrete_address a1, DIA_none) -> GT
+  | (DIA_concrete_address a1, DIA_concrete_address a2) -> compare a1 a2
+  | (DIA_concrete_address a1, _) -> LT
+  | (DIA_register r1, DIA_register r2) -> compare r1 r2
+  | (DIA_register _, _) -> GT
+end
+
+instance (Ord dia)
+  let compare = diaCompare
+  let (<)  n1 n2 = (diaCompare n1 n2) = LT
+  let (<=) n1 n2 = (diaCompare n1 n2) <> GT
+  let (>)  n1 n2 = (diaCompare n1 n2) = GT
+  let (>=) n1 n2 = (diaCompare n1 n2) <> LT
+end
+
+let stringFromDia = function
+  | DIA_none               ->  "DIA_none"
+  | DIA_concrete_address a ->  "DIA_concrete_address " ^ show a
+  | DIA_register r ->  "DIA_delayed_register " ^ show r
+end
+
+instance (Show dia)
+  let show = stringFromDia
+end
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_instr_kinds.v b/snapshots/coq/lib/coq/Sail2_instr_kinds.v
new file mode 100644
index 00000000..0145d8b3
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_instr_kinds.v
@@ -0,0 +1,253 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+
+(*
+
+class ( EnumerationType 'a )
+  val toNat : 'a -> nat
+end
+
+
+val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering
+let ~{ocaml} enumeration_typeCompare e1 e2 :=
+  compare (toNat e1) (toNat e2)
+let inline {ocaml} enumeration_typeCompare := defaultCompare
+
+
+default_instance forall 'a. EnumerationType 'a => (Ord 'a)
+  let compare := enumeration_typeCompare
+  let (<)  r1 r2 := (enumeration_typeCompare r1 r2) = LT
+  let (<=) r1 r2 := (enumeration_typeCompare r1 r2) <> GT
+  let (>)  r1 r2 := (enumeration_typeCompare r1 r2) = GT
+  let (>=) r1 r2 := (enumeration_typeCompare r1 r2) <> LT
+end
+*)
+
+(* Data structures for building up instructions *)
+
+(* careful: changes in the read/write/barrier kinds have to be
+   reflected in deep_shallow_convert *)
+Inductive read_kind :=
+  (* common reads *)
+  | Read_plain
+  (* Power reads *)
+  | Read_reserve
+  (* AArch64 reads *)
+  | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+  (* RISC-V reads *)
+  | Read_RISCV_acquire  | Read_RISCV_strong_acquire
+  | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+  | Read_RISCV_reserved_strong_acquire
+  (* x86 reads *)
+  | Read_X86_locked (* the read part of a lock'd instruction (rmw) *)
+.
+(*
+instance (Show read_kind)
+  let show := function
+    | Read_plain -> "Read_plain"
+    | Read_reserve -> "Read_reserve"
+    | Read_acquire -> "Read_acquire"
+    | Read_exclusive -> "Read_exclusive"
+    | Read_exclusive_acquire -> "Read_exclusive_acquire"
+    | Read_stream -> "Read_stream"
+    | Read_RISCV_acquire -> "Read_RISCV_acquire"
+    | Read_RISCV_strong_acquire -> "Read_RISCV_strong_acquire"
+    | Read_RISCV_reserved -> "Read_RISCV_reserved"
+    | Read_RISCV_reserved_acquire -> "Read_RISCV_reserved_acquire"
+    | Read_RISCV_reserved_strong_acquire -> "Read_RISCV_reserved_strong_acquire"
+    | Read_X86_locked -> "Read_X86_locked"
+  end
+end
+*)
+Inductive write_kind :=
+  (* common writes *)
+  | Write_plain
+  (* Power writes *)
+  | Write_conditional
+  (* AArch64 writes *)
+  | Write_release | Write_exclusive | Write_exclusive_release
+  (* RISC-V *)
+  | Write_RISCV_release     | Write_RISCV_strong_release
+  | Write_RISCV_conditional | Write_RISCV_conditional_release
+  | Write_RISCV_conditional_strong_release
+  (* x86 writes *)
+  | Write_X86_locked (* the write part of a lock'd instruction (rmw) *)
+.
+(*
+instance (Show write_kind)
+  let show := function
+    | Write_plain -> "Write_plain"
+    | Write_conditional -> "Write_conditional"
+    | Write_release -> "Write_release"
+    | Write_exclusive -> "Write_exclusive"
+    | Write_exclusive_release -> "Write_exclusive_release"
+    | Write_RISCV_release -> "Write_RISCV_release"
+    | Write_RISCV_strong_release -> "Write_RISCV_strong_release"
+    | Write_RISCV_conditional -> "Write_RISCV_conditional"
+    | Write_RISCV_conditional_release -> "Write_RISCV_conditional_release"
+    | Write_RISCV_conditional_strong_release -> "Write_RISCV_conditional_strong_release"
+    | Write_X86_locked -> "Write_X86_locked"
+  end
+end
+*)
+Inductive barrier_kind :=
+  (* Power barriers *)
+  Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
+  (* AArch64 barriers *)
+  | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
+  | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
+  | Barrier_TM_COMMIT
+  (* MIPS barriers *)
+  | Barrier_MIPS_SYNC
+  (* RISC-V barriers *)
+  | Barrier_RISCV_rw_rw
+  | Barrier_RISCV_r_rw
+  | Barrier_RISCV_r_r
+  | Barrier_RISCV_rw_w
+  | Barrier_RISCV_w_w
+  | Barrier_RISCV_i
+  (* X86 *)
+  | Barrier_x86_MFENCE.
+
+(*
+instance (Show barrier_kind)
+  let show := function
+    | Barrier_Sync -> "Barrier_Sync"
+    | Barrier_LwSync -> "Barrier_LwSync"
+    | Barrier_Eieio -> "Barrier_Eieio"
+    | Barrier_Isync -> "Barrier_Isync"
+    | Barrier_DMB -> "Barrier_DMB"
+    | Barrier_DMB_ST -> "Barrier_DMB_ST"
+    | Barrier_DMB_LD -> "Barrier_DMB_LD"
+    | Barrier_DSB -> "Barrier_DSB"
+    | Barrier_DSB_ST -> "Barrier_DSB_ST"
+    | Barrier_DSB_LD -> "Barrier_DSB_LD"
+    | Barrier_ISB -> "Barrier_ISB"
+    | Barrier_TM_COMMIT -> "Barrier_TM_COMMIT"
+    | Barrier_MIPS_SYNC -> "Barrier_MIPS_SYNC"
+    | Barrier_RISCV_rw_rw -> "Barrier_RISCV_rw_rw"
+    | Barrier_RISCV_r_rw  -> "Barrier_RISCV_r_rw"
+    | Barrier_RISCV_r_r   -> "Barrier_RISCV_r_r"
+    | Barrier_RISCV_rw_w  -> "Barrier_RISCV_rw_w"
+    | Barrier_RISCV_w_w   -> "Barrier_RISCV_w_w"
+    | Barrier_RISCV_i     -> "Barrier_RISCV_i"
+    | Barrier_x86_MFENCE  -> "Barrier_x86_MFENCE"
+  end
+end*)
+
+Inductive trans_kind :=
+  (* AArch64 *)
+  | Transaction_start | Transaction_commit | Transaction_abort.
+(*
+instance (Show trans_kind)
+  let show := function
+  | Transaction_start  -> "Transaction_start"
+  | Transaction_commit -> "Transaction_commit"
+  | Transaction_abort  -> "Transaction_abort"
+  end
+end*)
+
+Inductive instruction_kind :=
+  | IK_barrier   : barrier_kind -> instruction_kind
+  | IK_mem_read  : read_kind -> instruction_kind
+  | IK_mem_write : write_kind -> instruction_kind
+  | IK_mem_rmw   : (read_kind * write_kind) -> instruction_kind
+  | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+  indirect/computed-branch (single nia of kind NIA_indirect_address)
+  and branch/jump (single nia of kind NIA_concrete_address) *)
+  | IK_trans     : trans_kind -> instruction_kind
+  | IK_simple    : instruction_kind.
+
+(*
+instance (Show instruction_kind)
+  let show := function
+    | IK_barrier barrier_kind -> "IK_barrier " ^ (show barrier_kind)
+    | IK_mem_read read_kind   -> "IK_mem_read " ^ (show read_kind)
+    | IK_mem_write write_kind -> "IK_mem_write " ^ (show write_kind)
+    | IK_mem_rmw (r, w)       -> "IK_mem_rmw " ^ (show r) ^ " " ^ (show w)
+    | IK_branch               -> "IK_branch"
+    | IK_trans trans_kind     -> "IK_trans " ^ (show trans_kind)
+    | IK_simple               -> "IK_simple"
+  end
+end
+*)
+
+Definition read_is_exclusive r :=
+match r with
+  | Read_plain => false
+  | Read_reserve => true
+  | Read_acquire => false
+  | Read_exclusive => true
+  | Read_exclusive_acquire => true
+  | Read_stream => false
+  | Read_RISCV_acquire => false
+  | Read_RISCV_strong_acquire => false
+  | Read_RISCV_reserved => true
+  | Read_RISCV_reserved_acquire => true
+  | Read_RISCV_reserved_strong_acquire => true
+  | Read_X86_locked => true
+end.
+
+
+(*
+instance (EnumerationType read_kind)
+  let toNat := function
+    | Read_plain -> 0
+    | Read_reserve -> 1
+    | Read_acquire -> 2
+    | Read_exclusive -> 3
+    | Read_exclusive_acquire -> 4
+    | Read_stream -> 5
+    | Read_RISCV_acquire -> 6
+    | Read_RISCV_strong_acquire -> 7
+    | Read_RISCV_reserved -> 8
+    | Read_RISCV_reserved_acquire -> 9
+    | Read_RISCV_reserved_strong_acquire -> 10
+    | Read_X86_locked -> 11
+  end
+end
+
+instance (EnumerationType write_kind)
+  let toNat := function
+    | Write_plain -> 0
+    | Write_conditional -> 1
+    | Write_release -> 2
+    | Write_exclusive -> 3
+    | Write_exclusive_release -> 4
+    | Write_RISCV_release -> 5
+    | Write_RISCV_strong_release -> 6
+    | Write_RISCV_conditional -> 7
+    | Write_RISCV_conditional_release -> 8
+    | Write_RISCV_conditional_strong_release -> 9
+    | Write_X86_locked -> 10
+  end
+end
+
+instance (EnumerationType barrier_kind)
+  let toNat := function
+    | Barrier_Sync -> 0
+    | Barrier_LwSync -> 1
+    | Barrier_Eieio ->2
+    | Barrier_Isync -> 3
+    | Barrier_DMB -> 4
+    | Barrier_DMB_ST -> 5
+    | Barrier_DMB_LD -> 6
+    | Barrier_DSB -> 7
+    | Barrier_DSB_ST -> 8
+    | Barrier_DSB_LD -> 9
+    | Barrier_ISB -> 10
+    | Barrier_TM_COMMIT -> 11
+    | Barrier_MIPS_SYNC -> 12
+    | Barrier_RISCV_rw_rw -> 13
+    | Barrier_RISCV_r_rw -> 14
+    | Barrier_RISCV_r_r -> 15
+    | Barrier_RISCV_rw_w -> 16
+    | Barrier_RISCV_w_w -> 17
+    | Barrier_RISCV_i -> 18
+    | Barrier_x86_MFENCE -> 19
+  end
+end
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_operators.v b/snapshots/coq/lib/coq/Sail2_operators.v
new file mode 100644
index 00000000..5a8b1119
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_operators.v
@@ -0,0 +1,237 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_values.
+Require List.
+Import List.ListNotations.
+
+(*** Bit vector operations *)
+
+Section Bitvectors.
+Context {a b c} `{Bitvector a} `{Bitvector b} `{Bitvector c}.
+
+(*val concat_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b, Bitvector 'c => 'a -> 'b -> 'c*)
+Definition concat_bv (l : a) (r : b) : list bitU := bits_of l ++ bits_of r.
+
+(*val cons_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b => bitU -> 'a -> 'b*)
+Definition cons_bv b' (v : a) : list bitU := b' :: bits_of v.
+
+Definition cast_unit_bv b : list bitU := [b].
+Definition bv_of_bit len b : list bitU := extz_bits len [b].
+
+(*Definition most_significant v := match bits_of v with
+  | cons b _ => b
+  | _ => failwith "most_significant applied to empty vector"
+  end.
+
+Definition get_max_representable_in sign (n : integer) : integer :=
+  if (n = 64) then match sign with | true -> max_64 | false -> max_64u end
+  else if (n=32) then match sign with | true -> max_32 | false -> max_32u end
+  else if (n=8) then max_8
+  else if (n=5) then max_5
+  else match sign with | true -> integerPow 2 ((natFromInteger n) -1)
+                       | false -> integerPow 2 (natFromInteger n)
+       end
+
+Definition get_min_representable_in _ (n : integer) : integer :=
+  if n = 64 then min_64
+  else if n = 32 then min_32
+  else if n = 8 then min_8
+  else if n = 5 then min_5
+  else 0 - (integerPow 2 (natFromInteger n))
+
+val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
+Definition arith_op_bv_int {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : a) (r : Z) : a :=
+  let r' := of_int (length l) r in
+  arith_op_bv op sign l r'.
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
+Definition arith_op_int_bv {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : Z) (r : a) : a :=
+  let l' := of_int (length r) l in
+  arith_op_bv op sign l' r.
+(*
+Definition add_bv_int := arith_op_bv_int Zplus false 1.
+Definition sadd_bv_int := arith_op_bv_int Zplus true 1.
+Definition sub_bv_int := arith_op_bv_int Zminus false 1.
+Definition mult_bv_int := arith_op_bv_int Zmult false 2.
+Definition smult_bv_int := arith_op_bv_int Zmult true 2.
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> integer -> 'a -> 'b
+Definition arith_op_int_bv op sign size l r :=
+  let r' = int_of_bv sign r in
+  let n = op l r' in
+  of_int (size * length r) n
+
+Definition add_int_bv = arith_op_int_bv integerAdd false 1
+Definition sadd_int_bv = arith_op_int_bv integerAdd true 1
+Definition sub_int_bv = arith_op_int_bv integerMinus false 1
+Definition mult_int_bv = arith_op_int_bv integerMult false 2
+Definition smult_int_bv = arith_op_int_bv integerMult true 2
+
+Definition arith_op_bv_bit op sign (size : integer) l r :=
+  let l' = int_of_bv sign l in
+  let n = op l' (match r with | B1 -> (1 : integer) | _ -> 0 end) in
+  of_int (size * length l) n
+
+Definition add_bv_bit := arith_op_bv_bit integerAdd false 1
+Definition sadd_bv_bit := arith_op_bv_bit integerAdd true 1
+Definition sub_bv_bit := arith_op_bv_bit integerMinus true 1
+
+val arith_op_overflow_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> ('b * bitU * bitU)
+Definition arith_op_overflow_bv op sign size l r :=
+  let len := length l in
+  let act_size := len * size in
+  let (l_sign,r_sign) := (int_of_bv sign l,int_of_bv sign r) in
+  let (l_unsign,r_unsign) := (int_of_bv false l,int_of_bv false r) in
+  let n := op l_sign r_sign in
+  let n_unsign := op l_unsign r_unsign in
+  let correct_size := of_int act_size n in
+  let one_more_size_u := bits_of_int (act_size + 1) n_unsign in
+  let overflow :=
+    if n <= get_max_representable_in sign len &&
+         n >= get_min_representable_in sign len
+    then B0 else B1 in
+  let c_out := most_significant one_more_size_u in
+  (correct_size,overflow,c_out)
+
+Definition add_overflow_bv := arith_op_overflow_bv integerAdd false 1
+Definition add_overflow_bv_signed := arith_op_overflow_bv integerAdd true 1
+Definition sub_overflow_bv := arith_op_overflow_bv integerMinus false 1
+Definition sub_overflow_bv_signed := arith_op_overflow_bv integerMinus true 1
+Definition mult_overflow_bv := arith_op_overflow_bv integerMult false 2
+Definition mult_overflow_bv_signed := arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> ('b * bitU * bitU)
+Definition arith_op_overflow_bv_bit op sign size l r_bit :=
+  let act_size := length l * size in
+  let l' := int_of_bv sign l in
+  let l_u := int_of_bv false l in
+  let (n,nu,changed) := match r_bit with
+    | B1 -> (op l' 1, op l_u 1, true)
+    | B0 -> (l',l_u,false)
+    | BU -> failwith "arith_op_overflow_bv_bit applied to undefined bit"
+    end in
+  let correct_size := of_int act_size n in
+  let one_larger := bits_of_int (act_size + 1) nu in
+  let overflow :=
+    if changed
+    then
+      if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+      then B0 else B1
+    else B0 in
+  (correct_size,overflow,most_significant one_larger)
+
+Definition add_overflow_bv_bit := arith_op_overflow_bv_bit integerAdd false 1
+Definition add_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerAdd true 1
+Definition sub_overflow_bv_bit := arith_op_overflow_bv_bit integerMinus false 1
+Definition sub_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerMinus true 1
+
+type shift := LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot
+
+val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> 'a
+Definition shift_op_bv op v n :=
+  match op with
+  | LL_shift ->
+     of_bits (get_bits true v n (length v - 1) ++ repeat [B0] n)
+  | RR_shift ->
+     of_bits (repeat [B0] n ++ get_bits true v 0 (length v - n - 1))
+  | RR_shift_arith ->
+     of_bits (repeat [most_significant v] n ++ get_bits true v 0 (length v - n - 1))
+  | LL_rot ->
+     of_bits (get_bits true v n (length v - 1) ++ get_bits true v 0 (n - 1))
+  | RR_rot ->
+     of_bits (get_bits false v 0 (n - 1) ++ get_bits false v n (length v - 1))
+  end
+
+Definition shiftl_bv := shift_op_bv LL_shift (*"<<"*)
+Definition shiftr_bv := shift_op_bv RR_shift (*">>"*)
+Definition arith_shiftr_bv := shift_op_bv RR_shift_arith
+Definition rotl_bv := shift_op_bv LL_rot (*"<<<"*)
+Definition rotr_bv := shift_op_bv LL_rot (*">>>"*)
+
+Definition shiftl_mword w n := Machine_word.shiftLeft w (natFromInteger n)
+Definition shiftr_mword w n := Machine_word.shiftRight w (natFromInteger n)
+Definition rotl_mword w n := Machine_word.rotateLeft (natFromInteger n) w
+Definition rotr_mword w n := Machine_word.rotateRight (natFromInteger n) w
+
+Definition rec arith_op_no0 (op : integer -> integer -> integer) l r :=
+  if r = 0
+  then Nothing
+  else Just (op l r)
+
+val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> 'b
+Definition arith_op_bv_no0 op sign size l r :=
+  let act_size := length l * size in
+  let (l',r') := (int_of_bv sign l,int_of_bv sign r) in
+  let n := arith_op_no0 op l' r' in
+  let (representable,n') :=
+    match n with
+    | Just n' ->
+      (n' <= get_max_representable_in sign act_size &&
+         n' >= get_min_representable_in sign act_size, n')
+    | _ -> (false,0)
+    end in
+  if representable then (of_int act_size n') else (of_bits (repeat [BU] act_size))
+
+Definition mod_bv := arith_op_bv_no0 hardware_mod false 1
+Definition quot_bv := arith_op_bv_no0 hardware_quot false 1
+Definition quot_bv_signed := arith_op_bv_no0 hardware_quot true 1
+
+Definition mod_mword := Machine_word.modulo
+Definition quot_mword := Machine_word.unsignedDivide
+Definition quot_mword_signed := Machine_word.signedDivide
+
+Definition arith_op_bv_int_no0 op sign size l r :=
+  arith_op_bv_no0 op sign size l (of_int (length l) r)
+
+Definition quot_bv_int := arith_op_bv_int_no0 hardware_quot false 1
+Definition mod_bv_int := arith_op_bv_int_no0 hardware_mod false 1
+*)
+Definition replicate_bits_bv {a b} `{Bitvector a} `{Bitvector b} (v : a) count : b := of_bits (repeat (bits_of v) count).
+Import List.
+Import ListNotations.
+Definition duplicate_bit_bv {a} `{Bitvector a} bit len : a := replicate_bits_bv [bit] len.
+
+(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+Definition eq_bv {A} `{Bitvector A} (l : A) r := (unsigned l =? unsigned r).
+
+(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+Definition neq_bv (l : a) (r :a) : bool := (negb (unsigned l =? unsigned r)).
+(*
+val ucmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool
+Definition ucmp_bv cmp l r := cmp (unsigned l) (unsigned r)
+
+val scmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool
+Definition scmp_bv cmp l r := cmp (signed l) (signed r)
+
+Definition ult_bv := ucmp_bv (<)
+Definition slt_bv := scmp_bv (<)
+Definition ugt_bv := ucmp_bv (>)
+Definition sgt_bv := scmp_bv (>)
+Definition ulteq_bv := ucmp_bv (<=)
+Definition slteq_bv := scmp_bv (<=)
+Definition ugteq_bv := ucmp_bv (>=)
+Definition sgteq_bv := scmp_bv (>=)
+*)
+
+(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)*)
+Definition get_slice_int_bv {a} `{Bitvector a} len n lo : a :=
+  let hi := lo + len - 1 in
+  let bs := bools_of_int (hi + 1) n in
+  of_bools (subrange_list false bs hi lo).
+
+(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer
+Definition set_slice_int_bv {a} `{Bitvector a} len n lo (v : a) :=
+  let hi := lo + len - 1 in
+  let bs := bits_of_int (hi + 1) n in
+  maybe_failwith (signed_of_bits (update_subrange_list false bs hi lo (bits_of v))).*)
+
+End Bitvectors.
diff --git a/snapshots/coq/lib/coq/Sail2_operators_bitlists.v b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v
new file mode 100644
index 00000000..b0240c4e
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v
@@ -0,0 +1,187 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_values.
+Require Import Sail2_operators.
+
+(*
+
+(* Specialisation of operators to bit lists *)
+
+val access_vec_inc : list bitU -> integer -> bitU
+let access_vec_inc = access_bv_inc
+
+val access_vec_dec : list bitU -> integer -> bitU
+let access_vec_dec = access_bv_dec
+
+val update_vec_inc : list bitU -> integer -> bitU -> list bitU
+let update_vec_inc = update_bv_inc
+
+val update_vec_dec : list bitU -> integer -> bitU -> list bitU
+let update_vec_dec = update_bv_dec
+
+val subrange_vec_inc : list bitU -> integer -> integer -> list bitU
+let subrange_vec_inc = subrange_bv_inc
+
+val subrange_vec_dec : list bitU -> integer -> integer -> list bitU
+let subrange_vec_dec = subrange_bv_dec
+
+val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU
+let update_subrange_vec_inc = update_subrange_bv_inc
+
+val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU
+let update_subrange_vec_dec = update_subrange_bv_dec
+
+val extz_vec : integer -> list bitU -> list bitU
+let extz_vec = extz_bv
+
+val exts_vec : integer -> list bitU -> list bitU
+let exts_vec = exts_bv
+
+val concat_vec : list bitU -> list bitU -> list bitU
+let concat_vec = concat_bv
+
+val cons_vec : bitU -> list bitU -> list bitU
+let cons_vec = cons_bv
+
+val bool_of_vec : mword ty1 -> bitU
+let bool_of_vec = bool_of_bv
+
+val cast_unit_vec : bitU -> mword ty1
+let cast_unit_vec = cast_unit_bv
+
+val vec_of_bit : integer -> bitU -> list bitU
+let vec_of_bit = bv_of_bit
+
+val msb : list bitU -> bitU
+let msb = most_significant
+
+val int_of_vec : bool -> list bitU -> integer
+let int_of_vec = int_of_bv
+
+val string_of_vec : list bitU -> string
+let string_of_vec = string_of_bv
+
+val and_vec : list bitU -> list bitU -> list bitU
+val or_vec  : list bitU -> list bitU -> list bitU
+val xor_vec : list bitU -> list bitU -> list bitU
+val not_vec : list bitU -> list bitU
+let and_vec = and_bv
+let or_vec  = or_bv
+let xor_vec = xor_bv
+let not_vec = not_bv
+
+val add_vec   : list bitU -> list bitU -> list bitU
+val sadd_vec  : list bitU -> list bitU -> list bitU
+val sub_vec   : list bitU -> list bitU -> list bitU
+val mult_vec  : list bitU -> list bitU -> list bitU
+val smult_vec : list bitU -> list bitU -> list bitU
+let add_vec   = add_bv
+let sadd_vec  = sadd_bv
+let sub_vec   = sub_bv
+let mult_vec  = mult_bv
+let smult_vec = smult_bv
+
+val add_vec_int   : list bitU -> integer -> list bitU
+val sadd_vec_int  : list bitU -> integer -> list bitU
+val sub_vec_int   : list bitU -> integer -> list bitU
+val mult_vec_int  : list bitU -> integer -> list bitU
+val smult_vec_int : list bitU -> integer -> list bitU
+let add_vec_int   = add_bv_int
+let sadd_vec_int  = sadd_bv_int
+let sub_vec_int   = sub_bv_int
+let mult_vec_int  = mult_bv_int
+let smult_vec_int = smult_bv_int
+
+val add_int_vec   : integer -> list bitU -> list bitU
+val sadd_int_vec  : integer -> list bitU -> list bitU
+val sub_int_vec   : integer -> list bitU -> list bitU
+val mult_int_vec  : integer -> list bitU -> list bitU
+val smult_int_vec : integer -> list bitU -> list bitU
+let add_int_vec   = add_int_bv
+let sadd_int_vec  = sadd_int_bv
+let sub_int_vec   = sub_int_bv
+let mult_int_vec  = mult_int_bv
+let smult_int_vec = smult_int_bv
+
+val add_vec_bit  : list bitU -> bitU -> list bitU
+val sadd_vec_bit : list bitU -> bitU -> list bitU
+val sub_vec_bit  : list bitU -> bitU -> list bitU
+let add_vec_bit  = add_bv_bit
+let sadd_vec_bit = sadd_bv_bit
+let sub_vec_bit  = sub_bv_bit
+
+val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec        : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec         = add_overflow_bv
+let add_overflow_vec_signed  = add_overflow_bv_signed
+let sub_overflow_vec         = sub_overflow_bv
+let sub_overflow_vec_signed  = sub_overflow_bv_signed
+let mult_overflow_vec        = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit         = add_overflow_bv_bit
+let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit         = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed
+
+val shiftl       : list bitU -> integer -> list bitU
+val shiftr       : list bitU -> integer -> list bitU
+val arith_shiftr : list bitU -> integer -> list bitU
+val rotl         : list bitU -> integer -> list bitU
+val rotr         : list bitU -> integer -> list bitU
+let shiftl       = shiftl_bv
+let shiftr       = shiftr_bv
+let arith_shiftr = arith_shiftr_bv
+let rotl         = rotl_bv
+let rotr         = rotr_bv
+
+val mod_vec         : list bitU -> list bitU -> list bitU
+val quot_vec        : list bitU -> list bitU -> list bitU
+val quot_vec_signed : list bitU -> list bitU -> list bitU
+let mod_vec         = mod_bv
+let quot_vec        = quot_bv
+let quot_vec_signed = quot_bv_signed
+
+val mod_vec_int  : list bitU -> integer -> list bitU
+val quot_vec_int : list bitU -> integer -> list bitU
+let mod_vec_int  = mod_bv_int
+let quot_vec_int = quot_bv_int
+
+val replicate_bits : list bitU -> integer -> list bitU
+let replicate_bits = replicate_bits_bv
+
+val duplicate : bitU -> integer -> list bitU
+let duplicate = duplicate_bit_bv
+
+val eq_vec    : list bitU -> list bitU -> bool
+val neq_vec   : list bitU -> list bitU -> bool
+val ult_vec   : list bitU -> list bitU -> bool
+val slt_vec   : list bitU -> list bitU -> bool
+val ugt_vec   : list bitU -> list bitU -> bool
+val sgt_vec   : list bitU -> list bitU -> bool
+val ulteq_vec : list bitU -> list bitU -> bool
+val slteq_vec : list bitU -> list bitU -> bool
+val ugteq_vec : list bitU -> list bitU -> bool
+val sgteq_vec : list bitU -> list bitU -> bool
+let eq_vec    = eq_bv
+let neq_vec   = neq_bv
+let ult_vec   = ult_bv
+let slt_vec   = slt_bv
+let ugt_vec   = ugt_bv
+let sgt_vec   = sgt_bv
+let ulteq_vec = ulteq_bv
+let slteq_vec = slteq_bv
+let ugteq_vec = ugteq_bv
+let sgteq_vec = sgteq_bv
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_operators_mwords.v b/snapshots/coq/lib/coq/Sail2_operators_mwords.v
new file mode 100644
index 00000000..fba23071
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_operators_mwords.v
@@ -0,0 +1,438 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_values.
+Require Import Sail2_operators.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import bbv.Word.
+Require bbv.BinNotation.
+Require Import Arith.
+Require Import ZArith.
+Require Import Omega.
+Require Import Eqdep_dec.
+
+Module Z_eq_dec.
+Definition U := Z.
+Definition eq_dec := Z.eq_dec.
+End Z_eq_dec.
+Module ZEqdep := DecidableEqDep (Z_eq_dec).
+
+Definition cast_mword {m n} (x : mword m) (eq : m = n) : mword n.
+rewrite <- eq.
+exact x.
+Defined.
+
+Lemma cast_mword_refl {m} {H:m = m} (x : mword m) : cast_mword x H = x.
+rewrite (ZEqdep.UIP _ _ H eq_refl).
+reflexivity.
+Qed.
+
+Definition autocast {m n} (x : mword m) `{H:ArithFact (m = n)} : mword n :=
+  cast_mword x (use_ArithFact H).
+
+Definition autocast_m {rv e m n} (x : monad rv (mword m) e) `{H:ArithFact (m = n)} : monad rv (mword n) e :=
+  x >>= fun x => returnm (cast_mword x (use_ArithFact H)).
+
+Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n.
+rewrite <- eq.
+exact x.
+Defined.
+
+Lemma cast_word_refl {m} {H:m = m} (x : word m) : cast_word x H = x.
+rewrite (UIP_refl_nat _ H).
+reflexivity.
+Qed.
+
+Definition mword_of_nat {m} (x : Word.word m) : mword (Z.of_nat m).
+destruct m.
+- exact x.
+- simpl. rewrite SuccNat2Pos.id_succ. exact x.
+Defined.
+
+Definition cast_to_mword {m n} (x : Word.word m) (eq : Z.of_nat m = n) : mword n.
+destruct n.
+- constructor.
+- rewrite <- eq. exact (mword_of_nat x).
+- exfalso. destruct m; simpl in *; congruence.
+Defined.
+
+(*
+(* Specialisation of operators to machine words *)
+
+val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+Definition access_vec_inc {a} : mword a -> Z -> bitU := access_mword_inc.
+
+(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+Definition access_vec_dec {a} : mword a -> Z -> bitU := access_mword_dec.
+
+(*val update_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*)
+(* TODO: probably ought to use a monadic version instead, but using bad default for
+   type compatibility just now *)
+Definition update_vec_inc {a} (w : mword a) i b : mword a :=
+ opt_def w (update_mword_inc w i b).
+
+(*val update_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*)
+Definition update_vec_dec {a} (w : mword a) i b : mword a := opt_def w (update_mword_dec w i b).
+
+Lemma subrange_lemma0 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : (Z.to_nat o <= Z.to_nat m < Z.to_nat n)%nat.
+intros.
+unwrap_ArithFacts.
+split.
++ apply Z2Nat.inj_le; omega.
++ apply Z2Nat.inj_lt; omega.
+Qed.
+Lemma subrange_lemma1 {n m o} : (o <= m < n -> n = m + 1 + (n - (m + 1)))%nat.
+intros. omega.
+Qed.
+Lemma subrange_lemma2 {n m o} : (o <= m < n -> m+1 = o+(m-o+1))%nat.
+omega.
+Qed.
+Lemma subrange_lemma3 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} :
+  Z.of_nat (Z.to_nat m - Z.to_nat o + 1)%nat = m - o + 1.
+unwrap_ArithFacts.
+rewrite Nat2Z.inj_add.
+rewrite Nat2Z.inj_sub.
+repeat rewrite Z2Nat.id; try omega.
+reflexivity.
+apply Z2Nat.inj_le; omega.
+Qed.
+
+Definition subrange_vec_dec {n} (v : mword n) m o `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : mword (m - o + 1) :=
+  let n := Z.to_nat n in
+  let m := Z.to_nat m in
+  let o := Z.to_nat o in
+  let prf : (o <= m < n)%nat := subrange_lemma0 in
+  let w := get_word v in
+  cast_to_mword (split2 o (m-o+1)
+                        (cast_word (split1 (m+1) (n-(m+1)) (cast_word w (subrange_lemma1 prf)))
+                                   (subrange_lemma2 prf))) subrange_lemma3.
+
+Definition subrange_vec_inc {n} (v : mword n) m o `{ArithFact (0 <= m)} `{ArithFact (m <= o < n)} : mword (o - m + 1) := autocast (subrange_vec_dec v (n-1-m) (n-1-o)).
+
+(* TODO: get rid of bogus default *)
+Parameter dummy_vector : forall {n} `{ArithFact (n >= 0)}, mword n.
+
+(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+Definition update_subrange_vec_inc {a b} (v : mword a) i j (w : mword b) : mword a :=
+  opt_def dummy_vector (of_bits (update_subrange_bv_inc v i j w)).
+
+(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+Definition update_subrange_vec_dec {a b} (v : mword a) i j (w : mword b) : mword a :=
+  opt_def dummy_vector (of_bits (update_subrange_bv_dec v i j w)).
+
+Lemma mword_nonneg {a} : mword a -> a >= 0.
+destruct a;
+auto using Z.le_ge, Zle_0_pos with zarith.
+destruct 1.
+Qed.
+
+(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+Definition extz_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b.
+refine (cast_to_mword (Word.zext (get_word v) (Z.to_nat (b - a))) _).
+unwrap_ArithFacts.
+assert (a >= 0). { apply mword_nonneg. assumption. }
+rewrite <- Z2Nat.inj_add; try omega.
+rewrite Zplus_minus.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+Definition exts_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b.
+refine (cast_to_mword (Word.sext (get_word v) (Z.to_nat (b - a))) _).
+unwrap_ArithFacts.
+assert (a >= 0). { apply mword_nonneg. assumption. }
+rewrite <- Z2Nat.inj_add; try omega.
+rewrite Zplus_minus.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := extz_vec n v.
+
+Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v.
+
+Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat.
+intros.
+assert ((Z.to_nat m <= Z.to_nat n)%nat).
+{ apply Z2Nat.inj_le; omega. }
+omega.
+Qed.
+
+Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m :=
+  cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m).
+
+Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b.
+intros.
+rewrite Nat2Z.inj_add.
+rewrite Z2Nat.id; auto with zarith.
+rewrite Z2Nat.id; auto with zarith.
+Qed.
+
+
+(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
+Definition concat_vec {a b} (v : mword a) (w : mword b) : mword (a + b) :=
+ cast_to_mword (Word.combine (get_word w) (get_word v)) (ltac:(solve [auto using concat_eq, mword_nonneg with zarith]) : Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b).
+
+(*val cons_vec : forall 'a 'b 'c. Size 'a, Size 'b => bitU -> mword 'a -> mword 'b*)
+(*Definition cons_vec {a b} : bitU -> mword a -> mword b := cons_bv.*)
+
+(*val bool_of_vec : mword ty1 -> bitU
+Definition bool_of_vec := bool_of_bv
+
+val cast_unit_vec : bitU -> mword ty1
+Definition cast_unit_vec := cast_unit_bv
+
+val vec_of_bit : forall 'a. Size 'a => integer -> bitU -> mword 'a
+Definition vec_of_bit := bv_of_bit*)
+
+Require Import bbv.NatLib.
+
+Lemma Npow2_pow {n} : (2 ^ (N.of_nat n) = Npow2 n)%N.
+induction n.
+* reflexivity.
+* rewrite Nnat.Nat2N.inj_succ.
+  rewrite N.pow_succ_r'.
+  rewrite IHn.
+  rewrite Npow2_S.
+  rewrite Word.Nmul_two.
+  reflexivity.
+Qed.
+
+Program Definition uint {a} (x : mword a) : {z : Z & ArithFact (0 <= z /\ z <= 2 ^ a - 1)} :=
+ existT _ (Z.of_N (Word.wordToN (get_word x))) _.
+Next Obligation.
+constructor.
+constructor.
+* apply N2Z.is_nonneg.
+* assert (2 ^ a - 1 = Z.of_N (2 ^ (Z.to_N a) - 1)). {
+    rewrite N2Z.inj_sub.
+    * rewrite N2Z.inj_pow.
+      rewrite Z2N.id; auto.
+      destruct a; auto with zarith. destruct x.
+    * apply N.le_trans with (m := (2^0)%N); auto using N.le_refl.
+      apply N.pow_le_mono_r.
+      inversion 1.
+      apply N.le_0_l.
+  }
+  rewrite H.
+  apply N2Z.inj_le.
+  rewrite N.sub_1_r.
+  apply N.lt_le_pred.
+  rewrite <- Z_nat_N.
+  rewrite Npow2_pow.
+  apply Word.wordToN_bound.
+Defined.
+
+Lemma Zpow_pow2 {n} : 2 ^ Z.of_nat n = Z.of_nat (pow2 n).
+induction n.
+* reflexivity.
+* rewrite pow2_S_z.
+  rewrite Nat2Z.inj_succ.
+  rewrite Z.pow_succ_r; auto with zarith.
+Qed.
+
+Program Definition sint {a} `{ArithFact (a > 0)} (x : mword a) : {z : Z & ArithFact (-(2^(a-1)) <= z /\ z <= 2 ^ (a-1) - 1)} :=
+  existT _ (Word.wordToZ (get_word x)) _.
+Next Obligation.
+destruct H.
+destruct a; try inversion fact.
+constructor.
+generalize (get_word x).
+rewrite <- positive_nat_Z.
+destruct (Pos2Nat.is_succ p) as [n eq].
+rewrite eq.
+rewrite Nat2Z.id.
+intro w.
+destruct (Word.wordToZ_size' w) as [LO HI].
+replace 1 with (Z.of_nat 1); auto.
+rewrite <- Nat2Z.inj_sub; auto with arith.
+simpl.
+rewrite <- minus_n_O.
+rewrite Zpow_pow2.
+rewrite Z.sub_1_r.
+rewrite <- Z.lt_le_pred.
+auto.
+Defined.
+
+Lemma length_list_pos : forall {A} {l:list A}, length_list l >= 0.
+unfold length_list.
+auto with zarith.
+Qed.
+Hint Resolve length_list_pos : sail.
+
+Definition vec_of_bits (l:list bitU) : mword (length_list l) := opt_def dummy_vector (of_bits l).
+(*
+
+val msb : forall 'a. Size 'a => mword 'a -> bitU
+Definition msb := most_significant
+
+val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer
+Definition int_of_vec := int_of_bv
+
+val string_of_vec : forall 'a. Size 'a => mword 'a -> string*)
+Definition string_of_bits {n} (w : mword n) : string := string_of_bv w.
+Definition with_word' {n} (P : Type -> Type) : (forall n, Word.word n -> P (Word.word n)) -> mword n -> P (mword n) := fun f w => @with_word n _ (f (Z.to_nat n)) w.
+Definition word_binop {n} (f : forall n, Word.word n -> Word.word n -> Word.word n) : mword n -> mword n -> mword n := with_word' (fun x => x -> x) f.
+Definition word_unop {n} (f : forall n, Word.word n -> Word.word n) : mword n -> mword n := with_word' (fun x => x) f.
+
+
+(*
+val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val or_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
+Definition and_vec {n} : mword n -> mword n -> mword n := word_binop Word.wand.
+Definition or_vec  {n} : mword n -> mword n -> mword n := word_binop Word.wor.
+Definition xor_vec {n} : mword n -> mword n -> mword n := word_binop Word.wxor.
+Definition not_vec {n} : mword n -> mword n := word_unop Word.wnot.
+
+(*val add_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val sadd_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val sub_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val mult_vec  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b
+val smult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+Definition add_vec   {n} : mword n -> mword n -> mword n := word_binop Word.wplus.
+(*Definition sadd_vec  {n} : mword n -> mword n -> mword n := sadd_bv w.*)
+Definition sub_vec   {n} : mword n -> mword n -> mword n := word_binop Word.wminus.
+Definition mult_vec  {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m :=
+  word_binop Word.wmult (zero_extend l _) (zero_extend r _).
+Definition mults_vec  {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m :=
+  word_binop Word.wmult (sign_extend l _) (sign_extend r _).
+
+(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sadd_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
+val smult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+Definition add_vec_int   {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add   false l r.
+Definition sadd_vec_int  {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add   true  l r.
+Definition sub_vec_int   {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.sub   false l r.
+(*Definition mult_vec_int  {a b} : mword a -> Z -> mword b := mult_bv_int.
+Definition smult_vec_int {a b} : mword a -> Z -> mword b := smult_bv_int.*)
+
+(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sadd_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+val smult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+Definition add_int_vec   := add_int_bv
+Definition sadd_int_vec  := sadd_int_bv
+Definition sub_int_vec   := sub_int_bv
+Definition mult_int_vec  := mult_int_bv
+Definition smult_int_vec := smult_int_bv
+
+val add_vec_bit  : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+val sadd_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+val sub_vec_bit  : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+Definition add_vec_bit  := add_bv_bit
+Definition sadd_vec_bit := sadd_bv_bit
+Definition sub_vec_bit  := sub_bv_bit
+
+val add_overflow_vec         : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val add_overflow_vec_signed  : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val sub_overflow_vec         : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_signed  : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val mult_overflow_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val mult_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+Definition add_overflow_vec         := add_overflow_bv
+Definition add_overflow_vec_signed  := add_overflow_bv_signed
+Definition sub_overflow_vec         := sub_overflow_bv
+Definition sub_overflow_vec_signed  := sub_overflow_bv_signed
+Definition mult_overflow_vec        := mult_overflow_bv
+Definition mult_overflow_vec_signed := mult_overflow_bv_signed
+
+val add_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+Definition add_overflow_vec_bit         := add_overflow_bv_bit
+Definition add_overflow_vec_bit_signed  := add_overflow_bv_bit_signed
+Definition sub_overflow_vec_bit         := sub_overflow_bv_bit
+Definition sub_overflow_vec_bit_signed  := sub_overflow_bv_bit_signed
+
+val shiftl       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val shiftr       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val rotl         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val rotr         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(* TODO: check/redefine behaviour on out-of-range n *)
+Definition shiftl       {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wlshift w (Z.to_nat n)) v.
+Definition shiftr       {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshift w (Z.to_nat n)) v.
+Definition arith_shiftr {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshifta w (Z.to_nat n)) v.
+(*
+Definition rotl         := rotl_bv
+Definition rotr         := rotr_bv
+
+val mod_vec         : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val quot_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+Definition mod_vec         := mod_bv
+Definition quot_vec        := quot_bv
+Definition quot_vec_signed := quot_bv_signed
+
+val mod_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+Definition mod_vec_int  := mod_bv_int
+Definition quot_vec_int := quot_bv_int
+
+val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+Fixpoint replicate_bits_aux {a} (w : Word.word a) (n : nat) : Word.word (n * a) :=
+match n with
+| O => Word.WO
+| S m => Word.combine w (replicate_bits_aux w m)
+end.
+Lemma replicate_ok {n a} `{ArithFact (n >= 0)} `{ArithFact (a >= 0)} :
+   Z.of_nat (Z.to_nat n * Z.to_nat a) = a * n.
+destruct H. destruct H0.
+rewrite <- Z2Nat.id; auto with zarith.
+rewrite Z2Nat.inj_mul; auto with zarith.
+rewrite Nat.mul_comm. reflexivity.
+Qed.
+Definition replicate_bits {a} (w : mword a) (n : Z) `{ArithFact (n >= 0)} : mword (a * n) :=
+ cast_to_mword (replicate_bits_aux (get_word w) (Z.to_nat n)) replicate_ok.
+
+(*val duplicate : forall 'a. Size 'a => bitU -> integer -> mword 'a
+Definition duplicate := duplicate_bit_bv
+
+val eq_vec    : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val neq_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ult_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val slt_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ugt_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val sgt_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ulteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val slteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ugteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val sgteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+Definition eq_vec  {n} (x : mword n) (y : mword n) : bool := Word.weqb (get_word x) (get_word y).
+Definition neq_vec {n} (x : mword n) (y : mword n) : bool := negb (eq_vec x y).
+(*Definition ult_vec   := ult_bv.
+Definition slt_vec   := slt_bv.
+Definition ugt_vec   := ugt_bv.
+Definition sgt_vec   := sgt_bv.
+Definition ulteq_vec := ulteq_bv.
+Definition slteq_vec := slteq_bv.
+Definition ugteq_vec := ugteq_bv.
+Definition sgteq_vec := sgteq_bv.
+
+*)
+
+Program Fixpoint reverse_endianness_word {n} (bits : word n) : word n :=
+  match n with
+  | S (S (S (S (S (S (S (S m))))))) =>
+    combine
+      (reverse_endianness_word (split2 8 m bits))
+      (split1 8 m bits)
+  | _ => bits
+  end.
+Next Obligation.
+omega.
+Qed.
+
+Definition reverse_endianness {n} (bits : mword n) := with_word (P := id) reverse_endianness_word bits.
+
+Definition get_slice_int {a} `{ArithFact (a >= 0)} : Z -> Z -> Z -> mword a := get_slice_int_bv.
diff --git a/snapshots/coq/lib/coq/Sail2_prompt.v b/snapshots/coq/lib/coq/Sail2_prompt.v
new file mode 100644
index 00000000..ab7d5bac
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_prompt.v
@@ -0,0 +1,122 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(*Require Import Sail_impl_base*)
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+
+Require Import List.
+Import ListNotations.
+(*
+
+val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let rec iter_aux i f xs = match xs with
+  | x :: xs -> f i x >> iter_aux (i + 1) f xs
+  | [] -> return ()
+  end
+
+declare {isabelle} termination_argument iter_aux = automatic
+
+val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let iteri f xs = iter_aux 0 f xs
+
+val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let iter f xs = iteri (fun _ x -> f x) xs
+
+val foreachM : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+Fixpoint foreachM {a rv Vars e} (l : list a) (vars : Vars) (body : a -> Vars -> monad rv Vars e) : monad rv Vars e :=
+match l with
+| [] => returnm vars
+| (x :: xs) =>
+  body x vars >>= fun vars =>
+  foreachM xs vars body
+end.
+
+Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+  if sumbool_of_bool (from + off <=? to) then
+    match n with
+    | O => returnm vars
+    | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_up' from to step (off + step) n vars body
+    end
+  else returnm vars.
+
+Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+  if sumbool_of_bool (to <=? from + off) then
+    match n with
+    | O => returnm vars
+    | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_down' from to step (off - step) n vars body
+    end
+  else returnm vars.
+
+Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+    foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+    foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
+(*declare {isabelle} termination_argument foreachM = automatic*)
+
+(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+Definition and_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E :=
+ l >>= (fun l => if l then r else returnm false).
+
+(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+Definition or_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E :=
+ l >>= (fun l => if l then returnm true else r).
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+Definition bool_of_bitU_fail {rv E} (b : bitU) : monad rv bool E :=
+match b with
+  | B0 => returnm false
+  | B1 => returnm true
+  | BU => Fail "bool_of_bitU"
+end.
+
+(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+Definition bool_of_bitU_oracle {rv E} (b : bitU) : monad rv bool E :=
+match b with
+  | B0 => returnm false
+  | B1 => returnm true
+  | BU => undefined_bool tt
+end.
+
+
+(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e
+let rec whileM vars cond body =
+  cond vars >>= fun cond_val ->
+  if cond_val then
+    body vars >>= fun vars -> whileM vars cond body
+  else return vars
+
+val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e
+let rec untilM vars cond body =
+  body vars >>= fun vars ->
+  cond vars >>= fun cond_val ->
+  if cond_val then return vars else untilM vars cond body
+
+(*let write_two_regs r1 r2 vec =
+  let is_inc =
+    let is_inc_r1 = is_inc_of_reg r1 in
+    let is_inc_r2 = is_inc_of_reg r2 in
+    let () = ensure (is_inc_r1 = is_inc_r2)
+                    "write_two_regs called with vectors of different direction" in
+    is_inc_r1 in
+
+  let (size_r1 : integer) = size_of_reg r1 in
+  let (start_vec : integer) = get_start vec in
+  let size_vec = length vec in
+  let r1_v =
+    if is_inc
+    then slice vec start_vec (size_r1 - start_vec - 1)
+    else slice vec start_vec (start_vec - size_r1 - 1) in
+  let r2_v =
+    if is_inc
+    then slice vec (size_r1 - start_vec) (size_vec - start_vec)
+    else slice vec (start_vec - size_r1) (start_vec - size_vec) in
+  write_reg r1 r1_v >> write_reg r2 r2_v*)
+
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_prompt_monad.v b/snapshots/coq/lib/coq/Sail2_prompt_monad.v
new file mode 100644
index 00000000..43e873f7
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_prompt_monad.v
@@ -0,0 +1,252 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import String.
+(*Require Import Sail_impl_base*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+
+
+
+Definition register_name := string.
+Definition address := list bitU.
+
+Inductive monad regval a e :=
+  | Done : a -> monad regval a e
+  (* Read a number : bytes from memory, returned in little endian order *)
+  | Read_mem : read_kind -> address -> nat -> (list memory_byte -> monad regval a e) -> monad regval a e
+  (* Read the tag : a memory address *)
+  | Read_tag : address -> (bitU -> monad regval a e) -> monad regval a e
+  (* Tell the system a write is imminent, at address lifted, : size nat *)
+  | Write_ea : write_kind -> address -> nat -> monad regval a e -> monad regval a e
+  (* Request the result : store-exclusive *)
+  | Excl_res : (bool -> monad regval a e) -> monad regval a e
+  (* Request to write memory at last signalled address. Memory value should be 8
+     times the size given in ea signal, given in little endian order *)
+  | Write_memv : list memory_byte -> (bool -> monad regval a e) -> monad regval a e
+  (* Request to write the tag at last signalled address. *)
+  | Write_tag : address -> bitU -> (bool -> monad regval a e) -> monad regval a e
+  (* Tell the system to dynamically recalculate dependency footprint *)
+  | Footprint : monad regval a e -> monad regval a e
+  (* Request a memory barrier *)
+  | Barrier : barrier_kind -> monad regval a e -> monad regval a e
+  (* Request to read register, will track dependency when mode.track_values *)
+  | Read_reg : register_name -> (regval -> monad regval a e) -> monad regval a e
+  (* Request to write register *)
+  | Write_reg : register_name -> regval -> monad regval a e -> monad regval a e
+  | Undefined : (bool -> monad regval a e) -> monad regval a e
+  (*Result : a failed assert with possible error message to report*)
+  | Fail : string -> monad regval a e
+  | Error : string -> monad regval a e
+  (* Exception : type e *)
+  | Exception : e -> monad regval a e.
+  (* TODO: Reading/writing tags *)
+
+Arguments Done [_ _ _].
+Arguments Read_mem [_ _ _].
+Arguments Read_tag [_ _ _].
+Arguments Write_ea [_ _ _].
+Arguments Excl_res [_ _ _].
+Arguments Write_memv [_ _ _].
+Arguments Write_tag [_ _ _].
+Arguments Footprint [_ _ _].
+Arguments Barrier [_ _ _].
+Arguments Read_reg [_ _ _].
+Arguments Write_reg [_ _ _].
+Arguments Undefined [_ _ _].
+Arguments Fail [_ _ _].
+Arguments Error [_ _ _].
+Arguments Exception [_ _ _].
+
+(*val return : forall rv a e. a -> monad rv a e*)
+Definition returnm {rv A E} (a : A) : monad rv A E := Done a.
+
+(*val bind : forall rv a b e. monad rv a e -> (a -> monad rv b e) -> monad rv b e*)
+Fixpoint bind {rv A B E} (m : monad rv A E) (f : A -> monad rv B E) := match m with
+  | Done a => f a
+  | Read_mem rk a sz k => Read_mem rk a sz (fun v => bind (k v) f)
+  | Read_tag a k =>       Read_tag a       (fun v => bind (k v) f)
+  | Write_memv descr k => Write_memv descr (fun v => bind (k v) f)
+  | Write_tag a t k =>    Write_tag a t    (fun v => bind (k v) f)
+  | Read_reg descr k =>   Read_reg descr   (fun v => bind (k v) f)
+  | Excl_res k =>         Excl_res         (fun v => bind (k v) f)
+  | Undefined k =>        Undefined        (fun v => bind (k v) f)
+  | Write_ea wk a sz k => Write_ea wk a sz (bind k f)
+  | Footprint k =>        Footprint        (bind k f)
+  | Barrier bk k =>       Barrier bk       (bind k f)
+  | Write_reg r v k =>    Write_reg r v    (bind k f)
+  | Fail descr =>         Fail descr
+  | Error descr =>        Error descr
+  | Exception e =>        Exception e
+end.
+
+Notation "m >>= f" := (bind m f) (at level 50, left associativity).
+(*val (>>) : forall rv b e. monad rv unit e -> monad rv b e -> monad rv b e*)
+Definition bind0 {rv A E} (m : monad rv unit E) (n : monad rv A E) :=
+  m >>= fun (_ : unit) => n.
+Notation "m >> n" := (bind0 m n) (at level 50, left associativity).
+
+(*val exit : forall rv a e. unit -> monad rv a e*)
+Definition exit {rv A E} (_ : unit) : monad rv A E := Fail "exit".
+
+(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*)
+Definition undefined_bool {rv e} (_:unit) : monad rv bool e := Undefined returnm.
+
+(*val assert_exp : forall rv e. bool -> string -> monad rv unit e*)
+Definition assert_exp {rv E} (exp :bool) msg : monad rv unit E :=
+ if exp then Done tt else Fail msg.
+
+Definition assert_exp' {rv E} (exp :bool) msg : monad rv (exp = true) E :=
+ if exp return monad rv (exp = true) E then Done eq_refl else Fail msg.
+Definition bindH {rv A P E} (m : monad rv P E) (n : monad rv A E) :=
+  m >>= fun (H : P) => n.
+Notation "m >>> n" := (bindH m n) (at level 50, left associativity).
+
+(*val throw : forall rv a e. e -> monad rv a e*)
+Definition throw {rv A E} e : monad rv A E := Exception e.
+
+(*val try_catch : forall rv a e1 e2. monad rv a e1 -> (e1 -> monad rv a e2) -> monad rv a e2*)
+Fixpoint try_catch {rv A E1 E2} (m : monad rv A E1) (h : E1 -> monad rv A E2) := match m with
+  | Done a =>             Done a
+  | Read_mem rk a sz k => Read_mem rk a sz (fun v => try_catch (k v) h)
+  | Read_tag a k =>       Read_tag a       (fun v => try_catch (k v) h)
+  | Write_memv descr k => Write_memv descr (fun v => try_catch (k v) h)
+  | Write_tag a t k =>    Write_tag a t     (fun v => try_catch (k v) h)
+  | Read_reg descr k =>   Read_reg descr   (fun v => try_catch (k v) h)
+  | Excl_res k =>         Excl_res         (fun v => try_catch (k v) h)
+  | Undefined k =>        Undefined        (fun v => try_catch (k v) h)
+  | Write_ea wk a sz k => Write_ea wk a sz (try_catch k h)
+  | Footprint k =>        Footprint        (try_catch k h)
+  | Barrier bk k =>       Barrier bk       (try_catch k h)
+  | Write_reg r v k =>    Write_reg r v    (try_catch k h)
+  | Fail descr =>         Fail descr
+  | Error descr =>        Error descr
+  | Exception e =>        h e
+end.
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is "either r e", where "inr e"
+   represents a proper exception and "inl r" an early return : value "r". *)
+Definition monadR rv a r e := monad rv a (sum r e).
+
+(*val early_return : forall rv a r e. r -> monadR rv a r e*)
+Definition early_return {rv A R E} (r : R) : monadR rv A R E := throw (inl r).
+
+(*val catch_early_return : forall rv a e. monadR rv a a e -> monad rv a e*)
+Definition catch_early_return {rv A E} (m : monadR rv A A E) :=
+  try_catch m
+    (fun r => match r with
+      | inl a => returnm a
+      | inr e => throw e
+     end).
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftR : forall rv a r e. monad rv a e -> monadR rv a r e*)
+Definition liftR {rv A R E} (m : monad rv A E) : monadR rv A R E :=
+ try_catch m (fun e => throw (inr e)).
+
+(* Catch exceptions in the presence : early returns *)
+(*val try_catchR : forall rv a r e1 e2. monadR rv a r e1 -> (e1 -> monadR rv a r e2) ->  monadR rv a r e2*)
+Definition try_catchR {rv A R E1 E2} (m : monadR rv A R E1) (h : E1 -> monadR rv A R E2) :=
+  try_catch m
+    (fun r => match r with
+      | inl r => throw (inl r)
+      | inr e => h e
+     end).
+
+(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*)
+Definition maybe_fail {rv A E} msg (x : option A) : monad rv A E :=
+match x with
+  | Some a => returnm a
+  | None => Fail msg
+end.
+
+(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*)
+Definition read_mem_bytes {rv A E} rk (addr : mword A) sz : monad rv (list memory_byte) E :=
+  Read_mem rk (bits_of addr) (Z.to_nat sz) returnm.
+
+(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*)
+Definition read_mem {rv A B E} `{ArithFact (B >= 0)} rk (addr : mword A) sz : monad rv (mword B) E :=
+  bind
+    (read_mem_bytes rk addr sz)
+    (fun bytes =>
+       maybe_fail "bits_of_mem_bytes" (of_bits (bits_of_mem_bytes bytes))).
+
+(*val read_tag : forall rv a e. Bitvector a => a -> monad rv bitU e*)
+Definition read_tag {rv a e} `{Bitvector a} (addr : a) : monad rv bitU e :=
+ Read_tag (bits_of addr) returnm.
+
+(*val excl_result : forall rv e. unit -> monad rv bool e*)
+Definition excl_result {rv e} (_:unit) : monad rv bool e :=
+  let k successful := (returnm successful) in
+  Excl_res k.
+
+Definition write_mem_ea {rv a E} `{Bitvector a} wk (addr: a) sz : monad rv unit E :=
+ Write_ea wk (bits_of addr) (Z.to_nat sz) (Done tt).
+
+Definition write_mem_val {rv a e} `{Bitvector a} (v : a) : monad rv bool e := match mem_bytes_of_bits v with
+  | Some v => Write_memv v returnm
+  | None => Fail "write_mem_val"
+end.
+
+(*val write_tag : forall rv a e. Bitvector 'a => 'a -> bitU -> monad rv bool e*)
+Definition write_tag {rv a e} (addr : mword a) (b : bitU) : monad rv bool e := Write_tag (bits_of addr) b returnm.
+
+Definition read_reg {s rv a e} (reg : register_ref s rv a) : monad rv a e :=
+  let k v :=
+    match reg.(of_regval) v with
+      | Some v => Done v
+      | None => Error "read_reg: unrecognised value"
+    end
+  in
+  Read_reg reg.(name) k.
+
+(* TODO
+val read_reg_range : forall s r rv a e. Bitvector a => register_ref s rv r -> integer -> integer -> monad rv a e
+Definition read_reg_range reg i j :=
+  read_reg_aux of_bits (external_reg_slice reg (natFromInteger i,natFromInteger j))
+
+Definition read_reg_bit reg i :=
+  read_reg_aux (fun v -> v) (external_reg_slice reg (natFromInteger i,natFromInteger i)) >>= fun v ->
+  returnm (extract_only_element v)
+
+Definition read_reg_field reg regfield :=
+  read_reg_aux (external_reg_field_whole reg regfield)
+
+Definition read_reg_bitfield reg regfield :=
+  read_reg_aux (external_reg_field_whole reg regfield) >>= fun v ->
+  returnm (extract_only_element v)*)
+
+Definition reg_deref {s rv a e} := @read_reg s rv a e.
+
+(*Parameter write_reg : forall {s rv a e}, register_ref s rv a -> a -> monad rv unit e.*)
+Definition write_reg {s rv a e} (reg : register_ref s rv a) (v : a) : monad rv unit e :=
+ Write_reg reg.(name) (reg.(regval_of) v) (Done tt).
+
+(* TODO
+Definition write_reg reg v :=
+  write_reg_aux (external_reg_whole reg) v
+Definition write_reg_range reg i j v :=
+  write_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) v
+Definition write_reg_pos reg i v :=
+  let iN := natFromInteger i in
+  write_reg_aux (external_reg_slice reg (iN,iN)) [v]
+Definition write_reg_bit := write_reg_pos
+Definition write_reg_field reg regfield v :=
+  write_reg_aux (external_reg_field_whole reg regfield.field_name) v
+Definition write_reg_field_bit reg regfield bit :=
+  write_reg_aux (external_reg_field_whole reg regfield.field_name)
+                (Vector [bit] 0 (is_inc_of_reg reg))
+Definition write_reg_field_range reg regfield i j v :=
+  write_reg_aux (external_reg_field_slice reg regfield.field_name (natFromInteger i,natFromInteger j)) v
+Definition write_reg_field_pos reg regfield i v :=
+  write_reg_field_range reg regfield i i [v]
+Definition write_reg_field_bit := write_reg_field_pos*)
+
+(*val barrier : forall rv e. barrier_kind -> monad rv unit e*)
+Definition barrier {rv e} bk : monad rv unit e := Barrier bk (Done tt).
+
+(*val footprint : forall rv e. unit -> monad rv unit e*)
+Definition footprint {rv e} (_ : unit) : monad rv unit e := Footprint (Done tt).
diff --git a/snapshots/coq/lib/coq/Sail2_state.v b/snapshots/coq/lib/coq/Sail2_state.v
new file mode 100644
index 00000000..404309e0
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_state.v
@@ -0,0 +1,74 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(*Require Import Sail_impl_base*)
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state_monad.
+(*
+(* State monad wrapper around prompt monad *)
+
+val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e
+let rec liftState ra s = match s with
+  | (Done a)             -> returnS a
+  | (Read_mem rk a sz k) -> bindS (read_mem_bytesS rk a sz) (fun v -> liftState ra (k v))
+  | (Read_tag t k)       -> bindS (read_tagS t)             (fun v -> liftState ra (k v))
+  | (Write_memv a k)     -> bindS (write_mem_bytesS a)      (fun v -> liftState ra (k v))
+  | (Write_tagv t k)     -> bindS (write_tagS t)            (fun v -> liftState ra (k v))
+  | (Read_reg r k)       -> bindS (read_regvalS ra r)       (fun v -> liftState ra (k v))
+  | (Excl_res k)         -> bindS (excl_resultS ())         (fun v -> liftState ra (k v))
+  | (Undefined k)        -> bindS (undefined_boolS ())      (fun v -> liftState ra (k v))
+  | (Write_ea wk a sz k) -> seqS (write_mem_eaS wk a sz)    (liftState ra k)
+  | (Write_reg r v k)    -> seqS (write_regvalS ra r v)     (liftState ra k)
+  | (Footprint k)        -> liftState ra k
+  | (Barrier _ k)        -> liftState ra k
+  | (Fail descr)         -> failS descr
+  | (Error descr)        -> failS descr
+  | (Exception e)        -> throwS e
+end
+
+
+val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e
+let rec iterS_aux i f xs = match xs with
+  | x :: xs -> f i x >>$ iterS_aux (i + 1) f xs
+  | [] -> returnS ()
+  end
+
+declare {isabelle} termination_argument iterS_aux = automatic
+
+val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e
+let iteriS f xs = iterS_aux 0 f xs
+
+val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e
+let iterS f xs = iteriS (fun _ x -> f x) xs
+
+val foreachS : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec foreachS xs vars body = match xs with
+  | [] -> returnS vars
+  | x :: xs ->
+     body x vars >>$= fun vars ->
+     foreachS xs vars body
+end
+
+declare {isabelle} termination_argument foreachS = automatic
+
+
+val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec whileS vars cond body s =
+  (cond vars >>$= (fun cond_val s' ->
+  if cond_val then
+    (body vars >>$= (fun vars s'' -> whileS vars cond body s'')) s'
+  else returnS vars s')) s
+
+val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec untilS vars cond body s =
+  (body vars >>$= (fun vars s' ->
+  (cond vars >>$= (fun cond_val s'' ->
+  if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_state_monad.v b/snapshots/coq/lib/coq/Sail2_state_monad.v
new file mode 100644
index 00000000..5258c37a
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_state_monad.v
@@ -0,0 +1,258 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+(*
+(* 'a is result type *)
+
+type memstate = map integer memory_byte
+type tagstate = map integer bitU
+(* type regstate = map string (vector bitU) *)
+
+type sequential_state 'regs =
+  <| regstate : 'regs;
+     memstate : memstate;
+     tagstate : tagstate;
+     write_ea : maybe (write_kind * integer * integer);
+     last_exclusive_operation_was_load : bool|>
+
+val init_state : forall 'regs. 'regs -> sequential_state 'regs
+let init_state regs =
+  <| regstate = regs;
+     memstate = Map.empty;
+     tagstate = Map.empty;
+     write_ea = Nothing;
+     last_exclusive_operation_was_load = false |>
+
+type ex 'e =
+  | Failure of string
+  | Throw of 'e
+
+type result 'a 'e =
+  | Value of 'a
+  | Ex of (ex 'e)
+
+(* State, nondeterminism and exception monad with result value type 'a
+   and exception type 'e. *)
+type monadS 'regs 'a 'e = sequential_state 'regs -> list (result 'a 'e * sequential_state 'regs)
+
+val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e
+let returnS a s = [(Value a,s)]
+
+val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e
+let bindS m f (s : sequential_state 'regs) =
+  List.concatMap (function
+                  | (Value a, s') -> f a s'
+                  | (Ex e, s') -> [(Ex e, s')]
+                  end) (m s)
+
+val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e
+let seqS m n = bindS m (fun (_ : unit) -> n)
+
+let inline (>>$=) = bindS
+let inline (>>$) = seqS
+
+val chooseS : forall 'regs 'a 'e. list 'a -> monadS 'regs 'a 'e
+let chooseS xs s = List.map (fun x -> (Value x, s)) xs
+
+val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e
+let readS f = (fun s -> returnS (f s) s)
+
+val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e
+let updateS f = (fun s -> returnS () (f s))
+
+val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e
+let failS msg s = [(Ex (Failure msg), s)]
+
+val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e
+let exitS () = failS "exit"
+
+val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e
+let throwS e s = [(Ex (Throw e), s)]
+
+val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) ->  monadS 'regs 'a 'e2
+let try_catchS m h s =
+  List.concatMap (function
+                  | (Value a, s') -> returnS a s'
+                  | (Ex (Throw e), s') -> h e s'
+                  | (Ex (Failure msg), s') -> [(Ex (Failure msg), s')]
+                  end) (m s)
+
+val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e
+let assert_expS exp msg = if exp then returnS () else failS msg
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is "either 'r 'e", where "Right e"
+   represents a proper exception and "Left r" an early return of value "r". *)
+type monadSR 'regs 'a 'r 'e = monadS 'regs 'a (either 'r 'e)
+
+val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e
+let early_returnS r = throwS (Left r)
+
+val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e
+let catch_early_returnS m =
+  try_catchS m
+    (function
+      | Left a -> returnS a
+      | Right e -> throwS e
+     end)
+
+(* Lift to monad with early return by wrapping exceptions *)
+val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e
+let liftSR m = try_catchS m (fun e -> throwS (Right e))
+
+(* Catch exceptions in the presence of early returns *)
+val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) ->  monadSR 'regs 'a 'r 'e2
+let try_catchSR m h =
+  try_catchS m
+    (function
+      | Left r -> throwS (Left r)
+      | Right e -> h e
+     end)
+
+val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e
+let read_tagS addr =
+  readS (fun s -> fromMaybe B0 (Map.lookup (unsigned addr) s.tagstate))
+
+(* Read bytes from memory and return in little endian order *)
+val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e
+let read_mem_bytesS read_kind addr sz =
+  let addr = unsigned addr in
+  let sz = integerFromNat sz in
+  let addrs = index_list addr (addr+sz-1) 1 in
+  let read_byte s addr = Map.lookup addr s.memstate in
+  readS (fun s -> just_list (List.map (read_byte s) addrs)) >>$= (function
+    | Just mem_val ->
+       updateS (fun s ->
+         if read_is_exclusive read_kind
+         then <| s with last_exclusive_operation_was_load = true |>
+         else s) >>$
+       returnS mem_val
+    | Nothing -> failS "read_memS"
+  end)
+
+val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e
+let read_memS rk a sz =
+  read_mem_bytesS rk a (natFromInteger sz) >>$= (fun bytes ->
+  returnS (bits_of_mem_bytes bytes))
+
+val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e
+let excl_resultS () =
+  readS (fun s -> s.last_exclusive_operation_was_load) >>$= (fun excl_load ->
+  updateS (fun s -> <| s with last_exclusive_operation_was_load = false |>) >>$
+  chooseS (if excl_load then [false; true] else [false]))
+
+val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e
+let write_mem_eaS write_kind addr sz =
+  let addr = unsigned addr in
+  let sz = integerFromNat sz in
+  updateS (fun s -> <| s with write_ea = Just (write_kind, addr, sz) |>)
+
+(* Write little-endian list of bytes to previously announced address *)
+val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e
+let write_mem_bytesS v =
+  readS (fun s -> s.write_ea) >>$= (function
+      | Nothing -> failS "write ea has not been announced yet"
+      | Just (_, addr, sz) ->
+         let addrs = index_list addr (addr+sz-1) 1 in
+         (*let v = external_mem_value (bits_of v) in*)
+         let a_v = List.zip addrs v in
+         let write_byte mem (addr, v) = Map.insert addr v mem in
+         updateS (fun s ->
+           <| s with memstate = List.foldl write_byte s.memstate a_v |>) >>$
+         returnS true
+    end)
+
+val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e
+let write_mem_valS v = match mem_bytes_of_bits v with
+  | Just v -> write_mem_bytesS v
+  | Nothing -> failS "write_mem_val"
+end
+
+val write_tagS : forall 'regs 'e. bitU -> monadS 'regs bool 'e
+let write_tagS t =
+  readS (fun s -> s.write_ea) >>$= (function
+      | Nothing -> failS "write ea has not been announced yet"
+      | Just (_, addr, _) ->
+         (*let taddr = addr / cap_alignment in*)
+         updateS (fun s -> <| s with tagstate = Map.insert addr t s.tagstate |>) >>$
+         returnS true
+    end)
+
+val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e
+let read_regS reg = readS (fun s -> reg.read_from s.regstate)
+
+(* TODO
+let read_reg_range reg i j state =
+  let v = slice (get_reg state (name_of_reg reg)) i j in
+  [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+  let v = access (get_reg state (name_of_reg reg)) i in
+  [(Value v,state)]
+let read_reg_field reg regfield =
+  let (i,j) = register_field_indices reg regfield in
+  read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+  let (i,_) = register_field_indices reg regfield in
+  read_reg_bit reg i *)
+
+val read_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e
+let read_regvalS (read, _) reg =
+  readS (fun s -> read reg s.regstate) >>$= (function
+      | Just v ->  returnS v
+      | Nothing -> failS ("read_regvalS " ^ reg)
+    end)
+
+val write_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e
+let write_regvalS (_, write) reg v =
+  readS (fun s -> write reg v s.regstate) >>$= (function
+      | Just rs' -> updateS (fun s -> <| s with regstate = rs' |>)
+      | Nothing ->  failS ("write_regvalS " ^ reg)
+    end)
+
+val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e
+let write_regS reg v =
+  updateS (fun s -> <| s with regstate = reg.write_to v s.regstate |>)
+
+(* TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+  let current_value = get_reg state reg in
+  let new_value = f current_value v in
+  [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_values.v b/snapshots/coq/lib/coq/Sail2_values.v
new file mode 100644
index 00000000..f1f5f1de
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_values.v
@@ -0,0 +1,1576 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(* Version of sail_values.lem that uses Lems machine words library *)
+
+(*Require Import Sail_impl_base*)
+Require Export ZArith.
+Require Import Ascii.
+Require Export String.
+Require Import bbv.Word.
+Require Export List.
+Require Export Sumbool.
+Require Export DecidableClass.
+Import ListNotations.
+
+Open Scope Z.
+
+(* Constraint solving basics.  A HintDb which unfolding hints and lemmata
+   can be added to, and a typeclass to wrap constraint arguments in to
+   trigger automatic solving. *)
+Create HintDb sail.
+Class ArithFact (P : Prop) := { fact : P }.
+Lemma use_ArithFact {P} `(ArithFact P) : P.
+apply fact.
+Defined.
+
+Definition build_ex (n:Z) {P:Z -> Prop} `{H:ArithFact (P n)} : {x : Z & ArithFact (P x)} :=
+  existT _ n H.
+
+Definition generic_eq {T:Type} (x y:T) `{Decidable (x = y)} := Decidable_witness.
+Definition generic_neq {T:Type} (x y:T) `{Decidable (x = y)} := negb Decidable_witness.
+Lemma generic_eq_true {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = true -> x = y.
+apply Decidable_spec.
+Qed.
+Lemma generic_eq_false {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = false -> x <> y.
+unfold generic_eq.
+intros H1 H2.
+rewrite <- Decidable_spec in H2.
+congruence.
+Qed.
+Lemma generic_neq_true {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = true -> x <> y.
+unfold generic_neq.
+intros H1 H2.
+rewrite <- Decidable_spec in H2.
+destruct Decidable_witness; simpl in *; 
+congruence.
+Qed.
+Lemma generic_neq_false {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = false -> x = y.
+unfold generic_neq.
+intro H1.
+rewrite <- Decidable_spec.
+destruct Decidable_witness; simpl in *; 
+congruence.
+Qed.
+Instance Decidable_eq_from_dec {T:Type} (eqdec: forall x y : T, {x = y} + {x <> y}) : 
+  forall (x y : T), Decidable (eq x y) := {
+  Decidable_witness := proj1_sig (bool_of_sumbool (eqdec x y))
+}.
+destruct (eqdec x y); simpl; split; congruence.
+Qed.
+
+
+(* Project away range constraints in comparisons *)
+Definition ltb_range_l {P} (l : sigT P) r := Z.ltb (projT1 l) r.
+Definition leb_range_l {P} (l : sigT P) r := Z.leb (projT1 l) r.
+Definition gtb_range_l {P} (l : sigT P) r := Z.gtb (projT1 l) r.
+Definition geb_range_l {P} (l : sigT P) r := Z.geb (projT1 l) r.
+Definition ltb_range_r {P} l (r : sigT P) := Z.ltb l (projT1 r).
+Definition leb_range_r {P} l (r : sigT P) := Z.leb l (projT1 r).
+Definition gtb_range_r {P} l (r : sigT P) := Z.gtb l (projT1 r).
+Definition geb_range_r {P} l (r : sigT P) := Z.geb l (projT1 r).
+
+Definition ii := Z.
+Definition nn := nat.
+
+(*val pow : Z -> Z -> Z*)
+Definition pow m n := m ^ n.
+
+Definition pow2 n := pow 2 n.
+(*
+Definition inline lt := (<)
+Definition inline gt := (>)
+Definition inline lteq := (<=)
+Definition inline gteq := (>=)
+
+val eq : forall a. Eq a => a -> a -> bool
+Definition inline eq l r := (l = r)
+
+val neq : forall a. Eq a => a -> a -> bool*)
+Definition neq l r := (negb (l =? r)). (* Z only *)
+
+(*let add_int l r := integerAdd l r
+Definition add_signed l r := integerAdd l r
+Definition sub_int l r := integerMinus l r
+Definition mult_int l r := integerMult l r
+Definition div_int l r := integerDiv l r
+Definition div_nat l r := natDiv l r
+Definition power_int_nat l r := integerPow l r
+Definition power_int_int l r := integerPow l (Z.to_nat r)
+Definition negate_int i := integerNegate i
+Definition min_int l r := integerMin l r
+Definition max_int l r := integerMax l r
+
+Definition add_real l r := realAdd l r
+Definition sub_real l r := realMinus l r
+Definition mult_real l r := realMult l r
+Definition div_real l r := realDiv l r
+Definition negate_real r := realNegate r
+Definition abs_real r := realAbs r
+Definition power_real b e := realPowInteger b e*)
+
+Definition print_int (_ : string) (_ : Z) : unit := tt.
+
+(*
+Definition or_bool l r := (l || r)
+Definition and_bool l r := (l && r)
+Definition xor_bool l r := xor l r
+*)
+Definition append_list {A:Type} (l : list A) r := l ++ r.
+Definition length_list {A:Type} (xs : list A) := Z.of_nat (List.length xs).
+Definition take_list {A:Type} n (xs : list A) := firstn (Z.to_nat n) xs.
+Definition drop_list {A:Type} n (xs : list A) := skipn (Z.to_nat n) xs.
+(*
+val repeat : forall a. list a -> Z -> list a*)
+Fixpoint repeat' {a} (xs : list a) n :=
+  match n with
+  | O => []
+  | S n => xs ++ repeat' xs n
+  end.
+Lemma repeat'_length {a} {xs : list a} {n : nat} : List.length (repeat' xs n) = (n * List.length xs)%nat.
+induction n.
+* reflexivity.
+* simpl.
+  rewrite app_length.
+  auto with arith.
+Qed.
+Definition repeat {a} (xs : list a) (n : Z) :=
+  if n <=? 0 then []
+  else repeat' xs (Z.to_nat n).
+Lemma repeat_length {a} {xs : list a} {n : Z} (H : n >= 0) : length_list (repeat xs n) = n * length_list xs.
+unfold length_list, repeat.
+destruct n.
++ reflexivity. 
++ simpl (List.length _).
+  rewrite repeat'_length.
+  rewrite Nat2Z.inj_mul.
+  rewrite positive_nat_Z.
+  reflexivity.  
++ exfalso.
+  auto with zarith.
+Qed.
+
+(*declare {isabelle} termination_argument repeat = automatic
+
+Definition duplicate_to_list bit length := repeat [bit] length
+
+Fixpoint replace bs (n : Z) b' := match bs with
+  | [] => []
+  | b :: bs =>
+     if n = 0 then b' :: bs
+              else b :: replace bs (n - 1) b'
+  end
+declare {isabelle} termination_argument replace = automatic
+
+Definition upper n := n
+
+(* Modulus operation corresponding to quot below -- result
+   has sign of dividend. *)
+Definition hardware_mod (a: Z) (b:Z) : Z :=
+  let m := (abs a) mod (abs b) in
+  if a < 0 then ~m else m
+
+(* There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that *)
+Definition hardware_quot (a:Z) (b:Z) : Z :=
+  let q := (abs a) / (abs b) in
+  if ((a<0) = (b<0)) then
+    q  (* same sign -- result positive *)
+  else
+    ~q (* different sign -- result negative *)
+
+Definition max_64u := (integerPow 2 64) - 1
+Definition max_64  := (integerPow 2 63) - 1
+Definition min_64  := 0 - (integerPow 2 63)
+Definition max_32u := (4294967295 : Z)
+Definition max_32  := (2147483647 : Z)
+Definition min_32  := (0 - 2147483648 : Z)
+Definition max_8   := (127 : Z)
+Definition min_8   := (0 - 128 : Z)
+Definition max_5   := (31 : Z)
+Definition min_5   := (0 - 32 : Z)
+*)
+
+(* just_list takes a list of maybes and returns Some xs if all elements have
+   a value, and None if one of the elements is None. *)
+(*val just_list : forall a. list (option a) -> option (list a)*)
+Fixpoint just_list {A} (l : list (option A)) := match l with
+  | [] => Some []
+  | (x :: xs) =>
+    match (x, just_list xs) with
+      | (Some x, Some xs) => Some (x :: xs)
+      | (_, _) => None
+    end
+  end.
+(*declare {isabelle} termination_argument just_list = automatic
+
+lemma just_list_spec:
+  ((forall xs. (just_list xs = None) <-> List.elem None xs) &&
+   (forall xs es. (just_list xs = Some es) <-> (xs = List.map Some es)))*)
+
+Lemma just_list_length {A} : forall (l : list (option A)) (l' : list A),
+  Some l' = just_list l -> List.length l = List.length l'.
+induction l.
+* intros.
+  simpl in H.
+  inversion H.
+  reflexivity.
+* intros.
+  destruct a; simplify_eq H.
+  simpl in *.
+  destruct (just_list l); simplify_eq H.
+  intros.
+  subst.
+  simpl.
+  f_equal.
+  apply IHl.
+  reflexivity.
+Qed.
+
+Lemma just_list_length_Z {A} : forall (l : list (option A)) l', Some l' = just_list l -> length_list l = length_list l'.
+unfold length_list.
+intros.
+f_equal.
+auto using just_list_length.
+Qed.
+
+(*** Bits *)
+Inductive bitU := B0 | B1 | BU.
+
+Definition showBitU b :=
+match b with
+  | B0 => "O"
+  | B1 => "I"
+  | BU => "U"
+end%string.
+
+Definition bitU_char b :=
+match b with
+| B0 => "0"
+| B1 => "1"
+| BU => "?"
+end%char.
+
+(*instance (Show bitU)
+  let show := showBitU
+end*)
+
+Class BitU (a : Type) : Type := {
+  to_bitU : a -> bitU;
+  of_bitU : bitU -> a
+}.
+
+Instance bitU_BitU : (BitU bitU) := {
+  to_bitU b := b;
+  of_bitU b := b
+}.
+
+Definition bool_of_bitU bu := match bu with
+  | B0 => Some false
+  | B1 => Some true
+  | BU => None
+  end.
+
+Definition bitU_of_bool (b : bool) := if b then B1 else B0.
+
+(*Instance bool_BitU : (BitU bool) := {
+  to_bitU := bitU_of_bool;
+  of_bitU := bool_of_bitU
+}.*)
+
+Definition cast_bit_bool := bool_of_bitU.
+(*
+Definition bit_lifted_of_bitU bu := match bu with
+  | B0 => Bitl_zero
+  | B1 => Bitl_one
+  | BU => Bitl_undef
+  end.
+
+Definition bitU_of_bit := function
+  | Bitc_zero => B0
+  | Bitc_one  => B1
+  end.
+
+Definition bit_of_bitU := function
+  | B0 => Bitc_zero
+  | B1 => Bitc_one
+  | BU => failwith "bit_of_bitU: BU"
+  end.
+
+Definition bitU_of_bit_lifted := function
+  | Bitl_zero => B0
+  | Bitl_one  => B1
+  | Bitl_undef => BU
+  | Bitl_unknown => failwith "bitU_of_bit_lifted Bitl_unknown"
+  end.
+*)
+Definition not_bit b :=
+match b with
+  | B1 => B0
+  | B0 => B1
+  | BU => BU
+  end.
+
+(*val is_one : Z -> bitU*)
+Definition is_one (i : Z) :=
+  if i =? 1 then B1 else B0.
+
+Definition binop_bit op x y :=
+  match (x, y) with
+  | (BU,_) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*)
+  | (_,BU) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*)
+  | (x,y) => bitU_of_bool (op (bool_of_bitU x) (bool_of_bitU y))
+  end.
+
+(*val and_bit : bitU -> bitU -> bitU
+Definition and_bit := binop_bit (&&)
+
+val or_bit : bitU -> bitU -> bitU
+Definition or_bit := binop_bit (||)
+
+val xor_bit : bitU -> bitU -> bitU
+Definition xor_bit := binop_bit xor
+
+val (&.) : bitU -> bitU -> bitU
+Definition inline (&.) x y := and_bit x y
+
+val (|.) : bitU -> bitU -> bitU
+Definition inline (|.) x y := or_bit x y
+
+val (+.) : bitU -> bitU -> bitU
+Definition inline (+.) x y := xor_bit x y
+*)
+
+(*** Bool lists ***)
+
+(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
+Fixpoint bools_of_nat_aux len (x : nat) (acc : list bool) : list bool :=
+  match len with
+  | O => acc
+  | S len' => bools_of_nat_aux len' (x / 2) ((if x mod 2 =? 1 then true else false) :: acc)
+  end %nat.
+  (*else (if x mod 2 = 1 then true else false) :: bools_of_nat_aux (x / 2)*)
+(*declare {isabelle} termination_argument bools_of_nat_aux = automatic*)
+Definition bools_of_nat len n := bools_of_nat_aux (Z.to_nat len) n [] (*List.reverse (bools_of_nat_aux n)*).
+
+(*val nat_of_bools_aux : natural -> list bool -> natural*)
+Fixpoint nat_of_bools_aux (acc : nat) (bs : list bool) : nat :=
+  match bs with
+  | [] => acc
+  | true :: bs => nat_of_bools_aux ((2 * acc) + 1) bs
+  | false :: bs => nat_of_bools_aux (2 * acc) bs
+end.
+(*declare {isabelle; hol} termination_argument nat_of_bools_aux = automatic*)
+Definition nat_of_bools bs := nat_of_bools_aux 0 bs.
+
+(*val unsigned_of_bools : list bool -> integer*)
+Definition unsigned_of_bools bs := Z.of_nat (nat_of_bools bs).
+
+(*val signed_of_bools : list bool -> integer*)
+Definition signed_of_bools bs :=
+  match bs with
+    | true :: _  => 0 - (1 + (unsigned_of_bools (List.map negb bs)))
+    | false :: _ => unsigned_of_bools bs
+    | [] => 0 (* Treat empty list as all zeros *)
+  end.
+
+(*val int_of_bools : bool -> list bool -> integer*)
+Definition int_of_bools (sign : bool) bs := if sign then signed_of_bools bs else unsigned_of_bools bs.
+
+(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
+Fixpoint pad_list_nat {a} (x : a) (xs : list a) n :=
+  match n with
+  | O => xs
+  | S n' => pad_list_nat x (x :: xs) n'
+  end.
+(*declare {isabelle} termination_argument pad_list = automatic*)
+Definition pad_list {a} x xs n := @pad_list_nat a x xs (Z.to_nat n).
+
+Definition ext_list {a} pad len (xs : list a) :=
+  let longer := len - (Z.of_nat (List.length xs)) in
+  if longer <? 0 then skipn (Z.abs_nat (longer)) xs
+  else pad_list pad xs longer.
+
+(*let extz_bools len bs = ext_list false len bs*)
+Definition exts_bools len bs :=
+  match bs with
+    | true :: _ => ext_list true len bs
+    | _ => ext_list false len bs
+  end.
+
+Fixpoint add_one_bool_ignore_overflow_aux bits := match bits with
+  | [] => []
+  | false :: bits => true :: bits
+  | true :: bits => false :: add_one_bool_ignore_overflow_aux bits
+end.
+(*declare {isabelle; hol} termination_argument add_one_bool_ignore_overflow_aux = automatic*)
+
+Definition add_one_bool_ignore_overflow bits :=
+  List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)).
+
+(*let bool_list_of_int n =
+  let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
+  if n >= (0 : integer) then bs_abs
+  else add_one_bool_ignore_overflow (List.map not bs_abs)
+let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
+Definition bools_of_int len n :=
+  let bs_abs := bools_of_nat len (Z.abs_nat n) in
+  if n >=? 0 then bs_abs
+  else add_one_bool_ignore_overflow (List.map negb bs_abs).
+
+(*** Bit lists ***)
+
+(*val bits_of_nat_aux : natural -> list bitU*)
+Fixpoint bits_of_nat_aux n x :=
+  match n,x with
+  | O,_ => []
+  | _,O => []
+  | S n, S _ => (if x mod 2 =? 1 then B1 else B0) :: bits_of_nat_aux n (x / 2)
+  end%nat.
+(**declare {isabelle} termination_argument bits_of_nat_aux = automatic*)
+Definition bits_of_nat n := List.rev (bits_of_nat_aux n n).
+
+(*val nat_of_bits_aux : natural -> list bitU -> natural*)
+Fixpoint nat_of_bits_aux acc bs := match bs with
+  | [] => Some acc
+  | B1 :: bs => nat_of_bits_aux ((2 * acc) + 1) bs
+  | B0 :: bs => nat_of_bits_aux (2 * acc) bs
+  | BU :: bs => None
+end%nat.
+(*declare {isabelle} termination_argument nat_of_bits_aux = automatic*)
+Definition nat_of_bits bits := nat_of_bits_aux 0 bits.
+
+Definition not_bits := List.map not_bit.
+
+Definition binop_bits op bsl bsr :=
+  List.fold_right (fun '(bl, br) acc => binop_bit op bl br :: acc) [] (List.combine bsl bsr).
+(*
+Definition and_bits := binop_bits (&&)
+Definition or_bits := binop_bits (||)
+Definition xor_bits := binop_bits xor
+
+val unsigned_of_bits : list bitU -> Z*)
+Definition unsigned_of_bits bits :=
+match just_list (List.map bool_of_bitU bits) with
+| Some bs => Some (unsigned_of_bools bs)
+| None => None
+end.
+
+(*val signed_of_bits : list bitU -> Z*)
+Definition signed_of_bits bits :=
+  match just_list (List.map bool_of_bitU bits) with
+  | Some bs => Some (signed_of_bools bs)
+  | None => None
+  end.
+
+(*val int_of_bits : bool -> list bitU -> maybe integer*)
+Definition int_of_bits (sign : bool) bs :=
+ if sign then signed_of_bits bs else unsigned_of_bits bs.
+
+(*val pad_bitlist : bitU -> list bitU -> Z -> list bitU*)
+Fixpoint pad_bitlist_nat (b : bitU) bits n :=
+match n with
+| O => bits
+| S n' => pad_bitlist_nat b (b :: bits) n'
+end.
+Definition pad_bitlist b bits n := pad_bitlist_nat b bits (Z.to_nat n). (* Negative n will come out as 0 *)
+(*  if n <= 0 then bits else pad_bitlist b (b :: bits) (n - 1).
+declare {isabelle} termination_argument pad_bitlist = automatic*)
+
+Definition ext_bits pad len bits :=
+  let longer := len - (Z.of_nat (List.length bits)) in
+  if longer <? 0 then skipn (Z.abs_nat longer) bits
+  else pad_bitlist pad bits longer.
+
+Definition extz_bits len bits := ext_bits B0 len bits.
+Parameter undefined_list_bitU : list bitU.
+Definition exts_bits len bits :=
+  match bits with
+  | BU :: _ => undefined_list_bitU (*failwith "exts_bits: undefined bit"*)
+  | B1 :: _ => ext_bits B1 len bits
+  | _ => ext_bits B0 len bits
+  end.
+
+Fixpoint add_one_bit_ignore_overflow_aux bits := match bits with
+  | [] => []
+  | B0 :: bits => B1 :: bits
+  | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits
+  | BU :: _ => undefined_list_bitU (*failwith "add_one_bit_ignore_overflow: undefined bit"*)
+end.
+(*declare {isabelle} termination_argument add_one_bit_ignore_overflow_aux = automatic*)
+
+Definition add_one_bit_ignore_overflow bits :=
+  rev (add_one_bit_ignore_overflow_aux (rev bits)).
+
+Definition bitlist_of_int n :=
+  let bits_abs := B0 :: bits_of_nat (Z.abs_nat n) in
+  if n >=? 0 then bits_abs
+  else add_one_bit_ignore_overflow (not_bits bits_abs).
+
+Definition bits_of_int len n := exts_bits len (bitlist_of_int n).
+
+(*val arith_op_bits :
+  (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
+Definition arith_op_bits (op : Z -> Z -> Z) (sign : bool) l r :=
+  match (int_of_bits sign l, int_of_bits sign r) with
+    | (Some li, Some ri) => bits_of_int (length_list l) (op li ri)
+    | (_, _) => repeat [BU] (length_list l)
+  end.
+
+
+Definition char_of_nibble x :=
+  match x with
+  | (B0, B0, B0, B0) => Some "0"%char
+  | (B0, B0, B0, B1) => Some "1"%char
+  | (B0, B0, B1, B0) => Some "2"%char
+  | (B0, B0, B1, B1) => Some "3"%char
+  | (B0, B1, B0, B0) => Some "4"%char
+  | (B0, B1, B0, B1) => Some "5"%char
+  | (B0, B1, B1, B0) => Some "6"%char
+  | (B0, B1, B1, B1) => Some "7"%char
+  | (B1, B0, B0, B0) => Some "8"%char
+  | (B1, B0, B0, B1) => Some "9"%char
+  | (B1, B0, B1, B0) => Some "A"%char
+  | (B1, B0, B1, B1) => Some "B"%char
+  | (B1, B1, B0, B0) => Some "C"%char
+  | (B1, B1, B0, B1) => Some "D"%char
+  | (B1, B1, B1, B0) => Some "E"%char
+  | (B1, B1, B1, B1) => Some "F"%char
+  | _ => None
+  end.
+
+Fixpoint hexstring_of_bits bs := match bs with
+  | b1 :: b2 :: b3 :: b4 :: bs =>
+     let n := char_of_nibble (b1, b2, b3, b4) in
+     let s := hexstring_of_bits bs in
+     match (n, s) with
+     | (Some n, Some s) => Some (String n s)
+     | _ => None
+     end
+  | [] => Some EmptyString
+  | _ => None
+  end%string.
+
+Fixpoint binstring_of_bits bs := match bs with
+  | b :: bs => String (bitU_char b) (binstring_of_bits bs)
+  | [] => EmptyString
+  end.
+
+Definition show_bitlist bs :=
+  match hexstring_of_bits bs with
+  | Some s => String "0" (String "x" s)
+  | None => String "0" (String "b" (binstring_of_bits bs))
+  end.
+
+(*** List operations *)
+(*
+Definition inline (^^) := append_list
+
+val subrange_list_inc : forall a. list a -> Z -> Z -> list a*)
+Definition subrange_list_inc {A} (xs : list A) i j :=
+  let toJ := firstn (Z.to_nat j + 1) xs in
+  let fromItoJ := skipn (Z.to_nat i) toJ in
+  fromItoJ.
+
+(*val subrange_list_dec : forall a. list a -> Z -> Z -> list a*)
+Definition subrange_list_dec {A} (xs : list A) i j :=
+  let top := (length_list xs) - 1 in
+  subrange_list_inc xs (top - i) (top - j).
+
+(*val subrange_list : forall a. bool -> list a -> Z -> Z -> list a*)
+Definition subrange_list {A} (is_inc : bool) (xs : list A) i j :=
+ if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j.
+
+Definition splitAt {A} n (l : list A) := (firstn n l, skipn n l).
+
+(*val update_subrange_list_inc : forall a. list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list_inc {A} (xs : list A) i j xs' :=
+  let (toJ,suffix) := splitAt (Z.to_nat j + 1) xs in
+  let (prefix,_fromItoJ) := splitAt (Z.to_nat i) toJ in
+  prefix ++ xs' ++ suffix.
+
+(*val update_subrange_list_dec : forall a. list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list_dec {A} (xs : list A) i j xs' :=
+  let top := (length_list xs) - 1 in
+  update_subrange_list_inc xs (top - i) (top - j) xs'.
+
+(*val update_subrange_list : forall a. bool -> list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list {A} (is_inc : bool) (xs : list A) i j xs' :=
+  if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'.
+
+Open Scope nat.
+Fixpoint nth_in_range {A} (n:nat) (l:list A) : n < length l -> A.
+refine 
+  (match n, l with
+  | O, h::_ => fun _ => h
+  | S m, _::t => fun H => nth_in_range A m t _
+  | _,_ => fun H => _
+  end).
+exfalso. inversion H.
+exfalso. inversion H.
+simpl in H. omega.
+Defined.
+
+Lemma nth_in_range_is_nth : forall A n (l : list A) d (H : n < length l),
+  nth_in_range n l H = nth n l d.
+intros until d. revert n.
+induction l; intros n H.
+* inversion H.
+* destruct n.
+  + reflexivity.
+  + apply IHl.
+Qed.
+
+Lemma nth_Z_nat {A} {n} {xs : list A} :
+  (0 <= n)%Z -> (n < length_list xs)%Z -> Z.to_nat n < length xs.
+unfold length_list.
+intros nonneg bounded.
+rewrite Z2Nat.inj_lt in bounded; auto using Zle_0_nat.
+rewrite Nat2Z.id in bounded.
+assumption.
+Qed.
+
+(*
+Lemma nth_top_aux {A} {n} {xs : list A} : Z.to_nat n < length xs -> let top := ((length_list xs) - 1)%Z in Z.to_nat (top - n)%Z < length xs.
+unfold length_list.
+generalize (length xs).
+intro n0.
+rewrite <- (Nat2Z.id n0).
+intro H.
+apply Z2Nat.inj_lt.
+* omega. 
+*)
+
+Close Scope nat.
+
+(*val access_list_inc : forall a. list a -> Z -> a*)
+Definition access_list_inc {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} := nth_in_range (Z.to_nat n) xs (nth_Z_nat (use_ArithFact _) (use_ArithFact _)).
+
+(*val access_list_dec : forall a. list a -> Z -> a*)
+Definition access_list_dec {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} : A.
+refine (
+  let top := (length_list xs) - 1 in
+  @access_list_inc A xs (top - n) _ _).
+constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega.
+constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega.
+Defined.
+
+(*val access_list : forall a. bool -> list a -> Z -> a*)
+Definition access_list {A} (is_inc : bool) (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} :=
+  if is_inc then access_list_inc xs n else access_list_dec xs n.
+
+Definition access_list_opt_inc {A} (xs : list A) n := nth_error xs (Z.to_nat n).
+
+(*val access_list_dec : forall a. list a -> Z -> a*)
+Definition access_list_opt_dec {A} (xs : list A) n :=
+  let top := (length_list xs) - 1 in
+  access_list_opt_inc xs (top - n).
+
+(*val access_list : forall a. bool -> list a -> Z -> a*)
+Definition access_list_opt {A} (is_inc : bool) (xs : list A) n :=
+  if is_inc then access_list_opt_inc xs n else access_list_opt_dec xs n.
+
+Definition list_update {A} (xs : list A) n x := firstn n xs ++ x :: skipn (S n) xs.
+
+(*val update_list_inc : forall a. list a -> Z -> a -> list a*)
+Definition update_list_inc {A} (xs : list A) n x := list_update xs (Z.to_nat n) x.
+
+(*val update_list_dec : forall a. list a -> Z -> a -> list a*)
+Definition update_list_dec {A} (xs : list A) n x :=
+  let top := (length_list xs) - 1 in
+  update_list_inc xs (top - n) x.
+
+(*val update_list : forall a. bool -> list a -> Z -> a -> list a*)
+Definition update_list {A} (is_inc : bool) (xs : list A) n x :=
+  if is_inc then update_list_inc xs n x else update_list_dec xs n x.
+
+(*Definition extract_only_element := function
+  | [] => failwith "extract_only_element called for empty list"
+  | [e] => e
+  | _ => failwith "extract_only_element called for list with more elements"
+end*)
+
+(*** Machine words *)
+
+Definition mword (n : Z) :=
+  match n with
+  | Zneg _ => False
+  | Z0 => word 0
+  | Zpos p => word (Pos.to_nat p)
+  end.
+
+Definition get_word {n} : mword n -> word (Z.to_nat n) :=
+  match n with
+  | Zneg _ => fun x => match x with end
+  | Z0 => fun x => x
+  | Zpos p => fun x => x
+  end.
+
+Definition with_word {n} {P : Type -> Type} : (word (Z.to_nat n) -> P (word (Z.to_nat n))) -> mword n -> P (mword n) :=
+match n with
+| Zneg _ => fun f w => match w with end
+| Z0 => fun f w => f w
+| Zpos _ => fun f w => f w
+end.
+
+Program Definition to_word {n} : n >= 0 -> word (Z.to_nat n) -> mword n :=
+  match n with
+  | Zneg _ => fun H _ => _
+  | Z0 => fun _ w => w
+  | Zpos _ => fun _ w => w
+  end.
+
+(*val length_mword : forall a. mword a -> Z*)
+Definition length_mword {n} (w : mword n) := n.
+
+(*val slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b*)
+(*Definition slice_mword_dec w i j := word_extract (Z.to_nat i) (Z.to_nat j) w.
+
+val slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b
+Definition slice_mword_inc w i j :=
+  let top := (length_mword w) - 1 in
+  slice_mword_dec w (top - i) (top - j)
+
+val slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b
+Definition slice_mword is_inc w i j := if is_inc then slice_mword_inc w i j else slice_mword_dec w i j
+
+val update_slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword_dec w i j w' := word_update w (Z.to_nat i) (Z.to_nat j) w'
+
+val update_slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword_inc w i j w' :=
+  let top := (length_mword w) - 1 in
+  update_slice_mword_dec w (top - i) (top - j) w'
+
+val update_slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword is_inc w i j w' :=
+  if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'
+
+val access_mword_dec : forall a. mword a -> Z -> bitU*)
+Parameter undefined_bit : bool.
+Definition getBit {n} :=
+match n with
+| O => fun (w : word O) i => undefined_bit
+| S n => fun (w : word (S n)) i => wlsb (wrshift w i)
+end.
+
+Definition access_mword_dec {m} (w : mword m) n := bitU_of_bool (getBit (get_word w) (Z.to_nat n)).
+
+(*val access_mword_inc : forall a. mword a -> Z -> bitU*)
+Definition access_mword_inc {m} (w : mword m) n :=
+  let top := (length_mword w) - 1 in
+  access_mword_dec w (top - n).
+
+(*Parameter access_mword : forall {a}, bool -> mword a -> Z -> bitU.*)
+Definition access_mword {a} (is_inc : bool) (w : mword a) n :=
+  if is_inc then access_mword_inc w n else access_mword_dec w n.
+
+Definition setBit {n} :=
+match n with
+| O => fun (w : word O) i b => w
+| S n => fun (w : word (S n)) i (b : bool) =>
+  let bit : word (S n) := wlshift (natToWord _ 1) i in
+  let mask : word (S n) := wnot bit in
+  let masked := wand mask w in
+  if b then masked else wor masked bit
+end.
+
+(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+Definition update_mword_bool_dec {a} (w : mword a) n b : mword a :=
+  with_word (P := id) (fun w => setBit w (Z.to_nat n) b) w.
+Definition update_mword_dec {a} (w : mword a) n b :=
+ match bool_of_bitU b with
+ | Some bl => Some (update_mword_bool_dec w n bl)
+ | None => None
+ end.
+
+(*val update_mword_inc : forall a. mword a -> Z -> bitU -> mword a*)
+Definition update_mword_inc {a} (w : mword a) n b :=
+  let top := (length_mword w) - 1 in
+  update_mword_dec w (top - n) b.
+
+(*Parameter update_mword : forall {a}, bool -> mword a -> Z -> bitU -> mword a.*)
+Definition update_mword {a} (is_inc : bool) (w : mword a) n b :=
+  if is_inc then update_mword_inc w n b else update_mword_dec w n b.
+
+(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
+Definition int_of_mword {a} `{ArithFact (a >= 0)} (sign : bool) (w : mword a) :=
+  if sign then wordToZ (get_word w) else Z.of_N (wordToN (get_word w)).
+
+
+(*val mword_of_int : forall a. Size a => Z -> Z -> mword a
+Definition mword_of_int len n :=
+  let w := wordFromInteger n in
+  if (length_mword w = len) then w else failwith "unexpected word length"
+*)
+Program Definition mword_of_int {len} `{H:ArithFact (len >= 0)} n : mword len :=
+match len with
+| Zneg _ => _
+| Z0 => ZToWord 0 n
+| Zpos p => ZToWord (Pos.to_nat p) n
+end.
+Next Obligation.
+destruct H.
+auto.
+Defined.
+(*
+(* Translating between a type level number (itself n) and an integer *)
+
+Definition size_itself_int x := Z.of_nat (size_itself x)
+
+(* NB: the corresponding sail type is forall n. atom(n) -> itself(n),
+   the actual integer is ignored. *)
+
+val make_the_value : forall n. Z -> itself n
+Definition inline make_the_value x := the_value
+*)
+
+Fixpoint bitlistFromWord {n} w :=
+match w with
+| WO => []
+| WS b w => b :: bitlistFromWord w
+end.
+
+Fixpoint wordFromBitlist l : word (length l) :=
+match l with
+| [] => WO
+| b::t => WS b (wordFromBitlist t)
+end.
+
+Local Open Scope nat.
+Program Definition fit_bbv_word {n m} (w : word n) : word m :=
+match Nat.compare m n with
+| Gt => extz w (m - n)
+| Eq => w
+| Lt => split2 (n - m) m w
+end.
+Next Obligation.
+symmetry in Heq_anonymous.
+apply nat_compare_gt in Heq_anonymous.
+omega.
+Defined.
+Next Obligation.
+
+symmetry in Heq_anonymous.
+apply nat_compare_eq in Heq_anonymous.
+omega.
+Defined.
+Next Obligation.
+
+symmetry in Heq_anonymous.
+apply nat_compare_lt in Heq_anonymous.
+omega.
+Defined.
+Local Close Scope nat.
+
+(*** Bitvectors *)
+
+Class Bitvector (a:Type) : Type := {
+  bits_of : a -> list bitU;
+  of_bits : list bitU -> option a;
+  of_bools : list bool -> a;
+  (* The first parameter specifies the desired length of the bitvector *)
+  of_int : Z -> Z -> a;
+  length : a -> Z;
+  unsigned : a -> option Z;
+  signed : a -> option Z;
+  arith_op_bv : (Z -> Z -> Z) -> bool -> a -> a -> a
+}.
+
+Instance bitlist_Bitvector {a : Type} `{BitU a} : (Bitvector (list a)) := {
+  bits_of v := List.map to_bitU v;
+  of_bits v := Some (List.map of_bitU v);
+  of_bools v := List.map of_bitU (List.map bitU_of_bool v);
+  of_int len n := List.map of_bitU (bits_of_int len n);
+  length := length_list;
+  unsigned v := unsigned_of_bits (List.map to_bitU v);
+  signed v := signed_of_bits (List.map to_bitU v);
+  arith_op_bv op sign l r := List.map of_bitU (arith_op_bits op sign (List.map to_bitU l) (List.map to_bitU r))
+}.
+
+Class ReasonableSize (a : Z) : Prop := {
+  isPositive : a >= 0
+}.
+
+Hint Resolve -> Z.gtb_lt Z.geb_le Z.ltb_lt Z.leb_le : zbool.
+Hint Resolve <- Z.ge_le_iff Z.gt_lt_iff : zbool.
+
+(* Omega doesn't know about In, but can handle disjunctions. *)
+Ltac unfold_In :=
+repeat match goal with
+| H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H
+| H:context [In ?x []] |- _ => change (In x []) with False in H
+end.
+
+(* Definitions in the context that involve proof for other constraints can
+   break some of the constraint solving tactics, so prune definition bodies
+   down to integer types. *)
+Ltac not_Z ty := match ty with Z => fail 1 | _ => idtac end.
+Ltac clear_non_Z_defns := 
+  repeat match goal with H := _ : ?X |- _ => not_Z X; clearbody H end.
+
+Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0).
+constructor.
+destruct a.
+auto with zarith.
+auto using Z.le_ge, Zle_0_pos.
+destruct w.
+Qed.
+Ltac unwrap_ArithFacts :=
+  repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H'] end.
+Ltac unbool_comparisons :=
+  repeat match goal with
+  | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H
+  | H:context [Z.gtb _ _] |- _ => rewrite Z.gtb_ltb in H
+  | H:context [Z.leb _ _ = true] |- _ => rewrite Z.leb_le in H
+  | H:context [Z.ltb _ _ = true] |- _ => rewrite Z.ltb_lt in H
+  | H:context [Z.eqb _ _ = true] |- _ => rewrite Z.eqb_eq in H
+  | H:context [Z.leb _ _ = false] |- _ => rewrite Z.leb_gt in H
+  | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H
+  | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H
+  | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H
+  | H:context [andb _ _ = true] |- _ => apply andb_prop in H
+  | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H
+  | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H
+  | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H
+  | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H
+  end.
+(* Split up dependent pairs to get at proofs of properties *)
+Ltac extract_properties :=
+  repeat match goal with H := (projT1 ?X) |- _ =>
+    let x := fresh "x" in
+    let Hx := fresh "Hx" in
+    destruct X as [x Hx] in *;
+    change (projT1 (existT _ x Hx)) with x in *; unfold H in * end;
+  repeat match goal with |- context [projT1 ?X] =>
+    let x := fresh "x" in
+    let Hx := fresh "Hx" in
+    destruct X as [x Hx] in *;
+    change (projT1 (existT _ x Hx)) with x in * end.
+(* TODO: hyps, too? *)
+Ltac reduce_list_lengths :=
+  repeat match goal with |- context [length_list ?X] => 
+    let r := (eval cbn in (length_list X)) in
+    change (length_list X) with r
+  end.
+(* TODO: can we restrict this to concrete terms? *)
+Ltac reduce_pow :=
+  repeat match goal with H:context [Z.pow ?X ?Y] |- _ => 
+    let r := (eval cbn in (Z.pow X Y)) in
+    change (Z.pow X Y) with r in H
+  end;
+  repeat match goal with |- context [Z.pow ?X ?Y] => 
+    let r := (eval cbn in (Z.pow X Y)) in
+    change (Z.pow X Y) with r
+  end.
+Ltac dump_context :=
+  repeat match goal with
+  | H:=?X |- _ => idtac H ":=" X; fail
+  | H:?X |- _ => idtac H ":" X; fail end;
+  match goal with |- ?X => idtac "Goal:" X end.
+Ltac solve_arithfact :=
+(*dump_context;*)
+ clear_non_Z_defns;
+ extract_properties;
+ repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end;
+ unwrap_ArithFacts;
+ unfold_In;
+ autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *)
+ unbool_comparisons;
+ reduce_list_lengths;
+ reduce_pow;
+(*dump_context;*)
+ solve [apply ArithFact_mword; assumption
+       | constructor; omega with Z
+         (* The datatypes hints give us some list handling, esp In *)
+       | constructor; auto with datatypes zbool zarith sail].
+Hint Extern 0 (ArithFact _) => solve_arithfact : typeclass_instances.
+
+Hint Unfold length_mword : sail.
+
+Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a.
+constructor.
+destruct a.
+auto with zarith.
+auto using Z.le_ge, Zle_0_pos.
+destruct w.
+Qed.
+
+Hint Extern 0 (ReasonableSize ?A) => (unwrap_ArithFacts; solve [apply ReasonableSize_witness; assumption | constructor; omega]) : typeclass_instances.
+
+Instance mword_Bitvector {a : Z} `{ArithFact (a >= 0)} : (Bitvector (mword a)) := {
+  bits_of v := List.map bitU_of_bool (bitlistFromWord (get_word v));
+  of_bits v := option_map (fun bl => to_word isPositive (fit_bbv_word (wordFromBitlist bl))) (just_list (List.map bool_of_bitU v));
+  of_bools v := to_word isPositive (fit_bbv_word (wordFromBitlist v));
+  of_int len z := mword_of_int z; (* cheat a little *)
+  length v := a;
+  unsigned v := Some (Z.of_N (wordToN (get_word v)));
+  signed v := Some (wordToZ (get_word v));
+  arith_op_bv op sign l r := mword_of_int (op (int_of_mword sign l) (int_of_mword sign r))
+}.
+
+Section Bitvector_defs.
+Context {a b} `{Bitvector a} `{Bitvector b}.
+
+Definition opt_def {a} (def:a) (v:option a) :=
+match v with
+| Some x => x
+| None => def
+end.
+
+(* The Lem version is partial, but lets go with BU here to avoid constraints for now *)
+Definition access_bv_inc (v : a) n := opt_def BU (access_list_opt_inc (bits_of v) n).
+Definition access_bv_dec (v : a) n := opt_def BU (access_list_opt_dec (bits_of v) n).
+
+Definition update_bv_inc (v : a) n b := update_list true  (bits_of v) n b.
+Definition update_bv_dec (v : a) n b := update_list false (bits_of v) n b.
+
+Definition subrange_bv_inc (v : a) i j := subrange_list true  (bits_of v) i j.
+Definition subrange_bv_dec (v : a) i j := subrange_list true  (bits_of v) i j.
+
+Definition update_subrange_bv_inc (v : a) i j (v' : b) := update_subrange_list true  (bits_of v) i j (bits_of v').
+Definition update_subrange_bv_dec (v : a) i j (v' : b) := update_subrange_list false (bits_of v) i j (bits_of v').
+
+(*val extz_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
+Definition extz_bv n (v : a) : option b := of_bits (extz_bits n (bits_of v)).
+
+(*val exts_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
+Definition exts_bv n (v : a) : option b := of_bits (exts_bits n (bits_of v)).
+
+(*val string_of_bv : forall a. Bitvector a => a -> string *)
+Definition string_of_bv v := show_bitlist (bits_of v).
+
+End Bitvector_defs.
+
+(*** Bytes and addresses *)
+
+Definition memory_byte := list bitU.
+
+(*val byte_chunks : forall a. list a -> option (list (list a))*)
+Fixpoint byte_chunks {a} (bs : list a) := match bs with
+  | [] => Some []
+  | a::b::c::d::e::f::g::h::rest =>
+     match byte_chunks rest with
+     | None => None
+     | Some rest => Some ([a;b;c;d;e;f;g;h] :: rest)
+     end
+  | _ => None
+end.
+(*declare {isabelle} termination_argument byte_chunks = automatic*)
+
+Section BytesBits.
+Context {a} `{Bitvector a}.
+
+(*val bytes_of_bits : forall a. Bitvector a => a -> option (list memory_byte)*)
+Definition bytes_of_bits (bs : a) := byte_chunks (bits_of bs).
+
+(*val bits_of_bytes : forall a. Bitvector a => list memory_byte -> a*)
+Definition bits_of_bytes (bs : list memory_byte) : list bitU := List.concat (List.map bits_of bs).
+
+Definition mem_bytes_of_bits (bs : a) := option_map (@rev (list bitU)) (bytes_of_bits bs).
+Definition bits_of_mem_bytes (bs : list memory_byte) := bits_of_bytes (List.rev bs).
+
+End BytesBits.
+
+(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+Definition bitv_of_byte_lifteds v :=
+  foldl (fun x (Byte_lifted y) => x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+Definition bitv_of_bytes v :=
+  foldl (fun x (Byte y) => x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+Definition byte_lifteds_of_bitv bits :=
+  let bits := List.map bit_lifted_of_bitU bits in
+  byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+Definition bytes_of_bitv bits :=
+  let bits := List.map bit_of_bitU bits in
+  bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+Definition bit_lifteds_of_bitUs bits := List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+Definition bit_lifteds_of_bitv v := bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+Definition address_lifted_of_bitv v :=
+  let byte_lifteds := byte_lifteds_of_bitv v in
+  let maybe_address_integer :=
+    match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+    | Some bs => Some (integer_of_byte_list bs)
+    | _ => None
+    end in
+  Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+Definition bitv_of_address_lifted (Address_lifted bs _) := bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+Definition address_of_bitv v :=
+  let bytes := bytes_of_bitv v in
+  address_of_byte_list bytes*)
+
+Fixpoint reverse_endianness_list (bits : list bitU) :=
+  match bits with
+  | _ :: _ :: _ :: _ :: _ :: _ :: _ :: _ :: t =>
+    reverse_endianness_list t ++ firstn 8 bits
+  | _ => bits
+  end.
+
+(*** Registers *)
+
+Definition register_field := string.
+Definition register_field_index : Type := string * (Z * Z). (* name, start and end *)
+
+Inductive register :=
+  | Register : string * (* name *)
+               Z * (* length *)
+               Z * (* start index *)
+               bool * (* is increasing *)
+               list register_field_index
+               -> register
+  | UndefinedRegister : Z -> register (* length *)
+  | RegisterPair : register * register -> register.
+
+Record register_ref regstate regval a :=
+   { name : string;
+     (*is_inc : bool;*)
+     read_from : regstate -> a;
+     write_to : a -> regstate -> regstate;
+     of_regval : regval -> option a;
+     regval_of : a -> regval }.
+Notation "{[ r 'with' 'name' := e ]}" := ({| name := e; read_from := read_from r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'read_from' := e ]}" := ({| read_from := e; name := name r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'write_to' := e ]}" := ({| write_to := e; name := name r; read_from := read_from r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'of_regval' := e ]}" := ({| of_regval := e; name := name r; read_from := read_from r; write_to := write_to r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'regval_of' := e ]}" := ({| regval_of := e; name := name r; read_from := read_from r; write_to := write_to r; of_regval := of_regval r |}).
+Arguments name [_ _ _].
+Arguments read_from [_ _ _].
+Arguments write_to [_ _ _].
+Arguments of_regval [_ _ _].
+Arguments regval_of [_ _ _].
+
+(* Register accessors: pair of functions for reading and writing register values *)
+Definition register_accessors regstate regval : Type :=
+  ((string -> regstate -> option regval) *
+   (string -> regval -> regstate -> option regstate)).
+
+Record field_ref regtype a :=
+   { field_name : string;
+     field_start : Z;
+     field_is_inc : bool;
+     get_field : regtype -> a;
+     set_field : regtype -> a -> regtype }.
+Arguments field_name [_ _].
+Arguments field_start [_ _].
+Arguments field_is_inc [_ _].
+Arguments get_field [_ _].
+Arguments set_field [_ _].
+
+(*
+(*let name_of_reg := function
+  | Register name _ _ _ _ => name
+  | UndefinedRegister _ => failwith "name_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "name_of_reg RegisterPair"
+end
+
+Definition size_of_reg := function
+  | Register _ size _ _ _ => size
+  | UndefinedRegister size => size
+  | RegisterPair _ _ => failwith "size_of_reg RegisterPair"
+end
+
+Definition start_of_reg := function
+  | Register _ _ start _ _ => start
+  | UndefinedRegister _ => failwith "start_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "start_of_reg RegisterPair"
+end
+
+Definition is_inc_of_reg := function
+  | Register _ _ _ is_inc _ => is_inc
+  | UndefinedRegister _ => failwith "is_inc_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "in_inc_of_reg RegisterPair"
+end
+
+Definition dir_of_reg := function
+  | Register _ _ _ is_inc _ => dir_of_bool is_inc
+  | UndefinedRegister _ => failwith "dir_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "dir_of_reg RegisterPair"
+end
+
+Definition size_of_reg_nat reg := Z.to_nat (size_of_reg reg)
+Definition start_of_reg_nat reg := Z.to_nat (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> option (Z * Z)
+Fixpoint register_field_indices_aux register rfield :=
+  match register with
+  | Register _ _ _ _ rfields => List.lookup rfield rfields
+  | RegisterPair r1 r2 =>
+      let m_indices := register_field_indices_aux r1 rfield in
+      if isSome m_indices then m_indices else register_field_indices_aux r2 rfield
+  | UndefinedRegister _ => None
+  end
+
+val register_field_indices : register -> register_field -> Z * Z
+Definition register_field_indices register rfield :=
+  match register_field_indices_aux register rfield with
+  | Some indices => indices
+  | None => failwith "Invalid register/register-field combination"
+  end
+
+Definition register_field_indices_nat reg regfield=
+  let (i,j) := register_field_indices reg regfield in
+  (Z.to_nat i,Z.to_nat j)*)
+
+(*let rec external_reg_value reg_name v :=
+  let (internal_start, external_start, direction) :=
+    match reg_name with
+     | Reg _ start size dir =>
+        (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+     | Reg_slice _ reg_start dir (slice_start, _) =>
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_field _ reg_start dir _ (slice_start, _) =>
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_f_slice _ reg_start dir _ _ (slice_start, _) =>
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     end in
+  let bits := bit_lifteds_of_bitv v in
+  <| rv_bits           := bits;
+     rv_dir            := direction;
+     rv_start          := external_start;
+     rv_start_internal := internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+Definition internal_reg_value v :=
+  List.map bitU_of_bit_lifted v.rv_bits
+         (*(Z.of_nat v.rv_start_internal)
+         (v.rv_dir = D_increasing)*)
+
+
+Definition external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) :=
+  match d with
+  (*This is the case the thread/concurrecny model expects, so no change needed*)
+  | D_increasing => (i,j)
+  | D_decreasing => let slice_i = start - i in
+                    let slice_j = (i - j) + slice_i in
+                    (slice_i,slice_j)
+  end *)
+
+(* TODO
+Definition external_reg_whole r :=
+  Reg (r.name) (Z.to_nat r.start) (Z.to_nat r.size) (dir_of_bool r.is_inc)
+
+Definition external_reg_slice r (i,j) :=
+  let start := Z.to_nat r.start in
+  let dir := dir_of_bool r.is_inc in
+  Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+Definition external_reg_field_whole reg rfield :=
+  let (m,n) := register_field_indices_nat reg rfield in
+  let start := start_of_reg_nat reg in
+  let dir := dir_of_reg reg in
+  Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+Definition external_reg_field_slice reg rfield (i,j) :=
+  let (m,n) := register_field_indices_nat reg rfield in
+  let start := start_of_reg_nat reg in
+  let dir := dir_of_reg reg in
+  Reg_f_slice (name_of_reg reg) start dir rfield
+              (external_slice dir start (m,n))
+              (external_slice dir start (i,j))*)
+
+(*val external_mem_value : list bitU -> memory_value
+Definition external_mem_value v :=
+  byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+Definition internal_mem_value bytes :=
+  List.reverse bytes $> bitv_of_byte_lifteds*)
+
+
+val foreach : forall a vars.
+  (list a) -> vars -> (a -> vars -> vars) -> vars*)
+Fixpoint foreach {a Vars} (l : list a) (vars : Vars) (body : a -> Vars -> Vars) : Vars :=
+match l with
+| [] => vars
+| (x :: xs) => foreach xs (body x vars) body
+end.
+
+(*declare {isabelle} termination_argument foreach = automatic
+
+val index_list : Z -> Z -> Z -> list Z*)
+Fixpoint index_list' from to step n :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    match n with
+    | O => []
+    | S n => from :: index_list' (from + step) to step n
+    end
+  else [].
+
+Definition index_list from to step :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    index_list' from to step (S (Z.abs_nat (from - to)))
+  else [].
+
+Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Vars) : Vars :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    match n with
+    | O => vars
+    | S n => let vars := body from vars in foreach_Z' (from + step) to step n vars body
+    end
+  else vars.
+
+Definition foreach_Z {Vars} from to step vars body :=
+  foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body.
+
+Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars :=
+  if sumbool_of_bool (from + off <=? to) then
+    match n with
+    | O => vars
+    | S n => let vars := body (from + off) _ vars in foreach_Z_up' from to step (off + step) n vars body
+    end
+  else vars.
+
+Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars :=
+  if sumbool_of_bool (to <=? from + off) then
+    match n with
+    | O => vars
+    | S n => let vars := body (from + off) _ vars in foreach_Z_down' from to step (off - step) n vars body
+    end
+  else vars.
+
+Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+    foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+    foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
+(*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
+Fixpoint while vars cond body :=
+  if cond vars then while (body vars) cond body else vars
+
+val until : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
+Fixpoint until vars cond body :=
+  let vars := body vars in
+  if cond vars then vars else until (body vars) cond body
+
+
+Definition assert' b msg_opt :=
+  let msg := match msg_opt with
+  | Some msg => msg
+  | None  => "unspecified error"
+  end in
+  if b then () else failwith msg
+
+(* convert numbers unsafely to naturals *)
+
+class (ToNatural a) val toNatural : a -> natural end
+(* eta-expanded for Isabelle output, otherwise it breaks *)
+instance (ToNatural Z) let toNatural := (fun n => naturalFromInteger n) end
+instance (ToNatural int)     let toNatural := (fun n => naturalFromInt n)     end
+instance (ToNatural nat)     let toNatural := (fun n => naturalFromNat n)     end
+instance (ToNatural natural) let toNatural := (fun n => n)                    end
+
+Definition toNaturalFiveTup (n1,n2,n3,n4,n5) :=
+  (toNatural n1,
+   toNatural n2,
+   toNatural n3,
+   toNatural n4,
+   toNatural n5)
+
+(* Let the following types be generated by Sail per spec, using either bitlists
+   or machine words as bitvector representation *)
+(*type regfp :=
+  | RFull of (string)
+  | RSlice of (string * Z * Z)
+  | RSliceBit of (string * Z)
+  | RField of (string * string)
+
+type niafp :=
+  | NIAFP_successor
+  | NIAFP_concrete_address of vector bitU
+  | NIAFP_indirect_address
+
+(* only for MIPS *)
+type diafp :=
+  | DIAFP_none
+  | DIAFP_concrete of vector bitU
+  | DIAFP_reg of regfp
+
+Definition regfp_to_reg (reg_info : string -> option string -> (nat * nat * direction * (nat * nat))) := function
+  | RFull name =>
+     let (start,length,direction,_) := reg_info name None in
+     Reg name start length direction
+  | RSlice (name,i,j) =>
+     let i = Z.to_nat i in
+     let j = Z.to_nat j in
+     let (start,length,direction,_) = reg_info name None in
+     let slice = external_slice direction start (i,j) in
+     Reg_slice name start direction slice
+  | RSliceBit (name,i) =>
+     let i = Z.to_nat i in
+     let (start,length,direction,_) = reg_info name None in
+     let slice = external_slice direction start (i,i) in
+     Reg_slice name start direction slice
+  | RField (name,field_name) =>
+     let (start,length,direction,span) = reg_info name (Some field_name) in
+     let slice = external_slice direction start span in
+     Reg_field name start direction field_name slice
+end
+
+Definition niafp_to_nia reginfo = function
+  | NIAFP_successor => NIA_successor
+  | NIAFP_concrete_address v => NIA_concrete_address (address_of_bitv v)
+  | NIAFP_indirect_address => NIA_indirect_address
+end
+
+Definition diafp_to_dia reginfo = function
+  | DIAFP_none => DIA_none
+  | DIAFP_concrete v => DIA_concrete_address (address_of_bitv v)
+  | DIAFP_reg r => DIA_register (regfp_to_reg reginfo r)
+end
+*)
+*)
+
+(* Arithmetic functions which return proofs that match the expected Sail
+   types in smt.sail. *)
+
+Definition div_with_eq n m : {o : Z & ArithFact (o = Z.quot n m)} := build_ex (Z.quot n m).
+Definition mod_with_eq n m : {o : Z & ArithFact (o = Z.rem n m)} := build_ex (Z.rem n m).
+Definition abs_with_eq n   : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n).
+
+(* Similarly, for ranges (currently in MIPS) *)
+
+Definition eq_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) : bool :=
+  (projT1 l) =? (projT1 r).
+Definition add_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
+  : {x & ArithFact (n+o <= x <= m+p)} :=
+  build_ex ((projT1 l) + (projT1 r)).
+Definition sub_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
+  : {x & ArithFact (n-p <= x <= m-o)} :=
+  build_ex ((projT1 l) - (projT1 r)).
+Definition negate_range {n m} (l : {l : Z & ArithFact (n <= l <= m)})
+  : {x : Z & ArithFact ((- m) <= x <= (- n))} :=
+  build_ex (- (projT1 l)).
+
+Definition min_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c <= a /\ c <= b)} :=
+  build_ex (Z.min a b).
+Definition max_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c >= a /\ c >= b)} :=
+  build_ex (Z.max a b).
+
+
+(*** Generic vectors *)
+
+Definition vec (T:Type) (n:Z) := { l : list T & length_list l = n }.
+Definition vec_length {T n} (v : vec T n) := n.
+Definition vec_access_dec {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+  access_list_dec (projT1 v) m.
+Definition vec_access_inc {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+  access_list_inc (projT1 v) m.
+
+Program Definition vec_init {T} (t : T) (n : Z) `{ArithFact (n >= 0)} : vec T n :=
+  existT _ (repeat [t] n) _.
+Next Obligation.
+rewrite repeat_length; auto using fact.
+unfold length_list.
+simpl.
+auto with zarith.
+Qed.
+
+Lemma skipn_length {A n} {l: list A} : (n <= List.length l -> List.length (skipn n l) = List.length l - n)%nat.
+revert l.
+induction n.
+* simpl. auto with arith.
+* intros l H.
+  destruct l.
+  + inversion H.
+  + simpl in H.
+    simpl.
+    rewrite IHn; auto with arith.
+Qed.
+Lemma update_list_inc_length {T} {l:list T} {m x} : 0 <= m < length_list l -> length_list (update_list_inc l m x) = length_list l.
+unfold update_list_inc, list_update, length_list.
+intro H.
+f_equal.
+assert ((0 <= Z.to_nat m < Datatypes.length l)%nat).
+{ destruct H as [H1 H2].
+  split.
+  + change 0%nat with (Z.to_nat 0).
+    apply Z2Nat.inj_le; auto with zarith.
+  + rewrite <- Nat2Z.id.
+    apply Z2Nat.inj_lt; auto with zarith.
+}
+rewrite app_length.
+rewrite firstn_length_le; only 2:omega.
+cbn -[skipn].
+rewrite skipn_length;
+omega.
+Qed.
+
+Program Definition vec_update_dec {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_dec (projT1 v) m t) _.
+Next Obligation.
+unfold update_list_dec.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+  destruct v. simpl (projT1 _). rewrite e.
+  omega.
+Qed.
+
+Program Definition vec_update_inc {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_inc (projT1 v) m t) _.
+Next Obligation.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+  destruct v. simpl (projT1 _). rewrite e.
+  omega.
+Qed.
+
+Program Definition vec_map {S T} (f : S -> T) {n} (v : vec S n) : vec T n := existT _ (List.map f (projT1 v)) _.
+Next Obligation.
+destruct v as [l H].
+cbn.
+unfold length_list.
+rewrite map_length.
+apply H.
+Qed.
+
+Program Definition just_vec {A n} (v : vec (option A) n) : option (vec A n) :=
+  match just_list (projT1 v) with
+  | None => None
+  | Some v' => Some (existT _ v' _)
+  end.
+Next Obligation.
+rewrite <- (just_list_length_Z _ _ Heq_anonymous).
+destruct v.
+assumption.
+Qed.
+
+Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v.
+
+Program Definition vec_of_list {A} n (l : list A) : option (vec A n) :=
+  if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None.
+Next Obligation.
+symmetry.
+apply Z.eqb_eq.
+assumption.
+Qed.
+
+Definition vec_of_list_len {A} (l : list A) : vec A (length_list l) := existT _ l (eq_refl _).
+
+Definition map_bind {A B} (f : A -> option B) (a : option A) : option B :=
+match a with
+| Some a' => f a'
+| None => None
+end.
\ No newline at end of file
diff --git a/snapshots/coq/lib/coq/_CoqProject b/snapshots/coq/lib/coq/_CoqProject
new file mode 100644
index 00000000..9f5d26b8
--- /dev/null
+++ b/snapshots/coq/lib/coq/_CoqProject
@@ -0,0 +1,2 @@
+-R . Sail
+-R ../../../bbv/theories bbv
diff --git a/snapshots/coq/mips/_CoqProject b/snapshots/coq/mips/_CoqProject
new file mode 100644
index 00000000..ad38d28d
--- /dev/null
+++ b/snapshots/coq/mips/_CoqProject
@@ -0,0 +1,2 @@
+-R ../../bbv/theories bbv
+-R ../lib/coq Sail
\ No newline at end of file
diff --git a/snapshots/coq/mips/mips.v b/snapshots/coq/mips/mips.v
new file mode 100644
index 00000000..8d43a6e2
--- /dev/null
+++ b/snapshots/coq/mips/mips.v
@@ -0,0 +1,5890 @@
+(*Generated by Sail from mips.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Require Import mips_types.
+Require Import mips_extras.
+Import ListNotations.
+Open Scope string.
+Section Content.
+
+Definition neq_atom (x : Z) (y : Z) `{ArithFact (x = x)} `{ArithFact (y = y)}
+: bool :=
+   negb (Z.eqb x y).
+
+Definition neq_range {n : Z} {m : Z} {o : Z} {p : Z} '((existT _ x _) : {rangevar : Z & ArithFact (n <=
+  rangevar /\
+  rangevar <= m)}) '((existT _ y _) : {rangevar : Z & ArithFact (o <= rangevar /\ rangevar <= p)}) 
+: bool :=
+   negb (eq_range (build_ex x) (build_ex y)).
+
+Definition neq_int (x : Z) (y : Z)  : bool := negb (Z.eqb x y).
+
+Definition neq_bool (x : bool) (y : bool)  : bool := negb (Bool.eqb x y).
+
+Definition undefined_option {a : Type} (typ_a : a) 
+: M (option a) :=
+   undefined_unit tt >>= fun u_0 =>
+   let u_1 : a := typ_a in
+   (internal_pick [Some u_1;None])
+    : M (option a).
+
+Definition is_none {a : Type} (opt : option a) 
+: bool :=
+   match opt with | Some (_) => false | None => true end.
+
+Definition is_some {a : Type} (opt : option a) 
+: bool :=
+   match opt with | Some (_) => true | None => false end.
+
+Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} `{ArithFact (len =
+  len)}
+: mword len :=
+   if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len
+   else zero_extend v len.
+
+Definition neq_vec {n : Z} (x : mword n) (y : mword n)  : bool := negb (eq_vec x y).
+
+
+
+Definition cast_unit_vec (b : bitU) 
+: mword 1 :=
+   match b with | B0 => (vec_of_bits [B0]  : mword 1) | _ => (vec_of_bits [B1]  : mword 1) end.
+
+Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width =
+  width)}
+: M (unit) :=
+   (write_ram 64 width
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0]
+        : mword 64) addr data)
+    : M (unit).
+
+Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} `{ArithFact (width =
+  width)}
+: M (mword (8 * width)) :=
+   (autocast_m (read_ram 64 width
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0]
+                    : mword 64) addr))
+    : M (mword (8 * width)).
+
+Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} `{ArithFact (n = n)}
+: mword (n0 * n) :=
+   replicate_bits bs n.
+
+Definition undefined_exception '(tt : unit) 
+: M (exception) :=
+   undefined_string tt >>= fun u_0 =>
+   undefined_unit tt >>= fun u_1 =>
+   (internal_pick
+      [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1])
+    : M (exception).
+
+Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} 
+: mword m__tv :=
+   sign_extend v m__tv.
+
+Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} 
+: mword m__tv :=
+   zero_extend v m__tv.
+
+Definition zeros (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} 
+: mword n__tv :=
+   autocast (replicate_bits (vec_of_bits [B0]  : mword 1) n__tv).
+Arguments zeros _ _ {_}.
+
+Definition ones (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} 
+: mword n__tv :=
+   autocast (replicate_bits (vec_of_bits [B1]  : mword 1) n__tv).
+Arguments ones _ _ {_}.
+
+Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} 
+: bool :=
+   Z.ltb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} 
+: bool :=
+   Z.geb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} 
+: bool :=
+   Z.ltb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} 
+: bool :=
+   Z.geb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition bool_to_bits (x : bool) 
+: mword 1 :=
+   if (x) then (vec_of_bits [B1]  : mword 1)
+   else (vec_of_bits [B0]  : mword 1).
+
+Definition bit_to_bool (b : bitU)  : bool := match b with | B1 => true | _ => false end.
+
+Definition bits_to_bool (x : mword 1)  : bool := bit_to_bool (access_vec_dec x 0).
+
+Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} `{ArithFact (l = l)}
+: mword l :=
+   get_slice_int l n 0.
+
+Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= 1)} 
+: mword n__tv :=
+   autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0).
+
+Definition undefined_CauseReg '(tt : unit) 
+: M (CauseReg) :=
+   undefined_bitvector 32 >>= fun w__0 =>
+   returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |})
+    : CauseReg).
+
+Definition Mk_CauseReg (v : mword 32) 
+: CauseReg :=
+   {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_CauseReg_bits (v : CauseReg) 
+: mword 32 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0.
+
+Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_CauseReg_BD (v : CauseReg) 
+: mword 1 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31.
+
+Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_CauseReg_CE (v : CauseReg) 
+: mword 2 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28.
+
+Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec v 1 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_CauseReg_IV (v : CauseReg) 
+: mword 1 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23.
+
+Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_CauseReg_WP (v : CauseReg) 
+: mword 1 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22.
+
+Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_CauseReg_IP (v : CauseReg) 
+: mword 8 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8.
+
+Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_CauseReg_ExcCode (v : CauseReg) 
+: mword 5 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2.
+
+Definition _set_CauseReg_ExcCode (r_ref : register_ref regstate register_value CauseReg) (v : mword 5) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec v 4 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}.
+
+Definition undefined_TLBEntryLoReg '(tt : unit) 
+: M (TLBEntryLoReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |})
+    : TLBEntryLoReg).
+
+Definition Mk_TLBEntryLoReg (v : mword 64) 
+: TLBEntryLoReg :=
+   {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) 
+: mword 64 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0.
+
+Definition _set_TLBEntryLoReg_bits (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0
+            (subrange_vec_dec v 63 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0
+          (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63.
+
+Definition _set_TLBEntryLoReg_CapS (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63
+          (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62.
+
+Definition _set_TLBEntryLoReg_CapL (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62
+          (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) 
+: mword 24 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6.
+
+Definition _set_TLBEntryLoReg_PFN (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6
+            (subrange_vec_dec v 23 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6
+          (subrange_vec_dec x 23 0)) ]}.
+
+Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) 
+: mword 3 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3.
+
+Definition _set_TLBEntryLoReg_C (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3
+            (subrange_vec_dec v 2 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}.
+
+Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2.
+
+Definition _set_TLBEntryLoReg_D (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1.
+
+Definition _set_TLBEntryLoReg_V (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0.
+
+Definition _set_TLBEntryLoReg_G (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition undefined_TLBEntryHiReg '(tt : unit) 
+: M (TLBEntryHiReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |})
+    : TLBEntryHiReg).
+
+Definition Mk_TLBEntryHiReg (v : mword 64) 
+: TLBEntryHiReg :=
+   {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) 
+: mword 64 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0.
+
+Definition _set_TLBEntryHiReg_bits (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0
+            (subrange_vec_dec v 63 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0
+          (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) 
+: mword 2 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62.
+
+Definition _set_TLBEntryHiReg_R (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62
+            (subrange_vec_dec v 1 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62
+          (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) 
+: mword 27 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13.
+
+Definition _set_TLBEntryHiReg_VPN2 (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13
+            (subrange_vec_dec v 26 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13
+          (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) 
+: mword 8 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0.
+
+Definition _set_TLBEntryHiReg_ASID (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0
+            (subrange_vec_dec v 7 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition undefined_ContextReg '(tt : unit) 
+: M (ContextReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |})
+    : ContextReg).
+
+Definition Mk_ContextReg (v : mword 64) 
+: ContextReg :=
+   {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_ContextReg_bits (v : ContextReg) 
+: mword 64 :=
+   subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0.
+
+Definition _set_ContextReg_bits (r_ref : register_ref regstate register_value ContextReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       ContextReg_ContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+      : ContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) 
+: ContextReg :=
+   {[ v with
+     ContextReg_ContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_ContextReg_PTEBase (v : ContextReg) 
+: mword 41 :=
+   subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23.
+
+Definition _set_ContextReg_PTEBase (r_ref : register_ref regstate register_value ContextReg) (v : mword 41) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       ContextReg_ContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec v 40 0)) ]}
+      : ContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) 
+: ContextReg :=
+   {[ v with
+     ContextReg_ContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}.
+
+Definition _get_ContextReg_BadVPN2 (v : ContextReg) 
+: mword 19 :=
+   subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4.
+
+Definition _set_ContextReg_BadVPN2 (r_ref : register_ref regstate register_value ContextReg) (v : mword 19) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       ContextReg_ContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec v 18 0)) ]}
+      : ContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) 
+: ContextReg :=
+   {[ v with
+     ContextReg_ContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}.
+
+Definition undefined_XContextReg '(tt : unit) 
+: M (XContextReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |})
+    : XContextReg).
+
+Definition Mk_XContextReg (v : mword 64) 
+: XContextReg :=
+   {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_XContextReg_bits (v : XContextReg) 
+: mword 64 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0.
+
+Definition _set_XContextReg_bits (r_ref : register_ref regstate register_value XContextReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_XContextReg_XPTEBase (v : XContextReg) 
+: mword 31 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33.
+
+Definition _set_XContextReg_XPTEBase (r_ref : register_ref regstate register_value XContextReg) (v : mword 31) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 33
+            (subrange_vec_dec v 30 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}.
+
+Definition _get_XContextReg_XR (v : XContextReg) 
+: mword 2 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31.
+
+Definition _set_XContextReg_XR (r_ref : register_ref regstate register_value XContextReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec v 1 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_XContextReg_XBadVPN2 (v : XContextReg) 
+: mword 27 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4.
+
+Definition _set_XContextReg_XBadVPN2 (r_ref : register_ref regstate register_value XContextReg) (v : mword 27) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec v 26 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}.
+
+Definition TLBNumEntries := 64.
+
+Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1]  : mword 6).
+
+Definition MAX (n : Z) `{ArithFact (n = n)} : Z := Z.sub (pow2 n) 1.
+
+Definition MAX_U64 := MAX 64.
+
+Definition MAX_VA := MAX 40.
+
+Definition MAX_PA := MAX 36.
+
+Definition undefined_TLBEntry '(tt : unit) 
+: M (TLBEntry) :=
+   undefined_bitvector 53 >>= fun w__0 =>
+   undefined_bitvector 64 >>= fun w__1 =>
+   returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; 
+                TLBEntry_TLBEntry_chunk_0 := w__1 |})
+    : TLBEntry).
+
+Definition Mk_TLBEntry (v : mword 117) 
+: TLBEntry :=
+   {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); 
+      TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_TLBEntry_bits (v : TLBEntry) 
+: mword 117 :=
+   concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0)
+     (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0).
+
+Definition _set_TLBEntry_bits (r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec v 116 64)) ]}
+      : TLBEntry in
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) 
+: TLBEntry :=
+   let v :=
+     {[ v with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec x 116 64)) ]} in
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_TLBEntry_pagemask (v : TLBEntry) 
+: mword 16 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37.
+
+Definition _set_TLBEntry_pagemask (r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec v 15 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}.
+
+Definition _get_TLBEntry_r (v : TLBEntry) 
+: mword 2 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35.
+
+Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec v 1 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_TLBEntry_vpn2 (v : TLBEntry) 
+: mword 27 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8.
+
+Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec v 26 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_TLBEntry_asid (v : TLBEntry) 
+: mword 8 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0.
+
+Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec v 7 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_TLBEntry_g (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63.
+
+Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_valid (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62.
+
+Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_caps1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61.
+
+Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_capl1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60.
+
+Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_pfn1 (v : TLBEntry) 
+: mword 24 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36.
+
+Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec v 23 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}.
+
+Definition _get_TLBEntry_c1 (v : TLBEntry) 
+: mword 3 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33.
+
+Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec v 2 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}.
+
+Definition _get_TLBEntry_d1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32.
+
+Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_v1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31.
+
+Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_caps0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30.
+
+Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_capl0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29.
+
+Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_pfn0 (v : TLBEntry) 
+: mword 24 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5.
+
+Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec v 23 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}.
+
+Definition _get_TLBEntry_c0 (v : TLBEntry) 
+: mword 3 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2.
+
+Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec v 2 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}.
+
+Definition _get_TLBEntry_d0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1.
+
+Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_v0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0.
+
+Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition TLBEntries : vec (register_ref regstate register_value TLBEntry) 64 :=
+vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref;
+                 TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref;
+                 TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref;
+                 TLBEntry00_ref].
+
+Definition undefined_StatusReg '(tt : unit) 
+: M (StatusReg) :=
+   undefined_bitvector 32 >>= fun w__0 =>
+   returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |})
+    : StatusReg).
+
+Definition Mk_StatusReg (v : mword 32) 
+: StatusReg :=
+   {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_StatusReg_bits (v : StatusReg) 
+: mword 32 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0.
+
+Definition _set_StatusReg_bits (r_ref : register_ref regstate register_value StatusReg) (v : mword 32) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_StatusReg_CU (v : StatusReg) 
+: mword 4 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28.
+
+Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec v 3 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}.
+
+Definition _get_StatusReg_BEV (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22.
+
+Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_IM (v : StatusReg) 
+: mword 8 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8.
+
+Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_StatusReg_KX (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7.
+
+Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_SX (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6.
+
+Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_UX (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5.
+
+Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_KSU (v : StatusReg) 
+: mword 2 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3.
+
+Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_StatusReg_ERL (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2.
+
+Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_EXL (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1.
+
+Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_IE (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0.
+
+Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition execute_branch (pc : mword 64) 
+: M (unit) :=
+   write_reg delayedPC_ref pc >>
+   write_reg branchPending_ref (vec_of_bits [B1]  : mword 1)
+    : M (unit).
+
+Definition NotWordVal (word : mword 64) 
+: bool :=
+   neq_vec (zopz0zQzQ ((cast_unit_vec (access_vec_dec word 31))  : mword 1) 32)
+     (subrange_vec_dec word 63 32).
+
+Definition rGPR (idx : mword 5) 
+: M (mword 64) :=
+   let '(existT _ i _) := uint idx in
+   (if sumbool_of_bool ((Z.eqb i 0)) then
+      returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0]
+                 : mword 64)
+       : mword 64)
+    else read_reg GPR_ref >>= fun w__0 => returnm ((vec_access_dec w__0 i)  : mword 64))
+    : M (mword 64).
+
+Definition wGPR (idx : mword 5) (v : mword 64) 
+: M (unit) :=
+   let '(existT _ i _) := uint idx in
+   (if ((neq_atom i 0)) then
+      read_reg GPR_ref >>= fun w__0 => write_reg GPR_ref (vec_update_dec w__0 i v)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size = size)}
+: M (mword (8 * size)) :=
+   (autocast_m (__MIPS_read addr size))
+    : M (mword (8 * size)).
+
+Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size =
+  size)}
+: M (mword (8 * size)) :=
+   (autocast_m (__MIPS_read addr size))
+    : M (mword (8 * size)).
+
+Definition MEM_sync '(tt : unit)  : M (unit) := (skip tt)  : M (unit).
+
+Definition MEMea (addr : mword 64) (size : Z) `{ArithFact (size = size)}
+: M (unit) :=
+   (skip tt)
+    : M (unit).
+
+Definition MEMea_conditional (addr : mword 64) (size : Z) `{ArithFact (size = size)}
+: M (unit) :=
+   (skip tt)
+    : M (unit).
+
+Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size = size)}
+: M (unit) :=
+   (__MIPS_write addr size data)
+    : M (unit).
+
+Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size =
+  size)}
+: M (bool) :=
+   __MIPS_write addr size data >> returnm (true  : bool).
+
+Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} `{ArithFact (arg_ =
+  arg_)}
+: Exception :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then TLBL
+   else if sumbool_of_bool ((Z.eqb p0_ 3)) then TLBS
+   else if sumbool_of_bool ((Z.eqb p0_ 4)) then AdEL
+   else if sumbool_of_bool ((Z.eqb p0_ 5)) then AdES
+   else if sumbool_of_bool ((Z.eqb p0_ 6)) then Sys
+   else if sumbool_of_bool ((Z.eqb p0_ 7)) then Bp
+   else if sumbool_of_bool ((Z.eqb p0_ 8)) then ResI
+   else if sumbool_of_bool ((Z.eqb p0_ 9)) then CpU
+   else if sumbool_of_bool ((Z.eqb p0_ 10)) then Ov
+   else if sumbool_of_bool ((Z.eqb p0_ 11)) then Tr
+   else if sumbool_of_bool ((Z.eqb p0_ 12)) then C2E
+   else if sumbool_of_bool ((Z.eqb p0_ 13)) then C2Trap
+   else if sumbool_of_bool ((Z.eqb p0_ 14)) then XTLBRefillL
+   else if sumbool_of_bool ((Z.eqb p0_ 15)) then XTLBRefillS
+   else if sumbool_of_bool ((Z.eqb p0_ 16)) then XTLBInvL
+   else if sumbool_of_bool ((Z.eqb p0_ 17)) then XTLBInvS
+   else MCheck.
+
+Definition num_of_Exception (arg_ : Exception) 
+: {e : Z & ArithFact (0 <= e /\ e <= 18)} :=
+   match arg_ with
+   | Interrupt => build_ex 0
+   | TLBMod => build_ex 1
+   | TLBL => build_ex 2
+   | TLBS => build_ex 3
+   | AdEL => build_ex 4
+   | AdES => build_ex 5
+   | Sys => build_ex 6
+   | Bp => build_ex 7
+   | ResI => build_ex 8
+   | CpU => build_ex 9
+   | Ov => build_ex 10
+   | Tr => build_ex 11
+   | C2E => build_ex 12
+   | C2Trap => build_ex 13
+   | XTLBRefillL => build_ex 14
+   | XTLBRefillS => build_ex 15
+   | XTLBInvL => build_ex 16
+   | XTLBInvS => build_ex 17
+   | MCheck => build_ex 18
+   end.
+
+Definition undefined_Exception '(tt : unit) 
+: M (Exception) :=
+   (internal_pick
+      [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck])
+    : M (Exception).
+
+Definition ExceptionCode (ex : Exception) 
+: mword 5 :=
+   let x : bits 8 :=
+     match ex with
+     | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)
+     | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  : mword 8)
+     | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  : mword 8)
+     | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  : mword 8)
+     | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0]  : mword 8)
+     | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1]  : mword 8)
+     | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0]  : mword 8)
+     | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1]  : mword 8)
+     | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0]  : mword 8)
+     | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1]  : mword 8)
+     | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0]  : mword 8)
+     | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1]  : mword 8)
+     | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  : mword 8)
+     | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  : mword 8)
+     | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  : mword 8)
+     | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  : mword 8)
+     | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  : mword 8)
+     | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  : mword 8)
+     | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0]  : mword 8)
+     end in
+   subrange_vec_dec x 4 0.
+
+Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) 
+: M (o) :=
+   read_reg CP0Status_ref >>= fun w__0 =>
+   (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0))  : bool))) then
+      (read_reg inBranchDelay_ref  : M (mword 1)) >>= fun w__1 =>
+      (if (((bit_to_bool (access_vec_dec w__1 0))  : bool)) then
+         (read_reg PC_ref  : M (mword 64)) >>= fun w__2 =>
+         write_reg CP0EPC_ref (sub_vec_int w__2 4) >>
+         (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1]  : mword 1))
+          : M (unit)
+       else
+         (read_reg PC_ref  : M (mword 64)) >>= fun w__3 =>
+         write_reg CP0EPC_ref w__3 >>
+         (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0]  : mword 1))
+          : M (unit))
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   read_reg CP0Status_ref >>= fun w__4 =>
+   let vectorOffset :=
+     if (((bits_to_bool (_get_StatusReg_EXL w__4))  : bool)) then
+       (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12)
+     else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then
+       (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12)
+     else if ((generic_eq ex C2Trap)) then
+       (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12)
+     else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12) in
+   read_reg CP0Status_ref >>= fun w__5 =>
+   let vectorBase : bits 64 :=
+     if (((bits_to_bool (_get_StatusReg_BEV w__5))  : bool)) then
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0]
+         : mword 64)
+     else
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0]
+         : mword 64) in
+   write_reg nextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >>
+   _set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex) >>
+   _set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1]  : mword 1) >>
+   (throw (ISAException tt))
+    : M (o).
+
+Definition SignalException {o : Type} (ex : Exception) 
+: M (o) :=
+   (SignalExceptionMIPS ex
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0]
+        : mword 64))
+    : M (o).
+
+Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) 
+: M (o) :=
+   write_reg CP0BadVAddr_ref badAddr >> (SignalException ex)  : M (o).
+
+Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) 
+: M (o) :=
+   write_reg CP0BadVAddr_ref badAddr >>
+   _set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13) >>
+   _set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13) >>
+   _set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62) >>
+   _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62) >>
+   _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13) >>
+   (SignalException ex)
+    : M (o).
+
+Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ =
+  arg_)}
+: MemAccessType :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData
+   else StoreData.
+
+Definition num_of_MemAccessType (arg_ : MemAccessType) 
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+   match arg_ with
+   | Instruction => build_ex 0
+   | LoadData => build_ex 1
+   | StoreData => build_ex 2
+   end.
+
+Definition undefined_MemAccessType '(tt : unit) 
+: M (MemAccessType) :=
+   (internal_pick [Instruction;LoadData;StoreData])
+    : M (MemAccessType).
+
+Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ =
+  arg_)}
+: AccessLevel :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then User
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor
+   else Kernel.
+
+Definition num_of_AccessLevel (arg_ : AccessLevel) 
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+   match arg_ with | User => build_ex 0 | Supervisor => build_ex 1 | Kernel => build_ex 2 end.
+
+Definition undefined_AccessLevel '(tt : unit) 
+: M (AccessLevel) :=
+   (internal_pick [User;Supervisor;Kernel])
+    : M (AccessLevel).
+
+Definition int_of_AccessLevel (level : AccessLevel) 
+: Z :=
+   match level with | User => 0 | Supervisor => 1 | Kernel => 2 end.
+
+Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) 
+: bool :=
+   Z.geb (int_of_AccessLevel currentLevel) (int_of_AccessLevel requiredLevel).
+
+Definition getAccessLevel '(tt : unit) 
+: M (AccessLevel) :=
+   or_boolM
+     (read_reg CP0Status_ref >>= fun w__0 =>
+      returnm ((bits_to_bool (_get_StatusReg_EXL w__0))
+       : bool))
+     (read_reg CP0Status_ref >>= fun w__1 =>
+      returnm ((bits_to_bool (_get_StatusReg_ERL w__1))
+       : bool)) >>= fun w__2 =>
+   (if (w__2) then returnm (Kernel  : AccessLevel)
+    else
+      read_reg CP0Status_ref >>= fun w__3 =>
+      let p__27 := _get_StatusReg_KSU w__3 in
+      let b__0 := p__27 in
+      returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0]  : mword 2))) then Kernel
+                else if ((eq_vec b__0 (vec_of_bits [B0;B1]  : mword 2))) then Supervisor
+                else if ((eq_vec b__0 (vec_of_bits [B1;B0]  : mword 2))) then User
+                else User)
+       : AccessLevel))
+    : M (AccessLevel).
+
+Definition checkCP0Access '(tt : unit) 
+: M (unit) :=
+   getAccessLevel tt >>= fun accessLevel =>
+   and_boolM (returnm ((generic_neq accessLevel Kernel)  : bool))
+     (read_reg CP0Status_ref >>= fun w__0 =>
+      returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0))  : bool))
+       : bool)) >>= fun w__1 =>
+   (if (w__1) then
+      _set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0]  : mword 2) >>
+      (SignalException CpU)
+       : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition incrementCP0Count '(tt : unit) 
+: M (unit) :=
+   (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__0 =>
+   (read_reg TLBWired_ref  : M (mword 6)) >>= fun w__1 =>
+   (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax  : TLBIndexT)
+    else
+      (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__2 =>
+      returnm ((sub_vec_int w__2 1)
+       : TLBIndexT)) >>= fun w__3 =>
+   write_reg TLBRandom_ref w__3 >>
+   (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__4 =>
+   write_reg CP0Count_ref (add_vec_int w__4 1) >>
+   (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__5 =>
+   (read_reg CP0Compare_ref  : M (mword 32)) >>= fun w__6 =>
+   (if ((eq_vec w__5 w__6)) then
+      read_reg CP0Cause_ref >>= fun w__7 =>
+      (_set_CauseReg_IP CP0Cause_ref
+         (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   read_reg CP0Status_ref >>= fun w__8 =>
+   let ims := _get_StatusReg_IM w__8 in
+   read_reg CP0Cause_ref >>= fun w__9 =>
+   let ips := _get_CauseReg_IP w__9 in
+   read_reg CP0Status_ref >>= fun w__10 =>
+   let ie := _get_StatusReg_IE w__10 in
+   read_reg CP0Status_ref >>= fun w__11 =>
+   let exl := _get_StatusReg_EXL w__11 in
+   read_reg CP0Status_ref >>= fun w__12 =>
+   let erl := _get_StatusReg_ERL w__12 in
+   (if ((andb (negb ((bits_to_bool exl)  : bool))
+           (andb (negb ((bits_to_bool erl)  : bool))
+              (andb ((bits_to_bool ie)  : bool)
+                 (neq_vec (and_vec ips ims) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8))))))
+    then
+      (SignalException Interrupt)
+       : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ =
+  arg_)}
+: decode_failure :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then illegal_instruction
+   else internal_error.
+
+Definition num_of_decode_failure (arg_ : decode_failure) 
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+   match arg_ with
+   | no_matching_pattern => build_ex 0
+   | unsupported_instruction => build_ex 1
+   | illegal_instruction => build_ex 2
+   | internal_error => build_ex 3
+   end.
+
+Definition undefined_decode_failure '(tt : unit) 
+: M (decode_failure) :=
+   (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error])
+    : M (decode_failure).
+
+Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} `{ArithFact (arg_ =
+  arg_)}
+: Comparison :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ'
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then GE
+   else if sumbool_of_bool ((Z.eqb p0_ 3)) then GEU
+   else if sumbool_of_bool ((Z.eqb p0_ 4)) then GT'
+   else if sumbool_of_bool ((Z.eqb p0_ 5)) then LE
+   else if sumbool_of_bool ((Z.eqb p0_ 6)) then LT'
+   else LTU.
+
+Definition num_of_Comparison (arg_ : Comparison) 
+: {e : Z & ArithFact (0 <= e /\ e <= 7)} :=
+   match arg_ with
+   | EQ' => build_ex 0
+   | NE => build_ex 1
+   | GE => build_ex 2
+   | GEU => build_ex 3
+   | GT' => build_ex 4
+   | LE => build_ex 5
+   | LT' => build_ex 6
+   | LTU => build_ex 7
+   end.
+
+Definition undefined_Comparison '(tt : unit) 
+: M (Comparison) :=
+   (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU])
+    : M (Comparison).
+
+Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) 
+: bool :=
+   match cmp with
+   | EQ' => eq_vec valA valB
+   | NE => neq_vec valA valB
+   | GE => zopz0zKzJ_s valA valB
+   | GEU => zopz0zKzJ_u valA valB
+   | GT' => zopz0zI_s valB valA
+   | LE => zopz0zKzJ_s valB valA
+   | LT' => zopz0zI_s valA valB
+   | LTU => zopz0zI_u valA valB
+   end.
+
+Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = arg_)}
+: WordType :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then B
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then H
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then W
+   else D.
+
+Definition num_of_WordType (arg_ : WordType) 
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+   match arg_ with | B => build_ex 0 | H => build_ex 1 | W => build_ex 2 | D => build_ex 3 end.
+
+Definition undefined_WordType '(tt : unit) 
+: M (WordType) :=
+   (internal_pick [B;H;W;D])
+    : M (WordType).
+
+Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ =
+  arg_)}
+: WordTypeUnaligned :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then WL
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then DL
+   else DR.
+
+Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) 
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+   match arg_ with | WL => build_ex 0 | WR => build_ex 1 | DL => build_ex 2 | DR => build_ex 3 end.
+
+Definition undefined_WordTypeUnaligned '(tt : unit) 
+: M (WordTypeUnaligned) :=
+   (internal_pick [WL;WR;DL;DR])
+    : M (WordTypeUnaligned).
+
+Definition wordWidthBytes (w : WordType) 
+: {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} :=
+   match w with | B => build_ex 1 | H => build_ex 2 | W => build_ex 4 | D => build_ex 8 end.
+
+Definition alignment_width := 16.
+
+Definition isAddressAligned (addr : mword 64) (wordType : WordType) 
+: bool :=
+   let '(existT _ a _) := uint addr in
+   Z.eqb (projT1 (div_with_eq a alignment_width))
+     (Z.quot (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width).
+
+Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size =
+  size)}
+: M (mword (8 * size)) :=
+   (if ((eq_vec addr
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      (read_reg UART_RVALID_ref  : M (mword 1)) >>= fun rvalid =>
+      write_reg UART_RVALID_ref (vec_of_bits [B0]  : mword 1) >>
+      (read_reg UART_RDATA_ref  : M (mword 8)) >>= fun w__0 =>
+      returnm ((mask (Z.mul 8 size)
+                  (concat_vec
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                       : mword 32)
+                     (concat_vec w__0
+                        (concat_vec rvalid
+                           (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  : mword 7)
+                              (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                : mword 16))))))
+       : mword (8 * size))
+    else if ((eq_vec addr
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+                              B0]
+                  : mword 64))) then
+      returnm ((mask (Z.mul 8 size)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                                B1]
+                    : mword 64))
+       : mword (8 * size))
+    else
+      autocast_m (MEMr addr size) >>= fun w__1 =>
+      returnm ((autocast (reverse_endianness w__1))
+       : mword (8 * size)))
+    : M (mword (8 * size)).
+
+Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size =
+  size)}
+: M (mword (8 * size)) :=
+   autocast_m (MEMr_reserve addr size) >>= fun w__0 =>
+   returnm ((autocast (reverse_endianness w__0))
+    : mword (8 * size)).
+
+Definition init_cp0_state '(tt : unit) 
+: M (unit) :=
+   (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1)  : mword 1))
+    : M (unit).
+
+Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) 
+: bool :=
+   let entryValid := _get_TLBEntry_valid entry in
+   let entryR := _get_TLBEntry_r entry in
+   let entryMask := _get_TLBEntry_pagemask entry in
+   let entryVPN := _get_TLBEntry_vpn2 entry in
+   let entryASID := _get_TLBEntry_asid entry in
+   let entryG := _get_TLBEntry_g entry in
+   let vpnMask : bits 27 := not_vec (mips_zero_extend 27 entryMask) in
+   andb ((bits_to_bool entryValid)  : bool)
+     (andb (eq_vec r entryR)
+        (andb (eq_vec (and_vec vpn2 vpnMask) (and_vec entryVPN vpnMask))
+           (orb (eq_vec asid entryASID) ((bits_to_bool entryG)  : bool)))).
+
+Definition tlbSearch (VAddr : mword 64) 
+: M (option (mword 6)) :=
+   catch_early_return
+     (let r := subrange_vec_dec VAddr 63 62 in
+     let vpn2 := subrange_vec_dec VAddr 39 13 in
+     liftR (read_reg TLBEntryHi_ref) >>= fun w__0 =>
+     let asid := _get_TLBEntryHiReg_ASID w__0 in
+     (foreach_ZM_up 0 63 1 tt
+       (fun idx _ unit_var =>
+         liftR (reg_deref (vec_access_dec TLBEntries idx)) >>= fun w__1 =>
+         (if ((tlbEntryMatch r vpn2 asid w__1)) then
+            (early_return ((Some (to_bits 6 idx))  : option (mword 6)) : MR unit (option (mword 6)))
+             : MR (unit) _
+          else returnm (tt  : unit))
+          : MR (unit) _)) >>
+     returnm (None
+      : option (mword 6))).
+
+Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) 
+: M ((mword 64 * bool)) :=
+   tlbSearch vAddr >>= fun idx =>
+   (match idx with
+    | Some (idx) =>
+       let '(existT _ i _) := uint idx in
+       reg_deref (vec_access_dec TLBEntries i) >>= fun entry =>
+       let entryMask := _get_TLBEntry_pagemask entry in
+       let b__0 := entryMask in
+       (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16)))
+        then
+          returnm ((build_ex
+          12)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          14)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          16)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          18)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          20)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          22)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          24)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          26)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          28)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else
+          (undefined_range 12 28)
+           : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _) =>
+       let isOdd := access_vec_dec vAddr evenOddBit in
+       let '(caps, capl, pfn, d, v) :=
+         if (((bit_to_bool isOdd)  : bool)) then
+           (_get_TLBEntry_caps1 entry,
+            _get_TLBEntry_capl1 entry,
+            _get_TLBEntry_pfn1 entry,
+            _get_TLBEntry_d1 entry,
+            _get_TLBEntry_v1 entry)
+         else
+           (_get_TLBEntry_caps0 entry,
+            _get_TLBEntry_capl0 entry,
+            _get_TLBEntry_pfn0 entry,
+            _get_TLBEntry_d0 entry,
+            _get_TLBEntry_v0 entry) in
+       (if ((negb ((bits_to_bool v)  : bool))) then
+          (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL)
+             vAddr)
+           : M ((mword 64 * bool))
+        else if ((andb (generic_eq accessType StoreData) (negb ((bits_to_bool d)  : bool)))) then
+          (SignalExceptionTLB TLBMod vAddr)
+           : M ((mword 64 * bool))
+        else
+          let res : bits 64 :=
+            mips_zero_extend 64
+              (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12))
+                 (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in
+          returnm ((res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl))
+           : (mword 64 * bool)))
+        : M ((mword 64 * bool))
+    | None =>
+       (SignalExceptionTLB
+          (if ((generic_eq accessType StoreData)) then XTLBRefillS
+           else XTLBRefillL) vAddr)
+        : M ((mword 64 * bool))
+    end)
+    : M ((mword 64 * bool)).
+
+Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) 
+: M ((mword 64 * bool)) :=
+   getAccessLevel tt >>= fun currentAccessLevel =>
+   let compat32 :=
+     eq_vec (subrange_vec_dec vAddr 61 31)
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]
+         : mword 31) in
+   let b__0 := subrange_vec_dec vAddr 63 62 in
+   let '(requiredLevel, addr) :=
+     (if ((eq_vec b__0 (vec_of_bits [B1;B1]  : mword 2))) then
+        match (compat32, subrange_vec_dec vAddr 30 29) with
+        | (true, b__1) =>
+           if ((eq_vec b__1 (vec_of_bits [B1;B1]  : mword 2))) then
+             (Kernel, None  : option (bits 64))
+           else if ((eq_vec b__1 (vec_of_bits [B1;B0]  : mword 2))) then
+             (Supervisor, None  : option (bits 64))
+           else if ((eq_vec b__1 (vec_of_bits [B0;B1]  : mword 2))) then
+             (Kernel,
+              Some (concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        : mword 32)
+                      (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3) (subrange_vec_dec vAddr 28 0))))
+           else if ((eq_vec b__1 (vec_of_bits [B0;B0]  : mword 2))) then
+             (Kernel,
+              Some (concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        : mword 32)
+                      (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3) (subrange_vec_dec vAddr 28 0))))
+           else match (true, b__1) with | (g__25, g__26) => (Kernel, None  : option (bits 64)) end
+        | (g__25, g__26) => (Kernel, None  : option (bits 64))
+        end
+      else if ((eq_vec b__0 (vec_of_bits [B1;B0]  : mword 2))) then
+        (Kernel,
+         Some (concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5) (subrange_vec_dec vAddr 58 0)))
+      else if ((eq_vec b__0 (vec_of_bits [B0;B1]  : mword 2))) then
+        (Supervisor, None  : option (bits 64))
+      else (User, None  : option (bits 64)))
+      : (AccessLevel * option (bits 64)) in
+   (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then
+      (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr)
+       : M ((mword 64 * bool))
+    else
+      match addr with
+      | Some (a) => returnm ((a, false)  : (mword 64 * bool))
+      | None =>
+         (if ((andb (negb compat32) (gtb_range_l (uint (subrange_vec_dec vAddr 61 0)) MAX_VA))) then
+            (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL)
+               vAddr)
+             : M ((bits 64 * bool))
+          else (TLBTranslate2 vAddr accessType)  : M ((bits 64 * bool)))
+          : M ((mword 64 * bool))
+      end >>= fun '(pa, c) =>
+      (if ((gtb_range_l (uint pa) MAX_PA)) then
+         (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr)
+          : M ((mword 64 * bool))
+       else returnm ((pa, c)  : (mword 64 * bool)))
+       : M ((mword 64 * bool)))
+    : M ((mword 64 * bool)).
+
+Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) 
+: M (mword 64) :=
+   TLBTranslateC vAddr accessType >>= fun '(addr, c) => returnm (addr  : mword 64).
+
+Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <=
+  size /\
+  size <= 8)} `{ArithFact (size = size)}
+: M (unit) :=
+   let ledata := autocast (reverse_endianness data) in
+   (if ((eq_vec addr
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >>
+      write_reg UART_WRITTEN_ref ((cast_unit_vec B1)  : bits 1)
+       : M (unit)
+    else MEMea addr size >> (MEMval addr size ledata)  : M (unit))
+    : M (unit).
+
+Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <=
+  size /\
+  size <= 8)} `{ArithFact (size = size)}
+: M (bool) :=
+   MEMea_conditional addr size >>
+   (MEMval_conditional addr size (autocast (reverse_endianness data)))
+    : M (bool).
+
+Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) 
+: mword 64 :=
+   addr.
+
+Definition addrWrapperUnaligned (addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) 
+: mword 64 :=
+   addr.
+
+Definition TranslatePC (vAddr : mword 64) 
+: M (mword 64) :=
+   incrementCP0Count tt >>
+   (if ((neq_vec (subrange_vec_dec vAddr 1 0) (vec_of_bits [B0;B0]  : mword 2))) then
+      (SignalExceptionBadAddr AdEL vAddr)
+       : M (mword 64)
+    else (TLBTranslate vAddr Instruction)  : M (mword 64))
+    : M (mword 64).
+
+Definition have_cp2 := false.
+
+Definition ERETHook '(tt : unit)  : unit := tt.
+
+Definition init_cp2_state '(tt : unit)  : M (unit) := (skip tt)  : M (unit).
+
+Definition cp2_next_pc '(tt : unit)  : M (unit) := skip tt >> (skip tt)  : M (unit).
+
+Definition dump_cp2_state '(tt : unit)  : M (unit) := skip tt >> (skip tt)  : M (unit).
+
+Definition undefined_ast '(tt : unit) 
+: M (ast) :=
+   undefined_Comparison tt >>= fun u_0 =>
+   undefined_WordType tt >>= fun u_1 =>
+   undefined_bool tt >>= fun u_3 =>
+   undefined_bool tt >>= fun u_2 =>
+   undefined_bitvector 16 >>= fun u_4 =>
+   undefined_bitvector 5 >>= fun u_7 =>
+   undefined_bitvector 5 >>= fun u_6 =>
+   undefined_bitvector 5 >>= fun u_5 =>
+   undefined_unit tt >>= fun u_8 =>
+   undefined_bitvector 3 >>= fun u_9 =>
+   undefined_bitvector 16 >>= fun u_10 =>
+   undefined_bitvector 26 >>= fun u_11 =>
+   (internal_pick
+      [DADDIU (u_6,u_5,u_4);DADDU (u_7,u_6,u_5);DADDI (u_6,u_5,u_10);DADD (u_7,u_6,u_5);ADD (u_7,u_6,u_5);ADDI (u_6,u_5,u_10);ADDU (u_7,u_6,u_5);ADDIU (u_6,u_5,u_10);DSUBU (u_7,u_6,u_5);DSUB (u_7,u_6,u_5);SUB (u_7,u_6,u_5);SUBU (u_7,u_6,u_5);AND (u_7,u_6,u_5);ANDI (u_6,u_5,u_10);OR (u_7,u_6,u_5);ORI (u_6,u_5,u_10);NOR (u_7,u_6,u_5);XOR (u_7,u_6,u_5);XORI (u_6,u_5,u_10);LUI (u_5,u_4);DSLL (u_7,u_6,u_5);DSLL32 (u_7,u_6,u_5);DSLLV (u_7,u_6,u_5);DSRA (u_7,u_6,u_5);DSRA32 (u_7,u_6,u_5);DSRAV (u_7,u_6,u_5);DSRL (u_7,u_6,u_5);DSRL32 (u_7,u_6,u_5);DSRLV (u_7,u_6,u_5);SLL (u_7,u_6,u_5);SLLV (u_7,u_6,u_5);SRA (u_7,u_6,u_5);SRAV (u_7,u_6,u_5);SRL (u_7,u_6,u_5);SRLV (u_7,u_6,u_5);SLT (u_7,u_6,u_5);SLTI (u_6,u_5,u_10);SLTU (u_7,u_6,u_5);SLTIU (u_6,u_5,u_10);MOVN (u_7,u_6,u_5);MOVZ (u_7,u_6,u_5);MFHI u_5;MFLO u_5;MTHI u_5;MTLO u_5;MUL (u_7,u_6,u_5);MULT (u_6,u_5);MULTU (u_6,u_5);DMULT (u_6,u_5);DMULTU (u_6,u_5);MADD (u_6,u_5);MADDU (u_6,u_5);MSUB (u_6,u_5);MSUBU (u_6,u_5);DIV (u_6,u_5);DIVU (u_6,u_5);DDIV (u_6,u_5);DDIVU (u_6,u_5);J u_11;JAL u_11;JR u_5;JALR (u_6,u_5);BEQ (u_6,u_5,u_4,u_3,u_2);BCMPZ (u_5,u_4,u_0,u_3,u_2);SYSCALL u_8;BREAK u_8;WAIT u_8;TRAPREG (u_6,u_5,u_0);TRAPIMM (u_5,u_4,u_0);Load (u_1,u_3,u_2,u_6,u_5,u_4);Store (u_1,u_2,u_6,u_5,u_4);LWL (u_6,u_5,u_10);LWR (u_6,u_5,u_10);SWL (u_6,u_5,u_10);SWR (u_6,u_5,u_10);LDL (u_6,u_5,u_10);LDR (u_6,u_5,u_10);SDL (u_6,u_5,u_10);SDR (u_6,u_5,u_10);CACHE (u_6,u_5,u_10);SYNC u_8;MFC0 (u_6,u_5,u_9,u_2);HCF u_8;MTC0 (u_6,u_5,u_9,u_2);TLBWI u_8;TLBWR u_8;TLBR u_8;TLBP u_8;RDHWR (u_6,u_5);ERET u_8;RI u_8])
+    : M (ast).
+
+Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} 
+: mword 64 :=
+   if (sign) then mips_sign_extend 64 memResult
+   else mips_zero_extend 64 memResult.
+
+Definition TLBWriteEntry (idx : mword 6) 
+: M (unit) :=
+   (read_reg TLBPageMask_ref  : M (mword 16)) >>= fun pagemask =>
+   let b__0 := pagemask in
+   (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16)))
+    then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else (SignalException MCheck)  : M (unit)) >>
+   let '(existT _ i _) := uint idx in
+   let entry := vec_access_dec TLBEntries i in
+   _set_TLBEntry_pagemask entry pagemask >>
+   read_reg TLBEntryHi_ref >>= fun w__0 =>
+   _set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0) >>
+   read_reg TLBEntryHi_ref >>= fun w__1 =>
+   _set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1) >>
+   read_reg TLBEntryHi_ref >>= fun w__2 =>
+   _set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2) >>
+   and_boolM
+     (read_reg TLBEntryLo0_ref >>= fun w__3 =>
+      returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3))
+       : bool))
+     (read_reg TLBEntryLo1_ref >>= fun w__4 =>
+      returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4))
+       : bool)) >>= fun w__5 =>
+   _set_TLBEntry_g entry ((bool_to_bits w__5)  : mword 1) >>
+   _set_TLBEntry_valid entry ((cast_unit_vec B1)  : mword 1) >>
+   read_reg TLBEntryLo0_ref >>= fun w__6 =>
+   _set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6) >>
+   read_reg TLBEntryLo0_ref >>= fun w__7 =>
+   _set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7) >>
+   read_reg TLBEntryLo0_ref >>= fun w__8 =>
+   _set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8) >>
+   read_reg TLBEntryLo0_ref >>= fun w__9 =>
+   _set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9) >>
+   read_reg TLBEntryLo0_ref >>= fun w__10 =>
+   _set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10) >>
+   read_reg TLBEntryLo0_ref >>= fun w__11 =>
+   _set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11) >>
+   read_reg TLBEntryLo1_ref >>= fun w__12 =>
+   _set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12) >>
+   read_reg TLBEntryLo1_ref >>= fun w__13 =>
+   _set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13) >>
+   read_reg TLBEntryLo1_ref >>= fun w__14 =>
+   _set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14) >>
+   read_reg TLBEntryLo1_ref >>= fun w__15 =>
+   _set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15) >>
+   read_reg TLBEntryLo1_ref >>= fun w__16 =>
+   _set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16) >>
+   read_reg TLBEntryLo1_ref >>= fun w__17 =>
+   (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17))
+    : M (unit).
+
+Definition decode (v__0 : mword 32) 
+: option ast :=
+   if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B1]  : mword 6))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (DADDIU (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DADDU (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (DADDI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DADD (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (ADD (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ADDI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (ADDU (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ADDIU (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSUBU (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSUB (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SUB (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SUBU (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (AND (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ANDI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (OR (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ORI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (NOR (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (XOR (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B1;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (XORI (rs,rt,imm))
+   else if ((eq_vec (subrange_vec_dec v__0 31 21)
+               (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0]  : mword 11))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LUI (rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B0;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSLL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B0;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSLL32 (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSLLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B1]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRA (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B1]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRA32 (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSRAV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRL32 (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSRLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : regno := subrange_vec_dec v__0 10 6 in
+     Some (SLL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SLLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B1]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : regno := subrange_vec_dec v__0 10 6 in
+     Some (SRA (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SRAV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : regno := subrange_vec_dec v__0 10 6 in
+     Some (SRL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SRLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SLT (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SLTI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SLTU (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SLTIU (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MOVN (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MOVZ (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 16)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0]  : mword 11)))) then
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MFHI rd)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 16)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0]  : mword 11)))) then
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MFLO rd)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1]
+                    : mword 21)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     Some (MTHI rs)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1]
+                    : mword 21)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     Some (MTLO rs)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MUL (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MULT (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MULTU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DMULT (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DMULTU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MADD (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MADDU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MSUB (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MSUBU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DIV (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DIVU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DDIV (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DDIVU (rs,rt))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B0]  : mword 6)))
+   then
+     let offset : bits 26 := subrange_vec_dec v__0 25 0 in
+     Some (J offset)
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B1]  : mword 6)))
+   then
+     let offset : bits 26 := subrange_vec_dec v__0 25 0 in
+     Some (JAL offset)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (andb
+                  (eq_vec (subrange_vec_dec v__0 20 11)
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 10))
+                  (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B0]  : mword 6)))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     Some (JR rs)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (andb
+                  (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))
+                  (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B1]  : mword 6)))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (JALR (rs,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,false,false))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,false,true))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,true,false))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,true,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',true,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',true,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,true,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,true,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GT',false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GT',false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LE,false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LE,false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B0]  : mword 6))))
+   then
+     Some (SYSCALL tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B1]  : mword 6))))
+   then
+     Some (BREAK tt)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]
+                 : mword 32))) then
+     Some (WAIT tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,GE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B1]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,GEU))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,LT'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B1]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,LTU))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B0;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,EQ'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B1;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,NE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,EQ'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,NE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,GE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,GEU))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,LT'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,LTU))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (B,true,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (B,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (H,true,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (H,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (W,true,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (W,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (D,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (W,true,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (D,false,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (B,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (H,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (W,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (D,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (W,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (D,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LWL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LWR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SWL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SWR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LDL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LDR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SDL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SDR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let op : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (CACHE (base,op,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 11)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                    : mword 21))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B1;B1]  : mword 6))))
+   then
+     Some (SYNC tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MFC0 (rt,rd,sel,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MFC0 (rt,rd,sel,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+   then
+     Some (HCF tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+   then
+     Some (HCF tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MTC0 (rt,rd,sel,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MTC0 (rt,rd,sel,true))
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]
+                 : mword 32))) then
+     Some ((TLBWI tt)
+      : ast)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]
+                 : mword 32))) then
+     Some ((TLBWR tt)
+      : ast)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]
+                 : mword 32))) then
+     Some ((TLBR tt)
+      : ast)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0]
+                 : mword 32))) then
+     Some ((TLBP tt)
+      : ast)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1]  : mword 11)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (RDHWR (rt,rd))
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]
+                 : mword 32))) then
+     Some (ERET tt)
+   else Some (RI tt).
+
+Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm)))  : M (unit).
+
+Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (xor_vec w__0 w__1))  : M (unit).
+
+Definition execute_WAIT (g__16 : unit) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 => write_reg nextPC_ref w__0  : M (unit).
+
+Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   rGPR rt >>= fun rt_val =>
+   let condition := compare cmp rs_val rt_val in
+   (if (condition) then (SignalException Tr)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   let imm_val : bits 64 := mips_sign_extend 64 imm in
+   let condition := compare cmp rs_val imm_val in
+   (if (condition) then (SignalException Tr)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_TLBWR (g__20 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0)  : M (unit).
+
+Definition execute_TLBWI (g__19 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   (read_reg TLBIndex_ref  : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0)  : M (unit).
+
+Definition execute_TLBR (g__21 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   (read_reg TLBIndex_ref  : M (mword 6)) >>= fun w__0 =>
+   let '(existT _ i _) := uint w__0 in
+   reg_deref (vec_access_dec TLBEntries i) >>= fun entry =>
+   write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >>
+   _set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry) >>
+   _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry) >>
+   _set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry) >>
+   _set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry) >>
+   _set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry) >>
+   _set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry) >>
+   _set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry) >>
+   _set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry) >>
+   _set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry) >>
+   _set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry) >>
+   _set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry) >>
+   _set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry) >>
+   _set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry) >>
+   _set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry) >>
+   _set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry) >>
+   _set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry) >>
+   (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry))
+    : M (unit).
+
+Definition execute_TLBP (g__22 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   read_reg TLBEntryHi_ref >>= fun w__0 =>
+   tlbSearch (_get_TLBEntryHiReg_bits w__0) >>= fun result =>
+   (match result with
+    | Some (idx) =>
+       write_reg TLBProbe_ref (vec_of_bits [B0]  : mword 1) >>
+       write_reg TLBIndex_ref idx
+        : M (unit)
+    | None =>
+       write_reg TLBProbe_ref (vec_of_bits [B1]  : mword 1) >>
+       write_reg TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6)
+        : M (unit)
+    end)
+    : M (unit).
+
+Definition execute_Store (width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width in
+   rGPR rt >>= fun rt_val =>
+   (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr)  : M (unit)
+    else
+      TLBTranslate vAddr StoreData >>= fun pAddr =>
+      (if (conditional) then
+         (read_reg CP0LLBit_ref  : M (mword 1)) >>= fun w__1 =>
+         (if (((bit_to_bool (access_vec_dec w__1 0))  : bool)) then
+            (match width with
+             | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0))  : M (bool)
+             | D => (MEMw_conditional_wrapper pAddr 8 rt_val)  : M (bool)
+             | _ => (throw (Error_internal_error tt))  : M (bool)
+             end)
+             : M (bool)
+          else returnm (false  : bool)) >>= fun success =>
+         (wGPR rt (mips_zero_extend 64 ((bool_to_bits success)  : mword 1)))
+          : M (unit)
+       else
+         (match width with
+          | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rt_val 7 0))  : M (unit)
+          | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rt_val 15 0))  : M (unit)
+          | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0))  : M (unit)
+          | D => (MEMw_wrapper pAddr 8 rt_val)  : M (unit)
+          end)
+          : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SYSCALL (g__14 : unit)  : M (unit) := (SignalException Sys)  : M (unit).
+
+Definition execute_SYNC (g__17 : unit)  : M (unit) := (MEM_sync tt)  : M (unit).
+
+Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0]  : mword 2) in
+   rGPR rt >>= fun reg_val =>
+   let b__12 := subrange_vec_dec vAddr 1 0 in
+   (if ((eq_vec b__12 (vec_of_bits [B0;B0]  : mword 2))) then
+      (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0))
+       : M (unit)
+    else if ((eq_vec b__12 (vec_of_bits [B0;B1]  : mword 2))) then
+      (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0))
+       : M (unit)
+    else if ((eq_vec b__12 (vec_of_bits [B1;B0]  : mword 2))) then
+      (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0))
+       : M (unit)
+    else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0))  : M (unit))
+    : M (unit).
+
+Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   rGPR rt >>= fun reg_val =>
+   let b__8 := subrange_vec_dec vAddr 1 0 in
+   (if ((eq_vec b__8 (vec_of_bits [B0;B0]  : mword 2))) then
+      (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0))
+       : M (unit)
+    else if ((eq_vec b__8 (vec_of_bits [B0;B1]  : mword 2))) then
+      (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8))
+       : M (unit)
+    else if ((eq_vec b__8 (vec_of_bits [B1;B0]  : mword 2))) then
+      (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16))
+       : M (unit)
+    else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24))  : M (unit))
+    : M (unit).
+
+Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      (wGPR rd
+         (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0))))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let temp33 : bits 33 :=
+        sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0))
+          (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in
+      (if ((neq_bool ((bit_to_bool (access_vec_dec temp33 32))  : bool)
+              ((bit_to_bool (access_vec_dec temp33 31))
+               : bool))) then
+         (SignalException Ov)
+          : M (unit)
+       else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec temp33 31 0)))  : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 4 0 in
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2))  : M (unit))
+    : M (unit).
+
+Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1))  : M (unit))
+    : M (unit).
+
+Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 4 0 in
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right_arith rt32 sa >>= fun w__2 =>
+      (wGPR rd (mips_sign_extend 64 w__2))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right_arith rt32 sa >>= fun w__1 =>
+      (wGPR rd (mips_sign_extend 64 w__1))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   rGPR rt >>= fun rt_val =>
+   (wGPR rd
+      (mips_zero_extend 64
+         (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   let immext : bits 64 := mips_sign_extend 64 imm in
+   (wGPR rt
+      (mips_zero_extend 64
+         (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   let '(existT _ imm_val _) := sint imm in
+   rGPR rs >>= fun w__0 =>
+   let '(existT _ rs_val _) := sint w__0 in
+   (wGPR rt
+      (mips_zero_extend 64
+         (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   (wGPR rd
+      (mips_zero_extend 64
+         (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 4 0 in
+   rGPR rt >>= fun w__1 =>
+   let rt32 := subrange_vec_dec w__1 31 0 in
+   shift_bits_left rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2))  : M (unit).
+
+Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   let rt32 := subrange_vec_dec w__0 31 0 in
+   shift_bits_left rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1))  : M (unit).
+
+Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   rGPR rt >>= fun reg_val =>
+   let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0]  : mword 3) in
+   let b__40 := subrange_vec_dec vAddr 2 0 in
+   (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+      (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+      (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+      (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0))
+       : M (unit)
+    else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   rGPR rt >>= fun reg_val =>
+   let b__32 := subrange_vec_dec vAddr 2 0 in
+   (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+      (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+      (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+      (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48))
+       : M (unit)
+    else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56))  : M (unit))
+    : M (unit).
+
+Definition execute_RI (g__24 : unit)  : M (unit) := (SignalException ResI)  : M (unit).
+
+Definition execute_RDHWR (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   getAccessLevel tt >>= fun accessLevel =>
+   let haveAccessLevel : bool := generic_eq accessLevel Kernel in
+   read_reg CP0Status_ref >>= fun w__0 =>
+   let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in
+   let '(existT _ rdi _) := uint rd in
+   (read_reg CP0HWREna_ref  : M (mword 32)) >>= fun w__1 =>
+   let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in
+   (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then
+      (SignalException ResI)
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   let b__146 := rd in
+   (if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))) then
+      returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))) then
+      returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))) then
+      (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__2 =>
+      returnm ((mips_zero_extend 64 w__2)
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))) then
+      returnm ((mips_zero_extend 64 (vec_of_bits [B1]  : mword 1))
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B1;B1;B1;B0;B1]  : mword 5))) then
+      (read_reg CP0UserLocal_ref  : M (mword 64))
+       : M (bits 64)
+    else (SignalException ResI)  : M (bits 64)) >>= fun temp =>
+   (wGPR rt temp)
+    : M (unit).
+
+Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm)))  : M (unit).
+
+Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (or_vec w__0 w__1))  : M (unit).
+
+Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 => (wGPR rd (not_vec (or_vec w__0 w__1)))  : M (unit).
+
+Definition execute_MULTU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))  : bits 64)) >>= fun result =>
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MULT (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else
+      returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))
+       : bits 64)) >>= fun result =>
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   let result : bits 64 :=
+     mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (mword 64)
+    else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0))  : mword 64)) >>= fun w__1 =>
+   (wGPR rd w__1)
+    : M (unit).
+
+Definition execute_MTLO (rs : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => write_reg LO_ref w__0  : M (unit).
+
+Definition execute_MTHI (rs : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => write_reg HI_ref w__0  : M (unit).
+
+Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) 
+: M (unit) :=
+   checkCP0Access tt >>
+   rGPR rt >>= fun reg_val =>
+   (match (rd, sel) with
+    | (b__108, b__109) =>
+       (if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))
+               (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg TLBIndex_ref (mask 6 reg_val)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          returnm (tt
+           : unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B1;B0]  : mword 3)))) then
+          write_reg CP0UserLocal_ref reg_val
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax  : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg
+            CP0HWREna_ref
+            (concat_vec (subrange_vec_dec reg_val 31 29)
+               (concat_vec
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0]
+                    : mword 25) (subrange_vec_dec reg_val 3 0)))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          returnm (tt
+           : unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62) >>
+          _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13) >>
+          (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >>
+          read_reg CP0Cause_ref >>= fun w__0 =>
+          (_set_CauseReg_IP CP0Cause_ref
+             (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1]  : mword 8)))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          _set_StatusReg_CU CP0Status_ref (subrange_vec_dec reg_val 31 28) >>
+          _set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22))  : mword 1) >>
+          _set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8) >>
+          _set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7))  : mword 1) >>
+          _set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6))  : mword 1) >>
+          _set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5))  : mword 1) >>
+          _set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3) >>
+          _set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2))  : mword 1) >>
+          _set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1))  : mword 1) >>
+          (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0))  : mword 1))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          _set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23))  : mword 1) >>
+          read_reg CP0Cause_ref >>= fun w__1 =>
+          let ip := _get_CauseReg_IP w__1 in
+          (_set_CauseReg_IP CP0Cause_ref
+             (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8)))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0EPC_ref reg_val
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B1;B1;B1;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0ErrorEPC_ref reg_val
+           : M (unit)
+        else (SignalException ResI)  : M (unit))
+        : M (unit)
+    end)
+    : M (unit).
+
+Definition execute_MSUBU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))  : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MSUB (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else
+      returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))
+       : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   (if ((eq_vec w__0
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      rGPR rs >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   (if ((neq_vec w__0
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      rGPR rs >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_MFLO (rd : mword 5) 
+: M (unit) :=
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_MFHI (rd : mword 5) 
+: M (unit) :=
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) 
+: M (unit) :=
+   checkCP0Access tt >>
+   match (rd, sel) with
+   | (b__48, b__49) =>
+      (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))
+              (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBIndex_ref  : M (mword 6)) >>= fun w__0 =>
+         let idx : bits 31 := mips_zero_extend 31 w__0 in
+         (read_reg TLBProbe_ref  : M (mword 1)) >>= fun w__1 =>
+         returnm ((concat_vec
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                       : mword 32) (concat_vec w__1 idx))
+          : mword 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__2 =>
+         returnm ((mips_zero_extend 64 w__2)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBEntryLo0_ref >>= fun w__3 =>
+         returnm ((_get_TLBEntryLoReg_bits w__3)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBEntryLo1_ref >>= fun w__4 =>
+         returnm ((_get_TLBEntryLoReg_bits w__4)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBContext_ref >>= fun w__5 => returnm ((_get_ContextReg_bits w__5)  : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B1;B0]  : mword 3)))) then
+         (read_reg CP0UserLocal_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBPageMask_ref  : M (mword 16)) >>= fun w__7 =>
+         returnm ((mips_zero_extend 64
+                     (concat_vec w__7
+                        (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 12)))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBWired_ref  : M (mword 6)) >>= fun w__8 =>
+         returnm ((mips_zero_extend 64 w__8)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0HWREna_ref  : M (mword 32)) >>= fun w__9 =>
+         returnm ((mips_zero_extend 64 w__9)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0BadVAddr_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B1]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__11 =>
+         returnm ((mips_zero_extend 64 w__11)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBEntryHi_ref >>= fun w__12 =>
+         returnm ((_get_TLBEntryHiReg_bits w__12)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0Compare_ref  : M (mword 32)) >>= fun w__13 =>
+         returnm ((mips_zero_extend 64 w__13)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg CP0Status_ref >>= fun w__14 =>
+         returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__14))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg CP0Cause_ref >>= fun w__15 =>
+         returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__15))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0EPC_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                   B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                       : mword 32))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B1;B1;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B1;B1;B1]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0ConfigK0_ref  : M (mword 3)) >>= fun w__17 =>
+         returnm ((mips_zero_extend 64
+                     (concat_vec (vec_of_bits [B1]  : mword 1)
+                        (concat_vec
+                           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 15)
+                           (concat_vec (vec_of_bits [B1]  : mword 1)
+                              (concat_vec (vec_of_bits [B1;B0]  : mword 2)
+                                 (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                    (concat_vec (vec_of_bits [B0;B0;B1]  : mword 3)
+                                       (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4) w__17))))))))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B1]  : mword 3)))) then
+         returnm ((mips_zero_extend 64
+                     (concat_vec (vec_of_bits [B1]  : mword 1)
+                        (concat_vec TLBIndexMax
+                           (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                              (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                 (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                    (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                       (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                          (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                             (concat_vec (bool_to_bits have_cp2)
+                                                (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                   (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                      (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                         (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                            (concat_vec
+                                                               (vec_of_bits [B0]  : mword 1)
+                                                               (vec_of_bits [B0]  : mword 1))))))))))))))))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B1;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64
+                     (concat_vec (vec_of_bits [B1]  : mword 1)
+                        (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                           (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                              (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                 (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                    (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                       (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                          (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                             (vec_of_bits [B0;B0;B0;B0]  : mword 4))))))))))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B1;B1]  : mword 3)))) then
+         returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0]
+                    : mword 64)
+          : mword 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B1;B0;B1]  : mword 3)))) then
+         returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0]
+                    : mword 64)
+          : mword 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0LLAddr_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBXContext_ref >>= fun w__19 =>
+         returnm ((_get_XContextReg_bits w__19)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0ErrorEPC_ref  : M (mword 64))
+          : M (bits 64)
+       else (SignalException ResI)  : M (bits 64))
+       : M (mword 64)
+   end >>= fun result =>
+   (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0)))
+    : M (unit).
+
+Definition execute_MADDU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))  : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MADD (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else
+      returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))
+       : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_Load (width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width in
+   (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr)  : M (unit)
+    else
+      TLBTranslate vAddr LoadData >>= fun pAddr =>
+      (if (linked) then
+         write_reg CP0LLBit_ref (vec_of_bits [B1]  : mword 1) >>
+         write_reg CP0LLAddr_ref pAddr >>
+         (match width with
+          | W =>
+             MEMr_reserve_wrapper pAddr 4 >>= fun w__1 =>
+             returnm ((extendLoad w__1 sign)
+              : bits 64)
+          | D =>
+             MEMr_reserve_wrapper pAddr 8 >>= fun w__2 =>
+             returnm ((extendLoad w__2 sign)
+              : bits 64)
+          | _ => (throw (Error_internal_error tt))  : M (mword 64)
+          end)
+          : M (mword 64)
+       else
+         (match width with
+          | B => MEMr_wrapper pAddr 1 >>= fun w__5 => returnm ((extendLoad w__5 sign)  : bits 64)
+          | H => MEMr_wrapper pAddr 2 >>= fun w__6 => returnm ((extendLoad w__6 sign)  : bits 64)
+          | W => MEMr_wrapper pAddr 4 >>= fun w__7 => returnm ((extendLoad w__7 sign)  : bits 64)
+          | D => MEMr_wrapper pAddr 8 >>= fun w__8 => returnm ((extendLoad w__8 sign)  : bits 64)
+          end)
+          : M (mword 64)) >>= fun memResult =>
+      (wGPR rt memResult)
+       : M (unit))
+    : M (unit).
+
+Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0]  : mword 2)) 4 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__4 := subrange_vec_dec vAddr 1 0 in
+   let result : bits 32 :=
+     if ((eq_vec b__4 (vec_of_bits [B0;B0]  : mword 2))) then
+       concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24)
+     else if ((eq_vec b__4 (vec_of_bits [B0;B1]  : mword 2))) then
+       concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16)
+     else if ((eq_vec b__4 (vec_of_bits [B1;B0]  : mword 2))) then
+       concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8)
+     else mem_val in
+   (wGPR rt (mips_sign_extend 64 result))
+    : M (unit).
+
+Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0]  : mword 2)) 4 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__0 := subrange_vec_dec vAddr 1 0 in
+   let result : bits 32 :=
+     if ((eq_vec b__0 (vec_of_bits [B0;B0]  : mword 2))) then mem_val
+     else if ((eq_vec b__0 (vec_of_bits [B0;B1]  : mword 2))) then
+       concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0)
+     else if ((eq_vec b__0 (vec_of_bits [B1;B0]  : mword 2))) then
+       concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0)
+     else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in
+   (wGPR rt (mips_sign_extend 64 result))
+    : M (unit).
+
+Definition execute_LUI (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   (wGPR rt
+      (mips_sign_extend 64
+         (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+    : M (unit).
+
+Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0]  : mword 3)) 8 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__24 := subrange_vec_dec vAddr 2 0 in
+   (wGPR rt
+      (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56)
+       else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48)
+       else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40)
+       else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32)
+       else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24)
+       else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16)
+       else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8)
+       else mem_val))
+    : M (unit).
+
+Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0]  : mword 3)) 8 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__16 := subrange_vec_dec vAddr 2 0 in
+   (wGPR rt
+      (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0]  : mword 3))) then mem_val
+       else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0)
+       else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0)
+       else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0)
+       else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0)
+       else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0)
+       else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0)
+       else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0)))
+    : M (unit).
+
+Definition execute_JR (rs : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (execute_branch w__0)  : M (unit).
+
+Definition execute_JALR (rs : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   execute_branch w__0 >>
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__1 => (wGPR rd (add_vec_int w__1 8))  : M (unit).
+
+Definition execute_JAL (offset : mword 26) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 =>
+   execute_branch
+     (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28)
+        (concat_vec offset (vec_of_bits [B0;B0]  : mword 2))) >>
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__1 =>
+   (wGPR (vec_of_bits [B1;B1;B1;B1;B1]  : mword 5) (add_vec_int w__1 8))
+    : M (unit).
+
+Definition execute_J (offset : mword 26) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 =>
+   (execute_branch
+      (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28)
+         (concat_vec offset (vec_of_bits [B0;B0]  : mword 2))))
+    : M (unit).
+
+Definition execute_HCF (g__18 : unit)  : unit := tt.
+
+Definition execute_ERET (g__23 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   let '_ := (ERETHook tt)  : unit in
+   write_reg CP0LLBit_ref (vec_of_bits [B0]  : mword 1) >>
+   read_reg CP0Status_ref >>= fun w__0 =>
+   (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0))  : bool) ((bit_to_bool B1)  : bool)))
+    then
+      (read_reg CP0ErrorEPC_ref  : M (mword 64)) >>= fun w__1 =>
+      write_reg nextPC_ref w__1 >>
+      (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0]  : mword 1))
+       : M (unit)
+    else
+      (read_reg CP0EPC_ref  : M (mword 64)) >>= fun w__2 =>
+      write_reg nextPC_ref w__2 >>
+      (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0]  : mword 1))
+       : M (unit))
+    : M (unit).
+
+Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (sub_vec w__0 w__1))  : M (unit).
+
+Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in
+   (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64))  : bool)
+           ((bit_to_bool (access_vec_dec temp65 63))
+            : bool))) then
+      (SignalException Ov)
+       : M (unit)
+    else (wGPR rd (subrange_vec_dec temp65 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 5 0 in
+   shift_bits_right temp sa >>= fun w__1 => (wGPR rd w__1)  : M (unit).
+
+Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   let sa32 := concat_vec (vec_of_bits [B1]  : mword 1) sa in
+   shift_bits_right temp sa32 >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp => shift_bits_right temp sa >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 5 0 in
+   shift_bits_right_arith temp sa >>= fun w__1 => (wGPR rd w__1)  : M (unit).
+
+Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   let sa32 := concat_vec (vec_of_bits [B1]  : mword 1) sa in
+   shift_bits_right_arith temp sa32 >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp => shift_bits_right_arith temp sa >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   rGPR rs >>= fun w__1 =>
+   shift_bits_left w__0 (subrange_vec_dec w__1 5 0) >>= fun w__2 => (wGPR rd w__2)  : M (unit).
+
+Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   shift_bits_left w__0 (concat_vec (vec_of_bits [B1]  : mword 1) sa) >>= fun w__1 =>
+   (wGPR rd w__1)
+    : M (unit).
+
+Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 => shift_bits_left w__0 sa >>= fun w__1 => (wGPR rd w__1)  : M (unit).
+
+Definition execute_DMULTU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let result := mult_vec w__0 w__1 in
+   write_reg HI_ref (subrange_vec_dec result 127 64) >>
+   write_reg LO_ref (subrange_vec_dec result 63 0)
+    : M (unit).
+
+Definition execute_DMULT (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let result := mults_vec w__0 w__1 in
+   write_reg HI_ref (subrange_vec_dec result 127 64) >>
+   write_reg LO_ref (subrange_vec_dec result 63 0)
+    : M (unit).
+
+Definition execute_DIVU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal)
+           (orb (NotWordVal rtVal)
+              (eq_vec rtVal
+                 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0]
+                   : mword 64))))) then
+      undefined_bitvector 32 >>= fun w__0 =>
+      undefined_bitvector 32 >>= fun w__1 =>
+      returnm ((w__0  : bits 32, w__1  : bits 32)
+       : (bits 32 * bits 32))
+    else
+      let '(existT _ si _) := uint (subrange_vec_dec rsVal 31 0) in
+      let '(existT _ ti _) := uint (subrange_vec_dec rtVal 31 0) in
+      let qi := Z.quot si ti in
+      let ri := Z.rem si ti in
+      returnm ((to_bits 32 qi, to_bits 32 ri)
+       : (mword 32 * mword 32))) >>= fun '(q, r) =>
+   write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q)  : M (unit).
+
+Definition execute_DIV (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal)
+           (orb (NotWordVal rtVal)
+              (eq_vec rtVal
+                 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0]
+                   : mword 64))))) then
+      undefined_bitvector 32 >>= fun w__0 =>
+      undefined_bitvector 32 >>= fun w__1 =>
+      returnm ((w__0  : bits 32, w__1  : bits 32)
+       : (bits 32 * bits 32))
+    else
+      let '(existT _ si _) := sint (subrange_vec_dec rsVal 31 0) in
+      let '(existT _ ti _) := sint (subrange_vec_dec rtVal 31 0) in
+      let qi := Z.quot si ti in
+      let ri := Z.sub si (Z.mul ti qi) in
+      returnm ((to_bits 32 qi, to_bits 32 ri)
+       : (mword 32 * mword 32))) >>= fun '(q, r) =>
+   write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q)  : M (unit).
+
+Definition execute_DDIVU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let '(existT _ rsVal _) := uint w__0 in
+   rGPR rt >>= fun w__1 =>
+   let '(existT _ rtVal _) := uint w__1 in
+   (if ((eq_range (build_ex rtVal) (build_ex 0))) then
+      undefined_bitvector 64 >>= fun w__2 =>
+      undefined_bitvector 64 >>= fun w__3 =>
+      returnm ((w__2  : bits 64, w__3  : bits 64)
+       : (bits 64 * bits 64))
+    else
+      let qi := Z.quot rsVal rtVal in
+      let ri := Z.rem rsVal rtVal in
+      returnm ((to_bits 64 qi, to_bits 64 ri)
+       : (mword 64 * mword 64))) >>= fun '(q, r) =>
+   write_reg LO_ref q >> write_reg HI_ref r  : M (unit).
+
+Definition execute_DDIV (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let '(existT _ rsVal _) := sint w__0 in
+   rGPR rt >>= fun w__1 =>
+   let '(existT _ rtVal _) := sint w__1 in
+   (if ((eq_range (build_ex rtVal) (build_ex 0))) then
+      undefined_bitvector 64 >>= fun w__2 =>
+      undefined_bitvector 64 >>= fun w__3 =>
+      returnm ((w__2  : bits 64, w__3  : bits 64)
+       : (bits 64 * bits 64))
+    else
+      let qi := Z.quot rsVal rtVal in
+      let ri := Z.sub rsVal (Z.mul qi rtVal) in
+      returnm ((to_bits 64 qi, to_bits 64 ri)
+       : (mword 64 * mword 64))) >>= fun '(q, r) =>
+   write_reg LO_ref q >> write_reg HI_ref r  : M (unit).
+
+Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (add_vec w__0 w__1))  : M (unit).
+
+Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm)))  : M (unit).
+
+Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in
+   (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64))  : bool)
+           ((bit_to_bool (access_vec_dec sum65 63))
+            : bool))) then
+      (SignalException Ov)
+       : M (unit)
+    else (wGPR rt (subrange_vec_dec sum65 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in
+   (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64))  : bool)
+           ((bit_to_bool (access_vec_dec sum65 63))
+            : bool))) then
+      (SignalException Ov)
+       : M (unit)
+    else (wGPR rd (subrange_vec_dec sum65 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) 
+: M (unit) :=
+   (checkCP0Access tt)
+    : M (unit).
+
+Definition execute_BREAK (g__15 : unit)  : M (unit) := (SignalException Bp)  : M (unit).
+
+Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rd >>= fun w__1 =>
+   (if (((bits_to_bool
+            (xor_vec ((bool_to_bits (eq_vec w__0 w__1))  : mword 1) ((bool_to_bits ne)  : mword 1)))
+       : bool)) then
+      let offset : bits 64 :=
+        add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0]  : mword 2))) 4 in
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__2 =>
+      (execute_branch (add_vec w__2 offset))
+       : M (unit)
+    else if (likely) then
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__3 =>
+      write_reg nextPC_ref (add_vec_int w__3 8)
+       : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_BCMPZ (rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 =>
+   let linkVal := add_vec_int w__0 8 in
+   rGPR rs >>= fun regVal =>
+   let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0]  : mword 1)) in
+   (if (condition) then
+      let offset : bits 64 :=
+        add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0]  : mword 2))) 4 in
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__1 =>
+      (execute_branch (add_vec w__1 offset))
+       : M (unit)
+    else if (likely) then
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__2 =>
+      write_reg nextPC_ref (add_vec_int w__2 8)
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1]  : mword 5) linkVal)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm)))  : M (unit).
+
+Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (and_vec w__0 w__1))  : M (unit).
+
+Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      (wGPR rd
+         (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0))))
+       : M (unit))
+    : M (unit).
+
+Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0)  : M (unit)
+    else
+      (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm))))
+       : M (unit))
+    : M (unit).
+
+Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0)  : M (unit)
+    else
+      let sum33 : bits 33 :=
+        add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in
+      (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32))  : bool)
+              ((bit_to_bool (access_vec_dec sum33 31))
+               : bool))) then
+         (SignalException Ov)
+          : M (unit)
+       else (wGPR rt (mips_sign_extend 64 (subrange_vec_dec sum33 31 0)))  : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let sum33 : bits 33 :=
+        add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0))
+          (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in
+      (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32))  : bool)
+              ((bit_to_bool (access_vec_dec sum33 31))
+               : bool))) then
+         (SignalException Ov)
+          : M (unit)
+       else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec sum33 31 0)))  : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute (merge_var : ast) 
+: M (unit) :=
+   match merge_var with
+   | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm)  : M (unit)
+   | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd)  : M (unit)
+   | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm)  : M (unit)
+   | DADD (rs,rt,rd) => (execute_DADD rs rt rd)  : M (unit)
+   | ADD (rs,rt,rd) => (execute_ADD rs rt rd)  : M (unit)
+   | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm)  : M (unit)
+   | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd)  : M (unit)
+   | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm)  : M (unit)
+   | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd)  : M (unit)
+   | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd)  : M (unit)
+   | SUB (rs,rt,rd) => (execute_SUB rs rt rd)  : M (unit)
+   | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd)  : M (unit)
+   | AND (rs,rt,rd) => (execute_AND rs rt rd)  : M (unit)
+   | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm)  : M (unit)
+   | OR (rs,rt,rd) => (execute_OR rs rt rd)  : M (unit)
+   | ORI (rs,rt,imm) => (execute_ORI rs rt imm)  : M (unit)
+   | NOR (rs,rt,rd) => (execute_NOR rs rt rd)  : M (unit)
+   | XOR (rs,rt,rd) => (execute_XOR rs rt rd)  : M (unit)
+   | XORI (rs,rt,imm) => (execute_XORI rs rt imm)  : M (unit)
+   | LUI (rt,imm) => (execute_LUI rt imm)  : M (unit)
+   | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa)  : M (unit)
+   | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa)  : M (unit)
+   | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd)  : M (unit)
+   | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa)  : M (unit)
+   | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa)  : M (unit)
+   | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd)  : M (unit)
+   | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa)  : M (unit)
+   | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa)  : M (unit)
+   | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd)  : M (unit)
+   | SLL (rt,rd,sa) => (execute_SLL rt rd sa)  : M (unit)
+   | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd)  : M (unit)
+   | SRA (rt,rd,sa) => (execute_SRA rt rd sa)  : M (unit)
+   | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd)  : M (unit)
+   | SRL (rt,rd,sa) => (execute_SRL rt rd sa)  : M (unit)
+   | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd)  : M (unit)
+   | SLT (rs,rt,rd) => (execute_SLT rs rt rd)  : M (unit)
+   | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm)  : M (unit)
+   | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd)  : M (unit)
+   | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm)  : M (unit)
+   | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd)  : M (unit)
+   | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd)  : M (unit)
+   | MFHI (rd) => (execute_MFHI rd)  : M (unit)
+   | MFLO (rd) => (execute_MFLO rd)  : M (unit)
+   | MTHI (rs) => (execute_MTHI rs)  : M (unit)
+   | MTLO (rs) => (execute_MTLO rs)  : M (unit)
+   | MUL (rs,rt,rd) => (execute_MUL rs rt rd)  : M (unit)
+   | MULT (rs,rt) => (execute_MULT rs rt)  : M (unit)
+   | MULTU (rs,rt) => (execute_MULTU rs rt)  : M (unit)
+   | DMULT (rs,rt) => (execute_DMULT rs rt)  : M (unit)
+   | DMULTU (rs,rt) => (execute_DMULTU rs rt)  : M (unit)
+   | MADD (rs,rt) => (execute_MADD rs rt)  : M (unit)
+   | MADDU (rs,rt) => (execute_MADDU rs rt)  : M (unit)
+   | MSUB (rs,rt) => (execute_MSUB rs rt)  : M (unit)
+   | MSUBU (rs,rt) => (execute_MSUBU rs rt)  : M (unit)
+   | DIV (rs,rt) => (execute_DIV rs rt)  : M (unit)
+   | DIVU (rs,rt) => (execute_DIVU rs rt)  : M (unit)
+   | DDIV (rs,rt) => (execute_DDIV rs rt)  : M (unit)
+   | DDIVU (rs,rt) => (execute_DDIVU rs rt)  : M (unit)
+   | J (offset) => (execute_J offset)  : M (unit)
+   | JAL (offset) => (execute_JAL offset)  : M (unit)
+   | JR (rs) => (execute_JR rs)  : M (unit)
+   | JALR (rs,rd) => (execute_JALR rs rd)  : M (unit)
+   | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely)  : M (unit)
+   | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely)  : M (unit)
+   | SYSCALL (g__14) => (execute_SYSCALL g__14)  : M (unit)
+   | BREAK (g__15) => (execute_BREAK g__15)  : M (unit)
+   | WAIT (g__16) => (execute_WAIT g__16)  : M (unit)
+   | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp)  : M (unit)
+   | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp)  : M (unit)
+   | Load (width,sign,linked,base,rt,offset) =>
+      (execute_Load width sign linked base rt offset)  : M (unit)
+   | Store (width,conditional,base,rt,offset) =>
+      (execute_Store width conditional base rt offset)  : M (unit)
+   | LWL (base,rt,offset) => (execute_LWL base rt offset)  : M (unit)
+   | LWR (base,rt,offset) => (execute_LWR base rt offset)  : M (unit)
+   | SWL (base,rt,offset) => (execute_SWL base rt offset)  : M (unit)
+   | SWR (base,rt,offset) => (execute_SWR base rt offset)  : M (unit)
+   | LDL (base,rt,offset) => (execute_LDL base rt offset)  : M (unit)
+   | LDR (base,rt,offset) => (execute_LDR base rt offset)  : M (unit)
+   | SDL (base,rt,offset) => (execute_SDL base rt offset)  : M (unit)
+   | SDR (base,rt,offset) => (execute_SDR base rt offset)  : M (unit)
+   | CACHE (base,op,imm) => (execute_CACHE base op imm)  : M (unit)
+   | SYNC (g__17) => (execute_SYNC g__17)  : M (unit)
+   | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double)  : M (unit)
+   | HCF (g__18) => returnm ((execute_HCF g__18)  : unit)
+   | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double)  : M (unit)
+   | TLBWI (g__19) => (execute_TLBWI g__19)  : M (unit)
+   | TLBWR (g__20) => (execute_TLBWR g__20)  : M (unit)
+   | TLBR (g__21) => (execute_TLBR g__21)  : M (unit)
+   | TLBP (g__22) => (execute_TLBP g__22)  : M (unit)
+   | RDHWR (rt,rd) => (execute_RDHWR rt rd)  : M (unit)
+   | ERET (g__23) => (execute_ERET g__23)  : M (unit)
+   | RI (g__24) => (execute_RI g__24)  : M (unit)
+   end.
+
+Definition supported_instructions (instr : ast)  : option ast := Some instr.
+
+Definition initialize_registers '(tt : unit) 
+: M (unit) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   write_reg PC_ref w__0 >>
+   undefined_bitvector 64 >>= fun w__1 =>
+   write_reg nextPC_ref w__1 >>
+   undefined_bitvector 1 >>= fun w__2 =>
+   write_reg TLBProbe_ref w__2 >>
+   undefined_bitvector 6 >>= fun w__3 =>
+   write_reg TLBIndex_ref w__3 >>
+   undefined_bitvector 6 >>= fun w__4 =>
+   write_reg TLBRandom_ref w__4 >>
+   undefined_TLBEntryLoReg tt >>= fun w__5 =>
+   write_reg TLBEntryLo0_ref w__5 >>
+   undefined_TLBEntryLoReg tt >>= fun w__6 =>
+   write_reg TLBEntryLo1_ref w__6 >>
+   undefined_ContextReg tt >>= fun w__7 =>
+   write_reg TLBContext_ref w__7 >>
+   undefined_bitvector 16 >>= fun w__8 =>
+   write_reg TLBPageMask_ref w__8 >>
+   undefined_bitvector 6 >>= fun w__9 =>
+   write_reg TLBWired_ref w__9 >>
+   undefined_TLBEntryHiReg tt >>= fun w__10 =>
+   write_reg TLBEntryHi_ref w__10 >>
+   undefined_XContextReg tt >>= fun w__11 =>
+   write_reg TLBXContext_ref w__11 >>
+   undefined_TLBEntry tt >>= fun w__12 =>
+   write_reg TLBEntry00_ref w__12 >>
+   undefined_TLBEntry tt >>= fun w__13 =>
+   write_reg TLBEntry01_ref w__13 >>
+   undefined_TLBEntry tt >>= fun w__14 =>
+   write_reg TLBEntry02_ref w__14 >>
+   undefined_TLBEntry tt >>= fun w__15 =>
+   write_reg TLBEntry03_ref w__15 >>
+   undefined_TLBEntry tt >>= fun w__16 =>
+   write_reg TLBEntry04_ref w__16 >>
+   undefined_TLBEntry tt >>= fun w__17 =>
+   write_reg TLBEntry05_ref w__17 >>
+   undefined_TLBEntry tt >>= fun w__18 =>
+   write_reg TLBEntry06_ref w__18 >>
+   undefined_TLBEntry tt >>= fun w__19 =>
+   write_reg TLBEntry07_ref w__19 >>
+   undefined_TLBEntry tt >>= fun w__20 =>
+   write_reg TLBEntry08_ref w__20 >>
+   undefined_TLBEntry tt >>= fun w__21 =>
+   write_reg TLBEntry09_ref w__21 >>
+   undefined_TLBEntry tt >>= fun w__22 =>
+   write_reg TLBEntry10_ref w__22 >>
+   undefined_TLBEntry tt >>= fun w__23 =>
+   write_reg TLBEntry11_ref w__23 >>
+   undefined_TLBEntry tt >>= fun w__24 =>
+   write_reg TLBEntry12_ref w__24 >>
+   undefined_TLBEntry tt >>= fun w__25 =>
+   write_reg TLBEntry13_ref w__25 >>
+   undefined_TLBEntry tt >>= fun w__26 =>
+   write_reg TLBEntry14_ref w__26 >>
+   undefined_TLBEntry tt >>= fun w__27 =>
+   write_reg TLBEntry15_ref w__27 >>
+   undefined_TLBEntry tt >>= fun w__28 =>
+   write_reg TLBEntry16_ref w__28 >>
+   undefined_TLBEntry tt >>= fun w__29 =>
+   write_reg TLBEntry17_ref w__29 >>
+   undefined_TLBEntry tt >>= fun w__30 =>
+   write_reg TLBEntry18_ref w__30 >>
+   undefined_TLBEntry tt >>= fun w__31 =>
+   write_reg TLBEntry19_ref w__31 >>
+   undefined_TLBEntry tt >>= fun w__32 =>
+   write_reg TLBEntry20_ref w__32 >>
+   undefined_TLBEntry tt >>= fun w__33 =>
+   write_reg TLBEntry21_ref w__33 >>
+   undefined_TLBEntry tt >>= fun w__34 =>
+   write_reg TLBEntry22_ref w__34 >>
+   undefined_TLBEntry tt >>= fun w__35 =>
+   write_reg TLBEntry23_ref w__35 >>
+   undefined_TLBEntry tt >>= fun w__36 =>
+   write_reg TLBEntry24_ref w__36 >>
+   undefined_TLBEntry tt >>= fun w__37 =>
+   write_reg TLBEntry25_ref w__37 >>
+   undefined_TLBEntry tt >>= fun w__38 =>
+   write_reg TLBEntry26_ref w__38 >>
+   undefined_TLBEntry tt >>= fun w__39 =>
+   write_reg TLBEntry27_ref w__39 >>
+   undefined_TLBEntry tt >>= fun w__40 =>
+   write_reg TLBEntry28_ref w__40 >>
+   undefined_TLBEntry tt >>= fun w__41 =>
+   write_reg TLBEntry29_ref w__41 >>
+   undefined_TLBEntry tt >>= fun w__42 =>
+   write_reg TLBEntry30_ref w__42 >>
+   undefined_TLBEntry tt >>= fun w__43 =>
+   write_reg TLBEntry31_ref w__43 >>
+   undefined_TLBEntry tt >>= fun w__44 =>
+   write_reg TLBEntry32_ref w__44 >>
+   undefined_TLBEntry tt >>= fun w__45 =>
+   write_reg TLBEntry33_ref w__45 >>
+   undefined_TLBEntry tt >>= fun w__46 =>
+   write_reg TLBEntry34_ref w__46 >>
+   undefined_TLBEntry tt >>= fun w__47 =>
+   write_reg TLBEntry35_ref w__47 >>
+   undefined_TLBEntry tt >>= fun w__48 =>
+   write_reg TLBEntry36_ref w__48 >>
+   undefined_TLBEntry tt >>= fun w__49 =>
+   write_reg TLBEntry37_ref w__49 >>
+   undefined_TLBEntry tt >>= fun w__50 =>
+   write_reg TLBEntry38_ref w__50 >>
+   undefined_TLBEntry tt >>= fun w__51 =>
+   write_reg TLBEntry39_ref w__51 >>
+   undefined_TLBEntry tt >>= fun w__52 =>
+   write_reg TLBEntry40_ref w__52 >>
+   undefined_TLBEntry tt >>= fun w__53 =>
+   write_reg TLBEntry41_ref w__53 >>
+   undefined_TLBEntry tt >>= fun w__54 =>
+   write_reg TLBEntry42_ref w__54 >>
+   undefined_TLBEntry tt >>= fun w__55 =>
+   write_reg TLBEntry43_ref w__55 >>
+   undefined_TLBEntry tt >>= fun w__56 =>
+   write_reg TLBEntry44_ref w__56 >>
+   undefined_TLBEntry tt >>= fun w__57 =>
+   write_reg TLBEntry45_ref w__57 >>
+   undefined_TLBEntry tt >>= fun w__58 =>
+   write_reg TLBEntry46_ref w__58 >>
+   undefined_TLBEntry tt >>= fun w__59 =>
+   write_reg TLBEntry47_ref w__59 >>
+   undefined_TLBEntry tt >>= fun w__60 =>
+   write_reg TLBEntry48_ref w__60 >>
+   undefined_TLBEntry tt >>= fun w__61 =>
+   write_reg TLBEntry49_ref w__61 >>
+   undefined_TLBEntry tt >>= fun w__62 =>
+   write_reg TLBEntry50_ref w__62 >>
+   undefined_TLBEntry tt >>= fun w__63 =>
+   write_reg TLBEntry51_ref w__63 >>
+   undefined_TLBEntry tt >>= fun w__64 =>
+   write_reg TLBEntry52_ref w__64 >>
+   undefined_TLBEntry tt >>= fun w__65 =>
+   write_reg TLBEntry53_ref w__65 >>
+   undefined_TLBEntry tt >>= fun w__66 =>
+   write_reg TLBEntry54_ref w__66 >>
+   undefined_TLBEntry tt >>= fun w__67 =>
+   write_reg TLBEntry55_ref w__67 >>
+   undefined_TLBEntry tt >>= fun w__68 =>
+   write_reg TLBEntry56_ref w__68 >>
+   undefined_TLBEntry tt >>= fun w__69 =>
+   write_reg TLBEntry57_ref w__69 >>
+   undefined_TLBEntry tt >>= fun w__70 =>
+   write_reg TLBEntry58_ref w__70 >>
+   undefined_TLBEntry tt >>= fun w__71 =>
+   write_reg TLBEntry59_ref w__71 >>
+   undefined_TLBEntry tt >>= fun w__72 =>
+   write_reg TLBEntry60_ref w__72 >>
+   undefined_TLBEntry tt >>= fun w__73 =>
+   write_reg TLBEntry61_ref w__73 >>
+   undefined_TLBEntry tt >>= fun w__74 =>
+   write_reg TLBEntry62_ref w__74 >>
+   undefined_TLBEntry tt >>= fun w__75 =>
+   write_reg TLBEntry63_ref w__75 >>
+   undefined_bitvector 32 >>= fun w__76 =>
+   write_reg CP0Compare_ref w__76 >>
+   undefined_CauseReg tt >>= fun w__77 =>
+   write_reg CP0Cause_ref w__77 >>
+   undefined_bitvector 64 >>= fun w__78 =>
+   write_reg CP0EPC_ref w__78 >>
+   undefined_bitvector 64 >>= fun w__79 =>
+   write_reg CP0ErrorEPC_ref w__79 >>
+   undefined_bitvector 1 >>= fun w__80 =>
+   write_reg CP0LLBit_ref w__80 >>
+   undefined_bitvector 64 >>= fun w__81 =>
+   write_reg CP0LLAddr_ref w__81 >>
+   undefined_bitvector 64 >>= fun w__82 =>
+   write_reg CP0BadVAddr_ref w__82 >>
+   undefined_bitvector 32 >>= fun w__83 =>
+   write_reg CP0Count_ref w__83 >>
+   undefined_bitvector 32 >>= fun w__84 =>
+   write_reg CP0HWREna_ref w__84 >>
+   undefined_bitvector 64 >>= fun w__85 =>
+   write_reg CP0UserLocal_ref w__85 >>
+   undefined_bitvector 3 >>= fun w__86 =>
+   write_reg CP0ConfigK0_ref w__86 >>
+   undefined_StatusReg tt >>= fun w__87 =>
+   write_reg CP0Status_ref w__87 >>
+   undefined_bitvector 1 >>= fun w__88 =>
+   write_reg branchPending_ref w__88 >>
+   undefined_bitvector 1 >>= fun w__89 =>
+   write_reg inBranchDelay_ref w__89 >>
+   undefined_bitvector 64 >>= fun w__90 =>
+   write_reg delayedPC_ref w__90 >>
+   undefined_bitvector 64 >>= fun w__91 =>
+   write_reg HI_ref w__91 >>
+   undefined_bitvector 64 >>= fun w__92 =>
+   write_reg LO_ref w__92 >>
+   undefined_bitvector 64 >>= fun w__93 =>
+   undefined_vector 32 w__93 >>= fun w__94 =>
+   write_reg GPR_ref w__94 >>
+   undefined_bitvector 8 >>= fun w__95 =>
+   write_reg UART_WDATA_ref w__95 >>
+   undefined_bitvector 1 >>= fun w__96 =>
+   write_reg UART_WRITTEN_ref w__96 >>
+   undefined_bitvector 8 >>= fun w__97 =>
+   write_reg UART_RDATA_ref w__97 >>
+   undefined_bitvector 1 >>= fun w__98 => write_reg UART_RVALID_ref w__98  : M (unit).
+
+Definition initial_regstate : regstate :=
+{| UART_RVALID := (vec_of_bits [B0]  : mword 1); 
+   UART_RDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8); 
+   UART_WRITTEN := (vec_of_bits [B0]  : mword 1); 
+   UART_WDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8); 
+   GPR :=
+     (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0]
+                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0]
+                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0]
+                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0]
+                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0]
+                                                                                 : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0]
+                                                                                               : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0]
+                                                                                                             : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0]
+                                                                                                                           : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0]
+                                                                                                                                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0]
+                                                                                                                                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0]
+                                                                                                                                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                               B0]
+                                                                                                                                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                             B0]
+                                                                                                                                                                                                 : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                           B0]
+                                                                                                                                                                                                               : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                         B0]
+                                                                                                                                                                                                                             : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                       B0]
+                                                                                                                                                                                                                                           : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                     B0]
+                                                                                                                                                                                                                                                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                   B0]
+                                                                                                                                                                                                                                                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                 B0]
+                                                                                                                                                                                                                                                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                               B0]
+                                                                                                                                                                                                                                                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                                             B0]
+                                                                                                                                                                                                                                                                                                                 : mword 64);
+                       (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0]
+                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0]
+                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0]
+                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0]
+                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0]
+                                                                                 : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0]
+                                                                                               : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0]
+                                                                                                             : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0]
+                                                                                                                           : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0]
+                                                                                                                                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0]
+                                                                                                                                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0]
+                                                                                                                                                                     : mword 64)]); 
+   LO :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   HI :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   delayedPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   inBranchDelay := (vec_of_bits [B0]  : mword 1); 
+   branchPending := (vec_of_bits [B0]  : mword 1); 
+   CP0Status :=
+     ({| StatusReg_StatusReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 32) |}); 
+   CP0ConfigK0 := (vec_of_bits [B0;B0;B0]  : mword 3); 
+   CP0UserLocal :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0HWREna :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       : mword 32); 
+   CP0Count :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       : mword 32); 
+   CP0BadVAddr :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0LLAddr :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0LLBit := (vec_of_bits [B0]  : mword 1); 
+   CP0ErrorEPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0EPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0Cause :=
+     ({| CauseReg_CauseReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 32) |}); 
+   CP0Compare :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       : mword 32); 
+   TLBEntry63 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry62 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry61 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry60 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry59 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry58 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry57 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry56 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry55 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry54 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry53 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry52 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry51 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry50 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry49 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry48 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry47 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry46 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry45 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry44 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry43 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry42 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry41 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry40 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry39 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry38 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry37 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry36 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry35 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry34 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry33 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry32 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry31 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry30 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry29 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry28 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry27 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry26 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry25 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry24 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry23 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry22 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry21 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry20 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry19 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry18 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry17 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry16 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry15 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry14 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry13 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry12 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry11 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry10 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry09 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry08 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry07 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry06 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry05 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry04 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry03 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry02 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry01 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry00 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBXContext :=
+     ({| XContextReg_XContextReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntryHi :=
+     ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBWired := (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6); 
+   TLBPageMask := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16); 
+   TLBContext :=
+     ({| ContextReg_ContextReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntryLo1 :=
+     ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntryLo0 :=
+     ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6); 
+   TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6); 
+   TLBProbe := (vec_of_bits [B0]  : mword 1); 
+   nextPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   PC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64) |}.
+
+
+End Content.
diff --git a/snapshots/coq/mips/mips_extras.v b/snapshots/coq/mips/mips_extras.v
new file mode 100644
index 00000000..cc905f11
--- /dev/null
+++ b/snapshots/coq/mips/mips_extras.v
@@ -0,0 +1,162 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import String.
+Require Import List.
+Import List.ListNotations.
+(*
+val MEMr             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e
+val MEMr_reserve     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e
+val MEMr_tag         : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e
+val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e
+*)
+Definition MEMr {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size            : monad regval (mword b) e := read_mem Read_plain addr size.
+Definition MEMr_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size    : monad regval (mword b) e := read_mem Read_reserve addr size.
+
+(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*)
+Definition read_tag_bool {regval a e} (addr : mword a) : monad regval bool e :=
+  read_tag addr >>= fun t =>
+  maybe_fail "read_tag_bool" (bool_of_bitU t).
+
+(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*)
+Definition write_tag_bool {regval a e} (addr : mword a) t : monad regval unit e :=
+ write_tag addr (bitU_of_bool t) >>= fun _ => returnm tt.
+
+Definition MEMr_tag {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e :=
+  read_mem Read_plain addr size >>= fun v =>
+  read_tag_bool addr >>= fun t =>
+  returnm (t, v).
+
+Definition MEMr_tag_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e :=
+  read_mem Read_plain addr size >>= fun v =>
+  read_tag_bool addr >>= fun t =>
+  returnm (t, v).
+
+(*
+val MEMea                 : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+val MEMea_conditional     : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+val MEMea_tag             : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+*)
+Definition MEMea {regval a e} (addr : mword a) size                : monad regval unit e := write_mem_ea Write_plain addr size.
+Definition MEMea_conditional {regval a e} (addr : mword a) size    : monad regval unit e := write_mem_ea Write_conditional addr size.
+
+Definition MEMea_tag {regval a e} (addr : mword a) size            : monad regval unit e := write_mem_ea Write_plain addr size.
+Definition MEMea_tag_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size.
+
+(*
+val MEMval                 : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e
+val MEMval_conditional     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e
+val MEMval_tag             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e
+val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e
+*)
+Definition MEMval {regval a b e} (_ : mword a) (size : Z) (v : mword b)                      : monad regval unit e := write_mem_val v >>= fun _ => returnm tt.
+Definition MEMval_conditional {regval a b e} (_ : mword a) (size : Z) (v : mword b)          : monad regval bool e := write_mem_val v >>= fun b => returnm (if b then true else false).
+Definition MEMval_tag {regval a b e} (addr : mword a) (size : Z) t (v : mword b)             : monad regval unit e := write_mem_val v >>= fun _ => write_tag_bool addr t >>= fun _ => returnm tt.
+Definition MEMval_tag_conditional {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => write_tag_bool addr t >>= fun _ => returnm (if b then true else false).
+
+(*val MEM_sync  : forall 'regval 'e. unit -> monad 'regval unit 'e*)
+
+Definition MEM_sync {regval e} (_:unit) : monad regval unit e := barrier Barrier_MIPS_SYNC.
+
+(* Some wrappers copied from aarch64_extras *)
+(* TODO: Harmonise into a common library *)
+(*
+Definition get_slice_int_bl len n lo :=
+  (* TODO: Is this the intended behaviour? *)
+  let hi := lo + len - 1 in
+  let bs := bools_of_int (hi + 1) n in
+  subrange_list false bs hi lo
+
+val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a
+Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo)
+*)
+Definition write_ram {rv e} m size (_ : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv unit e :=
+  MEMea addr size >>
+  MEMval addr size data.
+
+Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := MEMr addr size.
+(*
+Definition string_of_bits bs := string_of_bv (bits_of bs).
+Definition string_of_int := show
+
+Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits))
+Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits))
+*)
+Definition shift_bits_left {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e :=
+  maybe_fail "shift_bits_left" (unsigned n) >>= fun n =>
+  returnm (shiftl v n).
+
+Definition shift_bits_right {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e :=
+  maybe_fail "shift_bits_right" (unsigned n) >>= fun n =>
+  returnm (shiftr v n).
+
+Definition shift_bits_right_arith {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e :=
+  maybe_fail "shift_bits_right" (unsigned n) >>= fun n =>
+  returnm (arith_shiftr v n).
+
+(* Use constants for undefined values for now *)
+Definition internal_pick {rv a e} (vs : list a) : monad rv a e :=
+match vs with
+| (h::_) => returnm h
+| _ => Fail "empty list in internal_pick"
+end.
+Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string.
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len).
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bits {rv e} := @undefined_bitvector rv e.
+Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU.
+(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*)
+Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i).
+Definition undefined_atom {rv e} i : monad rv Z e := returnm i.
+Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+
+Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt.
+
+(*val elf_entry : unit -> integer*)
+Definition elf_entry (_:unit) : Z := 0.
+(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*)
+
+(*Definition print_bits msg bs := prerr_endline (msg ^ (string_of_bits bs))
+
+val get_time_ns : unit -> integer*)
+Definition get_time_ns (_:unit) : Z := 0.
+(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*)
+
+Definition eq_bit (x : bitU) (y : bitU) : bool :=
+  match x, y with
+  | B0, B0 => true
+  | B1, B1 => true
+  | BU, BU => true
+  | _,_ => false
+  end.
+
+Require Import Zeuclid.
+Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
+refine (build_ex (ZEuclid.modulo m n)).
+constructor.
+destruct H.
+assert (Zabs n = n). { rewrite Zabs_eq; auto with zarith. }
+rewrite <- H at 3.
+lapply (ZEuclid.mod_always_pos m n); omega.
+Qed.
+
+(* Override the more general version *)
+
+Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
+Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r.
+
+
+Definition print_endline (_:string) : unit := tt.
+Definition prerr_endline (_:string) : unit := tt.
+Definition prerr_string (_:string) : unit := tt.
+Definition putchar {T} (_:T) : unit := tt.
+Require DecimalString.
+Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z).
diff --git a/snapshots/coq/mips/mips_types.v b/snapshots/coq/mips/mips_types.v
new file mode 100644
index 00000000..12d7d6cd
--- /dev/null
+++ b/snapshots/coq/mips/mips_types.v
@@ -0,0 +1,1441 @@
+(*Generated by Sail from mips.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Definition bits (n : Z) : Type := mword n.
+
+
+
+Inductive exception  :=
+  ISAException : unit -> exception
+  | Error_not_implemented : string -> exception
+  | Error_misaligned_access : unit -> exception
+  | Error_EBREAK : unit -> exception
+  | Error_internal_error : unit -> exception.
+Arguments exception : clear implicits.
+
+
+
+Record CauseReg  := { CauseReg_CauseReg_chunk_0 : mword 32; }.
+Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}).
+
+Record StatusReg  := { StatusReg_StatusReg_chunk_0 : mword 32; }.
+Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}).
+
+Record TLBEntryLoReg  := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}).
+
+Record TLBEntryHiReg  := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}).
+
+Record ContextReg  := { ContextReg_ContextReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}).
+
+Record XContextReg  := { XContextReg_XContextReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}).
+
+Definition TLBIndexT  : Type := bits 6.
+
+Record TLBEntry  := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}).
+Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}).
+
+Inductive Exception :=
+  Interrupt
+  | TLBMod
+  | TLBL
+  | TLBS
+  | AdEL
+  | AdES
+  | Sys
+  | Bp
+  | ResI
+  | CpU
+  | Ov
+  | Tr
+  | C2E
+  | C2Trap
+  | XTLBRefillL
+  | XTLBRefillS
+  | XTLBInvL
+  | XTLBInvS
+  | MCheck.
+Scheme Equality for Exception.
+Instance Decidable_eq_Exception : forall (x y : Exception), Decidable (x = y) :=
+Decidable_eq_from_dec Exception_eq_dec.
+
+
+Inductive MemAccessType := Instruction | LoadData | StoreData.
+Scheme Equality for MemAccessType.
+Instance Decidable_eq_MemAccessType : forall (x y : MemAccessType), Decidable (x = y) :=
+Decidable_eq_from_dec MemAccessType_eq_dec.
+
+
+Inductive AccessLevel := User | Supervisor | Kernel.
+Scheme Equality for AccessLevel.
+Instance Decidable_eq_AccessLevel : forall (x y : AccessLevel), Decidable (x = y) :=
+Decidable_eq_from_dec AccessLevel_eq_dec.
+
+
+Definition regno  : Type := bits 5.
+
+Definition imm16  : Type := bits 16.
+
+Definition regregreg  : Type := (regno * regno * regno).
+
+Definition regregimm16  : Type := (regno * regno * imm16).
+
+Inductive decode_failure :=
+  no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error.
+Scheme Equality for decode_failure.
+Instance Decidable_eq_decode_failure : forall (x y : decode_failure), Decidable (x = y) :=
+Decidable_eq_from_dec decode_failure_eq_dec.
+
+
+Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU.
+Scheme Equality for Comparison.
+Instance Decidable_eq_Comparison : forall (x y : Comparison), Decidable (x = y) :=
+Decidable_eq_from_dec Comparison_eq_dec.
+
+
+Inductive WordType := B | H | W | D.
+Scheme Equality for WordType.
+Instance Decidable_eq_WordType : forall (x y : WordType), Decidable (x = y) :=
+Decidable_eq_from_dec WordType_eq_dec.
+
+
+Inductive WordTypeUnaligned := WL | WR | DL | DR.
+Scheme Equality for WordTypeUnaligned.
+Instance Decidable_eq_WordTypeUnaligned : forall (x y : WordTypeUnaligned), Decidable (x = y) :=
+Decidable_eq_from_dec WordTypeUnaligned_eq_dec.
+
+
+Inductive ast  :=
+  DADDIU : (regno * regno * imm16) -> ast
+  | DADDU : (regno * regno * regno) -> ast
+  | DADDI : (regno * regno * bits 16) -> ast
+  | DADD : (regno * regno * regno) -> ast
+  | ADD : (regno * regno * regno) -> ast
+  | ADDI : (regno * regno * bits 16) -> ast
+  | ADDU : (regno * regno * regno) -> ast
+  | ADDIU : (regno * regno * bits 16) -> ast
+  | DSUBU : (regno * regno * regno) -> ast
+  | DSUB : (regno * regno * regno) -> ast
+  | SUB : (regno * regno * regno) -> ast
+  | SUBU : (regno * regno * regno) -> ast
+  | AND : (regno * regno * regno) -> ast
+  | ANDI : (regno * regno * bits 16) -> ast
+  | OR : (regno * regno * regno) -> ast
+  | ORI : (regno * regno * bits 16) -> ast
+  | NOR : (regno * regno * regno) -> ast
+  | XOR : (regno * regno * regno) -> ast
+  | XORI : (regno * regno * bits 16) -> ast
+  | LUI : (regno * imm16) -> ast
+  | DSLL : (regno * regno * regno) -> ast
+  | DSLL32 : (regno * regno * regno) -> ast
+  | DSLLV : (regno * regno * regno) -> ast
+  | DSRA : (regno * regno * regno) -> ast
+  | DSRA32 : (regno * regno * regno) -> ast
+  | DSRAV : (regno * regno * regno) -> ast
+  | DSRL : (regno * regno * regno) -> ast
+  | DSRL32 : (regno * regno * regno) -> ast
+  | DSRLV : (regno * regno * regno) -> ast
+  | SLL : (regno * regno * regno) -> ast
+  | SLLV : (regno * regno * regno) -> ast
+  | SRA : (regno * regno * regno) -> ast
+  | SRAV : (regno * regno * regno) -> ast
+  | SRL : (regno * regno * regno) -> ast
+  | SRLV : (regno * regno * regno) -> ast
+  | SLT : (regno * regno * regno) -> ast
+  | SLTI : (regno * regno * bits 16) -> ast
+  | SLTU : (regno * regno * regno) -> ast
+  | SLTIU : (regno * regno * bits 16) -> ast
+  | MOVN : (regno * regno * regno) -> ast
+  | MOVZ : (regno * regno * regno) -> ast
+  | MFHI : regno -> ast
+  | MFLO : regno -> ast
+  | MTHI : regno -> ast
+  | MTLO : regno -> ast
+  | MUL : (regno * regno * regno) -> ast
+  | MULT : (regno * regno) -> ast
+  | MULTU : (regno * regno) -> ast
+  | DMULT : (regno * regno) -> ast
+  | DMULTU : (regno * regno) -> ast
+  | MADD : (regno * regno) -> ast
+  | MADDU : (regno * regno) -> ast
+  | MSUB : (regno * regno) -> ast
+  | MSUBU : (regno * regno) -> ast
+  | DIV : (regno * regno) -> ast
+  | DIVU : (regno * regno) -> ast
+  | DDIV : (regno * regno) -> ast
+  | DDIVU : (regno * regno) -> ast
+  | J : bits 26 -> ast
+  | JAL : bits 26 -> ast
+  | JR : regno -> ast
+  | JALR : (regno * regno) -> ast
+  | BEQ : (regno * regno * imm16 * bool * bool) -> ast
+  | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast
+  | SYSCALL : unit -> ast
+  | BREAK : unit -> ast
+  | WAIT : unit -> ast
+  | TRAPREG : (regno * regno * Comparison) -> ast
+  | TRAPIMM : (regno * imm16 * Comparison) -> ast
+  | Load : (WordType * bool * bool * regno * regno * imm16) -> ast
+  | Store : (WordType * bool * regno * regno * imm16) -> ast
+  | LWL : (regno * regno * bits 16) -> ast
+  | LWR : (regno * regno * bits 16) -> ast
+  | SWL : (regno * regno * bits 16) -> ast
+  | SWR : (regno * regno * bits 16) -> ast
+  | LDL : (regno * regno * bits 16) -> ast
+  | LDR : (regno * regno * bits 16) -> ast
+  | SDL : (regno * regno * bits 16) -> ast
+  | SDR : (regno * regno * bits 16) -> ast
+  | CACHE : (regno * regno * bits 16) -> ast
+  | SYNC : unit -> ast
+  | MFC0 : (regno * regno * bits 3 * bool) -> ast
+  | HCF : unit -> ast
+  | MTC0 : (regno * regno * bits 3 * bool) -> ast
+  | TLBWI : unit -> ast
+  | TLBWR : unit -> ast
+  | TLBR : unit -> ast
+  | TLBP : unit -> ast
+  | RDHWR : (regno * regno) -> ast
+  | ERET : unit -> ast
+  | RI : unit -> ast.
+Arguments ast : clear implicits.
+
+
+
+Inductive register_value  :=
+  Regval_vector : (Z * bool * list register_value) -> register_value
+  | Regval_list : list register_value -> register_value
+  | Regval_option : option register_value -> register_value
+  | Regval_CauseReg : CauseReg -> register_value
+  | Regval_ContextReg : ContextReg -> register_value
+  | Regval_StatusReg : StatusReg -> register_value
+  | Regval_TLBEntry : TLBEntry -> register_value
+  | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value
+  | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value
+  | Regval_XContextReg : XContextReg -> register_value
+  | Regval_vector_16_dec_bit : mword 16 -> register_value
+  | Regval_vector_1_dec_bit : mword 1 -> register_value
+  | Regval_vector_32_dec_bit : mword 32 -> register_value
+  | Regval_vector_3_dec_bit : mword 3 -> register_value
+  | Regval_vector_64_dec_bit : mword 64 -> register_value
+  | Regval_vector_6_dec_bit : mword 6 -> register_value
+  | Regval_vector_8_dec_bit : mword 8 -> register_value.
+Arguments register_value : clear implicits.
+
+
+
+Record regstate  :=
+  { UART_RVALID : mword 1;
+    UART_RDATA : mword 8;
+    UART_WRITTEN : mword 1;
+    UART_WDATA : mword 8;
+    GPR : vec (mword 64) 32;
+    LO : mword 64;
+    HI : mword 64;
+    delayedPC : mword 64;
+    inBranchDelay : mword 1;
+    branchPending : mword 1;
+    CP0Status : StatusReg;
+    CP0ConfigK0 : mword 3;
+    CP0UserLocal : mword 64;
+    CP0HWREna : mword 32;
+    CP0Count : mword 32;
+    CP0BadVAddr : mword 64;
+    CP0LLAddr : mword 64;
+    CP0LLBit : mword 1;
+    CP0ErrorEPC : mword 64;
+    CP0EPC : mword 64;
+    CP0Cause : CauseReg;
+    CP0Compare : mword 32;
+    TLBEntry63 : TLBEntry;
+    TLBEntry62 : TLBEntry;
+    TLBEntry61 : TLBEntry;
+    TLBEntry60 : TLBEntry;
+    TLBEntry59 : TLBEntry;
+    TLBEntry58 : TLBEntry;
+    TLBEntry57 : TLBEntry;
+    TLBEntry56 : TLBEntry;
+    TLBEntry55 : TLBEntry;
+    TLBEntry54 : TLBEntry;
+    TLBEntry53 : TLBEntry;
+    TLBEntry52 : TLBEntry;
+    TLBEntry51 : TLBEntry;
+    TLBEntry50 : TLBEntry;
+    TLBEntry49 : TLBEntry;
+    TLBEntry48 : TLBEntry;
+    TLBEntry47 : TLBEntry;
+    TLBEntry46 : TLBEntry;
+    TLBEntry45 : TLBEntry;
+    TLBEntry44 : TLBEntry;
+    TLBEntry43 : TLBEntry;
+    TLBEntry42 : TLBEntry;
+    TLBEntry41 : TLBEntry;
+    TLBEntry40 : TLBEntry;
+    TLBEntry39 : TLBEntry;
+    TLBEntry38 : TLBEntry;
+    TLBEntry37 : TLBEntry;
+    TLBEntry36 : TLBEntry;
+    TLBEntry35 : TLBEntry;
+    TLBEntry34 : TLBEntry;
+    TLBEntry33 : TLBEntry;
+    TLBEntry32 : TLBEntry;
+    TLBEntry31 : TLBEntry;
+    TLBEntry30 : TLBEntry;
+    TLBEntry29 : TLBEntry;
+    TLBEntry28 : TLBEntry;
+    TLBEntry27 : TLBEntry;
+    TLBEntry26 : TLBEntry;
+    TLBEntry25 : TLBEntry;
+    TLBEntry24 : TLBEntry;
+    TLBEntry23 : TLBEntry;
+    TLBEntry22 : TLBEntry;
+    TLBEntry21 : TLBEntry;
+    TLBEntry20 : TLBEntry;
+    TLBEntry19 : TLBEntry;
+    TLBEntry18 : TLBEntry;
+    TLBEntry17 : TLBEntry;
+    TLBEntry16 : TLBEntry;
+    TLBEntry15 : TLBEntry;
+    TLBEntry14 : TLBEntry;
+    TLBEntry13 : TLBEntry;
+    TLBEntry12 : TLBEntry;
+    TLBEntry11 : TLBEntry;
+    TLBEntry10 : TLBEntry;
+    TLBEntry09 : TLBEntry;
+    TLBEntry08 : TLBEntry;
+    TLBEntry07 : TLBEntry;
+    TLBEntry06 : TLBEntry;
+    TLBEntry05 : TLBEntry;
+    TLBEntry04 : TLBEntry;
+    TLBEntry03 : TLBEntry;
+    TLBEntry02 : TLBEntry;
+    TLBEntry01 : TLBEntry;
+    TLBEntry00 : TLBEntry;
+    TLBXContext : XContextReg;
+    TLBEntryHi : TLBEntryHiReg;
+    TLBWired : mword 6;
+    TLBPageMask : mword 16;
+    TLBContext : ContextReg;
+    TLBEntryLo1 : TLBEntryLoReg;
+    TLBEntryLo0 : TLBEntryLoReg;
+    TLBRandom : mword 6;
+    TLBIndex : mword 6;
+    TLBProbe : mword 1;
+    nextPC : mword 64;
+    PC : mword 64; }.
+Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'delayedPC' := e ]}" := ({| delayedPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'inBranchDelay' := e ]}" := ({| inBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'branchPending' := e ]}" := ({| branchPending := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}).
+Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r |}).
+
+
+
+Definition CauseReg_of_regval (merge_var : register_value) 
+: option CauseReg :=
+   match merge_var with | Regval_CauseReg (v) => Some v | g__13 => None end.
+
+Definition regval_of_CauseReg (v : CauseReg)  : register_value := Regval_CauseReg v.
+
+Definition ContextReg_of_regval (merge_var : register_value) 
+: option ContextReg :=
+   match merge_var with | Regval_ContextReg (v) => Some v | g__12 => None end.
+
+Definition regval_of_ContextReg (v : ContextReg)  : register_value := Regval_ContextReg v.
+
+Definition StatusReg_of_regval (merge_var : register_value) 
+: option StatusReg :=
+   match merge_var with | Regval_StatusReg (v) => Some v | g__11 => None end.
+
+Definition regval_of_StatusReg (v : StatusReg)  : register_value := Regval_StatusReg v.
+
+Definition TLBEntry_of_regval (merge_var : register_value) 
+: option TLBEntry :=
+   match merge_var with | Regval_TLBEntry (v) => Some v | g__10 => None end.
+
+Definition regval_of_TLBEntry (v : TLBEntry)  : register_value := Regval_TLBEntry v.
+
+Definition TLBEntryHiReg_of_regval (merge_var : register_value) 
+: option TLBEntryHiReg :=
+   match merge_var with | Regval_TLBEntryHiReg (v) => Some v | g__9 => None end.
+
+Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg)  : register_value := Regval_TLBEntryHiReg v.
+
+Definition TLBEntryLoReg_of_regval (merge_var : register_value) 
+: option TLBEntryLoReg :=
+   match merge_var with | Regval_TLBEntryLoReg (v) => Some v | g__8 => None end.
+
+Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg)  : register_value := Regval_TLBEntryLoReg v.
+
+Definition XContextReg_of_regval (merge_var : register_value) 
+: option XContextReg :=
+   match merge_var with | Regval_XContextReg (v) => Some v | g__7 => None end.
+
+Definition regval_of_XContextReg (v : XContextReg)  : register_value := Regval_XContextReg v.
+
+Definition vector_16_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 16) :=
+   match merge_var with | Regval_vector_16_dec_bit (v) => Some v | g__6 => None end.
+
+Definition regval_of_vector_16_dec_bit (v : mword 16) 
+: register_value :=
+   Regval_vector_16_dec_bit v.
+
+Definition vector_1_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 1) :=
+   match merge_var with | Regval_vector_1_dec_bit (v) => Some v | g__5 => None end.
+
+Definition regval_of_vector_1_dec_bit (v : mword 1)  : register_value := Regval_vector_1_dec_bit v.
+
+Definition vector_32_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 32) :=
+   match merge_var with | Regval_vector_32_dec_bit (v) => Some v | g__4 => None end.
+
+Definition regval_of_vector_32_dec_bit (v : mword 32) 
+: register_value :=
+   Regval_vector_32_dec_bit v.
+
+Definition vector_3_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 3) :=
+   match merge_var with | Regval_vector_3_dec_bit (v) => Some v | g__3 => None end.
+
+Definition regval_of_vector_3_dec_bit (v : mword 3)  : register_value := Regval_vector_3_dec_bit v.
+
+Definition vector_64_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 64) :=
+   match merge_var with | Regval_vector_64_dec_bit (v) => Some v | g__2 => None end.
+
+Definition regval_of_vector_64_dec_bit (v : mword 64) 
+: register_value :=
+   Regval_vector_64_dec_bit v.
+
+Definition vector_6_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 6) :=
+   match merge_var with | Regval_vector_6_dec_bit (v) => Some v | g__1 => None end.
+
+Definition regval_of_vector_6_dec_bit (v : mword 6)  : register_value := Regval_vector_6_dec_bit v.
+
+Definition vector_8_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 8) :=
+   match merge_var with | Regval_vector_8_dec_bit (v) => Some v | g__0 => None end.
+
+Definition regval_of_vector_8_dec_bit (v : mword 8)  : register_value := Regval_vector_8_dec_bit v.
+
+
+
+Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with
+  | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None
+  | _ => None
+end.
+
+Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)).
+
+Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with
+  | Regval_list v => just_list (List.map of_regval v)
+  | _ => None
+end.
+
+Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs).
+
+Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with
+  | Regval_option v => option_map of_regval v
+  | _ => None
+end.
+
+Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v).
+
+
+Definition UART_RVALID_ref := {|
+  name := "UART_RVALID";
+  read_from := (fun s => s.(UART_RVALID));
+  write_to := (fun v s => ({[ s with UART_RVALID := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition UART_RDATA_ref := {|
+  name := "UART_RDATA";
+  read_from := (fun s => s.(UART_RDATA));
+  write_to := (fun v s => ({[ s with UART_RDATA := v ]}));
+  of_regval := (fun v => vector_8_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_8_dec_bit v) |}.
+
+Definition UART_WRITTEN_ref := {|
+  name := "UART_WRITTEN";
+  read_from := (fun s => s.(UART_WRITTEN));
+  write_to := (fun v s => ({[ s with UART_WRITTEN := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition UART_WDATA_ref := {|
+  name := "UART_WDATA";
+  read_from := (fun s => s.(UART_WDATA));
+  write_to := (fun v s => ({[ s with UART_WDATA := v ]}));
+  of_regval := (fun v => vector_8_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_8_dec_bit v) |}.
+
+Definition GPR_ref := {|
+  name := "GPR";
+  read_from := (fun s => s.(GPR));
+  write_to := (fun v s => ({[ s with GPR := v ]}));
+  of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v);
+  regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}.
+
+Definition LO_ref := {|
+  name := "LO";
+  read_from := (fun s => s.(LO));
+  write_to := (fun v s => ({[ s with LO := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition HI_ref := {|
+  name := "HI";
+  read_from := (fun s => s.(HI));
+  write_to := (fun v s => ({[ s with HI := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition delayedPC_ref := {|
+  name := "delayedPC";
+  read_from := (fun s => s.(delayedPC));
+  write_to := (fun v s => ({[ s with delayedPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition inBranchDelay_ref := {|
+  name := "inBranchDelay";
+  read_from := (fun s => s.(inBranchDelay));
+  write_to := (fun v s => ({[ s with inBranchDelay := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition branchPending_ref := {|
+  name := "branchPending";
+  read_from := (fun s => s.(branchPending));
+  write_to := (fun v s => ({[ s with branchPending := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition CP0Status_ref := {|
+  name := "CP0Status";
+  read_from := (fun s => s.(CP0Status));
+  write_to := (fun v s => ({[ s with CP0Status := v ]}));
+  of_regval := (fun v => StatusReg_of_regval v);
+  regval_of := (fun v => regval_of_StatusReg v) |}.
+
+Definition CP0ConfigK0_ref := {|
+  name := "CP0ConfigK0";
+  read_from := (fun s => s.(CP0ConfigK0));
+  write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]}));
+  of_regval := (fun v => vector_3_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_3_dec_bit v) |}.
+
+Definition CP0UserLocal_ref := {|
+  name := "CP0UserLocal";
+  read_from := (fun s => s.(CP0UserLocal));
+  write_to := (fun v s => ({[ s with CP0UserLocal := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0HWREna_ref := {|
+  name := "CP0HWREna";
+  read_from := (fun s => s.(CP0HWREna));
+  write_to := (fun v s => ({[ s with CP0HWREna := v ]}));
+  of_regval := (fun v => vector_32_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_32_dec_bit v) |}.
+
+Definition CP0Count_ref := {|
+  name := "CP0Count";
+  read_from := (fun s => s.(CP0Count));
+  write_to := (fun v s => ({[ s with CP0Count := v ]}));
+  of_regval := (fun v => vector_32_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_32_dec_bit v) |}.
+
+Definition CP0BadVAddr_ref := {|
+  name := "CP0BadVAddr";
+  read_from := (fun s => s.(CP0BadVAddr));
+  write_to := (fun v s => ({[ s with CP0BadVAddr := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0LLAddr_ref := {|
+  name := "CP0LLAddr";
+  read_from := (fun s => s.(CP0LLAddr));
+  write_to := (fun v s => ({[ s with CP0LLAddr := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0LLBit_ref := {|
+  name := "CP0LLBit";
+  read_from := (fun s => s.(CP0LLBit));
+  write_to := (fun v s => ({[ s with CP0LLBit := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition CP0ErrorEPC_ref := {|
+  name := "CP0ErrorEPC";
+  read_from := (fun s => s.(CP0ErrorEPC));
+  write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0EPC_ref := {|
+  name := "CP0EPC";
+  read_from := (fun s => s.(CP0EPC));
+  write_to := (fun v s => ({[ s with CP0EPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0Cause_ref := {|
+  name := "CP0Cause";
+  read_from := (fun s => s.(CP0Cause));
+  write_to := (fun v s => ({[ s with CP0Cause := v ]}));
+  of_regval := (fun v => CauseReg_of_regval v);
+  regval_of := (fun v => regval_of_CauseReg v) |}.
+
+Definition CP0Compare_ref := {|
+  name := "CP0Compare";
+  read_from := (fun s => s.(CP0Compare));
+  write_to := (fun v s => ({[ s with CP0Compare := v ]}));
+  of_regval := (fun v => vector_32_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_32_dec_bit v) |}.
+
+Definition TLBEntry63_ref := {|
+  name := "TLBEntry63";
+  read_from := (fun s => s.(TLBEntry63));
+  write_to := (fun v s => ({[ s with TLBEntry63 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry62_ref := {|
+  name := "TLBEntry62";
+  read_from := (fun s => s.(TLBEntry62));
+  write_to := (fun v s => ({[ s with TLBEntry62 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry61_ref := {|
+  name := "TLBEntry61";
+  read_from := (fun s => s.(TLBEntry61));
+  write_to := (fun v s => ({[ s with TLBEntry61 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry60_ref := {|
+  name := "TLBEntry60";
+  read_from := (fun s => s.(TLBEntry60));
+  write_to := (fun v s => ({[ s with TLBEntry60 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry59_ref := {|
+  name := "TLBEntry59";
+  read_from := (fun s => s.(TLBEntry59));
+  write_to := (fun v s => ({[ s with TLBEntry59 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry58_ref := {|
+  name := "TLBEntry58";
+  read_from := (fun s => s.(TLBEntry58));
+  write_to := (fun v s => ({[ s with TLBEntry58 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry57_ref := {|
+  name := "TLBEntry57";
+  read_from := (fun s => s.(TLBEntry57));
+  write_to := (fun v s => ({[ s with TLBEntry57 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry56_ref := {|
+  name := "TLBEntry56";
+  read_from := (fun s => s.(TLBEntry56));
+  write_to := (fun v s => ({[ s with TLBEntry56 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry55_ref := {|
+  name := "TLBEntry55";
+  read_from := (fun s => s.(TLBEntry55));
+  write_to := (fun v s => ({[ s with TLBEntry55 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry54_ref := {|
+  name := "TLBEntry54";
+  read_from := (fun s => s.(TLBEntry54));
+  write_to := (fun v s => ({[ s with TLBEntry54 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry53_ref := {|
+  name := "TLBEntry53";
+  read_from := (fun s => s.(TLBEntry53));
+  write_to := (fun v s => ({[ s with TLBEntry53 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry52_ref := {|
+  name := "TLBEntry52";
+  read_from := (fun s => s.(TLBEntry52));
+  write_to := (fun v s => ({[ s with TLBEntry52 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry51_ref := {|
+  name := "TLBEntry51";
+  read_from := (fun s => s.(TLBEntry51));
+  write_to := (fun v s => ({[ s with TLBEntry51 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry50_ref := {|
+  name := "TLBEntry50";
+  read_from := (fun s => s.(TLBEntry50));
+  write_to := (fun v s => ({[ s with TLBEntry50 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry49_ref := {|
+  name := "TLBEntry49";
+  read_from := (fun s => s.(TLBEntry49));
+  write_to := (fun v s => ({[ s with TLBEntry49 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry48_ref := {|
+  name := "TLBEntry48";
+  read_from := (fun s => s.(TLBEntry48));
+  write_to := (fun v s => ({[ s with TLBEntry48 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry47_ref := {|
+  name := "TLBEntry47";
+  read_from := (fun s => s.(TLBEntry47));
+  write_to := (fun v s => ({[ s with TLBEntry47 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry46_ref := {|
+  name := "TLBEntry46";
+  read_from := (fun s => s.(TLBEntry46));
+  write_to := (fun v s => ({[ s with TLBEntry46 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry45_ref := {|
+  name := "TLBEntry45";
+  read_from := (fun s => s.(TLBEntry45));
+  write_to := (fun v s => ({[ s with TLBEntry45 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry44_ref := {|
+  name := "TLBEntry44";
+  read_from := (fun s => s.(TLBEntry44));
+  write_to := (fun v s => ({[ s with TLBEntry44 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry43_ref := {|
+  name := "TLBEntry43";
+  read_from := (fun s => s.(TLBEntry43));
+  write_to := (fun v s => ({[ s with TLBEntry43 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry42_ref := {|
+  name := "TLBEntry42";
+  read_from := (fun s => s.(TLBEntry42));
+  write_to := (fun v s => ({[ s with TLBEntry42 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry41_ref := {|
+  name := "TLBEntry41";
+  read_from := (fun s => s.(TLBEntry41));
+  write_to := (fun v s => ({[ s with TLBEntry41 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry40_ref := {|
+  name := "TLBEntry40";
+  read_from := (fun s => s.(TLBEntry40));
+  write_to := (fun v s => ({[ s with TLBEntry40 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry39_ref := {|
+  name := "TLBEntry39";
+  read_from := (fun s => s.(TLBEntry39));
+  write_to := (fun v s => ({[ s with TLBEntry39 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry38_ref := {|
+  name := "TLBEntry38";
+  read_from := (fun s => s.(TLBEntry38));
+  write_to := (fun v s => ({[ s with TLBEntry38 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry37_ref := {|
+  name := "TLBEntry37";
+  read_from := (fun s => s.(TLBEntry37));
+  write_to := (fun v s => ({[ s with TLBEntry37 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry36_ref := {|
+  name := "TLBEntry36";
+  read_from := (fun s => s.(TLBEntry36));
+  write_to := (fun v s => ({[ s with TLBEntry36 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry35_ref := {|
+  name := "TLBEntry35";
+  read_from := (fun s => s.(TLBEntry35));
+  write_to := (fun v s => ({[ s with TLBEntry35 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry34_ref := {|
+  name := "TLBEntry34";
+  read_from := (fun s => s.(TLBEntry34));
+  write_to := (fun v s => ({[ s with TLBEntry34 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry33_ref := {|
+  name := "TLBEntry33";
+  read_from := (fun s => s.(TLBEntry33));
+  write_to := (fun v s => ({[ s with TLBEntry33 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry32_ref := {|
+  name := "TLBEntry32";
+  read_from := (fun s => s.(TLBEntry32));
+  write_to := (fun v s => ({[ s with TLBEntry32 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry31_ref := {|
+  name := "TLBEntry31";
+  read_from := (fun s => s.(TLBEntry31));
+  write_to := (fun v s => ({[ s with TLBEntry31 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry30_ref := {|
+  name := "TLBEntry30";
+  read_from := (fun s => s.(TLBEntry30));
+  write_to := (fun v s => ({[ s with TLBEntry30 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry29_ref := {|
+  name := "TLBEntry29";
+  read_from := (fun s => s.(TLBEntry29));
+  write_to := (fun v s => ({[ s with TLBEntry29 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry28_ref := {|
+  name := "TLBEntry28";
+  read_from := (fun s => s.(TLBEntry28));
+  write_to := (fun v s => ({[ s with TLBEntry28 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry27_ref := {|
+  name := "TLBEntry27";
+  read_from := (fun s => s.(TLBEntry27));
+  write_to := (fun v s => ({[ s with TLBEntry27 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry26_ref := {|
+  name := "TLBEntry26";
+  read_from := (fun s => s.(TLBEntry26));
+  write_to := (fun v s => ({[ s with TLBEntry26 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry25_ref := {|
+  name := "TLBEntry25";
+  read_from := (fun s => s.(TLBEntry25));
+  write_to := (fun v s => ({[ s with TLBEntry25 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry24_ref := {|
+  name := "TLBEntry24";
+  read_from := (fun s => s.(TLBEntry24));
+  write_to := (fun v s => ({[ s with TLBEntry24 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry23_ref := {|
+  name := "TLBEntry23";
+  read_from := (fun s => s.(TLBEntry23));
+  write_to := (fun v s => ({[ s with TLBEntry23 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry22_ref := {|
+  name := "TLBEntry22";
+  read_from := (fun s => s.(TLBEntry22));
+  write_to := (fun v s => ({[ s with TLBEntry22 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry21_ref := {|
+  name := "TLBEntry21";
+  read_from := (fun s => s.(TLBEntry21));
+  write_to := (fun v s => ({[ s with TLBEntry21 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry20_ref := {|
+  name := "TLBEntry20";
+  read_from := (fun s => s.(TLBEntry20));
+  write_to := (fun v s => ({[ s with TLBEntry20 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry19_ref := {|
+  name := "TLBEntry19";
+  read_from := (fun s => s.(TLBEntry19));
+  write_to := (fun v s => ({[ s with TLBEntry19 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry18_ref := {|
+  name := "TLBEntry18";
+  read_from := (fun s => s.(TLBEntry18));
+  write_to := (fun v s => ({[ s with TLBEntry18 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry17_ref := {|
+  name := "TLBEntry17";
+  read_from := (fun s => s.(TLBEntry17));
+  write_to := (fun v s => ({[ s with TLBEntry17 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry16_ref := {|
+  name := "TLBEntry16";
+  read_from := (fun s => s.(TLBEntry16));
+  write_to := (fun v s => ({[ s with TLBEntry16 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry15_ref := {|
+  name := "TLBEntry15";
+  read_from := (fun s => s.(TLBEntry15));
+  write_to := (fun v s => ({[ s with TLBEntry15 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry14_ref := {|
+  name := "TLBEntry14";
+  read_from := (fun s => s.(TLBEntry14));
+  write_to := (fun v s => ({[ s with TLBEntry14 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry13_ref := {|
+  name := "TLBEntry13";
+  read_from := (fun s => s.(TLBEntry13));
+  write_to := (fun v s => ({[ s with TLBEntry13 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry12_ref := {|
+  name := "TLBEntry12";
+  read_from := (fun s => s.(TLBEntry12));
+  write_to := (fun v s => ({[ s with TLBEntry12 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry11_ref := {|
+  name := "TLBEntry11";
+  read_from := (fun s => s.(TLBEntry11));
+  write_to := (fun v s => ({[ s with TLBEntry11 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry10_ref := {|
+  name := "TLBEntry10";
+  read_from := (fun s => s.(TLBEntry10));
+  write_to := (fun v s => ({[ s with TLBEntry10 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry09_ref := {|
+  name := "TLBEntry09";
+  read_from := (fun s => s.(TLBEntry09));
+  write_to := (fun v s => ({[ s with TLBEntry09 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry08_ref := {|
+  name := "TLBEntry08";
+  read_from := (fun s => s.(TLBEntry08));
+  write_to := (fun v s => ({[ s with TLBEntry08 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry07_ref := {|
+  name := "TLBEntry07";
+  read_from := (fun s => s.(TLBEntry07));
+  write_to := (fun v s => ({[ s with TLBEntry07 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry06_ref := {|
+  name := "TLBEntry06";
+  read_from := (fun s => s.(TLBEntry06));
+  write_to := (fun v s => ({[ s with TLBEntry06 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry05_ref := {|
+  name := "TLBEntry05";
+  read_from := (fun s => s.(TLBEntry05));
+  write_to := (fun v s => ({[ s with TLBEntry05 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry04_ref := {|
+  name := "TLBEntry04";
+  read_from := (fun s => s.(TLBEntry04));
+  write_to := (fun v s => ({[ s with TLBEntry04 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry03_ref := {|
+  name := "TLBEntry03";
+  read_from := (fun s => s.(TLBEntry03));
+  write_to := (fun v s => ({[ s with TLBEntry03 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry02_ref := {|
+  name := "TLBEntry02";
+  read_from := (fun s => s.(TLBEntry02));
+  write_to := (fun v s => ({[ s with TLBEntry02 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry01_ref := {|
+  name := "TLBEntry01";
+  read_from := (fun s => s.(TLBEntry01));
+  write_to := (fun v s => ({[ s with TLBEntry01 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry00_ref := {|
+  name := "TLBEntry00";
+  read_from := (fun s => s.(TLBEntry00));
+  write_to := (fun v s => ({[ s with TLBEntry00 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBXContext_ref := {|
+  name := "TLBXContext";
+  read_from := (fun s => s.(TLBXContext));
+  write_to := (fun v s => ({[ s with TLBXContext := v ]}));
+  of_regval := (fun v => XContextReg_of_regval v);
+  regval_of := (fun v => regval_of_XContextReg v) |}.
+
+Definition TLBEntryHi_ref := {|
+  name := "TLBEntryHi";
+  read_from := (fun s => s.(TLBEntryHi));
+  write_to := (fun v s => ({[ s with TLBEntryHi := v ]}));
+  of_regval := (fun v => TLBEntryHiReg_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntryHiReg v) |}.
+
+Definition TLBWired_ref := {|
+  name := "TLBWired";
+  read_from := (fun s => s.(TLBWired));
+  write_to := (fun v s => ({[ s with TLBWired := v ]}));
+  of_regval := (fun v => vector_6_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_6_dec_bit v) |}.
+
+Definition TLBPageMask_ref := {|
+  name := "TLBPageMask";
+  read_from := (fun s => s.(TLBPageMask));
+  write_to := (fun v s => ({[ s with TLBPageMask := v ]}));
+  of_regval := (fun v => vector_16_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_16_dec_bit v) |}.
+
+Definition TLBContext_ref := {|
+  name := "TLBContext";
+  read_from := (fun s => s.(TLBContext));
+  write_to := (fun v s => ({[ s with TLBContext := v ]}));
+  of_regval := (fun v => ContextReg_of_regval v);
+  regval_of := (fun v => regval_of_ContextReg v) |}.
+
+Definition TLBEntryLo1_ref := {|
+  name := "TLBEntryLo1";
+  read_from := (fun s => s.(TLBEntryLo1));
+  write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]}));
+  of_regval := (fun v => TLBEntryLoReg_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntryLoReg v) |}.
+
+Definition TLBEntryLo0_ref := {|
+  name := "TLBEntryLo0";
+  read_from := (fun s => s.(TLBEntryLo0));
+  write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]}));
+  of_regval := (fun v => TLBEntryLoReg_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntryLoReg v) |}.
+
+Definition TLBRandom_ref := {|
+  name := "TLBRandom";
+  read_from := (fun s => s.(TLBRandom));
+  write_to := (fun v s => ({[ s with TLBRandom := v ]}));
+  of_regval := (fun v => vector_6_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_6_dec_bit v) |}.
+
+Definition TLBIndex_ref := {|
+  name := "TLBIndex";
+  read_from := (fun s => s.(TLBIndex));
+  write_to := (fun v s => ({[ s with TLBIndex := v ]}));
+  of_regval := (fun v => vector_6_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_6_dec_bit v) |}.
+
+Definition TLBProbe_ref := {|
+  name := "TLBProbe";
+  read_from := (fun s => s.(TLBProbe));
+  write_to := (fun v s => ({[ s with TLBProbe := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition nextPC_ref := {|
+  name := "nextPC";
+  read_from := (fun s => s.(nextPC));
+  write_to := (fun v s => ({[ s with nextPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition PC_ref := {|
+  name := "PC";
+  read_from := (fun s => s.(PC));
+  write_to := (fun v s => ({[ s with PC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Local Open Scope string.
+Definition get_regval (reg_name : string) (s : regstate) : option register_value :=
+  if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else
+  if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else
+  if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else
+  if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else
+  if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else
+  if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else
+  if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else
+  if string_dec reg_name "delayedPC" then Some (delayedPC_ref.(regval_of) (delayedPC_ref.(read_from) s)) else
+  if string_dec reg_name "inBranchDelay" then Some (inBranchDelay_ref.(regval_of) (inBranchDelay_ref.(read_from) s)) else
+  if string_dec reg_name "branchPending" then Some (branchPending_ref.(regval_of) (branchPending_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else
+  if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else
+  if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else
+  if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else
+  if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else
+  if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else
+  if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else
+  if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else
+  if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else
+  if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else
+  if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else
+  if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else
+  if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else
+  if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else
+  if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else
+  if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else
+  if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else
+  if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else
+  None.
+
+Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate :=
+  if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else
+  if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else
+  if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else
+  if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else
+  if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else
+  if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else
+  if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else
+  if string_dec reg_name "delayedPC" then option_map (fun v => delayedPC_ref.(write_to) v s) (delayedPC_ref.(of_regval) v) else
+  if string_dec reg_name "inBranchDelay" then option_map (fun v => inBranchDelay_ref.(write_to) v s) (inBranchDelay_ref.(of_regval) v) else
+  if string_dec reg_name "branchPending" then option_map (fun v => branchPending_ref.(write_to) v s) (branchPending_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else
+  if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else
+  if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else
+  if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else
+  if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else
+  if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else
+  if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else
+  if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else
+  if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else
+  if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else
+  if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else
+  if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else
+  if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else
+  if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else
+  if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else
+  if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else
+  if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else
+  if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else
+  None.
+
+Definition register_accessors := (get_regval, set_regval).
+
+
+Definition MR a r := monadR register_value a r exception.
+Definition M a := monad register_value a exception.
-- 
cgit v1.2.3


From 5b9a669cb26d4d2fcee44f17f0328ba7035d2812 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 10 Jul 2018 22:45:54 +0100
Subject: HOL4 snapshot update

---
 snapshots/hol4/README.md                           |    11 +-
 snapshots/hol4/build                               |     2 +-
 snapshots/hol4/clean                               |     2 +-
 snapshots/hol4/lem/hol-lib/lem_numScript.sml       |     6 +-
 snapshots/hol4/sail/aarch64/Holmakefile            |    11 +
 .../hol4/sail/aarch64/aarch64_extrasScript.sml     |   135 +
 snapshots/hol4/sail/aarch64/aarch64_monoScript.sml | 36178 +++++++++++++++++++
 .../hol4/sail/aarch64/aarch64_mono_typesScript.sml |  2421 ++
 snapshots/hol4/sail/cheri/cheriScript.sml          |  8193 +++--
 snapshots/hol4/sail/cheri/cheri_typesScript.sml    |   224 +-
 snapshots/hol4/sail/cheri/mips_extrasScript.sml    |   186 +-
 snapshots/hol4/sail/lib/hol/Holmakefile            |     9 +-
 snapshots/hol4/sail/lib/hol/promptScript.sml       |    15 -
 snapshots/hol4/sail/lib/hol/prompt_monadScript.sml |    31 -
 .../hol4/sail/lib/hol/sail2_instr_kindsScript.sml  |   448 +
 .../hol4/sail/lib/hol/sail2_operatorsScript.sml    |   327 +
 .../lib/hol/sail2_operators_bitlistsScript.sml     |   769 +
 .../sail/lib/hol/sail2_operators_mwordsScript.sml  |   635 +
 snapshots/hol4/sail/lib/hol/sail2_promptScript.sml |    15 +
 .../hol4/sail/lib/hol/sail2_prompt_monadScript.sml |    31 +
 .../sail/lib/hol/sail2_stateAuxiliaryScript.sml    |    61 +
 snapshots/hol4/sail/lib/hol/sail2_stateScript.sml  |   141 +
 .../hol4/sail/lib/hol/sail2_state_monadScript.sml  |   359 +
 snapshots/hol4/sail/lib/hol/sail2_stringScript.sml |   215 +
 .../sail/lib/hol/sail2_valuesAuxiliaryScript.sml   |   139 +
 snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml |  1246 +
 .../hol4/sail/lib/hol/sail_instr_kindsScript.sml   |   473 -
 .../hol4/sail/lib/hol/sail_operatorsScript.sml     |   327 -
 .../sail/lib/hol/sail_operators_bitlistsScript.sml |   769 -
 .../sail/lib/hol/sail_operators_mwordsScript.sml   |   635 -
 .../sail/lib/hol/sail_valuesAuxiliaryScript.sml    |   139 -
 snapshots/hol4/sail/lib/hol/sail_valuesScript.sml  |  1231 -
 .../hol4/sail/lib/hol/stateAuxiliaryScript.sml     |    61 -
 snapshots/hol4/sail/lib/hol/stateScript.sml        |   129 -
 snapshots/hol4/sail/lib/hol/state_monadScript.sml  |   367 -
 snapshots/hol4/sail/mips/Holmakefile               |    11 +
 snapshots/hol4/sail/mips/mipsScript.sml            |  6871 ++++
 snapshots/hol4/sail/mips/mips_extrasScript.sml     |   242 +
 snapshots/hol4/sail/mips/mips_typesScript.sml      |  1692 +
 snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml |     2 +-
 snapshots/hol4/sail/riscv/riscvScript.sml          | 22940 ++++++++++--
 snapshots/hol4/sail/riscv/riscv_extrasScript.sml   |   198 +-
 snapshots/hol4/sail/riscv/riscv_typesScript.sml    |   639 +-
 43 files changed, 76515 insertions(+), 12021 deletions(-)
 create mode 100644 snapshots/hol4/sail/aarch64/Holmakefile
 create mode 100644 snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml
 create mode 100644 snapshots/hol4/sail/aarch64/aarch64_monoScript.sml
 create mode 100644 snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/promptScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/prompt_monadScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_instr_kindsScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_operatorsScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_promptScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_prompt_monadScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_stateAuxiliaryScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_stateScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_state_monadScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_stringScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_valuesAuxiliaryScript.sml
 create mode 100644 snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/sail_valuesScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/stateAuxiliaryScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/stateScript.sml
 delete mode 100644 snapshots/hol4/sail/lib/hol/state_monadScript.sml
 create mode 100644 snapshots/hol4/sail/mips/Holmakefile
 create mode 100644 snapshots/hol4/sail/mips/mipsScript.sml
 create mode 100644 snapshots/hol4/sail/mips/mips_extrasScript.sml
 create mode 100644 snapshots/hol4/sail/mips/mips_typesScript.sml

diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md
index 5ce3b5cb..5ce37726 100644
--- a/snapshots/hol4/README.md
+++ b/snapshots/hol4/README.md
@@ -1,12 +1,5 @@
 # Snapshot of HOL4 output for Sail CHERI and RISC-V models
 
 These theories are a snapshot of the generated files for the Sail
-CHERI and RISC-V models, translated to HOL4 via Lem.
-
-Generated using the following repository versions:
-HOL4: (master) bb9eaf3448d2c44c84c5d06849d0dc73db23670c, 17 May 2018
-Lem:  (master) 55cb119f5b9e9feae8ed02c1b63ef38360eff3a1, 17 May 2018
-Sail: (sail2)  b08f0e8538081d8efbbbd6431e739a0b83307678, 17 May 2018
-
-The theories are accepted by HOL4, but we have not done any
-further testing of them yet.
+MIPS, CHERI, RISC-V, and Aarch64 models, translated to HOL4 via Lem.
+They only require HOL4; the necessary Lem library files are included.
diff --git a/snapshots/hol4/build b/snapshots/hol4/build
index 2b8be130..e85bdb13 100755
--- a/snapshots/hol4/build
+++ b/snapshots/hol4/build
@@ -1,5 +1,5 @@
 #!/bin/bash
 
-for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do
+for d in lem/hol-lib sail/lib/hol sail/mips sail/cheri sail/riscv sail/aarch64; do
   (cd $d; Holmake)
 done
diff --git a/snapshots/hol4/clean b/snapshots/hol4/clean
index f4301d3f..822fede5 100755
--- a/snapshots/hol4/clean
+++ b/snapshots/hol4/clean
@@ -1,5 +1,5 @@
 #!/bin/bash
 
-for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do
+for d in lem/hol-lib sail/lib/hol sail/mips sail/cheri sail/riscv sail/aarch64; do
   (cd $d; Holmake cleanAll)
 done
diff --git a/snapshots/hol4/lem/hol-lib/lem_numScript.sml b/snapshots/hol4/lem/hol-lib/lem_numScript.sml
index 6064416b..de65941f 100644
--- a/snapshots/hol4/lem/hol-lib/lem_numScript.sml
+++ b/snapshots/hol4/lem/hol-lib/lem_numScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from num.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory;
+open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory transcTheory;
 
 val _ = numLib.prefer_num();
 
@@ -12,8 +12,8 @@ val _ = new_theory "lem_num"
 
 (*open import Bool Basic_classes*)
 (*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*)
-(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*)
-(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) 
+(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory` `transcTheory`*)
+(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.QArith.Qround` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) 
 
 (*class inline ( Numeral 'a ) 
   val fromNumeral : numeral -> 'a 
diff --git a/snapshots/hol4/sail/aarch64/Holmakefile b/snapshots/hol4/sail/aarch64/Holmakefile
new file mode 100644
index 00000000..feafe6c4
--- /dev/null
+++ b/snapshots/hol4/sail/aarch64/Holmakefile
@@ -0,0 +1,11 @@
+LEMDIR=../../lem/hol-lib
+
+INCLUDES = $(LEMDIR) ../lib/hol
+
+all: aarch64_monoTheory.uo
+.PHONY: all
+
+ifdef POLY
+HOLHEAP = ../lib/hol/sail-heap
+
+endif
diff --git a/snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml b/snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml
new file mode 100644
index 00000000..51d55245
--- /dev/null
+++ b/snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml
@@ -0,0 +1,135 @@
+(*Generated by Lem from ../aarch64_extras.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "aarch64_extras"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+(*type ty512*)
+(*type ty1024*)
+(*type ty2048*)
+
+val _ = Define `
+ ((hexchar_to_bool_list:char ->((bool)list)option) c=
+   (if c = #"0" then      SOME ([F;F;F;F])
+  else if c = #"1" then SOME ([F;F;F;T ])
+  else if c = #"2" then SOME ([F;F;T; F])
+  else if c = #"3" then SOME ([F;F;T; T ])
+  else if c = #"4" then SOME ([F;T; F;F])
+  else if c = #"5" then SOME ([F;T; F;T ])
+  else if c = #"6" then SOME ([F;T; T; F])
+  else if c = #"7" then SOME ([F;T; T; T ])
+  else if c = #"8" then SOME ([T; F;F;F])
+  else if c = #"9" then SOME ([T; F;F;T ])
+  else if c = #"A" then SOME ([T; F;T; F])
+  else if c = #"a" then SOME ([T; F;T; F])
+  else if c = #"B" then SOME ([T; F;T; T ])
+  else if c = #"b" then SOME ([T; F;T; T ])
+  else if c = #"C" then SOME ([T; T; F;F])
+  else if c = #"c" then SOME ([T; T; F;F])
+  else if c = #"D" then SOME ([T; T; F;T ])
+  else if c = #"d" then SOME ([T; T; F;T ])
+  else if c = #"E" then SOME ([T; T; T; F])
+  else if c = #"e" then SOME ([T; T; T; F])
+  else if c = #"F" then SOME ([T; T; T; T ])
+  else if c = #"f" then SOME ([T; T; T; T ])
+  else NONE))`;
+
+
+val _ = Define `
+ ((hexstring_to_bools:string ->((bool)list)option) s=
+   ((case (EXPLODE s) of
+      z :: x :: hs =>
+       let str = (if ((z = #"0") /\ (x = #"x")) then hs else z :: (x :: hs)) in
+       OPTION_MAP FLAT (just_list (MAP hexchar_to_bool_list str))
+    | _ => NONE
+  )))`;
+
+
+(*val hex_slice : forall 'rv 'n 'e. Size 'n => string -> integer -> integer -> monad 'rv (mword 'n) 'e*)
+val _ = Define `
+ ((hex_slice:string -> int -> int -> 'rv sail2_state_monad$sequential_state ->((('n words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) v len lo=  (sail2_state_monad$bindS
+  (sail2_state_monad$maybe_failS "hex_slice" (hexstring_to_bools v)) (\ bs . 
+   let hi = ((len + lo) -( 1 : int)) in
+   let bs = (ext_list F (len + lo) bs) in
+   sail2_state_monad$returnS (bitstring$v2w (subrange_list F bs hi lo)))))`;
+
+
+(*val BigEndianReverse : forall 'rv 'n 'e. Size 'n => mword 'n -> monad 'rv (mword 'n) 'e*)
+val _ = Define `
+ ((BigEndianReverse:'n words$word -> 'rv sail2_state_monad$sequential_state ->((('n words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) w=  (sail2_state_monad$returnS (reverse_endianness w)))`;
+
+
+(* Use constants for some undefined values for now *)
+val _ = Define `
+ ((undefined_string:unit -> 'a sail2_state_monad$sequential_state ->(((string),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS ""))`;
+
+val _ = Define `
+ ((undefined_unit:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((undefined_int:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (( 0 : int):ii)))`;
+
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+val _ = Define `
+ ((undefined_vector:int -> 'a -> 'rv sail2_state_monad$sequential_state ->((('a list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len u=  (sail2_state_monad$returnS (repeat [u] len)))`;
+
+(*val undefined_bitvector : forall 'rv 'a 'e. Size 'a => integer -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((undefined_bitvector:int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len=  (sail2_state_monad$returnS (bitstring$v2w (repeat [F] len))))`;
+
+(*val undefined_bits : forall 'rv 'a 'e. Size 'a => integer -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((undefined_bits:int ->('rv,('a words$word),'e)monad)=  undefined_bitvector)`;
+
+val _ = Define `
+ ((undefined_bit:unit -> 'a sail2_state_monad$sequential_state ->(((bitU),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS B0))`;
+
+val _ = Define `
+ ((undefined_real:unit -> 'a sail2_state_monad$sequential_state ->(((real),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`;
+
+val _ = Define `
+ ((undefined_range:'a -> 'd -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i j=  (sail2_state_monad$returnS i))`;
+
+val _ = Define `
+ ((undefined_atom:'a -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i=  (sail2_state_monad$returnS i))`;
+
+val _ = Define `
+ ((undefined_nat:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (( 0 : int):ii)))`;
+
+
+(*val write_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c =>
+  integer -> integer -> mword 'a -> mword 'b -> mword 'c -> monad 'rv unit 'e*)
+val _ = Define `
+ ((write_ram:int -> int -> 'a words$word -> 'b words$word -> 'c words$word -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address value=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+  (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1))
+  (sail2_state_monad$write_mem_valS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict value)) (\b .  (case (b ) of ( _ ) => sail2_state_monad$returnS ()  ))))`;
+
+
+(*val read_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c =>
+  integer -> integer -> mword 'a -> mword 'b -> monad 'rv (mword 'c) 'e*)
+val _ = Define `
+ ((read_ram:int -> int -> 'a words$word -> 'b words$word -> 'rv sail2_state_monad$sequential_state ->((('c words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address=
+   (
+  (*let _ = prerr_endline ("Reading " ^ (stringFromInteger size) ^ " bytes from address " ^ (stringFromInteger (unsigned address))) in*)sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`;
+
+
+(*val elf_entry : unit -> integer*)
+val _ = Define `
+ ((elf_entry:unit -> int) () = (( 0 : int)))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml b/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml
new file mode 100644
index 00000000..b454337e
--- /dev/null
+++ b/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml
@@ -0,0 +1,36178 @@
+(*Generated by Lem from aarch64_mono.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory aarch64_mono_typesTheory aarch64_extrasTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "aarch64_mono"
+
+(*Generated by Sail from aarch64_mono.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+(*open import Aarch64_mono_types*)
+(*open import Aarch64_extras*)
+
+
+
+
+
+
+
+(*val neq_bool : bool -> bool -> bool*)
+
+val _ = Define `
+ ((neq_bool:bool -> bool -> bool) x y=  (~ (((x = y)))))`;
+
+
+(*val vcons : forall  'a. 'a -> list 'a -> list 'a*)
+
+
+
+
+
+(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
+
+
+
+(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
+
+
+
+(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*)
+
+(*val __GetSlice_int : forall 'n. Size 'n => itself 'n -> ii -> ii -> mword 'n*)
+
+val _ = Define `
+ ((GetSlice_int:'n itself -> int -> int -> 'n words$word) n m o1=
+    (let n = (size_itself_int n) in
+   (get_slice_int n m o1  :  'n words$word)))`;
+
+
+(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*)
+
+(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*)
+
+(*val cast_unit_vec : bitU -> mword ty1*)
+
+val _ = Define `
+ ((cast_unit_vec0:bitU ->(1)words$word) b=
+    ((case b of   B0 => (vec_of_bits [B0]  :  1 words$word) | B1 => (vec_of_bits [B1]  :  1 words$word) )))`;
+
+
+(*val BoolStr : bool -> string*)
+
+val _ = Define `
+ ((BoolStr:bool -> string) b=  (if b then "true" else "false"))`;
+
+
+(*val ex_nat : ii -> integer*)
+
+val _ = Define `
+ ((ex_nat:int -> int) n=  n)`;
+
+
+(*val ex_int : ii -> integer*)
+
+val _ = Define `
+ ((ex_int:int -> int) n=  n)`;
+
+
+(*val ex_range : integer -> integer*)
+
+(*val coerce_int_nat : ii -> M ii*)
+
+val _ = Define `
+ ((coerce_int_nat:int ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x=  (sail2_state_monad$seqS (sail2_state_monad$assert_expS T "Cannot coerce int to nat") (sail2_state_monad$returnS x)))`;
+
+
+(*val break : unit -> unit*)
+
+val _ = Define `
+ ((break:unit -> unit) () =  () )`;
+
+
+(*val undefined_exception : unit -> M exception*)
+
+val _ = Define `
+ ((undefined_exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_string () ) (\ (u_0 : string) .  sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_1 : unit) . 
+   sail2_state$internal_pickS
+     [Error_Undefined u_1;Error_See u_0;Error_Implementation_Defined u_0;Error_ReservedEncoding u_1;Error_ExceptionTaken u_1]))))`;
+
+
+(*val __GetVerbosity : unit -> M (bits ty64)*)
+
+(*val get_cycle_count : unit -> M ii*)
+
+(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*)
+
+val _ = Define `
+ ((InitRAM:int -> int -> 'm words$word ->(8)words$word -> unit) g__302 g__303 g__304 g__305=  () )`;
+
+
+(*val __ReadRAM : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> M (mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((ReadRAM:'m itself -> int -> 'm words$word -> 'm words$word ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr_length bytes hex_ram addr=
+    (let addr_length = (size_itself_int addr_length) in
+   (read_ram addr_length bytes hex_ram addr  : ( 'p8_times_n_ words$word) M)))`;
+
+
+(*val __TraceMemoryWrite : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*)
+
+(*val __WriteRAM : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> mword 'p8_times_n_ -> M unit*)
+
+val _ = Define `
+ ((WriteRAM:'m itself -> int -> 'm words$word -> 'm words$word -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr_length bytes hex_ram addr data=
+    (let addr_length = (size_itself_int addr_length) in
+   write_ram addr_length bytes hex_ram addr data))`;
+
+
+val _ = Define `
+ ((TraceMemoryWrite:int -> 'm words$word -> 'p8_times_n_ words$word -> unit) bytes addr data=  () )`;
+
+
+(*val __TraceMemoryRead : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*)
+
+val _ = Define `
+ ((TraceMemoryRead:int -> 'm words$word -> 'p8_times_n_ words$word -> unit) bytes addr data=  () )`;
+
+
+(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((extz_vec m__tv v  :  'm words$word)))`;
+
+
+(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((exts_vec m__tv v  :  'm words$word)))`;
+
+
+(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*)
+
+val _ = Define `
+ ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l=
+    (let (one1 : 'n bits) = ((extzv n__tv (vec_of_bits [B1]  :  1 words$word)  :  'n words$word)) in
+   (shiftl ((sub_vec ((shiftl one1 l  :  'n words$word)) one1  :  'n words$word)) i  :  'n words$word)))`;
+
+
+(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
+
+val _ = Define `
+ ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j=
+    (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
+
+
+(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
+
+val _ = Define `
+ ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j=
+    (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i))  :  'n words$word)) in
+   (((and_vec xs m  :  'n words$word)) = m)))`;
+
+
+(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*)
+
+val _ = Define `
+ ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   let ys =
+     ((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l'  :  'm words$word))  :  'm words$word)) i'
+       :  'm words$word)) in
+   (or_vec ((shiftl ((extzv r__tv xs  :  'r words$word)) l'  :  'r words$word)) ((extzv r__tv ys  :  'r words$word))
+     :  'r words$word)))`;
+
+
+(*val slice_zeros_concat : forall 'n   'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*)
+
+val _ = Define `
+ ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (shiftl ((extzv r__tv xs  :  'r words$word)) l'  :  'r words$word)))`;
+
+
+(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*)
+
+val _ = Define `
+ ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   let ys =
+     ((shiftr
+        ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j'))  :  'n words$word))  :  'n words$word))
+        j'
+       :  'n words$word)) in
+   (xs = ys)))`;
+
+
+(*val subrange_subrange_concat : forall 'n   'm   's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*)
+
+val _ = Define `
+ ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   let ys =
+     ((shiftr
+        ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j'))  :  'm words$word))  :  'm words$word))
+        j'
+       :  'm words$word)) in
+   (or_vec
+      ((sub_vec_int ((shiftl ((extzv s__tv xs  :  's words$word)) i'  :  's words$word))
+          ((j' - (( 1 : int):ii)))
+         :  's words$word)) ((extzv s__tv ys  :  's words$word))
+     :  's words$word)))`;
+
+
+(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
+
+
+(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
+
+
+(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (extzv m__tv xs  :  'm words$word)))`;
+
+
+(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l=
+    (let xs =
+     ((arith_shiftr
+        ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word))
+            ((((((int_of_num (words$word_len xs))) - i)) - l))
+           :  'n words$word)) ((((int_of_num (words$word_len xs))) - l))
+       :  'n words$word)) in
+   (extsv m__tv xs  :  'm words$word)))`;
+
+
+(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+
+val _ = Define `
+ ((unsigned_slice:'n words$word -> int -> int -> int) xs i l=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   lem$w2ui xs))`;
+
+
+(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+
+val _ = Define `
+ ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) i
+       :  'n words$word)) in
+   lem$w2ui xs))`;
+
+
+(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*)
+
+val _ = Define `
+ ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m=
+    (let (v : 'n bits) = ((extsv n__tv (vec_of_bits [B1]  :  1 words$word)  :  'n words$word)) in
+   (shiftr v ((((int_of_num (words$word_len v))) - m))  :  'n words$word)))`;
+
+
+(*val boolean_of_num : integer -> boolean*)
+
+val _ = Define `
+ ((boolean_of_num:int -> boolean) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FALSE
+   else TRUE))`;
+
+
+(*val num_of_boolean : boolean -> integer*)
+
+val _ = Define `
+ ((num_of_boolean:boolean -> int) arg_=  ((case arg_ of   FALSE => (( 0 : int):ii) | TRUE => (( 1 : int):ii) )))`;
+
+
+(*val undefined_boolean : unit -> M boolean*)
+
+val _ = Define `
+ ((undefined_boolean:unit ->(regstate)sail2_state_monad$sequential_state ->(((boolean),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [FALSE;TRUE]))`;
+
+
+(*val signal_of_num : integer -> signal*)
+
+val _ = Define `
+ ((signal_of_num:int -> signal) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then LOW
+   else HIGH))`;
+
+
+(*val num_of_signal : signal -> integer*)
+
+val _ = Define `
+ ((num_of_signal:signal -> int) arg_=  ((case arg_ of   LOW => (( 0 : int):ii) | HIGH => (( 1 : int):ii) )))`;
+
+
+(*val undefined_signal : unit -> M signal*)
+
+val _ = Define `
+ ((undefined_signal:unit ->(regstate)sail2_state_monad$sequential_state ->(((signal),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [LOW;HIGH]))`;
+
+
+(*val __RetCode_of_num : integer -> __RetCode*)
+
+val _ = Define `
+ ((RetCode_of_num:int -> RetCode) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RC_OK
+   else if (((p0_ = (( 1 : int):ii)))) then RC_UNDEFINED
+   else if (((p0_ = (( 2 : int):ii)))) then RC_UNPREDICTABLE
+   else if (((p0_ = (( 3 : int):ii)))) then RC_SEE
+   else if (((p0_ = (( 4 : int):ii)))) then RC_IMPLEMENTATION_DEFINED
+   else if (((p0_ = (( 5 : int):ii)))) then RC_SUBARCHITECTURE_DEFINED
+   else if (((p0_ = (( 6 : int):ii)))) then RC_EXCEPTION_TAKEN
+   else if (((p0_ = (( 7 : int):ii)))) then RC_ASSERT_FAILED
+   else RC_UNMATCHED_CASE))`;
+
+
+(*val num_of___RetCode : __RetCode -> integer*)
+
+val _ = Define `
+ ((num_of___RetCode:RetCode -> int) arg_=
+    ((case arg_ of
+     RC_OK => (( 0 : int):ii)
+   | RC_UNDEFINED => (( 1 : int):ii)
+   | RC_UNPREDICTABLE => (( 2 : int):ii)
+   | RC_SEE => (( 3 : int):ii)
+   | RC_IMPLEMENTATION_DEFINED => (( 4 : int):ii)
+   | RC_SUBARCHITECTURE_DEFINED => (( 5 : int):ii)
+   | RC_EXCEPTION_TAKEN => (( 6 : int):ii)
+   | RC_ASSERT_FAILED => (( 7 : int):ii)
+   | RC_UNMATCHED_CASE => (( 8 : int):ii)
+   )))`;
+
+
+(*val undefined___RetCode : unit -> M __RetCode*)
+
+val _ = Define `
+ ((undefined___RetCode:unit ->(regstate)sail2_state_monad$sequential_state ->(((RetCode),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [RC_OK;RC_UNDEFINED;RC_UNPREDICTABLE;RC_SEE;RC_IMPLEMENTATION_DEFINED;RC_SUBARCHITECTURE_DEFINED;RC_EXCEPTION_TAKEN;RC_ASSERT_FAILED;RC_UNMATCHED_CASE]))`;
+
+
+(*val FPConvOp_of_num : integer -> FPConvOp*)
+
+val _ = Define `
+ ((FPConvOp_of_num:int -> FPConvOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FPConvOp_CVT_FtoI
+   else if (((p0_ = (( 1 : int):ii)))) then FPConvOp_CVT_ItoF
+   else if (((p0_ = (( 2 : int):ii)))) then FPConvOp_MOV_FtoI
+   else if (((p0_ = (( 3 : int):ii)))) then FPConvOp_MOV_ItoF
+   else FPConvOp_CVT_FtoI_JS))`;
+
+
+(*val num_of_FPConvOp : FPConvOp -> integer*)
+
+val _ = Define `
+ ((num_of_FPConvOp:FPConvOp -> int) arg_=
+    ((case arg_ of
+     FPConvOp_CVT_FtoI => (( 0 : int):ii)
+   | FPConvOp_CVT_ItoF => (( 1 : int):ii)
+   | FPConvOp_MOV_FtoI => (( 2 : int):ii)
+   | FPConvOp_MOV_ItoF => (( 3 : int):ii)
+   | FPConvOp_CVT_FtoI_JS => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_FPConvOp : unit -> M FPConvOp*)
+
+val _ = Define `
+ ((undefined_FPConvOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPConvOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [FPConvOp_CVT_FtoI;FPConvOp_CVT_ItoF;FPConvOp_MOV_FtoI;FPConvOp_MOV_ItoF;FPConvOp_CVT_FtoI_JS]))`;
+
+
+(*val Exception_of_num : integer -> Exception*)
+
+val _ = Define `
+ ((Exception_of_num:int -> Exception) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Exception_Uncategorized
+   else if (((p0_ = (( 1 : int):ii)))) then Exception_WFxTrap
+   else if (((p0_ = (( 2 : int):ii)))) then Exception_CP15RTTrap
+   else if (((p0_ = (( 3 : int):ii)))) then Exception_CP15RRTTrap
+   else if (((p0_ = (( 4 : int):ii)))) then Exception_CP14RTTrap
+   else if (((p0_ = (( 5 : int):ii)))) then Exception_CP14DTTrap
+   else if (((p0_ = (( 6 : int):ii)))) then Exception_AdvSIMDFPAccessTrap
+   else if (((p0_ = (( 7 : int):ii)))) then Exception_FPIDTrap
+   else if (((p0_ = (( 8 : int):ii)))) then Exception_PACTrap
+   else if (((p0_ = (( 9 : int):ii)))) then Exception_CP14RRTTrap
+   else if (((p0_ = (( 10 : int):ii)))) then Exception_IllegalState
+   else if (((p0_ = (( 11 : int):ii)))) then Exception_SupervisorCall
+   else if (((p0_ = (( 12 : int):ii)))) then Exception_HypervisorCall
+   else if (((p0_ = (( 13 : int):ii)))) then Exception_MonitorCall
+   else if (((p0_ = (( 14 : int):ii)))) then Exception_SystemRegisterTrap
+   else if (((p0_ = (( 15 : int):ii)))) then Exception_ERetTrap
+   else if (((p0_ = (( 16 : int):ii)))) then Exception_InstructionAbort
+   else if (((p0_ = (( 17 : int):ii)))) then Exception_PCAlignment
+   else if (((p0_ = (( 18 : int):ii)))) then Exception_DataAbort
+   else if (((p0_ = (( 19 : int):ii)))) then Exception_SPAlignment
+   else if (((p0_ = (( 20 : int):ii)))) then Exception_FPTrappedException
+   else if (((p0_ = (( 21 : int):ii)))) then Exception_SError
+   else if (((p0_ = (( 22 : int):ii)))) then Exception_Breakpoint
+   else if (((p0_ = (( 23 : int):ii)))) then Exception_SoftwareStep
+   else if (((p0_ = (( 24 : int):ii)))) then Exception_Watchpoint
+   else if (((p0_ = (( 25 : int):ii)))) then Exception_SoftwareBreakpoint
+   else if (((p0_ = (( 26 : int):ii)))) then Exception_VectorCatch
+   else if (((p0_ = (( 27 : int):ii)))) then Exception_IRQ
+   else Exception_FIQ))`;
+
+
+(*val num_of_Exception : Exception -> integer*)
+
+val _ = Define `
+ ((num_of_Exception:Exception -> int) arg_=
+    ((case arg_ of
+     Exception_Uncategorized => (( 0 : int):ii)
+   | Exception_WFxTrap => (( 1 : int):ii)
+   | Exception_CP15RTTrap => (( 2 : int):ii)
+   | Exception_CP15RRTTrap => (( 3 : int):ii)
+   | Exception_CP14RTTrap => (( 4 : int):ii)
+   | Exception_CP14DTTrap => (( 5 : int):ii)
+   | Exception_AdvSIMDFPAccessTrap => (( 6 : int):ii)
+   | Exception_FPIDTrap => (( 7 : int):ii)
+   | Exception_PACTrap => (( 8 : int):ii)
+   | Exception_CP14RRTTrap => (( 9 : int):ii)
+   | Exception_IllegalState => (( 10 : int):ii)
+   | Exception_SupervisorCall => (( 11 : int):ii)
+   | Exception_HypervisorCall => (( 12 : int):ii)
+   | Exception_MonitorCall => (( 13 : int):ii)
+   | Exception_SystemRegisterTrap => (( 14 : int):ii)
+   | Exception_ERetTrap => (( 15 : int):ii)
+   | Exception_InstructionAbort => (( 16 : int):ii)
+   | Exception_PCAlignment => (( 17 : int):ii)
+   | Exception_DataAbort => (( 18 : int):ii)
+   | Exception_SPAlignment => (( 19 : int):ii)
+   | Exception_FPTrappedException => (( 20 : int):ii)
+   | Exception_SError => (( 21 : int):ii)
+   | Exception_Breakpoint => (( 22 : int):ii)
+   | Exception_SoftwareStep => (( 23 : int):ii)
+   | Exception_Watchpoint => (( 24 : int):ii)
+   | Exception_SoftwareBreakpoint => (( 25 : int):ii)
+   | Exception_VectorCatch => (( 26 : int):ii)
+   | Exception_IRQ => (( 27 : int):ii)
+   | Exception_FIQ => (( 28 : int):ii)
+   )))`;
+
+
+(*val undefined_Exception : unit -> M Exception*)
+
+val _ = Define `
+ ((undefined_Exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((Exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [Exception_Uncategorized;Exception_WFxTrap;Exception_CP15RTTrap;Exception_CP15RRTTrap;Exception_CP14RTTrap;Exception_CP14DTTrap;Exception_AdvSIMDFPAccessTrap;Exception_FPIDTrap;Exception_PACTrap;Exception_CP14RRTTrap;Exception_IllegalState;Exception_SupervisorCall;Exception_HypervisorCall;Exception_MonitorCall;Exception_SystemRegisterTrap;Exception_ERetTrap;Exception_InstructionAbort;Exception_PCAlignment;Exception_DataAbort;Exception_SPAlignment;Exception_FPTrappedException;Exception_SError;Exception_Breakpoint;Exception_SoftwareStep;Exception_Watchpoint;Exception_SoftwareBreakpoint;Exception_VectorCatch;Exception_IRQ;Exception_FIQ]))`;
+
+
+(*val ArchVersion_of_num : integer -> ArchVersion*)
+
+val _ = Define `
+ ((ArchVersion_of_num:int -> ArchVersion) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then ARMv8p0
+   else if (((p0_ = (( 1 : int):ii)))) then ARMv8p1
+   else if (((p0_ = (( 2 : int):ii)))) then ARMv8p2
+   else ARMv8p3))`;
+
+
+(*val num_of_ArchVersion : ArchVersion -> integer*)
+
+val _ = Define `
+ ((num_of_ArchVersion:ArchVersion -> int) arg_=
+    ((case arg_ of
+     ARMv8p0 => (( 0 : int):ii)
+   | ARMv8p1 => (( 1 : int):ii)
+   | ARMv8p2 => (( 2 : int):ii)
+   | ARMv8p3 => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_ArchVersion : unit -> M ArchVersion*)
+
+val _ = Define `
+ ((undefined_ArchVersion:unit ->(regstate)sail2_state_monad$sequential_state ->(((ArchVersion),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [ARMv8p0;ARMv8p1;ARMv8p2;ARMv8p3]))`;
+
+
+(*val Unpredictable_of_num : integer -> Unpredictable*)
+
+val _ = Define `
+ ((Unpredictable_of_num:int -> Unpredictable) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Unpredictable_WBOVERLAPLD
+   else if (((p0_ = (( 1 : int):ii)))) then Unpredictable_WBOVERLAPST
+   else if (((p0_ = (( 2 : int):ii)))) then Unpredictable_LDPOVERLAP
+   else if (((p0_ = (( 3 : int):ii)))) then Unpredictable_BASEOVERLAP
+   else if (((p0_ = (( 4 : int):ii)))) then Unpredictable_DATAOVERLAP
+   else if (((p0_ = (( 5 : int):ii)))) then Unpredictable_DEVPAGE2
+   else if (((p0_ = (( 6 : int):ii)))) then Unpredictable_INSTRDEVICE
+   else if (((p0_ = (( 7 : int):ii)))) then Unpredictable_RESCPACR
+   else if (((p0_ = (( 8 : int):ii)))) then Unpredictable_RESMAIR
+   else if (((p0_ = (( 9 : int):ii)))) then Unpredictable_RESTEXCB
+   else if (((p0_ = (( 10 : int):ii)))) then Unpredictable_RESPRRR
+   else if (((p0_ = (( 11 : int):ii)))) then Unpredictable_RESDACR
+   else if (((p0_ = (( 12 : int):ii)))) then Unpredictable_RESVTCRS
+   else if (((p0_ = (( 13 : int):ii)))) then Unpredictable_RESTnSZ
+   else if (((p0_ = (( 14 : int):ii)))) then Unpredictable_OORTnSZ
+   else if (((p0_ = (( 15 : int):ii)))) then Unpredictable_LARGEIPA
+   else if (((p0_ = (( 16 : int):ii)))) then Unpredictable_ESRCONDPASS
+   else if (((p0_ = (( 17 : int):ii)))) then Unpredictable_ILZEROIT
+   else if (((p0_ = (( 18 : int):ii)))) then Unpredictable_ILZEROT
+   else if (((p0_ = (( 19 : int):ii)))) then Unpredictable_BPVECTORCATCHPRI
+   else if (((p0_ = (( 20 : int):ii)))) then Unpredictable_VCMATCHHALF
+   else if (((p0_ = (( 21 : int):ii)))) then Unpredictable_VCMATCHDAPA
+   else if (((p0_ = (( 22 : int):ii)))) then Unpredictable_WPMASKANDBAS
+   else if (((p0_ = (( 23 : int):ii)))) then Unpredictable_WPBASCONTIGUOUS
+   else if (((p0_ = (( 24 : int):ii)))) then Unpredictable_RESWPMASK
+   else if (((p0_ = (( 25 : int):ii)))) then Unpredictable_WPMASKEDBITS
+   else if (((p0_ = (( 26 : int):ii)))) then Unpredictable_RESBPWPCTRL
+   else if (((p0_ = (( 27 : int):ii)))) then Unpredictable_BPNOTIMPL
+   else if (((p0_ = (( 28 : int):ii)))) then Unpredictable_RESBPTYPE
+   else if (((p0_ = (( 29 : int):ii)))) then Unpredictable_BPNOTCTXCMP
+   else if (((p0_ = (( 30 : int):ii)))) then Unpredictable_BPMATCHHALF
+   else if (((p0_ = (( 31 : int):ii)))) then Unpredictable_BPMISMATCHHALF
+   else if (((p0_ = (( 32 : int):ii)))) then Unpredictable_RESTARTALIGNPC
+   else if (((p0_ = (( 33 : int):ii)))) then Unpredictable_RESTARTZEROUPPERPC
+   else if (((p0_ = (( 34 : int):ii)))) then Unpredictable_ZEROUPPER
+   else if (((p0_ = (( 35 : int):ii)))) then Unpredictable_ERETZEROUPPERPC
+   else if (((p0_ = (( 36 : int):ii)))) then Unpredictable_A32FORCEALIGNPC
+   else if (((p0_ = (( 37 : int):ii)))) then Unpredictable_SMD
+   else if (((p0_ = (( 38 : int):ii)))) then Unpredictable_AFUPDATE
+   else if (((p0_ = (( 39 : int):ii)))) then Unpredictable_IESBinDebug
+   else if (((p0_ = (( 40 : int):ii)))) then Unpredictable_ZEROPMSEVFR
+   else if (((p0_ = (( 41 : int):ii)))) then Unpredictable_NOOPTYPES
+   else if (((p0_ = (( 42 : int):ii)))) then Unpredictable_ZEROMINLATENCY
+   else if (((p0_ = (( 43 : int):ii)))) then Unpredictable_CLEARERRITEZERO
+   else Unpredictable_TBD))`;
+
+
+(*val num_of_Unpredictable : Unpredictable -> integer*)
+
+val _ = Define `
+ ((num_of_Unpredictable:Unpredictable -> int) arg_=
+    ((case arg_ of
+     Unpredictable_WBOVERLAPLD => (( 0 : int):ii)
+   | Unpredictable_WBOVERLAPST => (( 1 : int):ii)
+   | Unpredictable_LDPOVERLAP => (( 2 : int):ii)
+   | Unpredictable_BASEOVERLAP => (( 3 : int):ii)
+   | Unpredictable_DATAOVERLAP => (( 4 : int):ii)
+   | Unpredictable_DEVPAGE2 => (( 5 : int):ii)
+   | Unpredictable_INSTRDEVICE => (( 6 : int):ii)
+   | Unpredictable_RESCPACR => (( 7 : int):ii)
+   | Unpredictable_RESMAIR => (( 8 : int):ii)
+   | Unpredictable_RESTEXCB => (( 9 : int):ii)
+   | Unpredictable_RESPRRR => (( 10 : int):ii)
+   | Unpredictable_RESDACR => (( 11 : int):ii)
+   | Unpredictable_RESVTCRS => (( 12 : int):ii)
+   | Unpredictable_RESTnSZ => (( 13 : int):ii)
+   | Unpredictable_OORTnSZ => (( 14 : int):ii)
+   | Unpredictable_LARGEIPA => (( 15 : int):ii)
+   | Unpredictable_ESRCONDPASS => (( 16 : int):ii)
+   | Unpredictable_ILZEROIT => (( 17 : int):ii)
+   | Unpredictable_ILZEROT => (( 18 : int):ii)
+   | Unpredictable_BPVECTORCATCHPRI => (( 19 : int):ii)
+   | Unpredictable_VCMATCHHALF => (( 20 : int):ii)
+   | Unpredictable_VCMATCHDAPA => (( 21 : int):ii)
+   | Unpredictable_WPMASKANDBAS => (( 22 : int):ii)
+   | Unpredictable_WPBASCONTIGUOUS => (( 23 : int):ii)
+   | Unpredictable_RESWPMASK => (( 24 : int):ii)
+   | Unpredictable_WPMASKEDBITS => (( 25 : int):ii)
+   | Unpredictable_RESBPWPCTRL => (( 26 : int):ii)
+   | Unpredictable_BPNOTIMPL => (( 27 : int):ii)
+   | Unpredictable_RESBPTYPE => (( 28 : int):ii)
+   | Unpredictable_BPNOTCTXCMP => (( 29 : int):ii)
+   | Unpredictable_BPMATCHHALF => (( 30 : int):ii)
+   | Unpredictable_BPMISMATCHHALF => (( 31 : int):ii)
+   | Unpredictable_RESTARTALIGNPC => (( 32 : int):ii)
+   | Unpredictable_RESTARTZEROUPPERPC => (( 33 : int):ii)
+   | Unpredictable_ZEROUPPER => (( 34 : int):ii)
+   | Unpredictable_ERETZEROUPPERPC => (( 35 : int):ii)
+   | Unpredictable_A32FORCEALIGNPC => (( 36 : int):ii)
+   | Unpredictable_SMD => (( 37 : int):ii)
+   | Unpredictable_AFUPDATE => (( 38 : int):ii)
+   | Unpredictable_IESBinDebug => (( 39 : int):ii)
+   | Unpredictable_ZEROPMSEVFR => (( 40 : int):ii)
+   | Unpredictable_NOOPTYPES => (( 41 : int):ii)
+   | Unpredictable_ZEROMINLATENCY => (( 42 : int):ii)
+   | Unpredictable_CLEARERRITEZERO => (( 43 : int):ii)
+   | Unpredictable_TBD => (( 44 : int):ii)
+   )))`;
+
+
+(*val undefined_Unpredictable : unit -> M Unpredictable*)
+
+val _ = Define `
+ ((undefined_Unpredictable:unit ->(regstate)sail2_state_monad$sequential_state ->(((Unpredictable),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [Unpredictable_WBOVERLAPLD;Unpredictable_WBOVERLAPST;Unpredictable_LDPOVERLAP;Unpredictable_BASEOVERLAP;Unpredictable_DATAOVERLAP;Unpredictable_DEVPAGE2;Unpredictable_INSTRDEVICE;Unpredictable_RESCPACR;Unpredictable_RESMAIR;Unpredictable_RESTEXCB;Unpredictable_RESPRRR;Unpredictable_RESDACR;Unpredictable_RESVTCRS;Unpredictable_RESTnSZ;Unpredictable_OORTnSZ;Unpredictable_LARGEIPA;Unpredictable_ESRCONDPASS;Unpredictable_ILZEROIT;Unpredictable_ILZEROT;Unpredictable_BPVECTORCATCHPRI;Unpredictable_VCMATCHHALF;Unpredictable_VCMATCHDAPA;Unpredictable_WPMASKANDBAS;Unpredictable_WPBASCONTIGUOUS;Unpredictable_RESWPMASK;Unpredictable_WPMASKEDBITS;Unpredictable_RESBPWPCTRL;Unpredictable_BPNOTIMPL;Unpredictable_RESBPTYPE;Unpredictable_BPNOTCTXCMP;Unpredictable_BPMATCHHALF;Unpredictable_BPMISMATCHHALF;Unpredictable_RESTARTALIGNPC;Unpredictable_RESTARTZEROUPPERPC;Unpredictable_ZEROUPPER;Unpredictable_ERETZEROUPPERPC;Unpredictable_A32FORCEALIGNPC;Unpredictable_SMD;Unpredictable_AFUPDATE;Unpredictable_IESBinDebug;Unpredictable_ZEROPMSEVFR;Unpredictable_NOOPTYPES;Unpredictable_ZEROMINLATENCY;Unpredictable_CLEARERRITEZERO;Unpredictable_TBD]))`;
+
+
+(*val Constraint_of_num : integer -> Constraint*)
+
+val _ = Define `
+ ((Constraint_of_num:int -> Constraint) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Constraint_NONE
+   else if (((p0_ = (( 1 : int):ii)))) then Constraint_UNKNOWN
+   else if (((p0_ = (( 2 : int):ii)))) then Constraint_UNDEF
+   else if (((p0_ = (( 3 : int):ii)))) then Constraint_UNDEFEL0
+   else if (((p0_ = (( 4 : int):ii)))) then Constraint_NOP
+   else if (((p0_ = (( 5 : int):ii)))) then Constraint_TRUE
+   else if (((p0_ = (( 6 : int):ii)))) then Constraint_FALSE
+   else if (((p0_ = (( 7 : int):ii)))) then Constraint_DISABLED
+   else if (((p0_ = (( 8 : int):ii)))) then Constraint_UNCOND
+   else if (((p0_ = (( 9 : int):ii)))) then Constraint_COND
+   else if (((p0_ = (( 10 : int):ii)))) then Constraint_ADDITIONAL_DECODE
+   else if (((p0_ = (( 11 : int):ii)))) then Constraint_WBSUPPRESS
+   else if (((p0_ = (( 12 : int):ii)))) then Constraint_FAULT
+   else if (((p0_ = (( 13 : int):ii)))) then Constraint_FORCE
+   else Constraint_FORCENOSLCHECK))`;
+
+
+(*val num_of_Constraint : Constraint -> integer*)
+
+val _ = Define `
+ ((num_of_Constraint:Constraint -> int) arg_=
+    ((case arg_ of
+     Constraint_NONE => (( 0 : int):ii)
+   | Constraint_UNKNOWN => (( 1 : int):ii)
+   | Constraint_UNDEF => (( 2 : int):ii)
+   | Constraint_UNDEFEL0 => (( 3 : int):ii)
+   | Constraint_NOP => (( 4 : int):ii)
+   | Constraint_TRUE => (( 5 : int):ii)
+   | Constraint_FALSE => (( 6 : int):ii)
+   | Constraint_DISABLED => (( 7 : int):ii)
+   | Constraint_UNCOND => (( 8 : int):ii)
+   | Constraint_COND => (( 9 : int):ii)
+   | Constraint_ADDITIONAL_DECODE => (( 10 : int):ii)
+   | Constraint_WBSUPPRESS => (( 11 : int):ii)
+   | Constraint_FAULT => (( 12 : int):ii)
+   | Constraint_FORCE => (( 13 : int):ii)
+   | Constraint_FORCENOSLCHECK => (( 14 : int):ii)
+   )))`;
+
+
+(*val undefined_Constraint : unit -> M Constraint*)
+
+val _ = Define `
+ ((undefined_Constraint:unit ->(regstate)sail2_state_monad$sequential_state ->(((Constraint),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [Constraint_NONE;Constraint_UNKNOWN;Constraint_UNDEF;Constraint_UNDEFEL0;Constraint_NOP;Constraint_TRUE;Constraint_FALSE;Constraint_DISABLED;Constraint_UNCOND;Constraint_COND;Constraint_ADDITIONAL_DECODE;Constraint_WBSUPPRESS;Constraint_FAULT;Constraint_FORCE;Constraint_FORCENOSLCHECK]))`;
+
+
+(*val InstrSet_of_num : integer -> InstrSet*)
+
+val _ = Define `
+ ((InstrSet_of_num:int -> InstrSet) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then InstrSet_A64
+   else if (((p0_ = (( 1 : int):ii)))) then InstrSet_A32
+   else InstrSet_T32))`;
+
+
+(*val num_of_InstrSet : InstrSet -> integer*)
+
+val _ = Define `
+ ((num_of_InstrSet:InstrSet -> int) arg_=
+    ((case arg_ of   InstrSet_A64 => (( 0 : int):ii) | InstrSet_A32 => (( 1 : int):ii) | InstrSet_T32 => (( 2 : int):ii) )))`;
+
+
+(*val undefined_InstrSet : unit -> M InstrSet*)
+
+val _ = Define `
+ ((undefined_InstrSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((InstrSet),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [InstrSet_A64;InstrSet_A32;InstrSet_T32]))`;
+
+
+(*val undefined_ProcState : unit -> M ProcState*)
+
+val _ = Define `
+ ((undefined_ProcState:unit ->(regstate)sail2_state_monad$sequential_state ->(((ProcState),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__0 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__3 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__4 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__5 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__6 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__7 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__8 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__9 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__11 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__12 : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__13 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__14 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__15 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__16 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (w__17 : 8 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__18 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__19 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__20 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__21 : 5 bits) . 
+   sail2_state_monad$returnS (<| ProcState_N := w__0; 
+              ProcState_Z := w__1; 
+              ProcState_C := w__2; 
+              ProcState_V := w__3; 
+              ProcState_D := w__4; 
+              ProcState_A := w__5; 
+              ProcState_I := w__6; 
+              ProcState_F := w__7; 
+              ProcState_PAN := w__8; 
+              ProcState_UAO := w__9; 
+              ProcState_SS := w__10; 
+              ProcState_IL := w__11; 
+              ProcState_EL := w__12; 
+              ProcState_nRW := w__13; 
+              ProcState_SP := w__14; 
+              ProcState_Q := w__15; 
+              ProcState_GE := w__16; 
+              ProcState_IT := w__17; 
+              ProcState_J := w__18; 
+              ProcState_T := w__19; 
+              ProcState_E := w__20; 
+              ProcState_M := w__21 |>)))))))))))))))))))))))))`;
+
+
+(*val BranchType_of_num : integer -> BranchType*)
+
+val _ = Define `
+ ((BranchType_of_num:int -> BranchType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then BranchType_CALL
+   else if (((p0_ = (( 1 : int):ii)))) then BranchType_ERET
+   else if (((p0_ = (( 2 : int):ii)))) then BranchType_DBGEXIT
+   else if (((p0_ = (( 3 : int):ii)))) then BranchType_RET
+   else if (((p0_ = (( 4 : int):ii)))) then BranchType_JMP
+   else if (((p0_ = (( 5 : int):ii)))) then BranchType_EXCEPTION
+   else BranchType_UNKNOWN))`;
+
+
+(*val num_of_BranchType : BranchType -> integer*)
+
+val _ = Define `
+ ((num_of_BranchType:BranchType -> int) arg_=
+    ((case arg_ of
+     BranchType_CALL => (( 0 : int):ii)
+   | BranchType_ERET => (( 1 : int):ii)
+   | BranchType_DBGEXIT => (( 2 : int):ii)
+   | BranchType_RET => (( 3 : int):ii)
+   | BranchType_JMP => (( 4 : int):ii)
+   | BranchType_EXCEPTION => (( 5 : int):ii)
+   | BranchType_UNKNOWN => (( 6 : int):ii)
+   )))`;
+
+
+(*val undefined_BranchType : unit -> M BranchType*)
+
+val _ = Define `
+ ((undefined_BranchType:unit ->(regstate)sail2_state_monad$sequential_state ->(((BranchType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [BranchType_CALL;BranchType_ERET;BranchType_DBGEXIT;BranchType_RET;BranchType_JMP;BranchType_EXCEPTION;BranchType_UNKNOWN]))`;
+
+
+(*val undefined_ExceptionRecord : unit -> M ExceptionRecord*)
+
+val _ = Define `
+ ((undefined_ExceptionRecord:unit ->(regstate)sail2_state_monad$sequential_state ->(((ExceptionRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_Exception () ) (\ (w__0 : Exception) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 25 : int):ii)  : ( 25 words$word) M) (\ (w__1 : 25 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (w__4 : 52 bits) . 
+   sail2_state_monad$returnS (<| ExceptionRecord_typ := w__0; 
+              ExceptionRecord_syndrome := w__1; 
+              ExceptionRecord_vaddress := w__2; 
+              ExceptionRecord_ipavalid := w__3; 
+              ExceptionRecord_ipaddress := w__4 |>))))))))`;
+
+
+(*val Fault_of_num : integer -> Fault*)
+
+val _ = Define `
+ ((Fault_of_num:int -> Fault) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Fault_None
+   else if (((p0_ = (( 1 : int):ii)))) then Fault_AccessFlag
+   else if (((p0_ = (( 2 : int):ii)))) then Fault_Alignment
+   else if (((p0_ = (( 3 : int):ii)))) then Fault_Background
+   else if (((p0_ = (( 4 : int):ii)))) then Fault_Domain
+   else if (((p0_ = (( 5 : int):ii)))) then Fault_Permission
+   else if (((p0_ = (( 6 : int):ii)))) then Fault_Translation
+   else if (((p0_ = (( 7 : int):ii)))) then Fault_AddressSize
+   else if (((p0_ = (( 8 : int):ii)))) then Fault_SyncExternal
+   else if (((p0_ = (( 9 : int):ii)))) then Fault_SyncExternalOnWalk
+   else if (((p0_ = (( 10 : int):ii)))) then Fault_SyncParity
+   else if (((p0_ = (( 11 : int):ii)))) then Fault_SyncParityOnWalk
+   else if (((p0_ = (( 12 : int):ii)))) then Fault_AsyncParity
+   else if (((p0_ = (( 13 : int):ii)))) then Fault_AsyncExternal
+   else if (((p0_ = (( 14 : int):ii)))) then Fault_Debug
+   else if (((p0_ = (( 15 : int):ii)))) then Fault_TLBConflict
+   else if (((p0_ = (( 16 : int):ii)))) then Fault_Lockdown
+   else if (((p0_ = (( 17 : int):ii)))) then Fault_Exclusive
+   else Fault_ICacheMaint))`;
+
+
+(*val num_of_Fault : Fault -> integer*)
+
+val _ = Define `
+ ((num_of_Fault:Fault -> int) arg_=
+    ((case arg_ of
+     Fault_None => (( 0 : int):ii)
+   | Fault_AccessFlag => (( 1 : int):ii)
+   | Fault_Alignment => (( 2 : int):ii)
+   | Fault_Background => (( 3 : int):ii)
+   | Fault_Domain => (( 4 : int):ii)
+   | Fault_Permission => (( 5 : int):ii)
+   | Fault_Translation => (( 6 : int):ii)
+   | Fault_AddressSize => (( 7 : int):ii)
+   | Fault_SyncExternal => (( 8 : int):ii)
+   | Fault_SyncExternalOnWalk => (( 9 : int):ii)
+   | Fault_SyncParity => (( 10 : int):ii)
+   | Fault_SyncParityOnWalk => (( 11 : int):ii)
+   | Fault_AsyncParity => (( 12 : int):ii)
+   | Fault_AsyncExternal => (( 13 : int):ii)
+   | Fault_Debug => (( 14 : int):ii)
+   | Fault_TLBConflict => (( 15 : int):ii)
+   | Fault_Lockdown => (( 16 : int):ii)
+   | Fault_Exclusive => (( 17 : int):ii)
+   | Fault_ICacheMaint => (( 18 : int):ii)
+   )))`;
+
+
+(*val undefined_Fault : unit -> M Fault*)
+
+val _ = Define `
+ ((undefined_Fault:unit ->(regstate)sail2_state_monad$sequential_state ->(((Fault),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [Fault_None;Fault_AccessFlag;Fault_Alignment;Fault_Background;Fault_Domain;Fault_Permission;Fault_Translation;Fault_AddressSize;Fault_SyncExternal;Fault_SyncExternalOnWalk;Fault_SyncParity;Fault_SyncParityOnWalk;Fault_AsyncParity;Fault_AsyncExternal;Fault_Debug;Fault_TLBConflict;Fault_Lockdown;Fault_Exclusive;Fault_ICacheMaint]))`;
+
+
+(*val AccType_of_num : integer -> AccType*)
+
+val _ = Define `
+ ((AccType_of_num:int -> AccType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then AccType_NORMAL
+   else if (((p0_ = (( 1 : int):ii)))) then AccType_VEC
+   else if (((p0_ = (( 2 : int):ii)))) then AccType_STREAM
+   else if (((p0_ = (( 3 : int):ii)))) then AccType_VECSTREAM
+   else if (((p0_ = (( 4 : int):ii)))) then AccType_ATOMIC
+   else if (((p0_ = (( 5 : int):ii)))) then AccType_ATOMICRW
+   else if (((p0_ = (( 6 : int):ii)))) then AccType_ORDERED
+   else if (((p0_ = (( 7 : int):ii)))) then AccType_ORDEREDRW
+   else if (((p0_ = (( 8 : int):ii)))) then AccType_LIMITEDORDERED
+   else if (((p0_ = (( 9 : int):ii)))) then AccType_UNPRIV
+   else if (((p0_ = (( 10 : int):ii)))) then AccType_IFETCH
+   else if (((p0_ = (( 11 : int):ii)))) then AccType_PTW
+   else if (((p0_ = (( 12 : int):ii)))) then AccType_DC
+   else if (((p0_ = (( 13 : int):ii)))) then AccType_IC
+   else if (((p0_ = (( 14 : int):ii)))) then AccType_DCZVA
+   else AccType_AT))`;
+
+
+(*val num_of_AccType : AccType -> integer*)
+
+val _ = Define `
+ ((num_of_AccType:AccType -> int) arg_=
+    ((case arg_ of
+     AccType_NORMAL => (( 0 : int):ii)
+   | AccType_VEC => (( 1 : int):ii)
+   | AccType_STREAM => (( 2 : int):ii)
+   | AccType_VECSTREAM => (( 3 : int):ii)
+   | AccType_ATOMIC => (( 4 : int):ii)
+   | AccType_ATOMICRW => (( 5 : int):ii)
+   | AccType_ORDERED => (( 6 : int):ii)
+   | AccType_ORDEREDRW => (( 7 : int):ii)
+   | AccType_LIMITEDORDERED => (( 8 : int):ii)
+   | AccType_UNPRIV => (( 9 : int):ii)
+   | AccType_IFETCH => (( 10 : int):ii)
+   | AccType_PTW => (( 11 : int):ii)
+   | AccType_DC => (( 12 : int):ii)
+   | AccType_IC => (( 13 : int):ii)
+   | AccType_DCZVA => (( 14 : int):ii)
+   | AccType_AT => (( 15 : int):ii)
+   )))`;
+
+
+(*val undefined_AccType : unit -> M AccType*)
+
+val _ = Define `
+ ((undefined_AccType:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [AccType_NORMAL;AccType_VEC;AccType_STREAM;AccType_VECSTREAM;AccType_ATOMIC;AccType_ATOMICRW;AccType_ORDERED;AccType_ORDEREDRW;AccType_LIMITEDORDERED;AccType_UNPRIV;AccType_IFETCH;AccType_PTW;AccType_DC;AccType_IC;AccType_DCZVA;AccType_AT]))`;
+
+
+(*val undefined_FaultRecord : unit -> M FaultRecord*)
+
+val _ = Define `
+ ((undefined_FaultRecord:unit ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_Fault () ) (\ (w__0 : Fault) .  sail2_state_monad$bindS
+   (undefined_AccType () ) (\ (w__1 : AccType) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (w__2 : 52 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__4 : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (w__5 : ii) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__6 : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__7 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__8 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__9 : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__10 : 4 bits) . 
+   sail2_state_monad$returnS (<| FaultRecord_typ := w__0; 
+              FaultRecord_acctype := w__1; 
+              FaultRecord_ipaddress := w__2; 
+              FaultRecord_s2fs1walk := w__3; 
+              FaultRecord_write := w__4; 
+              FaultRecord_level := w__5; 
+              FaultRecord_extflag := w__6; 
+              FaultRecord_secondstage := w__7; 
+              FaultRecord_domain := w__8; 
+              FaultRecord_errortype := w__9; 
+              FaultRecord_debugmoe := w__10 |>))))))))))))))`;
+
+
+(*val MBReqDomain_of_num : integer -> MBReqDomain*)
+
+val _ = Define `
+ ((MBReqDomain_of_num:int -> MBReqDomain) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MBReqDomain_Nonshareable
+   else if (((p0_ = (( 1 : int):ii)))) then MBReqDomain_InnerShareable
+   else if (((p0_ = (( 2 : int):ii)))) then MBReqDomain_OuterShareable
+   else MBReqDomain_FullSystem))`;
+
+
+(*val num_of_MBReqDomain : MBReqDomain -> integer*)
+
+val _ = Define `
+ ((num_of_MBReqDomain:MBReqDomain -> int) arg_=
+    ((case arg_ of
+     MBReqDomain_Nonshareable => (( 0 : int):ii)
+   | MBReqDomain_InnerShareable => (( 1 : int):ii)
+   | MBReqDomain_OuterShareable => (( 2 : int):ii)
+   | MBReqDomain_FullSystem => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_MBReqDomain : unit -> M MBReqDomain*)
+
+val _ = Define `
+ ((undefined_MBReqDomain:unit ->(regstate)sail2_state_monad$sequential_state ->(((MBReqDomain),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [MBReqDomain_Nonshareable;MBReqDomain_InnerShareable;MBReqDomain_OuterShareable;MBReqDomain_FullSystem]))`;
+
+
+(*val MBReqTypes_of_num : integer -> MBReqTypes*)
+
+val _ = Define `
+ ((MBReqTypes_of_num:int -> MBReqTypes) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MBReqTypes_Reads
+   else if (((p0_ = (( 1 : int):ii)))) then MBReqTypes_Writes
+   else MBReqTypes_All))`;
+
+
+(*val num_of_MBReqTypes : MBReqTypes -> integer*)
+
+val _ = Define `
+ ((num_of_MBReqTypes:MBReqTypes -> int) arg_=
+    ((case arg_ of
+     MBReqTypes_Reads => (( 0 : int):ii)
+   | MBReqTypes_Writes => (( 1 : int):ii)
+   | MBReqTypes_All => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_MBReqTypes : unit -> M MBReqTypes*)
+
+val _ = Define `
+ ((undefined_MBReqTypes:unit ->(regstate)sail2_state_monad$sequential_state ->(((MBReqTypes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [MBReqTypes_Reads;MBReqTypes_Writes;MBReqTypes_All]))`;
+
+
+(*val MemType_of_num : integer -> MemType*)
+
+val _ = Define `
+ ((MemType_of_num:int -> MemType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MemType_Normal
+   else MemType_Device))`;
+
+
+(*val num_of_MemType : MemType -> integer*)
+
+val _ = Define `
+ ((num_of_MemType:MemType -> int) arg_=  ((case arg_ of   MemType_Normal => (( 0 : int):ii) | MemType_Device => (( 1 : int):ii) )))`;
+
+
+(*val undefined_MemType : unit -> M MemType*)
+
+val _ = Define `
+ ((undefined_MemType:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [MemType_Normal;MemType_Device]))`;
+
+
+(*val DeviceType_of_num : integer -> DeviceType*)
+
+val _ = Define `
+ ((DeviceType_of_num:int -> DeviceType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then DeviceType_GRE
+   else if (((p0_ = (( 1 : int):ii)))) then DeviceType_nGRE
+   else if (((p0_ = (( 2 : int):ii)))) then DeviceType_nGnRE
+   else DeviceType_nGnRnE))`;
+
+
+(*val num_of_DeviceType : DeviceType -> integer*)
+
+val _ = Define `
+ ((num_of_DeviceType:DeviceType -> int) arg_=
+    ((case arg_ of
+     DeviceType_GRE => (( 0 : int):ii)
+   | DeviceType_nGRE => (( 1 : int):ii)
+   | DeviceType_nGnRE => (( 2 : int):ii)
+   | DeviceType_nGnRnE => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_DeviceType : unit -> M DeviceType*)
+
+val _ = Define `
+ ((undefined_DeviceType:unit ->(regstate)sail2_state_monad$sequential_state ->(((DeviceType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [DeviceType_GRE;DeviceType_nGRE;DeviceType_nGnRE;DeviceType_nGnRnE]))`;
+
+
+(*val undefined_MemAttrHints : unit -> M MemAttrHints*)
+
+val _ = Define `
+ ((undefined_MemAttrHints:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__0 : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__1 : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__2 : bool) . 
+   sail2_state_monad$returnS (<| MemAttrHints_attrs := w__0; 
+              MemAttrHints_hints := w__1; 
+              MemAttrHints_transient := w__2 |>))))))`;
+
+
+(*val undefined_MemoryAttributes : unit -> M MemoryAttributes*)
+
+val _ = Define `
+ ((undefined_MemoryAttributes:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_MemType () ) (\ (w__0 : MemType) .  sail2_state_monad$bindS
+   (undefined_DeviceType () ) (\ (w__1 : DeviceType) .  sail2_state_monad$bindS
+   (undefined_MemAttrHints () ) (\ (w__2 : MemAttrHints) .  sail2_state_monad$bindS
+   (undefined_MemAttrHints () ) (\ (w__3 : MemAttrHints) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__4 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__5 : bool) . 
+   sail2_state_monad$returnS (<| MemoryAttributes_typ := w__0; 
+              MemoryAttributes_device := w__1; 
+              MemoryAttributes_inner := w__2; 
+              MemoryAttributes_outer := w__3; 
+              MemoryAttributes_shareable := w__4; 
+              MemoryAttributes_outershareable := w__5 |>)))))))))`;
+
+
+(*val undefined_FullAddress : unit -> M FullAddress*)
+
+val _ = Define `
+ ((undefined_FullAddress:unit ->(regstate)sail2_state_monad$sequential_state ->(((FullAddress),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (w__0 : 52 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
+   sail2_state_monad$returnS (<| FullAddress_physicaladdress := w__0; 
+              FullAddress_NS := w__1 |>)))))`;
+
+
+(*val undefined_AddressDescriptor : unit -> M AddressDescriptor*)
+
+val _ = Define `
+ ((undefined_AddressDescriptor:unit ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_FaultRecord () ) (\ (w__0 : FaultRecord) .  sail2_state_monad$bindS
+   (undefined_MemoryAttributes () ) (\ (w__1 : MemoryAttributes) .  sail2_state_monad$bindS
+   (undefined_FullAddress () ) (\ (w__2 : FullAddress) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+   sail2_state_monad$returnS (<| AddressDescriptor_fault := w__0; 
+              AddressDescriptor_memattrs := w__1; 
+              AddressDescriptor_paddress := w__2; 
+              AddressDescriptor_vaddress := w__3 |>)))))))`;
+
+
+(*val undefined_DescriptorUpdate : unit -> M DescriptorUpdate*)
+
+val _ = Define `
+ ((undefined_DescriptorUpdate:unit ->(regstate)sail2_state_monad$sequential_state ->(((DescriptorUpdate),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) .  sail2_state_monad$bindS
+   (undefined_AddressDescriptor () ) (\ (w__2 : AddressDescriptor) . 
+   sail2_state_monad$returnS (<| DescriptorUpdate_AF := w__0; 
+              DescriptorUpdate_AP := w__1; 
+              DescriptorUpdate_descaddr := w__2 |>))))))`;
+
+
+(*val MemAtomicOp_of_num : integer -> MemAtomicOp*)
+
+val _ = Define `
+ ((MemAtomicOp_of_num:int -> MemAtomicOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MemAtomicOp_ADD
+   else if (((p0_ = (( 1 : int):ii)))) then MemAtomicOp_BIC
+   else if (((p0_ = (( 2 : int):ii)))) then MemAtomicOp_EOR
+   else if (((p0_ = (( 3 : int):ii)))) then MemAtomicOp_ORR
+   else if (((p0_ = (( 4 : int):ii)))) then MemAtomicOp_SMAX
+   else if (((p0_ = (( 5 : int):ii)))) then MemAtomicOp_SMIN
+   else if (((p0_ = (( 6 : int):ii)))) then MemAtomicOp_UMAX
+   else if (((p0_ = (( 7 : int):ii)))) then MemAtomicOp_UMIN
+   else MemAtomicOp_SWP))`;
+
+
+(*val num_of_MemAtomicOp : MemAtomicOp -> integer*)
+
+val _ = Define `
+ ((num_of_MemAtomicOp:MemAtomicOp -> int) arg_=
+    ((case arg_ of
+     MemAtomicOp_ADD => (( 0 : int):ii)
+   | MemAtomicOp_BIC => (( 1 : int):ii)
+   | MemAtomicOp_EOR => (( 2 : int):ii)
+   | MemAtomicOp_ORR => (( 3 : int):ii)
+   | MemAtomicOp_SMAX => (( 4 : int):ii)
+   | MemAtomicOp_SMIN => (( 5 : int):ii)
+   | MemAtomicOp_UMAX => (( 6 : int):ii)
+   | MemAtomicOp_UMIN => (( 7 : int):ii)
+   | MemAtomicOp_SWP => (( 8 : int):ii)
+   )))`;
+
+
+(*val undefined_MemAtomicOp : unit -> M MemAtomicOp*)
+
+val _ = Define `
+ ((undefined_MemAtomicOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAtomicOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [MemAtomicOp_ADD;MemAtomicOp_BIC;MemAtomicOp_EOR;MemAtomicOp_ORR;MemAtomicOp_SMAX;MemAtomicOp_SMIN;MemAtomicOp_UMAX;MemAtomicOp_UMIN;MemAtomicOp_SWP]))`;
+
+
+(*val FPType_of_num : integer -> FPType*)
+
+val _ = Define `
+ ((FPType_of_num:int -> FPType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FPType_Nonzero
+   else if (((p0_ = (( 1 : int):ii)))) then FPType_Zero
+   else if (((p0_ = (( 2 : int):ii)))) then FPType_Infinity
+   else if (((p0_ = (( 3 : int):ii)))) then FPType_QNaN
+   else FPType_SNaN))`;
+
+
+(*val num_of_FPType : FPType -> integer*)
+
+val _ = Define `
+ ((num_of_FPType:FPType -> int) arg_=
+    ((case arg_ of
+     FPType_Nonzero => (( 0 : int):ii)
+   | FPType_Zero => (( 1 : int):ii)
+   | FPType_Infinity => (( 2 : int):ii)
+   | FPType_QNaN => (( 3 : int):ii)
+   | FPType_SNaN => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_FPType : unit -> M FPType*)
+
+val _ = Define `
+ ((undefined_FPType:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [FPType_Nonzero;FPType_Zero;FPType_Infinity;FPType_QNaN;FPType_SNaN]))`;
+
+
+(*val FPExc_of_num : integer -> FPExc*)
+
+val _ = Define `
+ ((FPExc_of_num:int -> FPExc) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FPExc_InvalidOp
+   else if (((p0_ = (( 1 : int):ii)))) then FPExc_DivideByZero
+   else if (((p0_ = (( 2 : int):ii)))) then FPExc_Overflow
+   else if (((p0_ = (( 3 : int):ii)))) then FPExc_Underflow
+   else if (((p0_ = (( 4 : int):ii)))) then FPExc_Inexact
+   else FPExc_InputDenorm))`;
+
+
+(*val num_of_FPExc : FPExc -> integer*)
+
+val _ = Define `
+ ((num_of_FPExc:FPExc -> int) arg_=
+    ((case arg_ of
+     FPExc_InvalidOp => (( 0 : int):ii)
+   | FPExc_DivideByZero => (( 1 : int):ii)
+   | FPExc_Overflow => (( 2 : int):ii)
+   | FPExc_Underflow => (( 3 : int):ii)
+   | FPExc_Inexact => (( 4 : int):ii)
+   | FPExc_InputDenorm => (( 5 : int):ii)
+   )))`;
+
+
+(*val undefined_FPExc : unit -> M FPExc*)
+
+val _ = Define `
+ ((undefined_FPExc:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPExc),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [FPExc_InvalidOp;FPExc_DivideByZero;FPExc_Overflow;FPExc_Underflow;FPExc_Inexact;FPExc_InputDenorm]))`;
+
+
+(*val FPRounding_of_num : integer -> FPRounding*)
+
+val _ = Define `
+ ((FPRounding_of_num:int -> FPRounding) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FPRounding_TIEEVEN
+   else if (((p0_ = (( 1 : int):ii)))) then FPRounding_POSINF
+   else if (((p0_ = (( 2 : int):ii)))) then FPRounding_NEGINF
+   else if (((p0_ = (( 3 : int):ii)))) then FPRounding_ZERO
+   else if (((p0_ = (( 4 : int):ii)))) then FPRounding_TIEAWAY
+   else FPRounding_ODD))`;
+
+
+(*val num_of_FPRounding : FPRounding -> integer*)
+
+val _ = Define `
+ ((num_of_FPRounding:FPRounding -> int) arg_=
+    ((case arg_ of
+     FPRounding_TIEEVEN => (( 0 : int):ii)
+   | FPRounding_POSINF => (( 1 : int):ii)
+   | FPRounding_NEGINF => (( 2 : int):ii)
+   | FPRounding_ZERO => (( 3 : int):ii)
+   | FPRounding_TIEAWAY => (( 4 : int):ii)
+   | FPRounding_ODD => (( 5 : int):ii)
+   )))`;
+
+
+(*val undefined_FPRounding : unit -> M FPRounding*)
+
+val _ = Define `
+ ((undefined_FPRounding:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPRounding),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [FPRounding_TIEEVEN;FPRounding_POSINF;FPRounding_NEGINF;FPRounding_ZERO;FPRounding_TIEAWAY;FPRounding_ODD]))`;
+
+
+(*val SysRegAccess_of_num : integer -> SysRegAccess*)
+
+val _ = Define `
+ ((SysRegAccess_of_num:int -> SysRegAccess) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then SysRegAccess_OK
+   else if (((p0_ = (( 1 : int):ii)))) then SysRegAccess_UNDEFINED
+   else if (((p0_ = (( 2 : int):ii)))) then SysRegAccess_TrapToEL1
+   else if (((p0_ = (( 3 : int):ii)))) then SysRegAccess_TrapToEL2
+   else SysRegAccess_TrapToEL3))`;
+
+
+(*val num_of_SysRegAccess : SysRegAccess -> integer*)
+
+val _ = Define `
+ ((num_of_SysRegAccess:SysRegAccess -> int) arg_=
+    ((case arg_ of
+     SysRegAccess_OK => (( 0 : int):ii)
+   | SysRegAccess_UNDEFINED => (( 1 : int):ii)
+   | SysRegAccess_TrapToEL1 => (( 2 : int):ii)
+   | SysRegAccess_TrapToEL2 => (( 3 : int):ii)
+   | SysRegAccess_TrapToEL3 => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_SysRegAccess : unit -> M SysRegAccess*)
+
+val _ = Define `
+ ((undefined_SysRegAccess:unit ->(regstate)sail2_state_monad$sequential_state ->(((SysRegAccess),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [SysRegAccess_OK;SysRegAccess_UNDEFINED;SysRegAccess_TrapToEL1;SysRegAccess_TrapToEL2;SysRegAccess_TrapToEL3]))`;
+
+
+(*val SRType_of_num : integer -> SRType*)
+
+val _ = Define `
+ ((SRType_of_num:int -> SRType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then SRType_LSL
+   else if (((p0_ = (( 1 : int):ii)))) then SRType_LSR
+   else if (((p0_ = (( 2 : int):ii)))) then SRType_ASR
+   else if (((p0_ = (( 3 : int):ii)))) then SRType_ROR
+   else SRType_RRX))`;
+
+
+(*val num_of_SRType : SRType -> integer*)
+
+val _ = Define `
+ ((num_of_SRType:SRType -> int) arg_=
+    ((case arg_ of
+     SRType_LSL => (( 0 : int):ii)
+   | SRType_LSR => (( 1 : int):ii)
+   | SRType_ASR => (( 2 : int):ii)
+   | SRType_ROR => (( 3 : int):ii)
+   | SRType_RRX => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_SRType : unit -> M SRType*)
+
+val _ = Define `
+ ((undefined_SRType:unit ->(regstate)sail2_state_monad$sequential_state ->(((SRType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [SRType_LSL;SRType_LSR;SRType_ASR;SRType_ROR;SRType_RRX]))`;
+
+
+(*val ShiftType_of_num : integer -> ShiftType*)
+
+val _ = Define `
+ ((ShiftType_of_num:int -> ShiftType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then ShiftType_LSL
+   else if (((p0_ = (( 1 : int):ii)))) then ShiftType_LSR
+   else if (((p0_ = (( 2 : int):ii)))) then ShiftType_ASR
+   else ShiftType_ROR))`;
+
+
+(*val num_of_ShiftType : ShiftType -> integer*)
+
+val _ = Define `
+ ((num_of_ShiftType:ShiftType -> int) arg_=
+    ((case arg_ of
+     ShiftType_LSL => (( 0 : int):ii)
+   | ShiftType_LSR => (( 1 : int):ii)
+   | ShiftType_ASR => (( 2 : int):ii)
+   | ShiftType_ROR => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_ShiftType : unit -> M ShiftType*)
+
+val _ = Define `
+ ((undefined_ShiftType:unit ->(regstate)sail2_state_monad$sequential_state ->(((ShiftType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [ShiftType_LSL;ShiftType_LSR;ShiftType_ASR;ShiftType_ROR]))`;
+
+
+(*val PrefetchHint_of_num : integer -> PrefetchHint*)
+
+val _ = Define `
+ ((PrefetchHint_of_num:int -> PrefetchHint) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Prefetch_READ
+   else if (((p0_ = (( 1 : int):ii)))) then Prefetch_WRITE
+   else Prefetch_EXEC))`;
+
+
+(*val num_of_PrefetchHint : PrefetchHint -> integer*)
+
+val _ = Define `
+ ((num_of_PrefetchHint:PrefetchHint -> int) arg_=
+    ((case arg_ of
+     Prefetch_READ => (( 0 : int):ii)
+   | Prefetch_WRITE => (( 1 : int):ii)
+   | Prefetch_EXEC => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_PrefetchHint : unit -> M PrefetchHint*)
+
+val _ = Define `
+ ((undefined_PrefetchHint:unit ->(regstate)sail2_state_monad$sequential_state ->(((PrefetchHint),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [Prefetch_READ;Prefetch_WRITE;Prefetch_EXEC]))`;
+
+
+(*val InterruptID_of_num : integer -> InterruptID*)
+
+val _ = Define `
+ ((InterruptID_of_num:int -> InterruptID) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then InterruptID_PMUIRQ
+   else if (((p0_ = (( 1 : int):ii)))) then InterruptID_COMMIRQ
+   else if (((p0_ = (( 2 : int):ii)))) then InterruptID_CTIIRQ
+   else if (((p0_ = (( 3 : int):ii)))) then InterruptID_COMMRX
+   else InterruptID_COMMTX))`;
+
+
+(*val num_of_InterruptID : InterruptID -> integer*)
+
+val _ = Define `
+ ((num_of_InterruptID:InterruptID -> int) arg_=
+    ((case arg_ of
+     InterruptID_PMUIRQ => (( 0 : int):ii)
+   | InterruptID_COMMIRQ => (( 1 : int):ii)
+   | InterruptID_CTIIRQ => (( 2 : int):ii)
+   | InterruptID_COMMRX => (( 3 : int):ii)
+   | InterruptID_COMMTX => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_InterruptID : unit -> M InterruptID*)
+
+val _ = Define `
+ ((undefined_InterruptID:unit ->(regstate)sail2_state_monad$sequential_state ->(((InterruptID),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [InterruptID_PMUIRQ;InterruptID_COMMIRQ;InterruptID_CTIIRQ;InterruptID_COMMRX;InterruptID_COMMTX]))`;
+
+
+(*val CrossTriggerOut_of_num : integer -> CrossTriggerOut*)
+
+val _ = Define `
+ ((CrossTriggerOut_of_num:int -> CrossTriggerOut) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CrossTriggerOut_DebugRequest
+   else if (((p0_ = (( 1 : int):ii)))) then CrossTriggerOut_RestartRequest
+   else if (((p0_ = (( 2 : int):ii)))) then CrossTriggerOut_IRQ
+   else if (((p0_ = (( 3 : int):ii)))) then CrossTriggerOut_RSVD3
+   else if (((p0_ = (( 4 : int):ii)))) then CrossTriggerOut_TraceExtIn0
+   else if (((p0_ = (( 5 : int):ii)))) then CrossTriggerOut_TraceExtIn1
+   else if (((p0_ = (( 6 : int):ii)))) then CrossTriggerOut_TraceExtIn2
+   else CrossTriggerOut_TraceExtIn3))`;
+
+
+(*val num_of_CrossTriggerOut : CrossTriggerOut -> integer*)
+
+val _ = Define `
+ ((num_of_CrossTriggerOut:CrossTriggerOut -> int) arg_=
+    ((case arg_ of
+     CrossTriggerOut_DebugRequest => (( 0 : int):ii)
+   | CrossTriggerOut_RestartRequest => (( 1 : int):ii)
+   | CrossTriggerOut_IRQ => (( 2 : int):ii)
+   | CrossTriggerOut_RSVD3 => (( 3 : int):ii)
+   | CrossTriggerOut_TraceExtIn0 => (( 4 : int):ii)
+   | CrossTriggerOut_TraceExtIn1 => (( 5 : int):ii)
+   | CrossTriggerOut_TraceExtIn2 => (( 6 : int):ii)
+   | CrossTriggerOut_TraceExtIn3 => (( 7 : int):ii)
+   )))`;
+
+
+(*val undefined_CrossTriggerOut : unit -> M CrossTriggerOut*)
+
+val _ = Define `
+ ((undefined_CrossTriggerOut:unit ->(regstate)sail2_state_monad$sequential_state ->(((CrossTriggerOut),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [CrossTriggerOut_DebugRequest;CrossTriggerOut_RestartRequest;CrossTriggerOut_IRQ;CrossTriggerOut_RSVD3;CrossTriggerOut_TraceExtIn0;CrossTriggerOut_TraceExtIn1;CrossTriggerOut_TraceExtIn2;CrossTriggerOut_TraceExtIn3]))`;
+
+
+(*val CrossTriggerIn_of_num : integer -> CrossTriggerIn*)
+
+val _ = Define `
+ ((CrossTriggerIn_of_num:int -> CrossTriggerIn) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CrossTriggerIn_CrossHalt
+   else if (((p0_ = (( 1 : int):ii)))) then CrossTriggerIn_PMUOverflow
+   else if (((p0_ = (( 2 : int):ii)))) then CrossTriggerIn_RSVD2
+   else if (((p0_ = (( 3 : int):ii)))) then CrossTriggerIn_RSVD3
+   else if (((p0_ = (( 4 : int):ii)))) then CrossTriggerIn_TraceExtOut0
+   else if (((p0_ = (( 5 : int):ii)))) then CrossTriggerIn_TraceExtOut1
+   else if (((p0_ = (( 6 : int):ii)))) then CrossTriggerIn_TraceExtOut2
+   else CrossTriggerIn_TraceExtOut3))`;
+
+
+(*val num_of_CrossTriggerIn : CrossTriggerIn -> integer*)
+
+val _ = Define `
+ ((num_of_CrossTriggerIn:CrossTriggerIn -> int) arg_=
+    ((case arg_ of
+     CrossTriggerIn_CrossHalt => (( 0 : int):ii)
+   | CrossTriggerIn_PMUOverflow => (( 1 : int):ii)
+   | CrossTriggerIn_RSVD2 => (( 2 : int):ii)
+   | CrossTriggerIn_RSVD3 => (( 3 : int):ii)
+   | CrossTriggerIn_TraceExtOut0 => (( 4 : int):ii)
+   | CrossTriggerIn_TraceExtOut1 => (( 5 : int):ii)
+   | CrossTriggerIn_TraceExtOut2 => (( 6 : int):ii)
+   | CrossTriggerIn_TraceExtOut3 => (( 7 : int):ii)
+   )))`;
+
+
+(*val undefined_CrossTriggerIn : unit -> M CrossTriggerIn*)
+
+val _ = Define `
+ ((undefined_CrossTriggerIn:unit ->(regstate)sail2_state_monad$sequential_state ->(((CrossTriggerIn),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [CrossTriggerIn_CrossHalt;CrossTriggerIn_PMUOverflow;CrossTriggerIn_RSVD2;CrossTriggerIn_RSVD3;CrossTriggerIn_TraceExtOut0;CrossTriggerIn_TraceExtOut1;CrossTriggerIn_TraceExtOut2;CrossTriggerIn_TraceExtOut3]))`;
+
+
+(*val MemBarrierOp_of_num : integer -> MemBarrierOp*)
+
+val _ = Define `
+ ((MemBarrierOp_of_num:int -> MemBarrierOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MemBarrierOp_DSB
+   else if (((p0_ = (( 1 : int):ii)))) then MemBarrierOp_DMB
+   else MemBarrierOp_ISB))`;
+
+
+(*val num_of_MemBarrierOp : MemBarrierOp -> integer*)
+
+val _ = Define `
+ ((num_of_MemBarrierOp:MemBarrierOp -> int) arg_=
+    ((case arg_ of
+     MemBarrierOp_DSB => (( 0 : int):ii)
+   | MemBarrierOp_DMB => (( 1 : int):ii)
+   | MemBarrierOp_ISB => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_MemBarrierOp : unit -> M MemBarrierOp*)
+
+val _ = Define `
+ ((undefined_MemBarrierOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemBarrierOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [MemBarrierOp_DSB;MemBarrierOp_DMB;MemBarrierOp_ISB]))`;
+
+
+(*val undefined_AccessDescriptor : unit -> M AccessDescriptor*)
+
+val _ = Define `
+ ((undefined_AccessDescriptor:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_AccType () ) (\ (w__0 : AccType) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (w__4 : ii) . 
+   sail2_state_monad$returnS (<| AccessDescriptor_acctype := w__0; 
+              AccessDescriptor_page_table_walk := w__1; 
+              AccessDescriptor_secondstage := w__2; 
+              AccessDescriptor_s2fs1walk := w__3; 
+              AccessDescriptor_level := w__4 |>))))))))`;
+
+
+(*val undefined_Permissions : unit -> M Permissions*)
+
+val _ = Define `
+ ((undefined_Permissions:unit ->(regstate)sail2_state_monad$sequential_state ->(((Permissions),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M) (\ (w__0 : 3 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__3 : 1 bits) . 
+   sail2_state_monad$returnS (<| Permissions_ap := w__0; 
+              Permissions_xn := w__1; 
+              Permissions_xxn := w__2; 
+              Permissions_pxn := w__3 |>)))))))`;
+
+
+(*val undefined_TLBRecord : unit -> M TLBRecord*)
+
+val _ = Define `
+ ((undefined_TLBRecord:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_Permissions () ) (\ (w__0 : Permissions) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__2 : 4 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (w__4 : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (w__5 : ii) .  sail2_state_monad$bindS
+   (undefined_DescriptorUpdate () ) (\ (w__6 : DescriptorUpdate) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__7 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_AddressDescriptor () ) (\ (w__8 : AddressDescriptor) . 
+   sail2_state_monad$returnS (<| TLBRecord_perms := w__0; 
+              TLBRecord_nG := w__1; 
+              TLBRecord_domain := w__2; 
+              TLBRecord_contiguous := w__3; 
+              TLBRecord_level := w__4; 
+              TLBRecord_blocksize := w__5; 
+              TLBRecord_descupdate := w__6; 
+              TLBRecord_CnP := w__7; 
+              TLBRecord_addrdesc := w__8 |>))))))))))))`;
+
+
+(*val ImmediateOp_of_num : integer -> ImmediateOp*)
+
+val _ = Define `
+ ((ImmediateOp_of_num:int -> ImmediateOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then ImmediateOp_MOVI
+   else if (((p0_ = (( 1 : int):ii)))) then ImmediateOp_MVNI
+   else if (((p0_ = (( 2 : int):ii)))) then ImmediateOp_ORR
+   else ImmediateOp_BIC))`;
+
+
+(*val num_of_ImmediateOp : ImmediateOp -> integer*)
+
+val _ = Define `
+ ((num_of_ImmediateOp:ImmediateOp -> int) arg_=
+    ((case arg_ of
+     ImmediateOp_MOVI => (( 0 : int):ii)
+   | ImmediateOp_MVNI => (( 1 : int):ii)
+   | ImmediateOp_ORR => (( 2 : int):ii)
+   | ImmediateOp_BIC => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_ImmediateOp : unit -> M ImmediateOp*)
+
+val _ = Define `
+ ((undefined_ImmediateOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((ImmediateOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [ImmediateOp_MOVI;ImmediateOp_MVNI;ImmediateOp_ORR;ImmediateOp_BIC]))`;
+
+
+(*val MoveWideOp_of_num : integer -> MoveWideOp*)
+
+val _ = Define `
+ ((MoveWideOp_of_num:int -> MoveWideOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MoveWideOp_N
+   else if (((p0_ = (( 1 : int):ii)))) then MoveWideOp_Z
+   else MoveWideOp_K))`;
+
+
+(*val num_of_MoveWideOp : MoveWideOp -> integer*)
+
+val _ = Define `
+ ((num_of_MoveWideOp:MoveWideOp -> int) arg_=
+    ((case arg_ of   MoveWideOp_N => (( 0 : int):ii) | MoveWideOp_Z => (( 1 : int):ii) | MoveWideOp_K => (( 2 : int):ii) )))`;
+
+
+(*val undefined_MoveWideOp : unit -> M MoveWideOp*)
+
+val _ = Define `
+ ((undefined_MoveWideOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MoveWideOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [MoveWideOp_N;MoveWideOp_Z;MoveWideOp_K]))`;
+
+
+(*val SystemAccessType_of_num : integer -> SystemAccessType*)
+
+val _ = Define `
+ ((SystemAccessType_of_num:int -> SystemAccessType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then SystemAccessType_RT
+   else if (((p0_ = (( 1 : int):ii)))) then SystemAccessType_RRT
+   else SystemAccessType_DT))`;
+
+
+(*val num_of_SystemAccessType : SystemAccessType -> integer*)
+
+val _ = Define `
+ ((num_of_SystemAccessType:SystemAccessType -> int) arg_=
+    ((case arg_ of
+     SystemAccessType_RT => (( 0 : int):ii)
+   | SystemAccessType_RRT => (( 1 : int):ii)
+   | SystemAccessType_DT => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_SystemAccessType : unit -> M SystemAccessType*)
+
+val _ = Define `
+ ((undefined_SystemAccessType:unit ->(regstate)sail2_state_monad$sequential_state ->(((SystemAccessType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [SystemAccessType_RT;SystemAccessType_RRT;SystemAccessType_DT]))`;
+
+
+(*val VBitOp_of_num : integer -> VBitOp*)
+
+val _ = Define `
+ ((VBitOp_of_num:int -> VBitOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then VBitOp_VBIF
+   else if (((p0_ = (( 1 : int):ii)))) then VBitOp_VBIT
+   else if (((p0_ = (( 2 : int):ii)))) then VBitOp_VBSL
+   else VBitOp_VEOR))`;
+
+
+(*val num_of_VBitOp : VBitOp -> integer*)
+
+val _ = Define `
+ ((num_of_VBitOp:VBitOp -> int) arg_=
+    ((case arg_ of
+     VBitOp_VBIF => (( 0 : int):ii)
+   | VBitOp_VBIT => (( 1 : int):ii)
+   | VBitOp_VBSL => (( 2 : int):ii)
+   | VBitOp_VEOR => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_VBitOp : unit -> M VBitOp*)
+
+val _ = Define `
+ ((undefined_VBitOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((VBitOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [VBitOp_VBIF;VBitOp_VBIT;VBitOp_VBSL;VBitOp_VEOR]))`;
+
+
+(*val TimeStamp_of_num : integer -> TimeStamp*)
+
+val _ = Define `
+ ((TimeStamp_of_num:int -> TimeStamp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then TimeStamp_None
+   else if (((p0_ = (( 1 : int):ii)))) then TimeStamp_Virtual
+   else TimeStamp_Physical))`;
+
+
+(*val num_of_TimeStamp : TimeStamp -> integer*)
+
+val _ = Define `
+ ((num_of_TimeStamp:TimeStamp -> int) arg_=
+    ((case arg_ of
+     TimeStamp_None => (( 0 : int):ii)
+   | TimeStamp_Virtual => (( 1 : int):ii)
+   | TimeStamp_Physical => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_TimeStamp : unit -> M TimeStamp*)
+
+val _ = Define `
+ ((undefined_TimeStamp:unit ->(regstate)sail2_state_monad$sequential_state ->(((TimeStamp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [TimeStamp_None;TimeStamp_Virtual;TimeStamp_Physical]))`;
+
+
+(*val PrivilegeLevel_of_num : integer -> PrivilegeLevel*)
+
+val _ = Define `
+ ((PrivilegeLevel_of_num:int -> PrivilegeLevel) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then PL3
+   else if (((p0_ = (( 1 : int):ii)))) then PL2
+   else if (((p0_ = (( 2 : int):ii)))) then PL1
+   else PL0))`;
+
+
+(*val num_of_PrivilegeLevel : PrivilegeLevel -> integer*)
+
+val _ = Define `
+ ((num_of_PrivilegeLevel:PrivilegeLevel -> int) arg_=
+    ((case arg_ of   PL3 => (( 0 : int):ii) | PL2 => (( 1 : int):ii) | PL1 => (( 2 : int):ii) | PL0 => (( 3 : int):ii) )))`;
+
+
+(*val undefined_PrivilegeLevel : unit -> M PrivilegeLevel*)
+
+val _ = Define `
+ ((undefined_PrivilegeLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((PrivilegeLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [PL3;PL2;PL1;PL0]))`;
+
+
+(*val undefined_AArch32_SErrorSyndrome : unit -> M AArch32_SErrorSyndrome*)
+
+val _ = Define `
+ ((undefined_AArch32_SErrorSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->(((AArch32_SErrorSyndrome),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__0 : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
+   sail2_state_monad$returnS (<| AArch32_SErrorSyndrome_AET := w__0; 
+              AArch32_SErrorSyndrome_ExT := w__1 |>)))))`;
+
+
+(*val SystemOp_of_num : integer -> SystemOp*)
+
+val _ = Define `
+ ((SystemOp_of_num:int -> SystemOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Sys_AT
+   else if (((p0_ = (( 1 : int):ii)))) then Sys_DC
+   else if (((p0_ = (( 2 : int):ii)))) then Sys_IC
+   else if (((p0_ = (( 3 : int):ii)))) then Sys_TLBI
+   else Sys_SYS))`;
+
+
+(*val num_of_SystemOp : SystemOp -> integer*)
+
+val _ = Define `
+ ((num_of_SystemOp:SystemOp -> int) arg_=
+    ((case arg_ of
+     Sys_AT => (( 0 : int):ii)
+   | Sys_DC => (( 1 : int):ii)
+   | Sys_IC => (( 2 : int):ii)
+   | Sys_TLBI => (( 3 : int):ii)
+   | Sys_SYS => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_SystemOp : unit -> M SystemOp*)
+
+val _ = Define `
+ ((undefined_SystemOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((SystemOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [Sys_AT;Sys_DC;Sys_IC;Sys_TLBI;Sys_SYS]))`;
+
+
+(*val undefined_PCSample : unit -> M PCSample*)
+
+val _ = Define `
+ ((undefined_PCSample:unit ->(regstate)sail2_state_monad$sequential_state ->(((PCSample),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__2 : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__3 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__4 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__5 : 32 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__6 : 32 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__7 : 16 bits) . 
+   sail2_state_monad$returnS (<| PCSample_valid_name := w__0; 
+              PCSample_pc := w__1; 
+              PCSample_el := w__2; 
+              PCSample_rw := w__3; 
+              PCSample_ns := w__4; 
+              PCSample_contextidr := w__5; 
+              PCSample_contextidr_el2 := w__6; 
+              PCSample_vmid := w__7 |>)))))))))))`;
+
+
+(*val ReduceOp_of_num : integer -> ReduceOp*)
+
+val _ = Define `
+ ((ReduceOp_of_num:int -> ReduceOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then ReduceOp_FMINNUM
+   else if (((p0_ = (( 1 : int):ii)))) then ReduceOp_FMAXNUM
+   else if (((p0_ = (( 2 : int):ii)))) then ReduceOp_FMIN
+   else if (((p0_ = (( 3 : int):ii)))) then ReduceOp_FMAX
+   else if (((p0_ = (( 4 : int):ii)))) then ReduceOp_FADD
+   else ReduceOp_ADD))`;
+
+
+(*val num_of_ReduceOp : ReduceOp -> integer*)
+
+val _ = Define `
+ ((num_of_ReduceOp:ReduceOp -> int) arg_=
+    ((case arg_ of
+     ReduceOp_FMINNUM => (( 0 : int):ii)
+   | ReduceOp_FMAXNUM => (( 1 : int):ii)
+   | ReduceOp_FMIN => (( 2 : int):ii)
+   | ReduceOp_FMAX => (( 3 : int):ii)
+   | ReduceOp_FADD => (( 4 : int):ii)
+   | ReduceOp_ADD => (( 5 : int):ii)
+   )))`;
+
+
+(*val undefined_ReduceOp : unit -> M ReduceOp*)
+
+val _ = Define `
+ ((undefined_ReduceOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((ReduceOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [ReduceOp_FMINNUM;ReduceOp_FMAXNUM;ReduceOp_FMIN;ReduceOp_FMAX;ReduceOp_FADD;ReduceOp_ADD]))`;
+
+
+(*val LogicalOp_of_num : integer -> LogicalOp*)
+
+val _ = Define `
+ ((LogicalOp_of_num:int -> LogicalOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then LogicalOp_AND
+   else if (((p0_ = (( 1 : int):ii)))) then LogicalOp_EOR
+   else LogicalOp_ORR))`;
+
+
+(*val num_of_LogicalOp : LogicalOp -> integer*)
+
+val _ = Define `
+ ((num_of_LogicalOp:LogicalOp -> int) arg_=
+    ((case arg_ of   LogicalOp_AND => (( 0 : int):ii) | LogicalOp_EOR => (( 1 : int):ii) | LogicalOp_ORR => (( 2 : int):ii) )))`;
+
+
+(*val undefined_LogicalOp : unit -> M LogicalOp*)
+
+val _ = Define `
+ ((undefined_LogicalOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((LogicalOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [LogicalOp_AND;LogicalOp_EOR;LogicalOp_ORR]))`;
+
+
+(*val ExtendType_of_num : integer -> ExtendType*)
+
+val _ = Define `
+ ((ExtendType_of_num:int -> ExtendType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then ExtendType_SXTB
+   else if (((p0_ = (( 1 : int):ii)))) then ExtendType_SXTH
+   else if (((p0_ = (( 2 : int):ii)))) then ExtendType_SXTW
+   else if (((p0_ = (( 3 : int):ii)))) then ExtendType_SXTX
+   else if (((p0_ = (( 4 : int):ii)))) then ExtendType_UXTB
+   else if (((p0_ = (( 5 : int):ii)))) then ExtendType_UXTH
+   else if (((p0_ = (( 6 : int):ii)))) then ExtendType_UXTW
+   else ExtendType_UXTX))`;
+
+
+(*val num_of_ExtendType : ExtendType -> integer*)
+
+val _ = Define `
+ ((num_of_ExtendType:ExtendType -> int) arg_=
+    ((case arg_ of
+     ExtendType_SXTB => (( 0 : int):ii)
+   | ExtendType_SXTH => (( 1 : int):ii)
+   | ExtendType_SXTW => (( 2 : int):ii)
+   | ExtendType_SXTX => (( 3 : int):ii)
+   | ExtendType_UXTB => (( 4 : int):ii)
+   | ExtendType_UXTH => (( 5 : int):ii)
+   | ExtendType_UXTW => (( 6 : int):ii)
+   | ExtendType_UXTX => (( 7 : int):ii)
+   )))`;
+
+
+(*val undefined_ExtendType : unit -> M ExtendType*)
+
+val _ = Define `
+ ((undefined_ExtendType:unit ->(regstate)sail2_state_monad$sequential_state ->(((ExtendType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [ExtendType_SXTB;ExtendType_SXTH;ExtendType_SXTW;ExtendType_SXTX;ExtendType_UXTB;ExtendType_UXTH;ExtendType_UXTW;ExtendType_UXTX]))`;
+
+
+(*val SystemHintOp_of_num : integer -> SystemHintOp*)
+
+val _ = Define `
+ ((SystemHintOp_of_num:int -> SystemHintOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then SystemHintOp_NOP
+   else if (((p0_ = (( 1 : int):ii)))) then SystemHintOp_YIELD
+   else if (((p0_ = (( 2 : int):ii)))) then SystemHintOp_WFE
+   else if (((p0_ = (( 3 : int):ii)))) then SystemHintOp_WFI
+   else if (((p0_ = (( 4 : int):ii)))) then SystemHintOp_SEV
+   else if (((p0_ = (( 5 : int):ii)))) then SystemHintOp_SEVL
+   else if (((p0_ = (( 6 : int):ii)))) then SystemHintOp_ESB
+   else SystemHintOp_PSB))`;
+
+
+(*val num_of_SystemHintOp : SystemHintOp -> integer*)
+
+val _ = Define `
+ ((num_of_SystemHintOp:SystemHintOp -> int) arg_=
+    ((case arg_ of
+     SystemHintOp_NOP => (( 0 : int):ii)
+   | SystemHintOp_YIELD => (( 1 : int):ii)
+   | SystemHintOp_WFE => (( 2 : int):ii)
+   | SystemHintOp_WFI => (( 3 : int):ii)
+   | SystemHintOp_SEV => (( 4 : int):ii)
+   | SystemHintOp_SEVL => (( 5 : int):ii)
+   | SystemHintOp_ESB => (( 6 : int):ii)
+   | SystemHintOp_PSB => (( 7 : int):ii)
+   )))`;
+
+
+(*val undefined_SystemHintOp : unit -> M SystemHintOp*)
+
+val _ = Define `
+ ((undefined_SystemHintOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((SystemHintOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [SystemHintOp_NOP;SystemHintOp_YIELD;SystemHintOp_WFE;SystemHintOp_WFI;SystemHintOp_SEV;SystemHintOp_SEVL;SystemHintOp_ESB;SystemHintOp_PSB]))`;
+
+
+(*val MemOp_of_num : integer -> MemOp*)
+
+val _ = Define `
+ ((MemOp_of_num:int -> MemOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then MemOp_LOAD
+   else if (((p0_ = (( 1 : int):ii)))) then MemOp_STORE
+   else MemOp_PREFETCH))`;
+
+
+(*val num_of_MemOp : MemOp -> integer*)
+
+val _ = Define `
+ ((num_of_MemOp:MemOp -> int) arg_=
+    ((case arg_ of   MemOp_LOAD => (( 0 : int):ii) | MemOp_STORE => (( 1 : int):ii) | MemOp_PREFETCH => (( 2 : int):ii) )))`;
+
+
+(*val undefined_MemOp : unit -> M MemOp*)
+
+val _ = Define `
+ ((undefined_MemOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [MemOp_LOAD;MemOp_STORE;MemOp_PREFETCH]))`;
+
+
+(*val OpType_of_num : integer -> OpType*)
+
+val _ = Define `
+ ((OpType_of_num:int -> OpType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then OpType_Load
+   else if (((p0_ = (( 1 : int):ii)))) then OpType_Store
+   else if (((p0_ = (( 2 : int):ii)))) then OpType_LoadAtomic
+   else if (((p0_ = (( 3 : int):ii)))) then OpType_Branch
+   else OpType_Other))`;
+
+
+(*val num_of_OpType : OpType -> integer*)
+
+val _ = Define `
+ ((num_of_OpType:OpType -> int) arg_=
+    ((case arg_ of
+     OpType_Load => (( 0 : int):ii)
+   | OpType_Store => (( 1 : int):ii)
+   | OpType_LoadAtomic => (( 2 : int):ii)
+   | OpType_Branch => (( 3 : int):ii)
+   | OpType_Other => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_OpType : unit -> M OpType*)
+
+val _ = Define `
+ ((undefined_OpType:unit ->(regstate)sail2_state_monad$sequential_state ->(((OpType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [OpType_Load;OpType_Store;OpType_LoadAtomic;OpType_Branch;OpType_Other]))`;
+
+
+(*val FPUnaryOp_of_num : integer -> FPUnaryOp*)
+
+val _ = Define `
+ ((FPUnaryOp_of_num:int -> FPUnaryOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FPUnaryOp_ABS
+   else if (((p0_ = (( 1 : int):ii)))) then FPUnaryOp_MOV
+   else if (((p0_ = (( 2 : int):ii)))) then FPUnaryOp_NEG
+   else FPUnaryOp_SQRT))`;
+
+
+(*val num_of_FPUnaryOp : FPUnaryOp -> integer*)
+
+val _ = Define `
+ ((num_of_FPUnaryOp:FPUnaryOp -> int) arg_=
+    ((case arg_ of
+     FPUnaryOp_ABS => (( 0 : int):ii)
+   | FPUnaryOp_MOV => (( 1 : int):ii)
+   | FPUnaryOp_NEG => (( 2 : int):ii)
+   | FPUnaryOp_SQRT => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_FPUnaryOp : unit -> M FPUnaryOp*)
+
+val _ = Define `
+ ((undefined_FPUnaryOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPUnaryOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [FPUnaryOp_ABS;FPUnaryOp_MOV;FPUnaryOp_NEG;FPUnaryOp_SQRT]))`;
+
+
+(*val CompareOp_of_num : integer -> CompareOp*)
+
+val _ = Define `
+ ((CompareOp_of_num:int -> CompareOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CompareOp_GT
+   else if (((p0_ = (( 1 : int):ii)))) then CompareOp_GE
+   else if (((p0_ = (( 2 : int):ii)))) then CompareOp_EQ
+   else if (((p0_ = (( 3 : int):ii)))) then CompareOp_LE
+   else CompareOp_LT))`;
+
+
+(*val num_of_CompareOp : CompareOp -> integer*)
+
+val _ = Define `
+ ((num_of_CompareOp:CompareOp -> int) arg_=
+    ((case arg_ of
+     CompareOp_GT => (( 0 : int):ii)
+   | CompareOp_GE => (( 1 : int):ii)
+   | CompareOp_EQ => (( 2 : int):ii)
+   | CompareOp_LE => (( 3 : int):ii)
+   | CompareOp_LT => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_CompareOp : unit -> M CompareOp*)
+
+val _ = Define `
+ ((undefined_CompareOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((CompareOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [CompareOp_GT;CompareOp_GE;CompareOp_EQ;CompareOp_LE;CompareOp_LT]))`;
+
+
+(*val PSTATEField_of_num : integer -> PSTATEField*)
+
+val _ = Define `
+ ((PSTATEField_of_num:int -> PSTATEField) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then PSTATEField_DAIFSet
+   else if (((p0_ = (( 1 : int):ii)))) then PSTATEField_DAIFClr
+   else if (((p0_ = (( 2 : int):ii)))) then PSTATEField_PAN
+   else if (((p0_ = (( 3 : int):ii)))) then PSTATEField_UAO
+   else PSTATEField_SP))`;
+
+
+(*val num_of_PSTATEField : PSTATEField -> integer*)
+
+val _ = Define `
+ ((num_of_PSTATEField:PSTATEField -> int) arg_=
+    ((case arg_ of
+     PSTATEField_DAIFSet => (( 0 : int):ii)
+   | PSTATEField_DAIFClr => (( 1 : int):ii)
+   | PSTATEField_PAN => (( 2 : int):ii)
+   | PSTATEField_UAO => (( 3 : int):ii)
+   | PSTATEField_SP => (( 4 : int):ii)
+   )))`;
+
+
+(*val undefined_PSTATEField : unit -> M PSTATEField*)
+
+val _ = Define `
+ ((undefined_PSTATEField:unit ->(regstate)sail2_state_monad$sequential_state ->(((PSTATEField),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [PSTATEField_DAIFSet;PSTATEField_DAIFClr;PSTATEField_PAN;PSTATEField_UAO;PSTATEField_SP]))`;
+
+
+(*val FPMaxMinOp_of_num : integer -> FPMaxMinOp*)
+
+val _ = Define `
+ ((FPMaxMinOp_of_num:int -> FPMaxMinOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then FPMaxMinOp_MAX
+   else if (((p0_ = (( 1 : int):ii)))) then FPMaxMinOp_MIN
+   else if (((p0_ = (( 2 : int):ii)))) then FPMaxMinOp_MAXNUM
+   else FPMaxMinOp_MINNUM))`;
+
+
+(*val num_of_FPMaxMinOp : FPMaxMinOp -> integer*)
+
+val _ = Define `
+ ((num_of_FPMaxMinOp:FPMaxMinOp -> int) arg_=
+    ((case arg_ of
+     FPMaxMinOp_MAX => (( 0 : int):ii)
+   | FPMaxMinOp_MIN => (( 1 : int):ii)
+   | FPMaxMinOp_MAXNUM => (( 2 : int):ii)
+   | FPMaxMinOp_MINNUM => (( 3 : int):ii)
+   )))`;
+
+
+(*val undefined_FPMaxMinOp : unit -> M FPMaxMinOp*)
+
+val _ = Define `
+ ((undefined_FPMaxMinOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPMaxMinOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [FPMaxMinOp_MAX;FPMaxMinOp_MIN;FPMaxMinOp_MAXNUM;FPMaxMinOp_MINNUM]))`;
+
+
+(*val CountOp_of_num : integer -> CountOp*)
+
+val _ = Define `
+ ((CountOp_of_num:int -> CountOp) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CountOp_CLZ
+   else if (((p0_ = (( 1 : int):ii)))) then CountOp_CLS
+   else CountOp_CNT))`;
+
+
+(*val num_of_CountOp : CountOp -> integer*)
+
+val _ = Define `
+ ((num_of_CountOp:CountOp -> int) arg_=
+    ((case arg_ of   CountOp_CLZ => (( 0 : int):ii) | CountOp_CLS => (( 1 : int):ii) | CountOp_CNT => (( 2 : int):ii) )))`;
+
+
+(*val undefined_CountOp : unit -> M CountOp*)
+
+val _ = Define `
+ ((undefined_CountOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((CountOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [CountOp_CLZ;CountOp_CLS;CountOp_CNT]))`;
+
+
+(*val VFPNegMul_of_num : integer -> VFPNegMul*)
+
+val _ = Define `
+ ((VFPNegMul_of_num:int -> VFPNegMul) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then VFPNegMul_VNMLA
+   else if (((p0_ = (( 1 : int):ii)))) then VFPNegMul_VNMLS
+   else VFPNegMul_VNMUL))`;
+
+
+(*val num_of_VFPNegMul : VFPNegMul -> integer*)
+
+val _ = Define `
+ ((num_of_VFPNegMul:VFPNegMul -> int) arg_=
+    ((case arg_ of
+     VFPNegMul_VNMLA => (( 0 : int):ii)
+   | VFPNegMul_VNMLS => (( 1 : int):ii)
+   | VFPNegMul_VNMUL => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_VFPNegMul : unit -> M VFPNegMul*)
+
+val _ = Define `
+ ((undefined_VFPNegMul:unit ->(regstate)sail2_state_monad$sequential_state ->(((VFPNegMul),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [VFPNegMul_VNMLA;VFPNegMul_VNMLS;VFPNegMul_VNMUL]))`;
+
+
+(*val VBitOps_of_num : integer -> VBitOps*)
+
+val _ = Define `
+ ((VBitOps_of_num:int -> VBitOps) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then VBitOps_VBIF
+   else if (((p0_ = (( 1 : int):ii)))) then VBitOps_VBIT
+   else VBitOps_VBSL))`;
+
+
+(*val num_of_VBitOps : VBitOps -> integer*)
+
+val _ = Define `
+ ((num_of_VBitOps:VBitOps -> int) arg_=
+    ((case arg_ of   VBitOps_VBIF => (( 0 : int):ii) | VBitOps_VBIT => (( 1 : int):ii) | VBitOps_VBSL => (( 2 : int):ii) )))`;
+
+
+(*val undefined_VBitOps : unit -> M VBitOps*)
+
+val _ = Define `
+ ((undefined_VBitOps:unit ->(regstate)sail2_state_monad$sequential_state ->(((VBitOps),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [VBitOps_VBIF;VBitOps_VBIT;VBitOps_VBSL]))`;
+
+
+(*val VCGEtype_of_num : integer -> VCGEtype*)
+
+val _ = Define `
+ ((VCGEtype_of_num:int -> VCGEtype) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then VCGEtype_signed
+   else if (((p0_ = (( 1 : int):ii)))) then VCGEtype_unsigned
+   else VCGEtype_fp))`;
+
+
+(*val num_of_VCGEtype : VCGEtype -> integer*)
+
+val _ = Define `
+ ((num_of_VCGEtype:VCGEtype -> int) arg_=
+    ((case arg_ of
+     VCGEtype_signed => (( 0 : int):ii)
+   | VCGEtype_unsigned => (( 1 : int):ii)
+   | VCGEtype_fp => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_VCGEtype : unit -> M VCGEtype*)
+
+val _ = Define `
+ ((undefined_VCGEtype:unit ->(regstate)sail2_state_monad$sequential_state ->(((VCGEtype),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [VCGEtype_signed;VCGEtype_unsigned;VCGEtype_fp]))`;
+
+
+(*val VCGTtype_of_num : integer -> VCGTtype*)
+
+val _ = Define `
+ ((VCGTtype_of_num:int -> VCGTtype) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then VCGTtype_signed
+   else if (((p0_ = (( 1 : int):ii)))) then VCGTtype_unsigned
+   else VCGTtype_fp))`;
+
+
+(*val num_of_VCGTtype : VCGTtype -> integer*)
+
+val _ = Define `
+ ((num_of_VCGTtype:VCGTtype -> int) arg_=
+    ((case arg_ of
+     VCGTtype_signed => (( 0 : int):ii)
+   | VCGTtype_unsigned => (( 1 : int):ii)
+   | VCGTtype_fp => (( 2 : int):ii)
+   )))`;
+
+
+(*val undefined_VCGTtype : unit -> M VCGTtype*)
+
+val _ = Define `
+ ((undefined_VCGTtype:unit ->(regstate)sail2_state_monad$sequential_state ->(((VCGTtype),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [VCGTtype_signed;VCGTtype_unsigned;VCGTtype_fp]))`;
+
+
+(*val __InstrEnc_of_num : integer -> __InstrEnc*)
+
+val _ = Define `
+ ((InstrEnc_of_num:int -> InstrEnc) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then A64
+   else if (((p0_ = (( 1 : int):ii)))) then A32
+   else if (((p0_ = (( 2 : int):ii)))) then T16
+   else T32))`;
+
+
+(*val num_of___InstrEnc : __InstrEnc -> integer*)
+
+val _ = Define `
+ ((num_of___InstrEnc:InstrEnc -> int) arg_=
+    ((case arg_ of   A64 => (( 0 : int):ii) | A32 => (( 1 : int):ii) | T16 => (( 2 : int):ii) | T32 => (( 3 : int):ii) )))`;
+
+
+(*val undefined___InstrEnc : unit -> M __InstrEnc*)
+
+val _ = Define `
+ ((undefined___InstrEnc:unit ->(regstate)sail2_state_monad$sequential_state ->(((InstrEnc),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [A64;A32;T16;T32]))`;
+
+
+(*val AArch64_CheckAndUpdateDescriptor_SecondStage : DescriptorUpdate -> FaultRecord -> mword ty64 -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+(*val AArch64_TranslationTableWalk_SecondStage : mword ty52 -> mword ty64 -> AccType -> bool -> bool -> ii -> M TLBRecord*)
+
+(*val AArch64_SecondStageTranslate : AddressDescriptor -> mword ty64 -> AccType -> bool -> bool -> bool -> ii -> bool -> M AddressDescriptor*)
+
+(*val AArch64_CheckAndUpdateDescriptor : DescriptorUpdate -> FaultRecord -> bool -> mword ty64 -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+(*val __UNKNOWN_real : unit -> real*)
+
+val _ = Define `
+ ((UNKNOWN_real:unit -> real) () =  (realFromFrac(( 0 : int))(( 10 : int))))`;
+
+
+(*val __UNKNOWN_integer : unit -> ii*)
+
+val _ = Define `
+ ((UNKNOWN_integer:unit -> int) () =  ((( 0 : int):ii)))`;
+
+
+(*val aget_PC : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((aget_PC:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  ((sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M)))`;
+
+
+(*val UndefinedFault : unit -> M unit*)
+
+val _ = Define `
+ ((UndefinedFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$assert_expS F "Undefined fault"))`;
+
+
+(*val ThisInstrAddr : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*)
+
+val _ = Define `
+ ((ThisInstrAddr:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+   sail2_state_monad$returnS ((slice w__0 (( 0 : int):ii) N__tv  :  'N words$word)))))`;
+
+
+(*val ThisInstr : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((ThisInstr0:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  ((sail2_state_monad$read_regS ThisInstr_ref  : ( 32 words$word) M)))`;
+
+
+(*val __UNKNOWN_SystemHintOp : unit -> SystemHintOp*)
+
+val _ = Define `
+ ((UNKNOWN_SystemHintOp:unit -> SystemHintOp) () =  SystemHintOp_NOP)`;
+
+
+(*val SynchronizeContext : unit -> unit*)
+
+val _ = Define `
+ ((SynchronizeContext:unit -> unit) () =  () )`;
+
+
+(*val SErrorPending : unit -> M bool*)
+
+val _ = Define `
+ ((SErrorPending:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$read_regS PendingPhysicalSError_ref))`;
+
+
+(*val ResetExternalDebugRegisters : bool -> unit*)
+
+val _ = Define `
+ ((ResetExternalDebugRegisters:bool -> unit) cold_reset=  () )`;
+
+
+(*val ProfilingSynchronizationBarrier : unit -> unit*)
+
+val _ = Define `
+ ((ProfilingSynchronizationBarrier:unit -> unit) () =  () )`;
+
+
+(*val ProcessorID : unit -> ii*)
+
+val _ = Define `
+ ((ProcessorID:unit -> int) () =  ((( 0 : int):ii)))`;
+
+
+(*val __UNKNOWN_PrefetchHint : unit -> PrefetchHint*)
+
+val _ = Define `
+ ((UNKNOWN_PrefetchHint:unit -> PrefetchHint) () =  Prefetch_READ)`;
+
+
+(*val __UNKNOWN_PSTATEField : unit -> PSTATEField*)
+
+val _ = Define `
+ ((UNKNOWN_PSTATEField:unit -> PSTATEField) () =  PSTATEField_DAIFSet)`;
+
+
+(*val PACCellShuffle : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((PACCellShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (outdata : 64 bits) . 
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 24 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) ((slice indata (( 44 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) ((slice indata (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 48 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) ((slice indata (( 40 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) ((slice indata (( 32 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) ((slice indata (( 56 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) ((slice indata (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 36 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) ((slice indata (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) ((slice indata (( 60 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   sail2_state_monad$returnS outdata)))`;
+
+
+(*val PACCellInvShuffle : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((PACCellInvShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (outdata : 64 bits) . 
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 24 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) ((slice indata (( 48 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 36 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) ((slice indata (( 56 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 44 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) ((slice indata (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) ((slice indata (( 32 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) ((slice indata (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) ((slice indata (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) ((slice indata (( 40 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) ((slice indata (( 60 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   sail2_state_monad$returnS outdata)))`;
+
+
+(*val __UNKNOWN_MoveWideOp : unit -> MoveWideOp*)
+
+val _ = Define `
+ ((UNKNOWN_MoveWideOp:unit -> MoveWideOp) () =  MoveWideOp_N)`;
+
+
+(*val __UNKNOWN_MemType : unit -> MemType*)
+
+val _ = Define `
+ ((UNKNOWN_MemType:unit -> MemType) () =  MemType_Normal)`;
+
+
+(*val __UNKNOWN_MemOp : unit -> MemOp*)
+
+val _ = Define `
+ ((UNKNOWN_MemOp:unit -> MemOp) () =  MemOp_LOAD)`;
+
+
+val _ = Define `
+((MemHint_RWA:(2)words$word)=  ((vec_of_bits [B1;B1]  :  2 words$word)))`;
+
+
+val _ = Define `
+((MemHint_RA:(2)words$word)=  ((vec_of_bits [B1;B0]  :  2 words$word)))`;
+
+
+val _ = Define `
+((MemHint_No:(2)words$word)=  ((vec_of_bits [B0;B0]  :  2 words$word)))`;
+
+
+(*val __UNKNOWN_MemBarrierOp : unit -> MemBarrierOp*)
+
+val _ = Define `
+ ((UNKNOWN_MemBarrierOp:unit -> MemBarrierOp) () =  MemBarrierOp_DSB)`;
+
+
+val _ = Define `
+((MemAttr_WT:(2)words$word)=  ((vec_of_bits [B1;B0]  :  2 words$word)))`;
+
+
+val _ = Define `
+((MemAttr_WB:(2)words$word)=  ((vec_of_bits [B1;B1]  :  2 words$word)))`;
+
+
+val _ = Define `
+((MemAttr_NC:(2)words$word)=  ((vec_of_bits [B0;B0]  :  2 words$word)))`;
+
+
+(*val __UNKNOWN_MemAtomicOp : unit -> MemAtomicOp*)
+
+val _ = Define `
+ ((UNKNOWN_MemAtomicOp:unit -> MemAtomicOp) () =  MemAtomicOp_ADD)`;
+
+
+(*val __UNKNOWN_MBReqTypes : unit -> MBReqTypes*)
+
+val _ = Define `
+ ((UNKNOWN_MBReqTypes:unit -> MBReqTypes) () =  MBReqTypes_Reads)`;
+
+
+(*val __UNKNOWN_MBReqDomain : unit -> MBReqDomain*)
+
+val _ = Define `
+ ((UNKNOWN_MBReqDomain:unit -> MBReqDomain) () =  MBReqDomain_Nonshareable)`;
+
+
+val _ = Define `
+((M32_User:(5)words$word)=  ((vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_Undef:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_System:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_Svc:(5)words$word)=  ((vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_Monitor:(5)words$word)=  ((vec_of_bits [B1;B0;B1;B1;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_IRQ:(5)words$word)=  ((vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_Hyp:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_FIQ:(5)words$word)=  ((vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((M32_Abort:(5)words$word)=  ((vec_of_bits [B1;B0;B1;B1;B1]  :  5 words$word)))`;
+
+
+(*val __UNKNOWN_LogicalOp : unit -> LogicalOp*)
+
+val _ = Define `
+ ((UNKNOWN_LogicalOp:unit -> LogicalOp) () =  LogicalOp_AND)`;
+
+
+(*val IsExclusiveLocal : FullAddress -> ii -> ii -> M bool*)
+
+val _ = Define `
+ ((IsExclusiveLocal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1=  (sail2_state_monad$read_regS ExclusiveLocal_ref))`;
+
+
+(*val InterruptPending : unit -> M bool*)
+
+val _ = Define `
+ ((InterruptPending:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$read_regS PendingInterrupt_ref))`;
+
+
+(*val asl_Int : forall 'N . Size 'N => mword 'N -> bool -> ii*)
+
+val _ = Define `
+ ((asl_Int:'N words$word -> bool -> int) x unsigned=  (if unsigned then lem$w2ui x else integer_word$w2i x))`;
+
+
+(*val InstructionSynchronizationBarrier : unit -> unit*)
+
+val _ = Define `
+ ((InstructionSynchronizationBarrier:unit -> unit) () =  () )`;
+
+
+(*val __UNKNOWN_InstrSet : unit -> InstrSet*)
+
+val _ = Define `
+ ((UNKNOWN_InstrSet:unit -> InstrSet) () =  InstrSet_A64)`;
+
+
+(*val Hint_Yield : unit -> unit*)
+
+val _ = Define `
+ ((Hint_Yield:unit -> unit) () =  () )`;
+
+
+(*val Hint_Prefetch : mword ty64 -> PrefetchHint -> ii -> bool -> unit*)
+
+val _ = Define `
+ ((Hint_Prefetch:(64)words$word -> PrefetchHint -> int -> bool -> unit) address hint target stream=  () )`;
+
+
+(*val Hint_Branch : BranchType -> unit*)
+
+val _ = Define `
+ ((Hint_Branch:BranchType -> unit) hint=  () )`;
+
+
+(*val HaveFP16Ext : unit -> bool*)
+
+val _ = Define `
+ ((HaveFP16Ext:unit -> bool) () =  T)`;
+
+
+(*val HaveAnyAArch32 : unit -> bool*)
+
+val _ = Define `
+ ((HaveAnyAArch32:unit -> bool) () =  F)`;
+
+
+(*val __UNKNOWN_Fault : unit -> Fault*)
+
+val _ = Define `
+ ((UNKNOWN_Fault:unit -> Fault) () =  Fault_None)`;
+
+
+(*val __UNKNOWN_FPUnaryOp : unit -> FPUnaryOp*)
+
+val _ = Define `
+ ((UNKNOWN_FPUnaryOp:unit -> FPUnaryOp) () =  FPUnaryOp_ABS)`;
+
+
+(*val __UNKNOWN_FPType : unit -> FPType*)
+
+val _ = Define `
+ ((UNKNOWN_FPType:unit -> FPType) () =  FPType_Nonzero)`;
+
+
+(*val __UNKNOWN_FPRounding : unit -> FPRounding*)
+
+val _ = Define `
+ ((UNKNOWN_FPRounding:unit -> FPRounding) () =  FPRounding_TIEEVEN)`;
+
+
+(*val __UNKNOWN_FPMaxMinOp : unit -> FPMaxMinOp*)
+
+val _ = Define `
+ ((UNKNOWN_FPMaxMinOp:unit -> FPMaxMinOp) () =  FPMaxMinOp_MAX)`;
+
+
+(*val FPDecodeRounding : mword ty2 -> FPRounding*)
+
+val _ = Define `
+ ((FPDecodeRounding:(2)words$word -> FPRounding) rmode=
+    (let b__0 = rmode in
+   if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then FPRounding_TIEEVEN
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then FPRounding_POSINF
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then FPRounding_NEGINF
+   else FPRounding_ZERO))`;
+
+
+(*val FPRoundingMode : mword ty32 -> FPRounding*)
+
+val _ = Define `
+ ((FPRoundingMode:(32)words$word -> FPRounding) fpcr=  (FPDecodeRounding ((slice fpcr (( 22 : int):ii) (( 2 : int):ii)  :  2 words$word))))`;
+
+
+(*val __UNKNOWN_FPConvOp : unit -> FPConvOp*)
+
+val _ = Define `
+ ((UNKNOWN_FPConvOp:unit -> FPConvOp) () =  FPConvOp_CVT_FtoI)`;
+
+
+(*val __UNKNOWN_boolean : unit -> bool*)
+
+val _ = Define `
+ ((UNKNOWN_boolean:unit -> bool) () =  F)`;
+
+
+(*val __ResetInterruptState : unit -> M unit*)
+
+val _ = Define `
+ ((ResetInterruptState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PendingPhysicalSError_ref F) (sail2_state_monad$write_regS PendingInterrupt_ref F)))`;
+
+
+(*val __ResetExecuteState : unit -> M unit*)
+
+val _ = Define `
+ ((ResetExecuteState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$write_regS Sleeping_ref F))`;
+
+
+(*val Unreachable : unit -> M unit*)
+
+val _ = Define `
+ ((Unreachable:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val RBankSelect : mword ty5 -> ii -> ii -> ii -> ii -> ii -> ii -> ii -> M ii*)
+
+val _ = Define `
+ ((RBankSelect:(5)words$word -> int -> int -> int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode usr fiq irq svc abt und hyp=  (sail2_state_monad$bindS
+   (undefined_int () ) (\ (result : ii) . 
+   let pat_0 = mode in
+   if (((pat_0 = M32_User))) then sail2_state_monad$returnS usr
+   else if (((pat_0 = M32_FIQ))) then sail2_state_monad$returnS fiq
+   else if (((pat_0 = M32_IRQ))) then sail2_state_monad$returnS irq
+   else if (((pat_0 = M32_Svc))) then sail2_state_monad$returnS svc
+   else if (((pat_0 = M32_Abort))) then sail2_state_monad$returnS abt
+   else if (((pat_0 = M32_Hyp))) then sail2_state_monad$returnS hyp
+   else if (((pat_0 = M32_Undef))) then sail2_state_monad$returnS und
+   else if (((pat_0 = M32_System))) then sail2_state_monad$returnS usr
+   else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result))))`;
+
+
+(*val TakeUnmaskedSErrorInterrupts : unit -> M unit*)
+
+val _ = Define `
+ ((TakeUnmaskedSErrorInterrupts:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val TakeUnmaskedPhysicalSErrorInterrupts : bool -> M unit*)
+
+val _ = Define `
+ ((TakeUnmaskedPhysicalSErrorInterrupts:bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) iesb_req=  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val StopInstructionPrefetchAndEnableITR : unit -> M unit*)
+
+val _ = Define `
+ ((StopInstructionPrefetchAndEnableITR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val SendEvent : unit -> M unit*)
+
+val _ = Define `
+ ((SendEvent:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val MarkExclusiveLocal : FullAddress -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((MarkExclusiveLocal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1=  (sail2_state_monad$write_regS ExclusiveLocal_ref F))`;
+
+
+(*val MarkExclusiveGlobal : FullAddress -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((MarkExclusiveGlobal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1=  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val IsExclusiveGlobal : FullAddress -> ii -> ii -> M bool*)
+
+val _ = Define `
+ ((IsExclusiveGlobal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1=  (sail2_state_monad$seqS (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS F)))`;
+
+
+(*val ExclusiveMonitorsStatus : unit -> M (mword ty1)*)
+
+val _ = Define `
+ ((ExclusiveMonitorsStatus:unit ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS (vec_of_bits [B0]  :  1 words$word))))`;
+
+
+(*val __UNKNOWN_Exception : unit -> Exception*)
+
+val _ = Define `
+ ((UNKNOWN_Exception:unit -> Exception) () =  Exception_Uncategorized)`;
+
+
+(*val SendEventLocal : unit -> M unit*)
+
+val _ = Define `
+ ((SendEventLocal:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$write_regS EventRegister_ref (vec_of_bits [B1]  :  1 words$word)))`;
+
+
+(*val ErrorSynchronizationBarrier : MBReqDomain -> MBReqTypes -> unit*)
+
+val _ = Define `
+ ((ErrorSynchronizationBarrier:MBReqDomain -> MBReqTypes -> unit) domain1 types=  () )`;
+
+
+(*val EnterLowPowerState : unit -> M unit*)
+
+val _ = Define `
+ ((EnterLowPowerState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$write_regS Sleeping_ref T))`;
+
+
+(*val WaitForInterrupt : unit -> M unit*)
+
+val _ = Define `
+ ((WaitForInterrupt:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (EnterLowPowerState () ))`;
+
+
+(*val EndOfInstruction : unit -> M unit*)
+
+val _ = Define `
+ ((EndOfInstruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$throwS (Error_ExceptionTaken () )))`;
+
+
+(*val TweakCellRot : mword ty4 -> M (mword ty4)*)
+
+val _ = Define `
+ ((TweakCellRot:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) incell_name=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (outcell : 4 bits) . 
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 3 : int):ii)
+        ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 : int):ii)]  :  1 words$word)
+            (vec_of_bits [access_vec_dec incell_name (( 1 : int):ii)]  :  1 words$word)
+           :  1 words$word))
+       :  4 words$word)) in
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 2 : int):ii)
+        (vec_of_bits [access_vec_dec incell_name (( 3 : int):ii)]  :  1 words$word)
+       :  4 words$word)) in
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 1 : int):ii)
+        (vec_of_bits [access_vec_dec incell_name (( 2 : int):ii)]  :  1 words$word)
+       :  4 words$word)) in
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 0 : int):ii)
+        (vec_of_bits [access_vec_dec incell_name (( 1 : int):ii)]  :  1 words$word)
+       :  4 words$word)) in
+   sail2_state_monad$returnS outcell)))`;
+
+
+(*val TweakShuffle : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((TweakShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (outdata : 64 bits) . 
+   let (outdata : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) ((slice indata (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 24 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__0 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) w__0  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 44 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__1 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) w__1  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 32 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__2 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) w__2  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) ((slice indata (( 48 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) ((slice indata (( 56 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 60 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__3 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) w__3  :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__4 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) w__4  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 40 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__5 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) w__5  :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellRot ((slice indata (( 36 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__6 :
+      4 words$word) . 
+   let (outdata : 64 bits) = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) w__6  :  64 words$word)) in
+   sail2_state_monad$returnS outdata))))))))))`;
+
+
+(*val TweakCellInvRot : mword ty4 -> M (mword ty4)*)
+
+val _ = Define `
+ ((TweakCellInvRot:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) incell_name=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (outcell : 4 bits) . 
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 3 : int):ii)
+        (vec_of_bits [access_vec_dec incell_name (( 2 : int):ii)]  :  1 words$word)
+       :  4 words$word)) in
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 2 : int):ii)
+        (vec_of_bits [access_vec_dec incell_name (( 1 : int):ii)]  :  1 words$word)
+       :  4 words$word)) in
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 1 : int):ii)
+        (vec_of_bits [access_vec_dec incell_name (( 0 : int):ii)]  :  1 words$word)
+       :  4 words$word)) in
+   let (outcell : 4 bits) =
+     ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 0 : int):ii)
+        ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 : int):ii)]  :  1 words$word)
+            (vec_of_bits [access_vec_dec incell_name (( 3 : int):ii)]  :  1 words$word)
+           :  1 words$word))
+       :  4 words$word)) in
+   sail2_state_monad$returnS outcell)))`;
+
+
+(*val TweakInvShuffle : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((TweakInvShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (outdata : 64 bits) .  sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 48 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__0 :
+      4 words$word) . 
+   let (outdata : 64 bits) = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) w__0  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 24 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) ((slice indata (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__1 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) w__1  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__2 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) w__2  :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 60 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__3 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) w__3  :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 56 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__4 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) w__4  :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__5 :
+      4 words$word) . 
+   let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) w__5  :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) ((slice indata (( 32 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 36 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in
+   let outdata =
+     ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) ((slice indata (( 40 : int):ii) (( 4 : int):ii)  :  4 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TweakCellInvRot ((slice indata (( 44 : int):ii) (( 4 : int):ii)  :  4 words$word))  : ( 4 words$word) M) (\ (w__6 :
+      4 words$word) . 
+   let (outdata : 64 bits) = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) w__6  :  64 words$word)) in
+   sail2_state_monad$returnS outdata))))))))))`;
+
+
+val _ = Define `
+((EL3:(2)words$word)=  ((vec_of_bits [B1;B1]  :  2 words$word)))`;
+
+
+val _ = Define `
+((EL2:(2)words$word)=  ((vec_of_bits [B1;B0]  :  2 words$word)))`;
+
+
+val _ = Define `
+((EL1:(2)words$word)=  ((vec_of_bits [B0;B1]  :  2 words$word)))`;
+
+
+val _ = Define `
+((EL0:(2)words$word)=  ((vec_of_bits [B0;B0]  :  2 words$word)))`;
+
+
+(*val __UNKNOWN_DeviceType : unit -> DeviceType*)
+
+val _ = Define `
+ ((UNKNOWN_DeviceType:unit -> DeviceType) () =  DeviceType_GRE)`;
+
+
+(*val DecodeShift : mword ty2 -> ShiftType*)
+
+val _ = Define `
+ ((DecodeShift:(2)words$word -> ShiftType) op=
+    (let b__0 = op in
+   if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then ShiftType_LSL
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then ShiftType_LSR
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then ShiftType_ASR
+   else ShiftType_ROR))`;
+
+
+(*val DecodeRegExtend : mword ty3 -> ExtendType*)
+
+val _ = Define `
+ ((DecodeRegExtend:(3)words$word -> ExtendType) op=
+    (let b__0 = op in
+   if (((b__0 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then ExtendType_UXTB
+   else if (((b__0 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then ExtendType_UXTH
+   else if (((b__0 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then ExtendType_UXTW
+   else if (((b__0 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then ExtendType_UXTX
+   else if (((b__0 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then ExtendType_SXTB
+   else if (((b__0 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then ExtendType_SXTH
+   else if (((b__0 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then ExtendType_SXTW
+   else ExtendType_SXTX))`;
+
+
+val _ = Define `
+((DebugHalt_Watchpoint:(6)words$word)=  ((vec_of_bits [B1;B0;B1;B0;B1;B1]  :  6 words$word)))`;
+
+
+val _ = Define `
+((DebugHalt_HaltInstruction:(6)words$word)=  ((vec_of_bits [B1;B0;B1;B1;B1;B1]  :  6 words$word)))`;
+
+
+val _ = Define `
+((DebugHalt_Breakpoint:(6)words$word)=  ((vec_of_bits [B0;B0;B0;B1;B1;B1]  :  6 words$word)))`;
+
+
+val _ = Define `
+((DebugException_VectorCatch:(4)words$word)=  ((vec_of_bits [B0;B1;B0;B1]  :  4 words$word)))`;
+
+
+(*val DataSynchronizationBarrier : MBReqDomain -> MBReqTypes -> unit*)
+
+val _ = Define `
+ ((DataSynchronizationBarrier:MBReqDomain -> MBReqTypes -> unit) domain1 types=  () )`;
+
+
+(*val DataMemoryBarrier : MBReqDomain -> MBReqTypes -> unit*)
+
+val _ = Define `
+ ((DataMemoryBarrier:MBReqDomain -> MBReqTypes -> unit) domain1 types=  () )`;
+
+
+(*val aarch64_system_barriers : MBReqDomain -> MemBarrierOp -> MBReqTypes -> unit*)
+
+val _ = Define `
+ ((aarch64_system_barriers:MBReqDomain -> MemBarrierOp -> MBReqTypes -> unit) domain1 op types=
+    ((case op of
+     MemBarrierOp_DSB => DataSynchronizationBarrier domain1 types
+   | MemBarrierOp_DMB => DataMemoryBarrier domain1 types
+   | MemBarrierOp_ISB => InstructionSynchronizationBarrier () 
+   )))`;
+
+
+(*val __UNKNOWN_Constraint : unit -> Constraint*)
+
+val _ = Define `
+ ((UNKNOWN_Constraint:unit -> Constraint) () =  Constraint_NONE)`;
+
+
+(*val ConstrainUnpredictable : Unpredictable -> Constraint*)
+
+val _ = Define `
+ ((ConstrainUnpredictable:Unpredictable -> Constraint) which=
+    ((case which of
+     Unpredictable_WBOVERLAPLD => Constraint_WBSUPPRESS
+   | Unpredictable_WBOVERLAPST => Constraint_NONE
+   | Unpredictable_LDPOVERLAP => Constraint_UNDEF
+   | Unpredictable_BASEOVERLAP => Constraint_NONE
+   | Unpredictable_DATAOVERLAP => Constraint_NONE
+   | Unpredictable_DEVPAGE2 => Constraint_FAULT
+   | Unpredictable_INSTRDEVICE => Constraint_NONE
+   | Unpredictable_RESCPACR => Constraint_UNKNOWN
+   | Unpredictable_RESMAIR => Constraint_UNKNOWN
+   | Unpredictable_RESTEXCB => Constraint_UNKNOWN
+   | Unpredictable_RESDACR => Constraint_UNKNOWN
+   | Unpredictable_RESPRRR => Constraint_UNKNOWN
+   | Unpredictable_RESVTCRS => Constraint_UNKNOWN
+   | Unpredictable_RESTnSZ => Constraint_FORCE
+   | Unpredictable_OORTnSZ => Constraint_FORCE
+   | Unpredictable_LARGEIPA => Constraint_FORCE
+   | Unpredictable_ESRCONDPASS => Constraint_FALSE
+   | Unpredictable_ILZEROIT => Constraint_FALSE
+   | Unpredictable_ILZEROT => Constraint_FALSE
+   | Unpredictable_BPVECTORCATCHPRI => Constraint_TRUE
+   | Unpredictable_VCMATCHHALF => Constraint_FALSE
+   | Unpredictable_VCMATCHDAPA => Constraint_FALSE
+   | Unpredictable_WPMASKANDBAS => Constraint_FALSE
+   | Unpredictable_WPBASCONTIGUOUS => Constraint_FALSE
+   | Unpredictable_RESWPMASK => Constraint_DISABLED
+   | Unpredictable_WPMASKEDBITS => Constraint_FALSE
+   | Unpredictable_RESBPWPCTRL => Constraint_DISABLED
+   | Unpredictable_BPNOTIMPL => Constraint_DISABLED
+   | Unpredictable_RESBPTYPE => Constraint_DISABLED
+   | Unpredictable_BPNOTCTXCMP => Constraint_DISABLED
+   | Unpredictable_BPMATCHHALF => Constraint_FALSE
+   | Unpredictable_BPMISMATCHHALF => Constraint_FALSE
+   | Unpredictable_RESTARTALIGNPC => Constraint_FALSE
+   | Unpredictable_RESTARTZEROUPPERPC => Constraint_TRUE
+   | Unpredictable_ZEROUPPER => Constraint_TRUE
+   | Unpredictable_ERETZEROUPPERPC => Constraint_TRUE
+   | Unpredictable_A32FORCEALIGNPC => Constraint_FALSE
+   | Unpredictable_SMD => Constraint_UNDEF
+   | Unpredictable_AFUPDATE => Constraint_TRUE
+   | Unpredictable_IESBinDebug => Constraint_TRUE
+   | Unpredictable_CLEARERRITEZERO => Constraint_FALSE
+   )))`;
+
+
+(*val ClearPendingPhysicalSError : unit -> M unit*)
+
+val _ = Define `
+ ((ClearPendingPhysicalSError:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$write_regS PendingPhysicalSError_ref F))`;
+
+
+(*val ClearExclusiveLocal : ii -> M unit*)
+
+val _ = Define `
+ ((ClearExclusiveLocal:int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) processorid=  (sail2_state_monad$write_regS ExclusiveLocal_ref F))`;
+
+
+(*val aarch64_system_monitors : unit -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_monitors:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (ClearExclusiveLocal ((ProcessorID () ))))`;
+
+
+(*val system_monitors_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((system_monitors_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T) (aarch64_system_monitors () )))`;
+
+
+(*val ClearExclusiveByAddress : FullAddress -> ii -> ii -> unit*)
+
+val _ = Define `
+ ((ClearExclusiveByAddress:FullAddress -> int -> int -> unit) paddress processorid size1=  () )`;
+
+
+(*val ClearEventRegister : unit -> M unit*)
+
+val _ = Define `
+ ((ClearEventRegister:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$write_regS EventRegister_ref (vec_of_bits [B0]  :  1 words$word)))`;
+
+
+(*val CTI_SignalEvent : CrossTriggerIn -> M unit*)
+
+val _ = Define `
+ ((CTI_SignalEvent:CrossTriggerIn ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) id=  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val __UNKNOWN_BranchType : unit -> BranchType*)
+
+val _ = Define `
+ ((UNKNOWN_BranchType:unit -> BranchType) () =  BranchType_CALL)`;
+
+
+(*val __UNKNOWN_AccType : unit -> AccType*)
+
+val _ = Define `
+ ((UNKNOWN_AccType:unit -> AccType) () =  AccType_NORMAL)`;
+
+
+(*val CreateAccessDescriptorPTW : AccType -> bool -> bool -> ii -> M AccessDescriptor*)
+
+val _ = Define `
+ ((CreateAccessDescriptorPTW:AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AccessDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype secondstage s2fs1walk level=  (sail2_state_monad$bindS
+   (undefined_AccessDescriptor () ) (\ (accdesc : AccessDescriptor) . 
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_acctype := acctype|>)) in
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_page_table_walk := T|>)) in
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_secondstage := s2fs1walk|>)) in
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_secondstage := secondstage|>)) in
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_level := level|>)) in
+   sail2_state_monad$returnS accdesc)))`;
+
+
+(*val CreateAccessDescriptor : AccType -> M AccessDescriptor*)
+
+val _ = Define `
+ ((CreateAccessDescriptor:AccType ->(regstate)sail2_state_monad$sequential_state ->(((AccessDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype=  (sail2_state_monad$bindS
+   (undefined_AccessDescriptor () ) (\ (accdesc : AccessDescriptor) . 
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_acctype := acctype|>)) in
+   let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_page_table_walk := F|>)) in
+   sail2_state_monad$returnS accdesc)))`;
+
+
+(*val aarch64_system_register_cpsr : PSTATEField -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_register_cpsr:PSTATEField ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) field' operand=
+    ((case field' of
+     PSTATEField_SP => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__0 with<| ProcState_SP := ((vec_of_bits [access_vec_dec operand (( 0 : int):ii)]  :  1 words$word))|>))
+   | PSTATEField_DAIFSet => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__1 with<|
+          ProcState_D :=
+            ((or_vec w__2.ProcState_D (vec_of_bits [access_vec_dec operand (( 3 : int):ii)]  :  1 words$word)
+               :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__3 with<|
+          ProcState_A :=
+            ((or_vec w__4.ProcState_A (vec_of_bits [access_vec_dec operand (( 2 : int):ii)]  :  1 words$word)
+               :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__5 with<|
+          ProcState_I :=
+            ((or_vec w__6.ProcState_I (vec_of_bits [access_vec_dec operand (( 1 : int):ii)]  :  1 words$word)
+               :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__7 with<|
+          ProcState_F :=
+            ((or_vec w__8.ProcState_F (vec_of_bits [access_vec_dec operand (( 0 : int):ii)]  :  1 words$word)
+               :  1 words$word))|>)))))))))
+   | PSTATEField_DAIFClr => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__9 with<|
+          ProcState_D :=
+            ((and_vec w__10.ProcState_D
+                ((not_vec (vec_of_bits [access_vec_dec operand (( 3 : int):ii)]  :  1 words$word)  :  1 words$word))
+               :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__11 with<|
+          ProcState_A :=
+            ((and_vec w__12.ProcState_A
+                ((not_vec (vec_of_bits [access_vec_dec operand (( 2 : int):ii)]  :  1 words$word)  :  1 words$word))
+               :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__13 with<|
+          ProcState_I :=
+            ((and_vec w__14.ProcState_I
+                ((not_vec (vec_of_bits [access_vec_dec operand (( 1 : int):ii)]  :  1 words$word)  :  1 words$word))
+               :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__15 with<|
+          ProcState_F :=
+            ((and_vec w__16.ProcState_F
+                ((not_vec (vec_of_bits [access_vec_dec operand (( 0 : int):ii)]  :  1 words$word)  :  1 words$word))
+               :  1 words$word))|>)))))))))
+   | PSTATEField_PAN => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__17 with<| ProcState_PAN := ((vec_of_bits [access_vec_dec operand (( 0 : int):ii)]  :  1 words$word))|>))
+   | PSTATEField_UAO => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__18 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__18 with<| ProcState_UAO := ((vec_of_bits [access_vec_dec operand (( 0 : int):ii)]  :  1 words$word))|>))
+   )))`;
+
+
+(*val AArch64_SysRegWrite : ii -> ii -> ii -> ii -> ii -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((AArch64_SysRegWrite:int -> int -> int -> int -> int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 val_name=  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val AArch64_SysRegRead : ii -> ii -> ii -> ii -> ii -> M (mword ty64)*)
+
+val _ = Define `
+ ((AArch64_SysRegRead:int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4=
+    (let g__301 = (arg0, arg1, arg2, arg3, arg4) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "Tried to read system register")
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)))`;
+
+
+(*val AArch64_SysInstr : ii -> ii -> ii -> ii -> ii -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((AArch64_SysInstr:int -> int -> int -> int -> int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 val_name=  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val AArch64_ResetControlRegisters : bool -> unit*)
+
+val _ = Define `
+ ((AArch64_ResetControlRegisters:bool -> unit) cold_reset=  () )`;
+
+
+(*val AArch64_ReportDeferredSError : mword ty25 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AArch64_ReportDeferredSError:(25)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) syndrome=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (target : 64 bits) . 
+   let (target : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 1 : int):ii) target (( 31 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word)) in
+   let (target : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 1 : int):ii) target (( 24 : int):ii)
+        (vec_of_bits [access_vec_dec syndrome (( 24 : int):ii)]  :  1 words$word)
+       :  64 words$word)) in
+   let (target : 64 bits) =
+     ((set_slice (( 64 : int):ii) (( 24 : int):ii) target (( 0 : int):ii) ((slice syndrome (( 0 : int):ii) (( 24 : int):ii)  :  24 words$word))
+       :  64 words$word)) in
+   sail2_state_monad$returnS target)))`;
+
+
+(*val AArch64_MarkExclusiveVA : mword ty64 -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((AArch64_MarkExclusiveVA:(64)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address processorid size1=  (sail2_state_monad$assert_expS F "FALSE"))`;
+
+
+(*val AArch64_IsExclusiveVA : mword ty64 -> ii -> ii -> M bool*)
+
+val _ = Define `
+ ((AArch64_IsExclusiveVA:(64)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address processorid size1=  (sail2_state_monad$seqS (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS F)))`;
+
+
+(*val AArch64_CreateFaultRecord : Fault -> mword ty52 -> ii -> AccType -> bool -> mword ty1 -> mword ty2 -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_CreateFaultRecord:Fault ->(52)words$word -> int -> AccType -> bool ->(1)words$word ->(2)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ ipaddress level acctype write extflag errortype secondstage s2fs1walk=  (sail2_state_monad$bindS
+   (undefined_FaultRecord () ) (\ (fault : FaultRecord) . 
+   let fault = ((fault with<| FaultRecord_typ := typ|>)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__0 : 4 bits) . 
+   let fault = ((fault with<| FaultRecord_domain := w__0|>)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__1 : 4 bits) . 
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_debugmoe := w__1|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_errortype := errortype|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_ipaddress := ipaddress|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_level := level|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_acctype := acctype|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_write := write|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_extflag := extflag|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_secondstage := secondstage|>)) in
+   let (fault : FaultRecord) = ((fault with<| FaultRecord_s2fs1walk := s2fs1walk|>)) in
+   sail2_state_monad$returnS fault)))))`;
+
+
+(*val AArch64_TranslationFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_TranslationFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) . 
+   AArch64_CreateFaultRecord Fault_Translation ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk))))`;
+
+
+(*val AArch64_PermissionFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_PermissionFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) . 
+   AArch64_CreateFaultRecord Fault_Permission ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk))))`;
+
+
+(*val AArch64_NoFault : unit -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_NoFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (level : ii) . 
+   let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) . 
+   let (secondstage : bool) = F in
+   let (s2fs1walk : bool) = F in
+   AArch64_CreateFaultRecord Fault_None ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk)))))))`;
+
+
+(*val AArch64_DebugFault : AccType -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_DebugFault:AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype iswrite=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (level : ii) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) . 
+   let (secondstage : bool) = F in
+   let (s2fs1walk : bool) = F in
+   AArch64_CreateFaultRecord Fault_Debug ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk))))))`;
+
+
+(*val AArch64_CheckUnallocatedSystemAccess : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M bool*)
+
+val _ = Define `
+ ((AArch64_CheckUnallocatedSystemAccess:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 read=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS F)))`;
+
+
+(*val AArch64_CheckSystemRegisterTraps : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M (bool * mword ty2)*)
+
+val _ = Define `
+ ((AArch64_CheckSystemRegisterTraps:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 read=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS (F, (vec_of_bits [B0;B0]  :  2 words$word)))))`;
+
+
+(*val AArch64_CheckAdvSIMDFPSystemRegisterTraps : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M (bool * mword ty2)*)
+
+val _ = Define `
+ ((AArch64_CheckAdvSIMDFPSystemRegisterTraps:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 read=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS (F, (vec_of_bits [B0;B0]  :  2 words$word)))))`;
+
+
+(*val AArch64_AlignmentFault : AccType -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_AlignmentFault:AccType -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype iswrite secondstage=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (level : ii) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) . 
+   AArch64_CreateFaultRecord Fault_Alignment ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk)))))))`;
+
+
+(*val AArch64_AddressSizeFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_AddressSizeFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) . 
+   AArch64_CreateFaultRecord Fault_AddressSize ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk))))`;
+
+
+(*val AArch64_AccessFlagFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_AccessFlagFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (extflag : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (errortype : 2 bits) . 
+   AArch64_CreateFaultRecord Fault_AccessFlag ipaddress level acctype iswrite extflag errortype
+     secondstage s2fs1walk))))`;
+
+
+(*val AArch32_CurrentCond : unit -> M (mword ty4)*)
+
+val _ = Define `
+ ((AArch32_CurrentCond:unit ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  ((sail2_state_monad$read_regS currentCond_ref  : ( 4 words$word) M)))`;
+
+
+(*val aget_SP : forall 'width . Size 'width => integer -> unit -> M (mword 'width)*)
+
+val _ = Define `
+ ((aget_SP:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) () =  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ (((width__tv = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . 
+   if (((w__0.ProcState_SP = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS SP_EL0_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+     sail2_state_monad$returnS ((slice w__1 (( 0 : int):ii) width__tv  :  'width words$word)))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+     let p__300 = (w__2.ProcState_EL) in
+     let pat_0 = p__300 in
+     if (((pat_0 = EL0))) then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS SP_EL0_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+       sail2_state_monad$returnS ((slice w__3 (( 0 : int):ii) width__tv  :  'width words$word)))
+     else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS SP_EL1_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+       sail2_state_monad$returnS ((slice w__4 (( 0 : int):ii) width__tv  :  'width words$word)))
+     else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS SP_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+       sail2_state_monad$returnS ((slice w__5 (( 0 : int):ii) width__tv  :  'width words$word)))
+     else sail2_state_monad$bindS
+       (sail2_state_monad$read_regS SP_EL3_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+       sail2_state_monad$returnS ((slice w__6 (( 0 : int):ii) width__tv  :  'width words$word)))))))`;
+
+
+(*val __IMPDEF_integer : string -> ii*)
+
+val _ = Define `
+ ((IMPDEF_integer:string -> int) x=
+    (if (((x = "Maximum Physical Address Size"))) then (( 52 : int):ii)
+   else if (((x = "Maximum Virtual Address Size"))) then (( 56 : int):ii)
+   else (( 0 : int):ii)))`;
+
+
+(*val VAMax : unit -> ii*)
+
+val _ = Define `
+ ((VAMax:unit -> int) () =  (IMPDEF_integer "Maximum Virtual Address Size"))`;
+
+
+(*val PAMax : unit -> ii*)
+
+val _ = Define `
+ ((PAMax:unit -> int) () =  (IMPDEF_integer "Maximum Physical Address Size"))`;
+
+
+(*val __IMPDEF_boolean : string -> bool*)
+
+val _ = Define `
+ ((IMPDEF_boolean:string -> bool) x=
+    (if (((x = "Condition valid for trapped T32"))) then T
+   else if (((x = "Has Dot Product extension"))) then T
+   else if (((x = "Has RAS extension"))) then T
+   else if (((x = "Has SHA512 and SHA3 Crypto instructions"))) then T
+   else if (((x = "Has SM3 and SM4 Crypto instructions"))) then T
+   else if (((x = "Has basic Crypto instructions"))) then T
+   else if (((x = "Have CRC extension"))) then T
+   else if (((x = "Report I-cache maintenance fault in IFSR"))) then T
+   else if (((x = "Reserved Control Space EL0 Trapped"))) then T
+   else if (((x = "Translation fault on misprogrammed contiguous bit"))) then T
+   else if (((x = "UNDEF unallocated CP15 access at NS EL0"))) then T
+   else if (((x = "UNDEF unallocated CP15 access at NS EL0"))) then T
+   else F))`;
+
+
+(*val WaitForEvent : unit -> M unit*)
+
+val _ = Define `
+ ((WaitForEvent:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS EventRegister_ref  : ( 1 words$word) M) (\ (w__0 : 1 bits) . 
+   if (((w__0 = (vec_of_bits [B0]  :  1 words$word)))) then EnterLowPowerState () 
+   else sail2_state_monad$returnS () )))`;
+
+
+(*val ThisInstrLength : unit -> M ii*)
+
+val _ = Define `
+ ((ThisInstrLength:unit ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS ThisInstrEnc_ref) (\ (w__0 : InstrEnc) . 
+   sail2_state_monad$returnS (if (((w__0 = T16))) then (( 16 : int):ii)
+           else (( 32 : int):ii)))))`;
+
+
+(*val RoundTowardsZero : real -> ii*)
+
+val _ = Define `
+ ((RoundTowardsZero:real -> int) x=
+    (if (((x = (realFromFrac(( 0 : int))(( 10 : int)))))) then (( 0 : int):ii)
+   else if ((x >= (realFromFrac(( 0 : int))(( 10 : int))))) then flr x
+   else clg x))`;
+
+
+(*val Restarting : unit -> M bool*)
+
+val _ = Define `
+ ((Restarting:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+   sail2_state_monad$returnS (((((slice w__0 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))))))`;
+
+
+(*val PtrHasUpperAndLowerAddRanges : unit -> M bool*)
+
+val _ = Define `
+ ((PtrHasUpperAndLowerAddRanges:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$or_boolS
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL1)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$returnS (((w__1.ProcState_EL = EL0))))))
+     (sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$returnS (((w__3.ProcState_EL = EL2)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))))`;
+
+
+(*val MemAttrDefaults : MemoryAttributes -> M MemoryAttributes*)
+
+val _ = Define `
+ ((MemAttrDefaults:MemoryAttributes ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) memattrs__arg=
+    (let memattrs = memattrs__arg in
+   if (((memattrs.MemoryAttributes_typ = MemType_Device))) then sail2_state_monad$bindS
+     (undefined_MemAttrHints () ) (\ (w__0 : MemAttrHints) . 
+     let memattrs = ((memattrs with<| MemoryAttributes_inner := w__0|>)) in sail2_state_monad$bindS
+     (undefined_MemAttrHints () ) (\ (w__1 : MemAttrHints) . 
+     let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_outer := w__1|>)) in
+     let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_shareable := T|>)) in
+     let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_outershareable := T|>)) in
+     sail2_state_monad$returnS memattrs))
+   else sail2_state_monad$bindS
+     (undefined_DeviceType () ) (\ (w__2 : DeviceType) . 
+     let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_device := w__2|>)) in
+     let (memattrs : MemoryAttributes) =
+       (if ((((((memattrs.MemoryAttributes_inner.MemAttrHints_attrs = MemAttr_NC))) /\ (((memattrs.MemoryAttributes_outer.MemAttrHints_attrs = MemAttr_NC)))))) then
+         let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_shareable := T|>)) in
+         (memattrs with<| MemoryAttributes_outershareable := T|>)
+       else memattrs) in
+     sail2_state_monad$returnS memattrs)))`;
+
+
+(*val IsEventRegisterSet : unit -> M bool*)
+
+val _ = Define `
+ ((IsEventRegisterSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS EventRegister_ref  : ( 1 words$word) M) (\ (w__0 : 1 bits) . 
+   sail2_state_monad$returnS (((w__0 = (vec_of_bits [B1]  :  1 words$word)))))))`;
+
+
+(*val HaveEL : mword ty2 -> bool*)
+
+val _ = Define `
+ ((HaveEL:(2)words$word -> bool) el=  (if ((((((el = EL1))) \/ (((el = EL0)))))) then T else T))`;
+
+
+(*val HighestEL : unit -> mword ty2*)
+
+val _ = Define `
+ ((HighestEL:unit ->(2)words$word) () =  (if ((HaveEL EL3)) then EL3 else if ((HaveEL EL2)) then EL2 else EL1))`;
+
+
+(*val Have16bitVMID : unit -> bool*)
+
+val _ = Define `
+ ((Have16bitVMID:unit -> bool) () =  (HaveEL EL2))`;
+
+
+(*val HasArchVersion : ArchVersion -> bool*)
+
+val _ = Define `
+ ((HasArchVersion:ArchVersion -> bool) version=
+    ((((version = ARMv8p0))) \/ ((((((version = ARMv8p1))) \/ ((((((version = ARMv8p2))) \/ (((version = ARMv8p3)))))))))))`;
+
+
+(*val HaveVirtHostExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveVirtHostExt:unit -> bool) () =  (HasArchVersion ARMv8p1))`;
+
+
+(*val HaveUAOExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveUAOExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val HaveTrapLoadStoreMultipleDeviceExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveTrapLoadStoreMultipleDeviceExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val HaveStatisticalProfiling : unit -> bool*)
+
+val _ = Define `
+ ((HaveStatisticalProfiling:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val HaveRASExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveRASExt:unit -> bool) () =  (((HasArchVersion ARMv8p2)) \/ ((IMPDEF_boolean "Has RAS extension"))))`;
+
+
+(*val HavePrivATExt : unit -> bool*)
+
+val _ = Define `
+ ((HavePrivATExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val HavePANExt : unit -> bool*)
+
+val _ = Define `
+ ((HavePANExt:unit -> bool) () =  (HasArchVersion ARMv8p1))`;
+
+
+(*val HavePACExt : unit -> bool*)
+
+val _ = Define `
+ ((HavePACExt:unit -> bool) () =  (HasArchVersion ARMv8p3))`;
+
+
+(*val HaveNVExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveNVExt:unit -> bool) () =  (HasArchVersion ARMv8p3))`;
+
+
+(*val HaveFJCVTZSExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveFJCVTZSExt:unit -> bool) () =  (HasArchVersion ARMv8p3))`;
+
+
+(*val HaveExtendedExecuteNeverExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveExtendedExecuteNeverExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val HaveDirtyBitModifierExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveDirtyBitModifierExt:unit -> bool) () =  (HasArchVersion ARMv8p1))`;
+
+
+(*val HaveCommonNotPrivateTransExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveCommonNotPrivateTransExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val HaveCRCExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveCRCExt:unit -> bool) () =  (((HasArchVersion ARMv8p1)) \/ ((IMPDEF_boolean "Have CRC extension"))))`;
+
+
+(*val HaveAtomicExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveAtomicExt:unit -> bool) () =  (HasArchVersion ARMv8p1))`;
+
+
+(*val HaveAccessFlagUpdateExt : unit -> bool*)
+
+val _ = Define `
+ ((HaveAccessFlagUpdateExt:unit -> bool) () =  (HasArchVersion ARMv8p1))`;
+
+
+(*val Have52BitVAExt : unit -> bool*)
+
+val _ = Define `
+ ((Have52BitVAExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val Have52BitPAExt : unit -> bool*)
+
+val _ = Define `
+ ((Have52BitPAExt:unit -> bool) () =  (HasArchVersion ARMv8p2))`;
+
+
+(*val AArch64_HaveHPDExt : unit -> bool*)
+
+val _ = Define `
+ ((AArch64_HaveHPDExt:unit -> bool) () =  (HasArchVersion ARMv8p1))`;
+
+
+(*val ExternalInvasiveDebugEnabled : unit -> M bool*)
+
+val _ = Define `
+ ((ExternalInvasiveDebugEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGEN_ref) (\ (w__0 : signal) .  sail2_state_monad$returnS (((w__0 = HIGH))))))`;
+
+
+(*val ConstrainUnpredictableInteger : ii -> ii -> Unpredictable -> M (Constraint * ii)*)
+
+val _ = Define `
+ ((ConstrainUnpredictableInteger:int -> int -> Unpredictable ->(regstate)sail2_state_monad$sequential_state ->(((Constraint#int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) low high which=
+    (let (c : Constraint) = (ConstrainUnpredictable which) in
+   if (((c = Constraint_UNKNOWN))) then sail2_state_monad$returnS (c, low)
+   else sail2_state_monad$bindS (undefined_int () ) (\ (w__0 : ii) .  sail2_state_monad$returnS (c, w__0))))`;
+
+
+(*val ConstrainUnpredictableBool : Unpredictable -> M bool*)
+
+val _ = Define `
+ ((ConstrainUnpredictableBool:Unpredictable ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) which=
+    (let (c : Constraint) = (ConstrainUnpredictable which) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((c = Constraint_TRUE))) \/ (((c = Constraint_FALSE)))))) "((c == Constraint_TRUE) || (c == Constraint_FALSE))")
+   (sail2_state_monad$returnS (((c = Constraint_TRUE))))))`;
+
+
+(*val CombineS1S2Device : DeviceType -> DeviceType -> M DeviceType*)
+
+val _ = Define `
+ ((CombineS1S2Device:DeviceType -> DeviceType ->(regstate)sail2_state_monad$sequential_state ->(((DeviceType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s1device s2device=  (sail2_state_monad$bindS
+   (undefined_DeviceType () ) (\ (result : DeviceType) . 
+   let (result : DeviceType) =
+     (if ((((((s2device = DeviceType_nGnRnE))) \/ (((s1device = DeviceType_nGnRnE)))))) then
+       DeviceType_nGnRnE
+     else if ((((((s2device = DeviceType_nGnRE))) \/ (((s1device = DeviceType_nGnRE)))))) then
+       DeviceType_nGnRE
+     else if ((((((s2device = DeviceType_nGRE))) \/ (((s1device = DeviceType_nGRE)))))) then
+       DeviceType_nGRE
+     else DeviceType_GRE) in
+   sail2_state_monad$returnS result)))`;
+
+
+(*val CombineS1S2AttrHints : MemAttrHints -> MemAttrHints -> M MemAttrHints*)
+
+val _ = Define `
+ ((CombineS1S2AttrHints:MemAttrHints -> MemAttrHints ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s1desc s2desc=  (sail2_state_monad$bindS
+   (undefined_MemAttrHints () ) (\ (result : MemAttrHints) .  sail2_state_monad$bindS
+   (if ((((((s2desc.MemAttrHints_attrs = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ (((s1desc.MemAttrHints_attrs = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$bindS
+      (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__0 : 2 bits) . 
+      let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := w__0|>)) in
+      sail2_state_monad$returnS result)
+    else
+      let (result : MemAttrHints) =
+        (if ((((((s2desc.MemAttrHints_attrs = MemAttr_NC))) \/ (((s1desc.MemAttrHints_attrs = MemAttr_NC)))))) then
+          (result with<| MemAttrHints_attrs := MemAttr_NC|>)
+        else if ((((((s2desc.MemAttrHints_attrs = MemAttr_WT))) \/ (((s1desc.MemAttrHints_attrs = MemAttr_WT)))))) then
+          (result with<| MemAttrHints_attrs := MemAttr_WT|>)
+        else (result with<| MemAttrHints_attrs := MemAttr_WB|>)) in
+      sail2_state_monad$returnS result) (\ (result : MemAttrHints) . 
+   let (result : MemAttrHints) = ((result with<| MemAttrHints_hints := (s1desc.MemAttrHints_hints)|>)) in
+   let (result : MemAttrHints) =
+     ((result with<| MemAttrHints_transient := (s1desc.MemAttrHints_transient)|>)) in
+   sail2_state_monad$returnS result))))`;
+
+
+(*val AArch64_InstructionDevice : AddressDescriptor -> mword ty64 -> mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M AddressDescriptor*)
+
+val _ = Define `
+ ((AArch64_InstructionDevice:AddressDescriptor ->(64)words$word ->(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addrdesc__arg vaddress ipaddress level acctype iswrite secondstage s2fs1walk=
+    (let addrdesc = addrdesc__arg in
+   let (c : Constraint) = (ConstrainUnpredictable Unpredictable_INSTRDEVICE) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((c = Constraint_NONE))) \/ (((c = Constraint_FAULT)))))) "((c == Constraint_NONE) || (c == Constraint_FAULT))")
+   (if (((c = Constraint_FAULT))) then sail2_state_monad$bindS
+     (AArch64_PermissionFault ipaddress level acctype iswrite secondstage s2fs1walk) (\ (w__0 :
+       FaultRecord) . 
+     let (addrdesc : AddressDescriptor) = ((addrdesc with<| AddressDescriptor_fault := w__0|>)) in
+     sail2_state_monad$returnS addrdesc)
+   else
+     let (tmp_120 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in
+     let tmp_120 = ((tmp_120 with<| MemoryAttributes_typ := MemType_Normal|>)) in
+     let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_120|>)) in
+     let (tmp_130 : MemAttrHints) = (addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+     let tmp_130 = ((tmp_130 with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+     let (tmp_140 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in
+     let tmp_140 = ((tmp_140 with<| MemoryAttributes_inner := tmp_130|>)) in
+     let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_140|>)) in
+     let (tmp_150 : MemAttrHints) = (addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+     let tmp_150 = ((tmp_150 with<| MemAttrHints_hints := MemHint_No|>)) in
+     let (tmp_160 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in
+     let tmp_160 = ((tmp_160 with<| MemoryAttributes_inner := tmp_150|>)) in
+     let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_160|>)) in
+     let (tmp_170 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in
+     let tmp_170 =
+       ((tmp_170 with<|
+         MemoryAttributes_outer := (addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner)|>)) in
+     let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_170|>)) in sail2_state_monad$bindS
+     (MemAttrDefaults addrdesc.AddressDescriptor_memattrs) (\ (w__1 : MemoryAttributes) . 
+     let (addrdesc : AddressDescriptor) = ((addrdesc with<| AddressDescriptor_memattrs := w__1|>)) in
+     sail2_state_monad$returnS addrdesc))))`;
+
+
+(*val aget_Vpart : forall 'width . Size 'width => integer -> ii -> ii -> M (mword 'width)*)
+
+val _ = Define `
+ ((aget_Vpart:int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) n part=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))")
+   (sail2_state_monad$assert_expS ((((((part = (( 0 : int):ii)))) \/ (((part = (( 1 : int):ii))))))) "((part == 0) || (part == 1))"))
+   (if (((part = (( 0 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ (((width__tv = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))")
+     (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 bits) list) . 
+     sail2_state_monad$returnS ((slice ((access_list_dec w__0 n  :  128 words$word)) (( 0 : int):ii) width__tv  :  'width words$word)))
+   else sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS (((width__tv = (( 64 : int):ii)))) "(width == 64)")
+     (sail2_state_monad$read_regS V_ref)) (\ (w__1 : ( 128 bits) list) . 
+     sail2_state_monad$returnS ((words$w2w
+                ((slice ((access_list_dec w__1 n  :  128 words$word)) (( 64 : int):ii) (( 64 : int):ii)  :  'width words$word))
+               :  'width words$word))))))`;
+
+
+(*val aget_V : forall 'width . Size 'width => integer -> ii -> M (mword 'width)*)
+
+val _ = Define `
+ ((aget_V:int -> int ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) n=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))")
+   (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ ((((((width__tv = (( 64 : int):ii)))) \/ (((width__tv = (( 128 : int):ii)))))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))"))
+   (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 bits) list) . 
+   sail2_state_monad$returnS ((slice ((access_list_dec w__0 n  :  128 words$word)) (( 0 : int):ii) width__tv  :  'width words$word)))))`;
+
+
+(*val LookUpRIndex : ii -> mword ty5 -> M ii*)
+
+val _ = Define `
+ ((LookUpRIndex:int ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n mode=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 14 : int):ii)))))) "((n >= 0) && (n <= 14))")
+   (undefined_int () )) (\ (result : ii) . 
+   let p0_ = n in
+   if (((p0_ = (( 8 : int):ii)))) then RBankSelect mode (( 8 : int):ii) (( 24 : int):ii) (( 8 : int):ii) (( 8 : int):ii) (( 8 : int):ii) (( 8 : int):ii) (( 8 : int):ii)
+   else if (((p0_ = (( 9 : int):ii)))) then RBankSelect mode (( 9 : int):ii) (( 25 : int):ii) (( 9 : int):ii) (( 9 : int):ii) (( 9 : int):ii) (( 9 : int):ii) (( 9 : int):ii)
+   else if (((p0_ = (( 10 : int):ii)))) then
+     RBankSelect mode (( 10 : int):ii) (( 26 : int):ii) (( 10 : int):ii) (( 10 : int):ii) (( 10 : int):ii) (( 10 : int):ii) (( 10 : int):ii)
+   else if (((p0_ = (( 11 : int):ii)))) then
+     RBankSelect mode (( 11 : int):ii) (( 27 : int):ii) (( 11 : int):ii) (( 11 : int):ii) (( 11 : int):ii) (( 11 : int):ii) (( 11 : int):ii)
+   else if (((p0_ = (( 12 : int):ii)))) then
+     RBankSelect mode (( 12 : int):ii) (( 28 : int):ii) (( 12 : int):ii) (( 12 : int):ii) (( 12 : int):ii) (( 12 : int):ii) (( 12 : int):ii)
+   else if (((p0_ = (( 13 : int):ii)))) then
+     RBankSelect mode (( 13 : int):ii) (( 29 : int):ii) (( 17 : int):ii) (( 19 : int):ii) (( 21 : int):ii) (( 23 : int):ii) (( 15 : int):ii)
+   else if (((p0_ = (( 14 : int):ii)))) then
+     RBankSelect mode (( 14 : int):ii) (( 30 : int):ii) (( 16 : int):ii) (( 18 : int):ii) (( 20 : int):ii) (( 22 : int):ii) (( 14 : int):ii)
+   else sail2_state_monad$returnS n)))`;
+
+
+(*val HighestSetBit : forall 'N . Size 'N => mword 'N -> M ii*)
+
+val _ = Define `
+ ((HighestSetBit:'N words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x=
+    (sail2_state_monad$catch_early_returnS
+     ( sail2_state_monad$seqS(sail2_state$foreachS (index_list ((((int_of_num (words$word_len x))) - (( 1 : int):ii))) (( 0 : int):ii) (~ (( 1 : int):ii))) () 
+        (\ i unit_var . 
+          if ((((vec_of_bits [access_vec_dec x i]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+            (sail2_state_monad$early_returnS i : (unit, ii) MR)
+          else sail2_state_monad$returnS () ))
+      (sail2_state_monad$returnS ((~ (( 1 : int):ii)))))))`;
+
+
+(*val CountLeadingZeroBits : forall 'N . Size 'N => mword 'N -> M ii*)
+
+val _ = Define `
+ ((CountLeadingZeroBits:'N words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x=  (sail2_state_monad$bindS
+   (HighestSetBit x) (\ (w__0 : ii) . 
+   sail2_state_monad$returnS ((((((int_of_num (words$word_len x))) - (( 1 : int):ii))) - ((ex_int w__0)))))))`;
+
+
+(*val CountLeadingSignBits : forall 'N . Size 'N => mword 'N -> M ii*)
+
+val _ = Define `
+ ((CountLeadingSignBits:'N words$word ->(regstate)sail2_state_monad$sequential_state ->(((ii),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x=
+    (CountLeadingZeroBits
+     ((xor_vec ((shiftr x (( 1 : int):ii)  :  'N words$word))
+         ((and_vec x ((slice_mask ((int_of_num (words$word_len x))) (( 0 : int):ii) ((int_of_num (words$word_len x)))  :  'N words$word))  :  'N words$word))
+        :  'N words$word))))`;
+
+
+(*val BitReverse : forall 'N . Size 'N => mword 'N -> M (mword 'N)*)
+
+val _ = Define `
+ ((BitReverse:'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) data=  (sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len data)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   let (result : 'N bits) =
+     (foreach (index_list (( 0 : int):ii) ((((int_of_num (words$word_len data))) - (( 1 : int):ii))) (( 1 : int):ii)) result
+       (\ i result . 
+         (set_slice ((int_of_num (words$word_len data))) (( 1 : int):ii) result
+            ((((((int_of_num (words$word_len data))) - i)) - (( 1 : int):ii)))
+            (vec_of_bits [access_vec_dec data i]  :  1 words$word)
+           :  'N words$word))) in
+   sail2_state_monad$returnS result)))`;
+
+
+(*val NextInstrAddr : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*)
+
+val _ = Define `
+ ((NextInstrAddr:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (ThisInstrLength () ) (\ (w__1 : ii) . 
+   sail2_state_monad$returnS ((slice ((add_vec_int w__0 ((((ex_int w__1)) / (( 8 : int):ii)))  :  64 words$word)) (( 0 : int):ii)
+              N__tv
+             :  'N words$word))))))`;
+
+
+(*val AArch32_ExceptionClass : Exception -> M (ii * mword ty1)*)
+
+val _ = Define `
+ ((AArch32_ExceptionClass:Exception ->(regstate)sail2_state_monad$sequential_state ->(((int#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ=  (sail2_state_monad$bindS
+   (ThisInstrLength () ) (\ (w__0 : ii) . 
+   let (il : 1 bits) =
+     (if (((((ex_int w__0)) = (( 32 : int):ii)))) then (vec_of_bits [B1]  :  1 words$word)
+     else (vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (ec : ii) .  sail2_state_monad$bindS
+   (case typ of
+     Exception_Uncategorized =>
+      let (ec : ii) = ((( 0 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_WFxTrap =>
+      let (ec : ii) = ((( 1 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP15RTTrap =>
+      let (ec : ii) = ((( 3 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP15RRTTrap =>
+      let (ec : ii) = ((( 4 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP14RTTrap =>
+      let (ec : ii) = ((( 5 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP14DTTrap =>
+      let (ec : ii) = ((( 6 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_AdvSIMDFPAccessTrap =>
+      let (ec : ii) = ((( 7 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_FPIDTrap =>
+      let (ec : ii) = ((( 8 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP14RRTTrap =>
+      let (ec : ii) = ((( 12 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_IllegalState =>
+      let (ec : ii) = ((( 14 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SupervisorCall =>
+      let (ec : ii) = ((( 17 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_HypervisorCall =>
+      let (ec : ii) = ((( 18 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_MonitorCall =>
+      let (ec : ii) = ((( 19 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_InstructionAbort =>
+      let (ec : ii) = ((( 32 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_PCAlignment =>
+      let (ec : ii) = ((( 34 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_DataAbort =>
+      let (ec : ii) = ((( 36 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_FPTrappedException =>
+      let (ec : ii) = ((( 40 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | _ => sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS (ec, il))
+   ) (\ varstup .  let ((ec : ii), (il : 1 bits)) = varstup in sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((((((((ex_int ec)) = (( 32 : int):ii)))) \/ (((((ex_int ec)) = (( 36 : int):ii))))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$returnS (((w__1.ProcState_EL = EL2)))))) (\ (w__2 :
+     bool) . 
+   let (ec : ii) = (if w__2 then ((ex_int ec)) + (( 1 : int):ii) else ec) in
+   sail2_state_monad$returnS (ec, il)))))))`;
+
+
+(*val RotCell : mword ty4 -> ii -> M (mword ty4)*)
+
+val _ = Define `
+ ((RotCell:(4)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) incell_name amount=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (tmp : 8 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (outcell : 4 bits) . 
+   let (tmp : 8 bits) =
+     ((set_slice (( 8 : int):ii) (( 8 : int):ii) tmp (( 0 : int):ii)
+        ((concat_vec ((slice incell_name (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+            ((slice incell_name (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+           :  8 words$word))
+       :  8 words$word)) in
+   let (outcell : 4 bits) = ((slice tmp (((( 4 : int):ii) - amount)) (( 4 : int):ii)  :  4 words$word)) in
+   sail2_state_monad$returnS outcell))))`;
+
+
+(*val FPNeg : forall 'N . Size 'N => mword 'N -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPNeg:'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op=
+    (let p0_ = (int_of_num (words$word_len op)) in
+   if (((p0_ = (( 16 : int):ii)))) then
+     let (op :  16 words$word) = ((words$w2w op  :  16 words$word)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (sail2_state_monad$returnS ((words$w2w
+                ((concat_vec
+                    ((not_vec
+                        (vec_of_bits [access_vec_dec op (((( 16 : int):ii) - (( 1 : int):ii)))]
+                          :  1 words$word)
+                       :  1 words$word))
+                    ((slice op (( 0 : int):ii) (((( 16 : int):ii) - (( 1 : int):ii)))  :  15 words$word))
+                   :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then
+     let (op :  32 words$word) = ((words$w2w op  :  32 words$word)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (sail2_state_monad$returnS ((words$w2w
+                ((concat_vec
+                    ((not_vec
+                        (vec_of_bits [access_vec_dec op (((( 32 : int):ii) - (( 1 : int):ii)))]
+                          :  1 words$word)
+                       :  1 words$word))
+                    ((slice op (( 0 : int):ii) (((( 32 : int):ii) - (( 1 : int):ii)))  :  31 words$word))
+                   :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then
+     let (op :  64 words$word) = ((words$w2w op  :  64 words$word)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (sail2_state_monad$returnS ((words$w2w
+                ((concat_vec
+                    ((not_vec
+                        (vec_of_bits [access_vec_dec op (((( 64 : int):ii) - (( 1 : int):ii)))]
+                          :  1 words$word)
+                       :  1 words$word))
+                    ((slice op (( 0 : int):ii) (((( 64 : int):ii) - (( 1 : int):ii)))  :  63 words$word))
+                   :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val FPAbs : forall 'N . Size 'N => mword 'N -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPAbs:'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op=
+    (let p0_ = (int_of_num (words$word_len op)) in
+   if (((p0_ = (( 16 : int):ii)))) then
+     let (op :  16 words$word) = ((words$w2w op  :  16 words$word)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (sail2_state_monad$returnS ((words$w2w
+                ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                    ((slice op (( 0 : int):ii) (((( 16 : int):ii) - (( 1 : int):ii)))  :  15 words$word))
+                   :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then
+     let (op :  32 words$word) = ((words$w2w op  :  32 words$word)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (sail2_state_monad$returnS ((words$w2w
+                ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                    ((slice op (( 0 : int):ii) (((( 32 : int):ii) - (( 1 : int):ii)))  :  31 words$word))
+                   :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then
+     let (op :  64 words$word) = ((words$w2w op  :  64 words$word)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (sail2_state_monad$returnS ((words$w2w
+                ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                    ((slice op (( 0 : int):ii) (((( 64 : int):ii) - (( 1 : int):ii)))  :  63 words$word))
+                   :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val EncodeLDFSC : Fault -> ii -> M (mword ty6)*)
+
+val _ = Define `
+ ((EncodeLDFSC:Fault -> int ->(regstate)sail2_state_monad$sequential_state ->((((6)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ level=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (result : 6 bits) . 
+   (case typ of
+     Fault_AddressSize =>
+      let result =
+        ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+           ((GetSlice_int ((make_the_value (( 2 : int):ii)  :  2 itself)) level (( 0 : int):ii)  :  2 words$word))
+          :  6 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))")
+      (sail2_state_monad$returnS result)
+   | Fault_AccessFlag =>
+      let result =
+        ((concat_vec (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)
+           ((GetSlice_int ((make_the_value (( 2 : int):ii)  :  2 itself)) level (( 0 : int):ii)  :  2 words$word))
+          :  6 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii)))))))))) "((level == 1) || ((level == 2) || (level == 3)))")
+      (sail2_state_monad$returnS result)
+   | Fault_Permission =>
+      let result =
+        ((concat_vec (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)
+           ((GetSlice_int ((make_the_value (( 2 : int):ii)  :  2 itself)) level (( 0 : int):ii)  :  2 words$word))
+          :  6 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii)))))))))) "((level == 1) || ((level == 2) || (level == 3)))")
+      (sail2_state_monad$returnS result)
+   | Fault_Translation =>
+      let result =
+        ((concat_vec (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)
+           ((GetSlice_int ((make_the_value (( 2 : int):ii)  :  2 itself)) level (( 0 : int):ii)  :  2 words$word))
+          :  6 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))")
+      (sail2_state_monad$returnS result)
+   | Fault_SyncExternal =>
+      let (result : 6 bits) = ((vec_of_bits [B0;B1;B0;B0;B0;B0]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_SyncExternalOnWalk =>
+      let result =
+        ((concat_vec (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)
+           ((GetSlice_int ((make_the_value (( 2 : int):ii)  :  2 itself)) level (( 0 : int):ii)  :  2 words$word))
+          :  6 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))")
+      (sail2_state_monad$returnS result)
+   | Fault_SyncParity =>
+      let (result : 6 bits) = ((vec_of_bits [B0;B1;B1;B0;B0;B0]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_SyncParityOnWalk =>
+      let result =
+        ((concat_vec (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)
+           ((GetSlice_int ((make_the_value (( 2 : int):ii)  :  2 itself)) level (( 0 : int):ii)  :  2 words$word))
+          :  6 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))")
+      (sail2_state_monad$returnS result)
+   | Fault_AsyncParity =>
+      let (result : 6 bits) = ((vec_of_bits [B0;B1;B1;B0;B0;B1]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_AsyncExternal =>
+      let (result : 6 bits) = ((vec_of_bits [B0;B1;B0;B0;B0;B1]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_Alignment =>
+      let (result : 6 bits) = ((vec_of_bits [B1;B0;B0;B0;B0;B1]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_Debug =>
+      let (result : 6 bits) = ((vec_of_bits [B1;B0;B0;B0;B1;B0]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_TLBConflict =>
+      let (result : 6 bits) = ((vec_of_bits [B1;B1;B0;B0;B0;B0]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_Lockdown =>
+      let (result : 6 bits) = ((vec_of_bits [B1;B1;B0;B1;B0;B0]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | Fault_Exclusive =>
+      let (result : 6 bits) = ((vec_of_bits [B1;B1;B0;B1;B0;B1]  :  6 words$word)) in
+      sail2_state_monad$returnS result
+   | _ => sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result)
+   ))))`;
+
+
+
+
+(*val AArch32_ReportHypEntry : ExceptionRecord -> M unit*)
+
+val _ = Define `
+ ((AArch32_ReportHypEntry:ExceptionRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception=
+    (let (typ : Exception) = (exception.ExceptionRecord_typ) in sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (il : 1 bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (ec : ii) .  sail2_state_monad$bindS
+   (AArch32_ExceptionClass typ  : ((ii #  1 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let ec = tup__0 in
+   let il = tup__1 in
+   let (iss : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let (il : 1 bits) =
+     (if (((((((((((ex_int ec)) = (( 36 : int):ii)))) \/ (((((ex_int ec)) = (( 37 : int):ii))))))) /\ ((((vec_of_bits [access_vec_dec iss (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+       (vec_of_bits [B1]  :  1 words$word)
+     else il) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HSR_ref
+     ((concat_vec
+         ((concat_vec
+             ((GetSlice_int ((make_the_value (( 6 : int):ii)  :  6 itself)) ec (( 0 : int):ii)  :  6 words$word)) il
+            :  7 words$word)) iss
+        :  32 words$word)))
+   (if ((((((typ = Exception_InstructionAbort))) \/ (((typ = Exception_PCAlignment)))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS HIFAR_ref ((slice exception.ExceptionRecord_vaddress (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__0 : 32 bits) . 
+      sail2_state_monad$write_regS HDFAR_ref w__0)
+    else if (((typ = Exception_DataAbort))) then sail2_state_monad$bindS
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) .  sail2_state_monad$seqS
+      (sail2_state_monad$write_regS HIFAR_ref w__1)
+      (sail2_state_monad$write_regS HDFAR_ref ((slice exception.ExceptionRecord_vaddress (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word))))
+    else sail2_state_monad$returnS () ))
+   (if exception.ExceptionRecord_ipavalid then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS HPFAR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+     sail2_state_monad$write_regS
+       HPFAR_ref
+       ((set_slice (( 32 : int):ii) (( 28 : int):ii) w__2 (( 4 : int):ii)
+           ((slice exception.ExceptionRecord_ipaddress (( 12 : int):ii) (( 28 : int):ii)  :  28 words$word))
+          :  32 words$word)))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS HPFAR_ref  : ( 32 words$word) M) (\ (w__3 :  32 words$word) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 28 : int):ii)  : ( 28 words$word) M) (\ (w__4 :  28 words$word) . 
+     sail2_state_monad$write_regS HPFAR_ref ((set_slice (( 32 : int):ii) (( 28 : int):ii) w__3 (( 4 : int):ii) w__4  :  32 words$word))))))))))`;
+
+
+(*val aset_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> mword 'size -> M (mword 'N)*)
+
+(*val aset_Elem__1 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> mword 'size -> M (mword 'N)*)
+
+val _ = Define `
+ ((aset_Elem__0:'N words$word -> int -> 'size itself -> 'size words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vector_name__arg e size1 value_name=
+    (let size1 = (size_itself_int size1) in
+   let vector_name = vector_name__arg in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((e >= (( 0 : int):ii))) /\ ((((((e + (( 1 : int):ii))) * size1)) <= ((int_of_num (words$word_len vector_name)))))))) "((e >= 0) && (((e + 1) * size) <= N))")
+   (let (vector_name :  'N words$word) =
+     ((set_slice ((int_of_num (words$word_len vector_name))) size1 vector_name ((e * size1)) value_name
+       :  'N words$word)) in
+   sail2_state_monad$returnS vector_name)))`;
+
+
+val _ = Define `
+ ((aset_Elem__1:'N words$word -> int -> 'size words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vector_name__arg e value_name=
+    (let vector_name = vector_name__arg in
+   (aset_Elem__0 vector_name e ((make_the_value ((int_of_num (words$word_len value_name)))  :  'size itself)) value_name
+     : ( 'N words$word) M)))`;
+
+
+(*val aget_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> M (mword 'size)*)
+
+(*val aget_Elem__1 : forall 'N 'size . Size 'N, Size 'size => integer -> mword 'N -> ii -> M (mword 'size)*)
+
+val _ = Define `
+ ((aget_Elem__0:'N words$word -> int -> 'size itself ->(regstate)sail2_state_monad$sequential_state ->((('size words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vector_name e size1=
+    (let size1 = (size_itself_int size1) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((e >= (( 0 : int):ii))) /\ ((((((e + (( 1 : int):ii))) * size1)) <= ((int_of_num (words$word_len vector_name)))))))) "((e >= 0) && (((e + 1) * size) <= N))")
+   (sail2_state_monad$returnS ((slice vector_name ((e * size1)) size1  :  'size words$word)))))`;
+
+
+val _ = Define `
+ ((aget_Elem__1:int -> 'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('size words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (size__tv : int) vector_name e=
+    ((aget_Elem__0 vector_name e ((make_the_value size__tv  :  'size itself))  : ( 'size words$word) M)))`;
+
+
+(*val UnsignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*)
+
+val _ = Define `
+ ((UnsignedSatQ:int -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) i N=
+    (let N = (size_itself_int N) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (saturated : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (result : ii) . 
+   let ((result : ii), (saturated : bool)) =
+     (if ((i > ((((pow2 N)) - (( 1 : int):ii))))) then
+       let (result : ii) = (((pow2 N)) - (( 1 : int):ii)) in
+       let (saturated : bool) = T in
+       (result, saturated)
+     else
+       let ((result : ii), (saturated : bool)) =
+         (if ((i < (( 0 : int):ii))) then
+           let (result : ii) = ((( 0 : int):ii)) in
+           let (saturated : bool) = T in
+           (result, saturated)
+         else
+           let (result : ii) = i in
+           let (saturated : bool) = F in
+           (result, saturated)) in
+       (result, saturated)) in
+   sail2_state_monad$returnS ((GetSlice_int ((make_the_value N  :  'N itself)) result (( 0 : int):ii)  :  'N words$word), saturated)))))`;
+
+
+(*val SignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*)
+
+val _ = Define `
+ ((SignedSatQ:int -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) i N=
+    (let N = (size_itself_int N) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (saturated : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (result : ii) . 
+   let ((result : ii), (saturated : bool)) =
+     (if ((i > ((((pow2 ((N - (( 1 : int):ii))))) - (( 1 : int):ii))))) then
+       let (result : ii) = (((pow2 ((N - (( 1 : int):ii))))) - (( 1 : int):ii)) in
+       let (saturated : bool) = T in
+       (result, saturated)
+     else
+       let ((result : ii), (saturated : bool)) =
+         (if ((i < ((~ ((pow2 ((N - (( 1 : int):ii))))))))) then
+           let (result : ii) = (~ ((pow2 ((N - (( 1 : int):ii)))))) in
+           let (saturated : bool) = T in
+           (result, saturated)
+         else
+           let (result : ii) = i in
+           let (saturated : bool) = F in
+           (result, saturated)) in
+       (result, saturated)) in
+   sail2_state_monad$returnS ((GetSlice_int ((make_the_value N  :  'N itself)) result (( 0 : int):ii)  :  'N words$word), saturated)))))`;
+
+
+(*val SatQ : forall 'N . Size 'N => ii -> itself 'N -> bool -> M (mword 'N * bool)*)
+
+val _ = Define `
+ ((SatQ:int -> 'N itself -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) i N unsigned=
+    (let N = (size_itself_int N) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (sat : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector N  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (if unsigned then (UnsignedSatQ i ((make_the_value N  :  'N itself))  : (( 'N words$word # bool)) M)
+    else (SignedSatQ i ((make_the_value N  :  'N itself))  : (( 'N words$word # bool)) M)) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let (result : 'N bits) = tup__0 in
+   let (sat : bool) = tup__1 in
+   sail2_state_monad$returnS (result, sat))))))`;
+
+
+(*val Replicate : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*)
+
+val _ = Define `
+ ((Replicate:int -> 'M words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((N__tv % ((int_of_num (words$word_len x))))) = (( 0 : int):ii)))) "((N MOD M) == 0)")
+   (let O1 = (N__tv / ((int_of_num (words$word_len x)))) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "") (sail2_state_monad$returnS ((replicate_bits x ((N__tv / ((int_of_num (words$word_len x)))))  :  'N words$word))))))`;
+
+
+(*val Zeros__0 : forall 'N . Size 'N => itself 'N -> mword 'N*)
+
+(*val Zeros__1 : forall 'N . Size 'N => integer -> unit -> mword 'N*)
+
+val _ = Define `
+ ((Zeros__0:'N itself -> 'N words$word) N=
+    (let N = (size_itself_int N) in
+   (replicate_bits (vec_of_bits [B0]  :  1 words$word) N  :  'N words$word)))`;
+
+
+val _ = Define `
+ ((Zeros__1:int -> unit -> 'N words$word) (N__tv : int) () =  ((Zeros__0 ((make_the_value N__tv  :  'N itself))  :  'N words$word)))`;
+
+
+(*val __ResetMemoryState : unit -> M unit*)
+
+val _ = Define `
+ ((ResetMemoryState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS Memory_ref  : ( 52 words$word) M) (\ (w__0 :  52 words$word) . 
+   let (_ : unit) =
+     (InitRAM (( 52 : int):ii) (( 1 : int):ii) w__0 ((Zeros__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word))) in
+   sail2_state_monad$write_regS ExclusiveLocal_ref F)))`;
+
+
+(*val ZeroExtend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> M (mword 'N)*)
+
+(*val ZeroExtend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*)
+
+val _ = Define `
+ ((ZeroExtend__0:'M words$word -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x N=
+    (let N = (size_itself_int N) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((N >= ((int_of_num (words$word_len x))))) "") (sail2_state_monad$returnS ((extzv N x  :  'N words$word)))))`;
+
+
+val _ = Define `
+ ((ZeroExtend__1:int -> 'M words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x=
+    ((ZeroExtend__0 x ((make_the_value N__tv  :  'N itself))  : ( 'N words$word) M)))`;
+
+
+(*val aset_Vpart : forall 'width . Size 'width => ii -> ii -> mword 'width -> M unit*)
+
+val _ = Define `
+ ((aset_Vpart:int -> int -> 'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n part value_name=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))")
+   (sail2_state_monad$assert_expS ((((((part = (( 0 : int):ii)))) \/ (((part = (( 1 : int):ii))))))) "((part == 0) || (part == 1))"))
+   (if (((part = (( 0 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 8 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))")
+     (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 words$word) list) .  sail2_state_monad$bindS
+     (ZeroExtend__1 (( 128 : int):ii) value_name  : ( 128 words$word) M) (\ (w__1 : 128 bits) . 
+     sail2_state_monad$write_regS V_ref ((update_list_dec w__0 n w__1  : ( 128 words$word) list))))
+   else sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii)))) "(width == 64)")
+     (sail2_state_monad$read_regS V_ref)) (\ (w__2 : ( 128 bits) list) . 
+     let (tmp_2870 : 128 bits) = ((access_list_dec w__2 n  :  128 words$word)) in
+     let tmp_2870 =
+       ((update_subrange_vec_dec tmp_2870 (( 127 : int):ii) (( 64 : int):ii)
+          ((subrange_vec_dec value_name (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+         :  128 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS V_ref) (\ (w__3 : ( 128 words$word) list) . 
+     sail2_state_monad$write_regS V_ref ((update_list_dec w__3 n tmp_2870  : ( 128 words$word) list)))))))`;
+
+
+(*val aset_V : forall 'width . Size 'width => ii -> mword 'width -> M unit*)
+
+val _ = Define `
+ ((aset_V:int -> 'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n value_name=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))")
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 8 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 64 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 128 : int):ii)))))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))"))
+   (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 words$word) list) .  sail2_state_monad$bindS
+   (ZeroExtend__1 (( 128 : int):ii) value_name  : ( 128 words$word) M) (\ (w__1 : 128 bits) . 
+   sail2_state_monad$write_regS V_ref ((update_list_dec w__0 n w__1  : ( 128 words$word) list))))))`;
+
+
+(*val AArch64_ResetSIMDFPRegisters : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_ResetSIMDFPRegisters:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
+     (\ i unit_var .  sail2_state_monad$bindS
+       (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  aset_V i w__0))))`;
+
+
+(*val aset_SP : forall 'width . Size 'width => mword 'width -> M unit*)
+
+val _ = Define `
+ ((aset_SP:'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii))))))) "((width == 32) || (width == 64))")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . 
+   if (((w__0.ProcState_SP = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+     (ZeroExtend__1 (( 64 : int):ii) value_name  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+     sail2_state_monad$write_regS SP_EL0_ref w__1)
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+     let p__299 = (w__2.ProcState_EL) in
+     let pat_0 = p__299 in
+     if (((pat_0 = EL0))) then sail2_state_monad$bindS
+       (ZeroExtend__1 (( 64 : int):ii) value_name  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+       sail2_state_monad$write_regS SP_EL0_ref w__3)
+     else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+       (ZeroExtend__1 (( 64 : int):ii) value_name  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+       sail2_state_monad$write_regS SP_EL1_ref w__4)
+     else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+       (ZeroExtend__1 (( 64 : int):ii) value_name  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+       sail2_state_monad$write_regS SP_EL2_ref w__5)
+     else sail2_state_monad$bindS
+       (ZeroExtend__1 (( 64 : int):ii) value_name  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+       sail2_state_monad$write_regS SP_EL3_ref w__6)))))`;
+
+
+(*val LSR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*)
+
+val _ = Define `
+ ((LSR_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift > (( 0 : int):ii))) "(shift > 0)")
+   (let (result : 'N bits) = ((shiftr x shift  :  'N words$word)) in
+   let (carry_out : 1 bits) =
+     (if ((shift > ((int_of_num (words$word_len result))))) then (vec_of_bits [B0]  :  1 words$word)
+     else (vec_of_bits [access_vec_dec x ((shift - (( 1 : int):ii)))]  :  1 words$word)) in
+   sail2_state_monad$returnS (result, carry_out))))`;
+
+
+(*val LSR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*)
+
+val _ = Define `
+ ((LSR:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)")
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M)) (\ (anon10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len x)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x
+   else sail2_state_monad$bindS
+     (LSR_C x shift  : (( 'N words$word #  1 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+     let (result : 'N bits) = tup__0 in
+     let (anon10 : 1 bits) = tup__1 in
+     sail2_state_monad$returnS result)))))`;
+
+
+(*val Poly32Mod2 : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((Poly32Mod2:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) data__arg poly=
+    (let data = data__arg in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((int_of_num (words$word_len data))) > (( 32 : int):ii))) "(N > 32)")
+   (let (poly' : 'N bits) = ((extzv ((int_of_num (words$word_len data))) poly  :  'N words$word)) in
+   let (data :  'N words$word) =
+     (foreach (index_list ((((int_of_num (words$word_len data))) - (( 1 : int):ii))) (( 32 : int):ii) (~ (( 1 : int):ii))) data
+       (\ i data . 
+         if ((((vec_of_bits [access_vec_dec data i]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+           (or_vec data ((sub_vec_int ((shiftl poly' i  :  'N words$word)) (( 32 : int):ii)  :  'N words$word))
+             :  'N words$word)
+         else data)) in
+   sail2_state_monad$returnS ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))))`;
+
+
+(*val LSL_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*)
+
+val _ = Define `
+ ((LSL_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift > (( 0 : int):ii))) "(shift > 0)")
+   (let (result : 'N bits) = ((shiftl x shift  :  'N words$word)) in
+   let (carry_out : 1 bits) =
+     (if ((shift > ((int_of_num (words$word_len result))))) then (vec_of_bits [B0]  :  1 words$word)
+     else (vec_of_bits [access_vec_dec x ((((int_of_num (words$word_len result))) - shift))]  :  1 words$word)) in
+   sail2_state_monad$returnS (result, carry_out))))`;
+
+
+(*val LSL : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*)
+
+val _ = Define `
+ ((LSL:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)")
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M)) (\ (anon10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len x)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x
+   else sail2_state_monad$bindS
+     (LSL_C x shift  : (( 'N words$word #  1 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+     let (result : 'N bits) = tup__0 in
+     let (anon10 : 1 bits) = tup__1 in
+     sail2_state_monad$returnS result)))))`;
+
+
+(*val AArch32_ITAdvance : unit -> M unit*)
+
+val _ = Define `
+ ((AArch32_ITAdvance:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   if (((((slice w__0.ProcState_IT (( 0 : int):ii) (( 3 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     sail2_state_monad$write_regS
+       PSTATE_ref
+       (w__1 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))|>))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+     let (tmp_2760 : 8 bits) = (w__2.ProcState_IT) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$bindS
+     (LSL ((slice w__3.ProcState_IT (( 0 : int):ii) (( 5 : int):ii)  :  5 words$word)) (( 1 : int):ii)  : ( 5 words$word) M) (\ (w__4 :
+        5 words$word) . 
+     let tmp_2760 = ((set_slice (( 8 : int):ii) (( 5 : int):ii) tmp_2760 (( 0 : int):ii) w__4  :  8 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_IT := tmp_2760|>))))))))`;
+
+
+(*val LSInstructionSyndrome : unit -> M (mword ty11)*)
+
+val _ = Define `
+ ((LSInstructionSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->((((11)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE")
+   (sail2_state_monad$returnS ((Zeros__0 ((make_the_value (( 11 : int):ii)  :  11 itself))  :  11 words$word)))))`;
+
+
+(*val IsZero : forall 'N . Size 'N => mword 'N -> bool*)
+
+val _ = Define `
+ ((IsZero:'N words$word -> bool) x=  (x = ((Zeros__0 ((make_the_value ((int_of_num (words$word_len x)))  :  'N itself))  :  'N words$word))))`;
+
+
+(*val IsZeroBit : forall 'N . Size 'N => mword 'N -> mword ty1*)
+
+val _ = Define `
+ ((IsZeroBit:'N words$word ->(1)words$word) x=
+    (if ((IsZero x)) then (vec_of_bits [B1]  :  1 words$word)
+   else (vec_of_bits [B0]  :  1 words$word)))`;
+
+
+(*val AddWithCarry : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty1 -> (mword 'N * mword ty4)*)
+
+val _ = Define `
+ ((AddWithCarry:'N words$word -> 'N words$word ->(1)words$word -> 'N words$word#(4)words$word) x y carry_in=
+    (let (unsigned_sum : ii) = (((((lem$w2ui x)) + ((lem$w2ui y)))) + ((lem$w2ui carry_in))) in
+   let (signed_sum : ii) = (((((integer_word$w2i x)) + ((integer_word$w2i y)))) + ((lem$w2ui carry_in))) in
+   let (result : 'N bits) =
+     ((GetSlice_int ((make_the_value ((int_of_num (words$word_len x)))  :  'N itself)) unsigned_sum (( 0 : int):ii)  :  'N words$word)) in
+   let (n : 1 bits) =
+     ((vec_of_bits [access_vec_dec result ((((int_of_num (words$word_len result))) - (( 1 : int):ii)))]  :  1 words$word)) in
+   let (z : 1 bits) =
+     (if ((IsZero result)) then (vec_of_bits [B1]  :  1 words$word)
+     else (vec_of_bits [B0]  :  1 words$word)) in
+   let (c : 1 bits) =
+     (if (((((lem$w2ui result)) = ((ex_int unsigned_sum))))) then (vec_of_bits [B0]  :  1 words$word)
+     else (vec_of_bits [B1]  :  1 words$word)) in
+   let (v : 1 bits) =
+     (if (((((integer_word$w2i result)) = ((ex_int signed_sum))))) then (vec_of_bits [B0]  :  1 words$word)
+     else (vec_of_bits [B1]  :  1 words$word)) in
+   (result,
+    (concat_vec ((concat_vec ((concat_vec n z  :  2 words$word)) c  :  3 words$word)) v  :  4 words$word))))`;
+
+
+(*val GetPSRFromPSTATE : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((GetPSRFromPSTATE:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (let (spsr : 32 bits) = ((Zeros__1 (( 32 : int):ii) ()   :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   let spsr = ((update_subrange_vec_dec spsr (( 31 : int):ii) (( 31 : int):ii) w__0.ProcState_N  :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+   let spsr = ((update_subrange_vec_dec spsr (( 30 : int):ii) (( 30 : int):ii) w__1.ProcState_Z  :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let spsr = ((update_subrange_vec_dec spsr (( 29 : int):ii) (( 29 : int):ii) w__2.ProcState_C  :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+   let spsr = ((update_subrange_vec_dec spsr (( 28 : int):ii) (( 28 : int):ii) w__3.ProcState_V  :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+   let spsr = ((update_subrange_vec_dec spsr (( 21 : int):ii) (( 21 : int):ii) w__4.ProcState_SS  :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+   let spsr = ((update_subrange_vec_dec spsr (( 20 : int):ii) (( 20 : int):ii) w__5.ProcState_IL  :  32 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+   if (((w__6.ProcState_nRW = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 27 : int):ii) (( 27 : int):ii) w__7.ProcState_Q  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . 
+     let spsr =
+       ((update_subrange_vec_dec spsr (( 26 : int):ii) (( 25 : int):ii)
+          ((subrange_vec_dec w__8.ProcState_IT (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+         :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 19 : int):ii) (( 16 : int):ii) w__9.ProcState_GE  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+     let spsr =
+       ((update_subrange_vec_dec spsr (( 15 : int):ii) (( 10 : int):ii)
+          ((subrange_vec_dec w__10.ProcState_IT (( 7 : int):ii) (( 2 : int):ii)  :  6 words$word))
+         :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 9 : int):ii) (( 9 : int):ii) w__11.ProcState_E  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 8 : int):ii) (( 8 : int):ii) w__12.ProcState_A  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 7 : int):ii) (( 7 : int):ii) w__13.ProcState_I  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 6 : int):ii) (( 6 : int):ii) w__14.ProcState_F  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 5 : int):ii) (( 5 : int):ii) w__15.ProcState_T  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS ((((vec_of_bits [access_vec_dec w__16.ProcState_M (( 4 : int):ii)]  :  1 words$word) = w__17.ProcState_nRW))) "(((PSTATE).M)<4> == (PSTATE).nRW)")
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . 
+     let (spsr : 32 bits) =
+       ((update_subrange_vec_dec spsr (( 4 : int):ii) (( 0 : int):ii) w__18.ProcState_M  :  32 words$word)) in
+     sail2_state_monad$returnS spsr))))))))))))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 9 : int):ii) (( 9 : int):ii) w__19.ProcState_D  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 8 : int):ii) (( 8 : int):ii) w__20.ProcState_A  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 7 : int):ii) (( 7 : int):ii) w__21.ProcState_I  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 6 : int):ii) (( 6 : int):ii) w__22.ProcState_F  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__23 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 4 : int):ii) (( 4 : int):ii) w__23.ProcState_nRW  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__24 : ProcState) . 
+     let spsr = ((update_subrange_vec_dec spsr (( 3 : int):ii) (( 2 : int):ii) w__24.ProcState_EL  :  32 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__25 : ProcState) . 
+     let (spsr : 32 bits) =
+       ((update_subrange_vec_dec spsr (( 0 : int):ii) (( 0 : int):ii) w__25.ProcState_SP  :  32 words$word)) in
+     sail2_state_monad$returnS spsr))))))))))))))))`;
+
+
+(*val FPZero : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPZero:int ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) sign=
+    (let p0_ = N__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 5 bits) = ((Zeros__0 ((make_the_value (( 5 : int):ii)  :  5 itself))  :  5 words$word)) in
+     let (frac : 10 bits) = ((Zeros__0 ((make_the_value F1  :  10 itself))  :  10 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  6 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 8 bits) = ((Zeros__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word)) in
+     let (frac : 23 bits) = ((Zeros__0 ((make_the_value F1  :  23 itself))  :  23 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  9 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 11 bits) = ((Zeros__0 ((make_the_value (( 11 : int):ii)  :  11 itself))  :  11 words$word)) in
+     let (frac : 52 bits) = ((Zeros__0 ((make_the_value F1  :  52 itself))  :  52 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  12 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val ExceptionSyndrome : Exception -> M ExceptionRecord*)
+
+val _ = Define `
+ ((ExceptionSyndrome:Exception ->(regstate)sail2_state_monad$sequential_state ->(((ExceptionRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ=  (sail2_state_monad$bindS
+   (undefined_ExceptionRecord () ) (\ (r : ExceptionRecord) . 
+   let (r : ExceptionRecord) = ((r with<| ExceptionRecord_typ := typ|>)) in
+   let (r : ExceptionRecord) =
+     ((r with<| ExceptionRecord_syndrome := ((Zeros__1 (( 25 : int):ii) ()   :  25 words$word))|>)) in
+   let (r : ExceptionRecord) =
+     ((r with<| ExceptionRecord_vaddress := ((Zeros__1 (( 64 : int):ii) ()   :  64 words$word))|>)) in
+   let (r : ExceptionRecord) = ((r with<| ExceptionRecord_ipavalid := F|>)) in
+   let (r : ExceptionRecord) =
+     ((r with<| ExceptionRecord_ipaddress := ((Zeros__1 (( 52 : int):ii) ()   :  52 words$word))|>)) in
+   sail2_state_monad$returnS r)))`;
+
+
+(*val ConstrainUnpredictableBits : forall 'width . Size 'width => integer -> Unpredictable -> M (Constraint * mword 'width)*)
+
+val _ = Define `
+ ((ConstrainUnpredictableBits:int -> Unpredictable ->(regstate)sail2_state_monad$sequential_state ->(((Constraint#'width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) which=
+    (let (c : Constraint) = (ConstrainUnpredictable which) in
+   if (((c = Constraint_UNKNOWN))) then
+     sail2_state_monad$returnS (c, (Zeros__0 ((make_the_value width__tv  :  'width itself))  :  'width words$word))
+   else sail2_state_monad$bindS
+     (undefined_bitvector width__tv  : ( 'width words$word) M) (\ (w__0 :  'width words$word) . 
+     sail2_state_monad$returnS (c, w__0))))`;
+
+
+(*val AArch64_SysInstrWithResult : ii -> ii -> ii -> ii -> ii -> M (mword ty64)*)
+
+val _ = Define `
+ ((AArch64_SysInstrWithResult:int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE")
+   (sail2_state_monad$returnS ((Zeros__0 ((make_the_value (( 64 : int):ii)  :  64 itself))  :  64 words$word)))))`;
+
+
+(*val AArch64_PhysicalSErrorSyndrome : bool -> M (mword ty25)*)
+
+val _ = Define `
+ ((AArch64_PhysicalSErrorSyndrome:bool ->(regstate)sail2_state_monad$sequential_state ->((((25)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) implicit_esb=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE")
+   (sail2_state_monad$returnS ((Zeros__0 ((make_the_value (( 25 : int):ii)  :  25 itself))  :  25 words$word)))))`;
+
+
+(*val AArch32_PhysicalSErrorSyndrome : unit -> M AArch32_SErrorSyndrome*)
+
+val _ = Define `
+ ((AArch32_PhysicalSErrorSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->(((AArch32_SErrorSyndrome),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS F "FALSE")
+   (undefined_AArch32_SErrorSyndrome () )) (\ (r : AArch32_SErrorSyndrome) . 
+   let (r : AArch32_SErrorSyndrome) =
+     ((r with<|
+       AArch32_SErrorSyndrome_AET :=
+         ((Zeros__0 ((make_the_value (( 2 : int):ii)  :  2 itself))  :  2 words$word))|>)) in
+   let (r : AArch32_SErrorSyndrome) =
+     ((r with<|
+       AArch32_SErrorSyndrome_ExT :=
+         ((Zeros__0 ((make_the_value (( 1 : int):ii)  :  1 itself))  :  1 words$word))|>)) in
+   sail2_state_monad$returnS r)))`;
+
+
+(*val VFPExpandImm : forall 'N . Size 'N => integer -> mword ty8 -> M (mword 'N)*)
+
+val _ = Define `
+ ((VFPExpandImm:int ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) imm8=
+    (let p0_ = N__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in
+     let (sign : 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 : int):ii)]  :  1 words$word)) in
+     let (exp : 5 bits) =
+       ((concat_vec
+          ((concat_vec
+              ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)]  :  1 words$word)  :  1 words$word))
+              ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)]  :  1 words$word)
+                  (((( 5 : int):ii) - (( 3 : int):ii)))
+                 :  2 words$word))
+             :  3 words$word)) ((subrange_vec_dec imm8 (( 5 : int):ii) (( 4 : int):ii)  :  2 words$word))
+         :  5 words$word)) in
+     let (frac : 10 bits) =
+       ((concat_vec ((subrange_vec_dec imm8 (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+          ((Zeros__0 ((make_the_value ((F1 - (( 4 : int):ii)))  :  6 itself))  :  6 words$word))
+         :  10 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  6 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in
+     let (sign : 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 : int):ii)]  :  1 words$word)) in
+     let (exp : 8 bits) =
+       ((concat_vec
+          ((concat_vec
+              ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)]  :  1 words$word)  :  1 words$word))
+              ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)]  :  1 words$word)
+                  (((( 8 : int):ii) - (( 3 : int):ii)))
+                 :  5 words$word))
+             :  6 words$word)) ((subrange_vec_dec imm8 (( 5 : int):ii) (( 4 : int):ii)  :  2 words$word))
+         :  8 words$word)) in
+     let (frac : 23 bits) =
+       ((concat_vec ((subrange_vec_dec imm8 (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+          ((Zeros__0 ((make_the_value ((F1 - (( 4 : int):ii)))  :  19 itself))  :  19 words$word))
+         :  23 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  9 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in
+     let (sign : 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 : int):ii)]  :  1 words$word)) in
+     let (exp : 11 bits) =
+       ((concat_vec
+          ((concat_vec
+              ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)]  :  1 words$word)  :  1 words$word))
+              ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)]  :  1 words$word)
+                  (((( 11 : int):ii) - (( 3 : int):ii)))
+                 :  8 words$word))
+             :  9 words$word)) ((subrange_vec_dec imm8 (( 5 : int):ii) (( 4 : int):ii)  :  2 words$word))
+         :  11 words$word)) in
+     let (frac : 52 bits) =
+       ((concat_vec ((subrange_vec_dec imm8 (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+          ((Zeros__0 ((make_the_value ((F1 - (( 4 : int):ii)))  :  48 itself))  :  48 words$word))
+         :  52 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  12 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val SignExtend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> M (mword 'N)*)
+
+(*val SignExtend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*)
+
+val _ = Define `
+ ((SignExtend__0:'M words$word -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x N=
+    (let N = (size_itself_int N) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((N >= ((int_of_num (words$word_len x))))) "") (sail2_state_monad$returnS ((extsv N x  :  'N words$word)))))`;
+
+
+val _ = Define `
+ ((SignExtend__1:int -> 'M words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x=
+    ((SignExtend__0 x ((make_the_value N__tv  :  'N itself))  : ( 'N words$word) M)))`;
+
+
+(*val Extend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> bool -> M (mword 'N)*)
+
+(*val Extend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> bool -> M (mword 'N)*)
+
+val _ = Define `
+ ((Extend__0:'M words$word -> 'N itself -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x N unsigned=
+    (let N = (size_itself_int N) in
+   if unsigned then (ZeroExtend__0 x ((make_the_value N  :  'N itself))  : ( 'N words$word) M)
+   else (SignExtend__0 x ((make_the_value N  :  'N itself))  : ( 'N words$word) M)))`;
+
+
+val _ = Define `
+ ((Extend__1:int -> 'M words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x unsigned=
+    ((Extend__0 x ((make_the_value N__tv  :  'N itself)) unsigned  : ( 'N words$word) M)))`;
+
+
+(*val ASR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*)
+
+val _ = Define `
+ ((ASR_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift > (( 0 : int):ii))) "(shift > 0)")
+   (let (result : 'N bits) = ((arith_shiftr x shift  :  'N words$word)) in
+   let (carry_out : 1 bits) =
+     (if ((shift > ((int_of_num (words$word_len result))))) then
+       (vec_of_bits [access_vec_dec x ((((int_of_num (words$word_len result))) - (( 1 : int):ii)))]  :  1 words$word)
+     else (vec_of_bits [access_vec_dec x ((shift - (( 1 : int):ii)))]  :  1 words$word)) in
+   sail2_state_monad$returnS (result, carry_out))))`;
+
+
+(*val ASR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*)
+
+val _ = Define `
+ ((ASR:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)")
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M)) (\ (anon10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len x)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x
+   else sail2_state_monad$bindS
+     (ASR_C x shift  : (( 'N words$word #  1 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+     let (result : 'N bits) = tup__0 in
+     let (anon10 : 1 bits) = tup__1 in
+     sail2_state_monad$returnS result)))))`;
+
+
+(*val Ones__0 : forall 'N . Size 'N => itself 'N -> mword 'N*)
+
+(*val Ones__1 : forall 'N . Size 'N => integer -> unit -> mword 'N*)
+
+val _ = Define `
+ ((Ones__0:'N itself -> 'N words$word) N=
+    (let N = (size_itself_int N) in
+   (replicate_bits (vec_of_bits [B1]  :  1 words$word) N  :  'N words$word)))`;
+
+
+val _ = Define `
+ ((Ones__1:int -> unit -> 'N words$word) (N__tv : int) () =  ((Ones__0 ((make_the_value N__tv  :  'N itself))  :  'N words$word)))`;
+
+
+(*val IsOnes : forall 'N . Size 'N => mword 'N -> bool*)
+
+val _ = Define `
+ ((IsOnes:'N words$word -> bool) x=  (x = ((Ones__0 ((make_the_value ((int_of_num (words$word_len x)))  :  'N itself))  :  'N words$word))))`;
+
+
+(*val FPMaxNormal : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMaxNormal:int ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) sign=
+    (let p0_ = N__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 5 bits) =
+       ((concat_vec
+          ((Ones__0 ((make_the_value (((( 5 : int):ii) - (( 1 : int):ii)))  :  4 itself))  :  4 words$word))
+          (vec_of_bits [B0]  :  1 words$word)
+         :  5 words$word)) in
+     let (frac : 10 bits) = ((Ones__0 ((make_the_value F1  :  10 itself))  :  10 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  6 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 8 bits) =
+       ((concat_vec
+          ((Ones__0 ((make_the_value (((( 8 : int):ii) - (( 1 : int):ii)))  :  7 itself))  :  7 words$word))
+          (vec_of_bits [B0]  :  1 words$word)
+         :  8 words$word)) in
+     let (frac : 23 bits) = ((Ones__0 ((make_the_value F1  :  23 itself))  :  23 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  9 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 11 bits) =
+       ((concat_vec
+          ((Ones__0 ((make_the_value (((( 11 : int):ii) - (( 1 : int):ii)))  :  10 itself))  :  10 words$word))
+          (vec_of_bits [B0]  :  1 words$word)
+         :  11 words$word)) in
+     let (frac : 52 bits) = ((Ones__0 ((make_the_value F1  :  52 itself))  :  52 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  12 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val FPInfinity : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPInfinity:int ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) sign=
+    (let p0_ = N__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 5 bits) = ((Ones__0 ((make_the_value (( 5 : int):ii)  :  5 itself))  :  5 words$word)) in
+     let (frac : 10 bits) = ((Zeros__0 ((make_the_value F1  :  10 itself))  :  10 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  6 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 8 bits) = ((Ones__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word)) in
+     let (frac : 23 bits) = ((Zeros__0 ((make_the_value F1  :  23 itself))  :  23 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  9 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in
+     let (exp : 11 bits) = ((Ones__0 ((make_the_value (( 11 : int):ii)  :  11 itself))  :  11 words$word)) in
+     let (frac : 52 bits) = ((Zeros__0 ((make_the_value F1  :  52 itself))  :  52 words$word)) in
+     sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp  :  12 words$word)) frac  :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val FPDefaultNaN : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPDefaultNaN:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) () =
+    (let p0_ = N__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in
+     let (sign : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+     let (exp : 5 bits) = ((Ones__0 ((make_the_value (( 5 : int):ii)  :  5 itself))  :  5 words$word)) in
+     let (frac : 10 bits) =
+       ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+          ((Zeros__0 ((make_the_value ((F1 - (( 1 : int):ii)))  :  9 itself))  :  9 words$word))
+         :  10 words$word)) in
+     sail2_state_monad$returnS ((words$w2w
+                ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) exp  :  6 words$word)) frac
+                   :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in
+     let (sign : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+     let (exp : 8 bits) = ((Ones__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word)) in
+     let (frac : 23 bits) =
+       ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+          ((Zeros__0 ((make_the_value ((F1 - (( 1 : int):ii)))  :  22 itself))  :  22 words$word))
+         :  23 words$word)) in
+     sail2_state_monad$returnS ((words$w2w
+                ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) exp  :  9 words$word)) frac
+                   :  'N words$word))
+               :  'N words$word)))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))")
+     (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in
+     let (sign : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+     let (exp : 11 bits) = ((Ones__0 ((make_the_value (( 11 : int):ii)  :  11 itself))  :  11 words$word)) in
+     let (frac : 52 bits) =
+       ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+          ((Zeros__0 ((make_the_value ((F1 - (( 1 : int):ii)))  :  51 itself))  :  51 words$word))
+         :  52 words$word)) in
+     sail2_state_monad$returnS ((words$w2w
+                ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) exp  :  12 words$word)) frac
+                   :  'N words$word))
+               :  'N words$word)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`;
+
+
+(*val FPConvertNaN : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> M (mword 'M)*)
+
+val _ = Define `
+ ((FPConvertNaN:int -> 'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (sail2_state_monad$assert_expS ((((((M__tv = (( 16 : int):ii)))) \/ ((((((M__tv = (( 32 : int):ii)))) \/ (((M__tv = (( 64 : int):ii)))))))))) "((M == 16) || ((M == 32) || (M == 64)))"))
+   (undefined_bitvector M__tv  : ( 'M words$word) M)) (\ (result : 'M bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 51 : int):ii)  : ( 51 words$word) M) (\ (frac : 51 bits) . 
+   let (sign : 1 bits) =
+     ((vec_of_bits [access_vec_dec op ((((int_of_num (words$word_len op))) - (( 1 : int):ii)))]  :  1 words$word)) in
+   let p0_ = (int_of_num (words$word_len op)) in
+   let (frac : 51 bits) =
+     (if (((p0_ = (( 64 : int):ii)))) then
+       let (op :  64 words$word) = ((words$w2w op  :  64 words$word)) in
+       (slice op (( 0 : int):ii) (( 51 : int):ii)  :  51 words$word)
+     else if (((p0_ = (( 32 : int):ii)))) then
+       let (op :  32 words$word) = ((words$w2w op  :  32 words$word)) in
+       (concat_vec ((slice op (( 0 : int):ii) (( 22 : int):ii)  :  22 words$word))
+          ((Zeros__0 ((make_the_value (( 29 : int):ii)  :  29 itself))  :  29 words$word))
+         :  51 words$word)
+     else
+       let (op :  16 words$word) = ((words$w2w op  :  16 words$word)) in
+       (concat_vec ((slice op (( 0 : int):ii) (( 9 : int):ii)  :  9 words$word))
+          ((Zeros__0 ((make_the_value (( 42 : int):ii)  :  42 itself))  :  42 words$word))
+         :  51 words$word)) in
+   let p0_ = (int_of_num (words$word_len result)) in
+   let (result : 'M bits) =
+     (if (((p0_ = (( 64 : int):ii)))) then
+       (concat_vec
+          ((concat_vec sign
+              ((Ones__0 ((make_the_value (((( 64 : int):ii) - (( 52 : int):ii))) ))  :  12 words$word))
+             :  13 words$word)) frac
+         :  'M words$word)
+     else if (((p0_ = (( 32 : int):ii)))) then
+       (concat_vec
+          ((concat_vec sign
+              ((Ones__0 ((make_the_value (((( 32 : int):ii) - (( 23 : int):ii))) ))  :  9 words$word))
+             :  10 words$word)) ((slice frac (( 29 : int):ii) (( 22 : int):ii)  :  22 words$word))
+         :  'M words$word)
+     else
+       (concat_vec
+          ((concat_vec sign
+              ((Ones__0 ((make_the_value ((p0_ - (( 10 : int):ii))) ))  :  6 words$word))
+             :  7 words$word)) ((slice frac (( 42 : int):ii) (( 9 : int):ii)  :  9 words$word))
+         :  'M words$word)) in
+   sail2_state_monad$returnS result))))`;
+
+
+(*val ExcVectorBase : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((ExcVectorBase:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+   if ((((vec_of_bits [access_vec_dec w__0 (( 13 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+     sail2_state_monad$returnS ((concat_vec ((Ones__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+                ((Zeros__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+               :  32 words$word))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS VBAR_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+     sail2_state_monad$returnS ((concat_vec ((slice w__1 (( 5 : int):ii) (( 27 : int):ii)  :  27 words$word))
+                ((Zeros__0 ((make_the_value (( 5 : int):ii)  :  5 itself))  :  5 words$word))
+               :  32 words$word))))))`;
+
+
+(*val PACSub : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((PACSub:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Tinput=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (Toutput : 64 bits) . 
+   let (Toutput : 64 bits) =
+     (foreach (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) Toutput
+       (\ i Toutput . 
+         let b__0 = ((slice Tinput (((( 4 : int):ii) * i)) (( 4 : int):ii)  :  4 words$word)) in
+         if (((b__0 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)
+             :  64 words$word))) in
+   sail2_state_monad$returnS Toutput)))`;
+
+
+(*val PACMult : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((PACMult:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Sinput=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (t0 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (t1 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (t2 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (t3 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (Soutput : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) (( 3 : int):ii) (( 1 : int):ii)) (Soutput, t0, t1, t2, t3)
+     (\ i varstup .  let (Soutput, t0, t1, t2, t3) = varstup in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__0 :  4 words$word) .  sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 2 : int):ii)
+         : ( 4 words$word) M) (\ (w__1 :  4 words$word) . 
+       let t0 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t0 (( 0 : int):ii) ((xor_vec w__0 w__1  :  4 words$word))  :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * i)) (( 4 : int):ii)  :  4 words$word)) (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__2 :  4 words$word) . 
+       let t0 =
+         ((set_slice (( 4 : int):ii) (( 4 : int):ii) t0 (( 0 : int):ii)
+            ((xor_vec ((slice t0 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word)) w__2  :  4 words$word))
+           :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__3 :  4 words$word) .  sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__4 :  4 words$word) . 
+       let t1 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t1 (( 0 : int):ii) ((xor_vec w__3 w__4  :  4 words$word))  :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * i)) (( 4 : int):ii)  :  4 words$word)) (( 2 : int):ii)
+         : ( 4 words$word) M) (\ (w__5 :  4 words$word) . 
+       let t1 =
+         ((set_slice (( 4 : int):ii) (( 4 : int):ii) t1 (( 0 : int):ii)
+            ((xor_vec ((slice t1 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word)) w__5  :  4 words$word))
+           :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 2 : int):ii)
+         : ( 4 words$word) M) (\ (w__6 :  4 words$word) .  sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__7 :  4 words$word) . 
+       let t2 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t2 (( 0 : int):ii) ((xor_vec w__6 w__7  :  4 words$word))  :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * i)) (( 4 : int):ii)  :  4 words$word)) (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__8 :  4 words$word) . 
+       let t2 =
+         ((set_slice (( 4 : int):ii) (( 4 : int):ii) t2 (( 0 : int):ii)
+            ((xor_vec ((slice t2 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word)) w__8  :  4 words$word))
+           :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__9 :  4 words$word) .  sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 2 : int):ii)
+         : ( 4 words$word) M) (\ (w__10 :  4 words$word) . 
+       let t3 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t3 (( 0 : int):ii) ((xor_vec w__9 w__10  :  4 words$word))  :  4 words$word)) in sail2_state_monad$bindS
+       (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) (( 4 : int):ii)  :  4 words$word))
+          (( 1 : int):ii)
+         : ( 4 words$word) M) (\ (w__11 :  4 words$word) . 
+       let (t3 : 4 bits) =
+         ((set_slice (( 4 : int):ii) (( 4 : int):ii) t3 (( 0 : int):ii)
+            ((xor_vec ((slice t3 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word)) w__11  :  4 words$word))
+           :  4 words$word)) in
+       let (Soutput : 64 bits) =
+         ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * i))
+            ((slice t3 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+           :  64 words$word)) in
+       let (Soutput : 64 bits) =
+         ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * ((i + (( 4 : int):ii)))))
+            ((slice t2 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+           :  64 words$word)) in
+       let (Soutput : 64 bits) =
+         ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * ((i + (( 8 : int):ii)))))
+            ((slice t1 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+           :  64 words$word)) in
+       let (Soutput : 64 bits) =
+         ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * ((i + (( 12 : int):ii)))))
+            ((slice t0 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word))
+           :  64 words$word)) in
+       sail2_state_monad$returnS (Soutput, t0, t1, t2, t3))))))))))))))) (\ varstup .  let ((Soutput : 64 bits), (t0 : 4
+     bits), (t1 : 4 bits), (t2 : 4 bits), (t3 : 4 bits)) = varstup in
+   sail2_state_monad$returnS Soutput))))))))`;
+
+
+(*val PACInvSub : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((PACInvSub:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Tinput=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (Toutput : 64 bits) . 
+   let (Toutput : 64 bits) =
+     (foreach (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) Toutput
+       (\ i Toutput . 
+         let b__0 = ((slice Tinput (((( 4 : int):ii) * i)) (( 4 : int):ii)  :  4 words$word)) in
+         if (((b__0 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)
+             :  64 words$word)
+         else if (((b__0 = (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)))) then
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)
+             :  64 words$word)
+         else
+           (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i))
+              (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)
+             :  64 words$word))) in
+   sail2_state_monad$returnS Toutput)))`;
+
+
+(*val ComputePAC : mword ty64 -> mword ty64 -> mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((ComputePAC:(64)words$word ->(64)words$word ->(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) data modifier key0 key1=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (workingval : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (runningmod : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (roundkey : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (modk0 : 64 bits) .  sail2_state_monad$bindS
+   (hex_slice "0xC0AC29B7C97C50DD" (( 64 : int):ii) (( 0 : int):ii)  : ( 64 words$word) M) (\ (Alpha : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS RC_ref) (\ (w__0 : ( 64 words$word) list) .  sail2_state_monad$bindS
+   (hex_slice "0x0" (( 64 : int):ii) (( 0 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RC_ref ((update_list_dec w__0 (( 0 : int):ii) w__1  : ( 64 words$word) list)))
+   (sail2_state_monad$read_regS RC_ref)) (\ (w__2 : ( 64 words$word) list) .  sail2_state_monad$bindS
+   (hex_slice "0x13198A2E03707344" (( 64 : int):ii) (( 0 : int):ii)  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RC_ref ((update_list_dec w__2 (( 1 : int):ii) w__3  : ( 64 words$word) list)))
+   (sail2_state_monad$read_regS RC_ref)) (\ (w__4 : ( 64 words$word) list) .  sail2_state_monad$bindS
+   (hex_slice "0xA493822299F31D0" (( 64 : int):ii) (( 0 : int):ii)  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RC_ref ((update_list_dec w__4 (( 2 : int):ii) w__5  : ( 64 words$word) list)))
+   (sail2_state_monad$read_regS RC_ref)) (\ (w__6 : ( 64 words$word) list) .  sail2_state_monad$bindS
+   (hex_slice "0x82EFA98EC4E6C89" (( 64 : int):ii) (( 0 : int):ii)  : ( 64 words$word) M) (\ (w__7 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RC_ref ((update_list_dec w__6 (( 3 : int):ii) w__7  : ( 64 words$word) list)))
+   (sail2_state_monad$read_regS RC_ref)) (\ (w__8 : ( 64 words$word) list) .  sail2_state_monad$bindS
+   (hex_slice "0x452821E638D01377" (( 64 : int):ii) (( 0 : int):ii)  : ( 64 words$word) M) (\ (w__9 :  64 words$word) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RC_ref ((update_list_dec w__8 (( 4 : int):ii) w__9  : ( 64 words$word) list)))
+   (let modk0 =
+     ((concat_vec
+        ((concat_vec (vec_of_bits [access_vec_dec key0 (( 0 : int):ii)]  :  1 words$word)
+            ((slice key0 (( 2 : int):ii) (( 62 : int):ii)  :  62 words$word))
+           :  63 words$word))
+        ((xor_vec (vec_of_bits [access_vec_dec key0 (( 63 : int):ii)]  :  1 words$word)
+            (vec_of_bits [access_vec_dec key0 (( 1 : int):ii)]  :  1 words$word)
+           :  1 words$word))
+       :  64 words$word)) in
+   let runningmod = modifier in
+   let workingval = ((xor_vec data key0  :  64 words$word)) in sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) (( 4 : int):ii) (( 1 : int):ii)) (roundkey, runningmod, workingval)
+     (\ i varstup .  let (roundkey, runningmod, workingval) = varstup in
+       let roundkey = ((xor_vec key1 runningmod  :  64 words$word)) in
+       let workingval = ((xor_vec workingval roundkey  :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS RC_ref) (\ (w__10 : ( 64 bits) list) . 
+       let workingval = ((xor_vec workingval ((access_list_dec w__10 i  :  64 words$word))  :  64 words$word)) in sail2_state_monad$bindS
+       (if ((i > (( 0 : int):ii))) then sail2_state_monad$bindS
+          (PACCellShuffle workingval  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+          let workingval = w__11 in
+          (PACMult workingval  : ( 64 words$word) M))
+        else sail2_state_monad$returnS workingval) (\ (workingval : 64 bits) .  sail2_state_monad$bindS
+       (PACSub workingval  : ( 64 words$word) M) (\ (w__13 : 64 bits) . 
+       let workingval = w__13 in sail2_state_monad$bindS
+       (TweakShuffle ((slice runningmod (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))  : ( 64 words$word) M) (\ (w__14 : 64
+         bits) . 
+       let (runningmod : 64 bits) = w__14 in
+       sail2_state_monad$returnS (roundkey, runningmod, workingval))))))) (\ varstup .  let ((roundkey : 64 bits), (runningmod : 64
+     bits), (workingval : 64 bits)) = varstup in
+   let roundkey = ((xor_vec modk0 runningmod  :  64 words$word)) in
+   let workingval = ((xor_vec workingval roundkey  :  64 words$word)) in sail2_state_monad$bindS
+   (PACCellShuffle workingval  : ( 64 words$word) M) (\ (w__15 : 64 bits) . 
+   let workingval = w__15 in sail2_state_monad$bindS
+   (PACMult workingval  : ( 64 words$word) M) (\ (w__16 : 64 bits) . 
+   let workingval = w__16 in sail2_state_monad$bindS
+   (PACSub workingval  : ( 64 words$word) M) (\ (w__17 : 64 bits) . 
+   let workingval = w__17 in sail2_state_monad$bindS
+   (PACCellShuffle workingval  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+   let workingval = w__18 in sail2_state_monad$bindS
+   (PACMult workingval  : ( 64 words$word) M) (\ (w__19 : 64 bits) . 
+   let workingval = w__19 in
+   let workingval = ((xor_vec key1 workingval  :  64 words$word)) in sail2_state_monad$bindS
+   (PACCellInvShuffle workingval  : ( 64 words$word) M) (\ (w__20 : 64 bits) . 
+   let workingval = w__20 in sail2_state_monad$bindS
+   (PACInvSub workingval  : ( 64 words$word) M) (\ (w__21 : 64 bits) . 
+   let workingval = w__21 in sail2_state_monad$bindS
+   (PACMult workingval  : ( 64 words$word) M) (\ (w__22 : 64 bits) . 
+   let workingval = w__22 in sail2_state_monad$bindS
+   (PACCellInvShuffle workingval  : ( 64 words$word) M) (\ (w__23 : 64 bits) . 
+   let workingval = w__23 in
+   let workingval = ((xor_vec workingval key0  :  64 words$word)) in
+   let workingval = ((xor_vec workingval runningmod  :  64 words$word)) in sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) (( 4 : int):ii) (( 1 : int):ii)) (roundkey, runningmod, workingval)
+     (\ i varstup .  let (roundkey, runningmod, workingval) = varstup in sail2_state_monad$bindS
+       (PACInvSub workingval  : ( 64 words$word) M) (\ (w__24 : 64 bits) . 
+       let workingval = w__24 in sail2_state_monad$bindS
+       (if ((i < (( 4 : int):ii))) then sail2_state_monad$bindS
+          (PACMult workingval  : ( 64 words$word) M) (\ (w__25 : 64 bits) . 
+          let workingval = w__25 in
+          (PACCellInvShuffle workingval  : ( 64 words$word) M))
+        else sail2_state_monad$returnS workingval) (\ (workingval : 64 bits) .  sail2_state_monad$bindS
+       (TweakInvShuffle ((slice runningmod (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))  : ( 64 words$word) M) (\ (w__27 : 64
+         bits) . 
+       let runningmod = w__27 in
+       let roundkey = ((xor_vec key1 runningmod  :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS RC_ref) (\ (w__28 : ( 64 bits) list) . 
+       let (workingval : 64 bits) =
+         ((xor_vec workingval ((access_list_dec w__28 (((( 4 : int):ii) - i))  :  64 words$word))
+           :  64 words$word)) in
+       let (workingval : 64 bits) = ((xor_vec workingval roundkey  :  64 words$word)) in
+       let (workingval : 64 bits) = ((xor_vec workingval Alpha  :  64 words$word)) in
+       sail2_state_monad$returnS (roundkey, runningmod, workingval))))))) (\ varstup .  let ((roundkey : 64 bits), (runningmod : 64
+     bits), (workingval : 64 bits)) = varstup in
+   let (workingval : 64 bits) = ((xor_vec workingval modk0  :  64 words$word)) in
+   sail2_state_monad$returnS workingval)))))))))))))))))))))))))))))`;
+
+
+(*val Align__0 : ii -> ii -> ii*)
+
+(*val Align__1 : forall 'N . Size 'N => mword 'N -> ii -> mword 'N*)
+
+val _ = Define `
+ ((Align__0:int -> int -> int) x y=  (y * ((x / y))))`;
+
+
+val _ = Define `
+ ((Align__1:'N words$word -> int -> 'N words$word) x y=
+    ((GetSlice_int ((make_the_value ((int_of_num (words$word_len x)))  :  'N itself)) ((Align__0 ((lem$w2ui x)) y)) (( 0 : int):ii)
+     :  'N words$word)))`;
+
+
+(*val aset__Mem : forall   'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> mword 'p8_times_size_ -> M unit*)
+
+val _ = Define `
+ ((aset__Mem:AddressDescriptor -> int -> AccessDescriptor -> 'p8_times_size_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) desc size1 accdesc value_name=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))")
+   (let (address : 52 bits) = (desc.AddressDescriptor_paddress.FullAddress_physicaladdress) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((address = ((Align__1 address size1  :  52 words$word))))) "(address == Align(address, size))")
+   (hex_slice "0x13000000" (( 52 : int):ii) (( 0 : int):ii)  : ( 52 words$word) M)) (\ (w__0 :  52 words$word) . 
+   if (((address = w__0))) then
+     if (((((lem$w2ui value_name)) = (( 4 : int):ii)))) then
+       let (_ : unit) = (prerr "Program exited by writing ^^D to TUBE\n") in
+       sail2_state_monad$exitS () 
+     else sail2_state_monad$returnS ((putchar ((lem$w2ui ((slice value_name (( 0 : int):ii) (( 8 : int):ii)  :  8 words$word))))))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS Memory_ref  : ( 52 words$word) M) (\ (w__1 :  52 words$word) . 
+     WriteRAM ((make_the_value (( 52 : int):ii)  :  52 itself)) size1 w__1 address value_name)))))`;
+
+
+(*val aget__Mem : forall   'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> M (mword 'p8_times_size_)*)
+
+val _ = Define `
+ ((aget__Mem:AddressDescriptor -> int -> AccessDescriptor ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_size_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) desc size1 accdesc=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))")
+   (let (address : 52 bits) = (desc.AddressDescriptor_paddress.FullAddress_physicaladdress) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((address = ((Align__1 address size1  :  52 words$word))))) "(address == Align(address, size))")
+   (sail2_state_monad$read_regS Memory_ref  : ( 52 words$word) M)) (\ (w__0 :  52 words$word) . 
+   (ReadRAM ((make_the_value (( 52 : int):ii)  :  52 itself)) size1 w__0 address
+     : ( 'p8_times_size_ words$word) M)))))`;
+
+
+(*val aset_X : forall 'width . Size 'width => ii -> mword 'width -> M unit*)
+
+val _ = Define `
+ ((aset_X:int -> 'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n value_name=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))")
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii))))))) "((width == 32) || (width == 64))"))
+   (if (((n <> (( 31 : int):ii)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS R_ref) (\ (w__0 : ( 64 words$word) list) .  sail2_state_monad$bindS
+     (ZeroExtend__0 value_name ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) . 
+     sail2_state_monad$write_regS R_ref ((update_list_dec w__0 n w__1  : ( 64 words$word) list))))
+   else sail2_state_monad$returnS () )))`;
+
+
+(*val aarch64_integer_arithmetic_address_pcrel : ii -> mword ty64 -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_address_pcrel:int ->(64)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d imm page=  (sail2_state_monad$bindS
+   (aget_PC ()   : ( 64 words$word) M) (\ (base : 64 bits) . 
+   let (base : 64 bits) =
+     (if page then
+       (set_slice (( 64 : int):ii) (( 12 : int):ii) base (( 0 : int):ii)
+          ((Zeros__0 ((make_the_value (( 12 : int):ii)  :  12 itself))  :  12 words$word))
+         :  64 words$word)
+     else base) in
+   aset_X d ((add_vec base imm  :  64 words$word)))))`;
+
+
+(*val integer_arithmetic_address_pcrel_decode : mword ty1 -> mword ty2 -> mword ty19 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_address_pcrel_decode:(1)words$word ->(2)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op immlo immhi Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (page : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (imm : 64 bits) .  sail2_state_monad$bindS
+   (if page then
+      (SignExtend__0
+         ((concat_vec ((concat_vec immhi immlo  :  21 words$word))
+             ((Zeros__0 ((make_the_value (( 12 : int):ii)  :  12 itself))  :  12 words$word))
+            :  33 words$word)) ((make_the_value (( 64 : int):ii)  :  64 itself))
+        : ( 64 words$word) M)
+    else
+      (SignExtend__0 ((concat_vec immhi immlo  :  21 words$word))
+         ((make_the_value (( 64 : int):ii)  :  64 itself))
+        : ( 64 words$word) M)) (\ (imm : 64 bits) . 
+   aarch64_integer_arithmetic_address_pcrel d imm page)))))`;
+
+
+(*val AArch64_ResetGeneralRegisters : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_ResetGeneralRegisters:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$foreachS (index_list (( 0 : int):ii) (( 30 : int):ii) (( 1 : int):ii)) () 
+     (\ i unit_var .  sail2_state_monad$bindS
+       (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  aset_X i w__0))))`;
+
+
+(*val aset_ELR__0 : mword ty2 -> mword ty64 -> M unit*)
+
+(*val aset_ELR__1 : mword ty64 -> M unit*)
+
+val _ = Define `
+ ((aset_ELR__0:(2)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el value_name=
+    (let (r : 64 bits) = value_name in
+   let pat_0 = el in
+   if (((pat_0 = EL1))) then sail2_state_monad$write_regS ELR_EL1_ref r
+   else if (((pat_0 = EL2))) then sail2_state_monad$write_regS ELR_EL2_ref r
+   else if (((pat_0 = EL3))) then sail2_state_monad$write_regS ELR_EL3_ref r
+   else Unreachable () ))`;
+
+
+val _ = Define `
+ ((aset_ELR__1:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL0))) "")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  aset_ELR__0 w__1.ProcState_EL value_name))))`;
+
+
+(*val aget_X : forall 'width . Size 'width => integer -> ii -> M (mword 'width)*)
+
+val _ = Define `
+ ((aget_X:int -> int ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) n=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))")
+   (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ (((width__tv = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))"))
+   (if (((n <> (( 31 : int):ii)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS R_ref) (\ (w__0 : ( 64 bits) list) . 
+     sail2_state_monad$returnS ((slice ((access_list_dec w__0 n  :  64 words$word)) (( 0 : int):ii) width__tv  :  'width words$word)))
+   else sail2_state_monad$returnS ((Zeros__0 ((make_the_value width__tv  :  'width itself))  :  'width words$word)))))`;
+
+
+(*val aarch64_system_sysops : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_sysops:bool -> int -> int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t=
+    (if has_result then sail2_state_monad$bindS
+     (AArch64_SysInstrWithResult sys_op0 sys_op1 sys_crn sys_crm sys_op2  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) . 
+     aset_X t w__0)
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) t  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+     AArch64_SysInstr sys_op0 sys_op1 sys_crn sys_crm sys_op2 w__1)))`;
+
+
+(*val aarch64_system_register_system : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_register_system:bool -> int -> int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t=
+    (if read then sail2_state_monad$bindS
+     (AArch64_SysRegRead sys_op0 sys_op1 sys_crn sys_crm sys_op2  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) . 
+     aset_X t w__0)
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) t  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+     AArch64_SysRegWrite sys_op0 sys_op1 sys_crn sys_crm sys_op2 w__1)))`;
+
+
+(*val aarch64_integer_insext_insert_movewide : ii -> ii -> mword ty16 -> MoveWideOp -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_insext_insert_movewide:int -> int ->(16)words$word -> MoveWideOp -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__267 imm opcode pos=
+    (if (((l__267 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (if (((opcode = MoveWideOp_K))) then (aget_X (( 8 : int):ii) d  : ( 8 words$word) M)
+      else
+        let (result : 8 bits) = ((Zeros__1 (( 8 : int):ii) ()   :  8 words$word)) in
+        sail2_state_monad$returnS result) (\ (result : 8 bits) . 
+     let result = ((set_slice (( 8 : int):ii) (( 16 : int):ii) result pos imm  :  8 words$word)) in
+     let (result : 8 bits) =
+       (if (((opcode = MoveWideOp_N))) then (not_vec result  :  8 words$word)
+       else result) in
+     aset_X d result))
+   else if (((l__267 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (if (((opcode = MoveWideOp_K))) then (aget_X (( 16 : int):ii) d  : ( 16 words$word) M)
+      else
+        let (result : 16 bits) = ((Zeros__1 (( 16 : int):ii) ()   :  16 words$word)) in
+        sail2_state_monad$returnS result) (\ (result : 16 bits) . 
+     let result = ((set_slice (( 16 : int):ii) (( 16 : int):ii) result pos imm  :  16 words$word)) in
+     let (result : 16 bits) =
+       (if (((opcode = MoveWideOp_N))) then (not_vec result  :  16 words$word)
+       else result) in
+     aset_X d result))
+   else if (((l__267 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (if (((opcode = MoveWideOp_K))) then (aget_X (( 32 : int):ii) d  : ( 32 words$word) M)
+      else
+        let (result : 32 bits) = ((Zeros__1 (( 32 : int):ii) ()   :  32 words$word)) in
+        sail2_state_monad$returnS result) (\ (result : 32 bits) . 
+     let result = ((set_slice (( 32 : int):ii) (( 16 : int):ii) result pos imm  :  32 words$word)) in
+     let (result : 32 bits) =
+       (if (((opcode = MoveWideOp_N))) then (not_vec result  :  32 words$word)
+       else result) in
+     aset_X d result))
+   else if (((l__267 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (if (((opcode = MoveWideOp_K))) then (aget_X (( 64 : int):ii) d  : ( 64 words$word) M)
+      else
+        let (result : 64 bits) = ((Zeros__1 (( 64 : int):ii) ()   :  64 words$word)) in
+        sail2_state_monad$returnS result) (\ (result : 64 bits) . 
+     let result = ((set_slice (( 64 : int):ii) (( 16 : int):ii) result pos imm  :  64 words$word)) in
+     let (result : 64 bits) =
+       (if (((opcode = MoveWideOp_N))) then (not_vec result  :  64 words$word)
+       else result) in
+     aset_X d result))
+   else if (((l__267 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (if (((opcode = MoveWideOp_K))) then (aget_X (( 128 : int):ii) d  : ( 128 words$word) M)
+      else
+        let (result : 128 bits) = ((Zeros__1 (( 128 : int):ii) ()   :  128 words$word)) in
+        sail2_state_monad$returnS result) (\ (result : 128 bits) . 
+     let result = ((set_slice (( 128 : int):ii) (( 16 : int):ii) result pos imm  :  128 words$word)) in
+     let (result : 128 bits) =
+       (if (((opcode = MoveWideOp_N))) then (not_vec result  :  128 words$word)
+       else result) in
+     aset_X d result))
+   else
+     let dbytes = (ex_int ((l__267 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_integer_insext_extract_immediate : ii -> ii -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_insext_extract_immediate:int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__262 lsb m n=
+    (if (((l__262 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) . 
+     let (concat1 : 16 bits) = ((concat_vec operand1 operand2  :  16 words$word)) in
+     let result = ((slice concat1 lsb (( 8 : int):ii)  :  8 words$word)) in
+     aset_X d result)))
+   else if (((l__262 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) . 
+     let (concat1 : 32 bits) = ((concat_vec operand1 operand2  :  32 words$word)) in
+     let result = ((slice concat1 lsb (( 16 : int):ii)  :  16 words$word)) in
+     aset_X d result)))
+   else if (((l__262 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) . 
+     let (concat1 : 64 bits) = ((concat_vec operand1 operand2  :  64 words$word)) in
+     let result = ((slice concat1 lsb (( 32 : int):ii)  :  32 words$word)) in
+     aset_X d result)))
+   else if (((l__262 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) . 
+     let (concat1 : 128 bits) = ((concat_vec operand1 operand2  :  128 words$word)) in
+     let result = ((slice concat1 lsb (( 64 : int):ii)  :  64 words$word)) in
+     aset_X d result)))
+   else if (((l__262 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) . 
+     let (concat1 : 256 bits) = ((concat_vec operand1 operand2  :  256 words$word)) in
+     let result = ((slice concat1 lsb (( 128 : int):ii)  :  128 words$word)) in
+     aset_X d result)))
+   else
+     let dbytes = (ex_int ((l__262 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_integer_arithmetic_rev : ii -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_rev:int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) container_size d l__257 n=
+    (if (((l__257 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (result : 8 bits) . 
+     let (containers : ii) = ((( 8 : int):ii) / container_size) in
+     let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in
+     let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rev_index : ii) . 
+     let ((index : ii), (result : 8 bits), (rev_index : ii)) =
+       (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                          result,
+                                                                                          rev_index)
+         (\ c varstup .  let (index, result, rev_index) = varstup in
+           let (rev_index : ii) =
+             (((ex_int index)) +
+               ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in
+           let ((index : ii), (result : 8 bits), (rev_index : ii)) =
+             (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\ e varstup .  let (index, result, rev_index) = varstup in
+                 let (result : 8 bits) =
+                   ((set_slice (( 8 : int):ii) (( 8 : int):ii) result rev_index
+                      ((slice operand index (( 8 : int):ii)  :  8 words$word))
+                     :  8 words$word)) in
+                 let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in
+                 let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in
+                 (index, result, rev_index))) in
+           (index, result, rev_index))) in
+     aset_X d result)))
+   else if (((l__257 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (result : 16 bits) . 
+     let (containers : ii) = ((( 16 : int):ii) / container_size) in
+     let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in
+     let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rev_index : ii) . 
+     let ((index : ii), (result : 16 bits), (rev_index : ii)) =
+       (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                          result,
+                                                                                          rev_index)
+         (\ c varstup .  let (index, result, rev_index) = varstup in
+           let (rev_index : ii) =
+             (((ex_int index)) +
+               ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in
+           let ((index : ii), (result : 16 bits), (rev_index : ii)) =
+             (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\ e varstup .  let (index, result, rev_index) = varstup in
+                 let (result : 16 bits) =
+                   ((set_slice (( 16 : int):ii) (( 8 : int):ii) result rev_index
+                      ((slice operand index (( 8 : int):ii)  :  8 words$word))
+                     :  16 words$word)) in
+                 let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in
+                 let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in
+                 (index, result, rev_index))) in
+           (index, result, rev_index))) in
+     aset_X d result)))
+   else if (((l__257 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (result : 32 bits) . 
+     let (containers : ii) = ((( 32 : int):ii) / container_size) in
+     let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in
+     let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rev_index : ii) . 
+     let ((index : ii), (result : 32 bits), (rev_index : ii)) =
+       (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                          result,
+                                                                                          rev_index)
+         (\ c varstup .  let (index, result, rev_index) = varstup in
+           let (rev_index : ii) =
+             (((ex_int index)) +
+               ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in
+           let ((index : ii), (result : 32 bits), (rev_index : ii)) =
+             (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\ e varstup .  let (index, result, rev_index) = varstup in
+                 let (result : 32 bits) =
+                   ((set_slice (( 32 : int):ii) (( 8 : int):ii) result rev_index
+                      ((slice operand index (( 8 : int):ii)  :  8 words$word))
+                     :  32 words$word)) in
+                 let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in
+                 let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in
+                 (index, result, rev_index))) in
+           (index, result, rev_index))) in
+     aset_X d result)))
+   else if (((l__257 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) . 
+     let (containers : ii) = ((( 64 : int):ii) / container_size) in
+     let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in
+     let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rev_index : ii) . 
+     let ((index : ii), (result : 64 bits), (rev_index : ii)) =
+       (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                          result,
+                                                                                          rev_index)
+         (\ c varstup .  let (index, result, rev_index) = varstup in
+           let (rev_index : ii) =
+             (((ex_int index)) +
+               ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in
+           let ((index : ii), (result : 64 bits), (rev_index : ii)) =
+             (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\ e varstup .  let (index, result, rev_index) = varstup in
+                 let (result : 64 bits) =
+                   ((set_slice (( 64 : int):ii) (( 8 : int):ii) result rev_index
+                      ((slice operand index (( 8 : int):ii)  :  8 words$word))
+                     :  64 words$word)) in
+                 let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in
+                 let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in
+                 (index, result, rev_index))) in
+           (index, result, rev_index))) in
+     aset_X d result)))
+   else if (((l__257 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (result : 128 bits) . 
+     let (containers : ii) = ((( 128 : int):ii) / container_size) in
+     let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in
+     let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rev_index : ii) . 
+     let ((index : ii), (result : 128 bits), (rev_index : ii)) =
+       (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                          result,
+                                                                                          rev_index)
+         (\ c varstup .  let (index, result, rev_index) = varstup in
+           let (rev_index : ii) =
+             (((ex_int index)) +
+               ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in
+           let ((index : ii), (result : 128 bits), (rev_index : ii)) =
+             (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\ e varstup .  let (index, result, rev_index) = varstup in
+                 let (result : 128 bits) =
+                   ((set_slice (( 128 : int):ii) (( 8 : int):ii) result rev_index
+                      ((slice operand index (( 8 : int):ii)  :  8 words$word))
+                     :  128 words$word)) in
+                 let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in
+                 let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in
+                 (index, result, rev_index))) in
+           (index, result, rev_index))) in
+     aset_X d result)))
+   else
+     let dbytes = (ex_int ((l__257 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_integer_arithmetic_rbit : ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_rbit:int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__252 n=
+    (if (((l__252 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (result : 8 bits) . 
+     let (result : 8 bits) =
+       (foreach (index_list (( 0 : int):ii) (((( 8 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result
+         (\ i result . 
+           (set_slice (( 8 : int):ii) (( 1 : int):ii) result (((((( 8 : int):ii) - (( 1 : int):ii))) - i))
+              (vec_of_bits [access_vec_dec operand i]  :  1 words$word)
+             :  8 words$word))) in
+     aset_X d result))
+   else if (((l__252 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (result : 16 bits) . 
+     let (result : 16 bits) =
+       (foreach (index_list (( 0 : int):ii) (((( 16 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result
+         (\ i result . 
+           (set_slice (( 16 : int):ii) (( 1 : int):ii) result (((((( 16 : int):ii) - (( 1 : int):ii))) - i))
+              (vec_of_bits [access_vec_dec operand i]  :  1 words$word)
+             :  16 words$word))) in
+     aset_X d result))
+   else if (((l__252 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (result : 32 bits) . 
+     let (result : 32 bits) =
+       (foreach (index_list (( 0 : int):ii) (((( 32 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result
+         (\ i result . 
+           (set_slice (( 32 : int):ii) (( 1 : int):ii) result (((((( 32 : int):ii) - (( 1 : int):ii))) - i))
+              (vec_of_bits [access_vec_dec operand i]  :  1 words$word)
+             :  32 words$word))) in
+     aset_X d result))
+   else if (((l__252 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) . 
+     let (result : 64 bits) =
+       (foreach (index_list (( 0 : int):ii) (((( 64 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result
+         (\ i result . 
+           (set_slice (( 64 : int):ii) (( 1 : int):ii) result (((((( 64 : int):ii) - (( 1 : int):ii))) - i))
+              (vec_of_bits [access_vec_dec operand i]  :  1 words$word)
+             :  64 words$word))) in
+     aset_X d result))
+   else if (((l__252 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (result : 128 bits) . 
+     let (result : 128 bits) =
+       (foreach (index_list (( 0 : int):ii) (((( 128 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result
+         (\ i result . 
+           (set_slice (( 128 : int):ii) (( 1 : int):ii) result (((((( 128 : int):ii) - (( 1 : int):ii))) - i))
+              (vec_of_bits [access_vec_dec operand i]  :  1 words$word)
+             :  128 words$word))) in
+     aset_X d result))
+   else
+     let dbytes = (ex_int ((l__252 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_arithmetic_rbit_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_rbit_decode:(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   aarch64_integer_arithmetic_rbit d datasize n)))`;
+
+
+(*val aarch64_integer_arithmetic_mul_widening_64128hi : ii -> ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_mul_widening_64128hi:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__247 m n unsigned=
+    (if (((l__247 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) . 
+     let (result : ii) =
+       (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 64 : int):ii)  :  64 words$word))))
+   else if (((l__247 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) . 
+     let (result : ii) =
+       (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 64 : int):ii)  :  64 words$word))))
+   else if (((l__247 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) . 
+     let (result : ii) =
+       (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 64 : int):ii)  :  64 words$word))))
+   else if (((l__247 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) . 
+     let (result : ii) =
+       (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 64 : int):ii)  :  64 words$word))))
+   else if (((l__247 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) . 
+     let (result : ii) =
+       (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 64 : int):ii)  :  64 words$word))))
+   else
+     let dbytes = (ex_int ((l__247 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_arithmetic_mul_widening_64128hi_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_mul_widening_64128hi_decode:(1)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op54 U Rm o0 Ra Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (a : ii) = (lem$w2ui Ra) in
+   let (destsize : int) = ((( 64 : int):ii)) in
+   let (datasize : ii) = destsize in
+   let (unsigned : bool) = (U = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_integer_arithmetic_mul_widening_64128hi d datasize m n unsigned)))`;
+
+
+(*val aarch64_integer_arithmetic_mul_widening_3264 : ii -> ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_mul_widening_3264:int -> int -> int -> int -> int -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) a d l__220 l__221 m n sub_op unsigned=
+    (if ((((((l__220 = (( 8 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if ((((((l__220 = (( 8 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__220 = (( 8 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__220 = (( 16 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if ((((((l__220 = (( 16 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__220 = (( 16 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__220 = (( 32 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if ((((((l__220 = (( 32 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__220 = (( 32 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__220 = (( 64 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if ((((((l__220 = (( 64 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__220 = (( 64 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__220 = (( 128 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if ((((((l__220 = (( 128 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((ex_int ((asl_Int operand3 unsigned)))) -
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))
+       else
+         ((ex_int ((asl_Int operand3 unsigned)))) +
+           ((((ex_int ((asl_Int operand1 unsigned)))) *
+               ((ex_int ((asl_Int operand2 unsigned))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__220 = (( 128 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if (((l__221 = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int ((l__220 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")
+   else if (((l__221 = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int ((l__220 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")
+   else sail2_state_monad$assert_expS T "destsize constraint"))`;
+
+
+(*val integer_arithmetic_mul_widening_3264_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_mul_widening_3264_decode:(1)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op54 U Rm o0 Ra Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (a : ii) = (lem$w2ui Ra) in
+   let (destsize : int) = ((( 64 : int):ii)) in
+   let (datasize : int) = ((( 32 : int):ii)) in
+   let (sub_op : bool) = (o0 = (vec_of_bits [B1]  :  1 words$word)) in
+   let (unsigned : bool) = (U = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_integer_arithmetic_mul_widening_3264 a d datasize destsize m n sub_op unsigned)))`;
+
+
+(*val aarch64_integer_arithmetic_mul_uniform_addsub : ii -> ii -> ii -> ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_mul_uniform_addsub:int -> int -> int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) a d l__193 l__194 m n sub_op=
+    (if ((((((l__193 = (( 8 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))))
+   else if ((((((l__193 = (( 8 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__193 = (( 8 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__193 = (( 16 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))))
+   else if ((((((l__193 = (( 16 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__193 = (( 16 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__193 = (( 32 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))))
+   else if ((((((l__193 = (( 32 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__193 = (( 32 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__193 = (( 64 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))))
+   else if ((((((l__193 = (( 64 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__193 = (( 64 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if ((((((l__193 = (( 128 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operand3 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))))
+   else if ((((((l__193 = (( 128 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operand3 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if sub_op then
+         ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))
+       else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))))
+   else if (((l__193 = (( 128 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint"
+   else if (((l__194 = (( 32 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int ((l__193 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")
+   else if (((l__194 = (( 64 : int):ii)))) then sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int ((l__193 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")
+   else sail2_state_monad$assert_expS T "destsize constraint"))`;
+
+
+(*val integer_arithmetic_mul_uniform_addsub_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_mul_uniform_addsub_decode:(1)words$word ->(2)words$word ->(3)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op54 op31 Rm o0 Ra Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (a : ii) = (lem$w2ui Ra) in
+   let (destsize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (datasize : ii) = destsize in
+   let (sub_op : bool) = (o0 = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_integer_arithmetic_mul_uniform_addsub a d datasize destsize m n sub_op)))`;
+
+
+(*val aarch64_integer_arithmetic_div : ii -> ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_div:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__188 m n unsigned=
+    (if (((l__188 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if ((IsZero operand2)) then (( 0 : int):ii)
+       else
+         RoundTowardsZero
+           (((((real_of_int ((asl_Int operand1 unsigned))))) /
+               (((real_of_int ((asl_Int operand2 unsigned)))))))) in
+     aset_X d ((GetSlice_int ((make_the_value (( 8 : int):ii)  :  8 itself)) result (( 0 : int):ii)  :  8 words$word)))))
+   else if (((l__188 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if ((IsZero operand2)) then (( 0 : int):ii)
+       else
+         RoundTowardsZero
+           (((((real_of_int ((asl_Int operand1 unsigned))))) /
+               (((real_of_int ((asl_Int operand2 unsigned)))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 16 : int):ii)  :  16 itself)) result (( 0 : int):ii)  :  16 words$word)))))
+   else if (((l__188 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if ((IsZero operand2)) then (( 0 : int):ii)
+       else
+         RoundTowardsZero
+           (((((real_of_int ((asl_Int operand1 unsigned))))) /
+               (((real_of_int ((asl_Int operand2 unsigned)))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))
+   else if (((l__188 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if ((IsZero operand2)) then (( 0 : int):ii)
+       else
+         RoundTowardsZero
+           (((((real_of_int ((asl_Int operand1 unsigned))))) /
+               (((real_of_int ((asl_Int operand2 unsigned)))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))
+   else if (((l__188 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (result : ii) . 
+     let (result : ii) =
+       (if ((IsZero operand2)) then (( 0 : int):ii)
+       else
+         RoundTowardsZero
+           (((((real_of_int ((asl_Int operand1 unsigned))))) /
+               (((real_of_int ((asl_Int operand2 unsigned)))))))) in
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 128 : int):ii)  :  128 itself)) result (( 0 : int):ii)  :  128 words$word)))))
+   else
+     let dbytes = (ex_int ((l__188 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_arithmetic_div_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_div_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 o1 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (unsigned : bool) = (o1 = (vec_of_bits [B0]  :  1 words$word)) in
+   aarch64_integer_arithmetic_div d datasize m n unsigned)))`;
+
+
+(*val aarch64_integer_arithmetic_cnt : ii -> ii -> ii -> CountOp -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_cnt:int -> int -> int -> CountOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__183 n opcode=
+    (if (((l__183 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_int () )) (\ (result : ii) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1
+      else CountLeadingSignBits operand1) (\ (result : ii) . 
+     aset_X d ((GetSlice_int ((make_the_value (( 8 : int):ii)  :  8 itself)) result (( 0 : int):ii)  :  8 words$word)))))
+   else if (((l__183 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_int () )) (\ (result : ii) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1
+      else CountLeadingSignBits operand1) (\ (result : ii) . 
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 16 : int):ii)  :  16 itself)) result (( 0 : int):ii)  :  16 words$word)))))
+   else if (((l__183 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_int () )) (\ (result : ii) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1
+      else CountLeadingSignBits operand1) (\ (result : ii) . 
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself)) result (( 0 : int):ii)  :  32 words$word)))))
+   else if (((l__183 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_int () )) (\ (result : ii) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1
+      else CountLeadingSignBits operand1) (\ (result : ii) . 
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 64 : int):ii)  :  64 itself)) result (( 0 : int):ii)  :  64 words$word)))))
+   else if (((l__183 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_int () )) (\ (result : ii) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1
+      else CountLeadingSignBits operand1) (\ (result : ii) . 
+     aset_X d
+       ((GetSlice_int ((make_the_value (( 128 : int):ii)  :  128 itself)) result (( 0 : int):ii)  :  128 words$word)))))
+   else
+     let dbytes = (ex_int ((l__183 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_arithmetic_cnt_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_cnt_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 op Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (opcode : CountOp) =
+     (if (((op = (vec_of_bits [B0]  :  1 words$word)))) then CountOp_CLZ
+     else CountOp_CLS) in
+   aarch64_integer_arithmetic_cnt d datasize n opcode)))`;
+
+
+(*val aarch64_integer_arithmetic_addsub_carry : ii -> ii -> ii -> ii -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_addsub_carry:int -> int -> int -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__178 m n setflags sub_op=
+    (if (((l__178 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . 
+     let (operand2 : 8 bits) = (if sub_op then (not_vec operand2  :  8 words$word) else operand2) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+     let (tup__0, tup__1) =
+       ((AddWithCarry operand1 operand2 w__0.ProcState_C  : ( 8 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__178 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . 
+     let (operand2 : 16 bits) = (if sub_op then (not_vec operand2  :  16 words$word) else operand2) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+     let (tup__0, tup__1) =
+       ((AddWithCarry operand1 operand2 w__5.ProcState_C  : ( 16 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__178 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . 
+     let (operand2 : 32 bits) = (if sub_op then (not_vec operand2  :  32 words$word) else operand2) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+     let (tup__0, tup__1) =
+       ((AddWithCarry operand1 operand2 w__10.ProcState_C  : ( 32 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__178 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . 
+     let (operand2 : 64 bits) = (if sub_op then (not_vec operand2  :  64 words$word) else operand2) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . 
+     let (tup__0, tup__1) =
+       ((AddWithCarry operand1 operand2 w__15.ProcState_C  : ( 64 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__178 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . 
+     let (operand2 : 128 bits) = (if sub_op then (not_vec operand2  :  128 words$word) else operand2) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . 
+     let (tup__0, tup__1) =
+       ((AddWithCarry operand1 operand2 w__20.ProcState_C  : ( 128 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else
+     let dbytes = (ex_int ((l__178 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_arithmetic_addsub_carry_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_addsub_carry_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   let (setflags : bool) = (S1 = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_integer_arithmetic_addsub_carry d datasize m n setflags sub_op)))`;
+
+
+(*val ExtendReg : forall 'N . Size 'N => integer -> ii -> ExtendType -> ii -> M (mword 'N)*)
+
+val _ = Define `
+ ((ExtendReg:int -> int -> ExtendType -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) reg typ shift=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((shift >= (( 0 : int):ii))) /\ ((shift <= (( 4 : int):ii)))))) "((shift >= 0) && (shift <= 4))")
+   (aget_X N__tv reg  : ( 'N words$word) M)) (\ (val_name : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (len : ii) . 
+   let (len : ii) =
+     ((case typ of
+       ExtendType_SXTB =>
+        let (unsigned : bool) = F in
+        (( 8 : int):ii)
+     | ExtendType_SXTH =>
+        let (unsigned : bool) = F in
+        (( 16 : int):ii)
+     | ExtendType_SXTW =>
+        let (unsigned : bool) = F in
+        (( 32 : int):ii)
+     | ExtendType_SXTX =>
+        let (unsigned : bool) = F in
+        (( 64 : int):ii)
+     | ExtendType_UXTB =>
+        let (unsigned : bool) = T in
+        (( 8 : int):ii)
+     | ExtendType_UXTH =>
+        let (unsigned : bool) = T in
+        (( 16 : int):ii)
+     | ExtendType_UXTW =>
+        let (unsigned : bool) = T in
+        (( 32 : int):ii)
+     | ExtendType_UXTX =>
+        let (unsigned : bool) = T in
+        (( 64 : int):ii)
+     )) in
+   let len = (int_min len ((((int_of_num (words$word_len val_name))) - shift))) in sail2_state_monad$bindS
+   (coerce_int_nat shift) (\ shift2 . 
+   let (len2 : int) = (ex_int len) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "hack")
+   (sail2_state_monad$returnS ((place_subrange ((int_of_num (words$word_len val_name))) val_name ((len2 - (( 1 : int):ii))) (( 0 : int):ii)
+              ((ex_nat shift2))
+             :  'N words$word)))))))))`;
+
+
+(*val aget_ELR__0 : mword ty2 -> M (mword ty64)*)
+
+(*val aget_ELR__1 : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((aget_ELR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (r : 64 bits) . 
+   let pat_0 = el in
+   if (((pat_0 = EL1))) then (sail2_state_monad$read_regS ELR_EL1_ref  : ( 64 words$word) M)
+   else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS ELR_EL2_ref  : ( 64 words$word) M)
+   else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS ELR_EL3_ref  : ( 64 words$word) M)
+   else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`;
+
+
+val _ = Define `
+ ((aget_ELR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL0))) "")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . 
+   (aget_ELR__0 w__1.ProcState_EL  : ( 64 words$word) M)))))`;
+
+
+(*val ROR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*)
+
+val _ = Define `
+ ((ROR_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((shift <> (( 0 : int):ii)))) "(shift != 0)")
+   (let (m : ii) = (shift % ((int_of_num (words$word_len x)))) in sail2_state_monad$bindS
+   (LSR x m  : ( 'N words$word) M) (\ (w__0 :  'N words$word) .  sail2_state_monad$bindS
+   (LSL x ((((int_of_num (words$word_len x))) - ((ex_int m))))  : ( 'N words$word) M) (\ (w__1 :  'N words$word) . 
+   let (result : 'N bits) = ((or_vec w__0 w__1  :  'N words$word)) in
+   let (carry_out : 1 bits) =
+     ((vec_of_bits [access_vec_dec result ((((int_of_num (words$word_len result))) - (( 1 : int):ii)))]  :  1 words$word)) in
+   sail2_state_monad$returnS (result, carry_out))))))`;
+
+
+(*val ROR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*)
+
+val _ = Define `
+ ((ROR:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)")
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M)) (\ (anon10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len x)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x
+   else sail2_state_monad$bindS
+     (ROR_C x shift  : (( 'N words$word #  1 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+     let (result : 'N bits) = tup__0 in
+     let (anon10 : 1 bits) = tup__1 in
+     sail2_state_monad$returnS result)))))`;
+
+
+(*val aarch64_integer_bitfield : forall 'datasize. Size 'datasize => ii -> ii -> ii -> itself 'datasize -> bool -> bool -> ii -> mword 'datasize -> mword 'datasize -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_bitfield:int -> int -> int -> 'datasize itself -> bool -> bool -> int -> 'datasize words$word -> 'datasize words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) R1 S1 d datasize extend inzero n tmask wmask=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (if inzero then sail2_state_monad$returnS ((Zeros__1 datasize ()   :  'datasize words$word))
+    else (aget_X datasize d  : ( 'datasize words$word) M))) (\ (dst : 'datasize bits) .  sail2_state_monad$bindS
+   (aget_X datasize n  : ( 'datasize words$word) M) (\ (src : 'datasize bits) .  sail2_state_monad$bindS
+   (ROR src R1  : ( 'datasize words$word) M) (\ (w__1 :  'datasize words$word) . 
+   let (bot : 'datasize bits) =
+     ((or_vec ((and_vec dst ((not_vec wmask  :  'datasize words$word))  :  'datasize words$word))
+        ((and_vec w__1 wmask  :  'datasize words$word))
+       :  'datasize words$word)) in sail2_state_monad$bindS
+   (if extend then
+      (Replicate ((int_of_num (words$word_len bot))) (vec_of_bits [access_vec_dec src S1]  :  1 words$word)
+        : ( 'datasize words$word) M)
+    else sail2_state_monad$returnS dst) (\ (top : 'datasize bits) . 
+   aset_X d
+     ((or_vec ((and_vec top ((not_vec tmask  :  'datasize words$word))  :  'datasize words$word))
+         ((and_vec bot tmask  :  'datasize words$word))
+        :  'datasize words$word))))))))`;
+
+
+(*val ShiftReg : forall 'N . Size 'N => integer -> ii -> ShiftType -> ii -> M (mword 'N)*)
+
+val _ = Define `
+ ((ShiftReg:int -> int -> ShiftType -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) reg typ amount=  (sail2_state_monad$bindS
+   (aget_X N__tv reg  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   (case typ of
+     ShiftType_LSL => (LSL result amount  : ( 'N words$word) M)
+   | ShiftType_LSR => (LSR result amount  : ( 'N words$word) M)
+   | ShiftType_ASR => (ASR result amount  : ( 'N words$word) M)
+   | ShiftType_ROR => (ROR result amount  : ( 'N words$word) M)
+   ))))`;
+
+
+(*val aarch64_integer_shift_variable : ii -> ii -> ii -> ii -> ShiftType -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_shift_variable:int -> int -> int -> int -> ShiftType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__173 m n shift_type=
+    (if (((l__173 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 8 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 8 : int):ii)))  : ( 8 words$word) M) (\ (w__0 : 8
+       bits) . 
+     let result = w__0 in
+     aset_X d result)))
+   else if (((l__173 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 16 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 16 : int):ii)))  : ( 16 words$word) M) (\ (w__1 : 16
+       bits) . 
+     let result = w__1 in
+     aset_X d result)))
+   else if (((l__173 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 32 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 32 : int):ii)))  : ( 32 words$word) M) (\ (w__2 : 32
+       bits) . 
+     let result = w__2 in
+     aset_X d result)))
+   else if (((l__173 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 64 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 64 : int):ii)))  : ( 64 words$word) M) (\ (w__3 : 64
+       bits) . 
+     let result = w__3 in
+     aset_X d result)))
+   else if (((l__173 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 128 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 128 : int):ii)))  : ( 128 words$word) M) (\ (w__4 : 128
+       bits) . 
+     let result = w__4 in
+     aset_X d result)))
+   else
+     let dbytes = (ex_int ((l__173 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_shift_variable_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_shift_variable_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 op2 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (shift_type : ShiftType) = (DecodeShift op2) in
+   aarch64_integer_shift_variable d datasize m n shift_type)))`;
+
+
+(*val aarch64_integer_logical_shiftedreg : ii -> ii -> bool -> ii -> ii -> LogicalOp -> bool -> ii -> ShiftType -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_logical_shiftedreg:int -> int -> bool -> int -> int -> LogicalOp -> bool -> int -> ShiftType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__168 invert m n op setflags shift_amount shift_type=
+    (if (((l__168 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 8 : int):ii) m shift_type shift_amount  : ( 8 words$word) M) (\ (operand2 : 8 bits) . 
+     let (operand2 : 8 bits) = (if invert then (not_vec operand2  :  8 words$word) else operand2) in sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (result : 8 bits) . 
+     let (result : 8 bits) =
+       ((case op of
+         LogicalOp_AND => (and_vec operand1 operand2  :  8 words$word)
+       | LogicalOp_ORR => (or_vec operand1 operand2  :  8 words$word)
+       | LogicalOp_EOR => (xor_vec operand1 operand2  :  8 words$word)
+       )) in sail2_state_monad$seqS
+     (if setflags then
+        let split_vec =
+          ((concat_vec
+             ((concat_vec
+                 (vec_of_bits [access_vec_dec result (((( 8 : int):ii) - (( 1 : int):ii)))]  :  1 words$word)
+                 ((IsZeroBit result  :  1 words$word))
+                :  2 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word)) in
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))
+   else if (((l__168 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 16 : int):ii) m shift_type shift_amount  : ( 16 words$word) M) (\ (operand2 : 16 bits) . 
+     let (operand2 : 16 bits) = (if invert then (not_vec operand2  :  16 words$word) else operand2) in sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (result : 16 bits) . 
+     let (result : 16 bits) =
+       ((case op of
+         LogicalOp_AND => (and_vec operand1 operand2  :  16 words$word)
+       | LogicalOp_ORR => (or_vec operand1 operand2  :  16 words$word)
+       | LogicalOp_EOR => (xor_vec operand1 operand2  :  16 words$word)
+       )) in sail2_state_monad$seqS
+     (if setflags then
+        let split_vec =
+          ((concat_vec
+             ((concat_vec
+                 (vec_of_bits [access_vec_dec result (((( 16 : int):ii) - (( 1 : int):ii)))]  :  1 words$word)
+                 ((IsZeroBit result  :  1 words$word))
+                :  2 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word)) in
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))
+   else if (((l__168 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 32 : int):ii) m shift_type shift_amount  : ( 32 words$word) M) (\ (operand2 : 32 bits) . 
+     let (operand2 : 32 bits) = (if invert then (not_vec operand2  :  32 words$word) else operand2) in sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (result : 32 bits) . 
+     let (result : 32 bits) =
+       ((case op of
+         LogicalOp_AND => (and_vec operand1 operand2  :  32 words$word)
+       | LogicalOp_ORR => (or_vec operand1 operand2  :  32 words$word)
+       | LogicalOp_EOR => (xor_vec operand1 operand2  :  32 words$word)
+       )) in sail2_state_monad$seqS
+     (if setflags then
+        let split_vec =
+          ((concat_vec
+             ((concat_vec
+                 (vec_of_bits [access_vec_dec result (((( 32 : int):ii) - (( 1 : int):ii)))]  :  1 words$word)
+                 ((IsZeroBit result  :  1 words$word))
+                :  2 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word)) in
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))
+   else if (((l__168 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 64 : int):ii) m shift_type shift_amount  : ( 64 words$word) M) (\ (operand2 : 64 bits) . 
+     let (operand2 : 64 bits) = (if invert then (not_vec operand2  :  64 words$word) else operand2) in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) . 
+     let (result : 64 bits) =
+       ((case op of
+         LogicalOp_AND => (and_vec operand1 operand2  :  64 words$word)
+       | LogicalOp_ORR => (or_vec operand1 operand2  :  64 words$word)
+       | LogicalOp_EOR => (xor_vec operand1 operand2  :  64 words$word)
+       )) in sail2_state_monad$seqS
+     (if setflags then
+        let split_vec =
+          ((concat_vec
+             ((concat_vec
+                 (vec_of_bits [access_vec_dec result (((( 64 : int):ii) - (( 1 : int):ii)))]  :  1 words$word)
+                 ((IsZeroBit result  :  1 words$word))
+                :  2 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word)) in
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))
+   else if (((l__168 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 128 : int):ii) m shift_type shift_amount  : ( 128 words$word) M) (\ (operand2 : 128 bits) . 
+     let (operand2 : 128 bits) = (if invert then (not_vec operand2  :  128 words$word) else operand2) in sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (result : 128 bits) . 
+     let (result : 128 bits) =
+       ((case op of
+         LogicalOp_AND => (and_vec operand1 operand2  :  128 words$word)
+       | LogicalOp_ORR => (or_vec operand1 operand2  :  128 words$word)
+       | LogicalOp_EOR => (xor_vec operand1 operand2  :  128 words$word)
+       )) in sail2_state_monad$seqS
+     (if setflags then
+        let split_vec =
+          ((concat_vec
+             ((concat_vec
+                 (vec_of_bits [access_vec_dec result (((( 128 : int):ii) - (( 1 : int):ii)))]  :  1 words$word)
+                 ((IsZeroBit result  :  1 words$word))
+                :  2 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word)) in
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))
+   else
+     let dbytes = (ex_int ((l__168 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_integer_arithmetic_addsub_shiftedreg : ii -> ii -> ii -> ii -> bool -> ii -> ShiftType -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_addsub_shiftedreg:int -> int -> int -> int -> bool -> int -> ShiftType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__163 m n setflags shift_amount shift_type sub_op=
+    (if (((l__163 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 8 : int):ii) m shift_type shift_amount  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 8 bits)) =
+       (if sub_op then
+         let (operand2 : 8 bits) = ((not_vec operand2  :  8 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 8 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__163 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 16 : int):ii) m shift_type shift_amount  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 16 bits)) =
+       (if sub_op then
+         let (operand2 : 16 bits) = ((not_vec operand2  :  16 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 16 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__163 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 32 : int):ii) m shift_type shift_amount  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 32 bits)) =
+       (if sub_op then
+         let (operand2 : 32 bits) = ((not_vec operand2  :  32 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 32 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__163 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 64 : int):ii) m shift_type shift_amount  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 64 bits)) =
+       (if sub_op then
+         let (operand2 : 64 bits) = ((not_vec operand2  :  64 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 64 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else if (((l__163 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (ShiftReg (( 128 : int):ii) m shift_type shift_amount  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 128 bits)) =
+       (if sub_op then
+         let (operand2 : 128 bits) = ((not_vec operand2  :  128 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 128 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (aset_X d result))))))
+   else
+     let dbytes = (ex_int ((l__163 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val Prefetch : mword ty64 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((Prefetch:(64)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address prfop=  (sail2_state_monad$bindS
+   (undefined_PrefetchHint () ) (\ (hint : PrefetchHint) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (target : ii) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (stream : bool) . 
+   let b__0 = ((slice prfop (( 3 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+   let (hint : PrefetchHint) =
+     (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then Prefetch_READ
+     else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then Prefetch_EXEC
+     else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then Prefetch_WRITE
+     else hint) in
+   let (target : ii) = (lem$w2ui ((slice prfop (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word))) in
+   let (stream : bool) =
+     ((vec_of_bits [access_vec_dec prfop (( 0 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)) in
+   let (_ : unit) = (Hint_Prefetch address hint target stream) in
+   sail2_state_monad$returnS () )))))`;
+
+
+(*val IsSecondStage : FaultRecord -> M bool*)
+
+val _ = Define `
+ ((IsSecondStage:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)")
+   (sail2_state_monad$returnS fault.FaultRecord_secondstage)))`;
+
+
+(*val IsFault : AddressDescriptor -> bool*)
+
+val _ = Define `
+ ((IsFault:AddressDescriptor -> bool) addrdesc=  (addrdesc.AddressDescriptor_fault.FaultRecord_typ <> Fault_None))`;
+
+
+(*val CombineS1S2Desc : AddressDescriptor -> AddressDescriptor -> M AddressDescriptor*)
+
+val _ = Define `
+ ((CombineS1S2Desc:AddressDescriptor -> AddressDescriptor ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s1desc s2desc=  (sail2_state_monad$bindS
+   (undefined_AddressDescriptor () ) (\ (result : AddressDescriptor) . 
+   let result = ((result with<| AddressDescriptor_paddress := (s2desc.AddressDescriptor_paddress)|>)) in sail2_state_monad$bindS
+   (if (((((IsFault s1desc)) \/ ((IsFault s2desc))))) then
+      let (result : AddressDescriptor) = (if ((IsFault s1desc)) then s1desc else s2desc) in
+      sail2_state_monad$returnS result
+    else if ((((((s2desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device))) \/ (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) then
+      let (tmp_610 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in
+      let tmp_610 = ((tmp_610 with<| MemoryAttributes_typ := MemType_Device|>)) in
+      let result = ((result with<| AddressDescriptor_memattrs := tmp_610|>)) in
+      if (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Normal))) then
+        let (tmp_620 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in
+        let (tmp_620 : MemoryAttributes) =
+          ((tmp_620 with<|
+            MemoryAttributes_device := (s2desc.AddressDescriptor_memattrs.MemoryAttributes_device)|>)) in
+        let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_620|>)) in
+        sail2_state_monad$returnS result
+      else if (((s2desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Normal))) then
+        let (tmp_630 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in
+        let (tmp_630 : MemoryAttributes) =
+          ((tmp_630 with<|
+            MemoryAttributes_device := (s1desc.AddressDescriptor_memattrs.MemoryAttributes_device)|>)) in
+        let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_630|>)) in
+        sail2_state_monad$returnS result
+      else
+        let (tmp_640 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS
+        (CombineS1S2Device s1desc.AddressDescriptor_memattrs.MemoryAttributes_device
+          s2desc.AddressDescriptor_memattrs.MemoryAttributes_device) (\ (w__0 : DeviceType) . 
+        let (tmp_640 : MemoryAttributes) = ((tmp_640 with<| MemoryAttributes_device := w__0|>)) in
+        let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_640|>)) in
+        sail2_state_monad$returnS result)
+    else
+      let (tmp_650 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in
+      let tmp_650 = ((tmp_650 with<| MemoryAttributes_typ := MemType_Normal|>)) in
+      let result = ((result with<| AddressDescriptor_memattrs := tmp_650|>)) in
+      let (tmp_660 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS
+      (undefined_DeviceType () ) (\ (w__1 : DeviceType) . 
+      let tmp_660 = ((tmp_660 with<| MemoryAttributes_device := w__1|>)) in
+      let result = ((result with<| AddressDescriptor_memattrs := tmp_660|>)) in
+      let (tmp_670 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS
+      (CombineS1S2AttrHints s1desc.AddressDescriptor_memattrs.MemoryAttributes_inner
+        s2desc.AddressDescriptor_memattrs.MemoryAttributes_inner) (\ (w__2 : MemAttrHints) . 
+      let tmp_670 = ((tmp_670 with<| MemoryAttributes_inner := w__2|>)) in
+      let result = ((result with<| AddressDescriptor_memattrs := tmp_670|>)) in
+      let (tmp_680 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS
+      (CombineS1S2AttrHints s1desc.AddressDescriptor_memattrs.MemoryAttributes_outer
+        s2desc.AddressDescriptor_memattrs.MemoryAttributes_outer) (\ (w__3 : MemAttrHints) . 
+      let (tmp_680 : MemoryAttributes) = ((tmp_680 with<| MemoryAttributes_outer := w__3|>)) in
+      let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_680|>)) in
+      let (tmp_690 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in
+      let (tmp_690 : MemoryAttributes) =
+        ((tmp_690 with<|
+          MemoryAttributes_shareable :=
+            (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_shareable \/ s2desc.AddressDescriptor_memattrs.MemoryAttributes_shareable)))|>)) in
+      let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_690|>)) in
+      let (tmp_700 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in
+      let (tmp_700 : MemoryAttributes) =
+        ((tmp_700 with<|
+          MemoryAttributes_outershareable :=
+            (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_outershareable \/ s2desc.AddressDescriptor_memattrs.MemoryAttributes_outershareable)))|>)) in
+      let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_700|>)) in
+      sail2_state_monad$returnS result)))) (\ (result : AddressDescriptor) .  sail2_state_monad$bindS
+   (MemAttrDefaults result.AddressDescriptor_memattrs) (\ (w__4 : MemoryAttributes) . 
+   let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := w__4|>)) in
+   sail2_state_monad$returnS result)))))`;
+
+
+(*val IsExternalSyncAbort__0 : Fault -> M bool*)
+
+(*val IsExternalSyncAbort__1 : FaultRecord -> M bool*)
+
+val _ = Define `
+ ((IsExternalSyncAbort__0:Fault ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((typ <> Fault_None))) "")
+   (sail2_state_monad$returnS ((((((typ = Fault_SyncExternal))) \/ ((((((typ = Fault_SyncParity))) \/ ((((((typ = Fault_SyncExternalOnWalk))) \/ (((typ = Fault_SyncParityOnWalk)))))))))))))))`;
+
+
+val _ = Define `
+ ((IsExternalSyncAbort__1:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (IsExternalSyncAbort__0 fault.FaultRecord_typ))`;
+
+
+(*val IsExternalAbort__0 : Fault -> M bool*)
+
+(*val IsExternalAbort__1 : FaultRecord -> M bool*)
+
+val _ = Define `
+ ((IsExternalAbort__0:Fault ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((typ <> Fault_None))) "")
+   (sail2_state_monad$returnS ((((((typ = Fault_SyncExternal))) \/ ((((((typ = Fault_SyncParity))) \/ ((((((typ = Fault_SyncExternalOnWalk))) \/ ((((((typ = Fault_SyncParityOnWalk))) \/ ((((((typ = Fault_AsyncExternal))) \/ (((typ = Fault_AsyncParity)))))))))))))))))))))`;
+
+
+val _ = Define `
+ ((IsExternalAbort__1:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (IsExternalAbort__0 fault.FaultRecord_typ))`;
+
+
+(*val IsDebugException : FaultRecord -> M bool*)
+
+val _ = Define `
+ ((IsDebugException:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)")
+   (sail2_state_monad$returnS (((fault.FaultRecord_typ = Fault_Debug))))))`;
+
+
+(*val IPAValid : FaultRecord -> M bool*)
+
+val _ = Define `
+ ((IPAValid:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)")
+   (sail2_state_monad$returnS (if fault.FaultRecord_s2fs1walk then
+             ((((fault.FaultRecord_typ = Fault_AccessFlag))) \/ ((((((fault.FaultRecord_typ = Fault_Permission))) \/ ((((((fault.FaultRecord_typ = Fault_Translation))) \/ (((fault.FaultRecord_typ = Fault_AddressSize))))))))))
+           else if fault.FaultRecord_secondstage then
+             ((((fault.FaultRecord_typ = Fault_AccessFlag))) \/ ((((((fault.FaultRecord_typ = Fault_Translation))) \/ (((fault.FaultRecord_typ = Fault_AddressSize)))))))
+           else F))))`;
+
+
+(*val aarch64_integer_logical_immediate : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> ii -> LogicalOp -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_logical_immediate:int -> 'datasize itself -> 'datasize words$word -> int -> LogicalOp -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d datasize imm n op setflags=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (undefined_bitvector datasize  : ( 'datasize words$word) M)) (\ (result : 'datasize bits) .  sail2_state_monad$bindS
+   (aget_X datasize n  : ( 'datasize words$word) M) (\ (operand1 : 'datasize bits) . 
+   let (operand2 : 'datasize bits) = imm in
+   let (result : 'datasize bits) =
+     ((case op of
+       LogicalOp_AND => (and_vec operand1 operand2  :  'datasize words$word)
+     | LogicalOp_ORR => (or_vec operand1 operand2  :  'datasize words$word)
+     | LogicalOp_EOR => (xor_vec operand1 operand2  :  'datasize words$word)
+     )) in sail2_state_monad$seqS
+   (if setflags then
+      let split_vec =
+        ((concat_vec
+           ((concat_vec
+               (vec_of_bits [access_vec_dec result ((datasize - (( 1 : int):ii)))]  :  1 words$word)
+               ((IsZeroBit result  :  1 words$word))
+              :  2 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+          :  4 words$word)) in
+      let (tup__0, tup__1, tup__2, tup__3) =
+        ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>)))))
+    else sail2_state_monad$returnS () )
+   (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+   else aset_X d result)))))`;
+
+
+(*val aarch64_integer_arithmetic_addsub_immediate : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> ii -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_addsub_immediate:int -> 'datasize itself -> 'datasize words$word -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d datasize imm n setflags sub_op=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (undefined_bitvector datasize  : ( 'datasize words$word) M)) (\ (result : 'datasize bits) .  sail2_state_monad$bindS
+   (if (((n = (( 31 : int):ii)))) then (aget_SP datasize ()   : ( 'datasize words$word) M)
+    else (aget_X datasize n  : ( 'datasize words$word) M)) (\ (operand1 : 'datasize bits) . 
+   let (operand2 : 'datasize bits) = imm in sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+   let ((carry_in : 1 bits), (operand2 : 'datasize bits)) =
+     (if sub_op then
+       let (operand2 : 'datasize bits) = ((not_vec operand2  :  'datasize words$word)) in
+       let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+       (carry_in, operand2)
+     else
+       let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+       (carry_in, operand2)) in
+   let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 'datasize words$word #  4 words$word))) in
+   let result = tup__0 in
+   let nzcv1 = tup__1 in sail2_state_monad$seqS
+   (if setflags then
+      let (tup__0, tup__1, tup__2, tup__3) =
+        ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_N := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_Z := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_C := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_V := tup__3|>)))))
+    else sail2_state_monad$returnS () )
+   (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+   else aset_X d result)))))))`;
+
+
+(*val aarch64_integer_arithmetic_addsub_extendedreg : ii -> ii -> ExtendType -> ii -> ii -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_arithmetic_addsub_extendedreg:int -> int -> ExtendType -> int -> int -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__158 extend_type m n setflags shift sub_op=
+    (if (((l__158 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then (aget_SP (( 8 : int):ii) ()   : ( 8 words$word) M)
+      else (aget_X (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (ExtendReg (( 8 : int):ii) m extend_type shift  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 8 bits)) =
+       (if sub_op then
+         let (operand2 : 8 bits) = ((not_vec operand2  :  8 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 8 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+     else aset_X d result))))))
+   else if (((l__158 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then (aget_SP (( 16 : int):ii) ()   : ( 16 words$word) M)
+      else (aget_X (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (ExtendReg (( 16 : int):ii) m extend_type shift  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 16 bits)) =
+       (if sub_op then
+         let (operand2 : 16 bits) = ((not_vec operand2  :  16 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 16 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+     else aset_X d result))))))
+   else if (((l__158 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then (aget_SP (( 32 : int):ii) ()   : ( 32 words$word) M)
+      else (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (ExtendReg (( 32 : int):ii) m extend_type shift  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 32 bits)) =
+       (if sub_op then
+         let (operand2 : 32 bits) = ((not_vec operand2  :  32 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 32 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+     else aset_X d result))))))
+   else if (((l__158 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 64 bits)) =
+       (if sub_op then
+         let (operand2 : 64 bits) = ((not_vec operand2  :  64 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 64 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__21 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+     else aset_X d result))))))
+   else if (((l__158 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then (aget_SP (( 128 : int):ii) ()   : ( 128 words$word) M)
+      else (aget_X (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (ExtendReg (( 128 : int):ii) m extend_type shift  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (nzcv1 : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (carry_in : 1 bits) . 
+     let ((carry_in : 1 bits), (operand2 : 128 bits)) =
+       (if sub_op then
+         let (operand2 : 128 bits) = ((not_vec operand2  :  128 words$word)) in
+         let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         (carry_in, operand2)
+       else
+         let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         (carry_in, operand2)) in
+     let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 128 words$word #  4 words$word))) in
+     let result = tup__0 in
+     let nzcv1 = tup__1 in sail2_state_monad$seqS
+     (if setflags then
+        let (tup__0, tup__1, tup__2, tup__3) =
+          ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+           (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_N := tup__0|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_Z := tup__1|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_C := tup__2|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_V := tup__3|>)))))
+      else sail2_state_monad$returnS () )
+     (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result
+     else aset_X d result))))))
+   else
+     let dbytes = (ex_int ((l__158 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val RestoredITBits : mword ty32 -> M (mword ty8)*)
+
+val _ = Define `
+ ((RestoredITBits:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((8)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr=
+    (let (it : 8 bits) =
+     ((concat_vec ((subrange_vec_dec spsr (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word))
+        ((subrange_vec_dec spsr (( 26 : int):ii) (( 25 : int):ii)  :  2 words$word))
+       :  8 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   if (((w__0.ProcState_IL = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+     (ConstrainUnpredictableBool Unpredictable_ILZEROIT) (\ (w__1 : bool) . 
+     sail2_state_monad$returnS (if w__1 then (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+             else it))
+   else if (((((~ ((IsZero ((subrange_vec_dec it (( 7 : int):ii) (( 4 : int):ii)  :  4 words$word)))))) /\ ((IsZero ((subrange_vec_dec it (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))))))) then
+     sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$bindS
+     (if (((w__2.ProcState_EL = EL2))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS HSCTLR_ref  : ( 32 words$word) M) (\ (w__3 : 32 bits) . 
+        sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__3 (( 7 : int):ii)]  :  1 words$word))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+        sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 7 : int):ii)]  :  1 words$word))) (\ (itd : 1 bits) . 
+     sail2_state_monad$returnS (if ((((((((((vec_of_bits [access_vec_dec spsr (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) /\ ((~ ((IsZero it))))))) \/ ((((((itd = (vec_of_bits [B1]  :  1 words$word)))) /\ ((~ ((IsZero ((subrange_vec_dec it (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))))))))))))
+             then
+               (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+             else it))))))`;
+
+
+(*val IsEL1TransRegimeRegs : unit -> M bool*)
+
+val _ = Define `
+ ((IsEL1TransRegimeRegs:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$or_boolS
+     (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL1))))))
+     (sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL0)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))))))`;
+
+
+(*val CalculateTBI : mword ty64 -> bool -> M bool*)
+
+val _ = Define `
+ ((CalculateTBI:(64)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr data=
+    (let (tbi : bool) = F in sail2_state_monad$bindS
+   (PtrHasUpperAndLowerAddRanges () ) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (IsEL1TransRegimeRegs () ) (\ (w__1 : bool) . 
+     if w__1 then
+       if data then
+         if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+         else sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+       else if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+         sail2_state$and_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 52 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+       else
+         sail2_state$and_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+     else if data then
+       if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+     else if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       sail2_state$and_boolS
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__14 : 64 bits) . 
+          sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__15 : 64 bits) . 
+          sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__15 (( 52 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+     else
+       sail2_state$and_boolS
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__17 : 64 bits) . 
+          sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+          sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . 
+     if (((w__20.ProcState_EL = EL2))) then
+       if data then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__21 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__21 (( 20 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+       else
+         sail2_state$and_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__22 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__22 (( 20 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__23 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 29 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+     else sail2_state_monad$bindS
+       (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . 
+       if (((w__26.ProcState_EL = EL3))) then
+         if data then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__27 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__27 (( 20 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+         else
+           sail2_state$and_boolS
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__28 : 32 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__28 (( 20 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__29 : 32 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__29 (( 29 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+       else sail2_state_monad$returnS tbi)))))`;
+
+
+(*val CalculateBottomPACBit : mword ty64 -> mword ty1 -> M ii*)
+
+val _ = Define `
+ ((CalculateBottomPACBit:(64)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr top_bit=  (sail2_state_monad$bindS
+   (undefined_int () ) (\ (tsz_field : ii) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (using64k : bool) .  sail2_state_monad$bindS
+   (PtrHasUpperAndLowerAddRanges () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (if w__0 then sail2_state_monad$bindS
+      (IsEL1TransRegimeRegs () ) (\ (w__1 : bool) . 
+      if w__1 then sail2_state_monad$bindS
+        (if (((top_bit = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+           sail2_state_monad$returnS ((lem$w2ui ((slice w__2 (( 16 : int):ii) (( 6 : int):ii)  :  6 words$word)))))
+         else sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+           sail2_state_monad$returnS ((lem$w2ui ((slice w__3 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word)))))) (\ (w__4 : ii) . 
+        let tsz_field = w__4 in sail2_state_monad$bindS
+        (if (((top_bit = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+           sail2_state_monad$returnS (((((slice w__5 (( 30 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))
+         else sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+           sail2_state_monad$returnS (((((slice w__6 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))) (\ (w__7 : bool) . 
+        let (using64k : bool) = w__7 in
+        sail2_state_monad$returnS (tsz_field, using64k)))
+      else sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((HaveEL EL2)) "HaveEL(EL2)")
+        (if (((top_bit = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+           sail2_state_monad$returnS ((lem$w2ui ((slice w__8 (( 16 : int):ii) (( 6 : int):ii)  :  6 words$word)))))
+         else sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+           sail2_state_monad$returnS ((lem$w2ui ((slice w__9 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))))) (\ (w__10 : ii) . 
+        let tsz_field = w__10 in sail2_state_monad$bindS
+        (if (((top_bit = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+           sail2_state_monad$returnS (((((slice w__11 (( 30 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))
+         else sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+           sail2_state_monad$returnS (((((slice w__12 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))) (\ (w__13 : bool) . 
+        let (using64k : bool) = w__13 in
+        sail2_state_monad$returnS (tsz_field, using64k))))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) .  sail2_state_monad$bindS
+      (if (((w__14.ProcState_EL = EL2))) then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__15 : 64 bits) . 
+         sail2_state_monad$returnS ((lem$w2ui ((slice w__15 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word)))))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__16 : 32 bits) . 
+         sail2_state_monad$returnS ((lem$w2ui ((slice w__16 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word)))))) (\ (w__17 : ii) . 
+      let tsz_field = w__17 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__18 : ProcState) .  sail2_state_monad$bindS
+      (if (((w__18.ProcState_EL = EL2))) then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__19 : 64 bits) . 
+         sail2_state_monad$returnS (((((slice w__19 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS (((((slice w__20 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))) (\ (w__21 : bool) . 
+      let (using64k : bool) = w__21 in
+      sail2_state_monad$returnS (tsz_field, using64k)))))) (\ varstup .  let ((tsz_field : ii), (using64k : bool)) = varstup in
+   let (max_limit_tsz_field : ii) = ((( 39 : int):ii)) in sail2_state_monad$bindS
+   (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+   (if ((((ex_int tsz_field)) > ((ex_int max_limit_tsz_field)))) then
+      let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FORCE) || (c == Constraint_NONE))")
+      (let (tsz_field : ii) = (if (((c = Constraint_FORCE))) then max_limit_tsz_field else tsz_field) in
+      sail2_state_monad$returnS (c, tsz_field))
+    else sail2_state_monad$returnS (c, tsz_field)) (\ varstup .  let ((c : Constraint), (tsz_field : ii)) = varstup in
+   let (tszmin : ii) =
+     (if (((using64k /\ (((((ex_int ((VAMax () )))) = (( 52 : int):ii))))))) then (( 12 : int):ii)
+     else (( 16 : int):ii)) in sail2_state_monad$bindS
+   (if ((((ex_int tsz_field)) < ((ex_int tszmin)))) then
+      let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FORCE) || (c == Constraint_NONE))")
+      (let (tsz_field : ii) = (if (((c = Constraint_FORCE))) then tszmin else tsz_field) in
+      sail2_state_monad$returnS tsz_field)
+    else sail2_state_monad$returnS tsz_field) (\ (tsz_field : ii) . 
+   sail2_state_monad$returnS (((( 64 : int):ii) - ((ex_int tsz_field)))))))))))))`;
+
+
+(*val Auth : mword ty64 -> mword ty64 -> mword ty128 -> bool -> mword ty1 -> M (mword ty64)*)
+
+val _ = Define `
+ ((Auth:(64)words$word ->(64)words$word ->(128)words$word -> bool ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr modifier K1 data keynumber=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (PAC : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (original_ptr : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (error_code : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (extfield : 64 bits) .  sail2_state_monad$bindS
+   (CalculateTBI ptr data) (\ (tbi : bool) .  sail2_state_monad$bindS
+   (CalculateBottomPACBit ptr (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word)) (\ (w__0 :
+     ii) . 
+   let bottom_PAC_bit = (ex_int w__0) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (let extfield =
+     ((replicate_bits (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word) (( 64 : int):ii)  :  64 words$word)) in
+   let (original_ptr : 64 bits) =
+     (if tbi then
+       (concat_vec ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word))
+          ((subrange_subrange_concat
+              ((((((((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) -
+                              (( 1 : int):ii)))
+                          - (((( 0 : int):ii) - (( 1 : int):ii)))))
+                      +
+                      ((bottom_PAC_bit - (( 1 : int):ii)))))
+                  - (((( 0 : int):ii) - (( 1 : int):ii)))))
+              extfield
+              ((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii)
+              ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii)
+             :  56 words$word))
+         :  64 words$word)
+     else
+       (subrange_subrange_concat ((int_of_num (words$word_len PAC))) extfield
+          ((((((~ bottom_PAC_bit)) + (( 64 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii) ptr
+          ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii)
+         :  64 words$word)) in sail2_state_monad$bindS
+   (ComputePAC original_ptr modifier ((subrange_vec_dec K1 (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word))
+      ((subrange_vec_dec K1 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+     : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (PAC : 64 bits) = w__1 in
+   let (result : 64 bits) =
+     (if tbi then
+       if ((subrange_subrange_eq PAC
+              ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii)))
+                  +
+                  bottom_PAC_bit)) bottom_PAC_bit ptr
+              ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii)))
+                  +
+                  bottom_PAC_bit)) bottom_PAC_bit)) then
+         original_ptr
+       else
+         let (error_code : 2 bits) =
+           ((concat_vec keynumber ((not_vec keynumber  :  1 words$word))  :  2 words$word)) in
+         (concat_vec
+            ((concat_vec ((subrange_vec_dec original_ptr (( 63 : int):ii) (( 55 : int):ii)  :  9 words$word)) error_code
+               :  11 words$word)) ((subrange_vec_dec original_ptr (( 52 : int):ii) (( 0 : int):ii)  :  53 words$word))
+           :  64 words$word)
+     else if (((((subrange_subrange_eq PAC
+                     ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) -
+                             (( 1 : int):ii)))
+                         + bottom_PAC_bit)) bottom_PAC_bit ptr
+                     ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) -
+                             (( 1 : int):ii)))
+                         + bottom_PAC_bit)) bottom_PAC_bit)) /\ (((((subrange_vec_dec PAC (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word)) = ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word)))))))) then
+       original_ptr
+     else
+       let (error_code : 2 bits) =
+         ((concat_vec keynumber ((not_vec keynumber  :  1 words$word))  :  2 words$word)) in
+       (concat_vec
+          ((concat_vec (vec_of_bits [access_vec_dec original_ptr (( 63 : int):ii)]  :  1 words$word) error_code
+             :  3 words$word)) ((subrange_vec_dec original_ptr (( 60 : int):ii) (( 0 : int):ii)  :  61 words$word))
+         :  64 words$word)) in
+   sail2_state_monad$returnS result)))))))))))`;
+
+
+(*val HighestELUsingAArch32 : unit -> bool*)
+
+val _ = Define `
+ ((HighestELUsingAArch32:unit -> bool) () =  (if ((~ ((HaveAnyAArch32 () )))) then F else F))`;
+
+
+(*val aget_SCR_GEN : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((aget_SCR_GEN:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((HaveEL EL3)) "HaveEL(EL3)")
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (r : 32 bits) . 
+   if ((HighestELUsingAArch32 () )) then (sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M)
+   else (sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M))))`;
+
+
+(*val IsSecureBelowEL3 : unit -> M bool*)
+
+val _ = Define `
+ ((IsSecureBelowEL3:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (if ((HaveEL EL3)) then sail2_state_monad$bindS
+     (aget_SCR_GEN ()   : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+     sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))
+   else sail2_state_monad$returnS (if ((HaveEL EL2)) then F else F)))`;
+
+
+(*val UsingAArch32 : unit -> M bool*)
+
+val _ = Define `
+ ((UsingAArch32:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   let (aarch32 : bool) = (w__0.ProcState_nRW = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if ((~ ((HaveAnyAArch32 () )))) then sail2_state_monad$assert_expS ((~ aarch32)) "!(aarch32)"
+    else sail2_state_monad$returnS () )
+   (if ((HighestELUsingAArch32 () )) then sail2_state_monad$assert_expS aarch32 "aarch32"
+    else sail2_state_monad$returnS () ))
+   (sail2_state_monad$returnS aarch32))))`;
+
+
+(*val aset_SPSR : mword ty32 -> M unit*)
+
+val _ = Define `
+ ((aset_SPSR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name=  (sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     let p__298 = (w__1.ProcState_M) in
+     let pat_0 = p__298 in
+     if (((pat_0 = M32_FIQ))) then sail2_state_monad$write_regS SPSR_fiq_ref value_name
+     else if (((pat_0 = M32_IRQ))) then sail2_state_monad$write_regS SPSR_irq_ref value_name
+     else if (((pat_0 = M32_Svc))) then sail2_state_monad$write_regS SPSR_svc_ref value_name
+     else if (((pat_0 = M32_Monitor))) then sail2_state_monad$write_regS SPSR_mon_ref value_name
+     else if (((pat_0 = M32_Abort))) then sail2_state_monad$write_regS SPSR_abt_ref value_name
+     else if (((pat_0 = M32_Hyp))) then sail2_state_monad$write_regS SPSR_hyp_ref value_name
+     else if (((pat_0 = M32_Undef))) then sail2_state_monad$write_regS SPSR_und_ref value_name
+     else Unreachable () )
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+     let p__297 = (w__2.ProcState_EL) in
+     let pat_0 = p__297 in
+     if (((pat_0 = EL1))) then sail2_state_monad$write_regS SPSR_EL1_ref value_name
+     else if (((pat_0 = EL2))) then sail2_state_monad$write_regS SPSR_EL2_ref value_name
+     else if (((pat_0 = EL3))) then sail2_state_monad$write_regS SPSR_EL3_ref value_name
+     else Unreachable () ))))`;
+
+
+(*val aget_SPSR : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((aget_SPSR:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (result : 32 bits) .  sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     let p__296 = (w__1.ProcState_M) in
+     let pat_0 = p__296 in
+     if (((pat_0 = M32_FIQ))) then (sail2_state_monad$read_regS SPSR_fiq_ref  : ( 32 words$word) M)
+     else if (((pat_0 = M32_IRQ))) then (sail2_state_monad$read_regS SPSR_irq_ref  : ( 32 words$word) M)
+     else if (((pat_0 = M32_Svc))) then (sail2_state_monad$read_regS SPSR_svc_ref  : ( 32 words$word) M)
+     else if (((pat_0 = M32_Monitor))) then (sail2_state_monad$read_regS SPSR_mon_ref  : ( 32 words$word) M)
+     else if (((pat_0 = M32_Abort))) then (sail2_state_monad$read_regS SPSR_abt_ref  : ( 32 words$word) M)
+     else if (((pat_0 = M32_Hyp))) then (sail2_state_monad$read_regS SPSR_hyp_ref  : ( 32 words$word) M)
+     else if (((pat_0 = M32_Undef))) then (sail2_state_monad$read_regS SPSR_und_ref  : ( 32 words$word) M)
+     else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . 
+     let p__295 = (w__9.ProcState_EL) in
+     let pat_0 = p__295 in
+     if (((pat_0 = EL1))) then (sail2_state_monad$read_regS SPSR_EL1_ref  : ( 32 words$word) M)
+     else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS SPSR_EL2_ref  : ( 32 words$word) M)
+     else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS SPSR_EL3_ref  : ( 32 words$word) M)
+     else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result))))))`;
+
+
+(*val IsSecure : unit -> M bool*)
+
+val _ = Define `
+ ((IsSecure:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL3)))))) (\ (w__3 :
+     bool) . 
+   if w__3 then sail2_state_monad$returnS T
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) ((UsingAArch32 () )))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+        sail2_state_monad$returnS (((w__6.ProcState_M = M32_Monitor)))))) (\ (w__7 : bool) . 
+     if w__7 then sail2_state_monad$returnS T
+     else IsSecureBelowEL3 () ))))`;
+
+
+(*val FPProcessException : FPExc -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((FPProcessException:FPExc ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception fpcr=  (sail2_state_monad$bindS
+   (undefined_int () ) (\ (cumul : ii) . 
+   let (cumul : ii) =
+     ((case exception of
+       FPExc_InvalidOp => (( 0 : int):ii)
+     | FPExc_DivideByZero => (( 1 : int):ii)
+     | FPExc_Overflow => (( 2 : int):ii)
+     | FPExc_Underflow => (( 3 : int):ii)
+     | FPExc_Inexact => (( 4 : int):ii)
+     | FPExc_InputDenorm => (( 7 : int):ii)
+     )) in
+   let (enable : ii) = (((ex_int cumul)) + (( 8 : int):ii)) in
+   if ((((vec_of_bits [access_vec_dec fpcr enable]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+     sail2_state_monad$throwS (Error_Implementation_Defined "floating-point trap handling")
+   else sail2_state_monad$bindS
+     (UsingAArch32 () ) (\ (w__0 : bool) . 
+     if w__0 then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS FPSCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+       sail2_state_monad$write_regS
+         FPSCR_ref
+         ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__1 cumul (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)))
+     else sail2_state_monad$bindS
+       (sail2_state_monad$read_regS FPSR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+       sail2_state_monad$write_regS
+         FPSR_ref
+         ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__2 cumul (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)))))))`;
+
+
+(*val FPRoundBase : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPRoundBase:int -> real ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr rounding=
+    (let p0_ = N__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS (((op <> (realFromFrac(( 0 : int))(( 10 : int)))))) ""))
+     (sail2_state_monad$assert_expS (((rounding <> FPRounding_TIEAWAY))) ""))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (F_mut : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (E_mut : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (minimum_exp : ii) . 
+     let minimum_exp = (~ (( 14 : int):ii)) in
+     let E_mut = ((( 5 : int):ii)) in
+     let F_mut = ((( 10 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (undefined_real () )) (\ (mantissa : real) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) . 
+     let ((mantissa : real), (sign : 1 bits)) =
+       (if ((op < (realFromFrac(( 0 : int))(( 10 : int))))) then
+         let (sign : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         let (mantissa : real) =((real_of_num 0) - op) in
+         (mantissa, sign)
+       else
+         let (sign : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         let (mantissa : real) = op in
+         (mantissa, sign)) in
+     let (exponent : ii) = ((( 0 : int):ii)) in
+     let ((exponent : ii), (mantissa : real)) =
+       (while (exponent, mantissa)
+         (\ varstup .  let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 : int))(( 10 : int))))
+         (\ varstup .  let (exponent, mantissa) = varstup in
+           let (mantissa : real) = (mantissa * (realFromFrac(( 20 : int))(( 10 : int)))) in
+           let (exponent : ii) = (((ex_int exponent)) - (( 1 : int):ii)) in
+           (exponent, mantissa))) in
+     let ((exponent : ii), (mantissa : real)) =
+       (while (exponent, mantissa)
+         (\ varstup .  let (exponent, mantissa) = varstup in mantissa >= (realFromFrac(( 20 : int))(( 10 : int))))
+         (\ varstup .  let (exponent, mantissa) = varstup in
+           let (mantissa : real) = (mantissa / (realFromFrac(( 20 : int))(( 10 : int)))) in
+           let (exponent : ii) = (((ex_int exponent)) + (( 1 : int):ii)) in
+           (exponent, mantissa))) in
+     if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ F))) \/ (((((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ T)))))) /\ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then sail2_state_monad$bindS
+       (UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (if w__0 then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS FPSCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+          sail2_state_monad$write_regS
+            FPSCR_ref
+            ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__1 (( 3 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)))
+        else sail2_state_monad$bindS
+          (sail2_state_monad$read_regS FPSR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+          sail2_state_monad$write_regS
+            FPSR_ref
+            ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__2 (( 3 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word))))
+       (FPZero (( 16 : int):ii) sign  : ( 'N words$word) M)) (\ (w__3 :  'N words$word) . 
+       sail2_state_monad$returnS ((words$w2w w__3  :  'N words$word))))
+     else
+       let (biased_exp : ii) =
+         (int_max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 : int):ii)))
+           (( 0 : int):ii)) in
+       let (mantissa : real) =
+         (if (((((ex_int biased_exp)) = (( 0 : int):ii)))) then
+           mantissa /
+             ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int)))
+                 ((((ex_int minimum_exp)) - ((ex_int exponent))))))
+         else mantissa) in
+       let (int_mant : ii) =
+         (flr ((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 10 : int):ii)))))) in
+       let (error : real) =
+         (((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 10 : int):ii))))) -
+           (((real_of_int int_mant)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+       (if ((((((((ex_int biased_exp)) = (( 0 : int):ii)))) /\ ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) \/ ((((vec_of_bits [access_vec_dec fpcr (( 11 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+          FPProcessException FPExc_Underflow fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$undefined_boolS () )) (\ (overflow_to_inf : bool) .  sail2_state_monad$bindS
+       (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . 
+       let ((overflow_to_inf : bool), (round_up : bool)) =
+         ((case rounding of
+           FPRounding_TIEEVEN =>
+            let (round_up : bool) =
+              (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii)  :  1 itself)) int_mant (( 0 : int):ii)
+                           :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))))))) in
+            let (overflow_to_inf : bool) = T in
+            (overflow_to_inf, round_up)
+         | FPRounding_POSINF =>
+            let (round_up : bool) =
+              ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B0]  :  1 words$word))))) in
+            let (overflow_to_inf : bool) = (sign = (vec_of_bits [B0]  :  1 words$word)) in
+            (overflow_to_inf, round_up)
+         | FPRounding_NEGINF =>
+            let (round_up : bool) =
+              ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B1]  :  1 words$word))))) in
+            let (overflow_to_inf : bool) = (sign = (vec_of_bits [B1]  :  1 words$word)) in
+            (overflow_to_inf, round_up)
+         | FPRounding_ZERO =>
+            let (round_up : bool) = F in
+            let (overflow_to_inf : bool) = F in
+            (overflow_to_inf, round_up)
+         | FPRounding_ODD =>
+            let (round_up : bool) = F in
+            let (overflow_to_inf : bool) = F in
+            (overflow_to_inf, round_up)
+         )) in
+       let ((biased_exp : ii), (int_mant : ii)) =
+         (if round_up then
+           let (int_mant : ii) = (((ex_int int_mant)) + (( 1 : int):ii)) in
+           let (biased_exp : ii) =
+             (if (((((ex_int int_mant)) = ((pow2 (( 10 : int):ii)))))) then (( 1 : int):ii)
+             else biased_exp) in
+           let ((biased_exp : ii), (int_mant : ii)) =
+             (if (((((ex_int int_mant)) = ((pow2 (( 11 : int):ii)))))) then
+               let (biased_exp : ii) = (((ex_int biased_exp)) + (( 1 : int):ii)) in
+               let (int_mant : ii) = (((ex_int int_mant)) / (( 2 : int):ii)) in
+               (biased_exp, int_mant)
+             else (biased_exp, int_mant)) in
+           (biased_exp, int_mant)
+         else (biased_exp, int_mant)) in
+       let (int_mant : ii) =
+         (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((rounding = FPRounding_ODD)))))) then
+           set_slice_int (( 1 : int):ii) int_mant (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+         else int_mant) in sail2_state_monad$bindS
+       (if (((F \/ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+          if ((((ex_int biased_exp)) >= ((((pow2 (( 5 : int):ii))) - (( 1 : int):ii))))) then sail2_state_monad$bindS
+            (if overflow_to_inf then (FPInfinity (( 16 : int):ii) sign  : ( 16 words$word) M)
+             else (FPMaxNormal (( 16 : int):ii) sign  : ( 16 words$word) M)) (\ (w__6 :  16 words$word) . 
+            let result = w__6 in sail2_state_monad$seqS
+            (FPProcessException FPExc_Overflow fpcr)
+            (let (error : real) = (realFromFrac(( 10 : int))(( 10 : int))) in
+            sail2_state_monad$returnS (error, result)))
+          else
+            let (result : 16 bits) =
+              ((concat_vec
+                 ((concat_vec sign
+                     ((GetSlice_int
+                         ((make_the_value (((((( 16 : int):ii) - (( 10 : int):ii))) - (( 1 : int):ii)))
+                            :  5 itself)) biased_exp (( 0 : int):ii)
+                        :  5 words$word))
+                    :  6 words$word))
+                 ((GetSlice_int ((make_the_value (( 10 : int):ii)  :  10 itself)) int_mant (( 0 : int):ii)
+                    :  10 words$word))
+                :  16 words$word)) in
+            sail2_state_monad$returnS (error, result)
+        else if ((((ex_int biased_exp)) >= ((pow2 (( 5 : int):ii))))) then
+          let result =
+            ((concat_vec sign
+               ((Ones__0 ((make_the_value (((( 16 : int):ii) - (( 1 : int):ii)))  :  15 itself))
+                  :  15 words$word))
+              :  16 words$word)) in sail2_state_monad$seqS
+          (FPProcessException FPExc_InvalidOp fpcr)
+          (let (error : real) = (realFromFrac(( 0 : int))(( 10 : int))) in
+          sail2_state_monad$returnS (error, result))
+        else
+          let (result : 16 bits) =
+            ((concat_vec
+               ((concat_vec sign
+                   ((GetSlice_int
+                       ((make_the_value (((((( 16 : int):ii) - (( 10 : int):ii))) - (( 1 : int):ii)))
+                          :  5 itself)) biased_exp (( 0 : int):ii)
+                      :  5 words$word))
+                  :  6 words$word))
+               ((GetSlice_int ((make_the_value (( 10 : int):ii)  :  10 itself)) int_mant (( 0 : int):ii)
+                  :  10 words$word))
+              :  16 words$word)) in
+          sail2_state_monad$returnS (error, result)) (\ varstup .  let ((error : real), (result : 16 bits)) = varstup in sail2_state_monad$seqS
+       (if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$returnS ((words$w2w result  :  'N words$word))))))))))))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS (((op <> (realFromFrac(( 0 : int))(( 10 : int)))))) ""))
+     (sail2_state_monad$assert_expS (((rounding <> FPRounding_TIEAWAY))) ""))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (F_mut : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (E_mut : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (minimum_exp : ii) . 
+     let minimum_exp = (~ (( 126 : int):ii)) in
+     let E_mut = ((( 8 : int):ii)) in
+     let F_mut = ((( 23 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (undefined_real () )) (\ (mantissa : real) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) . 
+     let ((mantissa : real), (sign : 1 bits)) =
+       (if ((op < (realFromFrac(( 0 : int))(( 10 : int))))) then
+         let (sign : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         let (mantissa : real) =((real_of_num 0) - op) in
+         (mantissa, sign)
+       else
+         let (sign : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         let (mantissa : real) = op in
+         (mantissa, sign)) in
+     let (exponent : ii) = ((( 0 : int):ii)) in
+     let ((exponent : ii), (mantissa : real)) =
+       (while (exponent, mantissa)
+         (\ varstup .  let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 : int))(( 10 : int))))
+         (\ varstup .  let (exponent, mantissa) = varstup in
+           let (mantissa : real) = (mantissa * (realFromFrac(( 20 : int))(( 10 : int)))) in
+           let (exponent : ii) = (((ex_int exponent)) - (( 1 : int):ii)) in
+           (exponent, mantissa))) in
+     let ((exponent : ii), (mantissa : real)) =
+       (while (exponent, mantissa)
+         (\ varstup .  let (exponent, mantissa) = varstup in mantissa >= (realFromFrac(( 20 : int))(( 10 : int))))
+         (\ varstup .  let (exponent, mantissa) = varstup in
+           let (mantissa : real) = (mantissa / (realFromFrac(( 20 : int))(( 10 : int)))) in
+           let (exponent : ii) = (((ex_int exponent)) + (( 1 : int):ii)) in
+           (exponent, mantissa))) in
+     if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ T))) \/ (((((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ F)))))) /\ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then sail2_state_monad$bindS
+       (UsingAArch32 () ) (\ (w__8 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (if w__8 then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS FPSCR_ref  : ( 32 words$word) M) (\ (w__9 :  32 words$word) . 
+          sail2_state_monad$write_regS
+            FPSCR_ref
+            ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__9 (( 3 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)))
+        else sail2_state_monad$bindS
+          (sail2_state_monad$read_regS FPSR_ref  : ( 32 words$word) M) (\ (w__10 :  32 words$word) . 
+          sail2_state_monad$write_regS
+            FPSR_ref
+            ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__10 (( 3 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word))))
+       (FPZero (( 32 : int):ii) sign  : ( 'N words$word) M)) (\ (w__11 :  'N words$word) . 
+       sail2_state_monad$returnS ((words$w2w w__11  :  'N words$word))))
+     else
+       let (biased_exp : ii) =
+         (int_max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 : int):ii)))
+           (( 0 : int):ii)) in
+       let (mantissa : real) =
+         (if (((((ex_int biased_exp)) = (( 0 : int):ii)))) then
+           mantissa /
+             ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int)))
+                 ((((ex_int minimum_exp)) - ((ex_int exponent))))))
+         else mantissa) in
+       let (int_mant : ii) =
+         (flr ((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 23 : int):ii)))))) in
+       let (error : real) =
+         (((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 23 : int):ii))))) -
+           (((real_of_int int_mant)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+       (if ((((((((ex_int biased_exp)) = (( 0 : int):ii)))) /\ ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) \/ ((((vec_of_bits [access_vec_dec fpcr (( 11 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+          FPProcessException FPExc_Underflow fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$undefined_boolS () )) (\ (overflow_to_inf : bool) .  sail2_state_monad$bindS
+       (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . 
+       let ((overflow_to_inf : bool), (round_up : bool)) =
+         ((case rounding of
+           FPRounding_TIEEVEN =>
+            let (round_up : bool) =
+              (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii)  :  1 itself)) int_mant (( 0 : int):ii)
+                           :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))))))) in
+            let (overflow_to_inf : bool) = T in
+            (overflow_to_inf, round_up)
+         | FPRounding_POSINF =>
+            let (round_up : bool) =
+              ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B0]  :  1 words$word))))) in
+            let (overflow_to_inf : bool) = (sign = (vec_of_bits [B0]  :  1 words$word)) in
+            (overflow_to_inf, round_up)
+         | FPRounding_NEGINF =>
+            let (round_up : bool) =
+              ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B1]  :  1 words$word))))) in
+            let (overflow_to_inf : bool) = (sign = (vec_of_bits [B1]  :  1 words$word)) in
+            (overflow_to_inf, round_up)
+         | FPRounding_ZERO =>
+            let (round_up : bool) = F in
+            let (overflow_to_inf : bool) = F in
+            (overflow_to_inf, round_up)
+         | FPRounding_ODD =>
+            let (round_up : bool) = F in
+            let (overflow_to_inf : bool) = F in
+            (overflow_to_inf, round_up)
+         )) in
+       let ((biased_exp : ii), (int_mant : ii)) =
+         (if round_up then
+           let (int_mant : ii) = (((ex_int int_mant)) + (( 1 : int):ii)) in
+           let (biased_exp : ii) =
+             (if (((((ex_int int_mant)) = ((pow2 (( 23 : int):ii)))))) then (( 1 : int):ii)
+             else biased_exp) in
+           let ((biased_exp : ii), (int_mant : ii)) =
+             (if (((((ex_int int_mant)) = ((pow2 (( 24 : int):ii)))))) then
+               let (biased_exp : ii) = (((ex_int biased_exp)) + (( 1 : int):ii)) in
+               let (int_mant : ii) = (((ex_int int_mant)) / (( 2 : int):ii)) in
+               (biased_exp, int_mant)
+             else (biased_exp, int_mant)) in
+           (biased_exp, int_mant)
+         else (biased_exp, int_mant)) in
+       let (int_mant : ii) =
+         (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((rounding = FPRounding_ODD)))))) then
+           set_slice_int (( 1 : int):ii) int_mant (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+         else int_mant) in sail2_state_monad$bindS
+       (if ((((ex_int biased_exp)) >= ((((pow2 (( 8 : int):ii))) - (( 1 : int):ii))))) then sail2_state_monad$bindS
+          (if overflow_to_inf then (FPInfinity (( 32 : int):ii) sign  : ( 32 words$word) M)
+           else (FPMaxNormal (( 32 : int):ii) sign  : ( 32 words$word) M)) (\ (w__14 :  32 words$word) . 
+          let result = w__14 in sail2_state_monad$seqS
+          (FPProcessException FPExc_Overflow fpcr)
+          (let (error : real) = (realFromFrac(( 10 : int))(( 10 : int))) in
+          sail2_state_monad$returnS (error, result)))
+        else
+          let (result : 32 bits) =
+            ((concat_vec
+               ((concat_vec sign
+                   ((GetSlice_int
+                       ((make_the_value (((((( 32 : int):ii) - (( 23 : int):ii))) - (( 1 : int):ii)))
+                          :  8 itself)) biased_exp (( 0 : int):ii)
+                      :  8 words$word))
+                  :  9 words$word))
+               ((GetSlice_int ((make_the_value (( 23 : int):ii)  :  23 itself)) int_mant (( 0 : int):ii)
+                  :  23 words$word))
+              :  32 words$word)) in
+          sail2_state_monad$returnS (error, result)) (\ varstup .  let ((error : real), (result : 32 bits)) = varstup in sail2_state_monad$seqS
+       (if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$returnS ((words$w2w result  :  'N words$word))))))))))))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS (((op <> (realFromFrac(( 0 : int))(( 10 : int)))))) ""))
+     (sail2_state_monad$assert_expS (((rounding <> FPRounding_TIEAWAY))) ""))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (F_mut : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (E_mut : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (minimum_exp : ii) . 
+     let minimum_exp = (~ (( 1022 : int):ii)) in
+     let E_mut = ((( 11 : int):ii)) in
+     let F_mut = ((( 52 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (undefined_real () )) (\ (mantissa : real) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) . 
+     let ((mantissa : real), (sign : 1 bits)) =
+       (if ((op < (realFromFrac(( 0 : int))(( 10 : int))))) then
+         let (sign : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+         let (mantissa : real) =((real_of_num 0) - op) in
+         (mantissa, sign)
+       else
+         let (sign : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+         let (mantissa : real) = op in
+         (mantissa, sign)) in
+     let (exponent : ii) = ((( 0 : int):ii)) in
+     let ((exponent : ii), (mantissa : real)) =
+       (while (exponent, mantissa)
+         (\ varstup .  let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 : int))(( 10 : int))))
+         (\ varstup .  let (exponent, mantissa) = varstup in
+           let (mantissa : real) = (mantissa * (realFromFrac(( 20 : int))(( 10 : int)))) in
+           let (exponent : ii) = (((ex_int exponent)) - (( 1 : int):ii)) in
+           (exponent, mantissa))) in
+     let ((exponent : ii), (mantissa : real)) =
+       (while (exponent, mantissa)
+         (\ varstup .  let (exponent, mantissa) = varstup in mantissa >= (realFromFrac(( 20 : int))(( 10 : int))))
+         (\ varstup .  let (exponent, mantissa) = varstup in
+           let (mantissa : real) = (mantissa / (realFromFrac(( 20 : int))(( 10 : int)))) in
+           let (exponent : ii) = (((ex_int exponent)) + (( 1 : int):ii)) in
+           (exponent, mantissa))) in
+     if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ T))) \/ (((((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ F)))))) /\ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then sail2_state_monad$bindS
+       (UsingAArch32 () ) (\ (w__16 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (if w__16 then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS FPSCR_ref  : ( 32 words$word) M) (\ (w__17 :  32 words$word) . 
+          sail2_state_monad$write_regS
+            FPSCR_ref
+            ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__17 (( 3 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)))
+        else sail2_state_monad$bindS
+          (sail2_state_monad$read_regS FPSR_ref  : ( 32 words$word) M) (\ (w__18 :  32 words$word) . 
+          sail2_state_monad$write_regS
+            FPSR_ref
+            ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__18 (( 3 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word))))
+       (FPZero (( 64 : int):ii) sign  : ( 'N words$word) M)) (\ (w__19 :  'N words$word) . 
+       sail2_state_monad$returnS ((words$w2w w__19  :  'N words$word))))
+     else
+       let (biased_exp : ii) =
+         (int_max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 : int):ii)))
+           (( 0 : int):ii)) in
+       let (mantissa : real) =
+         (if (((((ex_int biased_exp)) = (( 0 : int):ii)))) then
+           mantissa /
+             ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int)))
+                 ((((ex_int minimum_exp)) - ((ex_int exponent))))))
+         else mantissa) in
+       let (int_mant : ii) =
+         (flr ((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 52 : int):ii)))))) in
+       let (error : real) =
+         (((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 52 : int):ii))))) -
+           (((real_of_int int_mant)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+       (if ((((((((ex_int biased_exp)) = (( 0 : int):ii)))) /\ ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) \/ ((((vec_of_bits [access_vec_dec fpcr (( 11 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+          FPProcessException FPExc_Underflow fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$undefined_boolS () )) (\ (overflow_to_inf : bool) .  sail2_state_monad$bindS
+       (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . 
+       let ((overflow_to_inf : bool), (round_up : bool)) =
+         ((case rounding of
+           FPRounding_TIEEVEN =>
+            let (round_up : bool) =
+              (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii)  :  1 itself)) int_mant (( 0 : int):ii)
+                           :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))))))) in
+            let (overflow_to_inf : bool) = T in
+            (overflow_to_inf, round_up)
+         | FPRounding_POSINF =>
+            let (round_up : bool) =
+              ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B0]  :  1 words$word))))) in
+            let (overflow_to_inf : bool) = (sign = (vec_of_bits [B0]  :  1 words$word)) in
+            (overflow_to_inf, round_up)
+         | FPRounding_NEGINF =>
+            let (round_up : bool) =
+              ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B1]  :  1 words$word))))) in
+            let (overflow_to_inf : bool) = (sign = (vec_of_bits [B1]  :  1 words$word)) in
+            (overflow_to_inf, round_up)
+         | FPRounding_ZERO =>
+            let (round_up : bool) = F in
+            let (overflow_to_inf : bool) = F in
+            (overflow_to_inf, round_up)
+         | FPRounding_ODD =>
+            let (round_up : bool) = F in
+            let (overflow_to_inf : bool) = F in
+            (overflow_to_inf, round_up)
+         )) in
+       let ((biased_exp : ii), (int_mant : ii)) =
+         (if round_up then
+           let (int_mant : ii) = (((ex_int int_mant)) + (( 1 : int):ii)) in
+           let (biased_exp : ii) =
+             (if (((((ex_int int_mant)) = ((pow2 (( 52 : int):ii)))))) then (( 1 : int):ii)
+             else biased_exp) in
+           let ((biased_exp : ii), (int_mant : ii)) =
+             (if (((((ex_int int_mant)) = ((pow2 (( 53 : int):ii)))))) then
+               let (biased_exp : ii) = (((ex_int biased_exp)) + (( 1 : int):ii)) in
+               let (int_mant : ii) = (((ex_int int_mant)) / (( 2 : int):ii)) in
+               (biased_exp, int_mant)
+             else (biased_exp, int_mant)) in
+           (biased_exp, int_mant)
+         else (biased_exp, int_mant)) in
+       let (int_mant : ii) =
+         (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((rounding = FPRounding_ODD)))))) then
+           set_slice_int (( 1 : int):ii) int_mant (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+         else int_mant) in sail2_state_monad$bindS
+       (if ((((ex_int biased_exp)) >= ((((pow2 (( 11 : int):ii))) - (( 1 : int):ii))))) then sail2_state_monad$bindS
+          (if overflow_to_inf then (FPInfinity (( 64 : int):ii) sign  : ( 64 words$word) M)
+           else (FPMaxNormal (( 64 : int):ii) sign  : ( 64 words$word) M)) (\ (w__22 :  64 words$word) . 
+          let result = w__22 in sail2_state_monad$seqS
+          (FPProcessException FPExc_Overflow fpcr)
+          (let (error : real) = (realFromFrac(( 10 : int))(( 10 : int))) in
+          sail2_state_monad$returnS (error, result)))
+        else
+          let (result : 64 bits) =
+            ((concat_vec
+               ((concat_vec sign
+                   ((GetSlice_int
+                       ((make_the_value (((((( 64 : int):ii) - (( 52 : int):ii))) - (( 1 : int):ii)))
+                          :  11 itself)) biased_exp (( 0 : int):ii)
+                      :  11 words$word))
+                  :  12 words$word))
+               ((GetSlice_int ((make_the_value (( 52 : int):ii)  :  52 itself)) int_mant (( 0 : int):ii)
+                  :  52 words$word))
+              :  64 words$word)) in
+          sail2_state_monad$returnS (error, result)) (\ varstup .  let ((error : real), (result : 64 bits)) = varstup in sail2_state_monad$seqS
+       (if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$returnS ((words$w2w result  :  'N words$word))))))))))))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "") (sail2_state_monad$exitS () )))`;
+
+
+(*val FPRoundCV : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPRoundCV:int -> real ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr__arg rounding=
+    (let fpcr = fpcr__arg in
+   let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 19 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)) in
+   (FPRoundBase N__tv op fpcr rounding  : ( 'N words$word) M)))`;
+
+
+(*val FPRound__0 : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*)
+
+(*val FPRound__1 : forall 'N . Size 'N => integer -> real -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPRound__0:int -> real ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr__arg rounding=
+    (let fpcr = fpcr__arg in
+   let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 26 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)) in
+   (FPRoundBase N__tv op fpcr rounding  : ( 'N words$word) M)))`;
+
+
+val _ = Define `
+ ((FPRound__1:int -> real ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr=
+    ((FPRound__0 N__tv op fpcr ((FPRoundingMode fpcr))  : ( 'N words$word) M)))`;
+
+
+(*val FixedToFP : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> ii -> bool -> mword ty32 -> FPRounding -> M (mword 'N)*)
+
+val _ = Define `
+ ((FixedToFP:int -> 'M words$word -> int -> bool ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fbits unsigned fpcr rounding=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((N__tv = (( 16 : int):ii)))) \/ ((((((N__tv = (( 32 : int):ii)))) \/ (((N__tv = (( 64 : int):ii)))))))))) "")
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) ""))
+   (undefined_bitvector N__tv  : ( 'N words$word) M)) (\ (result : 'N bits) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((fbits >= (( 0 : int):ii))) "")
+   (sail2_state_monad$assert_expS (((rounding <> FPRounding_ODD))) ""))
+   (let (int_operand : ii) = (asl_Int op unsigned) in
+   let (real_operand : real) =
+     ((((real_of_int int_operand))) / ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) fbits))) in
+   if (((real_operand = (realFromFrac(( 0 : int))(( 10 : int)))))) then
+     (FPZero ((int_of_num (words$word_len result))) (vec_of_bits [B0]  :  1 words$word)  : ( 'N words$word) M)
+   else (FPRound__0 ((int_of_num (words$word_len result))) real_operand fpcr rounding  : ( 'N words$word) M)))))`;
+
+
+(*val FPProcessNaN : forall 'N . Size 'N => FPType -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPProcessNaN:FPType -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ op fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (sail2_state_monad$assert_expS ((((((typ = FPType_QNaN))) \/ (((typ = FPType_SNaN)))))) "((type == FPType_QNaN) || (type == FPType_SNaN))"))
+   (undefined_int () )) (\ (topfrac : ii) . 
+   let p0_ = (int_of_num (words$word_len op)) in
+   let (topfrac : ii) =
+     (if (((p0_ = (( 16 : int):ii)))) then
+       let (op :  16 words$word) = ((words$w2w op  :  16 words$word)) in
+       (( 9 : int):ii)
+     else if (((p0_ = (( 32 : int):ii)))) then
+       let (op :  32 words$word) = ((words$w2w op  :  32 words$word)) in
+       (( 22 : int):ii)
+     else
+       let (op :  64 words$word) = ((words$w2w op  :  64 words$word)) in
+       (( 51 : int):ii)) in
+   let (result : 'N bits) = op in sail2_state_monad$bindS
+   (if (((typ = FPType_SNaN))) then
+      let result =
+        ((set_slice ((int_of_num (words$word_len op))) (( 1 : int):ii) result topfrac (vec_of_bits [B1]  :  1 words$word)  :  'N words$word)) in sail2_state_monad$seqS
+      (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)
+    else sail2_state_monad$returnS result) (\ (result : 'N bits) . 
+   if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+     (FPDefaultNaN ((int_of_num (words$word_len op))) ()   : ( 'N words$word) M)
+   else sail2_state_monad$returnS result))))`;
+
+
+(*val FPProcessNaNs3 : forall 'N . Size 'N => FPType -> FPType -> FPType -> mword 'N -> mword 'N -> mword 'N -> mword ty32 -> M (bool * mword 'N)*)
+
+val _ = Define `
+ ((FPProcessNaNs3:FPType -> FPType -> FPType -> 'N words$word -> 'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#'N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) type1 type2 type3 op1 op2 op3 fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M)) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . 
+   if (((type1 = FPType_SNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type1 op1 fpcr  : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+     let (result : 'N bits) = w__0 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type2 = FPType_SNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type2 op2 fpcr  : ( 'N words$word) M) (\ (w__1 : 'N bits) . 
+     let (result : 'N bits) = w__1 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type3 = FPType_SNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type3 op3 fpcr  : ( 'N words$word) M) (\ (w__2 : 'N bits) . 
+     let (result : 'N bits) = w__2 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type1 = FPType_QNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type1 op1 fpcr  : ( 'N words$word) M) (\ (w__3 : 'N bits) . 
+     let (result : 'N bits) = w__3 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type2 = FPType_QNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type2 op2 fpcr  : ( 'N words$word) M) (\ (w__4 : 'N bits) . 
+     let (result : 'N bits) = w__4 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type3 = FPType_QNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type3 op3 fpcr  : ( 'N words$word) M) (\ (w__5 : 'N bits) . 
+     let (result : 'N bits) = w__5 in
+     sail2_state_monad$returnS (done, result))
+   else
+     let (done : bool) = F in
+     let (result : 'N bits) = ((Zeros__1 ((int_of_num (words$word_len op1))) ()   :  'N words$word)) in
+     sail2_state_monad$returnS (done, result)))))`;
+
+
+(*val FPProcessNaNs : forall 'N . Size 'N => FPType -> FPType -> mword 'N -> mword 'N -> mword ty32 -> M (bool * mword 'N)*)
+
+val _ = Define `
+ ((FPProcessNaNs:FPType -> FPType -> 'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#'N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) type1 type2 op1 op2 fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M)) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . 
+   if (((type1 = FPType_SNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type1 op1 fpcr  : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+     let (result : 'N bits) = w__0 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type2 = FPType_SNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type2 op2 fpcr  : ( 'N words$word) M) (\ (w__1 : 'N bits) . 
+     let (result : 'N bits) = w__1 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type1 = FPType_QNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type1 op1 fpcr  : ( 'N words$word) M) (\ (w__2 : 'N bits) . 
+     let (result : 'N bits) = w__2 in
+     sail2_state_monad$returnS (done, result))
+   else if (((type2 = FPType_QNaN))) then
+     let done = T in sail2_state_monad$bindS
+     (FPProcessNaN type2 op2 fpcr  : ( 'N words$word) M) (\ (w__3 : 'N bits) . 
+     let (result : 'N bits) = w__3 in
+     sail2_state_monad$returnS (done, result))
+   else
+     let (done : bool) = F in
+     let (result : 'N bits) = ((Zeros__1 ((int_of_num (words$word_len op1))) ()   :  'N words$word)) in
+     sail2_state_monad$returnS (done, result)))))`;
+
+
+(*val CurrentInstrSet : unit -> M InstrSet*)
+
+val _ = Define `
+ ((CurrentInstrSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((InstrSet),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_InstrSet () ) (\ (result : InstrSet) .  sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     let (result : InstrSet) =
+       (if (((w__1.ProcState_T = (vec_of_bits [B0]  :  1 words$word)))) then InstrSet_A32
+       else InstrSet_T32) in
+     sail2_state_monad$returnS result)
+   else sail2_state_monad$returnS InstrSet_A64))))`;
+
+
+(*val AArch32_ExecutingLSMInstr : unit -> M bool*)
+
+val _ = Define `
+ ((AArch32_ExecutingLSMInstr:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (ThisInstr0 ()   : ( 32 words$word) M) (\ (instr : 32 bits) .  sail2_state_monad$bindS
+   (CurrentInstrSet () ) (\ (instr_set : InstrSet) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((instr_set = InstrSet_A32))) \/ (((instr_set = InstrSet_T32)))))) "((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))")
+   (if (((instr_set = InstrSet_A32))) then
+     sail2_state_monad$returnS ((((((((slice instr (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word)) <> (vec_of_bits [B1;B1;B1;B1]  :  4 words$word)))) /\ (((((slice instr (( 25 : int):ii) (( 3 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))))))
+   else sail2_state_monad$bindS
+     (ThisInstrLength () ) (\ (w__0 : ii) . 
+     sail2_state_monad$returnS (if (((((ex_int w__0)) = (( 16 : int):ii)))) then
+               (((slice instr (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B1;B0;B0]  :  4 words$word))
+             else
+               ((((((slice instr (( 25 : int):ii) (( 7 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0;B0]  :  7 words$word)))) /\ ((((vec_of_bits [access_vec_dec instr (( 22 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))))))))`;
+
+
+(*val AArch32_ExecutingCP10or11Instr : unit -> M bool*)
+
+val _ = Define `
+ ((AArch32_ExecutingCP10or11Instr:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (ThisInstr0 ()   : ( 32 words$word) M) (\ (instr : 32 bits) .  sail2_state_monad$bindS
+   (CurrentInstrSet () ) (\ (instr_set : InstrSet) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((instr_set = InstrSet_A32))) \/ (((instr_set = InstrSet_T32)))))) "((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))")
+   (sail2_state_monad$returnS (if (((instr_set = InstrSet_A32))) then
+             (((((((((slice instr (( 24 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)))) \/ (((((slice instr (( 25 : int):ii) (( 3 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) /\ (((((and_vec ((slice instr (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                       (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+                      :  4 words$word)) = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))))
+           else
+             (((((((((and_vec ((slice instr (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                           (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+                          :  4 words$word)) = (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)))) /\ ((((((((slice instr (( 24 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)))) \/ (((((slice instr (( 25 : int):ii) (( 3 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))))))))) /\ (((((and_vec ((slice instr (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                       (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+                      :  4 words$word)) = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))))))))))`;
+
+
+(*val HaveAnyAArch64 : unit -> bool*)
+
+val _ = Define `
+ ((HaveAnyAArch64:unit -> bool) () =  (~ ((HighestELUsingAArch32 () ))))`;
+
+
+(*val AArch32_ReportDeferredSError : mword ty2 -> mword ty1 -> M (mword ty32)*)
+
+val _ = Define `
+ ((AArch32_ReportDeferredSError:(2)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) AET ExT=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (target : 32 bits) . 
+   let (target : 32 bits) =
+     ((set_slice (( 32 : int):ii) (( 1 : int):ii) target (( 31 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)) in
+   let (syndrome : 16 bits) = ((Zeros__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS
+   (if (((w__0.ProcState_EL = EL2))) then
+      let (syndrome : 16 bits) =
+        ((update_subrange_vec_dec syndrome (( 11 : int):ii) (( 10 : int):ii) AET  :  16 words$word)) in
+      let (syndrome : 16 bits) =
+        ((update_subrange_vec_dec syndrome (( 9 : int):ii) (( 9 : int):ii) ExT  :  16 words$word)) in
+      let (syndrome : 16 bits) =
+        ((update_subrange_vec_dec syndrome (( 5 : int):ii) (( 0 : int):ii)
+           (vec_of_bits [B0;B1;B0;B0;B0;B1]  :  6 words$word)
+          :  16 words$word)) in
+      sail2_state_monad$returnS syndrome
+    else
+      let syndrome = ((update_subrange_vec_dec syndrome (( 15 : int):ii) (( 14 : int):ii) AET  :  16 words$word)) in
+      let syndrome = ((update_subrange_vec_dec syndrome (( 12 : int):ii) (( 12 : int):ii) ExT  :  16 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS TTBCR_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      let syndrome =
+        ((update_subrange_vec_dec syndrome (( 9 : int):ii) (( 9 : int):ii)
+           (vec_of_bits [access_vec_dec w__1 (( 31 : int):ii)]  :  1 words$word)
+          :  16 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS TTBCR_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+      let (syndrome : 16 bits) =
+        (if ((((vec_of_bits [access_vec_dec w__2 (( 31 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+          (update_subrange_vec_dec syndrome (( 5 : int):ii) (( 0 : int):ii)
+             (vec_of_bits [B0;B1;B0;B0;B0;B1]  :  6 words$word)
+            :  16 words$word)
+        else
+          let (tup__0, tup__1) =
+            ((vec_of_bits [B1]  :  1 words$word), (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)) in
+          let (syndrome : 16 bits) =
+            ((update_subrange_vec_dec syndrome (( 10 : int):ii) (( 10 : int):ii) tup__0  :  16 words$word)) in
+          (update_subrange_vec_dec syndrome (( 3 : int):ii) (( 0 : int):ii) tup__1  :  16 words$word)) in
+      sail2_state_monad$returnS syndrome))) (\ (syndrome : 16 bits) . 
+   if ((HaveAnyAArch64 () )) then sail2_state_monad$bindS
+     (ZeroExtend__0 syndrome ((make_the_value (( 25 : int):ii)  :  25 itself))  : ( 25 words$word) M) (\ (w__3 :
+        25 words$word) . 
+     let (target : 32 bits) = ((update_subrange_vec_dec target (( 24 : int):ii) (( 0 : int):ii) w__3  :  32 words$word)) in
+     sail2_state_monad$returnS target)
+   else
+     let (target : 32 bits) =
+       ((update_subrange_vec_dec target (( 15 : int):ii) (( 0 : int):ii) syndrome  :  32 words$word)) in
+     sail2_state_monad$returnS target)))))`;
+
+
+(*val HaveAArch32EL : mword ty2 -> bool*)
+
+val _ = Define `
+ ((HaveAArch32EL:(2)words$word -> bool) el=
+    (if ((~ ((HaveEL el)))) then F
+   else if ((~ ((HaveAnyAArch32 () )))) then F
+   else if ((HighestELUsingAArch32 () )) then T
+   else if (((el = ((HighestEL ()   :  2 words$word))))) then F
+   else if (((el = EL0))) then T
+   else T))`;
+
+
+(*val AArch64_ResetSpecialRegisters : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_ResetSpecialRegisters:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_EL0_ref w__0)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_EL1_ref w__1)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__2 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_EL1_ref w__2)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__3 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ELR_EL1_ref w__3)
+   (if ((HaveEL EL2)) then sail2_state_monad$bindS
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__4 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SP_EL2_ref w__4)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__5 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SPSR_EL2_ref w__5)
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__6 : 64 bits) . 
+      sail2_state_monad$write_regS ELR_EL2_ref w__6)))
+    else sail2_state_monad$returnS () ))
+   (if ((HaveEL EL3)) then sail2_state_monad$bindS
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__7 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SP_EL3_ref w__7)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__8 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SPSR_EL3_ref w__8)
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__9 : 64 bits) . 
+      sail2_state_monad$write_regS ELR_EL3_ref w__9)))
+    else sail2_state_monad$returnS () ))
+   (if ((HaveAArch32EL EL1)) then sail2_state_monad$bindS
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__10 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SPSR_fiq_ref w__10)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__11 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SPSR_irq_ref w__11)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__12 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS SPSR_abt_ref w__12)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__13 : 32 bits) . 
+      sail2_state_monad$write_regS SPSR_und_ref w__13))))
+    else sail2_state_monad$returnS () ))
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__14 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DLR_EL0_ref w__14)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__15 : 32 bits) . 
+   sail2_state_monad$write_regS DSPSR_EL0_ref w__15))))))))`;
+
+
+(*val Halted : unit -> M bool*)
+
+val _ = Define `
+ ((Halted:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+      sail2_state_monad$returnS (((((slice w__0 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS (((((slice w__1 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word))))))) (\ (w__2 : bool) . 
+   sail2_state_monad$returnS ((~ w__2)))))`;
+
+
+(*val FPUnpackBase : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*)
+
+val _ = Define `
+ ((FPUnpackBase:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((FPType#(1)words$word#real),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fpval fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len fpval))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len fpval))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len fpval))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M)) (\ (frac64 : 52 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 11 : int):ii)  : ( 11 words$word) M) (\ (exp64 : 11 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 23 : int):ii)  : ( 23 words$word) M) (\ (frac32 : 23 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (exp32 : 8 bits) .  sail2_state_monad$bindS
+   (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 10 : int):ii)  : ( 10 words$word) M) (\ (frac16 : 10 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 5 : int):ii)  : ( 5 words$word) M) (\ (exp16 : 5 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (if (((((int_of_num (words$word_len fpval))) = (( 16 : int):ii)))) then
+      let (sign : 1 bits) = ((vec_of_bits [access_vec_dec fpval (( 15 : int):ii)]  :  1 words$word)) in
+      let (exp16 : 5 bits) = ((slice fpval (( 10 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+      let (frac16 : 10 bits) = ((slice fpval (( 0 : int):ii) (( 10 : int):ii)  :  10 words$word)) in
+      let ((typ : FPType), (value_name : real)) =
+        (if ((IsZero exp16)) then
+          let ((typ : FPType), (value_name : real)) =
+            (if (((((IsZero frac16)) \/ ((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+              let (typ : FPType) = FPType_Zero in
+              let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in
+              (typ, value_name)
+            else
+              let (typ : FPType) = FPType_Nonzero in
+              let (value_name : real) =
+                (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 14 : int):ii))))) *
+                  (((((real_of_int ((lem$w2ui frac16))))) *
+                      ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 10 : int):ii)))))))) in
+              (typ, value_name)) in
+          (typ, value_name)
+        else
+          let ((typ : FPType), (value_name : real)) =
+            (if (((((IsOnes exp16)) /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+              let ((typ : FPType), (value_name : real)) =
+                (if ((IsZero frac16)) then
+                  let (typ : FPType) = FPType_Infinity in
+                  let (value_name : real) = (realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 1000000 : int):ii)) in
+                  (typ, value_name)
+                else
+                  let (typ : FPType) =
+                    (if ((((vec_of_bits [access_vec_dec frac16 (( 9 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+                      FPType_QNaN
+                    else FPType_SNaN) in
+                  let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in
+                  (typ, value_name)) in
+              (typ, value_name)
+            else
+              let (typ : FPType) = FPType_Nonzero in
+              let (value_name : real) =
+                (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((((lem$w2ui exp16)) - (( 15 : int):ii)))))
+                  *
+                  (((realFromFrac(( 10 : int))(( 10 : int))) +
+                      (((((real_of_int ((lem$w2ui frac16))))) *
+                          ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 10 : int):ii)))))))))) in
+              (typ, value_name)) in
+          (typ, value_name)) in
+      sail2_state_monad$returnS (sign, typ, value_name)
+    else if (((((int_of_num (words$word_len fpval))) = (( 32 : int):ii)))) then
+      let sign = ((vec_of_bits [access_vec_dec fpval (( 31 : int):ii)]  :  1 words$word)) in
+      let exp32 = ((slice fpval (( 23 : int):ii) (( 8 : int):ii)  :  8 words$word)) in
+      let frac32 = ((slice fpval (( 0 : int):ii) (( 23 : int):ii)  :  23 words$word)) in sail2_state_monad$bindS
+      (if ((IsZero exp32)) then
+         if (((((IsZero frac32)) \/ ((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+           let typ = FPType_Zero in
+           let value_name = (realFromFrac(( 0 : int))(( 10 : int))) in sail2_state_monad$seqS
+           (if ((~ ((IsZero frac32)))) then FPProcessException FPExc_InputDenorm fpcr
+            else sail2_state_monad$returnS () )
+           (sail2_state_monad$returnS (typ, value_name))
+         else
+           let (typ : FPType) = FPType_Nonzero in
+           let (value_name : real) =
+             (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 126 : int):ii))))) *
+               (((((real_of_int ((lem$w2ui frac32))))) *
+                   ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 23 : int):ii)))))))) in
+           sail2_state_monad$returnS (typ, value_name)
+       else
+         let ((typ : FPType), (value_name : real)) =
+           (if ((IsOnes exp32)) then
+             let ((typ : FPType), (value_name : real)) =
+               (if ((IsZero frac32)) then
+                 let (typ : FPType) = FPType_Infinity in
+                 let (value_name : real) = (realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 1000000 : int):ii)) in
+                 (typ, value_name)
+               else
+                 let (typ : FPType) =
+                   (if ((((vec_of_bits [access_vec_dec frac32 (( 22 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+                     FPType_QNaN
+                   else FPType_SNaN) in
+                 let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in
+                 (typ, value_name)) in
+             (typ, value_name)
+           else
+             let (typ : FPType) = FPType_Nonzero in
+             let (value_name : real) =
+               (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((((lem$w2ui exp32)) - (( 127 : int):ii)))))
+                 *
+                 (((realFromFrac(( 10 : int))(( 10 : int))) +
+                     (((((real_of_int ((lem$w2ui frac32))))) *
+                         ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 23 : int):ii)))))))))) in
+             (typ, value_name)) in
+         sail2_state_monad$returnS (typ, value_name)) (\ varstup .  let ((typ : FPType), (value_name : real)) = varstup in
+      sail2_state_monad$returnS (sign, typ, value_name))
+    else
+      let sign = ((vec_of_bits [access_vec_dec fpval (( 63 : int):ii)]  :  1 words$word)) in
+      let exp64 = ((slice fpval (( 52 : int):ii) (( 11 : int):ii)  :  11 words$word)) in
+      let frac64 = ((slice fpval (( 0 : int):ii) (( 52 : int):ii)  :  52 words$word)) in sail2_state_monad$bindS
+      (if ((IsZero exp64)) then
+         if (((((IsZero frac64)) \/ ((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+           let typ = FPType_Zero in
+           let value_name = (realFromFrac(( 0 : int))(( 10 : int))) in sail2_state_monad$seqS
+           (if ((~ ((IsZero frac64)))) then FPProcessException FPExc_InputDenorm fpcr
+            else sail2_state_monad$returnS () )
+           (sail2_state_monad$returnS (typ, value_name))
+         else
+           let (typ : FPType) = FPType_Nonzero in
+           let (value_name : real) =
+             (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 1022 : int):ii))))) *
+               (((((real_of_int ((lem$w2ui frac64))))) *
+                   ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 52 : int):ii)))))))) in
+           sail2_state_monad$returnS (typ, value_name)
+       else
+         let ((typ : FPType), (value_name : real)) =
+           (if ((IsOnes exp64)) then
+             let ((typ : FPType), (value_name : real)) =
+               (if ((IsZero frac64)) then
+                 let (typ : FPType) = FPType_Infinity in
+                 let (value_name : real) = (realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 1000000 : int):ii)) in
+                 (typ, value_name)
+               else
+                 let (typ : FPType) =
+                   (if ((((vec_of_bits [access_vec_dec frac64 (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+                     FPType_QNaN
+                   else FPType_SNaN) in
+                 let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in
+                 (typ, value_name)) in
+             (typ, value_name)
+           else
+             let (typ : FPType) = FPType_Nonzero in
+             let (value_name : real) =
+               (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((((lem$w2ui exp64)) - (( 1023 : int):ii)))))
+                 *
+                 (((realFromFrac(( 10 : int))(( 10 : int))) +
+                     (((((real_of_int ((lem$w2ui frac64))))) *
+                         ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 52 : int):ii)))))))))) in
+             (typ, value_name)) in
+         sail2_state_monad$returnS (typ, value_name)) (\ varstup .  let ((typ : FPType), (value_name : real)) = varstup in
+      sail2_state_monad$returnS (sign, typ, value_name))) (\ varstup .  let ((sign : 1 bits), (typ : FPType), (value_name :
+     real)) = varstup in
+   let (value_name : real) =
+     (if (((sign = (vec_of_bits [B1]  :  1 words$word)))) then(real_of_num 0) - value_name
+     else value_name) in
+   sail2_state_monad$returnS (typ, sign, value_name)))))))))))))`;
+
+
+(*val FPUnpackCV : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*)
+
+val _ = Define `
+ ((FPUnpackCV:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((FPType#(1)words$word#real),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fpval fpcr__arg=
+    (let fpcr = fpcr__arg in
+   let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 19 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)) in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (fp_type : FPType) .  sail2_state_monad$bindS
+   (FPUnpackBase fpval fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let (fp_type : FPType) = tup__0 in
+   let (sign : 1 bits) = tup__1 in
+   let (value_name : real) = tup__2 in
+   sail2_state_monad$returnS (fp_type, sign, value_name)))))))`;
+
+
+(*val FPConvert__0 : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> mword ty32 -> FPRounding -> M (mword 'M)*)
+
+(*val FPConvert__1 : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> mword ty32 -> M (mword 'M)*)
+
+val _ = Define `
+ ((FPConvert__0:int -> 'N words$word ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op fpcr rounding=
+    (let p0_ = M__tv in
+   if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) ""))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+     (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+     (FPUnpackCV op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+     let typ = tup__0 in
+     let sign = tup__1 in
+     let value_name = tup__2 in
+     let (alt_hp : bool) =
+       (T /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))) in sail2_state_monad$bindS
+     (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$bindS
+        (if alt_hp then (FPZero (( 16 : int):ii) sign  : ( 16 words$word) M)
+         else if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+           (FPDefaultNaN (( 16 : int):ii) ()   : ( 16 words$word) M)
+         else (FPConvertNaN (( 16 : int):ii) op  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$seqS
+        (if ((((((typ = FPType_SNaN))) \/ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr
+         else sail2_state_monad$returnS () )
+        (sail2_state_monad$returnS result))
+      else if (((typ = FPType_Infinity))) then
+        if alt_hp then
+          let result =
+            ((concat_vec sign
+               ((Ones__0 ((make_the_value (((( 16 : int):ii) - (( 1 : int):ii)))  :  15 itself))
+                  :  15 words$word))
+              :  16 words$word)) in sail2_state_monad$seqS
+          (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)
+        else (FPInfinity (( 16 : int):ii) sign  : ( 16 words$word) M)
+      else if (((typ = FPType_Zero))) then (FPZero (( 16 : int):ii) sign  : ( 16 words$word) M)
+      else (FPRoundCV (( 16 : int):ii) value_name fpcr rounding  : ( 16 words$word) M)) (\ (result : 16
+       bits) . 
+     sail2_state_monad$returnS ((words$w2w result  :  'M words$word))))))))
+   else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) ""))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+     (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+     (FPUnpackCV op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+     let typ = tup__0 in
+     let sign = tup__1 in
+     let value_name = tup__2 in
+     let (alt_hp : bool) =
+       (F /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))) in sail2_state_monad$bindS
+     (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$bindS
+        (if alt_hp then (FPZero (( 32 : int):ii) sign  : ( 32 words$word) M)
+         else if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+           (FPDefaultNaN (( 32 : int):ii) ()   : ( 32 words$word) M)
+         else (FPConvertNaN (( 32 : int):ii) op  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$seqS
+        (if ((((((typ = FPType_SNaN))) \/ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr
+         else sail2_state_monad$returnS () )
+        (sail2_state_monad$returnS result))
+      else if (((typ = FPType_Infinity))) then
+        if alt_hp then
+          let result =
+            ((concat_vec sign
+               ((Ones__0 ((make_the_value (((( 32 : int):ii) - (( 1 : int):ii)))  :  31 itself))
+                  :  31 words$word))
+              :  32 words$word)) in sail2_state_monad$seqS
+          (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)
+        else (FPInfinity (( 32 : int):ii) sign  : ( 32 words$word) M)
+      else if (((typ = FPType_Zero))) then (FPZero (( 32 : int):ii) sign  : ( 32 words$word) M)
+      else (FPRoundCV (( 32 : int):ii) value_name fpcr rounding  : ( 32 words$word) M)) (\ (result : 32
+       bits) . 
+     sail2_state_monad$returnS ((words$w2w result  :  'M words$word))))))))
+   else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) ""))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+     (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+     (FPUnpackCV op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+     let typ = tup__0 in
+     let sign = tup__1 in
+     let value_name = tup__2 in
+     let (alt_hp : bool) =
+       (F /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))) in sail2_state_monad$bindS
+     (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$bindS
+        (if alt_hp then (FPZero (( 64 : int):ii) sign  : ( 64 words$word) M)
+         else if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+           (FPDefaultNaN (( 64 : int):ii) ()   : ( 64 words$word) M)
+         else (FPConvertNaN (( 64 : int):ii) op  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$seqS
+        (if ((((((typ = FPType_SNaN))) \/ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr
+         else sail2_state_monad$returnS () )
+        (sail2_state_monad$returnS result))
+      else if (((typ = FPType_Infinity))) then
+        if alt_hp then
+          let result =
+            ((concat_vec sign
+               ((Ones__0 ((make_the_value (((( 64 : int):ii) - (( 1 : int):ii)))  :  63 itself))
+                  :  63 words$word))
+              :  64 words$word)) in sail2_state_monad$seqS
+          (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)
+        else (FPInfinity (( 64 : int):ii) sign  : ( 64 words$word) M)
+      else if (((typ = FPType_Zero))) then (FPZero (( 64 : int):ii) sign  : ( 64 words$word) M)
+      else (FPRoundCV (( 64 : int):ii) value_name fpcr rounding  : ( 64 words$word) M)) (\ (result : 64
+       bits) . 
+     sail2_state_monad$returnS ((words$w2w result  :  'M words$word))))))))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "") (sail2_state_monad$exitS () )))`;
+
+
+val _ = Define `
+ ((FPConvert__1:int -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op fpcr=
+    ((FPConvert__0 M__tv op fpcr ((FPRoundingMode fpcr))  : ( 'M words$word) M)))`;
+
+
+(*val FPUnpack : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*)
+
+val _ = Define `
+ ((FPUnpack:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((FPType#(1)words$word#real),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fpval fpcr__arg=
+    (let fpcr = fpcr__arg in
+   let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 26 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)) in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (fp_type : FPType) .  sail2_state_monad$bindS
+   (FPUnpackBase fpval fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let (fp_type : FPType) = tup__0 in
+   let (sign : 1 bits) = tup__1 in
+   let (value_name : real) = tup__2 in
+   sail2_state_monad$returnS (fp_type, sign, value_name)))))))`;
+
+
+(*val FPToFixedJS : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> mword ty32 -> bool -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPToFixedJS:int -> 'M words$word ->(32)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr Is64=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 64 : int):ii)))) /\ (((N__tv = (( 32 : int):ii))))))) "((M == 64) && (N == 32))")
+   (undefined_real () )) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let typ = tup__0 in
+   let sign = tup__1 in
+   let value_name = tup__2 in
+   let (Z : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$seqS
+      (FPProcessException FPExc_InvalidOp fpcr)
+      (let (Z : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS Z)
+    else sail2_state_monad$returnS Z) (\ (Z : 1 bits) . 
+   let (int_result : ii) = (flr value_name) in
+   let (error : real) = (value_name - (((real_of_int int_result)))) in
+   let (round_it_up : bool) =
+     ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) < (( 0 : int):ii)))) in
+   let (int_result : ii) =
+     (if round_it_up then ((ex_int int_result)) + (( 1 : int):ii)
+     else int_result) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (result : ii) . 
+   let (result : ii) =
+     (if ((((ex_int int_result)) < (( 0 : int):ii))) then
+       ((ex_int int_result)) -
+         ((((pow2 (( 32 : int):ii))) *
+             ((ex_int
+                 ((clg
+                     (((((real_of_int int_result))) / (((real_of_int ((pow2 (( 32 : int):ii))))))))))))))
+     else
+       ((ex_int int_result)) -
+         ((((pow2 (( 32 : int):ii))) *
+             ((ex_int
+                 ((flr
+                     (((((real_of_int int_result))) / (((real_of_int ((pow2 (( 32 : int):ii))))))))))))))) in sail2_state_monad$bindS
+   (if (((((((ex_int int_result)) < ((~ ((pow2 (( 31 : int):ii))))))) \/ ((((ex_int int_result)) > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then sail2_state_monad$seqS
+      (FPProcessException FPExc_InvalidOp fpcr)
+      (let (Z : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS Z)
+    else if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then sail2_state_monad$seqS
+      (FPProcessException FPExc_Inexact fpcr)
+      (let (Z : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS Z)
+    else sail2_state_monad$returnS Z) (\ (Z : 1 bits) . 
+   let (Z : 1 bits) =
+     (if ((((((sign = (vec_of_bits [B1]  :  1 words$word)))) /\ (((value_name = (realFromFrac(( 0 : int))(( 10 : int))))))))) then
+       (vec_of_bits [B0]  :  1 words$word)
+     else Z) in
+   let (result : ii) = (if (((typ = FPType_Infinity))) then (( 0 : int):ii) else result) in sail2_state_monad$seqS
+   (if Is64 then
+      let split_vec =
+        ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) Z  :  2 words$word))
+           (vec_of_bits [B0;B0]  :  2 words$word)
+          :  4 words$word)) in
+      let (tup__0, tup__1, tup__2, tup__3) =
+        ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>)))))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPSCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+      sail2_state_monad$write_regS
+        FPSCR_ref
+        ((set_slice (( 32 : int):ii) (( 4 : int):ii) w__4 (( 28 : int):ii)
+            ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) Z  :  2 words$word))
+                (vec_of_bits [B0;B0]  :  2 words$word)
+               :  4 words$word))
+           :  32 words$word))))
+   (sail2_state_monad$returnS ((words$w2w
+              ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  'N itself)) result (( 0 : int):ii)  :  'N words$word))
+             :  'N words$word))))))))))))`;
+
+
+(*val FPToFixed : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> ii -> bool -> mword ty32 -> FPRounding -> M (mword 'M)*)
+
+val _ = Define `
+ ((FPToFixed:int -> 'N words$word -> int -> bool ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op fbits unsigned fpcr rounding=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (sail2_state_monad$assert_expS ((((((M__tv = (( 16 : int):ii)))) \/ ((((((M__tv = (( 32 : int):ii)))) \/ (((M__tv = (( 64 : int):ii)))))))))) "((M == 16) || ((M == 32) || (M == 64)))"))
+   (sail2_state_monad$assert_expS ((fbits >= (( 0 : int):ii))) "(fbits >= 0)"))
+   (sail2_state_monad$assert_expS (((rounding <> FPRounding_ODD))) "(rounding != FPRounding_ODD)"))
+   (undefined_real () )) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let typ = tup__0 in
+   let sign = tup__1 in
+   let value_name = tup__2 in sail2_state_monad$seqS
+   (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then
+      FPProcessException FPExc_InvalidOp fpcr
+    else sail2_state_monad$returnS () )
+   (let value_name = (value_name * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) fbits))) in
+   let (int_result : ii) = (flr value_name) in
+   let (error : real) = (value_name - (((real_of_int int_result)))) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . 
+   let (round_up : bool) =
+     ((case rounding of
+       FPRounding_TIEEVEN =>
+        (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii)  :  1 itself)) int_result (( 0 : int):ii)
+                     :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word))))))))
+     | FPRounding_POSINF => (error <> (realFromFrac(( 0 : int))(( 10 : int))))
+     | FPRounding_NEGINF => F
+     | FPRounding_ZERO =>
+        ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) < (( 0 : int):ii))))
+     | FPRounding_TIEAWAY =>
+        (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) >= (( 0 : int):ii)))))))
+     )) in
+   let (int_result : ii) = (if round_up then ((ex_int int_result)) + (( 1 : int):ii) else int_result) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (overflow : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector M__tv  : ( 'M words$word) M) (\ (result : 'M bits) .  sail2_state_monad$bindS
+   (SatQ int_result ((make_the_value ((int_of_num (words$word_len result)))  :  'M itself)) unsigned
+     : (( 'M words$word # bool)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let result = tup__0 in
+   let overflow = tup__1 in sail2_state_monad$seqS
+   (if overflow then FPProcessException FPExc_InvalidOp fpcr
+    else if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$returnS result))))))))))))`;
+
+
+(*val FPSqrt : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPSqrt:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let typ = tup__0 in
+   let sign = tup__1 in
+   let value_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then
+     (FPProcessNaN typ op fpcr  : ( 'N words$word) M)
+   else if (((typ = FPType_Zero))) then (FPZero ((int_of_num (words$word_len op))) sign  : ( 'N words$word) M)
+   else if ((((((typ = FPType_Infinity))) /\ (((sign = (vec_of_bits [B0]  :  1 words$word)))))))
+   then
+     (FPInfinity ((int_of_num (words$word_len op))) sign  : ( 'N words$word) M)
+   else if (((sign = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+     (FPDefaultNaN ((int_of_num (words$word_len op))) ()   : ( 'N words$word) M) (\ (w__3 : 'N bits) . 
+     let result = w__3 in sail2_state_monad$seqS
+     (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+   else (FPRound__1 ((int_of_num (words$word_len op))) ((sqrt value_name)) fpcr  : ( 'N words$word) M))))))))`;
+
+
+(*val FPRoundInt : forall 'N . Size 'N => mword 'N -> mword ty32 -> FPRounding -> bool -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPRoundInt:'N words$word ->(32)words$word -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op fpcr rounding exact=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((rounding <> FPRounding_ODD))) "(rounding != FPRounding_ODD)")
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))"))
+   (undefined_real () )) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let typ = tup__0 in
+   let sign = tup__1 in
+   let value_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (real_result : real) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) .  sail2_state_monad$bindS
+   (undefined_real () ) (\ (error : real) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (int_result : ii) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op)))  : ( 'N words$word) M) (\ (result : 'N bits) . 
+   if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then
+     (FPProcessNaN typ op fpcr  : ( 'N words$word) M)
+   else if (((typ = FPType_Infinity))) then (FPInfinity ((int_of_num (words$word_len op))) sign  : ( 'N words$word) M)
+   else if (((typ = FPType_Zero))) then (FPZero ((int_of_num (words$word_len op))) sign  : ( 'N words$word) M)
+   else
+     let int_result = (flr value_name) in
+     let error = (value_name - (((real_of_int int_result)))) in
+     let (round_up : bool) =
+       ((case rounding of
+         FPRounding_TIEEVEN =>
+          (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii)  :  1 itself)) int_result (( 0 : int):ii)
+                       :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word))))))))
+       | FPRounding_POSINF => (error <> (realFromFrac(( 0 : int))(( 10 : int))))
+       | FPRounding_NEGINF => F
+       | FPRounding_ZERO =>
+          ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) < (( 0 : int):ii))))
+       | FPRounding_TIEAWAY =>
+          (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) >= (( 0 : int):ii)))))))
+       )) in
+     let (int_result : ii) =
+       (if round_up then ((ex_int int_result)) + (( 1 : int):ii)
+       else int_result) in
+     let real_result = ((real_of_int int_result)) in sail2_state_monad$bindS
+     (if (((real_result = (realFromFrac(( 0 : int))(( 10 : int)))))) then (FPZero ((int_of_num (words$word_len op))) sign  : ( 'N words$word) M)
+      else (FPRound__0 ((int_of_num (words$word_len op))) real_result fpcr FPRounding_ZERO  : ( 'N words$word) M)) (\ (result : 'N
+       bits) .  sail2_state_monad$seqS
+     (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ exact))) then
+        FPProcessException FPExc_Inexact fpcr
+      else sail2_state_monad$returnS () )
+     (sail2_state_monad$returnS result)))))))))))))`;
+
+
+(*val FPCompare : forall 'N . Size 'N => mword 'N -> mword 'N -> bool -> mword ty32 -> M (mword ty4)*)
+
+val _ = Define `
+ ((FPCompare:'N words$word -> 'N words$word -> bool ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 signal_nans fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (result : 4 bits) . 
+   if ((((((((((((type1 = FPType_SNaN))) \/ (((type1 = FPType_QNaN)))))) \/ (((type2 = FPType_SNaN)))))) \/ (((type2 = FPType_QNaN)))))) then
+     let result = ((vec_of_bits [B0;B0;B1;B1]  :  4 words$word)) in sail2_state_monad$seqS
+     (if (((((((((type1 = FPType_SNaN))) \/ (((type2 = FPType_SNaN)))))) \/ signal_nans))) then
+        FPProcessException FPExc_InvalidOp fpcr
+      else sail2_state_monad$returnS () )
+     (sail2_state_monad$returnS result)
+   else
+     let (result : 4 bits) =
+       (if (((value1_name = value2_name))) then (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)
+       else if ((value1_name < value2_name)) then (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)
+       else (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)) in
+     sail2_state_monad$returnS result)))))))))))`;
+
+
+(*val FPSub : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPSub:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (let (rounding : FPRounding) = (FPRoundingMode fpcr) in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs type1 type2 op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (result_sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_real () ) (\ (result_value : real) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . 
+   if ((~ done)) then
+     let inf1 = (type1 = FPType_Infinity) in
+     let inf2 = (type2 = FPType_Infinity) in
+     let zero1 = (type1 = FPType_Zero) in
+     let zero2 = (type2 = FPType_Zero) in
+     if ((((((inf1 /\ inf2))) /\ (((sign1 = sign2)))))) then sail2_state_monad$bindS
+       (FPDefaultNaN ((int_of_num (words$word_len op1))) ()   : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+       let result = w__0 in sail2_state_monad$seqS
+       (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+     else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B0]  :  1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+       (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0]  :  1 words$word)  : ( 'N words$word) M)
+     else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B1]  :  1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+       (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1]  :  1 words$word)  : ( 'N words$word) M)
+     else if ((((((zero1 /\ zero2))) /\ (((sign1 = ((not_vec sign2  :  1 words$word))))))))
+     then
+       (FPZero ((int_of_num (words$word_len op1))) sign1  : ( 'N words$word) M)
+     else
+       let result_value = (value1_name - value2_name) in
+       if (((result_value = (realFromFrac(( 0 : int))(( 10 : int)))))) then
+         let result_sign =
+           (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1]  :  1 words$word)
+           else (vec_of_bits [B0]  :  1 words$word)) in
+         (FPZero ((int_of_num (words$word_len op1))) result_sign  : ( 'N words$word) M)
+       else (FPRound__0 ((int_of_num (words$word_len op1))) result_value fpcr rounding  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result))))))))))))))))))))`;
+
+
+(*val FPMulAdd : forall 'N . Size 'N => mword 'N -> mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMulAdd:'N words$word -> 'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addend op1 op2 fpcr=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len addend))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len addend))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len addend))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (let (rounding : FPRounding) = (FPRoundingMode fpcr) in sail2_state_monad$bindS
+   (undefined_real () ) (\ (valueA_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (signA : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typeA : FPType) .  sail2_state_monad$bindS
+   (FPUnpack addend fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let typeA = tup__0 in
+   let signA = tup__1 in
+   let valueA_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in
+   let (inf1 : bool) = (type1 = FPType_Infinity) in
+   let (zero1 : bool) = (type1 = FPType_Zero) in
+   let (inf2 : bool) = (type2 = FPType_Infinity) in
+   let (zero2 : bool) = (type2 = FPType_Zero) in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len addend)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs3 typeA type1 type2 addend op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (if ((((((typeA = FPType_QNaN))) /\ ((((((inf1 /\ zero2))) \/ (((zero1 /\ inf2))))))))) then sail2_state_monad$bindS
+      (FPDefaultNaN ((int_of_num (words$word_len addend))) ()   : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+      let result = w__0 in sail2_state_monad$seqS
+      (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+    else sail2_state_monad$returnS result) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (result_sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_real () ) (\ (result_value : real) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zeroP : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (infP : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (signP : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zeroA : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (infA : bool) . 
+   if ((~ done)) then
+     let infA = (typeA = FPType_Infinity) in
+     let zeroA = (typeA = FPType_Zero) in
+     let signP = ((xor_vec sign1 sign2  :  1 words$word)) in
+     let infP = (inf1 \/ inf2) in
+     let zeroP = (zero1 \/ zero2) in
+     if (((((((((inf1 /\ zero2))) \/ (((zero1 /\ inf2)))))) \/ ((((((infA /\ infP))) /\ (((signA <> signP))))))))) then sail2_state_monad$bindS
+       (FPDefaultNaN ((int_of_num (words$word_len addend))) ()   : ( 'N words$word) M) (\ (w__1 : 'N bits) . 
+       let result = w__1 in sail2_state_monad$seqS
+       (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+     else if ((((((infA /\ (((signA = (vec_of_bits [B0]  :  1 words$word))))))) \/ (((infP /\ (((signP = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+       (FPInfinity ((int_of_num (words$word_len addend))) (vec_of_bits [B0]  :  1 words$word)  : ( 'N words$word) M)
+     else if ((((((infA /\ (((signA = (vec_of_bits [B1]  :  1 words$word))))))) \/ (((infP /\ (((signP = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+       (FPInfinity ((int_of_num (words$word_len addend))) (vec_of_bits [B1]  :  1 words$word)  : ( 'N words$word) M)
+     else if ((((((zeroA /\ zeroP))) /\ (((signA = signP)))))) then
+       (FPZero ((int_of_num (words$word_len addend))) signA  : ( 'N words$word) M)
+     else
+       let result_value = (valueA_name + ((value1_name * value2_name))) in
+       if (((result_value = (realFromFrac(( 0 : int))(( 10 : int)))))) then
+         let result_sign =
+           (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1]  :  1 words$word)
+           else (vec_of_bits [B0]  :  1 words$word)) in
+         (FPZero ((int_of_num (words$word_len addend))) result_sign  : ( 'N words$word) M)
+       else (FPRound__1 ((int_of_num (words$word_len addend))) result_value fpcr  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result))))))))))))))))))))))))))`;
+
+
+(*val FPMul : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMul:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs type1 type2 op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . 
+   if ((~ done)) then
+     let inf1 = (type1 = FPType_Infinity) in
+     let inf2 = (type2 = FPType_Infinity) in
+     let zero1 = (type1 = FPType_Zero) in
+     let zero2 = (type2 = FPType_Zero) in
+     if ((((((inf1 /\ zero2))) \/ (((zero1 /\ inf2)))))) then sail2_state_monad$bindS
+       (FPDefaultNaN ((int_of_num (words$word_len op1))) ()   : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+       let result = w__0 in sail2_state_monad$seqS
+       (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+     else if (((inf1 \/ inf2))) then
+       (FPInfinity ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2  :  1 words$word))  : ( 'N words$word) M)
+     else if (((zero1 \/ zero2))) then
+       (FPZero ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2  :  1 words$word))  : ( 'N words$word) M)
+     else (FPRound__1 ((int_of_num (words$word_len op1))) ((value1_name * value2_name)) fpcr  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result)))))))))))))))))`;
+
+
+(*val FPMin : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMin:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs type1 type2 op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) . 
+   if ((~ done)) then
+     let ((sign : 1 bits), (typ : FPType), (value_name : real)) =
+       (if ((value1_name < value2_name)) then
+         let (tup__0, tup__1, tup__2) = (type1, sign1, value1_name) in
+         let (typ : FPType) = tup__0 in
+         let (sign : 1 bits) = tup__1 in
+         let (value_name : real) = tup__2 in
+         (sign, typ, value_name)
+       else
+         let (tup__0, tup__1, tup__2) = (type2, sign2, value2_name) in
+         let (typ : FPType) = tup__0 in
+         let (sign : 1 bits) = tup__1 in
+         let (value_name : real) = tup__2 in
+         (sign, typ, value_name)) in
+     if (((typ = FPType_Infinity))) then (FPInfinity ((int_of_num (words$word_len op1))) sign  : ( 'N words$word) M)
+     else if (((typ = FPType_Zero))) then
+       let sign = ((or_vec sign1 sign2  :  1 words$word)) in
+       (FPZero ((int_of_num (words$word_len op1))) sign  : ( 'N words$word) M)
+     else (FPRound__1 ((int_of_num (words$word_len op1))) value_name fpcr  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result))))))))))))))))`;
+
+
+(*val FPMinNum : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMinNum:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1__arg op2__arg fpcr=
+    (let op1 = op1__arg in
+   let op2 = op2__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (anon20 : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (anon10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let anon10 = tup__1 in
+   let anon20 = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (anon40 : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (anon30 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let anon30 = tup__1 in
+   let anon40 = tup__2 in sail2_state_monad$bindS
+   (if ((((((type1 = FPType_QNaN))) /\ (((type2 <> FPType_QNaN)))))) then sail2_state_monad$bindS
+      (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0]  :  1 words$word)  : ( 'N words$word) M) (\ (w__0 :
+         'N words$word) . 
+      let (op1 :  'N words$word) = w__0 in
+      sail2_state_monad$returnS (op1, op2))
+    else sail2_state_monad$bindS
+      (if ((((((type1 <> FPType_QNaN))) /\ (((type2 = FPType_QNaN)))))) then
+         (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0]  :  1 words$word)  : ( 'N words$word) M)
+       else sail2_state_monad$returnS op2) (\ (op2 :  'N words$word) . 
+      sail2_state_monad$returnS (op1, op2))) (\ varstup .  let ((op1 :  'N words$word), (op2 :  'N words$word)) = varstup in
+   (FPMin op1 op2 fpcr  : ( 'N words$word) M))))))))))))`;
+
+
+(*val FPMax : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMax:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs type1 type2 op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (typ : FPType) . 
+   if ((~ done)) then
+     let ((sign : 1 bits), (typ : FPType), (value_name : real)) =
+       (if ((value1_name > value2_name)) then
+         let (tup__0, tup__1, tup__2) = (type1, sign1, value1_name) in
+         let (typ : FPType) = tup__0 in
+         let (sign : 1 bits) = tup__1 in
+         let (value_name : real) = tup__2 in
+         (sign, typ, value_name)
+       else
+         let (tup__0, tup__1, tup__2) = (type2, sign2, value2_name) in
+         let (typ : FPType) = tup__0 in
+         let (sign : 1 bits) = tup__1 in
+         let (value_name : real) = tup__2 in
+         (sign, typ, value_name)) in
+     if (((typ = FPType_Infinity))) then (FPInfinity ((int_of_num (words$word_len op1))) sign  : ( 'N words$word) M)
+     else if (((typ = FPType_Zero))) then
+       let sign = ((and_vec sign1 sign2  :  1 words$word)) in
+       (FPZero ((int_of_num (words$word_len op1))) sign  : ( 'N words$word) M)
+     else (FPRound__1 ((int_of_num (words$word_len op1))) value_name fpcr  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result))))))))))))))))`;
+
+
+(*val FPMaxNum : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPMaxNum:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1__arg op2__arg fpcr=
+    (let op1 = op1__arg in
+   let op2 = op2__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (anon20 : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (anon10 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let anon10 = tup__1 in
+   let anon20 = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (anon40 : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (anon30 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let anon30 = tup__1 in
+   let anon40 = tup__2 in sail2_state_monad$bindS
+   (if ((((((type1 = FPType_QNaN))) /\ (((type2 <> FPType_QNaN)))))) then sail2_state_monad$bindS
+      (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1]  :  1 words$word)  : ( 'N words$word) M) (\ (w__0 :
+         'N words$word) . 
+      let (op1 :  'N words$word) = w__0 in
+      sail2_state_monad$returnS (op1, op2))
+    else sail2_state_monad$bindS
+      (if ((((((type1 <> FPType_QNaN))) /\ (((type2 = FPType_QNaN)))))) then
+         (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1]  :  1 words$word)  : ( 'N words$word) M)
+       else sail2_state_monad$returnS op2) (\ (op2 :  'N words$word) . 
+      sail2_state_monad$returnS (op1, op2))) (\ varstup .  let ((op1 :  'N words$word), (op2 :  'N words$word)) = varstup in
+   (FPMax op1 op2 fpcr  : ( 'N words$word) M))))))))))))`;
+
+
+(*val FPDiv : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPDiv:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (undefined_real () )) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs type1 type2 op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . 
+   if ((~ done)) then
+     let inf1 = (type1 = FPType_Infinity) in
+     let inf2 = (type2 = FPType_Infinity) in
+     let zero1 = (type1 = FPType_Zero) in
+     let zero2 = (type2 = FPType_Zero) in
+     if ((((((inf1 /\ inf2))) \/ (((zero1 /\ zero2)))))) then sail2_state_monad$bindS
+       (FPDefaultNaN ((int_of_num (words$word_len op1))) ()   : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+       let result = w__0 in sail2_state_monad$seqS
+       (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+     else if (((inf1 \/ zero2))) then sail2_state_monad$bindS
+       (FPInfinity ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2  :  1 words$word))  : ( 'N words$word) M) (\ (w__1 : 'N
+         bits) . 
+       let result = w__1 in sail2_state_monad$seqS
+       (if ((~ inf1)) then FPProcessException FPExc_DivideByZero fpcr
+        else sail2_state_monad$returnS () )
+       (sail2_state_monad$returnS result))
+     else if (((zero1 \/ inf2))) then
+       (FPZero ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2  :  1 words$word))  : ( 'N words$word) M)
+     else (FPRound__1 ((int_of_num (words$word_len op1))) ((value1_name / value2_name)) fpcr  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result)))))))))))))))))`;
+
+
+(*val FPAdd : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*)
+
+val _ = Define `
+ ((FPAdd:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")
+   (let (rounding : FPRounding) = (FPRoundingMode fpcr) in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value1_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign1 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type1 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op1 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type1 = tup__0 in
+   let sign1 = tup__1 in
+   let value1_name = tup__2 in sail2_state_monad$bindS
+   (undefined_real () ) (\ (value2_name : real) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (sign2 : 1 bits) .  sail2_state_monad$bindS
+   (undefined_FPType () ) (\ (type2 : FPType) .  sail2_state_monad$bindS
+   (FPUnpack op2 fpcr  : ((FPType #  1 words$word # real)) M) (\ varstup .  let (tup__0, tup__1, tup__2) = varstup in
+   let type2 = tup__0 in
+   let sign2 = tup__1 in
+   let value2_name = tup__2 in sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len op1)))  : ( 'N words$word) M) (\ (result : 'N bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (done : bool) .  sail2_state_monad$bindS
+   (FPProcessNaNs type1 type2 op1 op2 fpcr  : ((bool #  'N words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let done = tup__0 in
+   let result = tup__1 in sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (result_sign : 1 bits) .  sail2_state_monad$bindS
+   (undefined_real () ) (\ (result_value : real) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . 
+   if ((~ done)) then
+     let inf1 = (type1 = FPType_Infinity) in
+     let inf2 = (type2 = FPType_Infinity) in
+     let zero1 = (type1 = FPType_Zero) in
+     let zero2 = (type2 = FPType_Zero) in
+     if ((((((inf1 /\ inf2))) /\ (((sign1 = ((not_vec sign2  :  1 words$word)))))))) then sail2_state_monad$bindS
+       (FPDefaultNaN ((int_of_num (words$word_len op1))) ()   : ( 'N words$word) M) (\ (w__0 : 'N bits) . 
+       let result = w__0 in sail2_state_monad$seqS
+       (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result))
+     else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B0]  :  1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+       (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0]  :  1 words$word)  : ( 'N words$word) M)
+     else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B1]  :  1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+       (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1]  :  1 words$word)  : ( 'N words$word) M)
+     else if ((((((zero1 /\ zero2))) /\ (((sign1 = sign2)))))) then
+       (FPZero ((int_of_num (words$word_len op1))) sign1  : ( 'N words$word) M)
+     else
+       let result_value = (value1_name + value2_name) in
+       if (((result_value = (realFromFrac(( 0 : int))(( 10 : int)))))) then
+         let result_sign =
+           (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1]  :  1 words$word)
+           else (vec_of_bits [B0]  :  1 words$word)) in
+         (FPZero ((int_of_num (words$word_len op1))) result_sign  : ( 'N words$word) M)
+       else (FPRound__0 ((int_of_num (words$word_len op1))) result_value fpcr rounding  : ( 'N words$word) M)
+   else sail2_state_monad$returnS result))))))))))))))))))))`;
+
+
+(*val ExternalSecureInvasiveDebugEnabled : unit -> M bool*)
+
+val _ = Define `
+ ((ExternalSecureInvasiveDebugEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))
+     ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : bool) . 
+   if w__1 then sail2_state_monad$returnS F
+   else
+     sail2_state$and_boolS ((ExternalInvasiveDebugEnabled () ))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS SPIDEN_ref) (\ (w__3 : signal) .  sail2_state_monad$returnS (((w__3 = HIGH))))))))`;
+
+
+(*val ExternalDebugInterruptsDisabled : mword ty2 -> M bool*)
+
+val _ = Define `
+ ((ExternalDebugInterruptsDisabled:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (int_dis : bool) . 
+   let pat_0 = target in
+   if (((pat_0 = EL3))) then
+     sail2_state$and_boolS
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+        sail2_state_monad$returnS (((((slice w__0 (( 22 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))) ((ExternalSecureInvasiveDebugEnabled () ))
+   else if (((pat_0 = EL2))) then
+     sail2_state$and_boolS
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__3 : 32 bits) . 
+        sail2_state_monad$returnS (((((and_vec ((slice w__3 (( 22 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                       (vec_of_bits [B1;B0]  :  2 words$word)
+                      :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))
+       ((ExternalInvasiveDebugEnabled () ))
+   else sail2_state_monad$bindS
+     (IsSecure () ) (\ (w__6 : bool) . 
+     if w__6 then
+       sail2_state$and_boolS
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+          sail2_state_monad$returnS (((((and_vec ((slice w__7 (( 22 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                         (vec_of_bits [B1;B0]  :  2 words$word)
+                        :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))
+         ((ExternalSecureInvasiveDebugEnabled () ))
+     else
+       sail2_state$and_boolS
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+          sail2_state_monad$returnS (((((slice w__10 (( 22 : int):ii) (( 2 : int):ii)  :  2 words$word)) <> (vec_of_bits [B0;B0]  :  2 words$word)))))) ((ExternalInvasiveDebugEnabled () ))))))`;
+
+
+(*val ELStateUsingAArch32K : mword ty2 -> bool -> M (bool * bool)*)
+
+val _ = Define `
+ ((ELStateUsingAArch32K:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el secure=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (aarch32 : bool) . 
+   let (known : bool) = T in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (aarch32_at_el1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (aarch32_below_el3 : bool) .  sail2_state_monad$bindS
+   (if ((~ ((HaveAArch32EL el)))) then
+      let (aarch32 : bool) = F in
+      sail2_state_monad$returnS (aarch32, known)
+    else if ((HighestELUsingAArch32 () )) then
+      let (aarch32 : bool) = T in
+      sail2_state_monad$returnS (aarch32, known)
+    else sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 10 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__1 : bool) . 
+      let aarch32_below_el3 = w__1 in sail2_state_monad$bindS
+      (sail2_state$or_boolS (sail2_state_monad$returnS aarch32_below_el3)
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ ((~ secure))))))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 31 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+           ( sail2_state_monad$bindS(sail2_state$and_boolS
+              (sail2_state$and_boolS
+                 ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+                  sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+                 ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+                  sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (sail2_state_monad$returnS ((HaveVirtHostExt () )))) (\ (w__7 :
+              bool) . 
+            sail2_state_monad$returnS ((~ w__7)))))) (\ (w__9 : bool) . 
+      let aarch32_at_el1 = w__9 in
+      if ((((((el = EL0))) /\ ((~ aarch32_at_el1))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+        if (((w__10.ProcState_EL = EL0))) then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+          let (aarch32 : bool) = (w__11.ProcState_nRW = (vec_of_bits [B1]  :  1 words$word)) in
+          sail2_state_monad$returnS (aarch32, known))
+        else
+          let (known : bool) = F in
+          sail2_state_monad$returnS (aarch32, known))
+      else
+        let (aarch32 : bool) =
+          ((((aarch32_below_el3 /\ (((el <> EL3)))))) \/ (((aarch32_at_el1 /\ ((((((el = EL1))) \/ (((el = EL0)))))))))) in
+        sail2_state_monad$returnS (aarch32, known)))) (\ varstup .  let ((aarch32 : bool), (known : bool)) = varstup in sail2_state_monad$bindS
+   (if ((~ known)) then sail2_state_monad$undefined_boolS () 
+    else sail2_state_monad$returnS aarch32) (\ (aarch32 : bool) . 
+   sail2_state_monad$returnS (known, aarch32))))))))`;
+
+
+(*val ELUsingAArch32K : mword ty2 -> M (bool * bool)*)
+
+val _ = Define `
+ ((ELUsingAArch32K:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el=  (sail2_state_monad$bindS (IsSecureBelowEL3 () ) (\ (w__0 : bool) .  ELStateUsingAArch32K el w__0)))`;
+
+
+(*val ELStateUsingAArch32 : mword ty2 -> bool -> M bool*)
+
+val _ = Define `
+ ((ELStateUsingAArch32:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el secure=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (aarch32 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (known : bool) .  sail2_state_monad$bindS
+   (ELStateUsingAArch32K el secure) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let known = tup__0 in
+   let aarch32 = tup__1 in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS known "known") (sail2_state_monad$returnS aarch32))))))`;
+
+
+(*val ELUsingAArch32 : mword ty2 -> M bool*)
+
+val _ = Define `
+ ((ELUsingAArch32:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el=  (sail2_state_monad$bindS (IsSecureBelowEL3 () ) (\ (w__0 : bool) .  ELStateUsingAArch32 el w__0)))`;
+
+
+(*val UpdateEDSCRFields : unit -> M unit*)
+
+val _ = Define `
+ ((UpdateEDSCRFields:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (Halted () ) (\ (w__0 : bool) . 
+   if ((~ w__0)) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS
+       EDSCR_ref
+       ((set_slice (( 32 : int):ii) (( 2 : int):ii) w__1 (( 8 : int):ii) (vec_of_bits [B0;B0]  :  2 words$word)  :  32 words$word)))
+     (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__2 :  32 words$word) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__3 :  1 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS EDSCR_ref ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__2 (( 18 : int):ii) w__3  :  32 words$word)))
+     (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__4 :  32 words$word) . 
+     sail2_state_monad$write_regS
+       EDSCR_ref
+       ((set_slice (( 32 : int):ii) (( 4 : int):ii) w__4 (( 10 : int):ii) (vec_of_bits [B1;B1;B1;B1]  :  4 words$word)
+          :  32 words$word))))))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__5 :  32 words$word) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS EDSCR_ref ((set_slice (( 32 : int):ii) (( 2 : int):ii) w__5 (( 8 : int):ii) w__6.ProcState_EL  :  32 words$word)))
+     (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__7 :  32 words$word) .  sail2_state_monad$bindS
+     (IsSecure () ) (\ (w__8 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS
+       EDSCR_ref
+       ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__7 (( 18 : int):ii)
+           (if w__8 then (vec_of_bits [B0]  :  1 words$word)
+            else (vec_of_bits [B1]  :  1 words$word))
+          :  32 words$word)))
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M)) (\ (RW : 4 bits) .  sail2_state_monad$bindS
+     (ELUsingAArch32 EL1) (\ (w__9 : bool) . 
+     let (RW : 4 bits) =
+       ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 1 : int):ii)
+          (if w__9 then (vec_of_bits [B0]  :  1 words$word)
+           else (vec_of_bits [B1]  :  1 words$word))
+         :  4 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$bindS
+     (if (((w__10.ProcState_EL <> EL0))) then
+        let (RW : 4 bits) =
+          ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 0 : int):ii) (vec_of_bits [access_vec_dec RW (( 1 : int):ii)]  :  1 words$word)
+            :  4 words$word)) in
+        sail2_state_monad$returnS RW
+      else sail2_state_monad$bindS
+        (UsingAArch32 () ) (\ (w__11 : bool) . 
+        let (RW : 4 bits) =
+          ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 0 : int):ii)
+             (if w__11 then (vec_of_bits [B0]  :  1 words$word)
+              else (vec_of_bits [B1]  :  1 words$word))
+            :  4 words$word)) in
+        sail2_state_monad$returnS RW)) (\ (RW : 4 bits) .  sail2_state_monad$bindS
+     (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+       (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+          ( sail2_state_monad$bindS(aget_SCR_GEN ()   : ( 32 words$word) M) (\ (w__12 :  32 words$word) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__14 : bool) .  sail2_state_monad$bindS
+     (if w__14 then
+        let (RW : 4 bits) =
+          ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 2 : int):ii) (vec_of_bits [access_vec_dec RW (( 1 : int):ii)]  :  1 words$word)
+            :  4 words$word)) in
+        sail2_state_monad$returnS RW
+      else sail2_state_monad$bindS
+        (ELUsingAArch32 EL2) (\ (w__15 : bool) . 
+        let (RW : 4 bits) =
+          ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 2 : int):ii)
+             (if w__15 then (vec_of_bits [B0]  :  1 words$word)
+              else (vec_of_bits [B1]  :  1 words$word))
+            :  4 words$word)) in
+        sail2_state_monad$returnS RW)) (\ (RW : 4 bits) .  sail2_state_monad$bindS
+     (if ((~ ((HaveEL EL3)))) then
+        let (RW : 4 bits) =
+          ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 3 : int):ii) (vec_of_bits [access_vec_dec RW (( 2 : int):ii)]  :  1 words$word)
+            :  4 words$word)) in
+        sail2_state_monad$returnS RW
+      else sail2_state_monad$bindS
+        (ELUsingAArch32 EL3) (\ (w__16 : bool) . 
+        let (RW : 4 bits) =
+          ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 3 : int):ii)
+             (if w__16 then (vec_of_bits [B0]  :  1 words$word)
+              else (vec_of_bits [B1]  :  1 words$word))
+            :  4 words$word)) in
+        sail2_state_monad$returnS RW)) (\ (RW : 4 bits) .  sail2_state_monad$bindS
+     (if ((((vec_of_bits [access_vec_dec RW (( 3 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+        (undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M) (\ (w__17 :  3 words$word) . 
+        let (RW : 4 bits) = ((set_slice (( 4 : int):ii) (( 3 : int):ii) RW (( 0 : int):ii) w__17  :  4 words$word)) in
+        sail2_state_monad$returnS RW)
+      else if ((((vec_of_bits [access_vec_dec RW (( 2 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+        (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__18 :  2 words$word) . 
+        let (RW : 4 bits) = ((set_slice (( 4 : int):ii) (( 2 : int):ii) RW (( 0 : int):ii) w__18  :  4 words$word)) in
+        sail2_state_monad$returnS RW)
+      else if ((((vec_of_bits [access_vec_dec RW (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+        (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__19 :  1 words$word) . 
+        let (RW : 4 bits) = ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 0 : int):ii) w__19  :  4 words$word)) in
+        sail2_state_monad$returnS RW)
+      else sail2_state_monad$returnS RW) (\ (RW : 4 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__20 :  32 words$word) . 
+     sail2_state_monad$write_regS EDSCR_ref ((set_slice (( 32 : int):ii) (( 4 : int):ii) w__20 (( 10 : int):ii) RW  :  32 words$word))))))))))))))))))`;
+
+
+(*val Halt : mword ty6 -> M unit*)
+
+val _ = Define `
+ ((Halt:(6)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) reason=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (CTI_SignalEvent CrossTriggerIn_CrossHalt)
+   (UsingAArch32 () )) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__0 then sail2_state_monad$bindS
+      (ThisInstrAddr (( 32 : int):ii) ()   : ( 32 words$word) M) (\ (w__1 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DLR_ref w__1)
+      (GetPSRFromPSTATE ()   : ( 32 words$word) M)) (\ (w__2 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DSPSR_ref w__2)
+      (sail2_state_monad$read_regS DSPSR_ref  : ( 32 words$word) M)) (\ (w__3 :  32 words$word) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+      sail2_state_monad$write_regS
+        DSPSR_ref
+        ((update_subrange_vec_dec w__3 (( 21 : int):ii) (( 21 : int):ii) w__4.ProcState_SS  :  32 words$word))))))
+    else sail2_state_monad$bindS
+      (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__5 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DLR_EL0_ref w__5)
+      (GetPSRFromPSTATE ()   : ( 32 words$word) M)) (\ (w__6 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DSPSR_EL0_ref w__6)
+      (sail2_state_monad$read_regS DSPSR_EL0_ref  : ( 32 words$word) M)) (\ (w__7 :  32 words$word) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . 
+      sail2_state_monad$write_regS
+        DSPSR_EL0_ref
+        ((update_subrange_vec_dec w__7 (( 21 : int):ii) (( 21 : int):ii) w__8.ProcState_SS  :  32 words$word)))))))
+   (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__9 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     EDSCR_ref
+     ((update_subrange_vec_dec w__9 (( 24 : int):ii) (( 24 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  32 words$word)))
+   (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__10 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     EDSCR_ref
+     ((update_subrange_vec_dec w__10 (( 28 : int):ii) (( 28 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)))
+   (IsSecure () )) (\ (w__11 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__11 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__12 :  32 words$word) . 
+      sail2_state_monad$write_regS
+        EDSCR_ref
+        ((update_subrange_vec_dec w__12 (( 16 : int):ii) (( 16 : int):ii) (vec_of_bits [B0]  :  1 words$word)
+           :  32 words$word)))
+    else if ((HaveEL EL3)) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__13 :  32 words$word) .  sail2_state_monad$bindS
+      (ExternalSecureInvasiveDebugEnabled () ) (\ (w__14 : bool) . 
+      sail2_state_monad$write_regS
+        EDSCR_ref
+        ((update_subrange_vec_dec w__13 (( 16 : int):ii) (( 16 : int):ii)
+            (if w__14 then (vec_of_bits [B0]  :  1 words$word)
+             else (vec_of_bits [B1]  :  1 words$word))
+           :  32 words$word))))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      sail2_state_monad$assert_expS ((((vec_of_bits [access_vec_dec w__15 (( 16 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) "((EDSCR).SDD == '1')"))
+   (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__16 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     EDSCR_ref
+     ((update_subrange_vec_dec w__16 (( 20 : int):ii) (( 20 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)))
+   (UsingAArch32 () )) (\ (w__17 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__17 then sail2_state_monad$bindS
+      (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__18 : 4 bits) . 
+      let split_vec = w__18 in
+      let (tup__0, tup__1, tup__2, tup__3) =
+        ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_SS := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_A := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__21 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_I := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_F := tup__3|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__23 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_T := ((vec_of_bits [B1]  :  1 words$word))|>))))))))
+    else sail2_state_monad$bindS
+      (undefined_bitvector (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__25 : 5 bits) . 
+      let split_vec = w__25 in
+      let (tup__0, tup__1, tup__2, tup__3, tup__4) =
+        ((subrange_vec_dec split_vec (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_SS := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_D := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_A := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_I := tup__3|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__30 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__30 with<| ProcState_F := tup__4|>))))))))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__31 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__31 with<| ProcState_IL := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (StopInstructionPrefetchAndEnableITR () ))
+   (sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M)) (\ (w__32 :  32 words$word) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS EDSCR_ref ((update_subrange_vec_dec w__32 (( 5 : int):ii) (( 0 : int):ii) reason  :  32 words$word)))
+   (UpdateEDSCRFields () )))))))))))`;
+
+
+(*val aarch64_system_exceptions_debug_halt : unit -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_exceptions_debug_halt:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (Halt DebugHalt_HaltInstruction))`;
+
+
+(*val S2CacheDisabled : AccType -> M bool*)
+
+val _ = Define `
+ ((S2CacheDisabled:AccType ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (disable : 1 bits) .  sail2_state_monad$bindS
+   (ELUsingAArch32 EL2) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (if w__0 then
+      if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS HCR2_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+        sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__1 (( 1 : int):ii)]  :  1 words$word))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS HCR2_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+        sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__2 (( 0 : int):ii)]  :  1 words$word))
+    else if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+      sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 33 : int):ii)]  :  1 words$word))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+      sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__5 (( 32 : int):ii)]  :  1 words$word))) (\ (disable : 1 bits) . 
+   sail2_state_monad$returnS (((disable = (vec_of_bits [B1]  :  1 words$word)))))))))`;
+
+
+(*val S2ConvertAttrsHints : mword ty2 -> AccType -> M MemAttrHints*)
+
+val _ = Define `
+ ((S2ConvertAttrsHints:(2)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) attr acctype=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ ((IsZero attr)))) "!(IsZero(attr))")
+   (undefined_MemAttrHints () )) (\ (result : MemAttrHints) .  sail2_state_monad$bindS
+   (S2CacheDisabled acctype) (\ (w__0 : bool) . 
+   let (result : MemAttrHints) =
+     (if w__0 then
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+       (result with<| MemAttrHints_hints := MemHint_No|>)
+     else
+       let b__0 = attr in
+       if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+         (result with<| MemAttrHints_hints := MemHint_No|>)
+       else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WT|>)) in
+         (result with<| MemAttrHints_hints := MemHint_RWA|>)
+       else
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WB|>)) in
+         (result with<| MemAttrHints_hints := MemHint_RWA|>)) in
+   let (result : MemAttrHints) = ((result with<| MemAttrHints_transient := F|>)) in
+   sail2_state_monad$returnS result))))`;
+
+
+(*val S2AttrDecode : mword ty2 -> mword ty4 -> AccType -> M MemoryAttributes*)
+
+val _ = Define `
+ ((S2AttrDecode:(2)words$word ->(4)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SH attr acctype=  (sail2_state_monad$bindS
+   (undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) .  sail2_state_monad$bindS
+   (if (((((slice attr (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+      let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_typ := MemType_Device|>)) in
+      let b__0 = ((slice attr (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+      let (memattrs : MemoryAttributes) =
+        (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+          (memattrs with<| MemoryAttributes_device := DeviceType_nGnRnE|>)
+        else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+          (memattrs with<| MemoryAttributes_device := DeviceType_nGnRE|>)
+        else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+          (memattrs with<| MemoryAttributes_device := DeviceType_nGRE|>)
+        else (memattrs with<| MemoryAttributes_device := DeviceType_GRE|>)) in
+      sail2_state_monad$returnS memattrs
+    else if (((((slice attr (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) <> (vec_of_bits [B0;B0]  :  2 words$word))))
+    then
+      let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Normal|>)) in sail2_state_monad$bindS
+      (S2ConvertAttrsHints ((slice attr (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) acctype) (\ (w__0 :
+        MemAttrHints) . 
+      let memattrs = ((memattrs with<| MemoryAttributes_outer := w__0|>)) in sail2_state_monad$bindS
+      (S2ConvertAttrsHints ((slice attr (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) acctype) (\ (w__1 :
+        MemAttrHints) . 
+      let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_inner := w__1|>)) in
+      let (memattrs : MemoryAttributes) =
+        ((memattrs with<|
+          MemoryAttributes_shareable :=
+            ((((vec_of_bits [access_vec_dec SH (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))|>)) in
+      let (memattrs : MemoryAttributes) =
+        ((memattrs with<|
+          MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1;B0]  :  2 words$word))))|>)) in
+      sail2_state_monad$returnS memattrs))
+    else undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) . 
+   MemAttrDefaults memattrs))))`;
+
+
+(*val ELIsInHost : mword ty2 -> M bool*)
+
+val _ = Define `
+ ((ELIsInHost:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el=
+    (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS ( sail2_state_monad$bindS(IsSecureBelowEL3 () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))
+              (sail2_state_monad$returnS ((HaveVirtHostExt () ))))
+           ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+     (sail2_state$or_boolS (sail2_state_monad$returnS (((el = EL2))))
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((el = EL0))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))))))`;
+
+
+(*val S1TranslationRegime__0 : mword ty2 -> M (mword ty2)*)
+
+(*val S1TranslationRegime__1 : unit -> M (mword ty2)*)
+
+val _ = Define `
+ ((S1TranslationRegime__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el=
+    (if (((el <> EL0))) then sail2_state_monad$returnS el
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) ((ELUsingAArch32 EL3)))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__3 : bool) . 
+     if w__3 then sail2_state_monad$returnS EL3
+     else sail2_state_monad$bindS
+       (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveVirtHostExt () ))) ((ELIsInHost el))) (\ (w__5 : bool) . 
+       sail2_state_monad$returnS (if w__5 then EL2
+               else EL1)))))`;
+
+
+val _ = Define `
+ ((S1TranslationRegime__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   (S1TranslationRegime__0 w__0.ProcState_EL  : ( 2 words$word) M))))`;
+
+
+(*val aset_FAR__0 : mword ty2 -> mword ty64 -> M unit*)
+
+(*val aset_FAR__1 : mword ty64 -> M unit*)
+
+val _ = Define `
+ ((aset_FAR__0:(2)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime value_name=
+    (let (r : 64 bits) = value_name in
+   let pat_0 = regime in
+   if (((pat_0 = EL1))) then sail2_state_monad$write_regS FAR_EL1_ref r
+   else if (((pat_0 = EL2))) then sail2_state_monad$write_regS FAR_EL2_ref r
+   else if (((pat_0 = EL3))) then sail2_state_monad$write_regS FAR_EL3_ref r
+   else Unreachable () ))`;
+
+
+val _ = Define `
+ ((aset_FAR__1:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) . 
+   aset_FAR__0 w__0 value_name)))`;
+
+
+(*val aset_ESR__0 : mword ty2 -> mword ty32 -> M unit*)
+
+(*val aset_ESR__1 : mword ty32 -> M unit*)
+
+val _ = Define `
+ ((aset_ESR__0:(2)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime value_name=
+    (let (r : 32 bits) = value_name in
+   let pat_0 = regime in
+   if (((pat_0 = EL1))) then sail2_state_monad$write_regS ESR_EL1_ref r
+   else if (((pat_0 = EL2))) then sail2_state_monad$write_regS ESR_EL2_ref r
+   else if (((pat_0 = EL3))) then sail2_state_monad$write_regS ESR_EL3_ref r
+   else Unreachable () ))`;
+
+
+val _ = Define `
+ ((aset_ESR__1:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) . 
+   aset_ESR__0 w__0 value_name)))`;
+
+
+(*val aget_VBAR__0 : mword ty2 -> M (mword ty64)*)
+
+(*val aget_VBAR__1 : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((aget_VBAR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (r : 64 bits) . 
+   let pat_0 = regime in
+   if (((pat_0 = EL1))) then (sail2_state_monad$read_regS VBAR_EL1_ref  : ( 64 words$word) M)
+   else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS VBAR_EL2_ref  : ( 64 words$word) M)
+   else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS VBAR_EL3_ref  : ( 64 words$word) M)
+   else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`;
+
+
+val _ = Define `
+ ((aget_VBAR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) . 
+   (aget_VBAR__0 w__0  : ( 64 words$word) M))))`;
+
+
+(*val aget_SCTLR__0 : mword ty2 -> M (mword ty32)*)
+
+(*val aget_SCTLR__1 : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((aget_SCTLR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (r : 32 bits) . 
+   let pat_0 = regime in
+   if (((pat_0 = EL1))) then (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M)
+   else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M)
+   else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M)
+   else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`;
+
+
+val _ = Define `
+ ((aget_SCTLR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) . 
+   (aget_SCTLR__0 w__0  : ( 32 words$word) M))))`;
+
+
+(*val BigEndian : unit -> M bool*)
+
+val _ = Define `
+ ((BigEndian:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (bigend : bool) .  sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     let (bigend : bool) = (w__1.ProcState_E <> (vec_of_bits [B0]  :  1 words$word)) in
+     sail2_state_monad$returnS bigend)
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+     if (((w__2.ProcState_EL = EL0))) then sail2_state_monad$bindS
+       (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
+       let (bigend : bool) =
+         ((vec_of_bits [access_vec_dec w__3 (( 24 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)) in
+       sail2_state_monad$returnS bigend)
+     else sail2_state_monad$bindS
+       (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+       let (bigend : bool) =
+         ((vec_of_bits [access_vec_dec w__4 (( 25 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)) in
+       sail2_state_monad$returnS bigend))))))`;
+
+
+(*val aget_MAIR__0 : mword ty2 -> M (mword ty64)*)
+
+(*val aget_MAIR__1 : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((aget_MAIR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (r : 64 bits) . 
+   let pat_0 = regime in
+   if (((pat_0 = EL1))) then (sail2_state_monad$read_regS MAIR_EL1_ref  : ( 64 words$word) M)
+   else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS MAIR_EL2_ref  : ( 64 words$word) M)
+   else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS MAIR_EL3_ref  : ( 64 words$word) M)
+   else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`;
+
+
+val _ = Define `
+ ((aget_MAIR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) . 
+   (aget_MAIR__0 w__0  : ( 64 words$word) M))))`;
+
+
+(*val S1CacheDisabled : AccType -> M bool*)
+
+val _ = Define `
+ ((S1CacheDisabled:AccType ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (enable : 1 bits) .  sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$bindS
+   (if w__1 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+      if (((w__2.ProcState_EL = EL2))) then
+        if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS HSCTLR_ref  : ( 32 words$word) M) (\ (w__3 : 32 bits) . 
+          sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__3 (( 12 : int):ii)]  :  1 words$word))
+        else sail2_state_monad$bindS
+          (sail2_state_monad$read_regS HSCTLR_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+          sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 2 : int):ii)]  :  1 words$word))
+      else if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+        sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 12 : int):ii)]  :  1 words$word))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+        sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 2 : int):ii)]  :  1 words$word)))
+    else if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS
+      (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__9 :  32 words$word) . 
+      sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__9 (( 12 : int):ii)]  :  1 words$word))
+    else sail2_state_monad$bindS
+      (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__10 :  32 words$word) . 
+      sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__10 (( 2 : int):ii)]  :  1 words$word))) (\ (enable : 1 bits) . 
+   sail2_state_monad$returnS (((enable = (vec_of_bits [B0]  :  1 words$word))))))))))`;
+
+
+(*val ShortConvertAttrsHints : mword ty2 -> AccType -> bool -> M MemAttrHints*)
+
+val _ = Define `
+ ((ShortConvertAttrsHints:(2)words$word -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) RGN acctype secondstage=  (sail2_state_monad$bindS
+   (undefined_MemAttrHints () ) (\ (result : MemAttrHints) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((~ secondstage))) ((S1CacheDisabled acctype)))
+     (sail2_state$and_boolS (sail2_state_monad$returnS secondstage) ((S2CacheDisabled acctype)))) (\ (w__4 : bool) . 
+   let (result : MemAttrHints) =
+     (if w__4 then
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+       (result with<| MemAttrHints_hints := MemHint_No|>)
+     else
+       let b__0 = RGN in
+       if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+         (result with<| MemAttrHints_hints := MemHint_No|>)
+       else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WB|>)) in
+         (result with<| MemAttrHints_hints := MemHint_RWA|>)
+       else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WT|>)) in
+         (result with<| MemAttrHints_hints := MemHint_RA|>)
+       else
+         let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WB|>)) in
+         (result with<| MemAttrHints_hints := MemHint_RA|>)) in
+   let (result : MemAttrHints) = ((result with<| MemAttrHints_transient := F|>)) in
+   sail2_state_monad$returnS result))))`;
+
+
+(*val WalkAttrDecode : mword ty2 -> mword ty2 -> mword ty2 -> bool -> M MemoryAttributes*)
+
+val _ = Define `
+ ((WalkAttrDecode:(2)words$word ->(2)words$word ->(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SH ORGN IRGN secondstage=  (sail2_state_monad$bindS
+   (undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) . 
+   let (acctype : AccType) = AccType_NORMAL in
+   let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Normal|>)) in sail2_state_monad$bindS
+   (ShortConvertAttrsHints IRGN acctype secondstage) (\ (w__0 : MemAttrHints) . 
+   let memattrs = ((memattrs with<| MemoryAttributes_inner := w__0|>)) in sail2_state_monad$bindS
+   (ShortConvertAttrsHints ORGN acctype secondstage) (\ (w__1 : MemAttrHints) . 
+   let memattrs = ((memattrs with<| MemoryAttributes_outer := w__1|>)) in
+   let memattrs =
+     ((memattrs with<|
+       MemoryAttributes_shareable :=
+         ((((vec_of_bits [access_vec_dec SH (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))|>)) in
+   let memattrs =
+     ((memattrs with<|
+       MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1;B0]  :  2 words$word))))|>)) in
+   MemAttrDefaults memattrs)))))`;
+
+
+(*val LongConvertAttrsHints : mword ty4 -> AccType -> M MemAttrHints*)
+
+val _ = Define `
+ ((LongConvertAttrsHints:(4)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) attrfield acctype=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ ((IsZero attrfield)))) "!(IsZero(attrfield))")
+   (undefined_MemAttrHints () )) (\ (result : MemAttrHints) .  sail2_state_monad$bindS
+   (S1CacheDisabled acctype) (\ (w__0 : bool) . 
+   let (result : MemAttrHints) =
+     (if w__0 then
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+       (result with<| MemAttrHints_hints := MemHint_No|>)
+     else if (((((slice attrfield (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WT|>)) in
+       let (result : MemAttrHints) =
+         ((result with<| MemAttrHints_hints := ((slice attrfield (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word))|>)) in
+       (result with<| MemAttrHints_transient := T|>)
+     else if (((((slice attrfield (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_hints := MemHint_No|>)) in
+       (result with<| MemAttrHints_transient := F|>)
+     else if (((((slice attrfield (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+       let (result : MemAttrHints) =
+         ((result with<| MemAttrHints_attrs := ((slice attrfield (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word))|>)) in
+       let (result : MemAttrHints) = ((result with<| MemAttrHints_hints := MemAttr_WB|>)) in
+       (result with<| MemAttrHints_transient := T|>)
+     else
+       let (result : MemAttrHints) =
+         ((result with<| MemAttrHints_attrs := ((slice attrfield (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word))|>)) in
+       let (result : MemAttrHints) =
+         ((result with<| MemAttrHints_hints := ((slice attrfield (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word))|>)) in
+       (result with<| MemAttrHints_transient := F|>)) in
+   sail2_state_monad$returnS result))))`;
+
+
+(*val AArch64_S1AttrDecode : mword ty2 -> mword ty3 -> AccType -> M MemoryAttributes*)
+
+val _ = Define `
+ ((AArch64_S1AttrDecode:(2)words$word ->(3)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SH attr acctype=
+    (let uattr = (ex_nat ((lem$w2ui attr))) in sail2_state_monad$bindS
+   (undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) .  sail2_state_monad$bindS
+   (aget_MAIR__1 ()   : ( 64 words$word) M) (\ (mair : 64 bits) . 
+   let (index : int) = ((( 8 : int):ii) * uattr) in
+   let (attrfield : 8 bits) =
+     ((subrange_vec_dec mair (((( 7 : int):ii) + index)) index  :  8 words$word)) in sail2_state_monad$bindS
+   (undefined_Constraint () ) (\ (anon10 : Constraint) .  sail2_state_monad$bindS
+   (if (((((((((((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii)  :  4 words$word)) <> (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word))))))) \/ ((((((((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) /\ (((((and_vec ((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+                       (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)
+                      :  4 words$word)) <> (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))))))))) then sail2_state_monad$bindS
+      (ConstrainUnpredictableBits (( 8 : int):ii) Unpredictable_RESMAIR  : ((Constraint #  8 words$word)) M) (\ (w__0 :
+        (Constraint # 8 bits)) . 
+      let (tup__0, tup__1) = w__0 in
+      let (anon10 : Constraint) = tup__0 in
+      sail2_state_monad$returnS tup__1)
+    else sail2_state_monad$returnS attrfield) (\ (attrfield : 8 bits) .  sail2_state_monad$bindS
+   (if (((((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+      let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Device|>)) in
+      let b__0 = ((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) in
+      if (((b__0 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (memattrs : MemoryAttributes) =
+          ((memattrs with<| MemoryAttributes_device := DeviceType_nGnRnE|>)) in
+        sail2_state_monad$returnS memattrs
+      else if (((b__0 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (memattrs : MemoryAttributes) =
+          ((memattrs with<| MemoryAttributes_device := DeviceType_nGnRE|>)) in
+        sail2_state_monad$returnS memattrs
+      else if (((b__0 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (memattrs : MemoryAttributes) =
+          ((memattrs with<| MemoryAttributes_device := DeviceType_nGRE|>)) in
+        sail2_state_monad$returnS memattrs
+      else if (((b__0 = (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)))) then
+        let (memattrs : MemoryAttributes) =
+          ((memattrs with<| MemoryAttributes_device := DeviceType_GRE|>)) in
+        sail2_state_monad$returnS memattrs
+      else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS memattrs)
+    else if (((((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) <> (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+      let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Normal|>)) in sail2_state_monad$bindS
+      (LongConvertAttrsHints ((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii)  :  4 words$word)) acctype) (\ (w__1 :
+        MemAttrHints) . 
+      let memattrs = ((memattrs with<| MemoryAttributes_outer := w__1|>)) in sail2_state_monad$bindS
+      (LongConvertAttrsHints ((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) acctype) (\ (w__2 :
+        MemAttrHints) . 
+      let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_inner := w__2|>)) in
+      let (memattrs : MemoryAttributes) =
+        ((memattrs with<|
+          MemoryAttributes_shareable :=
+            ((((vec_of_bits [access_vec_dec SH (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))|>)) in
+      let (memattrs : MemoryAttributes) =
+        ((memattrs with<|
+          MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1;B0]  :  2 words$word))))|>)) in
+      sail2_state_monad$returnS memattrs))
+    else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS memattrs)) (\ (memattrs : MemoryAttributes) . 
+   MemAttrDefaults memattrs)))))))`;
+
+
+(*val IsInHost : unit -> M bool*)
+
+val _ = Define `
+ ((IsInHost:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  ELIsInHost w__0.ProcState_EL)))`;
+
+
+(*val aget_CPACR : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((aget_CPACR:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (IsInHost () ) (\ (w__0 : bool) . 
+   if w__0 then (sail2_state_monad$read_regS CPTR_EL2_ref  : ( 32 words$word) M)
+   else (sail2_state_monad$read_regS CPACR_EL1_ref  : ( 32 words$word) M))))`;
+
+
+(*val HasS2Translation : unit -> M bool*)
+
+val _ = Define `
+ ((HasS2Translation:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+        ( sail2_state_monad$bindS(IsInHost () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$returnS (((w__4.ProcState_EL = EL0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) .  sail2_state_monad$returnS (((w__5.ProcState_EL = EL1))))))))`;
+
+
+(*val AArch64_SecondStageWalk : AddressDescriptor -> mword ty64 -> AccType -> bool -> ii -> bool -> M AddressDescriptor*)
+
+val _ = Define `
+ ((AArch64_CheckAndUpdateDescriptor_SecondStage:DescriptorUpdate -> FaultRecord ->(64)words$word -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) result fault vaddress acctype iswrite s2fs1walk hwupdatewalk__arg=
+    (let hwupdatewalk = hwupdatewalk__arg in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (hw_update_AF : bool) . 
+   let (hw_update_AF : bool) =
+     (if result.DescriptorUpdate_AF then
+       if (((fault.FaultRecord_typ = Fault_None))) then T
+       else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then T
+       else F
+     else hw_update_AF) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (hw_update_AP : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (write_perm_req : bool) . 
+   let (hw_update_AP : bool) =
+     (if (((result.DescriptorUpdate_AP /\ (((fault.FaultRecord_typ = Fault_None)))))) then
+       let (write_perm_req : bool) =
+         ((((iswrite \/ ((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW))))))))) /\ ((~ s2fs1walk))) in
+       ((((write_perm_req /\ ((~ ((((((acctype = AccType_AT))) \/ (((acctype = AccType_DC))))))))))) \/ hwupdatewalk)
+     else F) in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (desc : 64 bits) .  sail2_state_monad$bindS
+   (undefined_AccessDescriptor () ) (\ (accdesc : AccessDescriptor) .  sail2_state_monad$bindS
+   (undefined_AddressDescriptor () ) (\ (descaddr2 : AddressDescriptor) .  sail2_state_monad$seqS
+   (if (((hw_update_AF \/ hw_update_AP))) then
+      let descaddr2 = (result.DescriptorUpdate_descaddr) in sail2_state_monad$bindS
+      (CreateAccessDescriptor AccType_ATOMICRW) (\ (w__0 : AccessDescriptor) . 
+      let accdesc = w__0 in sail2_state_monad$bindS
+      (aget__Mem descaddr2 (( 8 : int):ii) accdesc  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+      let desc = w__1 in
+      let (desc : 64 bits) =
+        (if hw_update_AF then
+          (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 10 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word)
+        else desc) in
+      let (desc : 64 bits) =
+        (if hw_update_AP then
+          (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word)
+        else desc) in
+      aset__Mem descaddr2 (( 8 : int):ii) accdesc desc))
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$returnS fault)))))))))`;
+
+
+(*val AArch64_CheckS2Permission : Permissions -> mword ty64 -> mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_CheckS2Permission:Permissions ->(64)words$word ->(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) perms vaddress ipaddress level acctype iswrite s2fs1walk hwupdatewalk=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+        ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2))))) ((HasS2Translation () ))) (\ (w__5 :
+     bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__5 "(((HaveEL(EL2) && !(IsSecure())) && !(ELUsingAArch32(EL2))) && HasS2Translation())")
+   (let (r : bool) =
+     ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+   let (w : bool) =
+     ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 2 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (xn : bool) .  sail2_state_monad$bindS
+   (if ((HaveExtendedExecuteNeverExt () )) then
+      let b__0 = ((concat_vec perms.Permissions_xn perms.Permissions_xxn  :  2 words$word)) in
+      if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS F
+      else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+        let (xn : bool) = (w__6.ProcState_EL = EL1) in
+        sail2_state_monad$returnS xn)
+      else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$returnS T
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . 
+        let (xn : bool) = (w__7.ProcState_EL = EL0) in
+        sail2_state_monad$returnS xn)
+    else
+      let (xn : bool) = (perms.Permissions_xn = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS xn) (\ (xn : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (failedread : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (fail1 : bool) . 
+   let ((fail1 : bool), (failedread : bool)) =
+     (if ((((((acctype = AccType_IFETCH))) /\ ((~ s2fs1walk))))) then
+       let (fail1 : bool) = xn in
+       let (failedread : bool) = T in
+       (fail1, failedread)
+     else
+       let ((fail1 : bool), (failedread : bool)) =
+         (if (((((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW)))))) /\ ((~ s2fs1walk))))) then
+           let (fail1 : bool) = (((~ r)) \/ ((~ w))) in
+           let (failedread : bool) = (~ r) in
+           (fail1, failedread)
+         else
+           let ((fail1 : bool), (failedread : bool)) =
+             (if (((iswrite /\ ((~ s2fs1walk))))) then
+               let (fail1 : bool) = (~ w) in
+               let (failedread : bool) = F in
+               (fail1, failedread)
+             else
+               let ((fail1 : bool), (failedread : bool)) =
+                 (if hwupdatewalk then
+                   let (fail1 : bool) = (~ w) in
+                   let (failedread : bool) = (~ iswrite) in
+                   (fail1, failedread)
+                 else
+                   let (fail1 : bool) = (~ r) in
+                   let (failedread : bool) = (~ iswrite) in
+                   (fail1, failedread)) in
+               (fail1, failedread)) in
+           (fail1, failedread)) in
+       (fail1, failedread)) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (domain1 : 4 bits) . 
+   if fail1 then sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__8 : 4 bits) . 
+     let domain1 = w__8 in
+     let secondstage = T in
+     AArch64_PermissionFault ipaddress level acctype ((~ failedread)) secondstage s2fs1walk)
+   else AArch64_NoFault () ))))))))))`;
+
+
+(*val IsZero_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*)
+
+val _ = Define `
+ ((IsZero_slice:'n words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) xs i l=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (sail2_state_monad$returnS ((IsZero ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)))))))`;
+
+
+(*val ZeroExtend_slice_append : forall 'n 'm 'o . Size 'm, Size 'n, Size 'o => integer -> mword 'n -> ii -> ii -> mword 'm -> M (mword 'o)*)
+
+val _ = Define `
+ ((ZeroExtend_slice_append:int -> 'n words$word -> int -> int -> 'm words$word ->(regstate)sail2_state_monad$sequential_state ->((('o words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o__tv : int) xs i l ys=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (let xs = ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) in
+   let (xs : 'o bits) =
+     ((shiftl ((extzv o__tv ((shiftr xs i  :  'n words$word))  :  'o words$word)) ((int_of_num (words$word_len ys)))  :  'o words$word)) in
+   let (ys : 'o bits) = ((extzv ((int_of_num (words$word_len xs))) ys  :  'o words$word)) in
+   sail2_state_monad$returnS ((or_vec xs ys  :  'o words$word)))))`;
+
+
+val _ = Define `
+ ((AArch64_TranslationTableWalk_SecondStage:(52)words$word ->(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress vaddress acctype iswrite s2fs1walk size1=
+    (sail2_state_monad$catch_early_returnS
+     ( sail2_state_monad$bindS(sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+              ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsSecure () )) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL2)) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+        (sail2_state_monad$liftRS ((HasS2Translation () )))) (\ (w__5 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$liftRS (sail2_state_monad$assert_expS w__5 ""))
+      (sail2_state_monad$liftRS (undefined_TLBRecord () ))) (\ (result : TLBRecord) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr : AddressDescriptor) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (baseregister : 64 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (inputaddr : 64 bits) . 
+      let (tmp_180 : MemoryAttributes) = (descaddr.AddressDescriptor_memattrs) in
+      let tmp_180 = ((tmp_180 with<| MemoryAttributes_typ := MemType_Normal|>)) in
+      let descaddr = ((descaddr with<| AddressDescriptor_memattrs := tmp_180|>)) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (startsizecheck : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsizecheck : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (startlevel : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (level : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (stride : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (firstblocklevel : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (grainsize : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hierattrsdisabled : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AP : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AF : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (singlepriv : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (lookupsecure : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (reversedescriptors : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (disabled : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (basefound : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M))) (\ (ps : 3 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_min : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_max : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (midgrain : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (largegrain : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (top : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) ipaddress  : ( 64 words$word) M))) (\ (w__6 : 64 bits) . 
+      let inputaddr = w__6 in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__7 : 32 bits) . 
+      let inputsize = ((( 64 : int):ii) - ((lem$w2ui ((slice w__7 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__8 : 32 bits) . 
+      let largegrain =
+        (((slice w__8 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__9 : 32 bits) . 
+      let midgrain =
+        (((slice w__9 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)) in
+      let inputsize_max = (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) else (( 48 : int):ii)) in sail2_state_monad$bindS
+      (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+         let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+         (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+         (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in
+         sail2_state_monad$returnS (c, inputsize))
+       else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize : ii)) = varstup in
+      let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+      (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+         let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+         (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+         (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in
+         sail2_state_monad$returnS inputsize)
+       else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__10 : 32 bits) . 
+      let ps = ((slice w__10 (( 16 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+        (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize
+                   ((((~ ((ex_int inputsize)))) + (( 64 : int):ii))))))) (\ (w__12 :
+        bool) . 
+      let basefound = w__12 in
+      let disabled = F in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTTBR_EL2_ref  : ( 64 words$word) M))) (\ (w__13 : 64 bits) . 
+      let baseregister = w__13 in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__14 : 32 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__15 : 32 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__16 : 32 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__14 (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word))
+               ((slice w__15 (( 10 : int):ii) (( 2 : int):ii)  :  2 words$word))
+               ((slice w__16 (( 12 : int):ii) (( 2 : int):ii)  :  2 words$word)) T)) (\ (w__17 : MemoryAttributes) . 
+      let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__17|>)) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M))) (\ (w__18 : 32 bits) . 
+      let reversedescriptors =
+        ((vec_of_bits [access_vec_dec w__18 (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+      let lookupsecure = F in
+      let singlepriv = T in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () )))
+        ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__19 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__19 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__20 : bool) . 
+      let update_AF = w__20 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF))))
+        ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__21 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__21 (( 22 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__22 : bool) . 
+      let update_AP = w__22 in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__23 : 32 bits) . 
+      let startlevel = (lem$w2ui ((slice w__23 (( 6 : int):ii) (( 2 : int):ii)  :  2 words$word))) in
+      let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) =
+        (if largegrain then
+          let (grainsize : ii) = ((( 16 : int):ii)) in
+          let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in
+          let (firstblocklevel : ii) = (if ((Have52BitPAExt () )) then (( 1 : int):ii) else (( 2 : int):ii)) in
+          (firstblocklevel, grainsize, level)
+        else
+          let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) =
+            (if midgrain then
+              let (grainsize : ii) = ((( 14 : int):ii)) in
+              let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in
+              let (firstblocklevel : ii) = ((( 2 : int):ii)) in
+              (firstblocklevel, grainsize, level)
+            else
+              let (grainsize : ii) = ((( 12 : int):ii)) in
+              let (level : ii) = ((( 2 : int):ii) - ((ex_int startlevel))) in
+              let (firstblocklevel : ii) = ((( 1 : int):ii)) in
+              (firstblocklevel, grainsize, level)) in
+          (firstblocklevel, grainsize, level)) in
+      let stride = (((ex_int grainsize)) - (( 3 : int):ii)) in
+      let (basefound : bool) =
+        (if largegrain then
+          if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii)))))))))
+          then
+            F
+          else basefound
+        else if midgrain then
+          if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 40 : int):ii)))))))))
+          then
+            F
+          else basefound
+        else if (((((((ex_int level)) < (( 0 : int):ii))) \/ ((((((((ex_int level)) = (( 0 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) then
+          F
+        else basefound) in
+      let inputsizecheck = inputsize in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int inputsize)) > ((ex_int ((PAMax () )))))))
+        (sail2_state$or_boolS ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL1)) (\ (w__24 : bool) .  sail2_state_monad$returnS ((~ w__24))))
+           (sail2_state_monad$returnS ((((ex_int inputsize)) > (( 40 : int):ii)))))) (\ (w__26 : bool) .  sail2_state_monad$bindS
+      (if w__26 then
+         (case ((ConstrainUnpredictable Unpredictable_LARGEIPA)) of
+           Constraint_FORCE =>
+            let (inputsize : ii) = (PAMax () ) in
+            let (inputsizecheck : ii) = (PAMax () ) in
+            sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)
+         | Constraint_FORCENOSLCHECK =>
+            let (inputsize : ii) = (PAMax () ) in
+            sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)
+         | Constraint_FAULT =>
+            let (basefound : bool) = F in
+            sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)
+         | _ => sail2_state_monad$seqS (sail2_state_monad$liftRS (Unreachable () )) (sail2_state_monad$returnS (basefound, inputsize, inputsizecheck))
+         )
+       else sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)) (\ varstup .  let ((basefound : bool), (inputsize :
+        ii), (inputsizecheck : ii)) = varstup in
+      let startsizecheck =
+        (((ex_int inputsizecheck)) -
+          (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) +
+              ((ex_int grainsize))))) in
+      let (basefound : bool) =
+        (if (((((((ex_int startsizecheck)) < (( 1 : int):ii))) \/ ((((ex_int startsizecheck)) > ((((ex_int stride)) + (( 4 : int):ii)))))))) then
+          F
+        else basefound) in
+      if (((((~ basefound)) \/ disabled))) then
+        let level = ((( 0 : int):ii)) in
+        let (tmp_190 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+        (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__27 :
+          FaultRecord) . 
+        let (tmp_190 : AddressDescriptor) = ((tmp_190 with<| AddressDescriptor_fault := w__27|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_190|>)) in
+        sail2_state_monad$returnS result)
+      else sail2_state_monad$bindS
+        (sail2_state_monad$liftRS (undefined_int () )) (\ (outputsize : ii) . 
+        let b__0 = ps in
+        let (outputsize : ii) =
+          (if (((b__0 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then (( 32 : int):ii)
+          else if (((b__0 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then (( 36 : int):ii)
+          else if (((b__0 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then (( 40 : int):ii)
+          else if (((b__0 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then (( 42 : int):ii)
+          else if (((b__0 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then (( 44 : int):ii)
+          else if (((b__0 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then (( 48 : int):ii)
+          else if (((b__0 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+            if (((((Have52BitPAExt () )) /\ largegrain))) then (( 52 : int):ii)
+            else (( 48 : int):ii)
+          else (( 48 : int):ii)) in
+        let (outputsize : ii) =
+          (if ((((ex_int outputsize)) > ((ex_int ((PAMax () )))))) then PAMax () 
+          else outputsize) in sail2_state_monad$bindS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii))))
+          ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice baseregister outputsize
+                    ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__28 :
+             bool) . 
+           sail2_state_monad$returnS ((~ w__28))))) (\ (w__29 : bool) . 
+        if w__29 then
+          let level = ((( 0 : int):ii)) in
+          let (tmp_200 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__30 :
+            FaultRecord) . 
+          let (tmp_200 : AddressDescriptor) = ((tmp_200 with<| AddressDescriptor_fault := w__30|>)) in
+          let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_200|>)) in
+          sail2_state_monad$returnS result)
+        else
+          let baselowerbound =
+            ((((( 3 : int):ii) + ((ex_int inputsize)))) -
+              (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride))))
+                  +
+                  ((ex_int grainsize))))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+          (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+          (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M)))) (\ (baseaddress : 52 bits) .  sail2_state_monad$bindS
+          (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then
+             let z = (if ((baselowerbound < (( 6 : int):ii))) then (( 6 : int):ii) else baselowerbound) in sail2_state_monad$seqS
+             (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+             (let (baseaddress : 52 bits) =
+               ((concat_vec ((slice baseregister (( 2 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                  ((slice_zeros_concat ((((((~ z)) + (( 48 : int):ii))) + z))
+                      baseregister z ((((~ z)) + (( 48 : int):ii))) z
+                     :  48 words$word))
+                 :  52 words$word)) in
+             sail2_state_monad$returnS baseaddress)
+           else
+             let (baseaddress : 52 bits) =
+               ((place_slice (( 52 : int):ii) baseregister baselowerbound
+                  ((((~ baselowerbound)) + (( 48 : int):ii))) baselowerbound
+                 :  52 words$word)) in
+             sail2_state_monad$returnS baseaddress) (\ (baseaddress : 52 bits) . 
+          let (ns_table : 1 bits) =
+            (if lookupsecure then (vec_of_bits [B0]  :  1 words$word)
+            else (vec_of_bits [B1]  :  1 words$word)) in
+          let (ap_table : 2 bits) = ((vec_of_bits [B0;B0]  :  2 words$word)) in
+          let (xn_table : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+          let (pxn_table : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+          let (addrselecttop : ii) = (((ex_int inputsize)) - (( 1 : int):ii)) in sail2_state_monad$bindS
+          (sail2_state$and_boolS
+            (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+               ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M))) (\ (w__31 : 64 bits) . 
+                sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__31 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+            ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M))) (\ (w__33 : 64 bits) . 
+             sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__33 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (apply_nvnv1_effect : bool) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (blocktranslate : bool) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (desc : 64 bits) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (undefined_AccessDescriptor () )) (\ (accdesc : AccessDescriptor) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hwupdatewalk : bool) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr2 : AddressDescriptor) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (undefined_int () )) (\ (addrselectbottom : ii) .  sail2_state_monad$bindS
+          (sail2_state$untilS (accdesc,
+                   addrselectbottom,
+                   addrselecttop,
+                   baseaddress,
+                   blocktranslate,
+                   desc,
+                   descaddr,
+                   descaddr2,
+                   level,
+                   result)
+            (\ varstup . 
+            let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
+                 baseaddress,
+                 blocktranslate,
+                 desc,
+                 descaddr,
+                 descaddr2,
+                 level,
+                 result) = varstup in
+              sail2_state_monad$returnS blocktranslate)
+            (\ varstup . 
+            let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
+                 baseaddress,
+                 blocktranslate,
+                 desc,
+                 descaddr,
+                 descaddr2,
+                 level,
+                 result) = varstup in
+              let addrselectbottom =
+                ((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride))))
+                  +
+                  ((ex_int grainsize))) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((ZeroExtend_slice_append (( 52 : int):ii) inputaddr addrselectbottom
+                        ((((((ex_int addrselecttop)) - ((ex_int addrselectbottom))))
+                            +
+                            (( 1 : int):ii))) (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                       : ( 52 words$word) M))) (\ (index : 52 bits) . 
+              let (tmp_210 : FullAddress) = (descaddr.AddressDescriptor_paddress) in
+              let tmp_210 =
+                ((tmp_210 with<|
+                  FullAddress_physicaladdress := ((or_vec baseaddress index  :  52 words$word))|>)) in
+              let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_210|>)) in
+              let (tmp_220 : FullAddress) = (descaddr.AddressDescriptor_paddress) in
+              let tmp_220 = ((tmp_220 with<| FullAddress_NS := ns_table|>)) in
+              let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_220|>)) in
+              let descaddr2 = descaddr in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) vaddress  : ( 64 words$word) M))) (\ (w__34 : 64 bits) . 
+              let descaddr2 = ((descaddr2 with<| AddressDescriptor_vaddress := w__34|>)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (CreateAccessDescriptorPTW acctype T s2fs1walk level)) (\ (w__35 :
+                AccessDescriptor) . 
+              let accdesc = w__35 in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((aget__Mem descaddr2 (( 8 : int):ii) accdesc  : ( 64 words$word) M))) (\ (w__36 : 64
+                bits) . 
+              let desc = w__36 in sail2_state_monad$bindS
+              (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc  : ( 64 words$word) M))
+               else sail2_state_monad$returnS desc) (\ (desc : 64 bits) .  sail2_state_monad$bindS
+              (if (((((((vec_of_bits [access_vec_dec desc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) \/ ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((ex_int level)) = (( 3 : int):ii))))))))))
+               then
+                 let (tmp_240 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__38 :
+                   FaultRecord) . 
+                 let tmp_240 = ((tmp_240 with<| AddressDescriptor_fault := w__38|>)) in
+                 let result = ((result with<| TLBRecord_addrdesc := tmp_240|>)) in sail2_state_monad$seqS
+                 (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR)
+                 (sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result)))
+               else if ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ (((((ex_int level)) = (( 3 : int):ii)))))))
+               then
+                 let (blocktranslate : bool) = T in
+                 sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result)
+               else sail2_state_monad$bindS
+                 (sail2_state$or_boolS
+                   (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))))))))))
+                   (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii))))
+                      ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize
+                                ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__39 :
+                         bool) . 
+                       sail2_state_monad$returnS ((~ w__39)))))) (\ (w__41 : bool) . 
+                 if w__41 then
+                   let (tmp_250 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__42 :
+                     FaultRecord) . 
+                   let tmp_250 = ((tmp_250 with<| AddressDescriptor_fault := w__42|>)) in
+                   let result = ((result with<| TLBRecord_addrdesc := tmp_250|>)) in sail2_state_monad$seqS
+                   (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR)
+                   (sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result)))
+                 else
+                   let gsz = grainsize in sail2_state_monad$seqS
+                   (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+                   (let (baseaddress : 52 bits) =
+                     (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then
+                       (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                          ((slice_zeros_concat
+                              ((((((~ gsz)) + (( 48 : int):ii))) + gsz)) desc
+                              gsz ((((~ gsz)) + (( 48 : int):ii))) gsz
+                             :  48 words$word))
+                         :  52 words$word)
+                     else
+                       (place_slice (( 52 : int):ii) desc gsz ((((~ gsz)) + (( 48 : int):ii)))
+                          gsz
+                         :  52 words$word)) in
+                   let (level : ii) = (((ex_int level)) + (( 1 : int):ii)) in
+                   let (addrselecttop : ii) = (((ex_int addrselectbottom)) - (( 1 : int):ii)) in
+                   let (blocktranslate : bool) = F in
+                   sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result)))) (\ varstup .  let ((addrselecttop :
+                ii), (baseaddress : 52 bits), (blocktranslate : bool), (level : ii), (result :
+                TLBRecord)) = varstup in
+              sail2_state_monad$returnS (accdesc,
+                      addrselectbottom,
+                      addrselecttop,
+                      baseaddress,
+                      blocktranslate,
+                      desc,
+                      descaddr,
+                      descaddr2,
+                      level,
+                      result))))))))) (\ varstup .  let ((accdesc : AccessDescriptor), (addrselectbottom :
+            ii), (addrselecttop : ii), (baseaddress : 52 bits), (blocktranslate : bool), (desc : 64
+            bits), (descaddr : AddressDescriptor), (descaddr2 : AddressDescriptor), (level : ii), (result :
+            TLBRecord)) = varstup in
+          if ((((ex_int level)) < ((ex_int firstblocklevel)))) then
+            let (tmp_260 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__43 :
+              FaultRecord) . 
+            let (tmp_260 : AddressDescriptor) = ((tmp_260 with<| AddressDescriptor_fault := w__43|>)) in
+            let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_260|>)) in
+            sail2_state_monad$returnS result)
+          else sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (contiguousbitcheck : bool) . 
+            let (contiguousbitcheck : bool) =
+              (if largegrain then
+                ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii))))
+              else if midgrain then
+                ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 30 : int):ii))))
+              else ((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii))))) in sail2_state_monad$bindS
+            (if (((contiguousbitcheck /\ ((((vec_of_bits [access_vec_dec desc (( 52 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then sail2_state_monad$bindS
+               (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (w__44 : bool) . 
+               if w__44 then
+                 let (tmp_270 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__45 :
+                   FaultRecord) . 
+                 let tmp_270 = ((tmp_270 with<| AddressDescriptor_fault := w__45|>)) in
+                 let result = ((result with<| TLBRecord_addrdesc := tmp_270|>)) in sail2_state_monad$seqS
+                 (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result))
+               else sail2_state_monad$returnS result)
+             else sail2_state_monad$returnS result) (\ (result : TLBRecord) .  sail2_state_monad$bindS
+            (sail2_state$or_boolS
+              (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))))))))))
+              (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii))))
+                 ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize
+                           ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__46 :
+                    bool) . 
+                  sail2_state_monad$returnS ((~ w__46)))))) (\ (w__48 : bool) . 
+            if w__48 then
+              let (tmp_280 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__49 :
+                FaultRecord) . 
+              let (tmp_280 : AddressDescriptor) = ((tmp_280 with<| AddressDescriptor_fault := w__49|>)) in
+              let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_280|>)) in
+              sail2_state_monad$returnS result)
+            else sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M))) (\ (outputaddress : 52
+                bits) . 
+              let asb = addrselectbottom in sail2_state_monad$seqS
+              (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+              (let (outputaddress : 52 bits) =
+                (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then
+                  (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                     ((slice_slice_concat (( 48 : int):ii) desc asb
+                         ((((~ asb)) + (( 48 : int):ii))) inputaddr (( 0 : int):ii) asb
+                        :  48 words$word))
+                    :  52 words$word)
+                else
+                  (slice_slice_concat (( 52 : int):ii) desc asb ((((~ asb)) + (( 48 : int):ii)))
+                     inputaddr (( 0 : int):ii) asb
+                    :  52 words$word)) in sail2_state_monad$bindS
+              (if ((((vec_of_bits [access_vec_dec desc (( 10 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+                 if ((~ update_AF)) then
+                   let (tmp_290 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS (AArch64_AccessFlagFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__50 :
+                     FaultRecord) . 
+                   let tmp_290 = ((tmp_290 with<| AddressDescriptor_fault := w__50|>)) in
+                   let result = ((result with<| TLBRecord_addrdesc := tmp_290|>)) in sail2_state_monad$seqS
+                   (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result))
+                 else
+                   let (tmp_300 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+                   let (tmp_300 : DescriptorUpdate) = ((tmp_300 with<| DescriptorUpdate_AF := T|>)) in
+                   let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_300|>)) in
+                   sail2_state_monad$returnS result
+               else sail2_state_monad$returnS result) (\ (result : TLBRecord) . 
+              let ((desc : 64 bits), (result : TLBRecord)) =
+                (if (((update_AP /\ ((((vec_of_bits [access_vec_dec desc (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+                  let ((desc : 64 bits), (result : TLBRecord)) =
+                    (if ((((vec_of_bits [access_vec_dec desc (( 7 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+                      let (desc : 64 bits) =
+                        ((set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+                          :  64 words$word)) in
+                      let (tmp_320 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+                      let (tmp_320 : DescriptorUpdate) =
+                        ((tmp_320 with<| DescriptorUpdate_AP := T|>)) in
+                      let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_320|>)) in
+                      (desc, result)
+                    else (desc, result)) in
+                  (desc, result)
+                else (desc, result)) in
+              let (tmp_330 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+              let tmp_330 = ((tmp_330 with<| DescriptorUpdate_descaddr := descaddr|>)) in
+              let result = ((result with<| TLBRecord_descupdate := tmp_330|>)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M))) (\ (xn : 1 bits) .  sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M))) (\ (pxn : 1 bits) . 
+              let (xn : 1 bits) =
+                (if apply_nvnv1_effect then
+                  let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)]  :  1 words$word)) in
+                  (vec_of_bits [B0]  :  1 words$word)
+                else
+                  let (xn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)]  :  1 words$word)) in
+                  let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)]  :  1 words$word)) in
+                  xn) in
+              let (contiguousbit : 1 bits) =
+                ((vec_of_bits [access_vec_dec desc (( 52 : int):ii)]  :  1 words$word)) in
+              let (nG : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 : int):ii)]  :  1 words$word)) in
+              let (sh : 2 bits) = ((slice desc (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M))) (\ (ap : 3 bits) . 
+              let (ap : 3 bits) =
+                (if apply_nvnv1_effect then
+                  (concat_vec (vec_of_bits [access_vec_dec desc (( 7 : int):ii)]  :  1 words$word)
+                     (vec_of_bits [B0;B1]  :  2 words$word)
+                    :  3 words$word)
+                else
+                  (concat_vec ((slice desc (( 6 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                     (vec_of_bits [B1]  :  1 words$word)
+                    :  3 words$word)) in
+              let (memattr : 4 bits) = ((slice desc (( 2 : int):ii) (( 4 : int):ii)  :  4 words$word)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M))) (\ (w__51 : 4 bits) . 
+              let result = ((result with<| TLBRecord_domain := w__51|>)) in
+              let result = ((result with<| TLBRecord_level := level|>)) in
+              let result =
+                ((result with<|
+                  TLBRecord_blocksize :=
+                    ((pow2
+                        (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride))))
+                            +
+                            ((ex_int grainsize))))))|>)) in
+              let (tmp_480 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+              let tmp_480 =
+                ((set_slice (( 3 : int):ii) (( 2 : int):ii) tmp_480 (( 1 : int):ii) ((slice ap (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                  :  3 words$word)) in
+              let (tmp_490 : Permissions) = (result.TLBRecord_perms) in
+              let tmp_490 = ((tmp_490 with<| Permissions_ap := tmp_480|>)) in
+              let result = ((result with<| TLBRecord_perms := tmp_490|>)) in
+              let (tmp_500 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+              let tmp_500 =
+                ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_500 (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+                  :  3 words$word)) in
+              let (tmp_510 : Permissions) = (result.TLBRecord_perms) in
+              let tmp_510 = ((tmp_510 with<| Permissions_ap := tmp_500|>)) in
+              let result = ((result with<| TLBRecord_perms := tmp_510|>)) in
+              let (tmp_520 : Permissions) = (result.TLBRecord_perms) in
+              let tmp_520 = ((tmp_520 with<| Permissions_xn := xn|>)) in
+              let result = ((result with<| TLBRecord_perms := tmp_520|>)) in
+              let (result : TLBRecord) =
+                (if ((HaveExtendedExecuteNeverExt () )) then
+                  let (tmp_530 : Permissions) = (result.TLBRecord_perms) in
+                  let (tmp_530 : Permissions) =
+                    ((tmp_530 with<|
+                      Permissions_xxn := ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)]  :  1 words$word))|>)) in
+                  (result with<| TLBRecord_perms := tmp_530|>)
+                else result) in
+              let (tmp_540 : Permissions) = (result.TLBRecord_perms) in
+              let tmp_540 = ((tmp_540 with<| Permissions_pxn := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+              let result = ((result with<| TLBRecord_perms := tmp_540|>)) in
+              let result = ((result with<| TLBRecord_nG := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+              let (tmp_550 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (S2AttrDecode sh memattr acctype)) (\ (w__52 : MemoryAttributes) . 
+              let tmp_550 = ((tmp_550 with<| AddressDescriptor_memattrs := w__52|>)) in
+              let result = ((result with<| TLBRecord_addrdesc := tmp_550|>)) in
+              let (tmp_560 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in
+              let tmp_560 = ((tmp_560 with<| FullAddress_NS := ((vec_of_bits [B1]  :  1 words$word))|>)) in
+              let (tmp_570 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+              let tmp_570 = ((tmp_570 with<| AddressDescriptor_paddress := tmp_560|>)) in
+              let result = ((result with<| TLBRecord_addrdesc := tmp_570|>)) in
+              let (tmp_580 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in
+              let tmp_580 = ((tmp_580 with<| FullAddress_physicaladdress := outputaddress|>)) in
+              let (tmp_590 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+              let tmp_590 = ((tmp_590 with<| AddressDescriptor_paddress := tmp_580|>)) in
+              let result = ((result with<| TLBRecord_addrdesc := tmp_590|>)) in
+              let (tmp_600 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (AArch64_NoFault () )) (\ (w__53 : FaultRecord) . 
+              let (tmp_600 : AddressDescriptor) = ((tmp_600 with<| AddressDescriptor_fault := w__53|>)) in
+              let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_600|>)) in
+              let (result : TLBRecord) =
+                ((result with<|
+                  TLBRecord_contiguous := (((contiguousbit = (vec_of_bits [B1]  :  1 words$word))))|>)) in
+              let (result : TLBRecord) =
+                (if ((HaveCommonNotPrivateTransExt () )) then
+                  (result with<|
+                    TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 : int):ii)]  :  1 words$word))|>)
+                else result) in
+              sail2_state_monad$returnS result))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
+
+
+val _ = Define `
+ ((AArch64_SecondStageTranslate:AddressDescriptor ->(64)words$word -> AccType -> bool -> bool -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk=  (sail2_state_monad$bindS
+   (HasS2Translation () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__0 "HasS2Translation()")
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 12 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (s2_enabled : bool) . 
+   let (secondstage : bool) = T in sail2_state_monad$bindS
+   (undefined_AddressDescriptor () ) (\ (result : AddressDescriptor) .  sail2_state_monad$bindS
+   (undefined_TLBRecord () ) (\ (S2 : TLBRecord) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) . 
+   if s2_enabled then
+     let ipaddress =
+       ((slice S1.AddressDescriptor_paddress.FullAddress_physicaladdress (( 0 : int):ii) (( 52 : int):ii)  :  52 words$word)) in sail2_state_monad$bindS
+     (AArch64_TranslationTableWalk_SecondStage ipaddress vaddress acctype iswrite s2fs1walk size1) (\ (w__3 :
+       TLBRecord) . 
+     let S2 = w__3 in sail2_state_monad$bindS
+     (if ((((((((((((((~ wasaligned)) /\ (((acctype <> AccType_IFETCH)))))) \/ (((acctype = AccType_DCZVA)))))) /\ (((S2.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ ((~ ((IsFault S2.TLBRecord_addrdesc))))))) then
+        let (tmp_710 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS
+        (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__4 : FaultRecord) . 
+        let (tmp_710 : AddressDescriptor) = ((tmp_710 with<| AddressDescriptor_fault := w__4|>)) in
+        let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := tmp_710|>)) in
+        sail2_state_monad$returnS S2)
+      else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) .  sail2_state_monad$bindS
+     (if ((~ ((IsFault S2.TLBRecord_addrdesc)))) then
+        let (tmp_720 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS
+        (AArch64_CheckS2Permission S2.TLBRecord_perms vaddress ipaddress S2.TLBRecord_level acctype
+          iswrite s2fs1walk hwupdatewalk) (\ (w__5 : FaultRecord) . 
+        let (tmp_720 : AddressDescriptor) = ((tmp_720 with<| AddressDescriptor_fault := w__5|>)) in
+        let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := tmp_720|>)) in
+        sail2_state_monad$returnS S2)
+      else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) .  sail2_state_monad$bindS
+     (if (((((((((((~ s2fs1walk)) /\ ((~ ((IsFault S2.TLBRecord_addrdesc))))))) /\ (((S2.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ (((acctype = AccType_IFETCH)))))) then sail2_state_monad$bindS
+        (AArch64_InstructionDevice S2.TLBRecord_addrdesc vaddress ipaddress S2.TLBRecord_level
+          acctype iswrite secondstage s2fs1walk) (\ (w__6 : AddressDescriptor) . 
+        let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := w__6|>)) in
+        sail2_state_monad$returnS S2)
+      else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) .  sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((s2fs1walk /\ ((~ ((IsFault S2.TLBRecord_addrdesc))))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 2 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       (sail2_state_monad$returnS (((S2.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device))))) (\ (w__9 : bool) .  sail2_state_monad$bindS
+     (if w__9 then
+        let (tmp_730 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS
+        (AArch64_PermissionFault ipaddress S2.TLBRecord_level acctype iswrite secondstage s2fs1walk) (\ (w__10 :
+          FaultRecord) . 
+        let (tmp_730 : AddressDescriptor) = ((tmp_730 with<| AddressDescriptor_fault := w__10|>)) in
+        let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := tmp_730|>)) in
+        sail2_state_monad$returnS S2)
+      else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) . 
+     let (tmp_740 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS
+     (AArch64_CheckAndUpdateDescriptor_SecondStage S2.TLBRecord_descupdate
+       S2.TLBRecord_addrdesc.AddressDescriptor_fault vaddress acctype iswrite s2fs1walk hwupdatewalk) (\ (w__11 :
+       FaultRecord) . 
+     let tmp_740 = ((tmp_740 with<| AddressDescriptor_fault := w__11|>)) in
+     let S2 = ((S2 with<| TLBRecord_addrdesc := tmp_740|>)) in
+     CombineS1S2Desc S1 S2.TLBRecord_addrdesc)))))))
+   else sail2_state_monad$returnS S1)))))))`;
+
+
+val _ = Define `
+ ((AArch64_SecondStageWalk:AddressDescriptor ->(64)words$word -> AccType -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) S1 vaddress acctype iswrite size1 hwupdatewalk=  (sail2_state_monad$bindS
+   (HasS2Translation () ) (\ (w__0 : bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__0 "HasS2Translation()")
+   (let (s2fs1walk : bool) = T in
+   let (wasaligned : bool) = T in
+   AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk))))`;
+
+
+(*val DoubleLockStatus : unit -> M bool*)
+
+val _ = Define `
+ ((DoubleLockStatus:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (ELUsingAArch32 EL1) (\ (w__0 : bool) . 
+   if w__0 then
+     sail2_state$and_boolS
+       (sail2_state$and_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGOSDLR_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGPRCR_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(Halted () ) (\ (w__4 : bool) .  sail2_state_monad$returnS ((~ w__4))))
+   else
+     sail2_state$and_boolS
+       (sail2_state$and_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS OSDLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGPRCR_EL1_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(Halted () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))))`;
+
+
+(*val HaltingAllowed : unit -> M bool*)
+
+val _ = Define `
+ ((HaltingAllowed:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$or_boolS ((Halted () )) ((DoubleLockStatus () ))) (\ (w__2 : bool) . 
+   if w__2 then sail2_state_monad$returnS F
+   else sail2_state_monad$bindS
+     (IsSecure () ) (\ (w__3 : bool) . 
+     if w__3 then ExternalSecureInvasiveDebugEnabled () 
+     else ExternalInvasiveDebugEnabled () ))))`;
+
+
+(*val system_exceptions_debug_halt_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((system_exceptions_debug_halt_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 14 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+     ( sail2_state_monad$bindS(HaltingAllowed () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))) (\ (w__2 : bool) .  sail2_state_monad$seqS
+   (if w__2 then UndefinedFault ()  else sail2_state_monad$returnS () ) (aarch64_system_exceptions_debug_halt () ))))`;
+
+
+(*val HaltOnBreakpointOrWatchpoint : unit -> M bool*)
+
+val _ = Define `
+ ((HaltOnBreakpointOrWatchpoint:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$and_boolS
+     (sail2_state$and_boolS ((HaltingAllowed () ))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 14 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS OSLSR_EL1_ref  : ( 32 words$word) M) (\ (w__3 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))))`;
+
+
+(*val DebugTargetFrom : bool -> M (mword ty2)*)
+
+val _ = Define `
+ ((DebugTargetFrom:bool ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) secure=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (if (((((HaveEL EL2)) /\ ((~ secure))))) then sail2_state_monad$bindS
+      (ELUsingAArch32 EL2) (\ (w__0 : bool) . 
+      if w__0 then
+        sail2_state$or_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HDCR_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+      else
+        sail2_state$or_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+    else sail2_state_monad$returnS F) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (target : 2 bits) . 
+   let (target : 2 bits) =
+     (if route_to_el2 then EL2
+     else if ((((((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))) /\ secure))) then EL3
+     else EL1) in
+   sail2_state_monad$returnS target)))))`;
+
+
+(*val DebugTarget : unit -> M (mword ty2)*)
+
+val _ = Define `
+ ((DebugTarget:unit ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (IsSecure () ) (\ (secure : bool) .  (DebugTargetFrom secure  : ( 2 words$word) M))))`;
+
+
+(*val SSAdvance : unit -> M unit*)
+
+val _ = Define `
+ ((SSAdvance:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (DebugTarget ()   : ( 2 words$word) M) (\ (target : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS ( sail2_state_monad$bindS(ELUsingAArch32 target) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (step_enabled : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS step_enabled)
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+      sail2_state_monad$returnS (((w__2.ProcState_SS = (vec_of_bits [B1]  :  1 words$word))))))) (\ (active_not_pending :
+     bool) . 
+   if active_not_pending then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_SS := ((vec_of_bits [B0]  :  1 words$word))|>))
+   else sail2_state_monad$returnS () )))))`;
+
+
+(*val ConditionHolds : mword ty4 -> M bool*)
+
+val _ = Define `
+ ((ConditionHolds:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cond=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (result : bool) . 
+   let b__0 = ((slice cond (( 1 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+      let (result : bool) = (w__0.ProcState_Z = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS result)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+      let (result : bool) = (w__1.ProcState_C = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS result)
+    else if (((b__0 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+      let (result : bool) = (w__2.ProcState_N = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS result)
+    else if (((b__0 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+      let (result : bool) = (w__3.ProcState_V = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS result)
+    else if (((b__0 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+      sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+         sail2_state_monad$returnS (((w__4.ProcState_C = (vec_of_bits [B1]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+         sail2_state_monad$returnS (((w__5.ProcState_Z = (vec_of_bits [B0]  :  1 words$word))))))
+    else if (((b__0 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . 
+      let (result : bool) = (w__7.ProcState_N = w__8.ProcState_V) in
+      sail2_state_monad$returnS result))
+    else if (((b__0 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+      sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) .  sail2_state_monad$bindS
+         (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+         sail2_state_monad$returnS (((w__9.ProcState_N = w__10.ProcState_V))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+         sail2_state_monad$returnS (((w__11.ProcState_Z = (vec_of_bits [B0]  :  1 words$word))))))
+    else sail2_state_monad$returnS T) (\ (result : bool) . 
+   let (result : bool) =
+     (if (((((((vec_of_bits [access_vec_dec cond (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((cond <> (vec_of_bits [B1;B1;B1;B1]  :  4 words$word))))))) then
+       ~ result
+     else result) in
+   sail2_state_monad$returnS result))))`;
+
+
+(*val aarch64_integer_conditional_select : mword ty4 -> ii -> ii -> bool -> bool -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_conditional_select:(4)words$word -> int -> int -> bool -> bool -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition d l__153 else_inc else_inv m n=
+    (if (((l__153 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__0 : bool) . 
+     let (result : 8 bits) =
+       (if w__0 then operand1
+       else
+         let (result : 8 bits) = operand2 in
+         let (result : 8 bits) = (if else_inv then (not_vec result  :  8 words$word) else result) in
+         if else_inc then (add_vec_int result (( 1 : int):ii)  :  8 words$word)
+         else result) in
+     aset_X d result))))
+   else if (((l__153 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__1 : bool) . 
+     let (result : 16 bits) =
+       (if w__1 then operand1
+       else
+         let (result : 16 bits) = operand2 in
+         let (result : 16 bits) = (if else_inv then (not_vec result  :  16 words$word) else result) in
+         if else_inc then (add_vec_int result (( 1 : int):ii)  :  16 words$word)
+         else result) in
+     aset_X d result))))
+   else if (((l__153 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__2 : bool) . 
+     let (result : 32 bits) =
+       (if w__2 then operand1
+       else
+         let (result : 32 bits) = operand2 in
+         let (result : 32 bits) = (if else_inv then (not_vec result  :  32 words$word) else result) in
+         if else_inc then (add_vec_int result (( 1 : int):ii)  :  32 words$word)
+         else result) in
+     aset_X d result))))
+   else if (((l__153 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__3 : bool) . 
+     let (result : 64 bits) =
+       (if w__3 then operand1
+       else
+         let (result : 64 bits) = operand2 in
+         let (result : 64 bits) = (if else_inv then (not_vec result  :  64 words$word) else result) in
+         if else_inc then (add_vec_int result (( 1 : int):ii)  :  64 words$word)
+         else result) in
+     aset_X d result))))
+   else if (((l__153 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__4 : bool) . 
+     let (result : 128 bits) =
+       (if w__4 then operand1
+       else
+         let (result : 128 bits) = operand2 in
+         let (result : 128 bits) = (if else_inv then (not_vec result  :  128 words$word) else result) in
+         if else_inc then (add_vec_int result (( 1 : int):ii)  :  128 words$word)
+         else result) in
+     aset_X d result))))
+   else
+     let dbytes = (ex_int ((l__153 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_conditional_select_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_conditional_select_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm cond o2 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (condition : 4 bits) = cond in
+   let (else_inv : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   let (else_inc : bool) = (o2 = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_integer_conditional_select condition d datasize else_inc else_inv m n)))`;
+
+
+(*val aarch64_integer_conditional_compare_register : mword ty4 -> ii -> mword ty4 -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_conditional_compare_register:(4)words$word -> int ->(4)words$word -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition l__148 flags__arg m n sub_op=
+    (if (((l__148 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) . 
+     let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (anon10 : 8 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__0 : bool) . 
+     let (flags :  4 words$word) =
+       (if w__0 then
+         let ((carry_in : 1 bits), (operand2 : 8 bits)) =
+           (if sub_op then
+             let (operand2 : 8 bits) = ((not_vec operand2  :  8 words$word)) in
+             let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+             (carry_in, operand2)
+           else (carry_in, operand2)) in
+         let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in  : ( 8 words$word #  4 words$word))) in
+         let (anon10 : 8 bits) = tup__0 in
+         tup__1
+       else flags) in
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__148 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) . 
+     let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (anon10 : 16 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__5 : bool) . 
+     let (flags :  4 words$word) =
+       (if w__5 then
+         let ((carry_in : 1 bits), (operand2 : 16 bits)) =
+           (if sub_op then
+             let (operand2 : 16 bits) = ((not_vec operand2  :  16 words$word)) in
+             let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+             (carry_in, operand2)
+           else (carry_in, operand2)) in
+         let (tup__0, tup__1) =
+           ((AddWithCarry operand1 operand2 carry_in  : ( 16 words$word #  4 words$word))) in
+         let (anon10 : 16 bits) = tup__0 in
+         tup__1
+       else flags) in
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__148 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) . 
+     let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (anon10 : 32 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__10 : bool) . 
+     let (flags :  4 words$word) =
+       (if w__10 then
+         let ((carry_in : 1 bits), (operand2 : 32 bits)) =
+           (if sub_op then
+             let (operand2 : 32 bits) = ((not_vec operand2  :  32 words$word)) in
+             let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+             (carry_in, operand2)
+           else (carry_in, operand2)) in
+         let (tup__0, tup__1) =
+           ((AddWithCarry operand1 operand2 carry_in  : ( 32 words$word #  4 words$word))) in
+         let (anon10 : 32 bits) = tup__0 in
+         tup__1
+       else flags) in
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__148 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) . 
+     let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (anon10 : 64 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__15 : bool) . 
+     let (flags :  4 words$word) =
+       (if w__15 then
+         let ((carry_in : 1 bits), (operand2 : 64 bits)) =
+           (if sub_op then
+             let (operand2 : 64 bits) = ((not_vec operand2  :  64 words$word)) in
+             let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+             (carry_in, operand2)
+           else (carry_in, operand2)) in
+         let (tup__0, tup__1) =
+           ((AddWithCarry operand1 operand2 carry_in  : ( 64 words$word #  4 words$word))) in
+         let (anon10 : 64 bits) = tup__0 in
+         tup__1
+       else flags) in
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__148 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) . 
+     let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (anon10 : 128 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__20 : bool) . 
+     let (flags :  4 words$word) =
+       (if w__20 then
+         let ((carry_in : 1 bits), (operand2 : 128 bits)) =
+           (if sub_op then
+             let (operand2 : 128 bits) = ((not_vec operand2  :  128 words$word)) in
+             let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+             (carry_in, operand2)
+           else (carry_in, operand2)) in
+         let (tup__0, tup__1) =
+           ((AddWithCarry operand1 operand2 carry_in  : ( 128 words$word #  4 words$word))) in
+         let (anon10 : 128 bits) = tup__0 in
+         tup__1
+       else flags) in
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_V := tup__3|>))))))))))
+   else
+     let dbytes = (ex_int ((l__148 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val integer_conditional_compare_register_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((integer_conditional_compare_register_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm cond o2 Rn o3 nzcv1=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   let (condition : 4 bits) = cond in
+   let (flags : 4 bits) = nzcv1 in
+   aarch64_integer_conditional_compare_register condition datasize flags m n sub_op)))`;
+
+
+(*val aarch64_integer_conditional_compare_immediate : forall 'datasize. Size 'datasize => mword ty4 -> itself 'datasize -> mword ty4 -> mword 'datasize -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_conditional_compare_immediate:(4)words$word -> 'datasize itself ->(4)words$word -> 'datasize words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition datasize flags__arg imm n sub_op=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (let flags = flags__arg in sail2_state_monad$bindS
+   (aget_X datasize n  : ( 'datasize words$word) M) (\ (operand1 : 'datasize bits) . 
+   let (operand2 : 'datasize bits) = imm in
+   let (carry_in : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (anon10 : 'datasize bits) .  sail2_state_monad$bindS
+   (ConditionHolds condition) (\ (w__0 : bool) . 
+   let (flags :  4 words$word) =
+     (if w__0 then
+       let ((carry_in : 1 bits), (operand2 : 'datasize bits)) =
+         (if sub_op then
+           let (operand2 : 'datasize bits) = ((not_vec operand2  :  'datasize words$word)) in
+           let (carry_in : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+           (carry_in, operand2)
+         else (carry_in, operand2)) in
+       let (tup__0, tup__1) =
+         ((AddWithCarry operand1 operand2 carry_in  : ( 'datasize words$word #  4 words$word))) in
+       let (anon10 : 'datasize bits) = tup__0 in
+       tup__1
+     else flags) in
+   let (tup__0, tup__1, tup__2, tup__3) =
+     ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+      (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+      (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+      (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_N := tup__0|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_Z := tup__1|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_C := tup__2|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . 
+   sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_V := tup__3|>)))))))))))`;
+
+
+(*val integer_conditional_compare_immediate_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((integer_conditional_compare_immediate_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 op S1 imm5 cond o2 Rn o3 nzcv1=
+    (if (((b__0 = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+     let (condition : 4 bits) = cond in
+     let (flags : 4 bits) = nzcv1 in sail2_state_monad$bindS
+     (ZeroExtend__0 imm5 ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (imm : 32
+       bits) . 
+     aarch64_integer_conditional_compare_immediate condition
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) flags imm n sub_op))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+     let (condition : 4 bits) = cond in
+     let (flags : 4 bits) = nzcv1 in sail2_state_monad$bindS
+     (ZeroExtend__0 imm5 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (imm : 64
+       bits) . 
+     aarch64_integer_conditional_compare_immediate condition
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) flags imm n sub_op))))`;
+
+
+(*val ConditionSyndrome : unit -> M (mword ty5)*)
+
+val _ = Define `
+ ((ConditionSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->((((5)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector (( 5 : int):ii)  : ( 5 words$word) M) (\ (syndrome : 5 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (cond : 4 bits) .  sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (AArch32_CurrentCond ()   : ( 4 words$word) M) (\ (w__1 : 4 bits) . 
+     let cond = w__1 in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+     if (((w__2.ProcState_T = (vec_of_bits [B0]  :  1 words$word)))) then
+       let syndrome =
+         ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  5 words$word)) in sail2_state_monad$bindS
+       (sail2_state$and_boolS ((ConditionHolds cond)) ((ConstrainUnpredictableBool Unpredictable_ESRCONDPASS))) (\ (w__5 :
+         bool) . 
+       let (syndrome : 5 bits) =
+         (if w__5 then
+           (set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+             :  5 words$word)
+         else (set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) cond  :  5 words$word)) in
+       sail2_state_monad$returnS syndrome)
+     else if ((IMPDEF_boolean "Condition valid for trapped T32")) then
+       let (syndrome : 5 bits) =
+         ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  5 words$word)) in
+       let (syndrome : 5 bits) = ((set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) cond  :  5 words$word)) in
+       sail2_state_monad$returnS syndrome
+     else
+       let syndrome =
+         ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  5 words$word)) in sail2_state_monad$bindS
+       (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__6 :  4 words$word) . 
+       let (syndrome : 5 bits) = ((set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) w__6  :  5 words$word)) in
+       sail2_state_monad$returnS syndrome)))
+   else
+     let (syndrome : 5 bits) =
+       ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  5 words$word)) in
+     let (syndrome : 5 bits) =
+       ((set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+         :  5 words$word)) in
+     sail2_state_monad$returnS syndrome)))))`;
+
+
+(*val BranchToAddr : forall 'N . Size 'N => mword 'N -> BranchType -> M unit*)
+
+val _ = Define `
+ ((BranchToAddr:'N words$word -> BranchType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target branch_type=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS BranchTaken_ref T)
+   (let (_ : unit) = (Hint_Branch branch_type) in
+   if (((((int_of_num (words$word_len target))) = (( 32 : int):ii)))) then sail2_state_monad$bindS
+     (UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS w__0 "UsingAArch32()")
+     (ZeroExtend__1 (( 64 : int):ii) target  : ( 64 words$word) M)) (\ (w__1 : 64 bits) . 
+     sail2_state_monad$write_regS PC_ref w__1))
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state_monad$returnS (((((int_of_num (words$word_len target))) = (( 64 : int):ii)))))
+       ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2))))) (\ (w__3 : bool) .  sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS w__3 "((N == 64) && !(UsingAArch32()))")
+     (sail2_state_monad$write_regS PC_ref ((slice target (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word)))))))`;
+
+
+(*val BadMode : mword ty5 -> M bool*)
+
+val _ = Define `
+ ((BadMode:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) . 
+   let pat_0 = mode in
+   let (valid_name : bool) =
+     (if (((pat_0 = M32_Monitor))) then HaveAArch32EL EL3
+     else if (((pat_0 = M32_Hyp))) then HaveAArch32EL EL2
+     else if (((pat_0 = M32_FIQ))) then HaveAArch32EL EL1
+     else if (((pat_0 = M32_IRQ))) then HaveAArch32EL EL1
+     else if (((pat_0 = M32_Svc))) then HaveAArch32EL EL1
+     else if (((pat_0 = M32_Abort))) then HaveAArch32EL EL1
+     else if (((pat_0 = M32_Undef))) then HaveAArch32EL EL1
+     else if (((pat_0 = M32_System))) then HaveAArch32EL EL1
+     else if (((pat_0 = M32_User))) then HaveAArch32EL EL0
+     else F) in
+   sail2_state_monad$returnS ((~ valid_name)))))`;
+
+
+(*val aset_Rmode : ii -> mword ty5 -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((aset_Rmode:int ->(5)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n mode value_name=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 14 : int):ii)))))) "((n >= 0) && (n <= 14))")
+   (IsSecure () )) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ w__0)) then sail2_state_monad$assert_expS (((mode <> M32_Monitor))) "(mode != M32_Monitor)"
+    else sail2_state_monad$returnS () )
+   (BadMode mode)) (\ (w__1 : bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "!(BadMode(mode))")
+   (if (((mode = M32_Monitor))) then
+     if (((n = (( 13 : int):ii)))) then sail2_state_monad$write_regS SP_mon_ref value_name
+     else if (((n = (( 14 : int):ii)))) then sail2_state_monad$write_regS LR_mon_ref value_name
+     else sail2_state_monad$bindS
+       (sail2_state_monad$read_regS R_ref) (\ (w__2 : ( 64 bits) list) . 
+       let (tmp_10 : 64 bits) = ((access_list_dec w__2 n  :  64 words$word)) in
+       let tmp_10 = ((update_subrange_vec_dec tmp_10 (( 31 : int):ii) (( 0 : int):ii) value_name  :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS R_ref) (\ (w__3 : ( 64 words$word) list) . 
+       sail2_state_monad$write_regS R_ref ((update_list_dec w__3 n tmp_10  : ( 64 words$word) list))))
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((HighestELUsingAArch32 () )))))
+       ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER))) (\ (w__5 : bool) . 
+     if w__5 then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS R_ref) (\ (w__6 : ( 64 words$word) list) .  sail2_state_monad$bindS
+       (LookUpRIndex n mode) (\ (w__7 : ii) .  sail2_state_monad$bindS
+       (ZeroExtend__0 value_name ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__8 :
+          64 words$word) . 
+       sail2_state_monad$write_regS R_ref ((update_list_dec w__6 w__7 w__8  : ( 64 words$word) list)))))
+     else sail2_state_monad$bindS
+       (sail2_state_monad$read_regS R_ref) (\ (w__9 : ( 64 bits) list) .  sail2_state_monad$bindS
+       (LookUpRIndex n mode) (\ (w__10 : ii) . 
+       let (tmp_20 : 64 bits) = ((access_list_dec w__9 w__10  :  64 words$word)) in
+       let tmp_20 = ((update_subrange_vec_dec tmp_20 (( 31 : int):ii) (( 0 : int):ii) value_name  :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS R_ref) (\ (w__11 : ( 64 words$word) list) .  sail2_state_monad$bindS
+       (LookUpRIndex n mode) (\ (w__12 : ii) . 
+       sail2_state_monad$write_regS R_ref ((update_list_dec w__11 w__12 tmp_20  : ( 64 words$word) list))))))))))))`;
+
+
+(*val aset_R : ii -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((aset_R:int ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n value_name=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  aset_Rmode n w__0.ProcState_M value_name)))`;
+
+
+(*val set_LR : mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_LR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name=  (aset_R (( 14 : int):ii) value_name))`;
+
+
+(*val ELFromM32 : mword ty5 -> M (bool * mword ty2)*)
+
+val _ = Define `
+ ((ELFromM32:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (el : 2 bits) .  sail2_state_monad$bindS
+   (BadMode mode) (\ (w__0 : bool) . 
+   let (valid_name : bool) = (~ w__0) in
+   let pat_0 = mode in sail2_state_monad$bindS
+   (if (((pat_0 = M32_Monitor))) then
+      let (el : 2 bits) = EL3 in
+      sail2_state_monad$returnS (el, valid_name)
+    else if (((pat_0 = M32_Hyp))) then
+      let el = EL2 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS valid_name)
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))
+           ( sail2_state_monad$bindS(aget_SCR_GEN ()   : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (w__3 : bool) . 
+      let (valid_name : bool) = w__3 in
+      sail2_state_monad$returnS (el, valid_name))
+    else if (((pat_0 = M32_FIQ))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__5 : bool) . 
+      let (el : 2 bits) = (if w__5 then EL3 else EL1) in
+      sail2_state_monad$returnS (el, valid_name))
+    else if (((pat_0 = M32_IRQ))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__7 : bool) . 
+      let (el : 2 bits) = (if w__7 then EL3 else EL1) in
+      sail2_state_monad$returnS (el, valid_name))
+    else if (((pat_0 = M32_Svc))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__8 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__9 : bool) . 
+      let (el : 2 bits) = (if w__9 then EL3 else EL1) in
+      sail2_state_monad$returnS (el, valid_name))
+    else if (((pat_0 = M32_Abort))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__11 : bool) . 
+      let (el : 2 bits) = (if w__11 then EL3 else EL1) in
+      sail2_state_monad$returnS (el, valid_name))
+    else if (((pat_0 = M32_Undef))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__12 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__13 : bool) . 
+      let (el : 2 bits) = (if w__13 then EL3 else EL1) in
+      sail2_state_monad$returnS (el, valid_name))
+    else if (((pat_0 = M32_System))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__14 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__15 : bool) . 
+      let (el : 2 bits) = (if w__15 then EL3 else EL1) in
+      sail2_state_monad$returnS (el, valid_name))
+    else
+      let ((el : 2 bits), (valid_name : bool)) =
+        (if (((pat_0 = M32_User))) then
+          let (el : 2 bits) = EL0 in
+          (el, valid_name)
+        else
+          let (valid_name : bool) = F in
+          (el, valid_name)) in
+      sail2_state_monad$returnS (el, valid_name)) (\ varstup .  let ((el : 2 bits), (valid_name : bool)) = varstup in sail2_state_monad$bindS
+   (if ((~ valid_name)) then (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M)
+    else sail2_state_monad$returnS el) (\ (el : 2 bits) . 
+   sail2_state_monad$returnS (valid_name, el)))))))`;
+
+
+(*val ELFromSPSR : mword ty32 -> M (bool * mword ty2)*)
+
+val _ = Define `
+ ((ELFromSPSR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (el : 2 bits) .  sail2_state_monad$bindS
+   (if ((((vec_of_bits [access_vec_dec spsr (( 4 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+      let el = ((slice spsr (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) in sail2_state_monad$bindS
+      (if ((HighestELUsingAArch32 () )) then sail2_state_monad$returnS F
+       else if ((~ ((HaveEL el)))) then sail2_state_monad$returnS F
+       else if ((((vec_of_bits [access_vec_dec spsr (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+         sail2_state_monad$returnS F
+       else if ((((((el = EL0))) /\ ((((vec_of_bits [access_vec_dec spsr (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+         sail2_state_monad$returnS F
+       else sail2_state_monad$bindS
+         (sail2_state$and_boolS (sail2_state_monad$returnS ((((((el = EL2))) /\ ((HaveEL EL3))))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__1 : bool) . 
+         let (valid_name : bool) = (if w__1 then F else T) in
+         sail2_state_monad$returnS valid_name)) (\ (valid_name : bool) . 
+      sail2_state_monad$returnS (el, valid_name))
+    else if ((~ ((HaveAnyAArch32 () )))) then
+      let (valid_name : bool) = F in
+      sail2_state_monad$returnS (el, valid_name)
+    else sail2_state_monad$bindS
+      (ELFromM32 ((slice spsr (( 0 : int):ii) (( 5 : int):ii)  :  5 words$word))  : ((bool #  2 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+      let (valid_name : bool) = tup__0 in
+      let (el : 2 bits) = tup__1 in
+      sail2_state_monad$returnS (el, valid_name))) (\ varstup .  let ((el : 2 bits), (valid_name : bool)) = varstup in sail2_state_monad$bindS
+   (if ((~ valid_name)) then (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M)
+    else sail2_state_monad$returnS el) (\ (el : 2 bits) . 
+   sail2_state_monad$returnS (valid_name, el)))))))`;
+
+
+(*val IllegalExceptionReturn : mword ty32 -> M bool*)
+
+val _ = Define `
+ ((IllegalExceptionReturn:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (target : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) .  sail2_state_monad$bindS
+   (ELFromSPSR spsr  : ((bool #  2 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let valid_name = tup__0 in
+   let target = tup__1 in
+   if ((~ valid_name)) then sail2_state_monad$returnS T
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+     if ((((lem$w2ui target)) > ((lem$w2ui w__0.ProcState_EL)))) then sail2_state_monad$returnS T
+     else
+       let (spsr_mode_is_aarch32 : bool) =
+         ((vec_of_bits [access_vec_dec spsr (( 4 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$undefined_boolS () ) (\ (target_el_is_aarch32 : bool) .  sail2_state_monad$bindS
+       (sail2_state_monad$undefined_boolS () ) (\ (known : bool) .  sail2_state_monad$bindS
+       (ELUsingAArch32K target) (\ varstup .  let (tup__0, tup__1) = varstup in
+       let known = tup__0 in
+       let target_el_is_aarch32 = tup__1 in sail2_state_monad$bindS
+       (sail2_state$or_boolS (sail2_state_monad$returnS known)
+         (sail2_state$and_boolS (sail2_state_monad$returnS (((target = EL0))))
+            ( sail2_state_monad$bindS(ELUsingAArch32 EL1) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))) (\ (w__3 : bool) .  sail2_state_monad$seqS
+       (sail2_state_monad$assert_expS w__3 "(known || ((target == EL0) && !(ELUsingAArch32(EL1))))")
+       (if (((known /\ ((neq_bool spsr_mode_is_aarch32 target_el_is_aarch32))))) then sail2_state_monad$returnS T
+       else sail2_state_monad$bindS
+         (sail2_state$and_boolS ((UsingAArch32 () )) (sail2_state_monad$returnS ((~ spsr_mode_is_aarch32)))) (\ (w__5 : bool) . 
+         if w__5 then sail2_state_monad$returnS T
+         else sail2_state_monad$bindS
+           (sail2_state$and_boolS
+             (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ (((target = EL1)))))))
+                ( sail2_state_monad$bindS(IsSecureBelowEL3 () ) (\ (w__6 : bool) .  sail2_state_monad$returnS ((~ w__6)))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__9 : bool) . 
+           sail2_state_monad$returnS (if w__9 then T
+                   else F))))))))))))))`;
+
+
+(*val AArch32_WriteMode : mword ty5 -> M unit*)
+
+val _ = Define `
+ ((AArch32_WriteMode:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (el : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) .  sail2_state_monad$bindS
+   (ELFromM32 mode  : ((bool #  2 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let valid_name = tup__0 in
+   let el = tup__1 in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS valid_name "valid")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_M := mode|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_EL := el|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_nRW := ((vec_of_bits [B1]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . 
+   sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__3 with<|
+       ProcState_SP :=
+         (if ((((((mode = M32_User))) \/ (((mode = M32_System)))))) then
+            (vec_of_bits [B0]  :  1 words$word)
+          else (vec_of_bits [B1]  :  1 words$word))|>))))))))))`;
+
+
+(*val AddrTop : mword ty64 -> bool -> mword ty2 -> M ii*)
+
+val _ = Define `
+ ((AddrTop:(64)words$word -> bool ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address IsInstr el=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((HaveEL el)) "HaveEL(el)")
+   (S1TranslationRegime__0 el  : ( 2 words$word) M)) (\ (regime : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (tbid : 1 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (tbi : 1 bits) .  sail2_state_monad$bindS
+   (ELUsingAArch32 regime) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$returnS (( 31 : int):ii)
+   else
+     let pat_0 = regime in sail2_state_monad$bindS
+     (if (((pat_0 = EL1))) then sail2_state_monad$bindS
+        (if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+           sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__1 (( 38 : int):ii)]  :  1 words$word))
+         else sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+           sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__2 (( 37 : int):ii)]  :  1 words$word))) (\ (w__3 :
+           1 words$word) . 
+        let tbi = w__3 in sail2_state_monad$bindS
+        (if ((HavePACExt () )) then
+           if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+             (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+             sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 52 : int):ii)]  :  1 words$word))
+           else sail2_state_monad$bindS
+             (sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+             sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__5 (( 51 : int):ii)]  :  1 words$word))
+         else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . 
+        sail2_state_monad$returnS (tbi, tbid)))
+      else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveVirtHostExt () ))) ((ELIsInHost el))) (\ (w__8 : bool) . 
+        if w__8 then sail2_state_monad$bindS
+          (if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+             (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+             sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__9 (( 38 : int):ii)]  :  1 words$word))
+           else sail2_state_monad$bindS
+             (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__10 : 64 bits) . 
+             sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__10 (( 37 : int):ii)]  :  1 words$word))) (\ (w__11 :
+             1 words$word) . 
+          let tbi = w__11 in sail2_state_monad$bindS
+          (if ((HavePACExt () )) then
+             if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+               (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+               sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__12 (( 52 : int):ii)]  :  1 words$word))
+             else sail2_state_monad$bindS
+               (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__13 : 64 bits) . 
+               sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__13 (( 51 : int):ii)]  :  1 words$word))
+           else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . 
+          sail2_state_monad$returnS (tbi, tbid)))
+        else sail2_state_monad$bindS
+          (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__15 : 64 bits) . 
+          let tbi = ((vec_of_bits [access_vec_dec w__15 (( 20 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+          (if ((HavePACExt () )) then sail2_state_monad$bindS
+             (sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__16 : 64 bits) . 
+             let (tbid : 1 bits) = ((vec_of_bits [access_vec_dec w__16 (( 29 : int):ii)]  :  1 words$word)) in
+             sail2_state_monad$returnS tbid)
+           else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . 
+          sail2_state_monad$returnS (tbi, tbid))))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__17 : 32 bits) . 
+        let tbi = ((vec_of_bits [access_vec_dec w__17 (( 20 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+        (if ((HavePACExt () )) then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M) (\ (w__18 : 32 bits) . 
+           let (tbid : 1 bits) = ((vec_of_bits [access_vec_dec w__18 (( 29 : int):ii)]  :  1 words$word)) in
+           sail2_state_monad$returnS tbid)
+         else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . 
+        sail2_state_monad$returnS (tbi, tbid)))) (\ varstup .  let ((tbi : 1 bits), (tbid : 1 bits)) = varstup in
+     sail2_state_monad$returnS (if ((((((tbi = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((~ ((HavePACExt () )))) \/ (((tbid = (vec_of_bits [B0]  :  1 words$word))))))) \/ ((~ IsInstr))))))))
+             then
+               (( 55 : int):ii)
+             else (( 63 : int):ii)))))))))`;
+
+
+(*val AddPAC : mword ty64 -> mword ty64 -> mword ty128 -> bool -> M (mword ty64)*)
+
+val _ = Define `
+ ((AddPAC:(64)words$word ->(64)words$word ->(128)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr modifier K1 data=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (PAC : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (ext_ptr : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (extfield : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (selbit : 1 bits) .  sail2_state_monad$bindS
+   (CalculateTBI ptr data) (\ (tbi : bool) . 
+   let (top_bit : int) = (if tbi then (( 55 : int):ii) else (( 63 : int):ii)) in sail2_state_monad$bindS
+   (PtrHasUpperAndLowerAddRanges () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (if w__0 then sail2_state_monad$bindS
+      (IsEL1TransRegimeRegs () ) (\ (w__1 : bool) . 
+      if w__1 then
+        if data then sail2_state_monad$bindS
+          (sail2_state$or_boolS
+            ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+             sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+            ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+             sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__4 : bool) . 
+          let (selbit : 1 bits) =
+            (if w__4 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word)
+            else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)]  :  1 words$word)) in
+          sail2_state_monad$returnS selbit)
+        else sail2_state_monad$bindS
+          (sail2_state$or_boolS
+            (sail2_state$and_boolS
+               ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+                sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+               ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+                sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 52 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+            (sail2_state$and_boolS
+               ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+                sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+               ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+                sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__11 : bool) . 
+          let (selbit : 1 bits) =
+            (if w__11 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word)
+            else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)]  :  1 words$word)) in
+          sail2_state_monad$returnS selbit)
+      else if data then sail2_state_monad$bindS
+        (sail2_state$or_boolS
+          (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+          (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__14 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (w__16 : bool) . 
+        let (selbit : 1 bits) =
+          (if w__16 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word)
+          else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)]  :  1 words$word)) in
+        sail2_state_monad$returnS selbit)
+      else sail2_state_monad$bindS
+        (sail2_state$or_boolS
+          (sail2_state$and_boolS
+             (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+                ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__17 : 64 bits) . 
+                 sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 38 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__19 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__19 (( 52 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+          (sail2_state$and_boolS
+             (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+                ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M) (\ (w__21 : 64 bits) . 
+                 sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__21 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M) (\ (w__23 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__25 : bool) . 
+        let (selbit : 1 bits) =
+          (if w__25 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word)
+          else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)]  :  1 words$word)) in
+        sail2_state_monad$returnS selbit))
+    else
+      let (selbit : 1 bits) =
+        (if tbi then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)]  :  1 words$word)
+        else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)]  :  1 words$word)) in
+      sail2_state_monad$returnS selbit) (\ (selbit : 1 bits) .  sail2_state_monad$bindS
+   (CalculateBottomPACBit ptr selbit) (\ (w__26 : ii) . 
+   let (bottom_PAC_bit : int) = (ex_int w__26) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (let extfield = ((replicate_bits selbit (( 64 : int):ii)  :  64 words$word)) in
+   let (ext_ptr : 64 bits) =
+     (if tbi then
+       (concat_vec ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word))
+          ((subrange_subrange_concat
+              ((((((((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) -
+                              (( 1 : int):ii)))
+                          - (((( 0 : int):ii) - (( 1 : int):ii)))))
+                      +
+                      ((bottom_PAC_bit - (( 1 : int):ii)))))
+                  - (((( 0 : int):ii) - (( 1 : int):ii)))))
+              extfield
+              ((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii)
+              ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii)
+             :  56 words$word))
+         :  64 words$word)
+     else
+       (subrange_subrange_concat ((int_of_num (words$word_len PAC))) extfield
+          ((((((~ bottom_PAC_bit)) + (( 64 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii) ptr
+          ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii)
+         :  64 words$word)) in sail2_state_monad$bindS
+   (ComputePAC ext_ptr modifier ((subrange_vec_dec K1 (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word))
+      ((subrange_vec_dec K1 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+     : ( 64 words$word) M) (\ (w__27 : 64 bits) . 
+   let (PAC : 64 bits) = w__27 in
+   let (PAC : 64 bits) =
+     (if (((((~ ((is_zero_subrange ptr
+                    ((((((((top_bit - bottom_PAC_bit)) + (( 1 : int):ii))) -
+                            (( 1 : int):ii)))
+                        + bottom_PAC_bit)) bottom_PAC_bit)))) /\ ((~ ((is_ones_subrange ptr
+                    ((((((((top_bit - bottom_PAC_bit)) + (( 1 : int):ii))) -
+                            (( 1 : int):ii)))
+                        + bottom_PAC_bit)) bottom_PAC_bit))))))) then
+       (update_subrange_vec_dec PAC ((top_bit - (( 1 : int):ii))) ((top_bit - (( 1 : int):ii)))
+          ((not_vec (vec_of_bits [access_vec_dec PAC ((top_bit - (( 1 : int):ii)))]  :  1 words$word)
+             :  1 words$word))
+         :  64 words$word)
+     else PAC) in
+   let (result : 64 bits) =
+     (if tbi then
+       (concat_vec
+          ((concat_vec ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word)) selbit  :  9 words$word))
+          ((subrange_subrange_concat
+              ((((((((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) -
+                                  (( 1 : int):ii)))
+                              + bottom_PAC_bit))
+                          - ((bottom_PAC_bit - (( 1 : int):ii)))))
+                      +
+                      ((bottom_PAC_bit - (( 1 : int):ii)))))
+                  - (((( 0 : int):ii) - (( 1 : int):ii))))) PAC
+              ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii)))
+                  +
+                  bottom_PAC_bit)) bottom_PAC_bit ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii)
+             :  55 words$word))
+         :  64 words$word)
+     else
+       (concat_vec
+          ((concat_vec ((subrange_vec_dec PAC (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word)) selbit  :  9 words$word))
+          ((subrange_subrange_concat
+              ((((((((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) -
+                                  (( 1 : int):ii)))
+                              + bottom_PAC_bit))
+                          - ((bottom_PAC_bit - (( 1 : int):ii)))))
+                      +
+                      ((bottom_PAC_bit - (( 1 : int):ii)))))
+                  - (((( 0 : int):ii) - (( 1 : int):ii))))) PAC
+              ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii)))
+                  +
+                  bottom_PAC_bit)) bottom_PAC_bit ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii)
+             :  55 words$word))
+         :  64 words$word)) in
+   sail2_state_monad$returnS result)))))))))))))`;
+
+
+(*val AArch64_vESBOperation : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_vESBOperation:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$returnS (((w__3.ProcState_EL = EL1))))))) (\ (w__5 :
+     bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__5 "((HaveEL(EL2) && !(IsSecure())) && (((PSTATE).EL == EL0) || ((PSTATE).EL == EL1)))")
+   (sail2_state$and_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (vSEI_enabled : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS vSEI_enabled)
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (vSEI_pending : bool) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS ((Halted () )) ((ExternalDebugInterruptsDisabled EL1))) (\ (vintdis : bool) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS (sail2_state_monad$returnS vintdis)
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+      sail2_state_monad$returnS (((w__11.ProcState_A = (vec_of_bits [B1]  :  1 words$word))))))) (\ (vmasked : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (VDISR_EL2 : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (VDISR : 32 bits) . 
+   if (((vSEI_pending /\ vmasked))) then sail2_state_monad$bindS
+     (ELUsingAArch32 EL1) (\ (w__12 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if w__12 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS VDFSR_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) .  sail2_state_monad$bindS
+        (sail2_state_monad$read_regS VDFSR_ref  : ( 32 words$word) M) (\ (w__14 : 32 bits) .  sail2_state_monad$bindS
+        (AArch32_ReportDeferredSError ((slice w__13 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word))
+           (vec_of_bits [access_vec_dec w__14 (( 12 : int):ii)]  :  1 words$word)
+          : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+        let (VDISR : 32 bits) = w__15 in
+        sail2_state_monad$returnS () )))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS VSESR_EL2_ref  : ( 32 words$word) M) (\ (w__16 : 32 bits) .  sail2_state_monad$bindS
+        (AArch64_ReportDeferredSError ((slice w__16 (( 0 : int):ii) (( 25 : int):ii)  :  25 words$word))  : ( 64 words$word) M) (\ (w__17 : 64
+          bits) . 
+        let (VDISR_EL2 : 64 bits) = w__17 in
+        sail2_state_monad$returnS () )))
+     (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M)) (\ (w__18 :  64 words$word) . 
+     sail2_state_monad$write_regS
+       HCR_EL2_ref
+       ((set_slice (( 64 : int):ii) (( 1 : int):ii) w__18 (( 8 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   else sail2_state_monad$returnS () )))))))))`;
+
+
+(*val AArch64_WatchpointByteMatch : ii -> mword ty64 -> M bool*)
+
+val _ = Define `
+ ((AArch64_WatchpointByteMatch:int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n vaddress=
+    (sail2_state_monad$catch_early_returnS
+     ( sail2_state_monad$bindS(sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (AddrTop vaddress F w__0.ProcState_EL)) (\ (top : int) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref)) (\ (w__1 : ( 64 bits) list) . 
+      let (bottom : ii) =
+        (if ((((vec_of_bits [access_vec_dec ((access_list_dec w__1 n  :  64 words$word)) (( 2 : int):ii)]
+                 :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+          (( 2 : int):ii)
+        else (( 3 : int):ii)) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__2 : ( 32 bits) list) . 
+      let (byte_select_match : bool) =
+        ((vec_of_bits [access_vec_dec
+                          ((subrange_vec_dec ((access_list_dec w__2 n  :  32 words$word)) (( 12 : int):ii) (( 5 : int):ii)
+                             :  8 words$word))
+                          ((unsigned_subrange vaddress ((((ex_int bottom)) - (( 1 : int):ii)))
+                              (( 0 : int):ii)))]
+            :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__3 : ( 32 bits) list) . 
+      let (mask : ii) =
+        (lem$w2ui ((subrange_vec_dec ((access_list_dec w__3 n  :  32 words$word)) (( 28 : int):ii) (( 24 : int):ii)  :  5 words$word))) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M))) (\ (MSB : 8 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M))) (\ (LSB1 : 8 bits) .  sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int mask)) > (( 0 : int):ii))))
+        ( sail2_state_monad$bindS(sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__4 : ( 32 bits) list) . 
+         sail2_state_monad$returnS ((~ ((IsOnes
+                        ((subrange_vec_dec ((access_list_dec w__4 n  :  32 words$word)) (( 12 : int):ii) (( 5 : int):ii)
+                           :  8 words$word))))))))) (\ (w__5 : bool) .  sail2_state_monad$bindS
+      (if w__5 then sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (ConstrainUnpredictableBool Unpredictable_WPMASKANDBAS)) (\ (w__6 : bool) . 
+         let (byte_select_match : bool) = w__6 in
+         sail2_state_monad$returnS (bottom, byte_select_match))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__7 : ( 32 bits) list) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__8 : ( 32 bits) list) . 
+         let LSB1 =
+           ((and_vec
+              ((subrange_vec_dec ((access_list_dec w__7 n  :  32 words$word)) (( 12 : int):ii) (( 5 : int):ii)
+                 :  8 words$word))
+              ((not_vec
+                  ((sub_vec_int
+                      ((subrange_vec_dec ((access_list_dec w__8 n  :  32 words$word)) (( 12 : int):ii) (( 5 : int):ii)
+                         :  8 words$word)) (( 1 : int):ii)
+                     :  8 words$word))
+                 :  8 words$word))
+             :  8 words$word)) in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__9 : ( 32 bits) list) . 
+         let MSB =
+           ((add_vec
+              ((subrange_vec_dec ((access_list_dec w__9 n  :  32 words$word)) (( 12 : int):ii) (( 5 : int):ii)
+                 :  8 words$word)) LSB1
+             :  8 words$word)) in
+         if ((~ ((IsZero ((and_vec MSB ((sub_vec_int MSB (( 1 : int):ii)  :  8 words$word))  :  8 words$word))))))
+         then sail2_state_monad$bindS
+           (sail2_state_monad$liftRS (ConstrainUnpredictableBool Unpredictable_WPBASCONTIGUOUS)) (\ (w__10 : bool) . 
+           let (byte_select_match : bool) = w__10 in
+           let (bottom : ii) = ((( 3 : int):ii)) in
+           sail2_state_monad$returnS (bottom, byte_select_match))
+         else sail2_state_monad$returnS (bottom, byte_select_match))))) (\ varstup .  let ((bottom : ii), (byte_select_match :
+        bool)) = varstup in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) .  sail2_state_monad$bindS
+      (if (((((((ex_int mask)) > (( 0 : int):ii))) /\ ((((ex_int mask)) <= (( 2 : int):ii)))))) then sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (ConstrainUnpredictableInteger (( 3 : int):ii) (( 31 : int):ii) Unpredictable_RESWPMASK)) (\ varstup .  let (tup__0, tup__1) = varstup in
+         let c = tup__0 in
+         let mask = tup__1 in sail2_state_monad$seqS
+         (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_DISABLED))) \/ ((((((c = Constraint_NONE))) \/ (((c = Constraint_UNKNOWN))))))))) "((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))"))
+         (case c of
+           Constraint_DISABLED => sail2_state_monad$seqS (sail2_state_monad$early_returnS F : (unit, bool) MR) (sail2_state_monad$returnS mask)
+         | Constraint_NONE => sail2_state_monad$returnS (( 0 : int):ii)
+         ))
+       else sail2_state_monad$returnS mask) (\ (mask : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (WVR_match : bool) . 
+      let (mask2 : int) = (ex_int mask) in
+      let (bottom2 : int) = (ex_int bottom) in sail2_state_monad$bindS
+      (if ((((ex_int mask)) > ((ex_int bottom)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+         (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref))) (\ (w__11 : ( 64 bits) list) . 
+         let WVR_match =
+           (subrange_subrange_eq vaddress
+             ((((((((top - mask2)) + (( 1 : int):ii))) - (( 1 : int):ii))) +
+                 mask2)) mask2 ((access_list_dec w__11 n  :  64 words$word))
+             ((((((((top - mask2)) + (( 1 : int):ii))) - (( 1 : int):ii))) +
+                 mask2)) mask2) in sail2_state_monad$bindS
+         (sail2_state$and_boolS (sail2_state_monad$returnS WVR_match)
+           ( sail2_state_monad$bindS(sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref)) (\ (w__12 : ( 64 bits) list) . 
+            sail2_state_monad$returnS ((~ ((is_zero_subrange ((access_list_dec w__12 n  :  64 words$word))
+                           ((((((mask2 - bottom2)) - (( 1 : int):ii))) +
+                               bottom2)) bottom2))))))) (\ (w__13 : bool) . 
+         if w__13 then sail2_state_monad$liftRS (ConstrainUnpredictableBool Unpredictable_WPMASKEDBITS)
+         else sail2_state_monad$returnS WVR_match))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref)) (\ (w__15 : ( 64 bits) list) . 
+         let (WVR_match : bool) =
+           (subrange_subrange_eq vaddress
+             ((((((((top - bottom2)) + (( 1 : int):ii))) - (( 1 : int):ii))) +
+                 bottom2)) bottom2 ((access_list_dec w__15 n  :  64 words$word))
+             ((((((((top - bottom2)) + (( 1 : int):ii))) - (( 1 : int):ii))) +
+                 bottom2)) bottom2) in
+         sail2_state_monad$returnS WVR_match)) (\ (WVR_match : bool) . 
+      sail2_state_monad$returnS (((WVR_match /\ byte_select_match)))))))))))))))))))`;
+
+
+(*val IsOnes_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*)
+
+val _ = Define `
+ ((IsOnes_slice:'n words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) xs i l=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word)) in
+   sail2_state_monad$returnS (((((and_vec xs m  :  'n words$word)) = m))))))`;
+
+
+(*val AArch64_TranslationTableWalk : mword ty52 -> mword ty64 -> AccType -> bool -> bool -> bool -> ii -> M TLBRecord*)
+
+val _ = Define `
+ ((AArch64_TranslationTableWalk:(52)words$word ->(64)words$word -> AccType -> bool -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress vaddress acctype iswrite secondstage s2fs1walk size1=
+    (sail2_state_monad$catch_early_returnS
+     ( sail2_state_monad$bindS (sail2_state_monad$seqS(if ((~ secondstage)) then sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((S1TranslationRegime__1 ()   : ( 2 words$word) M))) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (ELUsingAArch32 w__0)) (\ (w__1 : bool) .  sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((~ w__1)) "")))
+       else sail2_state_monad$bindS
+         (sail2_state$and_boolS
+           (sail2_state$and_boolS
+              (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+                 ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsSecure () )) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+              ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL2)) (\ (w__4 : bool) .  sail2_state_monad$returnS ((~ w__4)))))
+           (sail2_state_monad$liftRS ((HasS2Translation () )))) (\ (w__7 : bool) . 
+         sail2_state_monad$liftRS (sail2_state_monad$assert_expS w__7 "")))
+      (sail2_state_monad$liftRS (undefined_TLBRecord () ))) (\ (result : TLBRecord) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr : AddressDescriptor) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (baseregister : 64 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (inputaddr : 64 bits) . 
+      let (tmp_170 : FaultRecord) = (descaddr.AddressDescriptor_fault) in
+      let tmp_170 = ((tmp_170 with<| FaultRecord_typ := Fault_None|>)) in
+      let descaddr = ((descaddr with<| AddressDescriptor_fault := tmp_170|>)) in
+      let (tmp_180 : MemoryAttributes) = (descaddr.AddressDescriptor_memattrs) in
+      let tmp_180 = ((tmp_180 with<| MemoryAttributes_typ := MemType_Normal|>)) in
+      let descaddr = ((descaddr with<| AddressDescriptor_memattrs := tmp_180|>)) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (startsizecheck : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsizecheck : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (startlevel : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (level : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (stride : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (firstblocklevel : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (grainsize : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hierattrsdisabled : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AP : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AF : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (singlepriv : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (lookupsecure : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (reversedescriptors : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (disabled : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (basefound : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M))) (\ (ps : 3 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_min : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_max : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize : ii) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (midgrain : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (largegrain : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_int () )) (\ (top : ii) .  sail2_state_monad$bindS
+      (if ((~ secondstage)) then sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) vaddress  : ( 64 words$word) M))) (\ (w__8 : 64 bits) . 
+         let inputaddr = w__8 in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (AddrTop inputaddr (((acctype = AccType_IFETCH))) w__9.ProcState_EL)) (\ (w__10 :
+           ii) . 
+         let top = w__10 in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) .  sail2_state_monad$bindS
+         (if (((w__11.ProcState_EL = EL3))) then sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__12 : 32 bits) . 
+            let largegrain =
+              (((slice w__12 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__13 : 32 bits) . 
+            let midgrain =
+              (((slice w__13 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)) in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__14 : 32 bits) . 
+            let inputsize = ((( 64 : int):ii) - ((lem$w2ui ((slice w__14 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in
+            let inputsize_max =
+              (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+              else (( 48 : int):ii)) in sail2_state_monad$bindS
+            (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+               let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+               (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+               (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in
+               sail2_state_monad$returnS (c, inputsize))
+             else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize : ii)) = varstup in
+            let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+            (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+               let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+               (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+               (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in
+               sail2_state_monad$returnS inputsize)
+             else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__15 : 32 bits) . 
+            let ps = ((slice w__15 (( 16 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+            (sail2_state$and_boolS
+              (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+              (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize
+                         ((((((ex_int top)) - ((ex_int inputsize)))) + (( 1 : int):ii))))))) (\ (w__17 :
+              bool) . 
+            let basefound = w__17 in
+            let disabled = F in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL3_ref  : ( 64 words$word) M))) (\ (w__18 : 64 bits) . 
+            let baseregister = w__18 in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__19 : 32 bits) .  sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__20 : 32 bits) .  sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__21 : 32 bits) .  sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__19 (( 12 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                     ((slice w__20 (( 10 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                     ((slice w__21 (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__22 :
+              MemoryAttributes) . 
+            let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__22|>)) in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M))) (\ (w__23 : 32 bits) . 
+            let reversedescriptors =
+              ((vec_of_bits [access_vec_dec w__23 (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+            let lookupsecure = T in
+            let singlepriv = T in sail2_state_monad$bindS
+            (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () )))
+              ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__24 : 32 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__24 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__25 : bool) . 
+            let update_AF = w__25 in sail2_state_monad$bindS
+            (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF))))
+              ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__26 : 32 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__26 (( 22 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__27 : bool) . 
+            let update_AP = w__27 in sail2_state_monad$bindS
+            (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () )))
+              ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref  : ( 32 words$word) M))) (\ (w__28 : 32 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__28 (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__29 : bool) . 
+            let (hierattrsdisabled : bool) = w__29 in
+            sail2_state_monad$returnS (basefound,
+                    baseregister,
+                    descaddr,
+                    disabled,
+                    hierattrsdisabled,
+                    inputsize,
+                    largegrain,
+                    lookupsecure,
+                    midgrain,
+                    ps,
+                    reversedescriptors,
+                    singlepriv,
+                    update_AF,
+                    update_AP)))))))))))))))))
+          else sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (IsInHost () )) (\ (w__30 : bool) . 
+            if w__30 then sail2_state_monad$bindS
+              (if ((((vec_of_bits [access_vec_dec inputaddr top]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__31 : 64 bits) . 
+                 let largegrain =
+                   (((slice w__31 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__32 : 64 bits) . 
+                 let midgrain =
+                   (((slice w__32 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__33 : 64 bits) . 
+                 let inputsize =
+                   ((( 64 : int):ii) - ((lem$w2ui ((slice w__33 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in
+                 let inputsize_max =
+                   (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+                   else (( 48 : int):ii)) in sail2_state_monad$bindS
+                 (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+                    let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                    (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                    (let (inputsize : ii) =
+                      (if (((c = Constraint_FORCE))) then inputsize_max
+                      else inputsize) in
+                    sail2_state_monad$returnS (c, inputsize))
+                  else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize :
+                   ii)) = varstup in
+                 let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+                 (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+                    let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                    (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                    (let (inputsize : ii) =
+                      (if (((c = Constraint_FORCE))) then inputsize_min
+                      else inputsize) in
+                    sail2_state_monad$returnS inputsize)
+                  else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+                 (sail2_state$and_boolS
+                   (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+                   (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize
+                              ((((((ex_int top)) - ((ex_int inputsize)))) +
+                                  (( 1 : int):ii))))))) (\ (w__35 : bool) . 
+                 let basefound = w__35 in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__36 : 64 bits) . 
+                 let disabled =
+                   ((vec_of_bits [access_vec_dec w__36 (( 7 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL2_ref  : ( 64 words$word) M))) (\ (w__37 : 64 bits) . 
+                 let baseregister = w__37 in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__38 : 64 bits) .  sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__39 : 64 bits) .  sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__40 : 64 bits) .  sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__38 (( 12 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                          ((slice w__39 (( 10 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                          ((slice w__40 (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__41 :
+                   MemoryAttributes) . 
+                 let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__41|>)) in sail2_state_monad$bindS
+                 (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () )))
+                   ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__42 : 64 bits) . 
+                    sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__42 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__43 : bool) . 
+                 let (hierattrsdisabled : bool) = w__43 in
+                 sail2_state_monad$returnS (basefound,
+                         baseregister,
+                         descaddr,
+                         disabled,
+                         hierattrsdisabled,
+                         inputsize,
+                         largegrain,
+                         midgrain))))))))))))))
+               else sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__44 : 64 bits) . 
+                 let inputsize =
+                   ((( 64 : int):ii) - ((lem$w2ui ((slice w__44 (( 16 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__45 : 64 bits) . 
+                 let largegrain =
+                   (((slice w__45 (( 30 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__46 : 64 bits) . 
+                 let midgrain =
+                   (((slice w__46 (( 30 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in
+                 let inputsize_max =
+                   (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+                   else (( 48 : int):ii)) in sail2_state_monad$bindS
+                 (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+                    let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                    (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                    (let (inputsize : ii) =
+                      (if (((c = Constraint_FORCE))) then inputsize_max
+                      else inputsize) in
+                    sail2_state_monad$returnS (c, inputsize))
+                  else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize :
+                   ii)) = varstup in
+                 let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+                 (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+                    let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                    (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                    (let (inputsize : ii) =
+                      (if (((c = Constraint_FORCE))) then inputsize_min
+                      else inputsize) in
+                    sail2_state_monad$returnS inputsize)
+                  else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+                 (sail2_state$and_boolS
+                   (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+                   (sail2_state_monad$liftRS ((IsOnes_slice inputaddr inputsize
+                              ((((((ex_int top)) - ((ex_int inputsize)))) +
+                                  (( 1 : int):ii))))))) (\ (w__48 : bool) . 
+                 let basefound = w__48 in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__49 : 64 bits) . 
+                 let disabled =
+                   ((vec_of_bits [access_vec_dec w__49 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR1_EL2_ref  : ( 64 words$word) M))) (\ (w__50 : 64 bits) . 
+                 let baseregister = w__50 in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__51 : 64 bits) .  sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__52 : 64 bits) .  sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__53 : 64 bits) .  sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__51 (( 28 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                          ((slice w__52 (( 26 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                          ((slice w__53 (( 24 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__54 :
+                   MemoryAttributes) . 
+                 let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__54|>)) in sail2_state_monad$bindS
+                 (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () )))
+                   ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__55 : 64 bits) . 
+                    sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__55 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__56 : bool) . 
+                 let (hierattrsdisabled : bool) = w__56 in
+                 sail2_state_monad$returnS (basefound,
+                         baseregister,
+                         descaddr,
+                         disabled,
+                         hierattrsdisabled,
+                         inputsize,
+                         largegrain,
+                         midgrain))))))))))))))) (\ varstup .  let ((basefound : bool), (baseregister : 64
+                bits), (descaddr : AddressDescriptor), (disabled : bool), (hierattrsdisabled :
+                bool), (inputsize : ii), (largegrain : bool), (midgrain : bool)) = varstup in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__57 : 64 bits) . 
+              let ps = ((slice w__57 (( 32 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M))) (\ (w__58 : 32 bits) . 
+              let reversedescriptors =
+                ((vec_of_bits [access_vec_dec w__58 (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+              let lookupsecure = F in
+              let singlepriv = F in sail2_state_monad$bindS
+              (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () )))
+                ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__59 : 64 bits) . 
+                 sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__59 (( 39 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__60 : bool) . 
+              let update_AF = w__60 in sail2_state_monad$bindS
+              (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF))))
+                ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__61 : 64 bits) . 
+                 sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__61 (( 40 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__62 : bool) . 
+              let (update_AP : bool) = w__62 in
+              sail2_state_monad$returnS (basefound,
+                      baseregister,
+                      descaddr,
+                      disabled,
+                      hierattrsdisabled,
+                      inputsize,
+                      largegrain,
+                      lookupsecure,
+                      midgrain,
+                      ps,
+                      reversedescriptors,
+                      singlepriv,
+                      update_AF,
+                      update_AP))))))
+            else sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__63 : ProcState) . 
+              if (((w__63.ProcState_EL = EL2))) then sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__64 : 64 bits) . 
+                let inputsize =
+                  ((( 64 : int):ii) - ((lem$w2ui ((slice w__64 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__65 : 64 bits) . 
+                let largegrain =
+                  (((slice w__65 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__66 : 64 bits) . 
+                let midgrain =
+                  (((slice w__66 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)) in
+                let inputsize_max =
+                  (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+                  else (( 48 : int):ii)) in sail2_state_monad$bindS
+                (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+                   let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                   (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                   (let (inputsize : ii) =
+                     (if (((c = Constraint_FORCE))) then inputsize_max
+                     else inputsize) in
+                   sail2_state_monad$returnS (c, inputsize))
+                 else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize :
+                  ii)) = varstup in
+                let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+                (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+                   let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                   (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                   (let (inputsize : ii) =
+                     (if (((c = Constraint_FORCE))) then inputsize_min
+                     else inputsize) in
+                   sail2_state_monad$returnS inputsize)
+                 else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__67 : 64 bits) . 
+                let ps = ((slice w__67 (( 16 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+                (sail2_state$and_boolS
+                  (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+                  (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize
+                             ((((((ex_int top)) - ((ex_int inputsize)))) +
+                                 (( 1 : int):ii))))))) (\ (w__69 : bool) . 
+                let basefound = w__69 in
+                let disabled = F in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL2_ref  : ( 64 words$word) M))) (\ (w__70 : 64 bits) . 
+                let baseregister = w__70 in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__71 : 64 bits) .  sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__72 : 64 bits) .  sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__73 : 64 bits) .  sail2_state_monad$bindS
+                (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__71 (( 12 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                         ((slice w__72 (( 10 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                         ((slice w__73 (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__74 :
+                  MemoryAttributes) . 
+                let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__74|>)) in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M))) (\ (w__75 : 32 bits) . 
+                let reversedescriptors =
+                  ((vec_of_bits [access_vec_dec w__75 (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+                let lookupsecure = F in
+                let singlepriv = T in sail2_state_monad$bindS
+                (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () )))
+                  ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__76 : 64 bits) . 
+                   sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__76 (( 39 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__77 : bool) . 
+                let update_AF = w__77 in sail2_state_monad$bindS
+                (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF))))
+                  ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__78 : 64 bits) . 
+                   sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__78 (( 40 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__79 : bool) . 
+                let update_AP = w__79 in sail2_state_monad$bindS
+                (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () )))
+                  ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref  : ( 64 words$word) M))) (\ (w__80 : 64 bits) . 
+                   sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__80 (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__81 : bool) . 
+                let (hierattrsdisabled : bool) = w__81 in
+                sail2_state_monad$returnS (basefound,
+                        baseregister,
+                        descaddr,
+                        disabled,
+                        hierattrsdisabled,
+                        inputsize,
+                        largegrain,
+                        lookupsecure,
+                        midgrain,
+                        ps,
+                        reversedescriptors,
+                        singlepriv,
+                        update_AF,
+                        update_AP)))))))))))))))))
+              else sail2_state_monad$bindS
+                (if ((((vec_of_bits [access_vec_dec inputaddr top]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__82 : 64 bits) . 
+                   let inputsize =
+                     ((( 64 : int):ii) - ((lem$w2ui ((slice w__82 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__83 : 64 bits) . 
+                   let largegrain =
+                     (((slice w__83 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__84 : 64 bits) . 
+                   let midgrain =
+                     (((slice w__84 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)) in
+                   let inputsize_max =
+                     (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+                     else (( 48 : int):ii)) in sail2_state_monad$bindS
+                   (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+                      let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                      (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                      (let (inputsize : ii) =
+                        (if (((c = Constraint_FORCE))) then inputsize_max
+                        else inputsize) in
+                      sail2_state_monad$returnS (c, inputsize))
+                    else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize :
+                     ii)) = varstup in
+                   let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+                   (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+                      let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                      (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                      (let (inputsize : ii) =
+                        (if (((c = Constraint_FORCE))) then inputsize_min
+                        else inputsize) in
+                      sail2_state_monad$returnS inputsize)
+                    else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+                   (sail2_state$and_boolS
+                     (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+                     (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize
+                                ((((((ex_int top)) - ((ex_int inputsize)))) +
+                                    (( 1 : int):ii))))))) (\ (w__86 : bool) . 
+                   let basefound = w__86 in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__87 : 64 bits) . 
+                   let disabled =
+                     ((vec_of_bits [access_vec_dec w__87 (( 7 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL1_ref  : ( 64 words$word) M))) (\ (w__88 : 64 bits) . 
+                   let baseregister = w__88 in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__89 : 64 bits) .  sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__90 : 64 bits) .  sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__91 : 64 bits) .  sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__89 (( 12 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                            ((slice w__90 (( 10 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                            ((slice w__91 (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__92 :
+                     MemoryAttributes) . 
+                   let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__92|>)) in sail2_state_monad$bindS
+                   (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () )))
+                     ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__93 : 64 bits) . 
+                      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__93 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__94 : bool) . 
+                   let (hierattrsdisabled : bool) = w__94 in
+                   sail2_state_monad$returnS (basefound,
+                           baseregister,
+                           descaddr,
+                           disabled,
+                           hierattrsdisabled,
+                           inputsize,
+                           largegrain,
+                           midgrain))))))))))))))
+                 else sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__95 : 64 bits) . 
+                   let inputsize =
+                     ((( 64 : int):ii) - ((lem$w2ui ((slice w__95 (( 16 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__96 : 64 bits) . 
+                   let largegrain =
+                     (((slice w__96 (( 30 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__97 : 64 bits) . 
+                   let midgrain =
+                     (((slice w__97 (( 30 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in
+                   let inputsize_max =
+                     (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+                     else (( 48 : int):ii)) in sail2_state_monad$bindS
+                   (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+                      let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                      (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                      (let (inputsize : ii) =
+                        (if (((c = Constraint_FORCE))) then inputsize_max
+                        else inputsize) in
+                      sail2_state_monad$returnS (c, inputsize))
+                    else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize :
+                     ii)) = varstup in
+                   let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+                   (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+                      let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+                      (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+                      (let (inputsize : ii) =
+                        (if (((c = Constraint_FORCE))) then inputsize_min
+                        else inputsize) in
+                      sail2_state_monad$returnS inputsize)
+                    else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+                   (sail2_state$and_boolS
+                     (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+                     (sail2_state_monad$liftRS ((IsOnes_slice inputaddr inputsize
+                                ((((((ex_int top)) - ((ex_int inputsize)))) +
+                                    (( 1 : int):ii))))))) (\ (w__99 : bool) . 
+                   let basefound = w__99 in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__100 : 64 bits) . 
+                   let disabled =
+                     ((vec_of_bits [access_vec_dec w__100 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR1_EL1_ref  : ( 64 words$word) M))) (\ (w__101 : 64 bits) . 
+                   let baseregister = w__101 in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__102 : 64 bits) .  sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__103 : 64 bits) .  sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__104 : 64 bits) .  sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__102 (( 28 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                            ((slice w__103 (( 26 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                            ((slice w__104 (( 24 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__105 :
+                     MemoryAttributes) . 
+                   let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__105|>)) in sail2_state_monad$bindS
+                   (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () )))
+                     ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__106 : 64 bits) . 
+                      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__106 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__107 : bool) . 
+                   let (hierattrsdisabled : bool) = w__107 in
+                   sail2_state_monad$returnS (basefound,
+                           baseregister,
+                           descaddr,
+                           disabled,
+                           hierattrsdisabled,
+                           inputsize,
+                           largegrain,
+                           midgrain))))))))))))))) (\ varstup .  let ((basefound : bool), (baseregister : 64
+                  bits), (descaddr : AddressDescriptor), (disabled : bool), (hierattrsdisabled :
+                  bool), (inputsize : ii), (largegrain : bool), (midgrain : bool)) = varstup in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__108 : 64 bits) . 
+                let ps = ((slice w__108 (( 32 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M))) (\ (w__109 : 32 bits) . 
+                let reversedescriptors =
+                  ((vec_of_bits [access_vec_dec w__109 (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+                (sail2_state_monad$liftRS (IsSecure () )) (\ (w__110 : bool) . 
+                let lookupsecure = w__110 in
+                let singlepriv = F in sail2_state_monad$bindS
+                (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () )))
+                  ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__111 : 64 bits) . 
+                   sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__111 (( 39 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__112 : bool) . 
+                let update_AF = w__112 in sail2_state_monad$bindS
+                (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF))))
+                  ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref  : ( 64 words$word) M))) (\ (w__113 : 64 bits) . 
+                   sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__113 (( 40 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__114 : bool) . 
+                let (update_AP : bool) = w__114 in
+                sail2_state_monad$returnS (basefound,
+                        baseregister,
+                        descaddr,
+                        disabled,
+                        hierattrsdisabled,
+                        inputsize,
+                        largegrain,
+                        lookupsecure,
+                        midgrain,
+                        ps,
+                        reversedescriptors,
+                        singlepriv,
+                        update_AF,
+                        update_AP)))))))))) (\ varstup .  let ((basefound : bool), (baseregister : 64
+           bits), (descaddr : AddressDescriptor), (disabled : bool), (hierattrsdisabled : bool), (inputsize :
+           ii), (largegrain : bool), (lookupsecure : bool), (midgrain : bool), (ps : 3 bits), (reversedescriptors :
+           bool), (singlepriv : bool), (update_AF : bool), (update_AP : bool)) = varstup in
+         let ((firstblocklevel : ii), (grainsize : ii)) =
+           (if largegrain then
+             let (grainsize : ii) = ((( 16 : int):ii)) in
+             let (firstblocklevel : ii) = (if ((Have52BitPAExt () )) then (( 1 : int):ii) else (( 2 : int):ii)) in
+             (firstblocklevel, grainsize)
+           else
+             let ((firstblocklevel : ii), (grainsize : ii)) =
+               (if midgrain then
+                 let (grainsize : ii) = ((( 14 : int):ii)) in
+                 let (firstblocklevel : ii) = ((( 2 : int):ii)) in
+                 (firstblocklevel, grainsize)
+               else
+                 let (grainsize : ii) = ((( 12 : int):ii)) in
+                 let (firstblocklevel : ii) = ((( 1 : int):ii)) in
+                 (firstblocklevel, grainsize)) in
+             (firstblocklevel, grainsize)) in
+         let (stride : ii) = (((ex_int grainsize)) - (( 3 : int):ii)) in
+         let (level : ii) =
+           ((( 4 : int):ii) -
+             ((ex_int
+                 ((clg
+                     (((((real_of_int ((((ex_int inputsize)) - ((ex_int grainsize)))))))
+                         /
+                         (((real_of_int stride)))))))))) in
+         sail2_state_monad$returnS (basefound,
+                 baseregister,
+                 descaddr,
+                 disabled,
+                 firstblocklevel,
+                 grainsize,
+                 hierattrsdisabled,
+                 inputaddr,
+                 inputsize,
+                 largegrain,
+                 level,
+                 lookupsecure,
+                 midgrain,
+                 ps,
+                 reversedescriptors,
+                 singlepriv,
+                 stride,
+                 update_AF,
+                 update_AP))))))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) ipaddress  : ( 64 words$word) M))) (\ (w__115 : 64 bits) . 
+         let inputaddr = w__115 in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__116 : 32 bits) . 
+         let inputsize = ((( 64 : int):ii) - ((lem$w2ui ((slice w__116 (( 0 : int):ii) (( 6 : int):ii)  :  6 words$word))))) in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__117 : 32 bits) . 
+         let largegrain =
+           (((slice w__117 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__118 : 32 bits) . 
+         let midgrain =
+           (((slice w__118 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)) in
+         let inputsize_max =
+           (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii)
+           else (( 48 : int):ii)) in sail2_state_monad$bindS
+         (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
+            let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+            (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+            (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in
+            sail2_state_monad$returnS (c, inputsize))
+          else sail2_state_monad$returnS (c, inputsize)) (\ varstup .  let ((c : Constraint), (inputsize : ii)) = varstup in
+         let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS
+         (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then
+            let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS
+            (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) ""))
+            (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in
+            sail2_state_monad$returnS inputsize)
+          else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__119 : 32 bits) . 
+         let ps = ((slice w__119 (( 16 : int):ii) (( 3 : int):ii)  :  3 words$word)) in sail2_state_monad$bindS
+         (sail2_state$and_boolS
+           (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max))))))))
+           (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize
+                      ((((~ ((ex_int inputsize)))) + (( 64 : int):ii))))))) (\ (w__121 :
+           bool) . 
+         let basefound = w__121 in
+         let disabled = F in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTTBR_EL2_ref  : ( 64 words$word) M))) (\ (w__122 : 64 bits) . 
+         let baseregister = w__122 in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__123 : 32 bits) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__124 : 32 bits) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__125 : 32 bits) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__123 (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                  ((slice w__124 (( 10 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                  ((slice w__125 (( 12 : int):ii) (( 2 : int):ii)  :  2 words$word)) secondstage)) (\ (w__126 :
+           MemoryAttributes) . 
+         let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__126|>)) in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M))) (\ (w__127 : 32 bits) . 
+         let reversedescriptors =
+           ((vec_of_bits [access_vec_dec w__127 (( 25 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+         let lookupsecure = F in
+         let singlepriv = T in sail2_state_monad$bindS
+         (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () )))
+           ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__128 : 32 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__128 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__129 : bool) . 
+         let update_AF = w__129 in sail2_state_monad$bindS
+         (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF))))
+           ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__130 : 32 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__130 (( 22 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__131 : bool) . 
+         let update_AP = w__131 in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref  : ( 32 words$word) M))) (\ (w__132 : 32 bits) . 
+         let startlevel = (lem$w2ui ((slice w__132 (( 6 : int):ii) (( 2 : int):ii)  :  2 words$word))) in
+         let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) =
+           (if largegrain then
+             let (grainsize : ii) = ((( 16 : int):ii)) in
+             let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in
+             let (firstblocklevel : ii) = (if ((Have52BitPAExt () )) then (( 1 : int):ii) else (( 2 : int):ii)) in
+             (firstblocklevel, grainsize, level)
+           else
+             let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) =
+               (if midgrain then
+                 let (grainsize : ii) = ((( 14 : int):ii)) in
+                 let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in
+                 let (firstblocklevel : ii) = ((( 2 : int):ii)) in
+                 (firstblocklevel, grainsize, level)
+               else
+                 let (grainsize : ii) = ((( 12 : int):ii)) in
+                 let (level : ii) = ((( 2 : int):ii) - ((ex_int startlevel))) in
+                 let (firstblocklevel : ii) = ((( 1 : int):ii)) in
+                 (firstblocklevel, grainsize, level)) in
+             (firstblocklevel, grainsize, level)) in
+         let stride = (((ex_int grainsize)) - (( 3 : int):ii)) in
+         let (basefound : bool) =
+           (if largegrain then
+             if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) then
+               F
+             else basefound
+           else if midgrain then
+             if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 40 : int):ii))))))))) then
+               F
+             else basefound
+           else if (((((((ex_int level)) < (( 0 : int):ii))) \/ ((((((((ex_int level)) = (( 0 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) then
+             F
+           else basefound) in
+         let inputsizecheck = inputsize in sail2_state_monad$bindS
+         (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int inputsize)) > ((ex_int ((PAMax () )))))))
+           (sail2_state$or_boolS ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL1)) (\ (w__133 : bool) .  sail2_state_monad$returnS ((~ w__133))))
+              (sail2_state_monad$returnS ((((ex_int inputsize)) > (( 40 : int):ii)))))) (\ (w__135 : bool) .  sail2_state_monad$bindS
+         (if w__135 then
+            (case ((ConstrainUnpredictable Unpredictable_LARGEIPA)) of
+              Constraint_FORCE =>
+               let (inputsize : ii) = (PAMax () ) in
+               let (inputsizecheck : ii) = (PAMax () ) in
+               sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)
+            | Constraint_FORCENOSLCHECK =>
+               let (inputsize : ii) = (PAMax () ) in
+               sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)
+            | Constraint_FAULT =>
+               let (basefound : bool) = F in
+               sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)
+            | _ => sail2_state_monad$seqS (sail2_state_monad$liftRS (Unreachable () )) (sail2_state_monad$returnS (basefound, inputsize, inputsizecheck))
+            )
+          else sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)) (\ varstup .  let ((basefound :
+           bool), (inputsize : ii), (inputsizecheck : ii)) = varstup in
+         let (startsizecheck : ii) =
+           (((ex_int inputsizecheck)) -
+             (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) +
+                 ((ex_int grainsize))))) in
+         let (basefound : bool) =
+           (if (((((((ex_int startsizecheck)) < (( 1 : int):ii))) \/ ((((ex_int startsizecheck)) > ((((ex_int stride)) + (( 4 : int):ii)))))))) then
+             F
+           else basefound) in
+         sail2_state_monad$returnS (basefound,
+                 baseregister,
+                 descaddr,
+                 disabled,
+                 firstblocklevel,
+                 grainsize,
+                 hierattrsdisabled,
+                 inputaddr,
+                 inputsize,
+                 largegrain,
+                 level,
+                 lookupsecure,
+                 midgrain,
+                 ps,
+                 reversedescriptors,
+                 singlepriv,
+                 stride,
+                 update_AF,
+                 update_AP))))))))))))))))))))) (\ varstup .  let ((basefound : bool), (baseregister : 64 bits), (descaddr :
+        AddressDescriptor), (disabled : bool), (firstblocklevel : ii), (grainsize : ii), (hierattrsdisabled :
+        bool), (inputaddr : 64 bits), (inputsize : ii), (largegrain : bool), (level : ii), (lookupsecure :
+        bool), (midgrain : bool), (ps : 3 bits), (reversedescriptors : bool), (singlepriv : bool), (stride :
+        ii), (update_AF : bool), (update_AP : bool)) = varstup in
+      if (((((~ basefound)) \/ disabled))) then
+        let level = ((( 0 : int):ii)) in
+        let (tmp_190 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+        (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__136 :
+          FaultRecord) . 
+        let (tmp_190 : AddressDescriptor) = ((tmp_190 with<| AddressDescriptor_fault := w__136|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_190|>)) in
+        sail2_state_monad$returnS result)
+      else sail2_state_monad$bindS
+        (sail2_state_monad$liftRS (undefined_int () )) (\ (outputsize : ii) . 
+        let b__0 = ps in
+        let (outputsize : ii) =
+          (if (((b__0 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then (( 32 : int):ii)
+          else if (((b__0 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then (( 36 : int):ii)
+          else if (((b__0 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then (( 40 : int):ii)
+          else if (((b__0 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then (( 42 : int):ii)
+          else if (((b__0 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then (( 44 : int):ii)
+          else if (((b__0 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then (( 48 : int):ii)
+          else if (((b__0 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+            if (((((Have52BitPAExt () )) /\ largegrain))) then (( 52 : int):ii)
+            else (( 48 : int):ii)
+          else (( 48 : int):ii)) in
+        let (outputsize : ii) =
+          (if ((((ex_int outputsize)) > ((ex_int ((PAMax () )))))) then PAMax () 
+          else outputsize) in sail2_state_monad$bindS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii))))
+          ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice baseregister outputsize
+                    ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__137 :
+             bool) . 
+           sail2_state_monad$returnS ((~ w__137))))) (\ (w__138 : bool) . 
+        if w__138 then
+          let level = ((( 0 : int):ii)) in
+          let (tmp_200 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__139 :
+            FaultRecord) . 
+          let (tmp_200 : AddressDescriptor) = ((tmp_200 with<| AddressDescriptor_fault := w__139|>)) in
+          let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_200|>)) in
+          sail2_state_monad$returnS result)
+        else
+          let baselowerbound =
+            ((((( 3 : int):ii) + ((ex_int inputsize)))) -
+              (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride))))
+                  +
+                  ((ex_int grainsize))))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+          (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+          (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M)))) (\ (baseaddress : 52 bits) .  sail2_state_monad$bindS
+          (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then
+             let z = (if ((baselowerbound < (( 6 : int):ii))) then (( 6 : int):ii) else baselowerbound) in sail2_state_monad$seqS
+             (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+             (let (baseaddress : 52 bits) =
+               ((concat_vec ((slice baseregister (( 2 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                  ((slice_zeros_concat ((((((~ z)) + (( 48 : int):ii))) + z))
+                      baseregister z ((((~ z)) + (( 48 : int):ii))) z
+                     :  48 words$word))
+                 :  52 words$word)) in
+             sail2_state_monad$returnS baseaddress)
+           else
+             let (baseaddress : 52 bits) =
+               ((place_slice (( 52 : int):ii) baseregister baselowerbound
+                  ((((~ baselowerbound)) + (( 48 : int):ii))) baselowerbound
+                 :  52 words$word)) in
+             sail2_state_monad$returnS baseaddress) (\ (baseaddress : 52 bits) . 
+          let (ns_table : 1 bits) =
+            (if lookupsecure then (vec_of_bits [B0]  :  1 words$word)
+            else (vec_of_bits [B1]  :  1 words$word)) in
+          let (ap_table : 2 bits) = ((vec_of_bits [B0;B0]  :  2 words$word)) in
+          let (xn_table : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+          let (pxn_table : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+          let (addrselecttop : ii) = (((ex_int inputsize)) - (( 1 : int):ii)) in sail2_state_monad$bindS
+          (sail2_state$and_boolS
+            (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+               ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M))) (\ (w__140 : 64 bits) . 
+                sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__140 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+            ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M))) (\ (w__142 : 64 bits) . 
+             sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__142 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (apply_nvnv1_effect : bool) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (blocktranslate : bool) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (desc : 64 bits) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (undefined_AccessDescriptor () )) (\ (accdesc : AccessDescriptor) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hwupdatewalk : bool) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr2 : AddressDescriptor) .  sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (undefined_int () )) (\ (addrselectbottom : ii) .  sail2_state_monad$bindS
+          (sail2_state$untilS (accdesc,
+                   addrselectbottom,
+                   addrselecttop,
+                   ap_table,
+                   baseaddress,
+                   blocktranslate,
+                   desc,
+                   descaddr,
+                   descaddr2,
+                   hwupdatewalk,
+                   level,
+                   ns_table,
+                   pxn_table,
+                   result,
+                   xn_table)
+            (\ varstup . 
+            let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
+                 ap_table,
+                 baseaddress,
+                 blocktranslate,
+                 desc,
+                 descaddr,
+                 descaddr2,
+                 hwupdatewalk,
+                 level,
+                 ns_table,
+                 pxn_table,
+                 result,
+                 xn_table) = varstup in
+              sail2_state_monad$returnS blocktranslate)
+            (\ varstup . 
+            let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
+                 ap_table,
+                 baseaddress,
+                 blocktranslate,
+                 desc,
+                 descaddr,
+                 descaddr2,
+                 hwupdatewalk,
+                 level,
+                 ns_table,
+                 pxn_table,
+                 result,
+                 xn_table) = varstup in
+              let addrselectbottom =
+                ((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride))))
+                  +
+                  ((ex_int grainsize))) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((ZeroExtend_slice_append (( 52 : int):ii) inputaddr addrselectbottom
+                        ((((((ex_int addrselecttop)) - ((ex_int addrselectbottom))))
+                            +
+                            (( 1 : int):ii))) (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                       : ( 52 words$word) M))) (\ (index : 52 bits) . 
+              let (tmp_210 : FullAddress) = (descaddr.AddressDescriptor_paddress) in
+              let tmp_210 =
+                ((tmp_210 with<|
+                  FullAddress_physicaladdress := ((or_vec baseaddress index  :  52 words$word))|>)) in
+              let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_210|>)) in
+              let (tmp_220 : FullAddress) = (descaddr.AddressDescriptor_paddress) in
+              let tmp_220 = ((tmp_220 with<| FullAddress_NS := ns_table|>)) in
+              let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_220|>)) in sail2_state_monad$bindS
+              (sail2_state$or_boolS (sail2_state_monad$returnS secondstage)
+                ( sail2_state_monad$bindS(sail2_state_monad$liftRS (HasS2Translation () )) (\ (w__143 : bool) .  sail2_state_monad$returnS ((~ w__143))))) (\ (w__144 :
+                bool) .  sail2_state_monad$bindS
+              (if w__144 then
+                 let (descaddr2 : AddressDescriptor) = descaddr in
+                 sail2_state_monad$returnS (descaddr2, hwupdatewalk, result)
+               else
+                 let hwupdatewalk = F in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (AArch64_SecondStageWalk descaddr vaddress acctype iswrite (( 8 : int):ii)
+                          hwupdatewalk)) (\ (w__145 : AddressDescriptor) . 
+                 let descaddr2 = w__145 in sail2_state_monad$bindS
+                 (if ((IsFault descaddr2)) then
+                    let (tmp_230 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+                    let tmp_230 =
+                      ((tmp_230 with<| AddressDescriptor_fault := (descaddr2.AddressDescriptor_fault)|>)) in
+                    let result = ((result with<| TLBRecord_addrdesc := tmp_230|>)) in sail2_state_monad$seqS
+                    (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result)
+                  else sail2_state_monad$returnS result) (\ (result : TLBRecord) . 
+                 sail2_state_monad$returnS (descaddr2, hwupdatewalk, result)))) (\ varstup .  let ((descaddr2 :
+                AddressDescriptor), (hwupdatewalk : bool), (result : TLBRecord)) = varstup in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) vaddress  : ( 64 words$word) M))) (\ (w__146 : 64 bits) . 
+              let descaddr2 = ((descaddr2 with<| AddressDescriptor_vaddress := w__146|>)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (CreateAccessDescriptorPTW acctype secondstage s2fs1walk level)) (\ (w__147 :
+                AccessDescriptor) . 
+              let accdesc = w__147 in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((aget__Mem descaddr2 (( 8 : int):ii) accdesc  : ( 64 words$word) M))) (\ (w__148 : 64
+                bits) . 
+              let desc = w__148 in sail2_state_monad$bindS
+              (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc  : ( 64 words$word) M))
+               else sail2_state_monad$returnS desc) (\ (desc : 64 bits) .  sail2_state_monad$bindS
+              (if (((((((vec_of_bits [access_vec_dec desc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) \/ ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((ex_int level)) = (( 3 : int):ii))))))))))
+               then
+                 let (tmp_240 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage
+                          s2fs1walk)) (\ (w__150 : FaultRecord) . 
+                 let tmp_240 = ((tmp_240 with<| AddressDescriptor_fault := w__150|>)) in
+                 let result = ((result with<| TLBRecord_addrdesc := tmp_240|>)) in sail2_state_monad$seqS
+                 (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR)
+                 (sail2_state_monad$returnS (addrselecttop,
+                         ap_table,
+                         baseaddress,
+                         blocktranslate,
+                         level,
+                         ns_table,
+                         pxn_table,
+                         result,
+                         xn_table)))
+               else if ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ (((((ex_int level)) = (( 3 : int):ii)))))))
+               then
+                 let (blocktranslate : bool) = T in
+                 sail2_state_monad$returnS (addrselecttop,
+                         ap_table,
+                         baseaddress,
+                         blocktranslate,
+                         level,
+                         ns_table,
+                         pxn_table,
+                         result,
+                         xn_table)
+               else sail2_state_monad$bindS
+                 (sail2_state$or_boolS
+                   (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))))))))))
+                   (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii))))
+                      ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize
+                                ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__151 :
+                         bool) . 
+                       sail2_state_monad$returnS ((~ w__151)))))) (\ (w__153 : bool) . 
+                 if w__153 then
+                   let (tmp_250 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage
+                            s2fs1walk)) (\ (w__154 : FaultRecord) . 
+                   let tmp_250 = ((tmp_250 with<| AddressDescriptor_fault := w__154|>)) in
+                   let result = ((result with<| TLBRecord_addrdesc := tmp_250|>)) in sail2_state_monad$seqS
+                   (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR)
+                   (sail2_state_monad$returnS (addrselecttop,
+                           ap_table,
+                           baseaddress,
+                           blocktranslate,
+                           level,
+                           ns_table,
+                           pxn_table,
+                           result,
+                           xn_table)))
+                 else
+                   let gsz = grainsize in sail2_state_monad$seqS
+                   (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+                   (let (baseaddress : 52 bits) =
+                     (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then
+                       (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                          ((slice_zeros_concat
+                              ((((((~ gsz)) + (( 48 : int):ii))) + gsz)) desc
+                              gsz ((((~ gsz)) + (( 48 : int):ii))) gsz
+                             :  48 words$word))
+                         :  52 words$word)
+                     else
+                       (place_slice (( 52 : int):ii) desc gsz ((((~ gsz)) + (( 48 : int):ii)))
+                          gsz
+                         :  52 words$word)) in
+                   let (ns_table : 1 bits) =
+                     (if ((~ secondstage)) then
+                       (or_vec ns_table (vec_of_bits [access_vec_dec desc (( 63 : int):ii)]  :  1 words$word)
+                         :  1 words$word)
+                     else ns_table) in
+                   let ((ap_table : 2 bits), (pxn_table : 1 bits), (xn_table : 1 bits)) =
+                     (if (((((~ secondstage)) /\ ((~ hierattrsdisabled))))) then
+                       let (ap_table : 2 bits) =
+                         ((set_slice (( 2 : int):ii) (( 1 : int):ii) ap_table (( 1 : int):ii)
+                            ((or_vec (vec_of_bits [access_vec_dec ap_table (( 1 : int):ii)]  :  1 words$word)
+                                (vec_of_bits [access_vec_dec desc (( 62 : int):ii)]  :  1 words$word)
+                               :  1 words$word))
+                           :  2 words$word)) in
+                       let ((pxn_table : 1 bits), (xn_table : 1 bits)) =
+                         (if apply_nvnv1_effect then
+                           let (pxn_table : 1 bits) =
+                             ((or_vec pxn_table
+                                (vec_of_bits [access_vec_dec desc (( 60 : int):ii)]  :  1 words$word)
+                               :  1 words$word)) in
+                           (pxn_table, xn_table)
+                         else
+                           let (xn_table : 1 bits) =
+                             ((or_vec xn_table
+                                (vec_of_bits [access_vec_dec desc (( 60 : int):ii)]  :  1 words$word)
+                               :  1 words$word)) in
+                           (pxn_table, xn_table)) in
+                       let ((ap_table : 2 bits), (pxn_table : 1 bits)) =
+                         (if ((~ singlepriv)) then
+                           let ((ap_table : 2 bits), (pxn_table : 1 bits)) =
+                             (if ((~ apply_nvnv1_effect)) then
+                               let (pxn_table : 1 bits) =
+                                 ((or_vec pxn_table
+                                    (vec_of_bits [access_vec_dec desc (( 59 : int):ii)]  :  1 words$word)
+                                   :  1 words$word)) in
+                               let (ap_table : 2 bits) =
+                                 ((set_slice (( 2 : int):ii) (( 1 : int):ii) ap_table (( 0 : int):ii)
+                                    ((or_vec
+                                        (vec_of_bits [access_vec_dec ap_table (( 0 : int):ii)]  :  1 words$word)
+                                        (vec_of_bits [access_vec_dec desc (( 61 : int):ii)]  :  1 words$word)
+                                       :  1 words$word))
+                                   :  2 words$word)) in
+                               (ap_table, pxn_table)
+                             else (ap_table, pxn_table)) in
+                           (ap_table, pxn_table)
+                         else (ap_table, pxn_table)) in
+                       (ap_table, pxn_table, xn_table)
+                     else (ap_table, pxn_table, xn_table)) in
+                   let (level : ii) = (((ex_int level)) + (( 1 : int):ii)) in
+                   let (addrselecttop : ii) = (((ex_int addrselectbottom)) - (( 1 : int):ii)) in
+                   let (blocktranslate : bool) = F in
+                   sail2_state_monad$returnS (addrselecttop,
+                           ap_table,
+                           baseaddress,
+                           blocktranslate,
+                           level,
+                           ns_table,
+                           pxn_table,
+                           result,
+                           xn_table)))) (\ varstup .  let ((addrselecttop : ii), (ap_table : 2
+                bits), (baseaddress : 52 bits), (blocktranslate : bool), (level : ii), (ns_table : 1
+                bits), (pxn_table : 1 bits), (result : TLBRecord), (xn_table : 1 bits)) = varstup in
+              sail2_state_monad$returnS (accdesc,
+                      addrselectbottom,
+                      addrselecttop,
+                      ap_table,
+                      baseaddress,
+                      blocktranslate,
+                      desc,
+                      descaddr,
+                      descaddr2,
+                      hwupdatewalk,
+                      level,
+                      ns_table,
+                      pxn_table,
+                      result,
+                      xn_table))))))))))) (\ varstup .  let ((accdesc : AccessDescriptor), (addrselectbottom :
+            ii), (addrselecttop : ii), (ap_table : 2 bits), (baseaddress : 52 bits), (blocktranslate :
+            bool), (desc : 64 bits), (descaddr : AddressDescriptor), (descaddr2 :
+            AddressDescriptor), (hwupdatewalk : bool), (level : ii), (ns_table : 1 bits), (pxn_table : 1
+            bits), (result : TLBRecord), (xn_table : 1 bits)) = varstup in
+          if ((((ex_int level)) < ((ex_int firstblocklevel)))) then
+            let (tmp_260 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__155 :
+              FaultRecord) . 
+            let (tmp_260 : AddressDescriptor) = ((tmp_260 with<| AddressDescriptor_fault := w__155|>)) in
+            let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_260|>)) in
+            sail2_state_monad$returnS result)
+          else sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (contiguousbitcheck : bool) . 
+            let (contiguousbitcheck : bool) =
+              (if largegrain then
+                ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii))))
+              else if midgrain then
+                ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 30 : int):ii))))
+              else ((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii))))) in sail2_state_monad$bindS
+            (if (((contiguousbitcheck /\ ((((vec_of_bits [access_vec_dec desc (( 52 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then sail2_state_monad$bindS
+               (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (w__156 : bool) . 
+               if w__156 then
+                 let (tmp_270 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage
+                          s2fs1walk)) (\ (w__157 : FaultRecord) . 
+                 let tmp_270 = ((tmp_270 with<| AddressDescriptor_fault := w__157|>)) in
+                 let result = ((result with<| TLBRecord_addrdesc := tmp_270|>)) in sail2_state_monad$seqS
+                 (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result))
+               else sail2_state_monad$returnS result)
+             else sail2_state_monad$returnS result) (\ (result : TLBRecord) .  sail2_state_monad$bindS
+            (sail2_state$or_boolS
+              (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))))))))))
+              (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii))))
+                 ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize
+                           ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__158 :
+                    bool) . 
+                  sail2_state_monad$returnS ((~ w__158)))))) (\ (w__160 : bool) . 
+            if w__160 then
+              let (tmp_280 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__161 :
+                FaultRecord) . 
+              let (tmp_280 : AddressDescriptor) =
+                ((tmp_280 with<| AddressDescriptor_fault := w__161|>)) in
+              let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_280|>)) in
+              sail2_state_monad$returnS result)
+            else sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M))) (\ (outputaddress : 52
+                bits) . 
+              let asb = addrselectbottom in sail2_state_monad$seqS
+              (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T ""))
+              (let (outputaddress : 52 bits) =
+                (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then
+                  (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))
+                     ((slice_slice_concat (( 48 : int):ii) desc asb
+                         ((((~ asb)) + (( 48 : int):ii))) inputaddr (( 0 : int):ii) asb
+                        :  48 words$word))
+                    :  52 words$word)
+                else
+                  (slice_slice_concat (( 52 : int):ii) desc asb ((((~ asb)) + (( 48 : int):ii)))
+                     inputaddr (( 0 : int):ii) asb
+                    :  52 words$word)) in
+              let (tmp_330 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+              let tmp_330 = ((tmp_330 with<| DescriptorUpdate_AF := F|>)) in
+              let tmp_330 = ((tmp_330 with<| DescriptorUpdate_AP := F|>)) in
+              let tmp_330 = ((tmp_330 with<| DescriptorUpdate_descaddr := descaddr|>)) in
+              let result = ((result with<| TLBRecord_descupdate := tmp_330|>)) in sail2_state_monad$bindS
+              (if ((((vec_of_bits [access_vec_dec desc (( 10 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+                 if ((~ update_AF)) then
+                   let (tmp_290 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                   (sail2_state_monad$liftRS (AArch64_AccessFlagFault ipaddress level acctype iswrite secondstage
+                            s2fs1walk)) (\ (w__162 : FaultRecord) . 
+                   let tmp_290 = ((tmp_290 with<| AddressDescriptor_fault := w__162|>)) in
+                   let result = ((result with<| TLBRecord_addrdesc := tmp_290|>)) in sail2_state_monad$seqS
+                   (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result))
+                 else
+                   let (tmp_300 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+                   let (tmp_300 : DescriptorUpdate) = ((tmp_300 with<| DescriptorUpdate_AF := T|>)) in
+                   let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_300|>)) in
+                   sail2_state_monad$returnS result
+               else sail2_state_monad$returnS result) (\ (result : TLBRecord) . 
+              let ((desc : 64 bits), (result : TLBRecord)) =
+                (if (((update_AP /\ ((((vec_of_bits [access_vec_dec desc (( 51 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+                  let ((desc : 64 bits), (result : TLBRecord)) =
+                    (if (((((~ secondstage)) /\ ((((vec_of_bits [access_vec_dec desc (( 7 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+                      let (desc : 64 bits) =
+                        ((set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B0]  :  1 words$word)
+                          :  64 words$word)) in
+                      let (tmp_310 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+                      let (tmp_310 : DescriptorUpdate) =
+                        ((tmp_310 with<| DescriptorUpdate_AP := T|>)) in
+                      let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_310|>)) in
+                      (desc, result)
+                    else
+                      let ((desc : 64 bits), (result : TLBRecord)) =
+                        (if (((secondstage /\ ((((vec_of_bits [access_vec_dec desc (( 7 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+                          let (desc : 64 bits) =
+                            ((set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+                              :  64 words$word)) in
+                          let (tmp_320 : DescriptorUpdate) = (result.TLBRecord_descupdate) in
+                          let (tmp_320 : DescriptorUpdate) =
+                            ((tmp_320 with<| DescriptorUpdate_AP := T|>)) in
+                          let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_320|>)) in
+                          (desc, result)
+                        else (desc, result)) in
+                      (desc, result)) in
+                  (desc, result)
+                else (desc, result)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M))) (\ (xn : 1 bits) .  sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M))) (\ (pxn : 1 bits) . 
+              let ((pxn : 1 bits), (xn : 1 bits)) =
+                (if apply_nvnv1_effect then
+                  let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)]  :  1 words$word)) in
+                  let (xn : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in
+                  (pxn, xn)
+                else
+                  let (xn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)]  :  1 words$word)) in
+                  let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)]  :  1 words$word)) in
+                  (pxn, xn)) in
+              let (contiguousbit : 1 bits) =
+                ((vec_of_bits [access_vec_dec desc (( 52 : int):ii)]  :  1 words$word)) in
+              let (nG : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 : int):ii)]  :  1 words$word)) in
+              let (sh : 2 bits) = ((slice desc (( 8 : int):ii) (( 2 : int):ii)  :  2 words$word)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M))) (\ (ap : 3 bits) . 
+              let (ap : 3 bits) =
+                (if apply_nvnv1_effect then
+                  (concat_vec (vec_of_bits [access_vec_dec desc (( 7 : int):ii)]  :  1 words$word)
+                     (vec_of_bits [B0;B1]  :  2 words$word)
+                    :  3 words$word)
+                else
+                  (concat_vec ((slice desc (( 6 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                     (vec_of_bits [B1]  :  1 words$word)
+                    :  3 words$word)) in
+              let (memattr : 4 bits) = ((slice desc (( 2 : int):ii) (( 4 : int):ii)  :  4 words$word)) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS ((undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M))) (\ (w__163 : 4 bits) . 
+              let result = ((result with<| TLBRecord_domain := w__163|>)) in
+              let result = ((result with<| TLBRecord_level := level|>)) in
+              let result =
+                ((result with<|
+                  TLBRecord_blocksize :=
+                    ((pow2
+                        (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride))))
+                            +
+                            ((ex_int grainsize))))))|>)) in sail2_state_monad$bindS
+              (if ((~ secondstage)) then
+                 let (tmp_340 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_340 =
+                   ((tmp_340 with<| Permissions_xn := ((or_vec xn xn_table  :  1 words$word))|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_340|>)) in
+                 let (tmp_350 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+                 let tmp_350 =
+                   ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_350 (( 2 : int):ii)
+                      ((or_vec (vec_of_bits [access_vec_dec ap (( 2 : int):ii)]  :  1 words$word)
+                          (vec_of_bits [access_vec_dec ap_table (( 1 : int):ii)]  :  1 words$word)
+                         :  1 words$word))
+                     :  3 words$word)) in
+                 let (tmp_360 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_360 = ((tmp_360 with<| Permissions_ap := tmp_350|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_360|>)) in sail2_state_monad$bindS
+                 (if ((~ singlepriv)) then
+                    let (tmp_370 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+                    let tmp_370 =
+                      ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_370 (( 1 : int):ii)
+                         ((and_vec (vec_of_bits [access_vec_dec ap (( 1 : int):ii)]  :  1 words$word)
+                             ((not_vec (vec_of_bits [access_vec_dec ap_table (( 0 : int):ii)]  :  1 words$word)
+                                :  1 words$word))
+                            :  1 words$word))
+                        :  3 words$word)) in
+                    let (tmp_380 : Permissions) = (result.TLBRecord_perms) in
+                    let tmp_380 = ((tmp_380 with<| Permissions_ap := tmp_370|>)) in
+                    let result = ((result with<| TLBRecord_perms := tmp_380|>)) in
+                    let (tmp_390 : Permissions) = (result.TLBRecord_perms) in
+                    let tmp_390 =
+                      ((tmp_390 with<| Permissions_pxn := ((or_vec pxn pxn_table  :  1 words$word))|>)) in
+                    let result = ((result with<| TLBRecord_perms := tmp_390|>)) in sail2_state_monad$bindS
+                    (sail2_state_monad$liftRS (IsSecure () )) (\ (w__164 : bool) . 
+                    let (result : TLBRecord) =
+                      (if w__164 then
+                        (result with<| TLBRecord_nG := ((or_vec nG ns_table  :  1 words$word))|>)
+                      else (result with<| TLBRecord_nG := nG|>)) in
+                    sail2_state_monad$returnS result)
+                  else
+                    let (tmp_400 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+                    let (tmp_400 : 3 bits) =
+                      ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_400 (( 1 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+                        :  3 words$word)) in
+                    let (tmp_410 : Permissions) = (result.TLBRecord_perms) in
+                    let (tmp_410 : Permissions) = ((tmp_410 with<| Permissions_ap := tmp_400|>)) in
+                    let (result : TLBRecord) = ((result with<| TLBRecord_perms := tmp_410|>)) in
+                    let (tmp_420 : Permissions) = (result.TLBRecord_perms) in
+                    let (tmp_420 : Permissions) =
+                      ((tmp_420 with<| Permissions_pxn := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+                    let (result : TLBRecord) = ((result with<| TLBRecord_perms := tmp_420|>)) in
+                    let (result : TLBRecord) =
+                      ((result with<| TLBRecord_nG := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+                    sail2_state_monad$returnS result) (\ (result : TLBRecord) . 
+                 let (tmp_430 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+                 let tmp_430 =
+                   ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_430 (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+                     :  3 words$word)) in
+                 let (tmp_440 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_440 = ((tmp_440 with<| Permissions_ap := tmp_430|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_440|>)) in
+                 let (tmp_450 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (AArch64_S1AttrDecode sh ((slice memattr (( 0 : int):ii) (( 3 : int):ii)  :  3 words$word)) acctype)) (\ (w__165 :
+                   MemoryAttributes) . 
+                 let (tmp_450 : AddressDescriptor) =
+                   ((tmp_450 with<| AddressDescriptor_memattrs := w__165|>)) in
+                 let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_450|>)) in
+                 let (tmp_460 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in
+                 let (tmp_460 : FullAddress) =
+                   ((tmp_460 with<|
+                     FullAddress_NS :=
+                       ((or_vec (vec_of_bits [access_vec_dec memattr (( 3 : int):ii)]  :  1 words$word) ns_table
+                          :  1 words$word))|>)) in
+                 let (tmp_470 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+                 let (tmp_470 : AddressDescriptor) =
+                   ((tmp_470 with<| AddressDescriptor_paddress := tmp_460|>)) in
+                 let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_470|>)) in
+                 sail2_state_monad$returnS result))
+               else
+                 let (tmp_480 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+                 let tmp_480 =
+                   ((set_slice (( 3 : int):ii) (( 2 : int):ii) tmp_480 (( 1 : int):ii) ((slice ap (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                     :  3 words$word)) in
+                 let (tmp_490 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_490 = ((tmp_490 with<| Permissions_ap := tmp_480|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_490|>)) in
+                 let (tmp_500 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in
+                 let tmp_500 =
+                   ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_500 (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+                     :  3 words$word)) in
+                 let (tmp_510 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_510 = ((tmp_510 with<| Permissions_ap := tmp_500|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_510|>)) in
+                 let (tmp_520 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_520 = ((tmp_520 with<| Permissions_xn := xn|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_520|>)) in
+                 let (result : TLBRecord) =
+                   (if ((HaveExtendedExecuteNeverExt () )) then
+                     let (tmp_530 : Permissions) = (result.TLBRecord_perms) in
+                     let (tmp_530 : Permissions) =
+                       ((tmp_530 with<|
+                         Permissions_xxn := ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)]  :  1 words$word))|>)) in
+                     (result with<| TLBRecord_perms := tmp_530|>)
+                   else result) in
+                 let (tmp_540 : Permissions) = (result.TLBRecord_perms) in
+                 let tmp_540 = ((tmp_540 with<| Permissions_pxn := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+                 let result = ((result with<| TLBRecord_perms := tmp_540|>)) in
+                 let result = ((result with<| TLBRecord_nG := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+                 let (tmp_550 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+                 (sail2_state_monad$liftRS (S2AttrDecode sh memattr acctype)) (\ (w__166 : MemoryAttributes) . 
+                 let (tmp_550 : AddressDescriptor) =
+                   ((tmp_550 with<| AddressDescriptor_memattrs := w__166|>)) in
+                 let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_550|>)) in
+                 let (tmp_560 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in
+                 let (tmp_560 : FullAddress) =
+                   ((tmp_560 with<| FullAddress_NS := ((vec_of_bits [B1]  :  1 words$word))|>)) in
+                 let (tmp_570 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+                 let (tmp_570 : AddressDescriptor) =
+                   ((tmp_570 with<| AddressDescriptor_paddress := tmp_560|>)) in
+                 let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_570|>)) in
+                 sail2_state_monad$returnS result)) (\ (result : TLBRecord) . 
+              let (tmp_580 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in
+              let tmp_580 = ((tmp_580 with<| FullAddress_physicaladdress := outputaddress|>)) in
+              let (tmp_590 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+              let tmp_590 = ((tmp_590 with<| AddressDescriptor_paddress := tmp_580|>)) in
+              let result = ((result with<| TLBRecord_addrdesc := tmp_590|>)) in
+              let (tmp_600 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+              (sail2_state_monad$liftRS (AArch64_NoFault () )) (\ (w__167 : FaultRecord) . 
+              let (tmp_600 : AddressDescriptor) =
+                ((tmp_600 with<| AddressDescriptor_fault := w__167|>)) in
+              let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_600|>)) in
+              let (result : TLBRecord) =
+                ((result with<|
+                  TLBRecord_contiguous := (((contiguousbit = (vec_of_bits [B1]  :  1 words$word))))|>)) in
+              let (result : TLBRecord) =
+                (if ((HaveCommonNotPrivateTransExt () )) then
+                  (result with<|
+                    TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 : int):ii)]  :  1 words$word))|>)
+                else result) in
+              sail2_state_monad$returnS result)))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
+
+
+(*val IsZero_slice2 : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*)
+
+val _ = Define `
+ ((IsZero_slice2:'n words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) xs i l=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (sail2_state_monad$returnS ((IsZero ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)))))))`;
+
+
+(*val AArch64_TranslateAddressS1Off : mword ty64 -> AccType -> bool -> M TLBRecord*)
+
+val _ = Define `
+ ((AArch64_TranslateAddressS1Off:(64)words$word -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "")
+   (undefined_TLBRecord () )) (\ (result : TLBRecord) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$bindS
+   (AddrTop vaddress F w__2.ProcState_EL) (\ (Top : ii) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (level : ii) .  sail2_state_monad$bindS
+   (IsZero_slice2 vaddress ((PAMax () ))
+     ((((((ex_int Top)) + (( 1 : int):ii))) - ((ex_int ((PAMax () ))))))) (\ (w__3 :
+     bool) . 
+   if ((~ w__3)) then
+     let level = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (w__4 : 52 bits) . 
+     let ipaddress = w__4 in
+     let secondstage = F in
+     let s2fs1walk = F in
+     let (tmp_1980 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+     (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk) (\ (w__5 :
+       FaultRecord) . 
+     let (tmp_1980 : AddressDescriptor) = ((tmp_1980 with<| AddressDescriptor_fault := w__5|>)) in
+     let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_1980|>)) in
+     sail2_state_monad$returnS result))
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS ((HasS2Translation () ))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 12 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (default_cacheable : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (cacheable : bool) .  sail2_state_monad$bindS
+     (if default_cacheable then
+        let (tmp_1990 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_1990 : MemoryAttributes) =
+          ((tmp_1990 with<| MemoryAttributes_typ := MemType_Normal|>)) in
+        let (tmp_2000 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2000 : AddressDescriptor) =
+          ((tmp_2000 with<| AddressDescriptor_memattrs := tmp_1990|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2000|>)) in
+        let (tmp_2010 : MemAttrHints) =
+          (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+        let (tmp_2010 : MemAttrHints) = ((tmp_2010 with<| MemAttrHints_attrs := MemAttr_WB|>)) in
+        let (tmp_2020 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2020 : MemoryAttributes) = ((tmp_2020 with<| MemoryAttributes_inner := tmp_2010|>)) in
+        let (tmp_2030 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2030 : AddressDescriptor) =
+          ((tmp_2030 with<| AddressDescriptor_memattrs := tmp_2020|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2030|>)) in
+        let (tmp_2040 : MemAttrHints) =
+          (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+        let (tmp_2040 : MemAttrHints) = ((tmp_2040 with<| MemAttrHints_hints := MemHint_RWA|>)) in
+        let (tmp_2050 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2050 : MemoryAttributes) = ((tmp_2050 with<| MemoryAttributes_inner := tmp_2040|>)) in
+        let (tmp_2060 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2060 : AddressDescriptor) =
+          ((tmp_2060 with<| AddressDescriptor_memattrs := tmp_2050|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2060|>)) in
+        let (tmp_2070 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2070 : MemoryAttributes) = ((tmp_2070 with<| MemoryAttributes_shareable := F|>)) in
+        let (tmp_2080 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2080 : AddressDescriptor) =
+          ((tmp_2080 with<| AddressDescriptor_memattrs := tmp_2070|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2080|>)) in
+        let (tmp_2090 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2090 : MemoryAttributes) =
+          ((tmp_2090 with<| MemoryAttributes_outershareable := F|>)) in
+        let (tmp_2100 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2100 : AddressDescriptor) =
+          ((tmp_2100 with<| AddressDescriptor_memattrs := tmp_2090|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2100|>)) in
+        sail2_state_monad$returnS result
+      else if (((acctype <> AccType_IFETCH))) then
+        let (tmp_2110 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let tmp_2110 = ((tmp_2110 with<| MemoryAttributes_typ := MemType_Device|>)) in
+        let (tmp_2120 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let tmp_2120 = ((tmp_2120 with<| AddressDescriptor_memattrs := tmp_2110|>)) in
+        let result = ((result with<| TLBRecord_addrdesc := tmp_2120|>)) in
+        let (tmp_2130 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let tmp_2130 = ((tmp_2130 with<| MemoryAttributes_device := DeviceType_nGnRnE|>)) in
+        let (tmp_2140 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let tmp_2140 = ((tmp_2140 with<| AddressDescriptor_memattrs := tmp_2130|>)) in
+        let result = ((result with<| TLBRecord_addrdesc := tmp_2140|>)) in
+        let (tmp_2150 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in sail2_state_monad$bindS
+        (undefined_MemAttrHints () ) (\ (w__8 : MemAttrHints) . 
+        let (tmp_2150 : MemoryAttributes) = ((tmp_2150 with<| MemoryAttributes_inner := w__8|>)) in
+        let (tmp_2160 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2160 : AddressDescriptor) =
+          ((tmp_2160 with<| AddressDescriptor_memattrs := tmp_2150|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2160|>)) in
+        sail2_state_monad$returnS result)
+      else sail2_state_monad$bindS
+        (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__9 :  32 words$word) . 
+        let (cacheable : bool) =
+          ((vec_of_bits [access_vec_dec w__9 (( 12 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (tmp_2170 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2170 : MemoryAttributes) =
+          ((tmp_2170 with<| MemoryAttributes_typ := MemType_Normal|>)) in
+        let (tmp_2180 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2180 : AddressDescriptor) =
+          ((tmp_2180 with<| AddressDescriptor_memattrs := tmp_2170|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2180|>)) in
+        let (result : TLBRecord) =
+          (if cacheable then
+            let (tmp_2190 : MemAttrHints) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+            let (tmp_2190 : MemAttrHints) = ((tmp_2190 with<| MemAttrHints_attrs := MemAttr_WT|>)) in
+            let (tmp_2200 : MemoryAttributes) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+            let (tmp_2200 : MemoryAttributes) =
+              ((tmp_2200 with<| MemoryAttributes_inner := tmp_2190|>)) in
+            let (tmp_2210 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+            let (tmp_2210 : AddressDescriptor) =
+              ((tmp_2210 with<| AddressDescriptor_memattrs := tmp_2200|>)) in
+            let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2210|>)) in
+            let (tmp_2220 : MemAttrHints) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+            let (tmp_2220 : MemAttrHints) = ((tmp_2220 with<| MemAttrHints_hints := MemHint_RA|>)) in
+            let (tmp_2230 : MemoryAttributes) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+            let (tmp_2230 : MemoryAttributes) =
+              ((tmp_2230 with<| MemoryAttributes_inner := tmp_2220|>)) in
+            let (tmp_2240 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+            let (tmp_2240 : AddressDescriptor) =
+              ((tmp_2240 with<| AddressDescriptor_memattrs := tmp_2230|>)) in
+            (result with<| TLBRecord_addrdesc := tmp_2240|>)
+          else
+            let (tmp_2250 : MemAttrHints) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+            let (tmp_2250 : MemAttrHints) = ((tmp_2250 with<| MemAttrHints_attrs := MemAttr_NC|>)) in
+            let (tmp_2260 : MemoryAttributes) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+            let (tmp_2260 : MemoryAttributes) =
+              ((tmp_2260 with<| MemoryAttributes_inner := tmp_2250|>)) in
+            let (tmp_2270 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+            let (tmp_2270 : AddressDescriptor) =
+              ((tmp_2270 with<| AddressDescriptor_memattrs := tmp_2260|>)) in
+            let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2270|>)) in
+            let (tmp_2280 : MemAttrHints) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in
+            let (tmp_2280 : MemAttrHints) = ((tmp_2280 with<| MemAttrHints_hints := MemHint_No|>)) in
+            let (tmp_2290 : MemoryAttributes) =
+              (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+            let (tmp_2290 : MemoryAttributes) =
+              ((tmp_2290 with<| MemoryAttributes_inner := tmp_2280|>)) in
+            let (tmp_2300 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+            let (tmp_2300 : AddressDescriptor) =
+              ((tmp_2300 with<| AddressDescriptor_memattrs := tmp_2290|>)) in
+            (result with<| TLBRecord_addrdesc := tmp_2300|>)) in
+        let (tmp_2310 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2310 : MemoryAttributes) = ((tmp_2310 with<| MemoryAttributes_shareable := T|>)) in
+        let (tmp_2320 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2320 : AddressDescriptor) =
+          ((tmp_2320 with<| AddressDescriptor_memattrs := tmp_2310|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2320|>)) in
+        let (tmp_2330 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+        let (tmp_2330 : MemoryAttributes) =
+          ((tmp_2330 with<| MemoryAttributes_outershareable := T|>)) in
+        let (tmp_2340 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+        let (tmp_2340 : AddressDescriptor) =
+          ((tmp_2340 with<| AddressDescriptor_memattrs := tmp_2330|>)) in
+        let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2340|>)) in
+        sail2_state_monad$returnS result)) (\ (result : TLBRecord) . 
+     let (tmp_2350 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in
+     let tmp_2350 =
+       ((tmp_2350 with<|
+         MemoryAttributes_outer :=
+           (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner)|>)) in
+     let (tmp_2360 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+     let tmp_2360 = ((tmp_2360 with<| AddressDescriptor_memattrs := tmp_2350|>)) in
+     let result = ((result with<| TLBRecord_addrdesc := tmp_2360|>)) in
+     let (tmp_2370 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+     (MemAttrDefaults result.TLBRecord_addrdesc.AddressDescriptor_memattrs) (\ (w__10 :
+       MemoryAttributes) . 
+     let tmp_2370 = ((tmp_2370 with<| AddressDescriptor_memattrs := w__10|>)) in
+     let result = ((result with<| TLBRecord_addrdesc := tmp_2370|>)) in
+     let (tmp_2380 : Permissions) = (result.TLBRecord_perms) in sail2_state_monad$bindS
+     (undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M) (\ (w__11 : 3 bits) . 
+     let tmp_2380 = ((tmp_2380 with<| Permissions_ap := w__11|>)) in
+     let result = ((result with<| TLBRecord_perms := tmp_2380|>)) in
+     let (tmp_2390 : Permissions) = (result.TLBRecord_perms) in
+     let tmp_2390 = ((tmp_2390 with<| Permissions_xn := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+     let result = ((result with<| TLBRecord_perms := tmp_2390|>)) in
+     let (tmp_2400 : Permissions) = (result.TLBRecord_perms) in
+     let tmp_2400 = ((tmp_2400 with<| Permissions_pxn := ((vec_of_bits [B0]  :  1 words$word))|>)) in
+     let result = ((result with<| TLBRecord_perms := tmp_2400|>)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__12 : 1 bits) . 
+     let result = ((result with<| TLBRecord_nG := w__12|>)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__13 : bool) . 
+     let result = ((result with<| TLBRecord_contiguous := w__13|>)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__14 : 4 bits) . 
+     let result = ((result with<| TLBRecord_domain := w__14|>)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__15 : ii) . 
+     let result = ((result with<| TLBRecord_level := w__15|>)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__16 : ii) . 
+     let result = ((result with<| TLBRecord_blocksize := w__16|>)) in
+     let (tmp_2410 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in
+     let tmp_2410 =
+       ((tmp_2410 with<|
+         FullAddress_physicaladdress := ((slice vaddress (( 0 : int):ii) (( 52 : int):ii)  :  52 words$word))|>)) in
+     let (tmp_2420 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+     let tmp_2420 = ((tmp_2420 with<| AddressDescriptor_paddress := tmp_2410|>)) in
+     let result = ((result with<| TLBRecord_addrdesc := tmp_2420|>)) in
+     let (tmp_2430 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in sail2_state_monad$bindS
+     (IsSecure () ) (\ (w__17 : bool) . 
+     let tmp_2430 =
+       ((tmp_2430 with<|
+         FullAddress_NS :=
+           (if w__17 then (vec_of_bits [B0]  :  1 words$word)
+            else (vec_of_bits [B1]  :  1 words$word))|>)) in
+     let (tmp_2440 : AddressDescriptor) = (result.TLBRecord_addrdesc) in
+     let tmp_2440 = ((tmp_2440 with<| AddressDescriptor_paddress := tmp_2430|>)) in
+     let result = ((result with<| TLBRecord_addrdesc := tmp_2440|>)) in
+     let (tmp_2450 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS
+     (AArch64_NoFault () ) (\ (w__18 : FaultRecord) . 
+     let (tmp_2450 : AddressDescriptor) = ((tmp_2450 with<| AddressDescriptor_fault := w__18|>)) in
+     let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2450|>)) in
+     sail2_state_monad$returnS result))))))))))))))))))))))))`;
+
+
+(*val AArch64_MaybeZeroRegisterUppers : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_MaybeZeroRegisterUppers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__0 "UsingAArch32()")
+   (sail2_state_monad$undefined_boolS () )) (\ (include_R15_name : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (last : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (first : ii) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$returnS (((w__1.ProcState_EL = EL0)))))
+     ( sail2_state_monad$bindS(ELUsingAArch32 EL1) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2))))) (\ (w__3 : bool) .  sail2_state_monad$bindS
+   (if w__3 then
+      let (first : ii) = ((( 0 : int):ii)) in
+      let (last : ii) = ((( 14 : int):ii)) in
+      let (include_R15_name : bool) = F in
+      sail2_state_monad$returnS (first, include_R15_name, last)
+    else sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS
+              (sail2_state$or_boolS
+                 ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+                  sail2_state_monad$returnS (((w__4.ProcState_EL = EL0)))))
+                 ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+                  sail2_state_monad$returnS (((w__5.ProcState_EL = EL1)))))) (sail2_state_monad$returnS ((HaveEL EL2))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__8 : bool) .  sail2_state_monad$returnS ((~ w__8)))))
+        ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__10 : bool) .  sail2_state_monad$returnS ((~ w__10))))) (\ (w__11 : bool) . 
+      let ((first : ii), (include_R15_name : bool), (last : ii)) =
+        (if w__11 then
+          let (first : ii) = ((( 0 : int):ii)) in
+          let (last : ii) = ((( 30 : int):ii)) in
+          let (include_R15_name : bool) = F in
+          (first, include_R15_name, last)
+        else
+          let (first : ii) = ((( 0 : int):ii)) in
+          let (last : ii) = ((( 30 : int):ii)) in
+          let (include_R15_name : bool) = T in
+          (first, include_R15_name, last)) in
+      sail2_state_monad$returnS (first, include_R15_name, last))) (\ varstup .  let ((first : ii), (include_R15_name :
+     bool), (last : ii)) = varstup in
+   (sail2_state$foreachS (index_list first last (( 1 : int):ii)) () 
+     (\ n unit_var .  sail2_state_monad$bindS
+       (sail2_state$and_boolS (sail2_state_monad$returnS ((((((n <> (( 15 : int):ii)))) \/ include_R15_name))))
+         ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER))) (\ (w__13 : bool) . 
+       if w__13 then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS R_ref) (\ (w__14 : ( 64 bits) list) . 
+         let (tmp_30 : 64 bits) = ((access_list_dec w__14 n  :  64 words$word)) in
+         let tmp_30 =
+           ((set_slice (( 64 : int):ii) (( 32 : int):ii) tmp_30 (( 32 : int):ii) ((Zeros__1 (( 32 : int):ii) ()   :  32 words$word))
+             :  64 words$word)) in sail2_state_monad$bindS
+         (sail2_state_monad$read_regS R_ref) (\ (w__15 : ( 64 words$word) list) . 
+         sail2_state_monad$write_regS R_ref ((update_list_dec w__15 n tmp_30  : ( 64 words$word) list))))
+       else sail2_state_monad$returnS () )))))))))))`;
+
+
+(*val DCPSInstruction : mword ty2 -> M unit*)
+
+val _ = Define `
+ ((DCPSInstruction:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el=
+    (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (handle_el : 2 bits) . 
+   let pat_0 = target_el in sail2_state_monad$bindS
+   (if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL2)))))
+        (sail2_state$and_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+            sail2_state_monad$returnS (((w__1.ProcState_EL = EL3)))))
+           ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . 
+      if w__4 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+        let (handle_el : 2 bits) = (w__5.ProcState_EL) in
+        sail2_state_monad$returnS handle_el)
+      else sail2_state_monad$bindS
+        (sail2_state$and_boolS
+          (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+             ( sail2_state_monad$bindS(IsSecure () ) (\ (w__6 : bool) .  sail2_state_monad$returnS ((~ w__6)))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__9 : bool) . 
+        if w__9 then sail2_state_monad$seqS (UndefinedFault () ) (sail2_state_monad$returnS handle_el)
+        else sail2_state_monad$returnS EL1))
+    else if (((pat_0 = EL2))) then
+      if ((~ ((HaveEL EL2)))) then sail2_state_monad$seqS (UndefinedFault () ) (sail2_state_monad$returnS handle_el)
+      else sail2_state_monad$bindS
+        (sail2_state$and_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+           sail2_state_monad$returnS (((w__10.ProcState_EL = EL3)))))
+          ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__11 : bool) .  sail2_state_monad$returnS ((~ w__11))))) (\ (w__12 : bool) . 
+        if w__12 then sail2_state_monad$returnS EL3
+        else sail2_state_monad$bindS
+          (IsSecure () ) (\ (w__13 : bool) . 
+          if w__13 then sail2_state_monad$seqS (UndefinedFault () ) (sail2_state_monad$returnS handle_el)
+          else sail2_state_monad$returnS EL2))
+    else if (((pat_0 = EL3))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref  : ( 32 words$word) M) (\ (w__14 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 16 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))) (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))) (\ (w__15 :
+        bool) .  sail2_state_monad$seqS
+      (if w__15 then UndefinedFault ()  else sail2_state_monad$returnS () ) (sail2_state_monad$returnS EL3))
+    else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS handle_el)) (\ (handle_el : 2 bits) .  sail2_state_monad$bindS
+   (IsSecure () ) (\ (from_secure : bool) .  sail2_state_monad$bindS
+   (ELUsingAArch32 handle_el) (\ (w__16 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if w__16 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (if (((w__17.ProcState_M = M32_Monitor))) then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__18 :  32 words$word) . 
+         sail2_state_monad$write_regS
+           SCR_ref
+           ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__18 (( 0 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)))
+       else sail2_state_monad$returnS () )
+      (UsingAArch32 () )) (\ (w__19 : bool) .  sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS w__19 "UsingAArch32()")
+      (let pat_0 = handle_el in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (if (((pat_0 = EL1))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+         (AArch32_WriteMode M32_Svc)
+         (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () )))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__21 : bool) . 
+         if w__21 then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . 
+           sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_PAN := ((vec_of_bits [B1]  :  1 words$word))|>))
+         else sail2_state_monad$returnS () )
+       else if (((pat_0 = EL2))) then AArch32_WriteMode M32_Hyp
+       else sail2_state_monad$seqS
+         (AArch32_WriteMode M32_Monitor)
+         (if ((HavePANExt () )) then
+           if ((~ from_secure)) then sail2_state_monad$bindS
+             (sail2_state_monad$read_regS PSTATE_ref) (\ (w__23 : ProcState) . 
+             sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_PAN := ((vec_of_bits [B0]  :  1 words$word))|>))
+           else sail2_state_monad$bindS
+             (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__24 : 32 bits) . 
+             if ((((vec_of_bits [access_vec_dec w__24 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+               (sail2_state_monad$read_regS PSTATE_ref) (\ (w__25 : ProcState) . 
+               sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_PAN := ((vec_of_bits [B1]  :  1 words$word))|>))
+             else sail2_state_monad$returnS () )
+         else sail2_state_monad$returnS () ))
+      (if (((handle_el = EL2))) then sail2_state_monad$bindS
+         (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__26 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+         (sail2_state_monad$write_regS ELR_hyp_ref w__26)
+         (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__27 : 32 bits) . 
+         sail2_state_monad$write_regS HSR_ref w__27))
+       else sail2_state_monad$bindS
+         (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__28 :  32 words$word) . 
+         set_LR w__28)))
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__29 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (aset_SPSR w__29)
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__30 : ProcState) .  sail2_state_monad$bindS
+      (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__31 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__30 with<| ProcState_E := ((vec_of_bits [access_vec_dec w__31 (( 25 : int):ii)]  :  1 words$word))|>))
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__32 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DLR_ref w__32)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__33 : 32 bits) . 
+      sail2_state_monad$write_regS DSPSR_ref w__33))))))))
+    else sail2_state_monad$bindS
+      (UsingAArch32 () ) (\ (w__34 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (if w__34 then AArch64_MaybeZeroRegisterUppers () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__35 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__35 with<| ProcState_nRW := ((vec_of_bits [B0]  :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__36 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__36 with<| ProcState_SP := ((vec_of_bits [B1]  :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__37 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__37 with<| ProcState_EL := handle_el|>))
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () )))
+        (sail2_state$or_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS (((handle_el = EL1))))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__38 : 32 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__38 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+           (sail2_state$and_boolS
+              (sail2_state$and_boolS
+                 (sail2_state$and_boolS (sail2_state_monad$returnS (((handle_el = EL2))))
+                    ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__40 : 64 bits) . 
+                     sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__40 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+                 ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__42 : 64 bits) . 
+                  sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__42 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__44 : 32 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__44 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))))) (\ (w__47 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (if w__47 then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS PSTATE_ref) (\ (w__48 : ProcState) . 
+         sail2_state_monad$write_regS PSTATE_ref (w__48 with<| ProcState_PAN := ((vec_of_bits [B1]  :  1 words$word))|>))
+       else sail2_state_monad$returnS () )
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__49 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (aset_ELR__1 w__49)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__50 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (aset_SPSR w__50)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__51 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (aset_ESR__1 w__51)
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__52 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DLR_EL0_ref w__52)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__53 : 32 bits) .  sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DSPSR_EL0_ref w__53)
+      (if ((HaveUAOExt () )) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__54 : ProcState) . 
+        sail2_state_monad$write_regS PSTATE_ref (w__54 with<| ProcState_UAO := ((vec_of_bits [B0]  :  1 words$word))|>))
+      else sail2_state_monad$returnS () ))))))))))))
+   (UpdateEDSCRFields () ))
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () )))
+        ( sail2_state_monad$bindS(aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__55 :  32 words$word) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__55 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+     ((ConstrainUnpredictableBool Unpredictable_IESBinDebug)))) (\ (w__58 : bool) . 
+   let (_ : unit) =
+     (if w__58 then ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All
+     else () ) in
+   sail2_state_monad$returnS () )))))))`;
+
+
+(*val aarch64_system_exceptions_debug_exception : mword ty2 -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_exceptions_debug_exception:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_level=  (DCPSInstruction target_level))`;
+
+
+(*val AArch64_GenerateDebugExceptionsFrom : mword ty2 -> bool -> mword ty1 -> M bool*)
+
+val _ = Define `
+ ((AArch64_GenerateDebugExceptionsFrom:(2)words$word -> bool ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) from secure mask=  (sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS OSLSR_EL1_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))) ((DoubleLockStatus () ))) ((Halted () ))) (\ (w__4 :
+     bool) . 
+   if w__4 then sail2_state_monad$returnS F
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ ((~ secure))))))
+       (sail2_state$or_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (route_to_el2 : bool) . 
+     let (target : 2 bits) = (if route_to_el2 then EL2 else EL1) in sail2_state_monad$bindS
+     (sail2_state$or_boolS (sail2_state_monad$returnS (((((~ ((HaveEL EL3)))) \/ ((~ secure))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL3_ref  : ( 32 words$word) M) (\ (w__8 : 32 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 16 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (enabled : bool) . 
+     if (((from = target))) then
+       sail2_state$and_boolS
+         (sail2_state$and_boolS (sail2_state_monad$returnS enabled)
+            ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref  : ( 32 words$word) M) (\ (w__9 : 32 bits) . 
+             sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 13 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+         (sail2_state_monad$returnS (((mask = (vec_of_bits [B0]  :  1 words$word)))))
+     else
+       let (enabled : bool) = (enabled /\ ((((lem$w2ui target)) > ((lem$w2ui from))))) in
+       sail2_state_monad$returnS enabled)))))`;
+
+
+(*val AArch64_GenerateDebugExceptions : unit -> M bool*)
+
+val _ = Define `
+ ((AArch64_GenerateDebugExceptions:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS
+   (IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   AArch64_GenerateDebugExceptionsFrom w__0.ProcState_EL w__1 w__2.ProcState_D)))))`;
+
+
+(*val AArch64_FaultSyndrome : bool -> FaultRecord -> M (mword ty25)*)
+
+val _ = Define `
+ ((AArch64_FaultSyndrome:bool -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->((((25)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d_side fault=  (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)")
+   (let (iss : 25 bits) = ((Zeros__1 (( 25 : int):ii) ()   :  25 words$word)) in sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) ((IsExternalSyncAbort__1 fault))) (\ (w__1 : bool) . 
+   let (iss : 25 bits) =
+     (if w__1 then (set_slice (( 25 : int):ii) (( 2 : int):ii) iss (( 11 : int):ii) fault.FaultRecord_errortype  :  25 words$word)
+     else iss) in sail2_state_monad$bindS
+   (if d_side then sail2_state_monad$bindS
+      (sail2_state$and_boolS ((IsSecondStage fault)) (sail2_state_monad$returnS ((~ fault.FaultRecord_s2fs1walk)))) (\ (w__3 :
+        bool) .  sail2_state_monad$bindS
+      (if w__3 then sail2_state_monad$bindS
+         (LSInstructionSyndrome ()   : ( 11 words$word) M) (\ (w__4 :  11 words$word) . 
+         let (iss : 25 bits) = ((set_slice (( 25 : int):ii) (( 11 : int):ii) iss (( 14 : int):ii) w__4  :  25 words$word)) in
+         sail2_state_monad$returnS iss)
+       else sail2_state_monad$returnS iss) (\ (iss : 25 bits) . 
+      let (iss : 25 bits) =
+        (if ((((((fault.FaultRecord_acctype = AccType_DC))) \/ ((((((fault.FaultRecord_acctype = AccType_IC))) \/ (((fault.FaultRecord_acctype = AccType_AT))))))))) then
+          let (iss : 25 bits) =
+            ((set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 8 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  25 words$word)) in
+          (set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 6 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  25 words$word)
+        else
+          (set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 6 : int):ii)
+             (if fault.FaultRecord_write then (vec_of_bits [B1]  :  1 words$word)
+              else (vec_of_bits [B0]  :  1 words$word))
+            :  25 words$word)) in
+      sail2_state_monad$returnS iss))
+    else sail2_state_monad$returnS iss) (\ (iss : 25 bits) .  sail2_state_monad$bindS
+   (IsExternalAbort__1 fault) (\ (w__5 : bool) . 
+   let (iss : 25 bits) =
+     (if w__5 then (set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 9 : int):ii) fault.FaultRecord_extflag  :  25 words$word)
+     else iss) in
+   let iss =
+     ((set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 7 : int):ii)
+        (if fault.FaultRecord_s2fs1walk then (vec_of_bits [B1]  :  1 words$word)
+         else (vec_of_bits [B0]  :  1 words$word))
+       :  25 words$word)) in sail2_state_monad$bindS
+   (EncodeLDFSC fault.FaultRecord_typ fault.FaultRecord_level  : ( 6 words$word) M) (\ (w__6 :
+      6 words$word) . 
+   let (iss : 25 bits) = ((set_slice (( 25 : int):ii) (( 6 : int):ii) iss (( 0 : int):ii) w__6  :  25 words$word)) in
+   sail2_state_monad$returnS iss)))))))`;
+
+
+(*val AArch64_AbortSyndrome : Exception -> FaultRecord -> mword ty64 -> M ExceptionRecord*)
+
+val _ = Define `
+ ((AArch64_AbortSyndrome:Exception -> FaultRecord ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ExceptionRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ fault vaddress=  (sail2_state_monad$bindS
+   (ExceptionSyndrome typ) (\ (exception : ExceptionRecord) . 
+   let (d_side : bool) = ((((typ = Exception_DataAbort))) \/ (((typ = Exception_Watchpoint)))) in sail2_state_monad$bindS
+   (AArch64_FaultSyndrome d_side fault  : ( 25 words$word) M) (\ (w__0 : 25 bits) . 
+   let exception = ((exception with<| ExceptionRecord_syndrome := w__0|>)) in sail2_state_monad$bindS
+   (ZeroExtend__1 (( 64 : int):ii) vaddress  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let exception = ((exception with<| ExceptionRecord_vaddress := w__1|>)) in sail2_state_monad$bindS
+   (IPAValid fault) (\ (w__2 : bool) . 
+   let (exception : ExceptionRecord) =
+     (if w__2 then
+       let (exception : ExceptionRecord) = ((exception with<| ExceptionRecord_ipavalid := T|>)) in
+       (exception with<| ExceptionRecord_ipaddress := (fault.FaultRecord_ipaddress)|>)
+     else (exception with<| ExceptionRecord_ipavalid := F|>)) in
+   sail2_state_monad$returnS exception))))))`;
+
+
+(*val AArch64_ExecutingATS1xPInstr : unit -> M bool*)
+
+val _ = Define `
+ ((AArch64_ExecutingATS1xPInstr:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (if ((~ ((HavePrivATExt () )))) then sail2_state_monad$returnS F
+   else sail2_state_monad$bindS
+     (ThisInstr0 ()   : ( 32 words$word) M) (\ (instr : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M) (\ (op2 : 3 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (CRm : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M) (\ (CRn : 4 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 3 : int):ii)  : ( 3 words$word) M) (\ (op1 : 3 bits) . 
+     let (w__0 : bool) =
+       (if (((((slice instr (( 22 : int):ii) (( 10 : int):ii)  :  10 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0]  :  10 words$word)))) then
+         let (op1 : 3 bits) = ((slice instr (( 16 : int):ii) (( 3 : int):ii)  :  3 words$word)) in
+         let (CRn : 4 bits) = ((slice instr (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word)) in
+         let (CRm : 4 bits) = ((slice instr (( 8 : int):ii) (( 4 : int):ii)  :  4 words$word)) in
+         let (op2 : 3 bits) = ((slice instr (( 5 : int):ii) (( 3 : int):ii)  :  3 words$word)) in
+         ((((((((((op1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((CRn = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word))))))) /\ (((CRm = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word))))))) /\ ((((((op2 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) \/ (((op2 = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))))
+       else F) in
+     sail2_state_monad$returnS w__0)))))))`;
+
+
+(*val AArch64_ExceptionClass : Exception -> mword ty2 -> M (ii * mword ty1)*)
+
+val _ = Define `
+ ((AArch64_ExceptionClass:Exception ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ target_el=  (sail2_state_monad$bindS
+   (ThisInstrLength () ) (\ (w__0 : ii) . 
+   let (il : 1 bits) =
+     (if (((((ex_int w__0)) = (( 32 : int):ii)))) then (vec_of_bits [B1]  :  1 words$word)
+     else (vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (from_32 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((from_32 \/ (((il = (vec_of_bits [B1]  :  1 words$word))))))) "(from_32 || (il == '1'))")
+   (undefined_int () )) (\ (ec : ii) .  sail2_state_monad$bindS
+   (case typ of
+     Exception_Uncategorized =>
+      let (ec : ii) = ((( 0 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_WFxTrap =>
+      let (ec : ii) = ((( 1 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP15RTTrap =>
+      let ec = ((( 3 : int):ii)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il))
+   | Exception_CP15RRTTrap =>
+      let ec = ((( 4 : int):ii)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il))
+   | Exception_CP14RTTrap =>
+      let ec = ((( 5 : int):ii)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il))
+   | Exception_CP14DTTrap =>
+      let ec = ((( 6 : int):ii)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il))
+   | Exception_AdvSIMDFPAccessTrap =>
+      let (ec : ii) = ((( 7 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_FPIDTrap =>
+      let (ec : ii) = ((( 8 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_CP14RRTTrap =>
+      let ec = ((( 12 : int):ii)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il))
+   | Exception_IllegalState =>
+      let (ec : ii) = ((( 14 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SupervisorCall =>
+      let (ec : ii) = ((( 17 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_HypervisorCall =>
+      let (ec : ii) = ((( 18 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_MonitorCall =>
+      let (ec : ii) = ((( 19 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SystemRegisterTrap =>
+      let ec = ((( 24 : int):ii)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((~ from_32)) "!(from_32)") (sail2_state_monad$returnS (ec, il))
+   | Exception_InstructionAbort =>
+      let (ec : ii) = ((( 32 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_PCAlignment =>
+      let (ec : ii) = ((( 34 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_DataAbort =>
+      let (ec : ii) = ((( 36 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SPAlignment =>
+      let ec = ((( 38 : int):ii)) in
+      let il = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((~ from_32)) "!(from_32)") (sail2_state_monad$returnS (ec, il))
+   | Exception_FPTrappedException =>
+      let (ec : ii) = ((( 40 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SError =>
+      let (ec : ii) = ((( 47 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_Breakpoint =>
+      let (ec : ii) = ((( 48 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SoftwareStep =>
+      let (ec : ii) = ((( 50 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_Watchpoint =>
+      let (ec : ii) = ((( 52 : int):ii)) in
+      let (il : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_SoftwareBreakpoint =>
+      let (ec : ii) = ((( 56 : int):ii)) in
+      sail2_state_monad$returnS (ec, il)
+   | Exception_VectorCatch =>
+      let ec = ((( 58 : int):ii)) in
+      let il = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il))
+   | _ => sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS (ec, il))
+   ) (\ varstup .  let ((ec : ii), (il : 1 bits)) = varstup in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state_monad$returnS ((((((((ex_int ec)) = (( 32 : int):ii)))) \/ ((((((((ex_int ec)) = (( 36 : int):ii)))) \/ ((((((((ex_int ec)) = (( 48 : int):ii)))) \/ ((((((((ex_int ec)) = (( 50 : int):ii)))) \/ (((((ex_int ec)) = (( 52 : int):ii)))))))))))))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+      sail2_state_monad$returnS (((target_el = w__1.ProcState_EL)))))) (\ (w__2 : bool) . 
+   let (ec : ii) = (if w__2 then ((ex_int ec)) + (( 1 : int):ii) else ec) in
+   let (ec : ii) =
+     (if (((((((((((ex_int ec)) = (( 17 : int):ii)))) \/ ((((((((ex_int ec)) = (( 18 : int):ii)))) \/ ((((((((ex_int ec)) = (( 19 : int):ii)))) \/ ((((((((ex_int ec)) = (( 40 : int):ii)))) \/ (((((ex_int ec)) = (( 56 : int):ii)))))))))))))))) /\ ((~ from_32))))) then
+       ((ex_int ec)) + (( 4 : int):ii)
+     else ec) in
+   sail2_state_monad$returnS (ec, il))))))))`;
+
+
+(*val AArch64_ReportException : ExceptionRecord -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((AArch64_ReportException:ExceptionRecord ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception target_el=
+    (let (typ : Exception) = (exception.ExceptionRecord_typ) in sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (il : 1 bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (ec : ii) .  sail2_state_monad$bindS
+   (AArch64_ExceptionClass typ target_el  : ((ii #  1 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let ec = tup__0 in
+   let il = tup__1 in
+   let (iss : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let (il : 1 bits) =
+     (if (((((((((((ex_int ec)) = (( 36 : int):ii)))) \/ (((((ex_int ec)) = (( 37 : int):ii))))))) /\ ((((vec_of_bits [access_vec_dec iss (( 24 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+       (vec_of_bits [B1]  :  1 words$word)
+     else il) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (aset_ESR__0 target_el
+     ((concat_vec
+         ((concat_vec
+             ((GetSlice_int ((make_the_value (( 6 : int):ii)  :  6 itself)) ec (( 0 : int):ii)  :  6 words$word)) il
+            :  7 words$word)) iss
+        :  32 words$word)))
+   (if ((((((typ = Exception_InstructionAbort))) \/ ((((((typ = Exception_PCAlignment))) \/ ((((((typ = Exception_DataAbort))) \/ (((typ = Exception_Watchpoint)))))))))))) then
+      aset_FAR__0 target_el exception.ExceptionRecord_vaddress
+    else sail2_state_monad$bindS
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+      aset_FAR__0 target_el w__0)))
+   (if (((target_el = EL2))) then
+     if exception.ExceptionRecord_ipavalid then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS HPFAR_EL2_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+       sail2_state_monad$write_regS
+         HPFAR_EL2_ref
+         ((set_slice (( 64 : int):ii) (( 40 : int):ii) w__1 (( 4 : int):ii)
+             ((slice exception.ExceptionRecord_ipaddress (( 12 : int):ii) (( 40 : int):ii)  :  40 words$word))
+            :  64 words$word)))
+     else sail2_state_monad$bindS
+       (sail2_state_monad$read_regS HPFAR_EL2_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  sail2_state_monad$bindS
+       (undefined_bitvector (( 40 : int):ii)  : ( 40 words$word) M) (\ (w__3 :  40 words$word) . 
+       sail2_state_monad$write_regS HPFAR_EL2_ref ((set_slice (( 64 : int):ii) (( 40 : int):ii) w__2 (( 4 : int):ii) w__3  :  64 words$word))))
+   else sail2_state_monad$returnS () ))))))`;
+
+
+(*val AArch64_ESBOperation : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_ESBOperation:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 3 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (route_to_el3 : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (route_to_el2 : bool) . 
+   let (target : 2 bits) = (if route_to_el3 then EL3 else if route_to_el2 then EL2 else EL1) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (mask_active : bool) .  sail2_state_monad$bindS
+   (if (((target = EL1))) then
+      sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) .  sail2_state_monad$returnS (((w__6.ProcState_EL = EL0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) .  sail2_state_monad$returnS (((w__7.ProcState_EL = EL1)))))
+    else sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveVirtHostExt () )) /\ (((target = EL2)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) .  sail2_state_monad$bindS
+         (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__10 : 64 bits) . 
+         sail2_state_monad$returnS ((((access_vec_dec w__9 (( 34 : int):ii), access_vec_dec w__10 (( 27 : int):ii)) = (B1, B1)))))))) (\ (w__11 :
+        bool) . 
+      if w__11 then
+        sail2_state$or_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . 
+           sail2_state_monad$returnS (((w__12.ProcState_EL = EL0)))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . 
+           sail2_state_monad$returnS (((w__13.ProcState_EL = EL2)))))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . 
+        let (mask_active : bool) = (w__15.ProcState_EL = target) in
+        sail2_state_monad$returnS mask_active))) (\ (mask_active : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . 
+   let (mask_set : bool) = (w__16.ProcState_A = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state$or_boolS ((Halted () )) ((ExternalDebugInterruptsDisabled target))) (\ (intdis : bool) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . 
+         sail2_state_monad$returnS ((((lem$w2ui target)) < ((lem$w2ui w__19.ProcState_EL)))))) (sail2_state_monad$returnS intdis))
+     (sail2_state_monad$returnS (((mask_active /\ mask_set))))) (\ (masked : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (DISR_EL1 : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 25 : int):ii)  : ( 25 words$word) M) (\ (syndrome64 : 25 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (implicit_esb : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (DISR : 32 bits) .  sail2_state_monad$bindS
+   (undefined_AArch32_SErrorSyndrome () ) (\ (syndrome32 : AArch32_SErrorSyndrome) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS ((SErrorPending () )) (sail2_state_monad$returnS masked)) (\ (w__22 : bool) . 
+   if w__22 then sail2_state_monad$bindS
+     (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__23 :  2 words$word) .  sail2_state_monad$bindS
+     (ELUsingAArch32 w__23) (\ (w__24 : bool) .  sail2_state_monad$seqS
+     (if w__24 then sail2_state_monad$bindS
+        (AArch32_PhysicalSErrorSyndrome () ) (\ (w__25 : AArch32_SErrorSyndrome) . 
+        let syndrome32 = w__25 in sail2_state_monad$bindS
+        (AArch32_ReportDeferredSError syndrome32.AArch32_SErrorSyndrome_AET
+           syndrome32.AArch32_SErrorSyndrome_ExT
+          : ( 32 words$word) M) (\ (w__26 : 32 bits) . 
+        let (DISR : 32 bits) = w__26 in
+        sail2_state_monad$returnS () ))
+      else
+        let implicit_esb = F in sail2_state_monad$bindS
+        (AArch64_PhysicalSErrorSyndrome implicit_esb  : ( 25 words$word) M) (\ (w__27 : 25 bits) . 
+        let syndrome64 = w__27 in sail2_state_monad$bindS
+        (AArch64_ReportDeferredSError syndrome64  : ( 64 words$word) M) (\ (w__28 : 64 bits) . 
+        let (DISR_EL1 : 64 bits) = w__28 in
+        sail2_state_monad$returnS () )))
+     (ClearPendingPhysicalSError () )))
+   else sail2_state_monad$returnS () )))))))))))))))`;
+
+
+val _ = Define `
+ ((AArch64_CheckAndUpdateDescriptor:DescriptorUpdate -> FaultRecord -> bool ->(64)words$word -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) result fault secondstage vaddress acctype iswrite s2fs1walk hwupdatewalk__arg=
+    (sail2_state_monad$catch_early_returnS
+     ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((aget_SCTLR__1 ()   : ( 32 words$word) M))) (\ (w__0 :  32 words$word) . 
+      let reversedescriptors = (((access_vec_dec w__0 (( 25 : int):ii))) = B1) in
+      let hwupdatewalk = hwupdatewalk__arg in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hw_update_AF : bool) . 
+      let (hw_update_AF : bool) =
+        (if result.DescriptorUpdate_AF then
+          if (((fault.FaultRecord_typ = Fault_None))) then T
+          else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then T
+          else F
+        else F) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hw_update_AP : bool) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (write_perm_req : bool) . 
+      let (hw_update_AP : bool) =
+        (if (((result.DescriptorUpdate_AP /\ (((fault.FaultRecord_typ = Fault_None)))))) then
+          let (write_perm_req : bool) =
+            ((((iswrite \/ ((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW))))))))) /\ ((~ s2fs1walk))) in
+          ((((write_perm_req /\ ((~ ((((((acctype = AccType_AT))) \/ (((acctype = AccType_DC))))))))))) \/ hwupdatewalk)
+        else F) in sail2_state_monad$bindS
+      (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (desc : 64 bits) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_AccessDescriptor () )) (\ (accdesc : AccessDescriptor) .  sail2_state_monad$bindS
+      (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr2 : AddressDescriptor) .  sail2_state_monad$seqS
+      (if (((hw_update_AF \/ hw_update_AP))) then sail2_state_monad$bindS
+         (sail2_state$or_boolS (sail2_state_monad$returnS secondstage)
+           ( sail2_state_monad$bindS(sail2_state_monad$liftRS (HasS2Translation () )) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 :
+           bool) .  sail2_state_monad$bindS
+         (if w__2 then
+            let (descaddr2 : AddressDescriptor) = (result.DescriptorUpdate_descaddr) in
+            sail2_state_monad$returnS descaddr2
+          else
+            let hwupdatewalk = T in sail2_state_monad$bindS
+            (sail2_state_monad$liftRS (AArch64_SecondStageWalk result.DescriptorUpdate_descaddr vaddress acctype iswrite
+                     (( 8 : int):ii) hwupdatewalk)) (\ (w__3 : AddressDescriptor) . 
+            let descaddr2 = w__3 in sail2_state_monad$seqS
+            (if ((IsFault descaddr2)) then
+               (sail2_state_monad$early_returnS descaddr2.AddressDescriptor_fault : (unit, FaultRecord) MR)
+             else sail2_state_monad$returnS () )
+            (sail2_state_monad$returnS descaddr2))) (\ (descaddr2 : AddressDescriptor) .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (CreateAccessDescriptor AccType_ATOMICRW)) (\ (w__4 : AccessDescriptor) . 
+         let accdesc = w__4 in sail2_state_monad$bindS
+         (sail2_state_monad$liftRS ((aget__Mem descaddr2 (( 8 : int):ii) accdesc  : ( 64 words$word) M))) (\ (w__5 : 64 bits) . 
+         let desc = w__5 in sail2_state_monad$bindS
+         (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc  : ( 64 words$word) M))
+          else sail2_state_monad$returnS desc) (\ (desc : 64 bits) . 
+         let (desc : 64 bits) =
+           (if hw_update_AF then
+             (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 10 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word)
+           else desc) in
+         let (desc : 64 bits) =
+           (if hw_update_AP then
+             (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii)
+                (if secondstage then (vec_of_bits [B1]  :  1 words$word)
+                 else (vec_of_bits [B0]  :  1 words$word))
+               :  64 words$word)
+           else desc) in sail2_state_monad$bindS
+         (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc  : ( 64 words$word) M))
+          else sail2_state_monad$returnS desc) (\ (desc : 64 bits) . 
+         sail2_state_monad$liftRS (aset__Mem descaddr2 (( 8 : int):ii) accdesc desc)))))))
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS fault)))))))))))`;
+
+
+(*val AArch64_BreakpointValueMatch : ii -> mword ty64 -> bool -> bool*)
+
+val _ = Define `
+ ((AArch64_BreakpointValueMatch:int ->(64)words$word -> bool -> bool) n__arg vaddress linked_to=  F)`;
+
+
+(*val AArch64_StateMatch : mword ty2 -> mword ty1 -> mword ty2 -> bool -> mword ty4 -> bool -> bool -> M bool*)
+
+val _ = Define `
+ ((AArch64_StateMatch:(2)words$word ->(1)words$word ->(2)words$word -> bool ->(4)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SSC__arg HMC__arg PxC__arg linked__arg LBN isbreakpnt ispriv=
+    (sail2_state_monad$catch_early_returnS
+     (let HMC = HMC__arg in
+     let PxC = PxC__arg in
+     let SSC = SSC__arg in
+     let linked = linked__arg in sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((((((((((and_vec
+                                     ((concat_vec ((concat_vec HMC SSC  :  3 words$word)) PxC
+                                        :  5 words$word)) (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)
+                                    :  5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))) \/ ((((((((and_vec
+                                         ((concat_vec ((concat_vec HMC SSC  :  3 words$word)) PxC
+                                            :  5 words$word))
+                                         (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)
+                                        :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) \/ ((((((((and_vec
+                                             ((concat_vec ((concat_vec HMC SSC  :  3 words$word)) PxC
+                                                :  5 words$word))
+                                             (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)
+                                            :  5 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))) \/ ((((((((concat_vec ((concat_vec HMC SSC  :  3 words$word)) PxC
+                                                :  5 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))) \/ ((((((((concat_vec ((concat_vec HMC SSC  :  3 words$word))
+                                                     PxC
+                                                    :  5 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))) \/ (((((and_vec
+                                                     ((concat_vec
+                                                         ((concat_vec HMC SSC  :  3 words$word)) PxC
+                                                        :  5 words$word))
+                                                     (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)
+                                                    :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word))))))))))))))))))) \/ (((((((((HMC = (vec_of_bits [B0]  :  1 words$word)))) /\ (((PxC = (vec_of_bits [B0;B0]  :  2 words$word))))))) /\ (((((~ isbreakpnt)) \/ ((~ ((HaveAArch32EL EL1))))))))))))) \/ (((((((((SSC = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ (((SSC = (vec_of_bits [B1;B0]  :  2 words$word))))))) /\ ((~ ((HaveEL EL3)))))))))) \/ ((((((((((((((concat_vec HMC SSC  :  3 words$word)) <> (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((concat_vec HMC SSC  :  3 words$word)) <> (vec_of_bits [B1;B1;B1]  :  3 words$word))))))) /\ ((~ ((HaveEL EL3))))))) /\ ((~ ((HaveEL EL2)))))))))) \/ ((((((((concat_vec ((concat_vec HMC SSC  :  3 words$word)) PxC  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))) /\ ((~ ((HaveEL EL2)))))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$liftRS ((undefined_bitvector (( 5 : int):ii)  : ( 5 words$word) M))) (\ (tmp_50 : 5 bits) .  sail2_state_monad$bindS
+        (sail2_state_monad$liftRS ((ConstrainUnpredictableBits (( 5 : int):ii) Unpredictable_RESBPWPCTRL
+                 : ((Constraint #  5 words$word)) M))) (\ (w__0 : (Constraint # 5 bits)) . 
+        let (tup__0, tup__1) = w__0 in
+        let c = tup__0 in
+        let tmp_50 = tup__1 in
+        let (tmp_60 : 5 bits) = tmp_50 in
+        let HMC = ((vec_of_bits [access_vec_dec tmp_60 (( 4 : int):ii)]  :  1 words$word)) in
+        let (tmp_70 : 4 bits) = ((slice tmp_60 (( 0 : int):ii) (( 4 : int):ii)  :  4 words$word)) in
+        let SSC = ((slice tmp_70 (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+        let PxC = ((slice tmp_70 (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS
+        (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_DISABLED))) \/ (((c = Constraint_UNKNOWN)))))) "((c == Constraint_DISABLED) || (c == Constraint_UNKNOWN))"))
+        (if (((c = Constraint_DISABLED))) then (sail2_state_monad$early_returnS F : (unit, bool) MR)
+         else sail2_state_monad$returnS () ))
+        (sail2_state_monad$returnS (HMC, PxC, SSC, c))))
+      else sail2_state_monad$returnS (HMC, PxC, SSC, c)) (\ varstup .  let ((HMC :  1 words$word), (PxC :  2 words$word), (SSC :
+        2 words$word), (c : Constraint)) = varstup in
+     let (EL3_match : bool) =
+       ((((((HaveEL EL3)) /\ (((HMC = (vec_of_bits [B1]  :  1 words$word))))))) /\ ((((vec_of_bits [access_vec_dec SSC (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))) in
+     let (EL2_match : bool) = (((HaveEL EL2)) /\ (((HMC = (vec_of_bits [B1]  :  1 words$word))))) in
+     let (EL1_match : bool) =
+       ((vec_of_bits [access_vec_dec PxC (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+     let (EL0_match : bool) =
+       ((vec_of_bits [access_vec_dec PxC (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (priv_match : bool) .  sail2_state_monad$bindS
+     (if (((((~ ispriv)) /\ ((~ isbreakpnt))))) then sail2_state_monad$returnS EL0_match
+      else sail2_state_monad$bindS
+        (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . 
+        let p__294 = (w__1.ProcState_EL) in
+        let pat_0 = p__294 in
+        let (priv_match : bool) =
+          (if (((pat_0 = EL3))) then EL3_match
+          else if (((pat_0 = EL2))) then EL2_match
+          else if (((pat_0 = EL1))) then EL1_match
+          else EL0_match) in
+        sail2_state_monad$returnS priv_match)) (\ (priv_match : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (security_state_match : bool) . 
+     let b__0 = SSC in sail2_state_monad$bindS
+     (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS T
+      else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$liftRS (IsSecure () )) (\ (w__2 : bool) . 
+        let (security_state_match : bool) = (~ w__2) in
+        sail2_state_monad$returnS security_state_match)
+      else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$liftRS (IsSecure () )
+      else sail2_state_monad$returnS T) (\ (security_state_match : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (undefined_int () )) (\ (last_ctx_cmp : ii) .  sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (undefined_int () )) (\ (first_ctx_cmp : ii) .  sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (undefined_int () )) (\ (lbn : ii) .  sail2_state_monad$bindS
+     (if linked then
+        let lbn = (lem$w2ui LBN) in sail2_state_monad$bindS
+        (sail2_state_monad$liftRS ((sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M))) (\ (w__4 : 64 bits) .  sail2_state_monad$bindS
+        (sail2_state_monad$liftRS ((sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M))) (\ (w__5 : 64 bits) . 
+        let first_ctx_cmp =
+          (((lem$w2ui ((slice w__4 (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word)))) -
+            ((lem$w2ui ((slice w__5 (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word))))) in sail2_state_monad$bindS
+        (sail2_state_monad$liftRS ((sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M))) (\ (w__6 : 64 bits) . 
+        let last_ctx_cmp = (lem$w2ui ((slice w__6 (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word))) in
+        if (((((((ex_int lbn)) < ((ex_int first_ctx_cmp)))) \/ ((((ex_int lbn)) > ((ex_int last_ctx_cmp))))))) then sail2_state_monad$bindS
+          (sail2_state_monad$liftRS (ConstrainUnpredictableInteger first_ctx_cmp last_ctx_cmp Unpredictable_BPNOTCTXCMP)) (\ varstup .  let (tup__0, tup__1) = varstup in
+          let c = tup__0 in
+          let lbn = tup__1 in sail2_state_monad$bindS (sail2_state_monad$seqS
+          (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_DISABLED))) \/ ((((((c = Constraint_NONE))) \/ (((c = Constraint_UNKNOWN))))))))) "((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))"))
+          (case c of
+            Constraint_DISABLED => sail2_state_monad$seqS (sail2_state_monad$early_returnS F : (unit, bool) MR) (sail2_state_monad$returnS linked)
+          | Constraint_NONE => sail2_state_monad$returnS F
+          )) (\ (linked : bool) . 
+          sail2_state_monad$returnS (lbn, linked)))
+        else sail2_state_monad$returnS (lbn, linked))))
+      else sail2_state_monad$returnS (lbn, linked)) (\ varstup .  let ((lbn : ii), (linked : bool)) = varstup in sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (linked_match : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (linked_to : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (vaddress : 64 bits) .  sail2_state_monad$bindS
+     (if linked then sail2_state_monad$bindS
+        (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M))) (\ (w__7 : 64 bits) . 
+        let (vaddress : 64 bits) = w__7 in
+        let (linked_to : bool) = T in
+        let (linked_match : bool) = (AArch64_BreakpointValueMatch lbn vaddress linked_to) in
+        sail2_state_monad$returnS linked_match)
+      else sail2_state_monad$returnS linked_match) (\ (linked_match : bool) . 
+     sail2_state_monad$returnS ((((((priv_match /\ security_state_match))) /\ (((((~ linked)) \/ linked_match)))))))))))))))))))))))`;
+
+
+(*val AArch64_WatchpointMatch : ii -> mword ty64 -> ii -> bool -> bool -> M bool*)
+
+val _ = Define `
+ ((AArch64_WatchpointMatch:int ->(64)words$word -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n vaddress size1 ispriv iswrite=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))")
+   (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M)) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((n <= ((lem$w2ui ((slice w__2 (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word)))))) "(n <= UInt((ID_AA64DFR0_EL1).WRPs))")
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__3 : ( 32 bits) list) . 
+   let (enabled : bool) =
+     ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n  :  32 words$word)) (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__4 : ( 32 bits) list) . 
+   let (linked : bool) =
+     ((vec_of_bits [access_vec_dec ((access_list_dec w__4 n  :  32 words$word)) (( 20 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+   let (isbreakpnt : bool) = F in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__5 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__6 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__7 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__8 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (AArch64_StateMatch ((slice ((access_list_dec w__5 n  :  32 words$word)) (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word))
+     (vec_of_bits [access_vec_dec ((access_list_dec w__6 n  :  32 words$word)) (( 13 : int):ii)]  :  1 words$word)
+     ((slice ((access_list_dec w__7 n  :  32 words$word)) (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) linked
+     ((slice ((access_list_dec w__8 n  :  32 words$word)) (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word)) isbreakpnt
+     ispriv) (\ (state_match : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__9 : ( 32 bits) list) . 
+   let (ls_match : bool) =
+     ((vec_of_bits [access_vec_dec
+                       ((slice ((access_list_dec w__9 n  :  32 words$word)) (( 3 : int):ii) (( 2 : int):ii)  :  2 words$word))
+                       (if iswrite then (( 1 : int):ii)
+                        else (( 0 : int):ii))]
+         :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+   let (value_match_name : bool) = F in sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) ((size1 - (( 1 : int):ii))) (( 1 : int):ii)) value_match_name
+     (\ byte value_match_name . 
+       sail2_state$or_boolS (sail2_state_monad$returnS value_match_name)
+         ((AArch64_WatchpointByteMatch n ((add_vec_int vaddress byte  :  64 words$word)))))) (\ (value_match_name :
+     bool) . 
+   sail2_state_monad$returnS (((((((((value_match_name /\ state_match))) /\ ls_match))) /\ enabled)))))))))))))))))`;
+
+
+(*val AArch64_BreakpointMatch : ii -> mword ty64 -> ii -> M bool*)
+
+val _ = Define `
+ ((AArch64_BreakpointMatch:int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n vaddress size1=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))")
+   (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M)) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((n <= ((lem$w2ui ((slice w__2 (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word)))))) "(n <= UInt((ID_AA64DFR0_EL1).BRPs))")
+   (sail2_state_monad$read_regS DBGBCR_EL1_ref)) (\ (w__3 : ( 32 bits) list) . 
+   let (enabled : bool) =
+     ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n  :  32 words$word)) (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+   let (ispriv : bool) = (w__4.ProcState_EL <> EL0) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__5 : ( 32 bits) list) . 
+   let (linked : bool) =
+     (((and_vec ((slice ((access_list_dec w__5 n  :  32 words$word)) (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word))
+           (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)
+          :  4 words$word)) = (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)) in
+   let (isbreakpnt : bool) = T in
+   let (linked_to : bool) = F in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__6 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__7 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__8 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__9 : ( 32 bits) list) .  sail2_state_monad$bindS
+   (AArch64_StateMatch ((slice ((access_list_dec w__6 n  :  32 words$word)) (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word))
+     (vec_of_bits [access_vec_dec ((access_list_dec w__7 n  :  32 words$word)) (( 13 : int):ii)]  :  1 words$word)
+     ((slice ((access_list_dec w__8 n  :  32 words$word)) (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) linked
+     ((slice ((access_list_dec w__9 n  :  32 words$word)) (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word)) isbreakpnt
+     ispriv) (\ (state_match : bool) . 
+   let (value_match_name : bool) = (AArch64_BreakpointValueMatch n vaddress linked_to) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (match_i : bool) .  sail2_state_monad$bindS
+   (if (((((HaveAnyAArch32 () )) /\ (((size1 = (( 4 : int):ii))))))) then
+      let match_i =
+        (AArch64_BreakpointValueMatch n ((add_vec_int vaddress (( 2 : int):ii)  :  64 words$word)) linked_to) in
+      if (((((~ value_match_name)) /\ match_i))) then
+        ConstrainUnpredictableBool Unpredictable_BPMATCHHALF
+      else sail2_state_monad$returnS value_match_name
+    else sail2_state_monad$returnS value_match_name) (\ (value_match_name : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec vaddress (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__11 : ( 32 bits) list) . 
+      sail2_state_monad$returnS (((((slice ((access_list_dec w__11 n  :  32 words$word)) (( 5 : int):ii) (( 4 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B1;B1;B1]  :  4 words$word))))))) (\ (w__12 : bool) .  sail2_state_monad$bindS
+   (if w__12 then
+      if value_match_name then ConstrainUnpredictableBool Unpredictable_BPMATCHHALF
+      else sail2_state_monad$returnS value_match_name
+    else sail2_state_monad$returnS value_match_name) (\ (value_match_name : bool) . 
+   let (val_match : bool) = ((((value_match_name /\ state_match))) /\ enabled) in
+   sail2_state_monad$returnS val_match)))))))))))))))))`;
+
+
+(*val AArch64_CheckBreakpoint : mword ty64 -> ii -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_CheckBreakpoint:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress size1=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))")
+   (sail2_state$or_boolS
+     (sail2_state$and_boolS ((UsingAArch32 () )) (sail2_state_monad$returnS ((((((size1 = (( 2 : int):ii)))) \/ (((size1 = (( 4 : int):ii)))))))))
+     (sail2_state_monad$returnS (((size1 = (( 4 : int):ii))))))) (\ (w__4 : bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__4 "((UsingAArch32() && ((size == 2) || (size == 4))) || (size == 4))")
+   (let (val_match : bool) = F in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (match_i : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) ((lem$w2ui ((slice w__5 (( 12 : int):ii) (( 4 : int):ii)  :  4 words$word)))) (( 1 : int):ii)) (match_i,
+                                                                                             val_match)
+     (\ i varstup .  let (match_i, val_match) = varstup in sail2_state_monad$bindS
+       (AArch64_BreakpointMatch i vaddress size1) (\ (w__6 : bool) . 
+       let (match_i : bool) = w__6 in
+       let (val_match : bool) = (val_match \/ match_i) in
+       sail2_state_monad$returnS (match_i, val_match)))) (\ varstup .  let ((match_i : bool), (val_match : bool)) = varstup in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) .  sail2_state_monad$bindS
+   (undefined_AccType () ) (\ (acctype : AccType) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (reason : 6 bits) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS val_match) ((HaltOnBreakpointOrWatchpoint () ))) (\ (w__8 : bool) . 
+   if w__8 then
+     let reason = DebugHalt_Breakpoint in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (Halt reason) (undefined_FaultRecord () )) (\ (w__9 : FaultRecord) .  sail2_state_monad$returnS w__9)
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS val_match)
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 15 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) ((AArch64_GenerateDebugExceptions () ))) (\ (w__13 :
+       bool) . 
+     if w__13 then
+       let acctype = AccType_IFETCH in
+       let iswrite = F in
+       AArch64_DebugFault acctype iswrite
+     else AArch64_NoFault () ))))))))))))))`;
+
+
+(*val AArch64_BranchAddr : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AArch64_BranchAddr:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress=  (sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__0)) "!(UsingAArch32())")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$bindS
+   (AddrTop vaddress T w__1.ProcState_EL) (\ (w__2 : ii) .  sail2_state_monad$bindS
+   (coerce_int_nat w__2) (\ (msbit : ii) . 
+   if (((((ex_nat msbit)) = (( 63 : int):ii)))) then sail2_state_monad$returnS vaddress
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$or_boolS
+          (sail2_state$or_boolS
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+              sail2_state_monad$returnS (((w__3.ProcState_EL = EL0)))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+              sail2_state_monad$returnS (((w__4.ProcState_EL = EL1)))))) ((IsInHost () )))
+       (sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec vaddress msbit]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))) (\ (w__8 : bool) . 
+     sail2_state_monad$returnS (if w__8 then
+               (sext_slice (( 64 : int):ii) vaddress (( 0 : int):ii) ((((ex_nat msbit)) + (( 1 : int):ii)))
+                 :  64 words$word)
+             else
+               (zext_slice (( 64 : int):ii) vaddress (( 0 : int):ii) ((((ex_nat msbit)) + (( 1 : int):ii)))
+                 :  64 words$word)))))))))`;
+
+
+(*val BranchTo : forall 'N . Size 'N => mword 'N -> BranchType -> M unit*)
+
+val _ = Define `
+ ((BranchTo:'N words$word -> BranchType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target branch_type=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS BranchTaken_ref T)
+   (let (_ : unit) = (Hint_Branch branch_type) in
+   if (((((int_of_num (words$word_len target))) = (( 32 : int):ii)))) then sail2_state_monad$bindS
+     (UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS w__0 "UsingAArch32()")
+     (ZeroExtend__1 (( 64 : int):ii) target  : ( 64 words$word) M)) (\ (w__1 : 64 bits) . 
+     sail2_state_monad$write_regS PC_ref w__1))
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state_monad$returnS (((((int_of_num (words$word_len target))) = (( 64 : int):ii)))))
+       ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2))))) (\ (w__3 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS w__3 "((N == 64) && !(UsingAArch32()))")
+     (AArch64_BranchAddr ((slice target (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))  : ( 64 words$word) M)) (\ (w__4 : 64
+       bits) . 
+     sail2_state_monad$write_regS PC_ref w__4)))))`;
+
+
+(*val aarch64_branch_unconditional_immediate : BranchType -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_unconditional_immediate:BranchType ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) branch_type offset=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if (((branch_type = BranchType_CALL))) then sail2_state_monad$bindS
+      (aget_PC ()   : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+      aset_X (( 30 : int):ii) ((add_vec_int w__0 (( 4 : int):ii)  :  64 words$word)))
+    else sail2_state_monad$returnS () )
+   (aget_PC ()   : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
+   BranchTo ((add_vec w__1 offset  :  64 words$word)) branch_type)))`;
+
+
+(*val branch_unconditional_immediate_decode : mword ty1 -> mword ty26 -> M unit*)
+
+val _ = Define `
+ ((branch_unconditional_immediate_decode:(1)words$word ->(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op imm26=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (branch_type : BranchType) =
+     (if (((op = (vec_of_bits [B1]  :  1 words$word)))) then BranchType_CALL
+     else BranchType_JMP) in sail2_state_monad$bindS
+   (SignExtend__0 ((concat_vec imm26 (vec_of_bits [B0;B0]  :  2 words$word)  :  28 words$word))
+      ((make_the_value (( 64 : int):ii)  :  64 itself))
+     : ( 64 words$word) M) (\ (offset : 64 bits) . 
+   aarch64_branch_unconditional_immediate branch_type offset))))`;
+
+
+(*val aarch64_branch_conditional_test : ii -> mword ty1 -> ii -> mword ty64 -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_conditional_test:int ->(1)words$word -> int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) bit_pos bit_val l__143 offset t=
+    (if (((l__143 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (operand : 8 bits) . 
+     if ((((vec_of_bits [access_vec_dec operand bit_pos]  :  1 words$word) = bit_val))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+       BranchTo ((add_vec w__0 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__143 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (operand : 16 bits) . 
+     if ((((vec_of_bits [access_vec_dec operand bit_pos]  :  1 words$word) = bit_val))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+       BranchTo ((add_vec w__1 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__143 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (operand : 32 bits) . 
+     if ((((vec_of_bits [access_vec_dec operand bit_pos]  :  1 words$word) = bit_val))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+       BranchTo ((add_vec w__2 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__143 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (operand : 64 bits) . 
+     if ((((vec_of_bits [access_vec_dec operand bit_pos]  :  1 words$word) = bit_val))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
+       BranchTo ((add_vec w__3 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__143 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (operand : 128 bits) . 
+     if ((((vec_of_bits [access_vec_dec operand bit_pos]  :  1 words$word) = bit_val))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+       BranchTo ((add_vec w__4 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else
+     let dbytes = (ex_int ((l__143 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val branch_conditional_test_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty14 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((branch_conditional_test_decode:(1)words$word ->(1)words$word ->(5)words$word ->(14)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b5 op b40 imm14 Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (t : ii) = (lem$w2ui Rt) in
+   let (datasize : int) =
+     (if (((b5 = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (bit_pos : ii) = (lem$w2ui ((concat_vec b5 b40  :  6 words$word))) in
+   let (bit_val : 1 bits) = op in sail2_state_monad$bindS
+   (SignExtend__0 ((concat_vec imm14 (vec_of_bits [B0;B0]  :  2 words$word)  :  16 words$word))
+      ((make_the_value (( 64 : int):ii)  :  64 itself))
+     : ( 64 words$word) M) (\ (offset : 64 bits) . 
+   aarch64_branch_conditional_test bit_pos bit_val datasize offset t))))`;
+
+
+(*val aarch64_branch_conditional_cond : mword ty4 -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_conditional_cond:(4)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition offset=  (sail2_state_monad$bindS
+   (ConditionHolds condition) (\ (w__0 : bool) . 
+   if w__0 then sail2_state_monad$bindS
+     (aget_PC ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+     BranchTo ((add_vec w__1 offset  :  64 words$word)) BranchType_JMP)
+   else sail2_state_monad$returnS () )))`;
+
+
+(*val branch_conditional_cond_decode : mword ty1 -> mword ty19 -> mword ty1 -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((branch_conditional_cond_decode:(1)words$word ->(19)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) o1 imm19 o0 cond=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+      ((make_the_value (( 64 : int):ii)  :  64 itself))
+     : ( 64 words$word) M)) (\ (offset : 64 bits) . 
+   let (condition : 4 bits) = cond in
+   aarch64_branch_conditional_cond condition offset)))`;
+
+
+(*val aarch64_branch_conditional_compare : ii -> bool -> mword ty64 -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_conditional_compare:int -> bool ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__138 iszero offset t=
+    (if (((l__138 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (operand1 : 8 bits) . 
+     if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+       BranchTo ((add_vec w__0 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__138 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (operand1 : 16 bits) . 
+     if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+       BranchTo ((add_vec w__1 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__138 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (operand1 : 32 bits) . 
+     if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+       BranchTo ((add_vec w__2 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__138 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (operand1 : 64 bits) . 
+     if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
+       BranchTo ((add_vec w__3 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else if (((l__138 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (operand1 : 128 bits) . 
+     if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS
+       (aget_PC ()   : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+       BranchTo ((add_vec w__4 offset  :  64 words$word)) BranchType_JMP)
+     else sail2_state_monad$returnS () )
+   else
+     let dbytes = (ex_int ((l__138 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val branch_conditional_compare_decode : mword ty1 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((branch_conditional_compare_decode:(1)words$word ->(1)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op imm19 Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (t : ii) = (lem$w2ui Rt) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (iszero : bool) = (op = (vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+   (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+      ((make_the_value (( 64 : int):ii)  :  64 itself))
+     : ( 64 words$word) M) (\ (offset : 64 bits) . 
+   aarch64_branch_conditional_compare datasize iszero offset t))))`;
+
+
+(*val AArch64_TakeReset : bool -> M unit*)
+
+val _ = Define `
+ ((AArch64_TakeReset:bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cold_reset=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ ((HighestELUsingAArch32 () )))) "!(HighestELUsingAArch32())")
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_nRW := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (if ((HaveEL EL3)) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_EL := EL3|>))
+    else if ((HaveEL EL2)) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_EL := EL2|>))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_EL := EL1|>))))
+   (let (_ : unit) = (AArch64_ResetControlRegisters cold_reset) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_SP := ((vec_of_bits [B1]  :  1 words$word))|>))
+   (let split_vec = ((vec_of_bits [B1;B1;B1;B1]  :  4 words$word)) in
+   let (tup__0, tup__1, tup__2, tup__3) =
+     ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_D := tup__0|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_A := tup__1|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_I := tup__2|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_F := tup__3|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_SS := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) .  sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_IL := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (AArch64_ResetGeneralRegisters () ))
+   (AArch64_ResetSIMDFPRegisters () ))
+   (AArch64_ResetSpecialRegisters () ))
+   (let (_ : unit) = (ResetExternalDebugRegisters cold_reset) in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (rv : 64 bits) .  sail2_state_monad$bindS
+   (if ((HaveEL EL3)) then (sail2_state_monad$read_regS RVBAR_EL3_ref  : ( 64 words$word) M)
+    else if ((HaveEL EL2)) then (sail2_state_monad$read_regS RVBAR_EL2_ref  : ( 64 words$word) M)
+    else (sail2_state_monad$read_regS RVBAR_EL1_ref  : ( 64 words$word) M)) (\ (rv : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS ((IsZero_slice rv ((PAMax () )) (((( 64 : int):ii) - ((ex_int ((PAMax () ))))))))
+     ((IsZero_slice rv (( 0 : int):ii) (( 2 : int):ii)))) (\ (w__16 : bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__16 "(IsZero((rv)<PAMax()+:((63 - PAMax()) + 1)>) && IsZero((rv)<0+:((1 - 0) + 1)>))")
+   (BranchTo rv BranchType_UNKNOWN)))))))))))))))))`;
+
+
+(*val __TakeColdReset : unit -> M unit*)
+
+val _ = Define `
+ ((TakeColdReset:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_nRW := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) .  sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_SS := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (ResetInterruptState () ))
+   (ResetMemoryState () )) (ResetExecuteState () )) (AArch64_TakeReset T)))))`;
+
+
+(*val AArch64_TakeException : mword ty2 -> ExceptionRecord -> mword ty64 -> ii -> M unit*)
+
+val _ = Define `
+ ((AArch64_TakeException:(2)words$word -> ExceptionRecord ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el exception preferred_exception_return vect_offset__arg=
+    (let (vect_offset : ii) = vect_offset__arg in
+   let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL target_el)))
+        ( sail2_state_monad$bindS(ELUsingAArch32 target_el) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+      sail2_state_monad$returnS ((((lem$w2ui target_el)) >= ((lem$w2ui w__2.ProcState_EL))))))) (\ (w__3 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__3 "((HaveEL(target_el) && !(ELUsingAArch32(target_el))) && (UInt(target_el) >= UInt((PSTATE).EL)))")
+   (UsingAArch32 () )) (\ (from_32 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if from_32 then AArch64_MaybeZeroRegisterUppers () 
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) .  sail2_state_monad$bindS
+   (if ((((lem$w2ui target_el)) > ((lem$w2ui w__4.ProcState_EL)))) then sail2_state_monad$bindS
+      (sail2_state_monad$undefined_boolS () ) (\ (lower_32 : bool) .  sail2_state_monad$bindS
+      (if (((target_el = EL3))) then sail2_state_monad$bindS
+         (sail2_state$and_boolS ( sail2_state_monad$bindS(IsSecure () ) (\ (w__5 : bool) .  sail2_state_monad$returnS ((~ w__5))))
+           (sail2_state_monad$returnS ((HaveEL EL2)))) (\ (w__6 : bool) . 
+         if w__6 then ELUsingAArch32 EL2
+         else ELUsingAArch32 EL1)
+       else sail2_state_monad$bindS
+         (sail2_state$and_boolS
+           (sail2_state$and_boolS ((IsInHost () ))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+               sail2_state_monad$returnS (((w__10.ProcState_EL = EL0)))))) (sail2_state_monad$returnS (((target_el = EL2))))) (\ (w__12 :
+           bool) . 
+         if w__12 then ELUsingAArch32 EL0
+         else ELUsingAArch32 ((sub_vec_int target_el (( 1 : int):ii)  :  2 words$word)))) (\ (lower_32 : bool) . 
+      let (vect_offset : ii) = (vect_offset + (if lower_32 then (( 1536 : int):ii) else (( 1024 : int):ii))) in
+      sail2_state_monad$returnS vect_offset))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . 
+      let (vect_offset : ii) =
+        (if (((w__15.ProcState_SP = (vec_of_bits [B1]  :  1 words$word)))) then
+          ((ex_int vect_offset)) + (( 512 : int):ii)
+        else vect_offset) in
+      sail2_state_monad$returnS vect_offset)) (\ (vect_offset : ii) .  sail2_state_monad$bindS
+   (GetPSRFromPSTATE ()   : ( 32 words$word) M) (\ (spsr : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if ((HaveUAOExt () )) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_UAO := ((vec_of_bits [B0]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () )
+   (if ((~ ((((((exception.ExceptionRecord_typ = Exception_IRQ))) \/ (((exception.ExceptionRecord_typ = Exception_FIQ)))))))) then
+      AArch64_ReportException exception target_el
+    else sail2_state_monad$returnS () ))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_EL := target_el|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_nRW := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_SP := ((vec_of_bits [B1]  :  1 words$word))|>))
+   (aset_SPSR spsr))
+   (aset_ELR__1 preferred_exception_return))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_SS := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (let split_vec = ((vec_of_bits [B1;B1;B1;B1]  :  4 words$word)) in
+   let (tup__0, tup__1, tup__2, tup__3) =
+     ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_D := tup__0|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_A := tup__1|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_I := tup__2|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_F := tup__3|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_IL := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (if from_32 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__26 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_T := ((vec_of_bits [B0]  :  1 words$word))|>)))
+    else sail2_state_monad$returnS () ))
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () )))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__28 : ProcState) . 
+            sail2_state_monad$returnS (((w__28.ProcState_EL = EL1)))))
+           (sail2_state$and_boolS
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__29 : ProcState) . 
+               sail2_state_monad$returnS (((w__29.ProcState_EL = EL2))))) ((ELIsInHost EL0)))))
+     ( sail2_state_monad$bindS(aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__34 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__34 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__35 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__35 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__36 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__36 with<| ProcState_PAN := ((vec_of_bits [B1]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () )
+   (aget_VBAR__1 ()   : ( 64 words$word) M)) (\ (w__37 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (BranchTo
+     ((concat_vec ((slice w__37 (( 11 : int):ii) (( 53 : int):ii)  :  53 words$word))
+         ((GetSlice_int ((make_the_value (( 11 : int):ii)  :  11 itself)) vect_offset (( 0 : int):ii)  :  11 words$word))
+        :  64 words$word)) BranchType_EXCEPTION)
+   (sail2_state_monad$undefined_boolS () )) (\ (iesb_req : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () )))
+     ( sail2_state_monad$bindS(aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__38 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__38 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__39 : bool) .  sail2_state_monad$seqS
+   (if w__39 then
+      let (_ : unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in
+      let iesb_req = T in
+      TakeUnmaskedPhysicalSErrorInterrupts iesb_req
+    else sail2_state_monad$returnS () )
+   (EndOfInstruction () ))))))))))))))))))))))`;
+
+
+(*val TrapPACUse : mword ty2 -> M unit*)
+
+val _ = Define `
+ ((TrapPACUse:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL target_el)) /\ (((target_el <> EL0)))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+      sail2_state_monad$returnS ((((lem$w2ui target_el)) >= ((lem$w2ui w__0.ProcState_EL))))))) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__1 "((HaveEL(target_el) && (target_el != EL0)) && (UInt(target_el) >= UInt((PSTATE).EL)))")
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) .  sail2_state_monad$bindS
+   (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_PACTrap) (\ (w__2 : ExceptionRecord) . 
+   let exception = w__2 in
+   AArch64_TakeException target_el exception preferred_exception_return vect_offset))))))`;
+
+
+(*val Strip : mword ty64 -> bool -> M (mword ty64)*)
+
+val _ = Define `
+ ((Strip:(64)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) A data=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (original_ptr : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (extfield : 64 bits) .  sail2_state_monad$bindS
+   (CalculateTBI A data) (\ (tbi : bool) .  sail2_state_monad$bindS
+   (CalculateBottomPACBit A (vec_of_bits [access_vec_dec A (( 55 : int):ii)]  :  1 words$word)) (\ (w__0 : ii) . 
+   let bottom_PAC_bit = (ex_int w__0) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (let extfield =
+     ((replicate_bits (vec_of_bits [access_vec_dec A (( 55 : int):ii)]  :  1 words$word) (( 64 : int):ii)  :  64 words$word)) in
+   let (original_ptr : 64 bits) =
+     (if tbi then
+       (concat_vec ((slice A (( 56 : int):ii) (( 8 : int):ii)  :  8 words$word))
+          ((slice_slice_concat (( 56 : int):ii) extfield (( 0 : int):ii)
+              ((((~ bottom_PAC_bit)) + (( 56 : int):ii))) A (( 0 : int):ii) bottom_PAC_bit
+             :  56 words$word))
+         :  64 words$word)
+     else
+       (slice_slice_concat (( 64 : int):ii) extfield (( 0 : int):ii)
+          ((((~ bottom_PAC_bit)) + (( 64 : int):ii))) A (( 0 : int):ii) bottom_PAC_bit
+         :  64 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+   let p__293 = (w__1.ProcState_EL) in
+   let pat_0 = p__293 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__5 : bool) .  sail2_state_monad$returnS ((~ w__5)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__8 : bool) . 
+      let TrapEL2 = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__9 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__10 : bool) . 
+      let (TrapEL3 : bool) = w__10 in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__11 : bool) .  sail2_state_monad$returnS ((~ w__11)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__13 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let TrapEL2 = w__14 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__15 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__16 : bool) . 
+      let (TrapEL3 : bool) = w__16 in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3)))
+    else if (((pat_0 = EL2))) then
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__17 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__18 : bool) . 
+      let (TrapEL3 : bool) = w__18 in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3))
+    else
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3)) (\ varstup .  let ((TrapEL2 : bool), (TrapEL3 : bool)) = varstup in
+   if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else sail2_state_monad$returnS original_ptr)))))))))))`;
+
+
+(*val aarch64_integer_pac_strip_dp_1src : ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_strip_dp_1src:int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d data=
+    (if ((HavePACExt () )) then sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+     (Strip w__0 data  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  aset_X d w__1))
+   else sail2_state_monad$returnS () ))`;
+
+
+(*val integer_pac_strip_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_strip_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = ((( 30 : int):ii)) in
+   let (data : bool) = F in
+   aarch64_integer_pac_strip_dp_1src d data)))`;
+
+
+(*val AuthIB : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AuthIB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIBKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIBKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APIBKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__292 = (w__2.ProcState_EL) in
+   let pat_0 = p__292 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 30 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 30 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (Auth X Y APIBKey_EL1 F (vec_of_bits [B1]  :  1 words$word)  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_autib_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_autib_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if ((HavePACExt () )) then
+     if source_is_sp then sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+       (AuthIB w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+     else sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+       (AuthIB w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))
+   else sail2_state_monad$returnS () ))`;
+
+
+(*val integer_pac_autib_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_autib_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (undefined_int () )) (\ (d : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (n : ii) . 
+   let (source_is_sp : bool) = F in
+   let b__0 = ((concat_vec CRm op2  :  7 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (n : ii) = ((( 31 : int):ii)) in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (source_is_sp : bool) = T in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else sail2_state_monad$bindS
+      (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0]  :  7 words$word)))) then
+         let (d : ii) = ((( 17 : int):ii)) in
+         let (n : ii) = ((( 16 : int):ii)) in
+         sail2_state_monad$returnS (d, n)
+       else sail2_state_monad$seqS
+         (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIA")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIB")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIA")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIA")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIB")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIA")
+          else sail2_state_monad$throwS (Error_See "XPACLRI"))
+         (sail2_state_monad$returnS (d, n))) (\ varstup .  let ((d : ii), (n : ii)) = varstup in
+      sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup .  let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in
+   aarch64_integer_pac_autib_dp_1src d n source_is_sp)))))`;
+
+
+(*val AuthIA : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AuthIA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIAKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIAKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APIAKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__291 = (w__2.ProcState_EL) in
+   let pat_0 = p__291 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 31 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 31 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (Auth X Y APIAKey_EL1 F (vec_of_bits [B0]  :  1 words$word)  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_autia_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_autia_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if ((HavePACExt () )) then
+     if source_is_sp then sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+       (AuthIA w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+     else sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+       (AuthIA w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))
+   else sail2_state_monad$returnS () ))`;
+
+
+(*val integer_pac_autia_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_autia_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (undefined_int () )) (\ (d : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (n : ii) . 
+   let (source_is_sp : bool) = F in
+   let b__0 = ((concat_vec CRm op2  :  7 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B0]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (n : ii) = ((( 31 : int):ii)) in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (source_is_sp : bool) = T in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else sail2_state_monad$bindS
+      (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0]  :  7 words$word)))) then
+         let (d : ii) = ((( 17 : int):ii)) in
+         let (n : ii) = ((( 16 : int):ii)) in
+         sail2_state_monad$returnS (d, n)
+       else sail2_state_monad$seqS
+         (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIA")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIB")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIB")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIA")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIB")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIB")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "XPACLRI")
+          else sail2_state_monad$throwS (Error_See "HINT"))
+         (sail2_state_monad$returnS (d, n))) (\ varstup .  let ((d : ii), (n : ii)) = varstup in
+      sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup .  let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in
+   aarch64_integer_pac_autia_dp_1src d n source_is_sp)))))`;
+
+
+(*val aarch64_branch_unconditional_register : BranchType -> ii -> ii -> bool -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_unconditional_register:BranchType -> int -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) branch_type m n pac source_is_sp use_key_a=  (sail2_state_monad$bindS
+   (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (target : 64 bits) .  sail2_state_monad$bindS
+   (if pac then sail2_state_monad$bindS
+      (if source_is_sp then (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+       else (aget_X (( 64 : int):ii) m  : ( 64 words$word) M)) (\ (modifier : 64 bits) . 
+      if use_key_a then (AuthIA target modifier  : ( 64 words$word) M)
+      else (AuthIB target modifier  : ( 64 words$word) M))
+    else sail2_state_monad$returnS target) (\ (target : 64 bits) .  sail2_state_monad$seqS
+   (if (((branch_type = BranchType_CALL))) then sail2_state_monad$bindS
+      (aget_PC ()   : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+      aset_X (( 30 : int):ii) ((add_vec_int w__4 (( 4 : int):ii)  :  64 words$word)))
+    else sail2_state_monad$returnS () )
+   (BranchTo target branch_type)))))`;
+
+
+(*val AuthDB : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AuthDB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDBKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDBKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APDBKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__290 = (w__2.ProcState_EL) in
+   let pat_0 = p__290 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 13 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 13 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (Auth X Y APDBKey_EL1 T (vec_of_bits [B1]  :  1 words$word)  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_autdb_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_autdb_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if source_is_sp then sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+     (AuthDB w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+     (AuthDB w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))))`;
+
+
+(*val AuthDA : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AuthDA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDAKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDAKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APDAKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__289 = (w__2.ProcState_EL) in
+   let pat_0 = p__289 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (Auth X Y APDAKey_EL1 T (vec_of_bits [B0]  :  1 words$word)  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_autda_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_autda_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if source_is_sp then sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+     (AuthDA w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+     (AuthDA w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))))`;
+
+
+(*val AddPACIB : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AddPACIB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIBKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIBKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APIBKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__288 = (w__2.ProcState_EL) in
+   let pat_0 = p__288 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 30 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 30 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (AddPAC X Y APIBKey_EL1 F  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_pacib_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_pacib_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if ((HavePACExt () )) then
+     if source_is_sp then sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+       (AddPACIB w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+     else sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+       (AddPACIB w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))
+   else sail2_state_monad$returnS () ))`;
+
+
+(*val integer_pac_pacib_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacib_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (undefined_int () )) (\ (d : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (n : ii) . 
+   let (source_is_sp : bool) = F in
+   let b__0 = ((concat_vec CRm op2  :  7 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (n : ii) = ((( 31 : int):ii)) in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (source_is_sp : bool) = T in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else sail2_state_monad$bindS
+      (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0]  :  7 words$word)))) then
+         let (d : ii) = ((( 17 : int):ii)) in
+         let (n : ii) = ((( 16 : int):ii)) in
+         sail2_state_monad$returnS (d, n)
+       else sail2_state_monad$seqS
+         (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIA")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIA")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIB")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIA")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIA")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIB")
+          else sail2_state_monad$throwS (Error_See "XPACLRI"))
+         (sail2_state_monad$returnS (d, n))) (\ varstup .  let ((d : ii), (n : ii)) = varstup in
+      sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup .  let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in
+   aarch64_integer_pac_pacib_dp_1src d n source_is_sp)))))`;
+
+
+(*val AddPACIA : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AddPACIA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIAKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APIAKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APIAKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__287 = (w__2.ProcState_EL) in
+   let pat_0 = p__287 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 31 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 31 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (AddPAC X Y APIAKey_EL1 F  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_pacia_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_pacia_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if ((HavePACExt () )) then
+     if source_is_sp then sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+       (AddPACIA w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+     else sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+       (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+       (AddPACIA w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))
+   else sail2_state_monad$returnS () ))`;
+
+
+(*val integer_pac_pacia_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacia_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (undefined_int () )) (\ (d : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (n : ii) . 
+   let (source_is_sp : bool) = F in
+   let b__0 = ((concat_vec CRm op2  :  7 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (n : ii) = ((( 31 : int):ii)) in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B1]  :  7 words$word)))) then
+      let (d : ii) = ((( 30 : int):ii)) in
+      let (source_is_sp : bool) = T in
+      sail2_state_monad$returnS (d, n, source_is_sp)
+    else sail2_state_monad$bindS
+      (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)))) then
+         let (d : ii) = ((( 17 : int):ii)) in
+         let (n : ii) = ((( 16 : int):ii)) in
+         sail2_state_monad$returnS (d, n)
+       else sail2_state_monad$seqS
+         (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIB")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIA")
+          else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0]  :  7 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIB")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "PACIB")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIA")
+          else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word)))) then
+            sail2_state_monad$throwS (Error_See "AUTIB")
+          else sail2_state_monad$throwS (Error_See "XPACLRI"))
+         (sail2_state_monad$returnS (d, n))) (\ varstup .  let ((d : ii), (n : ii)) = varstup in
+      sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup .  let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in
+   aarch64_integer_pac_pacia_dp_1src d n source_is_sp)))))`;
+
+
+(*val AddPACGA : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AddPACGA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APGAKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APGAKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APGAKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__286 = (w__2.ProcState_EL) in
+   let pat_0 = p__286 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__6 : bool) .  sail2_state_monad$returnS ((~ w__6)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__9 : bool) . 
+      let TrapEL2 = w__9 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+      let (TrapEL3 : bool) =
+        ((vec_of_bits [access_vec_dec w__10 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__11 : bool) .  sail2_state_monad$returnS ((~ w__11)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__13 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let TrapEL2 = w__14 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__15 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__16 : bool) . 
+      let (TrapEL3 : bool) = w__16 in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3)))
+    else if (((pat_0 = EL2))) then
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__17 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__18 : bool) . 
+      let (TrapEL3 : bool) = w__18 in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3))
+    else
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (TrapEL2, TrapEL3)) (\ varstup .  let ((TrapEL2 : bool), (TrapEL3 : bool)) = varstup in
+   if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else sail2_state_monad$bindS
+     (ComputePAC X Y ((slice APGAKey_EL1 (( 64 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice APGAKey_EL1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       : ( 64 words$word) M) (\ (w__21 :  64 words$word) . 
+     sail2_state_monad$returnS ((concat_vec ((slice w__21 (( 32 : int):ii) (( 32 : int):ii)  :  32 words$word))
+                ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+               :  64 words$word)))))))))))`;
+
+
+(*val aarch64_integer_pac_pacga_dp_2src : ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_pacga_dp_2src:int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d m n source_is_sp=
+    (if source_is_sp then sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+     (AddPACGA w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+     (AddPACGA w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))))`;
+
+
+(*val AddPACDB : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AddPACDB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDBKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDBKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APDBKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__285 = (w__2.ProcState_EL) in
+   let pat_0 = p__285 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 13 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 13 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (AddPAC X Y APDBKey_EL1 T  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_pacdb_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_pacdb_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if source_is_sp then sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+     (AddPACDB w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+     (AddPACDB w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))))`;
+
+
+(*val AddPACDA : mword ty64 -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((AddPACDA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (Enable : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDAKeyHi_EL1_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS APDAKeyLo_EL1_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (APDAKey_EL1 : 128 bits) =
+     ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+        ((slice w__1 (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+       :  128 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+   let p__284 = (w__2.ProcState_EL) in
+   let pat_0 = p__284 in sail2_state_monad$bindS
+   (if (((pat_0 = EL0))) then sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (IsEL1Regime : bool) .  sail2_state_monad$bindS
+      (if IsEL1Regime then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let Enable = w__8 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__12 : bool) . 
+      let TrapEL2 = w__12 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__14 : bool) . 
+      let (TrapEL3 : bool) = w__14 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))))
+    else if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 : int):ii)]  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) .  sail2_state_monad$returnS ((~ w__16)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__19 : bool) . 
+      let TrapEL2 = w__19 in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__20 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__21 : bool) . 
+      let (TrapEL3 : bool) = w__21 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__22 : 32 bits) . 
+      let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 : int):ii)]  :  1 words$word)) in
+      let TrapEL2 = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__23 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) (\ (w__24 : bool) . 
+      let (TrapEL3 : bool) = w__24 in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCTLR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 : int):ii)]  :  1 words$word)) in
+      let (TrapEL2 : bool) = F in
+      let (TrapEL3 : bool) = F in
+      sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup .  let ((Enable : 1 bits), (TrapEL2 :
+     bool), (TrapEL3 : bool)) = varstup in
+   if (((Enable = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$returnS X
+   else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+   else (AddPAC X Y APDAKey_EL1 T  : ( 64 words$word) M))))))))))`;
+
+
+(*val aarch64_integer_pac_pacda_dp_1src : ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_pac_pacda_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp=
+    (if source_is_sp then sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+     (AddPACDA w__0 w__1  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  aset_X d w__2)))
+   else sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) d  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) n  : ( 64 words$word) M) (\ (w__4 :  64 words$word) .  sail2_state_monad$bindS
+     (AddPACDA w__3 w__4  : ( 64 words$word) M) (\ (w__5 :  64 words$word) .  aset_X d w__5)))))`;
+
+
+(*val AArch64_WatchpointException : mword ty64 -> FaultRecord -> M unit*)
+
+val _ = Define `
+ ((AArch64_WatchpointException:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL3))) "((PSTATE).EL != EL3)")
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+            sail2_state_monad$returnS (((w__3.ProcState_EL = EL0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+            sail2_state_monad$returnS (((w__4.ProcState_EL = EL1)))))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref  : ( 32 words$word) M) (\ (w__8 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (AArch64_AbortSyndrome Exception_Watchpoint fault vaddress) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$returnS (((w__10.ProcState_EL = EL2)))))
+     (sail2_state_monad$returnS route_to_el2)) (\ (w__11 : bool) . 
+   if w__11 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException EL1 exception preferred_exception_return vect_offset)))))))`;
+
+
+(*val AArch64_WFxTrap : mword ty2 -> bool -> M unit*)
+
+val _ = Define `
+ ((AArch64_WFxTrap:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el is_wfe=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((lem$w2ui target_el)) > ((lem$w2ui w__0.ProcState_EL)))) "(UInt(target_el) > UInt((PSTATE).EL))")
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_WFxTrap) (\ (exception : ExceptionRecord) . 
+   let (tmp_2720 : 25 bits) = (exception.ExceptionRecord_syndrome) in sail2_state_monad$bindS
+   (ConditionSyndrome ()   : ( 5 words$word) M) (\ (w__1 :  5 words$word) . 
+   let tmp_2720 = ((set_slice (( 25 : int):ii) (( 5 : int):ii) tmp_2720 (( 20 : int):ii) w__1  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2720|>)) in
+   let (tmp_2730 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2730 =
+     ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2730 (( 0 : int):ii)
+        (if is_wfe then (vec_of_bits [B1]  :  1 words$word)
+         else (vec_of_bits [B0]  :  1 words$word))
+       :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2730|>)) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((((((target_el = EL1))) /\ ((HaveEL EL2))))))
+        ( sail2_state_monad$bindS(IsSecure () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__5 : bool) . 
+   if w__5 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))`;
+
+
+(*val AArch64_CheckForWFxTrap : mword ty2 -> bool -> M unit*)
+
+val _ = Define `
+ ((AArch64_CheckForWFxTrap:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el is_wfe=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((HaveEL target_el)) "HaveEL(target_el)")
+   (sail2_state_monad$undefined_boolS () )) (\ (trap : bool) . 
+   let pat_0 = target_el in sail2_state_monad$bindS
+   (if (((pat_0 = EL1))) then sail2_state_monad$bindS
+      (if is_wfe then sail2_state_monad$bindS
+         (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__0 (( 18 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__1 (( 16 : int):ii)]  :  1 words$word))) (\ (w__2 :  1 words$word) . 
+      let (trap : bool) = (w__2 = (vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS trap)
+    else if (((pat_0 = EL2))) then sail2_state_monad$bindS
+      (if is_wfe then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__3 (( 14 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 13 : int):ii)]  :  1 words$word))) (\ (w__5 :  1 words$word) . 
+      let (trap : bool) = (w__5 = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS trap)
+    else sail2_state_monad$bindS
+      (if is_wfe then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 13 : int):ii)]  :  1 words$word))
+       else sail2_state_monad$bindS
+         (sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 12 : int):ii)]  :  1 words$word))) (\ (w__8 :  1 words$word) . 
+      let (trap : bool) = (w__8 = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS trap)) (\ (trap : bool) . 
+   if trap then AArch64_WFxTrap target_el is_wfe
+   else sail2_state_monad$returnS () ))))`;
+
+
+(*val aarch64_system_hints : SystemHintOp -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_hints:SystemHintOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op=
+    ((case op of
+     SystemHintOp_YIELD => sail2_state_monad$returnS ((Hint_Yield () ))
+   | SystemHintOp_WFE => sail2_state_monad$bindS
+      (IsEventRegisterSet () ) (\ (w__0 : bool) . 
+      if w__0 then ClearEventRegister () 
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (if (((w__1.ProcState_EL = EL0))) then AArch64_CheckForWFxTrap EL1 T
+         else sail2_state_monad$returnS () )
+        (sail2_state$and_boolS
+          (sail2_state$and_boolS
+             (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+                ( sail2_state_monad$bindS(IsSecure () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+             (sail2_state$or_boolS
+                ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+                 sail2_state_monad$returnS (((w__4.ProcState_EL = EL0)))))
+                ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+                 sail2_state_monad$returnS (((w__5.ProcState_EL = EL1)))))))
+          ( sail2_state_monad$bindS(IsInHost () ) (\ (w__8 : bool) .  sail2_state_monad$returnS ((~ w__8)))))) (\ (w__9 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (if w__9 then AArch64_CheckForWFxTrap EL2 T
+         else sail2_state_monad$returnS () )
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+           sail2_state_monad$returnS (((w__10.ProcState_EL <> EL3))))))) (\ (w__11 : bool) .  sail2_state_monad$seqS
+        (if w__11 then AArch64_CheckForWFxTrap EL3 T else sail2_state_monad$returnS () ) (WaitForEvent () )))))
+   | SystemHintOp_WFI => sail2_state_monad$bindS
+      (InterruptPending () ) (\ (w__12 : bool) . 
+      if ((~ w__12)) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (if (((w__13.ProcState_EL = EL0))) then AArch64_CheckForWFxTrap EL1 F
+         else sail2_state_monad$returnS () )
+        (sail2_state$and_boolS
+          (sail2_state$and_boolS
+             (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+                ( sail2_state_monad$bindS(IsSecure () ) (\ (w__14 : bool) .  sail2_state_monad$returnS ((~ w__14)))))
+             (sail2_state$or_boolS
+                ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . 
+                 sail2_state_monad$returnS (((w__16.ProcState_EL = EL0)))))
+                ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . 
+                 sail2_state_monad$returnS (((w__17.ProcState_EL = EL1)))))))
+          ( sail2_state_monad$bindS(IsInHost () ) (\ (w__20 : bool) .  sail2_state_monad$returnS ((~ w__20)))))) (\ (w__21 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (if w__21 then AArch64_CheckForWFxTrap EL2 F
+         else sail2_state_monad$returnS () )
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . 
+           sail2_state_monad$returnS (((w__22.ProcState_EL <> EL3))))))) (\ (w__23 : bool) .  sail2_state_monad$seqS
+        (if w__23 then AArch64_CheckForWFxTrap EL3 F else sail2_state_monad$returnS () ) (WaitForInterrupt () ))))
+      else sail2_state_monad$returnS () )
+   | SystemHintOp_SEV => SendEvent () 
+   | SystemHintOp_SEVL => SendEventLocal () 
+   | SystemHintOp_ESB =>
+      let (_ : unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in sail2_state_monad$bindS (sail2_state_monad$seqS
+      (AArch64_ESBOperation () )
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__24 : bool) .  sail2_state_monad$returnS ((~ w__24)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . 
+            sail2_state_monad$returnS (((w__26.ProcState_EL = EL0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__27 : ProcState) . 
+            sail2_state_monad$returnS (((w__27.ProcState_EL = EL1)))))))) (\ (w__29 : bool) .  sail2_state_monad$seqS
+      (if w__29 then AArch64_vESBOperation ()  else sail2_state_monad$returnS () ) (TakeUnmaskedSErrorInterrupts () ))
+   | SystemHintOp_PSB => sail2_state_monad$returnS ((ProfilingSynchronizationBarrier () ))
+   | _ => sail2_state_monad$returnS () 
+   )))`;
+
+
+(*val system_hints_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((system_hints_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (undefined_SystemHintOp () )) (\ (op : SystemHintOp) . 
+   let b__0 = ((concat_vec CRm op2  :  7 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) then
+      sail2_state_monad$returnS SystemHintOp_NOP
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) then
+      sail2_state_monad$returnS SystemHintOp_YIELD
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word)))) then
+      sail2_state_monad$returnS SystemHintOp_WFE
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word)))) then
+      sail2_state_monad$returnS SystemHintOp_WFI
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B0;B0]  :  7 words$word)))) then
+      sail2_state_monad$returnS SystemHintOp_SEV
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B0;B1]  :  7 words$word)))) then
+      sail2_state_monad$returnS SystemHintOp_SEVL
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1]  :  7 words$word)))) then sail2_state_monad$seqS
+      (sail2_state_monad$throwS (Error_See "XPACLRI")) (sail2_state_monad$returnS op)
+    else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 3 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)))) then sail2_state_monad$seqS
+      (sail2_state_monad$throwS (Error_See "PACIA1716, PACIB1716, AUTIA1716, AUTIB1716")) (sail2_state_monad$returnS op)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0]  :  7 words$word)))) then sail2_state_monad$seqS
+      (if ((~ ((HaveRASExt () )))) then EndOfInstruction () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS SystemHintOp_ESB)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B0;B0;B1]  :  7 words$word)))) then sail2_state_monad$seqS
+      (if ((~ ((HaveStatisticalProfiling () )))) then EndOfInstruction () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS SystemHintOp_PSB)
+    else sail2_state_monad$seqS
+      (if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 3 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+         sail2_state_monad$throwS (Error_See "PACIAZ, PACIASP, PACIBZ, PACIBSP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP")
+       else EndOfInstruction () )
+      (sail2_state_monad$returnS op)) (\ (op : SystemHintOp) . 
+   aarch64_system_hints op))))`;
+
+
+(*val AArch64_VectorCatchException : FaultRecord -> M unit*)
+
+val _ = Define `
+ ((AArch64_VectorCatchException:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL2))) "((PSTATE).EL != EL2)")
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))))) (\ (w__6 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__6 "((HaveEL(EL2) && !(IsSecure())) && (((HCR_EL2).TGE == '1') || ((MDCR_EL2).TDE == '1')))")
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (vaddress : 64 bits) .  sail2_state_monad$bindS
+   (AArch64_AbortSyndrome Exception_VectorCatch fault vaddress) (\ (exception : ExceptionRecord) . 
+   AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))`;
+
+
+(*val AArch64_UndefinedFault : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_UndefinedFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL0))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_Uncategorized) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+   if ((((lem$w2ui w__5.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+     AArch64_TakeException w__6.ProcState_EL exception preferred_exception_return vect_offset)
+   else if route_to_el2 then
+     AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))`;
+
+
+(*val AArch64_SystemRegisterTrap : mword ty2 -> mword ty2 -> mword ty3 -> mword ty3 -> mword ty4 -> mword ty5 -> mword ty4 -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((AArch64_SystemRegisterTrap:(2)words$word ->(2)words$word ->(3)words$word ->(3)words$word ->(4)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el op0 op2 op1 crn rt crm dir=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((lem$w2ui target_el)) >= ((lem$w2ui w__0.ProcState_EL)))) "(UInt(target_el) >= UInt((PSTATE).EL))")
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_SystemRegisterTrap) (\ (exception : ExceptionRecord) . 
+   let (tmp_2800 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2800 = ((set_slice (( 25 : int):ii) (( 2 : int):ii) tmp_2800 (( 20 : int):ii) op0  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2800|>)) in
+   let (tmp_2810 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2810 = ((set_slice (( 25 : int):ii) (( 3 : int):ii) tmp_2810 (( 17 : int):ii) op2  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2810|>)) in
+   let (tmp_2820 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2820 = ((set_slice (( 25 : int):ii) (( 3 : int):ii) tmp_2820 (( 14 : int):ii) op1  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2820|>)) in
+   let (tmp_2830 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2830 = ((set_slice (( 25 : int):ii) (( 4 : int):ii) tmp_2830 (( 10 : int):ii) crn  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2830|>)) in
+   let (tmp_2840 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2840 = ((set_slice (( 25 : int):ii) (( 5 : int):ii) tmp_2840 (( 5 : int):ii) rt  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2840|>)) in
+   let (tmp_2850 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2850 = ((set_slice (( 25 : int):ii) (( 4 : int):ii) tmp_2850 (( 1 : int):ii) crm  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2850|>)) in
+   let (tmp_2860 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2860 = ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2860 (( 0 : int):ii) dir  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2860|>)) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((((((target_el = EL1))) /\ ((HaveEL EL2))))))
+        ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__4 : bool) . 
+   if w__4 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException target_el exception preferred_exception_return vect_offset))))))`;
+
+
+(*val AArch64_SoftwareBreakpoint : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((AArch64_SoftwareBreakpoint:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . 
+            sail2_state_monad$returnS (((w__2.ProcState_EL = EL0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+            sail2_state_monad$returnS (((w__3.ProcState_EL = EL1)))))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_SoftwareBreakpoint) (\ (exception : ExceptionRecord) . 
+   let (tmp_2710 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2710 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2710 (( 0 : int):ii) immediate  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2710|>)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . 
+   if ((((lem$w2ui w__9.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . 
+     AArch64_TakeException w__10.ProcState_EL exception preferred_exception_return vect_offset)
+   else if route_to_el2 then
+     AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))`;
+
+
+(*val aarch64_system_exceptions_debug_breakpoint : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_exceptions_debug_breakpoint:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) comment=  (AArch64_SoftwareBreakpoint comment))`;
+
+
+(*val system_exceptions_debug_breakpoint_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((system_exceptions_debug_breakpoint_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (comment : 16 bits) = imm16 in
+   aarch64_system_exceptions_debug_breakpoint comment)))`;
+
+
+(*val AArch64_SPAlignmentFault : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_SPAlignmentFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_SPAlignment) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   if ((((lem$w2ui w__0.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     AArch64_TakeException w__1.ProcState_EL exception preferred_exception_return vect_offset)
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__5 : bool) . 
+     if w__5 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+     else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))`;
+
+
+(*val CheckSPAlignment : unit -> M unit*)
+
+val _ = Define `
+ ((CheckSPAlignment:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (sp : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (stack_align_check : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS
+   (if (((w__0.ProcState_EL = EL0))) then sail2_state_monad$bindS
+      (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+      let (stack_align_check : bool) =
+        ((vec_of_bits [access_vec_dec w__1 (( 4 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS stack_align_check)
+    else sail2_state_monad$bindS
+      (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+      let (stack_align_check : bool) =
+        ((vec_of_bits [access_vec_dec w__2 (( 3 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)) in
+      sail2_state_monad$returnS stack_align_check)) (\ (stack_align_check : bool) . 
+   if (((stack_align_check /\ (((sp <> ((Align__1 sp (( 16 : int):ii)  :  64 words$word)))))))) then
+     AArch64_SPAlignmentFault () 
+   else sail2_state_monad$returnS () ))))))`;
+
+
+(*val AArch64_InstructionAbort : mword ty64 -> FaultRecord -> M unit*)
+
+val _ = Define `
+ ((AArch64_InstructionAbort:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 3 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) ((IsExternalAbort__1 fault))) (\ (route_to_el3 :
+     bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__3 : bool) .  sail2_state_monad$returnS ((~ w__3)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+            sail2_state_monad$returnS (((w__5.ProcState_EL = EL0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+            sail2_state_monad$returnS (((w__6.ProcState_EL = EL1)))))))
+     (sail2_state$or_boolS
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))) ((IsSecondStage fault)))
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () )))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) ((IsExternalAbort__1 fault))))) (\ (route_to_el2 :
+     bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (AArch64_AbortSyndrome Exception_InstructionAbort fault vaddress) (\ (exception :
+     ExceptionRecord) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$returnS (((w__17.ProcState_EL = EL3)))))
+     (sail2_state_monad$returnS route_to_el3)) (\ (w__18 : bool) . 
+   if w__18 then AArch64_TakeException EL3 exception preferred_exception_return vect_offset
+   else sail2_state_monad$bindS
+     (sail2_state$or_boolS
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) .  sail2_state_monad$returnS (((w__19.ProcState_EL = EL2)))))
+       (sail2_state_monad$returnS route_to_el2)) (\ (w__20 : bool) . 
+     if w__20 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+     else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))`;
+
+
+(*val AArch64_DataAbort : mword ty64 -> FaultRecord -> M unit*)
+
+val _ = Define `
+ ((AArch64_DataAbort:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__0 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 3 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) ((IsExternalAbort__1 fault))) (\ (route_to_el3 :
+     bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__3 : bool) .  sail2_state_monad$returnS ((~ w__3)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+            sail2_state_monad$returnS (((w__5.ProcState_EL = EL0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+            sail2_state_monad$returnS (((w__6.ProcState_EL = EL1)))))))
+     (sail2_state$or_boolS
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))) ((IsSecondStage fault)))
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () )))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 37 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) ((IsExternalAbort__1 fault))))) (\ (route_to_el2 :
+     bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (AArch64_AbortSyndrome Exception_DataAbort fault vaddress) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$returnS (((w__17.ProcState_EL = EL3)))))
+     (sail2_state_monad$returnS route_to_el3)) (\ (w__18 : bool) . 
+   if w__18 then AArch64_TakeException EL3 exception preferred_exception_return vect_offset
+   else sail2_state_monad$bindS
+     (sail2_state$or_boolS
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) .  sail2_state_monad$returnS (((w__19.ProcState_EL = EL2)))))
+       (sail2_state_monad$returnS route_to_el2)) (\ (w__20 : bool) . 
+     if w__20 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+     else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))`;
+
+
+(*val AArch64_CheckForERetTrap : bool -> bool -> M unit*)
+
+val _ = Define `
+ ((AArch64_CheckForERetTrap:bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) eret_with_pac pac_uses_key_a=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL1))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (vect_offset : ii) . 
+   if route_to_el2 then sail2_state_monad$bindS
+     (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+     (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+     let vect_offset = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ExceptionSyndrome Exception_ERetTrap) (\ (w__5 : ExceptionRecord) . 
+     let exception = w__5 in
+     let (tmp_2550 : 25 bits) = (exception.ExceptionRecord_syndrome) in sail2_state_monad$bindS
+     (ZeroExtend__0 (vec_of_bits [B0]  :  1 words$word) ((make_the_value (( 23 : int):ii)  :  23 itself))
+       : ( 23 words$word) M) (\ (w__6 :  23 words$word) . 
+     let tmp_2550 = ((set_slice (( 25 : int):ii) (( 23 : int):ii) tmp_2550 (( 2 : int):ii) w__6  :  25 words$word)) in
+     let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2550|>)) in
+     let (exception : ExceptionRecord) =
+       (if ((~ eret_with_pac)) then
+         let (tmp_2560 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+         let (tmp_2560 : 25 bits) =
+           ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2560 (( 1 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  25 words$word)) in
+         let (exception : ExceptionRecord) = ((exception with<| ExceptionRecord_syndrome := tmp_2560|>)) in
+         let (tmp_2570 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+         let (tmp_2570 : 25 bits) =
+           ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2570 (( 0 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  25 words$word)) in
+         (exception with<| ExceptionRecord_syndrome := tmp_2570|>)
+       else
+         let (tmp_2580 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+         let (tmp_2580 : 25 bits) =
+           ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2580 (( 1 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  25 words$word)) in
+         let (exception : ExceptionRecord) = ((exception with<| ExceptionRecord_syndrome := tmp_2580|>)) in
+         if pac_uses_key_a then
+           let (tmp_2590 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+           let (tmp_2590 : 25 bits) =
+             ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2590 (( 0 : int):ii) (vec_of_bits [B0]  :  1 words$word)
+               :  25 words$word)) in
+           (exception with<| ExceptionRecord_syndrome := tmp_2590|>)
+         else
+           let (tmp_2600 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+           let (tmp_2600 : 25 bits) =
+             ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2600 (( 0 : int):ii) (vec_of_bits [B1]  :  1 words$word)
+               :  25 words$word)) in
+           (exception with<| ExceptionRecord_syndrome := tmp_2600|>)) in
+     AArch64_TakeException EL2 exception preferred_exception_return vect_offset))))
+   else sail2_state_monad$returnS () ))))`;
+
+
+(*val AArch64_CallSupervisor : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((AArch64_CallSupervisor:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate=  (sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if w__0 then AArch32_ITAdvance () 
+    else sail2_state_monad$returnS () )
+   (SSAdvance () ))
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$returnS (((w__3.ProcState_EL = EL0))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (NextInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_SupervisorCall) (\ (exception : ExceptionRecord) . 
+   let (tmp_2770 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2770 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2770 (( 0 : int):ii) immediate  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2770|>)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+   if ((((lem$w2ui w__6.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . 
+     AArch64_TakeException w__7.ProcState_EL exception preferred_exception_return vect_offset)
+   else if route_to_el2 then
+     AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException EL1 exception preferred_exception_return vect_offset)))))))`;
+
+
+(*val aarch64_system_exceptions_runtime_svc : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_exceptions_runtime_svc:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm=  (AArch64_CallSupervisor imm))`;
+
+
+(*val system_exceptions_runtime_svc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((system_exceptions_runtime_svc_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (imm : 16 bits) = imm16 in
+   aarch64_system_exceptions_runtime_svc imm)))`;
+
+
+(*val AArch64_CallSecureMonitor : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((AArch64_CallSecureMonitor:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3)))
+     ( sail2_state_monad$bindS(ELUsingAArch32 EL3) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__1 "(HaveEL(EL3) && !(ELUsingAArch32(EL3)))")
+   (UsingAArch32 () )) (\ (w__2 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if w__2 then AArch32_ITAdvance () 
+    else sail2_state_monad$returnS () )
+   (SSAdvance () ))
+   (NextInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_MonitorCall) (\ (exception : ExceptionRecord) . 
+   let (tmp_2930 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2930 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2930 (( 0 : int):ii) immediate  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2930|>)) in
+   AArch64_TakeException EL3 exception preferred_exception_return vect_offset))))))`;
+
+
+(*val AArch64_CallHypervisor : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((AArch64_CallHypervisor:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((HaveEL EL2)) "HaveEL(EL2)")
+   (UsingAArch32 () )) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if w__0 then AArch32_ITAdvance () 
+    else sail2_state_monad$returnS () )
+   (SSAdvance () ))
+   (NextInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_HypervisorCall) (\ (exception : ExceptionRecord) . 
+   let (tmp_2890 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+   let tmp_2890 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2890 (( 0 : int):ii) immediate  :  25 words$word)) in
+   let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2890|>)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+   if (((w__1.ProcState_EL = EL3))) then
+     AArch64_TakeException EL3 exception preferred_exception_return vect_offset
+   else AArch64_TakeException EL2 exception preferred_exception_return vect_offset))))))`;
+
+
+(*val AArch64_BreakpointException : FaultRecord -> M unit*)
+
+val _ = Define `
+ ((AArch64_BreakpointException:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL3))) "((PSTATE).EL != EL3)")
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+        (sail2_state$or_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+            sail2_state_monad$returnS (((w__3.ProcState_EL = EL0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+            sail2_state_monad$returnS (((w__4.ProcState_EL = EL1)))))))
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref  : ( 32 words$word) M) (\ (w__8 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 8 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (vaddress : 64 bits) .  sail2_state_monad$bindS
+   (AArch64_AbortSyndrome Exception_Breakpoint fault vaddress) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$returnS (((w__10.ProcState_EL = EL2)))))
+     (sail2_state_monad$returnS route_to_el2)) (\ (w__11 : bool) . 
+   if w__11 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset
+   else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))`;
+
+
+(*val AArch64_Abort : mword ty64 -> FaultRecord -> M unit*)
+
+val _ = Define `
+ ((AArch64_Abort:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault=  (sail2_state_monad$bindS
+   (IsDebugException fault) (\ (w__0 : bool) . 
+   if w__0 then
+     if (((fault.FaultRecord_acctype = AccType_IFETCH))) then sail2_state_monad$bindS
+       (sail2_state$and_boolS ((UsingAArch32 () ))
+         (sail2_state_monad$returnS (((fault.FaultRecord_debugmoe = DebugException_VectorCatch))))) (\ (w__2 :
+         bool) . 
+       if w__2 then AArch64_VectorCatchException fault
+       else AArch64_BreakpointException fault)
+     else AArch64_WatchpointException vaddress fault
+   else if (((fault.FaultRecord_acctype = AccType_IFETCH))) then
+     AArch64_InstructionAbort vaddress fault
+   else AArch64_DataAbort vaddress fault)))`;
+
+
+(*val AArch64_CheckAlignment : mword ty64 -> ii -> AccType -> bool -> M bool*)
+
+val _ = Define `
+ ((AArch64_CheckAlignment:(64)words$word -> int -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address alignment acctype iswrite=
+    (let (aligned : bool) = (address = ((Align__1 address alignment  :  64 words$word))) in
+   let (atomic : bool) = ((((acctype = AccType_ATOMIC))) \/ (((acctype = AccType_ATOMICRW)))) in
+   let (ordered : bool) =
+     ((((acctype = AccType_ORDERED))) \/ ((((((acctype = AccType_ORDEREDRW))) \/ (((acctype = AccType_LIMITEDORDERED))))))) in
+   let (vector_name : bool) = (acctype = AccType_VEC) in sail2_state_monad$bindS
+   (sail2_state$or_boolS (sail2_state_monad$returnS (((atomic \/ ordered))))
+     ( sail2_state_monad$bindS(aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (check' : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$seqS
+   (if (((check' /\ ((~ aligned))))) then
+      let secondstage = F in sail2_state_monad$bindS
+      (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__1 : FaultRecord) . 
+      AArch64_Abort address w__1)
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$returnS aligned)))))`;
+
+
+(*val AArch32_EnterMode : mword ty5 -> mword ty32 -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((AArch32_EnterMode:(5)words$word ->(32)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_mode preferred_exception_return lr_offset vect_offset=
+    (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS
+   (sail2_state$and_boolS ((ELUsingAArch32 EL1))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$returnS (((w__1.ProcState_EL <> EL2)))))) (\ (w__2 :
+     bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__2 "(ELUsingAArch32(EL1) && ((PSTATE).EL != EL2))")
+   (GetPSRFromPSTATE ()   : ( 32 words$word) M)) (\ (spsr : 32 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if (((w__3.ProcState_M = M32_Monitor))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+      sail2_state_monad$write_regS
+        SCR_ref
+        ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__4 (( 0 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)))
+    else sail2_state_monad$returnS () )
+   (AArch32_WriteMode target_mode))
+   (aset_SPSR spsr))
+   (aset_R (( 14 : int):ii) ((add_vec_int preferred_exception_return lr_offset  :  32 words$word))))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__5 with<| ProcState_T := ((vec_of_bits [access_vec_dec w__6 (( 30 : int):ii)]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_SS := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (if (((target_mode = M32_FIQ))) then
+      let split_vec = ((vec_of_bits [B1;B1;B1]  :  3 words$word)) in
+      let (tup__0, tup__1, tup__2) =
+        ((subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_A := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_I := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_F := tup__2|>))))
+    else if ((((((target_mode = M32_Abort))) \/ (((target_mode = M32_IRQ)))))) then
+      let split_vec = ((vec_of_bits [B1;B1]  :  2 words$word)) in
+      let (tup__0, tup__1) =
+        ((subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_A := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_I := tup__1|>)))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_I := ((vec_of_bits [B1]  :  1 words$word))|>))))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__14 with<| ProcState_E := ((vec_of_bits [access_vec_dec w__15 (( 25 : int):ii)]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_IL := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__17 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))|>))
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () )))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_ref  : ( 32 words$word) M) (\ (w__18 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 23 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__19 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__19 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_PAN := ((vec_of_bits [B1]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () )
+   (ExcVectorBase ()   : ( 32 words$word) M)) (\ (w__21 :  32 words$word) .  sail2_state_monad$seqS
+   (BranchTo
+     ((concat_vec ((slice w__21 (( 5 : int):ii) (( 27 : int):ii)  :  27 words$word))
+         ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) vect_offset (( 0 : int):ii)  :  5 words$word))
+        :  32 words$word)) BranchType_UNKNOWN)
+   (EndOfInstruction () )))))))))))))))`;
+
+
+(*val AArch64_AdvSIMDFPAccessTrap : mword ty2 -> M unit*)
+
+val _ = Define `
+ ((AArch64_AdvSIMDFPAccessTrap:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el=  (sail2_state_monad$bindS
+   (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+   let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((((((target_el = EL1))) /\ ((HaveEL EL2))))))
+        ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) . 
+   if route_to_el2 then sail2_state_monad$bindS
+     (ExceptionSyndrome Exception_Uncategorized) (\ (w__3 : ExceptionRecord) . 
+     let exception = w__3 in
+     AArch64_TakeException EL2 exception preferred_exception_return vect_offset)
+   else sail2_state_monad$bindS
+     (ExceptionSyndrome Exception_AdvSIMDFPAccessTrap) (\ (w__4 : ExceptionRecord) . 
+     let exception = w__4 in
+     let (tmp_2610 : 25 bits) = (exception.ExceptionRecord_syndrome) in sail2_state_monad$bindS
+     (ConditionSyndrome ()   : ( 5 words$word) M) (\ (w__5 :  5 words$word) . 
+     let tmp_2610 = ((set_slice (( 25 : int):ii) (( 5 : int):ii) tmp_2610 (( 20 : int):ii) w__5  :  25 words$word)) in
+     let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2610|>)) in
+     AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))`;
+
+
+(*val AArch64_CheckFPAdvSIMDTrap : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_CheckFPAdvSIMDTrap:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (disabled : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 :
+     bool) .  sail2_state_monad$seqS
+   (if w__1 then sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveVirtHostExt () )))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 34 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__3 : bool) . 
+      if w__3 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CPTR_EL2_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+        let p__283 = ((slice w__4 (( 20 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+        let v__94 = p__283 in sail2_state_monad$bindS
+        (if (((((subrange_vec_dec v__94 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$bindS
+           (sail2_state$and_boolS
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . 
+              sail2_state_monad$returnS (((w__5.ProcState_EL = EL1)))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__7 : bool) . 
+           let (disabled : bool) = (~ w__7) in
+           sail2_state_monad$returnS disabled)
+         else if (((v__94 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+           sail2_state$and_boolS
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . 
+              sail2_state_monad$returnS (((w__8.ProcState_EL = EL0)))))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__9 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+         else sail2_state_monad$returnS F) (\ (disabled : bool) . 
+        if disabled then AArch64_AdvSIMDFPAccessTrap EL2
+        else sail2_state_monad$returnS () ))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CPTR_EL2_ref  : ( 32 words$word) M) (\ (w__11 : 32 bits) . 
+        if ((((vec_of_bits [access_vec_dec w__11 (( 10 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+          AArch64_AdvSIMDFPAccessTrap EL2
+        else sail2_state_monad$returnS () ))
+    else sail2_state_monad$returnS () )
+   (if ((HaveEL EL3)) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CPTR_EL3_ref  : ( 32 words$word) M) (\ (w__12 : 32 bits) . 
+     if ((((vec_of_bits [access_vec_dec w__12 (( 10 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       AArch64_AdvSIMDFPAccessTrap EL3
+     else sail2_state_monad$returnS () )
+   else sail2_state_monad$returnS () )))))`;
+
+
+(*val AArch64_CheckFPAdvSIMDEnabled : unit -> M unit*)
+
+val _ = Define `
+ ((AArch64_CheckFPAdvSIMDEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (disabled : bool) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL0)))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$returnS (((w__1.ProcState_EL = EL1)))))) (\ (w__2 :
+     bool) .  sail2_state_monad$seqS
+   (if w__2 then sail2_state_monad$bindS
+      (aget_CPACR ()   : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
+      let p__282 = ((slice w__3 (( 20 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+      let v__96 = p__282 in sail2_state_monad$bindS
+      (if (((((subrange_vec_dec v__96 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) then
+         sail2_state_monad$returnS T
+       else if (((v__96 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . 
+         let (disabled : bool) = (w__4.ProcState_EL = EL0) in
+         sail2_state_monad$returnS disabled)
+       else sail2_state_monad$returnS F) (\ (disabled : bool) . 
+      if disabled then AArch64_AdvSIMDFPAccessTrap EL1
+      else sail2_state_monad$returnS () ))
+    else sail2_state_monad$returnS () )
+   (AArch64_CheckFPAdvSIMDTrap () )))))`;
+
+
+(*val CheckFPAdvSIMDEnabled64 : unit -> M unit*)
+
+val _ = Define `
+ ((CheckFPAdvSIMDEnabled64:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (AArch64_CheckFPAdvSIMDEnabled () ))`;
+
+
+(*val aarch64_float_move_fp_select : mword ty4 -> ii -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_move_fp_select:(4)words$word -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition d l__133 m n=
+    (if (((l__133 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (ConditionHolds condition)) (\ (w__0 : bool) .  sail2_state_monad$bindS
+     (if w__0 then (aget_V (( 8 : int):ii) n  : ( 8 words$word) M)
+      else (aget_V (( 8 : int):ii) m  : ( 8 words$word) M)) (\ (result : 8 bits) . 
+     aset_V d result))
+   else if (((l__133 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (ConditionHolds condition)) (\ (w__3 : bool) .  sail2_state_monad$bindS
+     (if w__3 then (aget_V (( 16 : int):ii) n  : ( 16 words$word) M)
+      else (aget_V (( 16 : int):ii) m  : ( 16 words$word) M)) (\ (result : 16 bits) . 
+     aset_V d result))
+   else if (((l__133 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (ConditionHolds condition)) (\ (w__6 : bool) .  sail2_state_monad$bindS
+     (if w__6 then (aget_V (( 32 : int):ii) n  : ( 32 words$word) M)
+      else (aget_V (( 32 : int):ii) m  : ( 32 words$word) M)) (\ (result : 32 bits) . 
+     aset_V d result))
+   else if (((l__133 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (ConditionHolds condition)) (\ (w__9 : bool) .  sail2_state_monad$bindS
+     (if w__9 then (aget_V (( 64 : int):ii) n  : ( 64 words$word) M)
+      else (aget_V (( 64 : int):ii) m  : ( 64 words$word) M)) (\ (result : 64 bits) . 
+     aset_V d result))
+   else if (((l__133 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (ConditionHolds condition)) (\ (w__12 : bool) .  sail2_state_monad$bindS
+     (if w__12 then (aget_V (( 128 : int):ii) n  : ( 128 words$word) M)
+      else (aget_V (( 128 : int):ii) m  : ( 128 words$word) M)) (\ (result : 128 bits) . 
+     aset_V d result))
+   else
+     let dbytes = (ex_int ((l__133 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_move_fp_imm : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_move_fp_imm:int -> 'datasize itself -> 'datasize words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d datasize imm=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint")) (CheckFPAdvSIMDEnabled64 () )) (aset_V d imm)))`;
+
+
+(*val aarch64_float_convert_int : forall 'fltsize 'intsize . Size 'fltsize, Size 'intsize => ii -> itself 'fltsize -> itself 'intsize -> ii -> FPConvOp -> ii -> FPRounding -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_convert_int:int -> 'fltsize itself -> 'intsize itself -> int -> FPConvOp -> int -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d fltsize intsize n op part rounding unsigned=
+    (let intsize = (size_itself_int intsize) in
+   let fltsize = (size_itself_int fltsize) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (CheckFPAdvSIMDEnabled64 () )
+   (undefined_bitvector fltsize  : ( 'fltsize words$word) M)) (\ (fltval : 'fltsize bits) .  sail2_state_monad$bindS
+   (undefined_bitvector intsize  : ( 'intsize words$word) M) (\ (intval : 'intsize bits) . 
+   (case op of
+     FPConvOp_CVT_FtoI => sail2_state_monad$bindS
+      (aget_V fltsize n  : ( 'fltsize words$word) M) (\ (w__0 : 'fltsize bits) . 
+      let fltval = w__0 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) .  sail2_state_monad$bindS
+      (FPToFixed intsize fltval (( 0 : int):ii) unsigned w__1 rounding  : ( 'intsize words$word) M) (\ (w__2 : 'intsize
+        bits) . 
+      let intval = w__2 in
+      aset_X d intval)))
+   | FPConvOp_CVT_ItoF => sail2_state_monad$bindS
+      (aget_X intsize n  : ( 'intsize words$word) M) (\ (w__3 : 'intsize bits) . 
+      let intval = w__3 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS
+      (FixedToFP fltsize intval (( 0 : int):ii) unsigned w__4 rounding  : ( 'fltsize words$word) M) (\ (w__5 : 'fltsize
+        bits) . 
+      let fltval = w__5 in
+      aset_V d fltval)))
+   | FPConvOp_MOV_FtoI => sail2_state_monad$bindS
+      (aget_Vpart fltsize n part  : ( 'fltsize words$word) M) (\ (w__6 : 'fltsize bits) . 
+      let fltval = w__6 in sail2_state_monad$bindS
+      (ZeroExtend__0 fltval ((make_the_value intsize  :  'intsize itself))  : ( 'intsize words$word) M) (\ (w__7 : 'intsize
+        bits) . 
+      let intval = w__7 in
+      aset_X d intval))
+   | FPConvOp_MOV_ItoF => sail2_state_monad$bindS
+      (aget_X intsize n  : ( 'intsize words$word) M) (\ (w__8 : 'intsize bits) . 
+      let intval = w__8 in
+      let fltval = ((slice intval (( 0 : int):ii) fltsize  :  'fltsize words$word)) in
+      aset_Vpart d part fltval)
+   | FPConvOp_CVT_FtoI_JS => sail2_state_monad$bindS
+      (aget_V fltsize n  : ( 'fltsize words$word) M) (\ (w__9 : 'fltsize bits) . 
+      let fltval = w__9 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__10 :  32 words$word) .  sail2_state_monad$bindS
+      (FPToFixedJS intsize fltval w__10 T  : ( 'intsize words$word) M) (\ (w__11 : 'intsize bits) . 
+      let intval = w__11 in sail2_state_monad$bindS
+      (ZeroExtend__0 ((slice intval (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word))
+         ((make_the_value (( 64 : int):ii)  :  64 itself))
+        : ( 64 words$word) M) (\ (w__12 :  64 words$word) . 
+      aset_X d w__12))))
+   )))))`;
+
+
+(*val aarch64_float_convert_fp : forall 'dstsize 'srcsize . Size 'dstsize, Size 'srcsize => ii -> itself 'dstsize -> ii -> itself 'srcsize -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_convert_fp:int -> 'dstsize itself -> int -> 'srcsize itself ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d dstsize n srcsize=
+    (let srcsize = (size_itself_int srcsize) in
+   let dstsize = (size_itself_int dstsize) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (CheckFPAdvSIMDEnabled64 () )
+   (undefined_bitvector dstsize  : ( 'dstsize words$word) M)) (\ (result : 'dstsize bits) .  sail2_state_monad$bindS
+   (aget_V srcsize n  : ( 'srcsize words$word) M) (\ (operand : 'srcsize bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) .  sail2_state_monad$bindS
+   (FPConvert__1 dstsize operand w__0  : ( 'dstsize words$word) M) (\ (w__1 : 'dstsize bits) . 
+   let result = w__1 in
+   aset_V d result))))))`;
+
+
+(*val aarch64_float_convert_fix : forall 'fltsize 'intsize . Size 'fltsize, Size 'intsize => ii -> itself 'fltsize -> ii -> itself 'intsize -> ii -> FPConvOp -> FPRounding -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_convert_fix:int -> 'fltsize itself -> int -> 'intsize itself -> int -> FPConvOp -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d fltsize fracbits intsize n op rounding unsigned=
+    (let intsize = (size_itself_int intsize) in
+   let fltsize = (size_itself_int fltsize) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (CheckFPAdvSIMDEnabled64 () )
+   (undefined_bitvector fltsize  : ( 'fltsize words$word) M)) (\ (fltval : 'fltsize bits) .  sail2_state_monad$bindS
+   (undefined_bitvector intsize  : ( 'intsize words$word) M) (\ (intval : 'intsize bits) . 
+   (case op of
+     FPConvOp_CVT_FtoI => sail2_state_monad$bindS
+      (aget_V fltsize n  : ( 'fltsize words$word) M) (\ (w__0 : 'fltsize bits) . 
+      let fltval = w__0 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) .  sail2_state_monad$bindS
+      (FPToFixed intsize fltval fracbits unsigned w__1 rounding  : ( 'intsize words$word) M) (\ (w__2 : 'intsize
+        bits) . 
+      let intval = w__2 in
+      aset_X d intval)))
+   | FPConvOp_CVT_ItoF => sail2_state_monad$bindS
+      (aget_X intsize n  : ( 'intsize words$word) M) (\ (w__3 : 'intsize bits) . 
+      let intval = w__3 in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS
+      (FixedToFP fltsize intval fracbits unsigned w__4 rounding  : ( 'fltsize words$word) M) (\ (w__5 : 'fltsize
+        bits) . 
+      let fltval = w__5 in
+      aset_V d fltval)))
+   )))))`;
+
+
+(*val aarch64_float_compare_uncond : bool -> ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_compare_uncond:bool -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cmp_with_zero l__128 m n signal_all_nans=
+    (if (((l__128 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (if cmp_with_zero then (FPZero (( 8 : int):ii) (vec_of_bits [B0]  :  1 words$word)  : ( 8 words$word) M)
+      else (aget_V (( 8 : int):ii) m  : ( 8 words$word) M)) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) .  sail2_state_monad$bindS
+     (FPCompare operand1 operand2 signal_all_nans w__2  : ( 4 words$word) M) (\ split_vec . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_V := tup__3|>)))))))))
+   else if (((l__128 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (if cmp_with_zero then (FPZero (( 16 : int):ii) (vec_of_bits [B0]  :  1 words$word)  : ( 16 words$word) M)
+      else (aget_V (( 16 : int):ii) m  : ( 16 words$word) M)) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__9 :  32 words$word) .  sail2_state_monad$bindS
+     (FPCompare operand1 operand2 signal_all_nans w__9  : ( 4 words$word) M) (\ split_vec . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_V := tup__3|>)))))))))
+   else if (((l__128 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (if cmp_with_zero then (FPZero (( 32 : int):ii) (vec_of_bits [B0]  :  1 words$word)  : ( 32 words$word) M)
+      else (aget_V (( 32 : int):ii) m  : ( 32 words$word) M)) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__16 :  32 words$word) .  sail2_state_monad$bindS
+     (FPCompare operand1 operand2 signal_all_nans w__16  : ( 4 words$word) M) (\ split_vec . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_V := tup__3|>)))))))))
+   else if (((l__128 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (if cmp_with_zero then (FPZero (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  : ( 64 words$word) M)
+      else (aget_V (( 64 : int):ii) m  : ( 64 words$word) M)) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__23 :  32 words$word) .  sail2_state_monad$bindS
+     (FPCompare operand1 operand2 signal_all_nans w__23  : ( 4 words$word) M) (\ split_vec . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__24 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_V := tup__3|>)))))))))
+   else if (((l__128 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (if cmp_with_zero then (FPZero (( 128 : int):ii) (vec_of_bits [B0]  :  1 words$word)  : ( 128 words$word) M)
+      else (aget_V (( 128 : int):ii) m  : ( 128 words$word) M)) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__30 :  32 words$word) .  sail2_state_monad$bindS
+     (FPCompare operand1 operand2 signal_all_nans w__30  : ( 4 words$word) M) (\ split_vec . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__31 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__31 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__32 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__32 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__33 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__33 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__34 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__34 with<| ProcState_V := tup__3|>)))))))))
+   else
+     let dbytes = (ex_int ((l__128 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_compare_cond : mword ty4 -> ii -> mword ty4 -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_compare_cond:(4)words$word -> int ->(4)words$word -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition l__123 flags__arg m n signal_all_nans=
+    (if (((l__123 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M)) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__0 : bool) .  sail2_state_monad$bindS
+     (if w__0 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+        (FPCompare operand1 operand2 signal_all_nans w__1  : ( 4 words$word) M))
+      else sail2_state_monad$returnS flags) (\ (flags :  4 words$word) . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__123 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M)) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__7 : bool) .  sail2_state_monad$bindS
+     (if w__7 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__8 :  32 words$word) . 
+        (FPCompare operand1 operand2 signal_all_nans w__8  : ( 4 words$word) M))
+      else sail2_state_monad$returnS flags) (\ (flags :  4 words$word) . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__123 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__14 : bool) .  sail2_state_monad$bindS
+     (if w__14 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__15 :  32 words$word) . 
+        (FPCompare operand1 operand2 signal_all_nans w__15  : ( 4 words$word) M))
+      else sail2_state_monad$returnS flags) (\ (flags :  4 words$word) . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__123 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__21 : bool) .  sail2_state_monad$bindS
+     (if w__21 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__22 :  32 words$word) . 
+        (FPCompare operand1 operand2 signal_all_nans w__22  : ( 4 words$word) M))
+      else sail2_state_monad$returnS flags) (\ (flags :  4 words$word) . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__24 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_V := tup__3|>))))))))))
+   else if (((l__123 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M)) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (ConditionHolds condition) (\ (w__28 : bool) .  sail2_state_monad$bindS
+     (if w__28 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__29 :  32 words$word) . 
+        (FPCompare operand1 operand2 signal_all_nans w__29  : ( 4 words$word) M))
+      else sail2_state_monad$returnS flags) (\ (flags :  4 words$word) . 
+     let (tup__0, tup__1, tup__2, tup__3) =
+       ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+        (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__31 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__31 with<| ProcState_N := tup__0|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__32 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__32 with<| ProcState_Z := tup__1|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__33 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS PSTATE_ref (w__33 with<| ProcState_C := tup__2|>))
+     (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__34 : ProcState) . 
+     sail2_state_monad$write_regS PSTATE_ref (w__34 with<| ProcState_V := tup__3|>))))))))))
+   else
+     let dbytes = (ex_int ((l__123 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_unary : ii -> ii -> FPUnaryOp -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_unary:int -> int -> FPUnaryOp -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__118 fpop n=
+    (if (((l__118 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand : 8 bits) .  sail2_state_monad$bindS
+     (case fpop of
+       FPUnaryOp_MOV => sail2_state_monad$returnS operand
+     | FPUnaryOp_ABS => (FPAbs operand  : ( 8 words$word) M)
+     | FPUnaryOp_NEG => (FPNeg operand  : ( 8 words$word) M)
+     | FPUnaryOp_SQRT => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+        (FPSqrt operand w__2  : ( 8 words$word) M))
+     ) (\ (result : 8 bits) . 
+     aset_V d result)))
+   else if (((l__118 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand : 16 bits) .  sail2_state_monad$bindS
+     (case fpop of
+       FPUnaryOp_MOV => sail2_state_monad$returnS operand
+     | FPUnaryOp_ABS => (FPAbs operand  : ( 16 words$word) M)
+     | FPUnaryOp_NEG => (FPNeg operand  : ( 16 words$word) M)
+     | FPUnaryOp_SQRT => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) . 
+        (FPSqrt operand w__6  : ( 16 words$word) M))
+     ) (\ (result : 16 bits) . 
+     aset_V d result)))
+   else if (((l__118 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand : 32 bits) .  sail2_state_monad$bindS
+     (case fpop of
+       FPUnaryOp_MOV => sail2_state_monad$returnS operand
+     | FPUnaryOp_ABS => (FPAbs operand  : ( 32 words$word) M)
+     | FPUnaryOp_NEG => (FPNeg operand  : ( 32 words$word) M)
+     | FPUnaryOp_SQRT => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__10 :  32 words$word) . 
+        (FPSqrt operand w__10  : ( 32 words$word) M))
+     ) (\ (result : 32 bits) . 
+     aset_V d result)))
+   else if (((l__118 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand : 64 bits) .  sail2_state_monad$bindS
+     (case fpop of
+       FPUnaryOp_MOV => sail2_state_monad$returnS operand
+     | FPUnaryOp_ABS => (FPAbs operand  : ( 64 words$word) M)
+     | FPUnaryOp_NEG => (FPNeg operand  : ( 64 words$word) M)
+     | FPUnaryOp_SQRT => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__14 :  32 words$word) . 
+        (FPSqrt operand w__14  : ( 64 words$word) M))
+     ) (\ (result : 64 bits) . 
+     aset_V d result)))
+   else if (((l__118 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand : 128 bits) .  sail2_state_monad$bindS
+     (case fpop of
+       FPUnaryOp_MOV => sail2_state_monad$returnS operand
+     | FPUnaryOp_ABS => (FPAbs operand  : ( 128 words$word) M)
+     | FPUnaryOp_NEG => (FPNeg operand  : ( 128 words$word) M)
+     | FPUnaryOp_SQRT => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__18 :  32 words$word) . 
+        (FPSqrt operand w__18  : ( 128 words$word) M))
+     ) (\ (result : 128 bits) . 
+     aset_V d result)))
+   else
+     let dbytes = (ex_int ((l__118 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_round : ii -> ii -> bool -> ii -> FPRounding -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_round:int -> int -> bool -> int -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__113 exact n rounding=
+    (if (((l__113 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand : 8 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) .  sail2_state_monad$bindS
+     (FPRoundInt operand w__0 rounding exact  : ( 8 words$word) M) (\ (w__1 : 8 bits) . 
+     let result = w__1 in
+     aset_V d result))))
+   else if (((l__113 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand : 16 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) .  sail2_state_monad$bindS
+     (FPRoundInt operand w__2 rounding exact  : ( 16 words$word) M) (\ (w__3 : 16 bits) . 
+     let result = w__3 in
+     aset_V d result))))
+   else if (((l__113 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand : 32 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS
+     (FPRoundInt operand w__4 rounding exact  : ( 32 words$word) M) (\ (w__5 : 32 bits) . 
+     let result = w__5 in
+     aset_V d result))))
+   else if (((l__113 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  sail2_state_monad$bindS
+     (FPRoundInt operand w__6 rounding exact  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+     let result = w__7 in
+     aset_V d result))))
+   else if (((l__113 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand : 128 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__8 :  32 words$word) .  sail2_state_monad$bindS
+     (FPRoundInt operand w__8 rounding exact  : ( 128 words$word) M) (\ (w__9 : 128 bits) . 
+     let result = w__9 in
+     aset_V d result))))
+   else
+     let dbytes = (ex_int ((l__113 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_mul_product : ii -> ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_mul_product:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__108 m n negated=
+    (if (((l__108 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMul operand1 operand2 w__0  : ( 8 words$word) M) (\ (w__1 : 8 bits) . 
+     let result = w__1 in sail2_state_monad$bindS
+     (if negated then (FPNeg result  : ( 8 words$word) M)
+      else sail2_state_monad$returnS result) (\ (result : 8 bits) . 
+     aset_V d result))))))
+   else if (((l__108 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__3 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMul operand1 operand2 w__3  : ( 16 words$word) M) (\ (w__4 : 16 bits) . 
+     let result = w__4 in sail2_state_monad$bindS
+     (if negated then (FPNeg result  : ( 16 words$word) M)
+      else sail2_state_monad$returnS result) (\ (result : 16 bits) . 
+     aset_V d result))))))
+   else if (((l__108 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMul operand1 operand2 w__6  : ( 32 words$word) M) (\ (w__7 : 32 bits) . 
+     let result = w__7 in sail2_state_monad$bindS
+     (if negated then (FPNeg result  : ( 32 words$word) M)
+      else sail2_state_monad$returnS result) (\ (result : 32 bits) . 
+     aset_V d result))))))
+   else if (((l__108 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__9 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMul operand1 operand2 w__9  : ( 64 words$word) M) (\ (w__10 : 64 bits) . 
+     let result = w__10 in sail2_state_monad$bindS
+     (if negated then (FPNeg result  : ( 64 words$word) M)
+      else sail2_state_monad$returnS result) (\ (result : 64 bits) . 
+     aset_V d result))))))
+   else if (((l__108 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__12 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMul operand1 operand2 w__12  : ( 128 words$word) M) (\ (w__13 : 128 bits) . 
+     let result = w__13 in sail2_state_monad$bindS
+     (if negated then (FPNeg result  : ( 128 words$word) M)
+      else sail2_state_monad$returnS result) (\ (result : 128 bits) . 
+     aset_V d result))))))
+   else
+     let dbytes = (ex_int ((l__108 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_mul_addsub : ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_mul_addsub:int -> int -> int -> int -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) a d l__103 m n op1_neg opa_neg=
+    (if (((l__103 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) a  : ( 8 words$word) M) (\ (operanda : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (if opa_neg then (FPNeg operanda  : ( 8 words$word) M)
+      else sail2_state_monad$returnS operanda) (\ (operanda : 8 bits) .  sail2_state_monad$bindS
+     (if op1_neg then (FPNeg operand1  : ( 8 words$word) M)
+      else sail2_state_monad$returnS operand1) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMulAdd operanda operand1 operand2 w__2  : ( 8 words$word) M) (\ (w__3 : 8 bits) . 
+     let result = w__3 in
+     aset_V d result))))))))
+   else if (((l__103 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) a  : ( 16 words$word) M) (\ (operanda : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (if opa_neg then (FPNeg operanda  : ( 16 words$word) M)
+      else sail2_state_monad$returnS operanda) (\ (operanda : 16 bits) .  sail2_state_monad$bindS
+     (if op1_neg then (FPNeg operand1  : ( 16 words$word) M)
+      else sail2_state_monad$returnS operand1) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMulAdd operanda operand1 operand2 w__6  : ( 16 words$word) M) (\ (w__7 : 16 bits) . 
+     let result = w__7 in
+     aset_V d result))))))))
+   else if (((l__103 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) a  : ( 32 words$word) M) (\ (operanda : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (if opa_neg then (FPNeg operanda  : ( 32 words$word) M)
+      else sail2_state_monad$returnS operanda) (\ (operanda : 32 bits) .  sail2_state_monad$bindS
+     (if op1_neg then (FPNeg operand1  : ( 32 words$word) M)
+      else sail2_state_monad$returnS operand1) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__10 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMulAdd operanda operand1 operand2 w__10  : ( 32 words$word) M) (\ (w__11 : 32 bits) . 
+     let result = w__11 in
+     aset_V d result))))))))
+   else if (((l__103 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) a  : ( 64 words$word) M) (\ (operanda : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (if opa_neg then (FPNeg operanda  : ( 64 words$word) M)
+      else sail2_state_monad$returnS operanda) (\ (operanda : 64 bits) .  sail2_state_monad$bindS
+     (if op1_neg then (FPNeg operand1  : ( 64 words$word) M)
+      else sail2_state_monad$returnS operand1) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__14 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMulAdd operanda operand1 operand2 w__14  : ( 64 words$word) M) (\ (w__15 : 64 bits) . 
+     let result = w__15 in
+     aset_V d result))))))))
+   else if (((l__103 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) a  : ( 128 words$word) M) (\ (operanda : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (if opa_neg then (FPNeg operanda  : ( 128 words$word) M)
+      else sail2_state_monad$returnS operanda) (\ (operanda : 128 bits) .  sail2_state_monad$bindS
+     (if op1_neg then (FPNeg operand1  : ( 128 words$word) M)
+      else sail2_state_monad$returnS operand1) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__18 :  32 words$word) .  sail2_state_monad$bindS
+     (FPMulAdd operanda operand1 operand2 w__18  : ( 128 words$word) M) (\ (w__19 : 128 bits) . 
+     let result = w__19 in
+     aset_V d result))))))))
+   else
+     let dbytes = (ex_int ((l__103 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_maxmin : ii -> ii -> ii -> ii -> FPMaxMinOp -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_maxmin:int -> int -> int -> int -> FPMaxMinOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__98 m n operation=
+    (if (((l__98 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (case operation of
+       FPMaxMinOp_MAX => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+        (FPMax operand1 operand2 w__0  : ( 8 words$word) M))
+     | FPMaxMinOp_MIN => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+        (FPMin operand1 operand2 w__2  : ( 8 words$word) M))
+     | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+        (FPMaxNum operand1 operand2 w__4  : ( 8 words$word) M))
+     | FPMaxMinOp_MINNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) . 
+        (FPMinNum operand1 operand2 w__6  : ( 8 words$word) M))
+     ) (\ (result : 8 bits) . 
+     aset_V d result))))
+   else if (((l__98 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (case operation of
+       FPMaxMinOp_MAX => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__8 :  32 words$word) . 
+        (FPMax operand1 operand2 w__8  : ( 16 words$word) M))
+     | FPMaxMinOp_MIN => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__10 :  32 words$word) . 
+        (FPMin operand1 operand2 w__10  : ( 16 words$word) M))
+     | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__12 :  32 words$word) . 
+        (FPMaxNum operand1 operand2 w__12  : ( 16 words$word) M))
+     | FPMaxMinOp_MINNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__14 :  32 words$word) . 
+        (FPMinNum operand1 operand2 w__14  : ( 16 words$word) M))
+     ) (\ (result : 16 bits) . 
+     aset_V d result))))
+   else if (((l__98 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (case operation of
+       FPMaxMinOp_MAX => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__16 :  32 words$word) . 
+        (FPMax operand1 operand2 w__16  : ( 32 words$word) M))
+     | FPMaxMinOp_MIN => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__18 :  32 words$word) . 
+        (FPMin operand1 operand2 w__18  : ( 32 words$word) M))
+     | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__20 :  32 words$word) . 
+        (FPMaxNum operand1 operand2 w__20  : ( 32 words$word) M))
+     | FPMaxMinOp_MINNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__22 :  32 words$word) . 
+        (FPMinNum operand1 operand2 w__22  : ( 32 words$word) M))
+     ) (\ (result : 32 bits) . 
+     aset_V d result))))
+   else if (((l__98 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (case operation of
+       FPMaxMinOp_MAX => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__24 :  32 words$word) . 
+        (FPMax operand1 operand2 w__24  : ( 64 words$word) M))
+     | FPMaxMinOp_MIN => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__26 :  32 words$word) . 
+        (FPMin operand1 operand2 w__26  : ( 64 words$word) M))
+     | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__28 :  32 words$word) . 
+        (FPMaxNum operand1 operand2 w__28  : ( 64 words$word) M))
+     | FPMaxMinOp_MINNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__30 :  32 words$word) . 
+        (FPMinNum operand1 operand2 w__30  : ( 64 words$word) M))
+     ) (\ (result : 64 bits) . 
+     aset_V d result))))
+   else if (((l__98 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (case operation of
+       FPMaxMinOp_MAX => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__32 :  32 words$word) . 
+        (FPMax operand1 operand2 w__32  : ( 128 words$word) M))
+     | FPMaxMinOp_MIN => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__34 :  32 words$word) . 
+        (FPMin operand1 operand2 w__34  : ( 128 words$word) M))
+     | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__36 :  32 words$word) . 
+        (FPMaxNum operand1 operand2 w__36  : ( 128 words$word) M))
+     | FPMaxMinOp_MINNUM => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__38 :  32 words$word) . 
+        (FPMinNum operand1 operand2 w__38  : ( 128 words$word) M))
+     ) (\ (result : 128 bits) . 
+     aset_V d result))))
+   else
+     let dbytes = (ex_int ((l__98 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_div : ii -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_div:int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__93 m n=
+    (if (((l__93 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) .  sail2_state_monad$bindS
+     (FPDiv operand1 operand2 w__0  : ( 8 words$word) M) (\ (w__1 : 8 bits) . 
+     let result = w__1 in
+     aset_V d result)))))
+   else if (((l__93 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) .  sail2_state_monad$bindS
+     (FPDiv operand1 operand2 w__2  : ( 16 words$word) M) (\ (w__3 : 16 bits) . 
+     let result = w__3 in
+     aset_V d result)))))
+   else if (((l__93 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS
+     (FPDiv operand1 operand2 w__4  : ( 32 words$word) M) (\ (w__5 : 32 bits) . 
+     let result = w__5 in
+     aset_V d result)))))
+   else if (((l__93 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  sail2_state_monad$bindS
+     (FPDiv operand1 operand2 w__6  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+     let result = w__7 in
+     aset_V d result)))))
+   else if (((l__93 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__8 :  32 words$word) .  sail2_state_monad$bindS
+     (FPDiv operand1 operand2 w__8  : ( 128 words$word) M) (\ (w__9 : 128 bits) . 
+     let result = w__9 in
+     aset_V d result)))))
+   else
+     let dbytes = (ex_int ((l__93 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_float_arithmetic_addsub : ii -> ii -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_arithmetic_addsub:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__88 m n sub_op=
+    (if (((l__88 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) n  : ( 8 words$word) M) (\ (operand1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_V (( 8 : int):ii) m  : ( 8 words$word) M) (\ (operand2 : 8 bits) .  sail2_state_monad$bindS
+     (if sub_op then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+        (FPSub operand1 operand2 w__0  : ( 8 words$word) M))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+        (FPAdd operand1 operand2 w__2  : ( 8 words$word) M))) (\ (result : 8 bits) . 
+     aset_V d result))))
+   else if (((l__88 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) n  : ( 16 words$word) M) (\ (operand1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_V (( 16 : int):ii) m  : ( 16 words$word) M) (\ (operand2 : 16 bits) .  sail2_state_monad$bindS
+     (if sub_op then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+        (FPSub operand1 operand2 w__4  : ( 16 words$word) M))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) . 
+        (FPAdd operand1 operand2 w__6  : ( 16 words$word) M))) (\ (result : 16 bits) . 
+     aset_V d result))))
+   else if (((l__88 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) n  : ( 32 words$word) M) (\ (operand1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_V (( 32 : int):ii) m  : ( 32 words$word) M) (\ (operand2 : 32 bits) .  sail2_state_monad$bindS
+     (if sub_op then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__8 :  32 words$word) . 
+        (FPSub operand1 operand2 w__8  : ( 32 words$word) M))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__10 :  32 words$word) . 
+        (FPAdd operand1 operand2 w__10  : ( 32 words$word) M))) (\ (result : 32 bits) . 
+     aset_V d result))))
+   else if (((l__88 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) n  : ( 64 words$word) M) (\ (operand1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_V (( 64 : int):ii) m  : ( 64 words$word) M) (\ (operand2 : 64 bits) .  sail2_state_monad$bindS
+     (if sub_op then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__12 :  32 words$word) . 
+        (FPSub operand1 operand2 w__12  : ( 64 words$word) M))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__14 :  32 words$word) . 
+        (FPAdd operand1 operand2 w__14  : ( 64 words$word) M))) (\ (result : 64 bits) . 
+     aset_V d result))))
+   else if (((l__88 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) n  : ( 128 words$word) M) (\ (operand1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_V (( 128 : int):ii) m  : ( 128 words$word) M) (\ (operand2 : 128 bits) .  sail2_state_monad$bindS
+     (if sub_op then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__16 :  32 words$word) . 
+        (FPSub operand1 operand2 w__16  : ( 128 words$word) M))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__18 :  32 words$word) . 
+        (FPAdd operand1 operand2 w__18  : ( 128 words$word) M))) (\ (result : 128 bits) . 
+     aset_V d result))))
+   else
+     let dbytes = (ex_int ((l__88 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val AArch64_AccessIsPrivileged : AccType -> M bool*)
+
+val _ = Define `
+ ((AArch64_AccessIsPrivileged:AccType ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (ispriv : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . 
+   if (((w__0.ProcState_EL = EL0))) then sail2_state_monad$returnS F
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . 
+     if (((w__1.ProcState_EL = EL3))) then sail2_state_monad$returnS T
+     else sail2_state_monad$bindS
+       (sail2_state$and_boolS
+         ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL2)))))
+         (sail2_state$or_boolS ( sail2_state_monad$bindS(IsInHost () ) (\ (w__3 : bool) .  sail2_state_monad$returnS ((~ w__3))))
+            ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+             sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__6 : bool) . 
+       if w__6 then sail2_state_monad$returnS T
+       else sail2_state_monad$bindS
+         (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveUAOExt () )))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . 
+            sail2_state_monad$returnS (((w__7.ProcState_UAO = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__8 :
+           bool) . 
+         let (ispriv : bool) = (if w__8 then T else (acctype <> AccType_UNPRIV)) in
+         sail2_state_monad$returnS ispriv)))))))`;
+
+
+(*val AArch64_CheckWatchpoint : mword ty64 -> AccType -> bool -> ii -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_CheckWatchpoint:(64)words$word -> AccType -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite size1=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))")
+   (let (val_match : bool) = F in sail2_state_monad$bindS
+   (AArch64_AccessIsPrivileged acctype) (\ (ispriv : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) ((lem$w2ui ((slice w__2 (( 20 : int):ii) (( 4 : int):ii)  :  4 words$word)))) (( 1 : int):ii)) val_match
+     (\ i val_match . 
+       sail2_state$or_boolS (sail2_state_monad$returnS val_match) ((AArch64_WatchpointMatch i vaddress size1 ispriv iswrite)))) (\ (val_match :
+     bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (reason : 6 bits) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS val_match) ((HaltOnBreakpointOrWatchpoint () ))) (\ (w__6 : bool) . 
+   if w__6 then
+     let reason = DebugHalt_Watchpoint in sail2_state_monad$seqS
+     (Halt reason) (undefined_FaultRecord () )
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS val_match)
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref  : ( 32 words$word) M) (\ (w__8 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 15 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) ((AArch64_GenerateDebugExceptions () ))) (\ (w__11 :
+       bool) . 
+     if w__11 then AArch64_DebugFault acctype iswrite
+     else AArch64_NoFault () )))))))))))`;
+
+
+(*val AArch64_CheckDebug : mword ty64 -> AccType -> bool -> ii -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_CheckDebug:(64)words$word -> AccType -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite size1=  (sail2_state_monad$bindS
+   (AArch64_NoFault () ) (\ (fault : FaultRecord) . 
+   let (d_side : bool) = (acctype <> AccType_IFETCH) in sail2_state_monad$bindS
+   (sail2_state$and_boolS ((AArch64_GenerateDebugExceptions () ))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 15 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (generate_exception : bool) .  sail2_state_monad$bindS
+   (HaltOnBreakpointOrWatchpoint () ) (\ (halt : bool) . 
+   if (((generate_exception \/ halt))) then
+     if d_side then AArch64_CheckWatchpoint vaddress acctype iswrite size1
+     else AArch64_CheckBreakpoint vaddress size1
+   else sail2_state_monad$returnS fault)))))`;
+
+
+(*val AArch64_CheckPermission : Permissions -> mword ty64 -> ii -> mword ty1 -> AccType -> bool -> M FaultRecord*)
+
+val _ = Define `
+ ((AArch64_CheckPermission:Permissions ->(64)words$word -> int ->(1)words$word -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) perms vaddress level NS acctype iswrite=  (sail2_state_monad$bindS
+   (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__0 :  2 words$word) .  sail2_state_monad$bindS
+   (ELUsingAArch32 w__0) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))")
+   (aget_SCTLR__1 ()   : ( 32 words$word) M)) (\ (w__2 :  32 words$word) . 
+   let (wxn : bool) =
+     ((vec_of_bits [access_vec_dec w__2 (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (xn : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (r : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (priv_xn : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (user_xn : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (pan : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (ispriv : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (user_w : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (user_r : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (priv_w : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (priv_r : bool) .  sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     (sail2_state$or_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$returnS (((w__3.ProcState_EL = EL0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$returnS (((w__4.ProcState_EL = EL1))))))
+     ((IsInHost () ))) (\ (w__7 : bool) .  sail2_state_monad$bindS
+   (if w__7 then
+      let priv_r = T in
+      let priv_w =
+        ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 2 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)) in
+      let user_r =
+        ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+      let user_w =
+        (((slice perms.Permissions_ap (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)) in sail2_state_monad$bindS
+      (AArch64_AccessIsPrivileged acctype) (\ (w__8 : bool) . 
+      let ispriv = w__8 in sail2_state_monad$bindS
+      (if ((HavePANExt () )) then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) .  sail2_state_monad$returnS w__9.ProcState_PAN)
+       else sail2_state_monad$returnS (vec_of_bits [B0]  :  1 words$word)) (\ (w__10 :  1 words$word) . 
+      let pan = w__10 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS
+              (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+                 ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__11 : 64 bits) . 
+                  sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+              ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__13 : 64 bits) . 
+               sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__15 : bool) .  sail2_state_monad$returnS ((~ w__15)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$returnS (((w__17.ProcState_EL = EL1)))))) (\ (w__18 :
+        bool) . 
+      let (pan : 1 bits) = (if w__18 then (vec_of_bits [B0]  :  1 words$word) else pan) in sail2_state_monad$bindS
+      (sail2_state$or_boolS
+        (sail2_state_monad$returnS ((((((((((((pan = (vec_of_bits [B1]  :  1 words$word)))) /\ user_r))) /\ ispriv))) /\ ((~ ((((((acctype = AccType_DC))) \/ ((((((acctype = AccType_AT))) \/ (((acctype = AccType_IFETCH)))))))))))))))
+        (sail2_state$and_boolS (sail2_state_monad$returnS (((acctype = AccType_AT)))) ((AArch64_ExecutingATS1xPInstr () )))) (\ (w__21 :
+        bool) . 
+      let ((priv_r : bool), (priv_w : bool)) =
+        (if w__21 then
+          let (priv_r : bool) = F in
+          let (priv_w : bool) = F in
+          (priv_r, priv_w)
+        else (priv_r, priv_w)) in
+      let (user_xn : bool) =
+        ((((perms.Permissions_xn = (vec_of_bits [B1]  :  1 words$word)))) \/ (((user_w /\ wxn)))) in
+      let (priv_xn : bool) =
+        (((((((perms.Permissions_pxn = (vec_of_bits [B1]  :  1 words$word)))) \/ (((priv_w /\ wxn)))))) \/ user_w) in
+      let ((r : bool), (w : bool), (xn : bool)) =
+        (if ispriv then
+          let (tup__0, tup__1, tup__2) = (priv_r, priv_w, priv_xn) in
+          let (r : bool) = tup__0 in
+          let (w : bool) = tup__1 in
+          let (xn : bool) = tup__2 in
+          (r, w, xn)
+        else
+          let (tup__0, tup__1, tup__2) = (user_r, user_w, user_xn) in
+          let (r : bool) = tup__0 in
+          let (w : bool) = tup__1 in
+          let (xn : bool) = tup__2 in
+          (r, w, xn)) in
+      sail2_state_monad$returnS (r, w, xn)))))
+    else
+      let (r : bool) = T in
+      let (w : bool) =
+        ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 2 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)) in
+      let (xn : bool) =
+        ((((perms.Permissions_xn = (vec_of_bits [B1]  :  1 words$word)))) \/ (((w /\ wxn)))) in
+      sail2_state_monad$returnS (r, w, xn)) (\ varstup .  let ((r : bool), (w : bool), (xn : bool)) = varstup in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) ((IsSecure () )))
+        (sail2_state_monad$returnS (((NS = (vec_of_bits [B1]  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__25 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__25 (( 9 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__26 : bool) . 
+   let (xn : bool) = (if w__26 then T else xn) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (failedread : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (fail1 : bool) . 
+   let ((fail1 : bool), (failedread : bool)) =
+     (if (((acctype = AccType_IFETCH))) then
+       let (fail1 : bool) = xn in
+       let (failedread : bool) = T in
+       (fail1, failedread)
+     else
+       let ((fail1 : bool), (failedread : bool)) =
+         (if ((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW)))))) then
+           let (fail1 : bool) = (((~ r)) \/ ((~ w))) in
+           let (failedread : bool) = (~ r) in
+           (fail1, failedread)
+         else
+           let ((fail1 : bool), (failedread : bool)) =
+             (if iswrite then
+               let (fail1 : bool) = (~ w) in
+               let (failedread : bool) = F in
+               (fail1, failedread)
+             else
+               let (fail1 : bool) = (~ r) in
+               let (failedread : bool) = T in
+               (fail1, failedread)) in
+           (fail1, failedread)) in
+       (fail1, failedread)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . 
+   if fail1 then
+     let secondstage = F in
+     let s2fs1walk = F in sail2_state_monad$bindS
+     (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (w__27 : 52 bits) . 
+     let ipaddress = w__27 in
+     AArch64_PermissionFault ipaddress level acctype ((~ failedread)) secondstage s2fs1walk)
+   else AArch64_NoFault () ))))))))))))))))))))))))`;
+
+
+(*val AArch64_FirstStageTranslate : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*)
+
+val _ = Define `
+ ((AArch64_FirstStageTranslate:(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite wasaligned size1=  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (s1_enabled : bool) .  sail2_state_monad$bindS
+   (HasS2Translation () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (if w__0 then
+      sail2_state$and_boolS
+        (sail2_state$and_boolS
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 12 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+    else sail2_state_monad$bindS
+      (aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__6 :  32 words$word) . 
+      let (s1_enabled : bool) =
+        ((vec_of_bits [access_vec_dec w__6 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+      sail2_state_monad$returnS s1_enabled)) (\ (s1_enabled : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M) (\ (ipaddress : 52 bits) . 
+   let (secondstage : bool) = F in
+   let (s2fs1walk : bool) = F in sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (nTLSMD : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (permissioncheck : bool) .  sail2_state_monad$bindS
+   (undefined_TLBRecord () ) (\ (S1 : TLBRecord) .  sail2_state_monad$bindS
+   (if s1_enabled then sail2_state_monad$bindS
+      (AArch64_TranslationTableWalk ipaddress vaddress acctype iswrite secondstage s2fs1walk size1) (\ (w__7 :
+        TLBRecord) . 
+      let (S1 : TLBRecord) = w__7 in
+      let (permissioncheck : bool) = T in
+      sail2_state_monad$returnS (S1, permissioncheck))
+    else sail2_state_monad$bindS
+      (AArch64_TranslateAddressS1Off vaddress acctype iswrite) (\ (w__8 : TLBRecord) . 
+      let S1 = w__8 in
+      let permissioncheck = F in sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state$and_boolS ((UsingAArch32 () )) (sail2_state_monad$returnS ((HaveTrapLoadStoreMultipleDeviceExt () ))))
+        ((AArch32_ExecutingLSMInstr () ))) (\ (w__12 : bool) .  sail2_state_monad$bindS
+      (if w__12 then
+         if ((((((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device))) /\ (((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_device <> DeviceType_GRE)))))) then sail2_state_monad$bindS
+           (S1TranslationRegime__1 ()   : ( 2 words$word) M) (\ (w__13 :  2 words$word) .  sail2_state_monad$bindS
+           (if (((w__13 = EL2))) then sail2_state_monad$bindS
+              (sail2_state_monad$read_regS SCTLR_EL2_ref  : ( 32 words$word) M) (\ (w__14 : 32 bits) . 
+              sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__14 (( 28 : int):ii)]  :  1 words$word))
+            else sail2_state_monad$bindS
+              (sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__15 : 32 bits) . 
+              sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__15 (( 28 : int):ii)]  :  1 words$word))) (\ (w__16 :
+              1 words$word) . 
+           let nTLSMD = w__16 in
+           if (((nTLSMD = (vec_of_bits [B0]  :  1 words$word)))) then
+             let (tmp_2460 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS
+             (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__17 : FaultRecord) . 
+             let (tmp_2460 : AddressDescriptor) =
+               ((tmp_2460 with<| AddressDescriptor_fault := w__17|>)) in
+             let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2460|>)) in
+             sail2_state_monad$returnS S1)
+           else sail2_state_monad$returnS S1))
+         else sail2_state_monad$returnS S1
+       else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) . 
+      sail2_state_monad$returnS (S1, permissioncheck))))) (\ varstup .  let ((S1 : TLBRecord), (permissioncheck :
+     bool)) = varstup in sail2_state_monad$bindS
+   (if ((((((((((((((~ wasaligned)) /\ (((acctype <> AccType_IFETCH)))))) \/ (((acctype = AccType_DCZVA)))))) /\ (((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ ((~ ((IsFault S1.TLBRecord_addrdesc))))))) then
+      let (tmp_2470 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS
+      (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__18 : FaultRecord) . 
+      let (tmp_2470 : AddressDescriptor) = ((tmp_2470 with<| AddressDescriptor_fault := w__18|>)) in
+      let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2470|>)) in
+      sail2_state_monad$returnS S1)
+    else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) .  sail2_state_monad$bindS
+   (if (((((~ ((IsFault S1.TLBRecord_addrdesc)))) /\ permissioncheck))) then
+      let (tmp_2480 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS
+      (AArch64_CheckPermission S1.TLBRecord_perms vaddress S1.TLBRecord_level
+        S1.TLBRecord_addrdesc.AddressDescriptor_paddress.FullAddress_NS acctype iswrite) (\ (w__19 :
+        FaultRecord) . 
+      let (tmp_2480 : AddressDescriptor) = ((tmp_2480 with<| AddressDescriptor_fault := w__19|>)) in
+      let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2480|>)) in
+      sail2_state_monad$returnS S1)
+    else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) .  sail2_state_monad$bindS
+   (if ((((((((~ ((IsFault S1.TLBRecord_addrdesc)))) /\ (((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ (((acctype = AccType_IFETCH)))))) then sail2_state_monad$bindS
+      (AArch64_InstructionDevice S1.TLBRecord_addrdesc vaddress ipaddress S1.TLBRecord_level acctype
+        iswrite secondstage s2fs1walk) (\ (w__20 : AddressDescriptor) . 
+      let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := w__20|>)) in
+      sail2_state_monad$returnS S1)
+    else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) . 
+   let (hwupdatewalk : bool) = F in
+   let s2fs1walk = F in
+   let (tmp_2490 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS
+   (AArch64_CheckAndUpdateDescriptor S1.TLBRecord_descupdate
+     S1.TLBRecord_addrdesc.AddressDescriptor_fault secondstage vaddress acctype iswrite s2fs1walk
+     hwupdatewalk) (\ (w__21 : FaultRecord) . 
+   let (tmp_2490 : AddressDescriptor) = ((tmp_2490 with<| AddressDescriptor_fault := w__21|>)) in
+   let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2490|>)) in
+   sail2_state_monad$returnS S1.TLBRecord_addrdesc))))))))))))))`;
+
+
+(*val AArch64_FullTranslate : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*)
+
+val _ = Define `
+ ((AArch64_FullTranslate:(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite wasaligned size1=  (sail2_state_monad$bindS
+   (AArch64_FirstStageTranslate vaddress acctype iswrite wasaligned size1) (\ (S1 :
+     AddressDescriptor) .  sail2_state_monad$bindS
+   (undefined_AddressDescriptor () ) (\ (result : AddressDescriptor) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (hwupdatewalk : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((IsFault S1))))) ((HasS2Translation () ))) (\ (w__1 : bool) . 
+   if w__1 then
+     let s2fs1walk = F in
+     let hwupdatewalk = F in
+     AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk
+   else sail2_state_monad$returnS S1)))))))`;
+
+
+(*val AArch64_TranslateAddress : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*)
+
+val _ = Define `
+ ((AArch64_TranslateAddress:(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite wasaligned size1=  (sail2_state_monad$bindS
+   (AArch64_FullTranslate vaddress acctype iswrite wasaligned size1) (\ (result :
+     AddressDescriptor) .  sail2_state_monad$bindS
+   (if (((((~ ((((((acctype = AccType_PTW))) \/ ((((((acctype = AccType_IC))) \/ (((acctype = AccType_AT))))))))))) /\ ((~ ((IsFault result))))))) then sail2_state_monad$bindS
+      (AArch64_CheckDebug vaddress acctype iswrite size1) (\ (w__0 : FaultRecord) . 
+      let (result : AddressDescriptor) = ((result with<| AddressDescriptor_fault := w__0|>)) in
+      sail2_state_monad$returnS result)
+    else sail2_state_monad$returnS result) (\ (result : AddressDescriptor) .  sail2_state_monad$bindS
+   (ZeroExtend__1 (( 64 : int):ii) vaddress  : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+   let (result : AddressDescriptor) = ((result with<| AddressDescriptor_vaddress := w__1|>)) in
+   sail2_state_monad$returnS result)))))`;
+
+
+(*val AArch64_aset_MemSingle : forall   'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> bool -> mword 'p8_times_size_ -> M unit*)
+
+val _ = Define `
+ ((AArch64_aset_MemSingle:(64)words$word -> int -> AccType -> bool -> 'p8_times_size_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype wasaligned value_name=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))")
+   (sail2_state_monad$assert_expS (((address = ((Align__1 address size1  :  64 words$word))))) "(address == Align(address, size))"))
+   (undefined_AddressDescriptor () )) (\ (memaddrdesc : AddressDescriptor) . 
+   let (iswrite : bool) = T in sail2_state_monad$bindS
+   (AArch64_TranslateAddress address acctype iswrite wasaligned size1) (\ (w__0 :
+     AddressDescriptor) . 
+   let memaddrdesc = w__0 in sail2_state_monad$seqS
+   (if ((IsFault memaddrdesc)) then AArch64_Abort address memaddrdesc.AddressDescriptor_fault
+    else sail2_state_monad$returnS () )
+   (let (_ : unit) =
+     (if memaddrdesc.AddressDescriptor_memattrs.MemoryAttributes_shareable then
+       ClearExclusiveByAddress memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1
+     else () ) in sail2_state_monad$bindS
+   (CreateAccessDescriptor acctype) (\ (accdesc : AccessDescriptor) . 
+   aset__Mem memaddrdesc size1 accdesc value_name))))))`;
+
+
+(*val aset_Mem : forall   'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> mword 'p8_times_size_ -> M unit*)
+
+val _ = Define `
+ ((aset_Mem:(64)words$word -> int -> AccType -> 'p8_times_size_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype value_name__arg=
+    (let value_name = value_name__arg in sail2_state_monad$bindS
+   (undefined_int () ) (\ (i : ii) . 
+   let (iswrite : bool) = T in sail2_state_monad$bindS
+   (BigEndian () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
+   (if w__0 then (BigEndianReverse value_name  : ( 'p8_times_size_ words$word) M)
+    else sail2_state_monad$returnS value_name) (\ value_name .  sail2_state_monad$bindS
+   (AArch64_CheckAlignment address size1 acctype iswrite) (\ (aligned : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (atomic : bool) . 
+   let (atomic : bool) =
+     (if ((((((size1 <> (( 16 : int):ii)))) \/ ((~ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))))) then
+       aligned
+     else (address = ((Align__1 address (( 8 : int):ii)  :  64 words$word)))) in sail2_state_monad$bindS
+   (undefined_Constraint () ) (\ (c : Constraint) . 
+   if ((~ atomic)) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS ((size1 > (( 1 : int):ii))) "(size > 1)")
+     (AArch64_aset_MemSingle address (( 1 : int):ii) acctype aligned
+       ((slice value_name (( 0 : int):ii) (( 8 : int):ii)  :  8 words$word))))
+     (if ((~ aligned)) then
+        let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((c = Constraint_FAULT))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FAULT) || (c == Constraint_NONE))")
+        (let (aligned : bool) = (if (((c = Constraint_NONE))) then T else aligned) in
+        sail2_state_monad$returnS aligned)
+      else sail2_state_monad$returnS aligned)) (\ (aligned : bool) . 
+     (sail2_state$foreachS (index_list (( 1 : int):ii) ((size1 - (( 1 : int):ii))) (( 1 : int):ii)) () 
+       (\ i unit_var . 
+         AArch64_aset_MemSingle ((add_vec_int address i  :  64 words$word)) (( 1 : int):ii) acctype aligned
+           ((slice value_name (((( 8 : int):ii) * i)) (( 8 : int):ii)  :  8 words$word)))))
+   else if ((((((size1 = (( 16 : int):ii)))) /\ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))) then sail2_state_monad$seqS
+     (AArch64_aset_MemSingle address (( 8 : int):ii) acctype aligned
+       ((slice value_name (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word)))
+     (AArch64_aset_MemSingle ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype aligned
+       ((slice value_name (( 64 : int):ii) (( 64 : int):ii)  :  64 words$word)))
+   else AArch64_aset_MemSingle address size1 acctype aligned value_name))))))))`;
+
+
+(*val AArch64_aget_MemSingle : forall   'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> bool -> M (mword 'p8_times_size_)*)
+
+val _ = Define `
+ ((AArch64_aget_MemSingle:(64)words$word -> int -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_size_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype wasaligned=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))")
+   (sail2_state_monad$assert_expS (((address = ((Align__1 address size1  :  64 words$word))))) "(address == Align(address, size))"))
+   (undefined_AddressDescriptor () )) (\ (memaddrdesc : AddressDescriptor) .  sail2_state_monad$bindS
+   (undefined_bitvector (((( 8 : int):ii) * size1))  : ( 'p8_times_size_ words$word) M) (\ value_name . 
+   let (iswrite : bool) = F in sail2_state_monad$bindS
+   (AArch64_TranslateAddress address acctype iswrite wasaligned size1) (\ (w__0 :
+     AddressDescriptor) . 
+   let memaddrdesc = w__0 in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((IsFault memaddrdesc)) then AArch64_Abort address memaddrdesc.AddressDescriptor_fault
+    else sail2_state_monad$returnS () )
+   (CreateAccessDescriptor acctype)) (\ (accdesc : AccessDescriptor) . 
+   (aget__Mem memaddrdesc size1 accdesc  : ( 'p8_times_size_ words$word) M)))))))`;
+
+
+(*val aget_Mem : forall   'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> M (mword 'p8_times_size_)*)
+
+val _ = Define `
+ ((aget_Mem:(64)words$word -> int -> AccType ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_size_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))")
+   (undefined_bitvector (((( 8 : int):ii) * size1))  : ( 'p8_times_size_ words$word) M)) (\ value_name .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (i : ii) . 
+   let (iswrite : bool) = F in sail2_state_monad$bindS
+   (AArch64_CheckAlignment address size1 acctype iswrite) (\ (aligned : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (atomic : bool) . 
+   let (atomic : bool) =
+     (if ((((((size1 <> (( 16 : int):ii)))) \/ ((~ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))))) then
+       aligned
+     else (address = ((Align__1 address (( 8 : int):ii)  :  64 words$word)))) in sail2_state_monad$bindS
+   (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+   (if ((~ atomic)) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((size1 > (( 1 : int):ii))) "(size > 1)")
+      (AArch64_aget_MemSingle address (( 1 : int):ii) acctype aligned  : ( 8 words$word) M)) (\ (w__0 :
+         8 words$word) . 
+      let value_name =
+        ((set_slice (((( 8 : int):ii) * size1)) (( 8 : int):ii) value_name (( 0 : int):ii) w__0
+          :  'p8_times_size_ words$word)) in sail2_state_monad$bindS
+      (if ((~ aligned)) then
+         let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in sail2_state_monad$seqS
+         (sail2_state_monad$assert_expS ((((((c = Constraint_FAULT))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FAULT) || (c == Constraint_NONE))")
+         (let (aligned : bool) = (if (((c = Constraint_NONE))) then T else aligned) in
+         sail2_state_monad$returnS aligned)
+       else sail2_state_monad$returnS aligned) (\ (aligned : bool) . 
+      (sail2_state$foreachS (index_list (( 1 : int):ii) ((size1 - (( 1 : int):ii))) (( 1 : int):ii)) value_name
+        (\ i value_name .  sail2_state_monad$bindS
+          (AArch64_aget_MemSingle ((add_vec_int address i  :  64 words$word)) (( 1 : int):ii) acctype aligned
+            : ( 8 words$word) M) (\ (w__1 :  8 words$word) . 
+          let value_name =
+            ((set_slice (((( 8 : int):ii) * size1)) (( 8 : int):ii) value_name (((( 8 : int):ii) * i)) w__1
+              :  'p8_times_size_ words$word)) in
+          sail2_state_monad$returnS value_name)))))
+    else if ((((((size1 = (( 16 : int):ii)))) /\ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))) then sail2_state_monad$bindS
+      (AArch64_aget_MemSingle address (( 8 : int):ii) acctype aligned  : ( 64 words$word) M) (\ (w__2 :
+         64 words$word) . 
+      let value_name =
+        ((set_slice (((( 8 : int):ii) * (( 16 : int):ii))) (( 64 : int):ii) value_name (( 0 : int):ii) w__2
+          :  'p8_times_size_ words$word)) in sail2_state_monad$bindS
+      (AArch64_aget_MemSingle ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype aligned
+        : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
+      let value_name =
+        ((set_slice (((( 8 : int):ii) * (( 16 : int):ii))) (( 64 : int):ii) value_name (( 64 : int):ii) w__3
+          :  'p8_times_size_ words$word)) in
+      sail2_state_monad$returnS value_name))
+    else (AArch64_aget_MemSingle address size1 acctype aligned  : ( 'p8_times_size_ words$word) M)) (\ value_name .  sail2_state_monad$bindS
+   (BigEndian () ) (\ (w__5 : bool) . 
+   if w__5 then (BigEndianReverse value_name  : ( 'p8_times_size_ words$word) M)
+   else sail2_state_monad$returnS value_name)))))))))`;
+
+
+(*val aarch64_memory_vector_single_nowb : forall 'datasize 'esize . Size 'datasize, Size 'esize => itself 'datasize -> itself 'esize -> ii -> ii -> MemOp -> ii -> bool -> integer -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_vector_single_nowb:'datasize itself -> 'esize itself -> int -> int -> MemOp -> int -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) datasize esize index m memop n replicate selem t__arg wback=
+    (let esize = (size_itself_int esize) in
+   let datasize = (size_itself_int datasize) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (let (t : ii) = t__arg in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (CheckFPAdvSIMDEnabled64 () )
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offs : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (rval : 128 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector esize  : ( 'esize words$word) M) (\ (element1 : 'esize bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (s : ii) . 
+   let (ebytes : int) = (ex_int ((esize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M))) (\ (address : 64 bits) . 
+   let offs = ((Zeros__1 (( 64 : int):ii) ()   :  64 words$word)) in sail2_state_monad$bindS
+   (if replicate then sail2_state_monad$bindS
+      (sail2_state$foreachS (index_list (( 0 : int):ii) ((selem - (( 1 : int):ii))) (( 1 : int):ii)) (element1, offs, t)
+        (\ s varstup .  let (element1, offs, t) = varstup in sail2_state_monad$bindS
+          (aget_Mem ((add_vec address offs  :  64 words$word)) ebytes AccType_VEC  : ( 'esize words$word) M) (\ (w__2 : 'esize
+            bits) . 
+          let element1 = w__2 in
+          let (v : int) = (ex_int ((datasize / esize))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "")
+          (aset_V t ((replicate_bits element1 v  :  'datasize words$word))))
+          (let (offs : 64 bits) = ((add_vec_int offs ebytes  :  64 words$word)) in
+          let (t : ii) = (((((ex_int t)) + (( 1 : int):ii))) % (( 32 : int):ii)) in
+          sail2_state_monad$returnS (element1, offs, t))))) (\ varstup .  let ((element1 : 'esize bits), (offs : 64
+        bits), (t : ii)) = varstup in
+      sail2_state_monad$returnS offs)
+    else sail2_state_monad$bindS
+      (sail2_state$foreachS (index_list (( 0 : int):ii) ((selem - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, t)
+        (\ s varstup .  let (offs, rval, t) = varstup in sail2_state_monad$bindS
+          (aget_V (( 128 : int):ii) t  : ( 128 words$word) M) (\ (w__3 : 128 bits) . 
+          let rval = w__3 in sail2_state_monad$bindS
+          (if (((memop = MemOp_LOAD))) then sail2_state_monad$bindS
+             (aget_Mem ((add_vec address offs  :  64 words$word)) ebytes AccType_VEC  : ( 'esize words$word) M) (\ (w__4 :
+                'esize words$word) .  sail2_state_monad$bindS
+             (aset_Elem__0 rval index ((make_the_value esize  :  'esize itself)) w__4
+               : ( 128 words$word) M) (\ (w__5 : 128 bits) . 
+             let rval = w__5 in sail2_state_monad$seqS
+             (aset_V t rval) (sail2_state_monad$returnS rval)))
+           else sail2_state_monad$bindS
+             (aget_Elem__0 rval index ((make_the_value esize  :  'esize itself))  : ( 'esize words$word) M) (\ w__6 .  sail2_state_monad$seqS
+             (aset_Mem ((add_vec address offs  :  64 words$word)) ebytes AccType_VEC w__6) (sail2_state_monad$returnS rval))) (\ (rval : 128
+            bits) . 
+          let (offs : 64 bits) = ((add_vec_int offs ebytes  :  64 words$word)) in
+          let (t : ii) = (((((ex_int t)) + (( 1 : int):ii))) % (( 32 : int):ii)) in
+          sail2_state_monad$returnS (offs, rval, t))))) (\ varstup .  let ((offs : 64 bits), (rval : 128 bits), (t :
+        ii)) = varstup in
+      sail2_state_monad$returnS offs)) (\ (offs : 64 bits) . 
+   if wback then sail2_state_monad$bindS
+     (if (((m <> (( 31 : int):ii)))) then (aget_X (( 64 : int):ii) m  : ( 64 words$word) M)
+      else sail2_state_monad$returnS offs) (\ (offs : 64 bits) . 
+     if (((n = (( 31 : int):ii)))) then aset_SP ((add_vec address offs  :  64 words$word))
+     else aset_X n ((add_vec address offs  :  64 words$word)))
+   else sail2_state_monad$returnS () ))))))))))`;
+
+
+(*val aarch64_memory_vector_multiple_nowb : forall 'datasize 'esize   . Size 'datasize, Size 'esize => itself 'datasize -> integer -> itself 'esize -> ii -> MemOp -> ii -> integer -> integer -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_vector_multiple_nowb:'datasize itself -> int -> 'esize itself -> int -> MemOp -> int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) datasize elements esize m memop n rpt selem t wback=
+    (let esize = (size_itself_int esize) in
+   let datasize = (size_itself_int datasize) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (CheckFPAdvSIMDEnabled64 () ))
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offs : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (rval : 'datasize bits) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (e : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (r : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (s : ii) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (tt : ii) . 
+   let ebytes = (ex_int ((esize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M))) (\ (address : 64 bits) . 
+   let offs = ((Zeros__1 (( 64 : int):ii) ()   :  64 words$word)) in sail2_state_monad$bindS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) ((rpt - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, tt)
+     (\ r varstup .  let (offs, rval, tt) = varstup in
+       (sail2_state$foreachS (index_list (( 0 : int):ii) ((elements - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, tt)
+         (\ e varstup .  let (offs, rval, tt) = varstup in
+           let tt = (((t + r)) % (( 32 : int):ii)) in
+           (sail2_state$foreachS (index_list (( 0 : int):ii) ((selem - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, tt)
+             (\ s varstup .  let (offs, rval, tt) = varstup in sail2_state_monad$bindS
+               (aget_V datasize tt  : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . 
+               let rval = w__2 in sail2_state_monad$bindS
+               (if (((memop = MemOp_LOAD))) then sail2_state_monad$bindS
+                  (aget_Mem ((add_vec address offs  :  64 words$word)) ebytes AccType_VEC
+                    : ( 'esize words$word) M) (\ (w__3 :  'esize words$word) .  sail2_state_monad$bindS
+                  (aset_Elem__0 rval e ((make_the_value esize  :  'esize itself)) w__3
+                    : ( 'datasize words$word) M) (\ (w__4 : 'datasize bits) . 
+                  let rval = w__4 in sail2_state_monad$seqS
+                  (aset_V tt rval) (sail2_state_monad$returnS rval)))
+                else sail2_state_monad$bindS
+                  (aget_Elem__0 rval e ((make_the_value esize  :  'esize itself))  : ( 'esize words$word) M) (\ w__5 .  sail2_state_monad$seqS
+                  (aset_Mem ((add_vec address offs  :  64 words$word)) ebytes AccType_VEC w__5)
+                  (sail2_state_monad$returnS rval))) (\ (rval : 'datasize bits) . 
+               let (offs : 64 bits) = ((add_vec_int offs ebytes  :  64 words$word)) in
+               let (tt : ii) = (((((ex_int tt)) + (( 1 : int):ii))) % (( 32 : int):ii)) in
+               sail2_state_monad$returnS (offs, rval, tt))))))))) (\ varstup .  let ((offs : 64 bits), (rval : 'datasize
+     bits), (tt : ii)) = varstup in
+   if wback then sail2_state_monad$bindS
+     (if (((m <> (( 31 : int):ii)))) then (aget_X (( 64 : int):ii) m  : ( 64 words$word) M)
+      else sail2_state_monad$returnS offs) (\ (offs : 64 bits) . 
+     if (((n = (( 31 : int):ii)))) then aset_SP ((add_vec address offs  :  64 words$word))
+     else aset_X n ((add_vec address offs  :  64 words$word)))
+   else sail2_state_monad$returnS () )))))))))))`;
+
+
+(*val aarch64_memory_single_simdfp_register : AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_simdfp_register:AccType -> int -> ExtendType -> int -> MemOp -> int -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__83 extend_type m memop n postindex shift t wback=
+    (if (((l__83 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M)) (\ (offset : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 8 : int):ii) t  : ( 8 words$word) M) (\ (w__2 : 8 bits) . 
+        let data = w__2 in
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__3 : 8
+          bits) . 
+        let data = w__3 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () )))))
+   else if (((l__83 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M)) (\ (offset : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 16 : int):ii) t  : ( 16 words$word) M) (\ (w__6 : 16 bits) . 
+        let data = w__6 in
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__7 : 16
+          bits) . 
+        let data = w__7 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () )))))
+   else if (((l__83 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M)) (\ (offset : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 32 : int):ii) t  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+        let data = w__10 in
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__11 : 32
+          bits) . 
+        let data = w__11 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () )))))
+   else if (((l__83 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M)) (\ (offset : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 64 : int):ii) t  : ( 64 words$word) M) (\ (w__14 : 64 bits) . 
+        let data = w__14 in
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__15 : 64
+          bits) . 
+        let data = w__15 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () )))))
+   else if (((l__83 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M)) (\ (offset : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 128 : int):ii) t  : ( 128 words$word) M) (\ (w__18 : 128 bits) . 
+        let data = w__18 in
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__19 : 128
+          bits) . 
+        let data = w__19 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () )))))
+   else
+     let dbytes = (ex_int ((l__83 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_memory_single_simdfp_immediate_signed_postidx : AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_simdfp_immediate_signed_postidx:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__78 memop n offset postindex t wback=
+    (if (((l__78 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 8 : int):ii) t  : ( 8 words$word) M) (\ (w__2 : 8 bits) . 
+        let data = w__2 in
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__3 : 8
+          bits) . 
+        let data = w__3 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__78 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 16 : int):ii) t  : ( 16 words$word) M) (\ (w__6 : 16 bits) . 
+        let data = w__6 in
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__7 : 16
+          bits) . 
+        let data = w__7 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__78 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 32 : int):ii) t  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+        let data = w__10 in
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__11 : 32
+          bits) . 
+        let data = w__11 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__78 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 64 : int):ii) t  : ( 64 words$word) M) (\ (w__14 : 64 bits) . 
+        let data = w__14 in
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__15 : 64
+          bits) . 
+        let data = w__15 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__78 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 128 : int):ii) t  : ( 128 words$word) M) (\ (w__18 : 128 bits) . 
+        let data = w__18 in
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__19 : 128
+          bits) . 
+        let data = w__19 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else
+     let dbytes = (ex_int ((l__78 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_memory_single_simdfp_immediate_signed_offset_normal : AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_simdfp_immediate_signed_offset_normal:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__73 memop n offset postindex t wback=
+    (if (((l__73 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 8 : int):ii) t  : ( 8 words$word) M) (\ (w__2 : 8 bits) . 
+        let data = w__2 in
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__3 : 8
+          bits) . 
+        let data = w__3 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__73 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 16 : int):ii) t  : ( 16 words$word) M) (\ (w__6 : 16 bits) . 
+        let data = w__6 in
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__7 : 16
+          bits) . 
+        let data = w__7 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__73 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 32 : int):ii) t  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+        let data = w__10 in
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__11 : 32
+          bits) . 
+        let data = w__11 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__73 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 64 : int):ii) t  : ( 64 words$word) M) (\ (w__14 : 64 bits) . 
+        let data = w__14 in
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__15 : 64
+          bits) . 
+        let data = w__15 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else if (((l__73 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (CheckFPAdvSIMDEnabled64 () ))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (aget_V (( 128 : int):ii) t  : ( 128 words$word) M) (\ (w__18 : 128 bits) . 
+        let data = w__18 in
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__19 : 128
+          bits) . 
+        let data = w__19 in
+        aset_V t data)
+     )
+     (if wback then
+       let (address : 64 bits) =
+         (if postindex then (add_vec address offset  :  64 words$word)
+         else address) in
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address
+     else sail2_state_monad$returnS () ))))
+   else
+     let dbytes = (ex_int ((l__73 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_memory_ordered : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> MemOp -> ii -> itself 'regsize -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_ordered:AccType -> 'datasize itself -> MemOp -> int -> 'regsize itself -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n regsize t=
+    (let regsize = (size_itself_int regsize) in
+   let datasize = (size_itself_int datasize) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (data : 'datasize bits) . 
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M))) (\ (address : 64 bits) . 
+   (case memop of
+     MemOp_STORE => sail2_state_monad$bindS
+      (aget_X ((int_of_num (words$word_len data))) t  : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . 
+      let data = w__2 in
+      aset_Mem address dbytes acctype data)
+   | MemOp_LOAD => sail2_state_monad$bindS
+      (aget_Mem address dbytes acctype  : ( 'datasize words$word) M) (\ (w__3 : 'datasize bits) . 
+      let data = w__3 in sail2_state_monad$bindS
+      (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__4 :
+         'regsize words$word) . 
+      aset_X t w__4))
+   ))))))`;
+
+
+(*val memory_ordered_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_ordered_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B0]  :  1 words$word)))) then AccType_LIMITEDORDERED
+       else AccType_ORDERED) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 8 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_ordered acctype ((make_the_value (( 8 : int):ii)  :  8 itself)) memop n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t)
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B0]  :  1 words$word)))) then AccType_LIMITEDORDERED
+       else AccType_ORDERED) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 16 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_ordered acctype ((make_the_value (( 16 : int):ii)  :  16 itself)) memop n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t)
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B0]  :  1 words$word)))) then AccType_LIMITEDORDERED
+       else AccType_ORDERED) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_ordered acctype ((make_the_value (( 32 : int):ii)  :  32 itself)) memop n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t)
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B0]  :  1 words$word)))) then AccType_LIMITEDORDERED
+       else AccType_ORDERED) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_ordered acctype ((make_the_value (( 64 : int):ii)  :  64 itself)) memop n
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) t)))`;
+
+
+(*val aarch64_memory_orderedrcpc : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> ii -> itself 'regsize -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_orderedrcpc:AccType -> 'datasize itself -> int -> 'regsize itself -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize n regsize t=
+    (let regsize = (size_itself_int regsize) in
+   let datasize = (size_itself_int datasize) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (data : 'datasize bits) . 
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M))) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (aget_Mem address dbytes acctype  : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . 
+   let data = w__2 in sail2_state_monad$bindS
+   (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__3 :
+      'regsize words$word) . 
+   aset_X t w__3)))))))`;
+
+
+(*val memory_orderedrcpc_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_orderedrcpc_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 A R1 Rs o3 opc Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) = AccType_ORDERED in
+     let (elsize : ii) = ((( 8 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 8 : int):ii)  :  8 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t)
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) = AccType_ORDERED in
+     let (elsize : ii) = ((( 16 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 16 : int):ii)  :  16 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t)
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) = AccType_ORDERED in
+     let (elsize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t)
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) = AccType_ORDERED in
+     let (elsize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 64 : int):ii)  :  64 itself)) n
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) t)))`;
+
+
+(*val aarch64_memory_literal_simdfp : mword ty64 -> integer -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_literal_simdfp:(64)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset l__70 t=
+    (if (((l__70 = (( 4 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS T ""))
+     (aget_PC ()   : ( 64 words$word) M)) (\ (w__0 :  64 words$word) . 
+     let (address : 64 bits) = ((add_vec w__0 offset  :  64 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_Mem address (( 4 : int):ii) AccType_VEC  : ( 32 words$word) M)) (\ (w__1 : 32 bits) . 
+     let data = w__1 in
+     aset_V t data)))
+   else if (((l__70 = (( 8 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS T ""))
+     (aget_PC ()   : ( 64 words$word) M)) (\ (w__2 :  64 words$word) . 
+     let (address : 64 bits) = ((add_vec w__2 offset  :  64 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_Mem address (( 8 : int):ii) AccType_VEC  : ( 64 words$word) M)) (\ (w__3 : 64 bits) . 
+     let data = w__3 in
+     aset_V t data)))
+   else if (((l__70 = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (sail2_state_monad$assert_expS T ""))
+     (aget_PC ()   : ( 64 words$word) M)) (\ (w__4 :  64 words$word) . 
+     let (address : 64 bits) = ((add_vec w__4 offset  :  64 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (CheckFPAdvSIMDEnabled64 () )
+     (aget_Mem address (( 16 : int):ii) AccType_VEC  : ( 128 words$word) M)) (\ (w__5 : 128 bits) . 
+     let data = w__5 in
+     aset_V t data)))
+   else sail2_state_monad$seqS (sail2_state_monad$assert_expS T "") (sail2_state_monad$assert_expS T "")))`;
+
+
+(*val aarch64_memory_literal_general : forall 'size. Size 'size => MemOp -> mword ty64 -> bool -> itself 'size -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_literal_general:MemOp ->(64)words$word -> bool -> 'size itself -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) memop offset signed size1 t=
+    (let size1 = (size_itself_int size1) in sail2_state_monad$bindS
+   (aget_PC ()   : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let (address : 64 bits) = ((add_vec w__0 offset  :  64 words$word)) in sail2_state_monad$bindS
+   (undefined_bitvector size1  : ( 'size words$word) M) (\ (data : 'size bits) . 
+   (case memop of
+     MemOp_LOAD => sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS T "")
+      (let bytes = (size1 / (( 8 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS T "")
+      (aget_Mem address bytes AccType_NORMAL  : ( 'size words$word) M)) (\ (w__1 : 'size bits) . 
+      let data = w__1 in
+      if signed then sail2_state_monad$bindS
+        (SignExtend__0 data ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+           64 words$word) . 
+        aset_X t w__2)
+      else aset_X t data))
+   | MemOp_PREFETCH =>
+      Prefetch address
+        ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+   )))))`;
+
+
+(*val memory_literal_general_decode : mword ty2 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_literal_general_decode:(2)words$word ->(1)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 imm19 Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (memop : MemOp) = MemOp_LOAD in
+     let (signed : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (size1 : ii) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let size1 = ((( 4 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+        ((make_the_value (( 64 : int):ii)  :  64 itself))
+       : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+     let offset = w__0 in
+     aarch64_memory_literal_general MemOp_LOAD offset F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) t))))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (memop : MemOp) = MemOp_LOAD in
+     let (signed : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (size1 : ii) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let size1 = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+        ((make_the_value (( 64 : int):ii)  :  64 itself))
+       : ( 64 words$word) M) (\ (w__1 : 64 bits) . 
+     let offset = w__1 in
+     aarch64_memory_literal_general MemOp_LOAD offset F
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) t))))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (memop : MemOp) = MemOp_LOAD in
+     let (signed : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (size1 : ii) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let size1 = ((( 4 : int):ii)) in
+     let signed = T in sail2_state_monad$bindS
+     (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+        ((make_the_value (( 64 : int):ii)  :  64 itself))
+       : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+     let offset = w__2 in
+     aarch64_memory_literal_general MemOp_LOAD offset T ((make_the_value (( 32 : int):ii)  :  32 itself))
+       t))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (memop : MemOp) = MemOp_LOAD in
+     let (signed : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (size1 : ii) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let memop = MemOp_PREFETCH in sail2_state_monad$bindS
+     (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+        ((make_the_value (( 64 : int):ii)  :  64 itself))
+       : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+     let offset = w__3 in
+     aarch64_memory_literal_general MemOp_PREFETCH offset F
+       ((make_the_value (((( 8 : int):ii) * (( 32 : int):ii)))  :  256 itself)) t))))))`;
+
+
+(*val aarch64_memory_atomicops_swp : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_atomicops_swp:int -> AccType -> int -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__65 ldacctype n regsize s stacctype t=
+    (if (((l__65 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 8 words$word) M) (\ (w__2 : 8
+       bits) . 
+     let data = w__2 in sail2_state_monad$bindS
+     (aget_X ((int_of_num (words$word_len data))) s  : ( 8 words$word) M) (\ w__3 .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype w__3)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__4 :
+        'regsize words$word) . 
+     aset_X t w__4)))))))
+   else if (((l__65 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 16 words$word) M) (\ (w__7 : 16
+       bits) . 
+     let data = w__7 in sail2_state_monad$bindS
+     (aget_X ((int_of_num (words$word_len data))) s  : ( 16 words$word) M) (\ w__8 .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype w__8)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__9 :
+        'regsize words$word) . 
+     aset_X t w__9)))))))
+   else if (((l__65 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 32 words$word) M) (\ (w__12 : 32
+       bits) . 
+     let data = w__12 in sail2_state_monad$bindS
+     (aget_X ((int_of_num (words$word_len data))) s  : ( 32 words$word) M) (\ w__13 .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype w__13)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__14 :
+        'regsize words$word) . 
+     aset_X t w__14)))))))
+   else if (((l__65 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 64 words$word) M) (\ (w__17 : 64
+       bits) . 
+     let data = w__17 in sail2_state_monad$bindS
+     (aget_X ((int_of_num (words$word_len address))) s  : ( 64 words$word) M) (\ w__18 .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype w__18)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__19 :
+        'regsize words$word) . 
+     aset_X t w__19)))))))
+   else if (((l__65 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 128 words$word) M) (\ (w__22 : 128
+       bits) . 
+     let data = w__22 in sail2_state_monad$bindS
+     (aget_X ((int_of_num (words$word_len data))) s  : ( 128 words$word) M) (\ w__23 .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype w__23)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__24 :
+        'regsize words$word) . 
+     aset_X t w__24)))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__65 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_atomicops_st : ii -> AccType -> ii -> MemAtomicOp -> ii -> AccType -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_atomicops_st:int -> AccType -> int -> MemAtomicOp -> int -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__60 ldacctype n op s stacctype=
+    (if (((l__60 = (( 8 : int):ii)))) then
+     let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (value_name : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) s  : ( 8 words$word) M) (\ (w__0 : 8 bits) . 
+     let value_name = w__0 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 8 words$word) M) (\ (w__3 : 8
+       bits) . 
+     let data = w__3 in
+     let (result : 8 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  8 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  8 words$word))  :  8 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  8 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  8 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in
+     aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype result)))))))
+   else if (((l__60 = (( 16 : int):ii)))) then
+     let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (value_name : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) s  : ( 16 words$word) M) (\ (w__4 : 16 bits) . 
+     let value_name = w__4 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 16 words$word) M) (\ (w__7 : 16
+       bits) . 
+     let data = w__7 in
+     let (result : 16 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  16 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  16 words$word))  :  16 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  16 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  16 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in
+     aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype result)))))))
+   else if (((l__60 = (( 32 : int):ii)))) then
+     let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (value_name : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) s  : ( 32 words$word) M) (\ (w__8 : 32 bits) . 
+     let value_name = w__8 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 32 words$word) M) (\ (w__11 : 32
+       bits) . 
+     let data = w__11 in
+     let (result : 32 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  32 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  32 words$word))  :  32 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  32 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  32 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in
+     aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype result)))))))
+   else if (((l__60 = (( 64 : int):ii)))) then
+     let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (value_name : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) s  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+     let value_name = w__12 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 64 words$word) M) (\ (w__15 : 64
+       bits) . 
+     let data = w__15 in
+     let (result : 64 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  64 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  64 words$word))  :  64 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  64 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  64 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in
+     aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype result)))))))
+   else if (((l__60 = (( 128 : int):ii)))) then
+     let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (value_name : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) s  : ( 128 words$word) M) (\ (w__16 : 128 bits) . 
+     let value_name = w__16 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 128 words$word) M) (\ (w__19 : 128
+       bits) . 
+     let data = w__19 in
+     let (result : 128 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  128 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  128 words$word))  :  128 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  128 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  128 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in
+     aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype result)))))))
+   else
+     let dbytes = (ex_int ((l__60 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint"))`;
+
+
+(*val aarch64_memory_atomicops_ld : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> MemAtomicOp -> itself 'regsize -> ii -> AccType -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_atomicops_ld:int -> AccType -> int -> MemAtomicOp -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__55 ldacctype n op regsize s stacctype t=
+    (if (((l__55 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (value_name : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (result : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) s  : ( 8 words$word) M) (\ (w__0 : 8 bits) . 
+     let value_name = w__0 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 8 words$word) M) (\ (w__3 : 8
+       bits) . 
+     let data = w__3 in
+     let (result : 8 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  8 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  8 words$word))  :  8 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  8 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  8 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype result)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__4 :
+        'regsize words$word) . 
+     aset_X t w__4)))))))))
+   else if (((l__55 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (value_name : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (result : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) s  : ( 16 words$word) M) (\ (w__5 : 16 bits) . 
+     let value_name = w__5 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 16 words$word) M) (\ (w__8 : 16
+       bits) . 
+     let data = w__8 in
+     let (result : 16 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  16 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  16 words$word))  :  16 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  16 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  16 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype result)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__9 :
+        'regsize words$word) . 
+     aset_X t w__9)))))))))
+   else if (((l__55 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (value_name : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (result : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) s  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+     let value_name = w__10 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 32 words$word) M) (\ (w__13 : 32
+       bits) . 
+     let data = w__13 in
+     let (result : 32 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  32 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  32 words$word))  :  32 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  32 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  32 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype result)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__14 :
+        'regsize words$word) . 
+     aset_X t w__14)))))))))
+   else if (((l__55 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (value_name : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (result : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) s  : ( 64 words$word) M) (\ (w__15 : 64 bits) . 
+     let value_name = w__15 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 64 words$word) M) (\ (w__18 : 64
+       bits) . 
+     let data = w__18 in
+     let (result : 64 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  64 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  64 words$word))  :  64 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  64 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  64 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype result)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__19 :
+        'regsize words$word) . 
+     aset_X t w__19)))))))))
+   else if (((l__55 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (value_name : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (result : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) s  : ( 128 words$word) M) (\ (w__20 : 128 bits) . 
+     let value_name = w__20 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 128 words$word) M) (\ (w__23 : 128
+       bits) . 
+     let data = w__23 in
+     let (result : 128 bits) =
+       ((case op of
+         MemAtomicOp_ADD => (add_vec data value_name  :  128 words$word)
+       | MemAtomicOp_BIC => (and_vec data ((not_vec value_name  :  128 words$word))  :  128 words$word)
+       | MemAtomicOp_EOR => (xor_vec data value_name  :  128 words$word)
+       | MemAtomicOp_ORR => (or_vec data value_name  :  128 words$word)
+       | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name
+       | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data
+       | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name
+       | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data
+       )) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype result)
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__24 :
+        'regsize words$word) . 
+     aset_X t w__24)))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__55 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_atomicops_cas_single : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_atomicops_cas_single:int -> AccType -> int -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__50 ldacctype n regsize s stacctype t=
+    (if (((l__50 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (comparevalue : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (newvalue : 8 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) s  : ( 8 words$word) M) (\ (w__0 : 8 bits) . 
+     let comparevalue = w__0 in sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) t  : ( 8 words$word) M) (\ (w__1 : 8 bits) . 
+     let newvalue = w__1 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 8 words$word) M) (\ (w__4 : 8
+       bits) . 
+     let data = w__4 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__5 :
+        'regsize words$word) . 
+     aset_X s w__5))))))))))
+   else if (((l__50 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (comparevalue : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (newvalue : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) s  : ( 16 words$word) M) (\ (w__6 : 16 bits) . 
+     let comparevalue = w__6 in sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) t  : ( 16 words$word) M) (\ (w__7 : 16 bits) . 
+     let newvalue = w__7 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 16 words$word) M) (\ (w__10 : 16
+       bits) . 
+     let data = w__10 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__11 :
+        'regsize words$word) . 
+     aset_X s w__11))))))))))
+   else if (((l__50 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (comparevalue : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (newvalue : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) s  : ( 32 words$word) M) (\ (w__12 : 32 bits) . 
+     let comparevalue = w__12 in sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) t  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+     let newvalue = w__13 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 32 words$word) M) (\ (w__16 : 32
+       bits) . 
+     let data = w__16 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__17 :
+        'regsize words$word) . 
+     aset_X s w__17))))))))))
+   else if (((l__50 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (comparevalue : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (newvalue : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) s  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+     let comparevalue = w__18 in sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) t  : ( 64 words$word) M) (\ (w__19 : 64 bits) . 
+     let newvalue = w__19 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 64 words$word) M) (\ (w__22 : 64
+       bits) . 
+     let data = w__22 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__23 :
+        'regsize words$word) . 
+     aset_X s w__23))))))))))
+   else if (((l__50 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (comparevalue : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (newvalue : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) s  : ( 128 words$word) M) (\ (w__24 : 128 bits) . 
+     let comparevalue = w__24 in sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) t  : ( 128 words$word) M) (\ (w__25 : 128 bits) . 
+     let newvalue = w__25 in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 128 words$word) M) (\ (w__28 : 128
+       bits) . 
+     let data = w__28 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M)) (\ (w__29 :
+        'regsize words$word) . 
+     aset_X s w__29))))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__50 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_atomicops_cas_pair : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_atomicops_cas_pair:int -> AccType -> int -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__45 ldacctype n regsize s stacctype t=
+    (if (((l__45 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (comparevalue : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (newvalue : 16 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) s  : ( 8 words$word) M) (\ (s1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) ((s + (( 1 : int):ii)))  : ( 8 words$word) M) (\ (s2 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) t  : ( 8 words$word) M) (\ (t1 : 8 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) ((t + (( 1 : int):ii)))  : ( 8 words$word) M) (\ (t2 : 8 bits) .  sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__0 : bool) . 
+     let comparevalue =
+       (if w__0 then (concat_vec s1 s2  :  16 words$word)
+       else (concat_vec s2 s1  :  16 words$word)) in sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__1 : bool) . 
+     let newvalue =
+       (if w__1 then (concat_vec t1 t2  :  16 words$word)
+       else (concat_vec t2 t1  :  16 words$word)) in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 16 words$word) M) (\ (w__4 : 16
+       bits) . 
+     let data = w__4 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (BigEndian () )) (\ (w__5 : bool) . 
+     if w__5 then sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 8 : int):ii) (( 8 : int):ii)  :  8 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__6 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__6)
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 8 : int):ii)  :  8 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__7 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__7))
+     else sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 8 : int):ii)  :  8 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__8 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__8)
+       (ZeroExtend__0 ((slice data (( 8 : int):ii) (( 8 : int):ii)  :  8 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__9 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__9))))))))))))))))
+   else if (((l__45 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (comparevalue : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (newvalue : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) s  : ( 16 words$word) M) (\ (s1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) ((s + (( 1 : int):ii)))  : ( 16 words$word) M) (\ (s2 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) t  : ( 16 words$word) M) (\ (t1 : 16 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) ((t + (( 1 : int):ii)))  : ( 16 words$word) M) (\ (t2 : 16 bits) .  sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__10 : bool) . 
+     let comparevalue =
+       (if w__10 then (concat_vec s1 s2  :  32 words$word)
+       else (concat_vec s2 s1  :  32 words$word)) in sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__11 : bool) . 
+     let newvalue =
+       (if w__11 then (concat_vec t1 t2  :  32 words$word)
+       else (concat_vec t2 t1  :  32 words$word)) in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 32 words$word) M) (\ (w__14 : 32
+       bits) . 
+     let data = w__14 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (BigEndian () )) (\ (w__15 : bool) . 
+     if w__15 then sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 16 : int):ii) (( 16 : int):ii)  :  16 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__16 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__16)
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 16 : int):ii)  :  16 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__17 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__17))
+     else sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 16 : int):ii)  :  16 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__18 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__18)
+       (ZeroExtend__0 ((slice data (( 16 : int):ii) (( 16 : int):ii)  :  16 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__19 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__19))))))))))))))))
+   else if (((l__45 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (comparevalue : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (newvalue : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) s  : ( 32 words$word) M) (\ (s1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) ((s + (( 1 : int):ii)))  : ( 32 words$word) M) (\ (s2 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) t  : ( 32 words$word) M) (\ (t1 : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) ((t + (( 1 : int):ii)))  : ( 32 words$word) M) (\ (t2 : 32 bits) .  sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__20 : bool) . 
+     let comparevalue =
+       (if w__20 then (concat_vec s1 s2  :  64 words$word)
+       else (concat_vec s2 s1  :  64 words$word)) in sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__21 : bool) . 
+     let newvalue =
+       (if w__21 then (concat_vec t1 t2  :  64 words$word)
+       else (concat_vec t2 t1  :  64 words$word)) in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 64 words$word) M) (\ (w__24 : 64
+       bits) . 
+     let data = w__24 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (BigEndian () )) (\ (w__25 : bool) . 
+     if w__25 then sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 32 : int):ii) (( 32 : int):ii)  :  32 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__26 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__26)
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__27 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__27))
+     else sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__28 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__28)
+       (ZeroExtend__0 ((slice data (( 32 : int):ii) (( 32 : int):ii)  :  32 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__29 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__29))))))))))))))))
+   else if (((l__45 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (comparevalue : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (newvalue : 128 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) s  : ( 64 words$word) M) (\ (s1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) ((s + (( 1 : int):ii)))  : ( 64 words$word) M) (\ (s2 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) t  : ( 64 words$word) M) (\ (t1 : 64 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) ((t + (( 1 : int):ii)))  : ( 64 words$word) M) (\ (t2 : 64 bits) .  sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__30 : bool) . 
+     let comparevalue =
+       (if w__30 then (concat_vec s1 s2  :  128 words$word)
+       else (concat_vec s2 s1  :  128 words$word)) in sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__31 : bool) . 
+     let newvalue =
+       (if w__31 then (concat_vec t1 t2  :  128 words$word)
+       else (concat_vec t2 t1  :  128 words$word)) in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 128 words$word) M) (\ (w__34 : 128
+       bits) . 
+     let data = w__34 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (BigEndian () )) (\ (w__35 : bool) . 
+     if w__35 then sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 64 : int):ii) (( 64 : int):ii)  :  64 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__36 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__36)
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__37 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__37))
+     else sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 64 : int):ii)  :  64 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__38 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__38)
+       (ZeroExtend__0 ((slice data (( 64 : int):ii) (( 64 : int):ii)  :  64 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__39 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__39))))))))))))))))
+   else if (((l__45 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 256 : int):ii)  : ( 256 words$word) M) (\ (comparevalue : 256 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 256 : int):ii)  : ( 256 words$word) M) (\ (newvalue : 256 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 256 : int):ii)  : ( 256 words$word) M) (\ (data : 256 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) s  : ( 128 words$word) M) (\ (s1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) ((s + (( 1 : int):ii)))  : ( 128 words$word) M) (\ (s2 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) t  : ( 128 words$word) M) (\ (t1 : 128 bits) .  sail2_state_monad$bindS
+     (aget_X (( 128 : int):ii) ((t + (( 1 : int):ii)))  : ( 128 words$word) M) (\ (t2 : 128 bits) .  sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__40 : bool) . 
+     let comparevalue =
+       (if w__40 then (concat_vec s1 s2  :  256 words$word)
+       else (concat_vec s2 s1  :  256 words$word)) in sail2_state_monad$bindS
+     (BigEndian () ) (\ (w__41 : bool) . 
+     let newvalue =
+       (if w__41 then (concat_vec t1 t2  :  256 words$word)
+       else (concat_vec t2 t1  :  256 words$word)) in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (aget_Mem address (((( 256 : int):ii) / (( 8 : int):ii))) ldacctype  : ( 256 words$word) M) (\ (w__44 : 256
+       bits) . 
+     let data = w__44 in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((data = comparevalue))) then
+        aset_Mem address (((( 256 : int):ii) / (( 8 : int):ii))) stacctype newvalue
+      else sail2_state_monad$returnS () )
+     (BigEndian () )) (\ (w__45 : bool) . 
+     if w__45 then sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 128 : int):ii) (( 128 : int):ii)  :  128 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__46 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__46)
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 128 : int):ii)  :  128 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__47 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__47))
+     else sail2_state_monad$bindS
+       (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 128 : int):ii)  :  128 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M) (\ (w__48 :  'regsize words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+       (aset_X s w__48)
+       (ZeroExtend__0 ((slice data (( 128 : int):ii) (( 128 : int):ii)  :  128 words$word))
+          ((make_the_value regsize  :  'regsize itself))
+         : ( 'regsize words$word) M)) (\ (w__49 :  'regsize words$word) . 
+       aset_X ((s + (( 1 : int):ii))) w__49))))))))))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__45 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val AArch64_SetExclusiveMonitors : mword ty64 -> ii -> M unit*)
+
+val _ = Define `
+ ((AArch64_SetExclusiveMonitors:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1=
+    (let (acctype : AccType) = AccType_ATOMIC in
+   let (iswrite : bool) = F in
+   let (aligned : bool) = (address <> ((Align__1 address size1  :  64 words$word))) in sail2_state_monad$bindS
+   (AArch64_TranslateAddress address acctype iswrite aligned size1) (\ (memaddrdesc :
+     AddressDescriptor) . 
+   let (_ : unit) = (if ((IsFault memaddrdesc)) then ()  else () ) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if memaddrdesc.AddressDescriptor_memattrs.MemoryAttributes_shareable then
+      MarkExclusiveGlobal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1
+    else sail2_state_monad$returnS () )
+   (MarkExclusiveLocal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1))
+   (AArch64_MarkExclusiveVA address ((ProcessorID () )) size1))))`;
+
+
+(*val AArch64_ExclusiveMonitorsPass : mword ty64 -> ii -> M bool*)
+
+val _ = Define `
+ ((AArch64_ExclusiveMonitorsPass:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1=
+    (let (acctype : AccType) = AccType_ATOMIC in
+   let (iswrite : bool) = T in
+   let (aligned : bool) = (address = ((Align__1 address size1  :  64 words$word))) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ aligned)) then
+      let secondstage = F in sail2_state_monad$bindS
+      (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__0 : FaultRecord) . 
+      AArch64_Abort address w__0)
+    else sail2_state_monad$returnS () )
+   (AArch64_IsExclusiveVA address ((ProcessorID () )) size1)) (\ (passed : bool) . 
+   if ((~ passed)) then sail2_state_monad$returnS F
+   else sail2_state_monad$bindS
+     (AArch64_TranslateAddress address acctype iswrite aligned size1) (\ (memaddrdesc :
+       AddressDescriptor) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if ((IsFault memaddrdesc)) then AArch64_Abort address memaddrdesc.AddressDescriptor_fault
+      else sail2_state_monad$returnS () )
+     (IsExclusiveLocal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1)) (\ (w__1 :
+       bool) . 
+     let passed = w__1 in
+     if passed then sail2_state_monad$seqS
+       (ClearExclusiveLocal ((ProcessorID () )))
+       (if memaddrdesc.AddressDescriptor_memattrs.MemoryAttributes_shareable then
+         IsExclusiveGlobal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1
+       else sail2_state_monad$returnS passed)
+     else sail2_state_monad$returnS passed))))))`;
+
+
+(*val AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled : unit -> M bool*)
+
+val _ = Define `
+ ((AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))
+     ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : bool) . 
+   if w__1 then sail2_state_monad$returnS F
+   else
+     sail2_state$and_boolS ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGEN_ref) (\ (w__2 : signal) .  sail2_state_monad$returnS (((w__2 = HIGH)))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS SPIDEN_ref) (\ (w__3 : signal) .  sail2_state_monad$returnS (((w__3 = HIGH))))))))`;
+
+
+(*val AArch32_GenerateDebugExceptionsFrom : mword ty2 -> bool -> M bool*)
+
+val _ = Define `
+ ((AArch32_GenerateDebugExceptionsFrom:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) from secure=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (mask : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS (((from = EL0))))
+     ( sail2_state_monad$bindS(ELStateUsingAArch32 EL1 secure) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 :
+     bool) . 
+   if w__1 then sail2_state_monad$bindS
+     (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (w__2 : 1 bits) . 
+     let mask = w__2 in
+     AArch64_GenerateDebugExceptionsFrom from secure mask)
+   else sail2_state_monad$bindS
+     (sail2_state$or_boolS
+       (sail2_state$or_boolS
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGOSLSR_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))) ((DoubleLockStatus () ))) ((Halted () ))) (\ (w__8 :
+       bool) . 
+     if w__8 then sail2_state_monad$returnS F
+     else sail2_state_monad$bindS
+       (sail2_state_monad$undefined_boolS () ) (\ (enabled : bool) .  sail2_state_monad$bindS
+       (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (spd : 2 bits) . 
+       if (((((HaveEL EL3)) /\ secure))) then sail2_state_monad$bindS
+         (ELUsingAArch32 EL3) (\ (w__9 : bool) .  sail2_state_monad$bindS
+         (if w__9 then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS SDCR_ref  : ( 32 words$word) M) (\ (w__10 : 32 bits) . 
+            sail2_state_monad$returnS ((slice w__10 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)))
+          else sail2_state_monad$bindS
+            (sail2_state_monad$read_regS MDCR_EL3_ref  : ( 32 words$word) M) (\ (w__11 : 32 bits) . 
+            sail2_state_monad$returnS ((slice w__11 (( 14 : int):ii) (( 2 : int):ii)  :  2 words$word)))) (\ (w__12 :  2 words$word) . 
+         let spd = w__12 in sail2_state_monad$bindS
+         (if ((((vec_of_bits [access_vec_dec spd (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+            let (enabled : bool) =
+              ((vec_of_bits [access_vec_dec spd (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+            sail2_state_monad$returnS enabled
+          else AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled () ) (\ (enabled : bool) . 
+         if (((from = EL0))) then
+           sail2_state$or_boolS (sail2_state_monad$returnS enabled)
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS SDER_ref  : ( 32 words$word) M) (\ (w__14 : 32 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))
+         else sail2_state_monad$returnS enabled)))
+       else
+         let (enabled : bool) = (from <> EL2) in
+         sail2_state_monad$returnS enabled)))))))`;
+
+
+(*val AArch32_GenerateDebugExceptions : unit -> M bool*)
+
+val _ = Define `
+ ((AArch32_GenerateDebugExceptions:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS
+   (IsSecure () ) (\ (w__1 : bool) .  AArch32_GenerateDebugExceptionsFrom w__0.ProcState_EL w__1))))`;
+
+
+(*val DebugExceptionReturnSS : mword ty32 -> M (mword ty1)*)
+
+val _ = Define `
+ ((DebugExceptionReturnSS:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr=  (sail2_state_monad$bindS
+   (sail2_state$or_boolS (sail2_state$or_boolS ((Halted () )) ((Restarting () )))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$returnS (((w__3.ProcState_EL <> EL0)))))) (\ (w__4 :
+     bool) .  sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__4 "((Halted() || Restarting()) || ((PSTATE).EL != EL0))")
+   (let (SS_bit : 1 bits) = ((vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (ELd : 2 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M) (\ (mask : 1 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (enabled_at_dest : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (secure : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (dest : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (enabled_at_source : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS MDSCR_EL1_ref  : ( 32 words$word) M) (\ (w__5 : 32 bits) . 
+   if ((((vec_of_bits [access_vec_dec w__5 (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+     (Restarting () ) (\ (w__6 : bool) .  sail2_state_monad$bindS
+     (if w__6 then sail2_state_monad$returnS F
+      else sail2_state_monad$bindS
+        (UsingAArch32 () ) (\ (w__7 : bool) . 
+        if w__7 then AArch32_GenerateDebugExceptions () 
+        else AArch64_GenerateDebugExceptions () )) (\ (enabled_at_source : bool) .  sail2_state_monad$bindS
+     (IllegalExceptionReturn spsr) (\ (w__10 : bool) .  sail2_state_monad$bindS
+     (if w__10 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+        let (dest : 2 bits) = (w__11.ProcState_EL) in
+        sail2_state_monad$returnS dest)
+      else sail2_state_monad$bindS
+        (ELFromSPSR spsr  : ((bool #  2 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+        let valid_name = tup__0 in
+        let dest = tup__1 in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS valid_name "valid") (sail2_state_monad$returnS dest))) (\ (dest : 2 bits) .  sail2_state_monad$bindS
+     (sail2_state$or_boolS ((IsSecureBelowEL3 () )) (sail2_state_monad$returnS (((dest = EL3))))) (\ (w__13 : bool) . 
+     let secure = w__13 in sail2_state_monad$bindS
+     (ELUsingAArch32 dest) (\ (w__14 : bool) .  sail2_state_monad$bindS
+     (if w__14 then AArch32_GenerateDebugExceptionsFrom dest secure
+      else
+        let mask = ((vec_of_bits [access_vec_dec spsr (( 9 : int):ii)]  :  1 words$word)) in
+        AArch64_GenerateDebugExceptionsFrom dest secure mask) (\ (enabled_at_dest : bool) .  sail2_state_monad$bindS
+     (DebugTargetFrom secure  : ( 2 words$word) M) (\ (w__17 : 2 bits) . 
+     let ELd = w__17 in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS ( sail2_state_monad$bindS(ELUsingAArch32 ELd) (\ (w__18 : bool) .  sail2_state_monad$returnS ((~ w__18))))
+          (sail2_state_monad$returnS ((~ enabled_at_source)))) (sail2_state_monad$returnS enabled_at_dest)) (\ (w__20 : bool) . 
+     let (SS_bit : 1 bits) =
+       (if w__20 then (vec_of_bits [access_vec_dec spsr (( 21 : int):ii)]  :  1 words$word)
+       else SS_bit) in
+     sail2_state_monad$returnS SS_bit)))))))))
+   else sail2_state_monad$returnS SS_bit))))))))))))`;
+
+
+(*val SetPSTATEFromPSR : mword ty32 -> M unit*)
+
+val _ = Define `
+ ((SetPSTATEFromPSR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr__arg=
+    (let spsr = spsr__arg in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS
+   (DebugExceptionReturnSS spsr  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_SS := w__1|>))
+   (IllegalExceptionReturn spsr)) (\ (w__2 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__2 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_IL := ((vec_of_bits [B1]  :  1 words$word))|>))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) .  sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__4 with<| ProcState_IL := ((vec_of_bits [access_vec_dec spsr (( 20 : int):ii)]  :  1 words$word))|>))
+      (if ((((vec_of_bits [access_vec_dec spsr (( 4 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+        AArch32_WriteMode ((slice spsr (( 0 : int):ii) (( 5 : int):ii)  :  5 words$word))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_nRW := ((vec_of_bits [B0]  :  1 words$word))|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_EL := ((slice spsr (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word))|>))
+        (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . 
+        sail2_state_monad$write_regS
+          PSTATE_ref
+          (w__7 with<| ProcState_SP := ((vec_of_bits [access_vec_dec spsr (( 0 : int):ii)]  :  1 words$word))|>)))))))
+   (sail2_state$and_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . 
+      sail2_state_monad$returnS (((w__8.ProcState_IL = (vec_of_bits [B1]  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . 
+      sail2_state_monad$returnS (((w__9.ProcState_nRW = (vec_of_bits [B1]  :  1 words$word)))))))) (\ (w__10 : bool) .  sail2_state_monad$bindS
+   (if w__10 then sail2_state_monad$bindS
+      (ConstrainUnpredictableBool Unpredictable_ILZEROT) (\ (w__11 : bool) . 
+      let (spsr :  32 words$word) =
+        (if w__11 then
+          (set_slice (( 32 : int):ii) (( 1 : int):ii) spsr (( 5 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)
+        else spsr) in
+      sail2_state_monad$returnS spsr)
+    else sail2_state_monad$returnS spsr) (\ (spsr :  32 words$word) . 
+   let split_vec = ((slice spsr (( 28 : int):ii) (( 4 : int):ii)  :  4 words$word)) in
+   let (tup__0, tup__1, tup__2, tup__3) =
+     ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+      (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_N := tup__0|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_Z := tup__1|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_C := tup__2|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_V := tup__3|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if (((w__16.ProcState_nRW = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__17 with<| ProcState_Q := ((vec_of_bits [access_vec_dec spsr (( 27 : int):ii)]  :  1 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS
+      (RestoredITBits spsr  : ( 8 words$word) M) (\ (w__19 : 8 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_IT := w__19|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_GE := ((slice spsr (( 16 : int):ii) (( 4 : int):ii)  :  4 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__21 : ProcState) .  sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__21 with<| ProcState_E := ((vec_of_bits [access_vec_dec spsr (( 9 : int):ii)]  :  1 words$word))|>))
+      (let split_vec = ((slice spsr (( 6 : int):ii) (( 3 : int):ii)  :  3 words$word)) in
+      let (tup__0, tup__1, tup__2) =
+        ((subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_A := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_I := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_F := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__25 with<| ProcState_T := ((vec_of_bits [access_vec_dec spsr (( 5 : int):ii)]  :  1 words$word))|>)))))))))))
+    else
+      let split_vec = ((slice spsr (( 6 : int):ii) (( 4 : int):ii)  :  4 words$word)) in
+      let (tup__0, tup__1, tup__2, tup__3) =
+        ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_D := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_A := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_I := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_F := tup__3|>))))))
+   (if ((HavePANExt () )) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__30 : ProcState) . 
+      sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__30 with<| ProcState_PAN := ((vec_of_bits [access_vec_dec spsr (( 22 : int):ii)]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () ))
+   (if ((HaveUAOExt () )) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PSTATE_ref) (\ (w__31 : ProcState) . 
+     sail2_state_monad$write_regS
+       PSTATE_ref
+       (w__31 with<| ProcState_UAO := ((vec_of_bits [access_vec_dec spsr (( 23 : int):ii)]  :  1 words$word))|>))
+   else sail2_state_monad$returnS () )))))))))))))`;
+
+
+(*val DRPSInstruction : unit -> M unit*)
+
+val _ = Define `
+ ((DRPSInstruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () )))
+        ( sail2_state_monad$bindS(aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+     ((ConstrainUnpredictableBool Unpredictable_IESBinDebug))) (\ (w__3 : bool) . 
+   let (_ : unit) =
+     (if w__3 then ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All
+     else () ) in sail2_state_monad$bindS
+   (aget_SPSR ()   : ( 32 words$word) M) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (SetPSTATEFromPSR w__4)
+   (UsingAArch32 () )) (\ (w__5 : bool) .  sail2_state_monad$seqS
+   (if w__5 then sail2_state_monad$bindS
+      (undefined_bitvector (( 13 : int):ii)  : ( 13 words$word) M) (\ (w__6 : 13 bits) . 
+      let split_vec = w__6 in
+      let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8, tup__9) =
+        ((subrange_vec_dec split_vec (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 10 : int):ii) (( 10 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 7 : int):ii) (( 4 : int):ii)  :  4 words$word),
+         (subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_N := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_Z := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_C := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_V := tup__3|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_Q := tup__4|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_GE := tup__5|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_SS := tup__6|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_A := tup__7|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_I := tup__8|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_F := tup__9|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
+        PSTATE_ref
+        (w__17 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_T := ((vec_of_bits [B1]  :  1 words$word))|>))
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__19 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DLR_ref w__19)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__20 : 32 bits) . 
+      sail2_state_monad$write_regS DSPSR_ref w__20)))))))))))))))
+    else sail2_state_monad$bindS
+      (undefined_bitvector (( 9 : int):ii)  : ( 9 words$word) M) (\ (w__21 : 9 bits) . 
+      let split_vec = w__21 in
+      let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8) =
+        ((subrange_vec_dec split_vec (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word),
+         (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_N := tup__0|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_Z := tup__1|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_C := tup__2|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_V := tup__3|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__26 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_SS := tup__4|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_D := tup__5|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_A := tup__6|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_I := tup__7|>))
+      (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__30 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS PSTATE_ref (w__30 with<| ProcState_F := tup__8|>))
+      (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__31 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS DLR_EL0_ref w__31)
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__32 : 32 bits) . 
+      sail2_state_monad$write_regS DSPSR_EL0_ref w__32)))))))))))))
+   (UpdateEDSCRFields () ))))))`;
+
+
+(*val aarch64_branch_unconditional_dret : unit -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_unconditional_dret:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (DRPSInstruction () ))`;
+
+
+(*val AArch64_ExceptionReturn : mword ty64 -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((AArch64_ExceptionReturn:(64)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) new_pc__arg spsr=
+    (let new_pc = new_pc__arg in
+   let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (iesb_req : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () )))
+     ( sail2_state_monad$bindS(aget_SCTLR__1 ()   : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 21 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__1 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if w__1 then
+      let (_ : unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in
+      let iesb_req = T in
+      TakeUnmaskedPhysicalSErrorInterrupts iesb_req
+    else sail2_state_monad$returnS () )
+   (SetPSTATEFromPSR spsr))
+   (ClearExclusiveLocal ((ProcessorID () ))))
+   (SendEventLocal () ))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) .  sail2_state_monad$bindS
+   (if (((w__2.ProcState_IL = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$bindS
+      (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
+      let new_pc = ((set_slice (( 64 : int):ii) (( 32 : int):ii) new_pc (( 32 : int):ii) w__3  :  64 words$word)) in sail2_state_monad$bindS
+      (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (w__4 :  2 words$word) . 
+      let (new_pc :  64 words$word) = ((set_slice (( 64 : int):ii) (( 2 : int):ii) new_pc (( 0 : int):ii) w__4  :  64 words$word)) in
+      sail2_state_monad$returnS new_pc))
+    else sail2_state_monad$bindS
+      (UsingAArch32 () ) (\ (w__5 : bool) . 
+      if w__5 then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+        let (new_pc :  64 words$word) =
+          (if (((w__6.ProcState_T = (vec_of_bits [B0]  :  1 words$word)))) then
+            (set_slice (( 64 : int):ii) (( 1 : int):ii) new_pc (( 0 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)
+          else
+            (set_slice (( 64 : int):ii) (( 2 : int):ii) new_pc (( 0 : int):ii) (vec_of_bits [B0;B0]  :  2 words$word)  :  64 words$word)) in
+        sail2_state_monad$returnS new_pc)
+      else (AArch64_BranchAddr new_pc  : ( 64 words$word) M))) (\ (new_pc :  64 words$word) .  sail2_state_monad$bindS
+   (UsingAArch32 () ) (\ (w__8 : bool) . 
+   if w__8 then BranchTo ((slice new_pc (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)) BranchType_UNKNOWN
+   else BranchToAddr new_pc BranchType_ERET)))))))`;
+
+
+(*val aarch64_branch_unconditional_eret : bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_branch_unconditional_eret:bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pac use_key_a=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (AArch64_CheckForERetTrap pac use_key_a)
+   (aget_ELR__1 ()   : ( 64 words$word) M)) (\ (target : 64 bits) .  sail2_state_monad$bindS
+   (if pac then
+      if use_key_a then sail2_state_monad$bindS
+        (aget_ELR__1 ()   : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+        (AuthIA w__0 w__1  : ( 64 words$word) M)))
+      else sail2_state_monad$bindS
+        (aget_ELR__1 ()   : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+        (AuthIB w__3 w__4  : ( 64 words$word) M)))
+    else sail2_state_monad$returnS target) (\ (target : 64 bits) .  sail2_state_monad$bindS
+   (aget_SPSR ()   : ( 32 words$word) M) (\ (w__6 :  32 words$word) . 
+   AArch64_ExceptionReturn target w__6)))))`;
+
+
+(*val AArch32_GeneralExceptionsToAArch64 : unit -> M bool*)
+
+val _ = Define `
+ ((AArch32_GeneralExceptionsToAArch64:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$or_boolS
+     (sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL0)))))
+        ( sail2_state_monad$bindS(ELUsingAArch32 EL1) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+              ( sail2_state_monad$bindS(IsSecure () ) (\ (w__3 : bool) .  sail2_state_monad$returnS ((~ w__3)))))
+           ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__5 : bool) .  sail2_state_monad$returnS ((~ w__5)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))))`;
+
+
+(*val AArch32_EnterHypMode : ExceptionRecord -> mword ty32 -> ii -> M unit*)
+
+val _ = Define `
+ ((AArch32_EnterHypMode:ExceptionRecord ->(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception preferred_exception_return vect_offset=
+    (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+     ((ELUsingAArch32 EL2))) (\ (w__3 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS w__3 "((HaveEL(EL2) && !(IsSecure())) && ELUsingAArch32(EL2))")
+   (GetPSRFromPSTATE ()   : ( 32 words$word) M)) (\ (spsr : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if ((~ ((((((exception.ExceptionRecord_typ = Exception_IRQ))) \/ (((exception.ExceptionRecord_typ = Exception_FIQ)))))))) then
+      AArch32_ReportHypEntry exception
+    else sail2_state_monad$returnS () )
+   (AArch32_WriteMode M32_Hyp))
+   (aset_SPSR spsr))
+   (sail2_state_monad$write_regS ELR_hyp_ref preferred_exception_return))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HSCTLR_ref  : ( 32 words$word) M) (\ (w__5 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__4 with<| ProcState_T := ((vec_of_bits [access_vec_dec w__5 (( 30 : int):ii)]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_SS := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))
+     ( sail2_state_monad$bindS(aget_SCR_GEN ()   : ( 32 words$word) M) (\ (w__7 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 3 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__8 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__8 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_A := ((vec_of_bits [B1]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () )
+   (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))
+     ( sail2_state_monad$bindS(aget_SCR_GEN ()   : ( 32 words$word) M) (\ (w__10 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__11 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__11 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_I := ((vec_of_bits [B1]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () )
+   (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))
+     ( sail2_state_monad$bindS(aget_SCR_GEN ()   : ( 32 words$word) M) (\ (w__13 :  32 words$word) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 2 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__14 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__14 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . 
+      sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_F := ((vec_of_bits [B1]  :  1 words$word))|>))
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HSCTLR_ref  : ( 32 words$word) M) (\ (w__17 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__16 with<| ProcState_E := ((vec_of_bits [access_vec_dec w__17 (( 25 : int):ii)]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_IL := ((vec_of_bits [B0]  :  1 words$word))|>))
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     PSTATE_ref
+     (w__19 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))|>))
+   (sail2_state_monad$read_regS HVBAR_ref  : ( 32 words$word) M)) (\ (w__20 : 32 bits) .  sail2_state_monad$seqS
+   (BranchTo
+     ((concat_vec ((slice w__20 (( 5 : int):ii) (( 27 : int):ii)  :  27 words$word))
+         ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) vect_offset (( 0 : int):ii)  :  5 words$word))
+        :  32 words$word)) BranchType_UNKNOWN)
+   (EndOfInstruction () ))))))))))))))))`;
+
+
+(*val AArch32_TakeUndefInstrException__0 : unit -> M unit*)
+
+(*val AArch32_TakeUndefInstrException__1 : ExceptionRecord -> M unit*)
+
+val _ = Define `
+ ((AArch32_TakeUndefInstrException__1:ExceptionRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL0))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_ref  : ( 32 words$word) M) (\ (w__4 : 32 bits) . 
+      sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (route_to_hyp : bool) .  sail2_state_monad$bindS
+   (ThisInstrAddr (( 32 : int):ii) ()   : ( 32 words$word) M) (\ (preferred_exception_return : 32 bits) . 
+   let (vect_offset : ii) = ((( 4 : int):ii)) in sail2_state_monad$bindS
+   (CurrentInstrSet () ) (\ (w__5 : InstrSet) . 
+   let (lr_offset : ii) = (if (((w__5 = InstrSet_A32))) then (( 4 : int):ii) else (( 2 : int):ii)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . 
+   if (((w__6.ProcState_EL = EL2))) then
+     AArch32_EnterHypMode exception preferred_exception_return vect_offset
+   else if route_to_hyp then AArch32_EnterHypMode exception preferred_exception_return (( 20 : int):ii)
+   else AArch32_EnterMode M32_Undef preferred_exception_return lr_offset vect_offset))))))`;
+
+
+val _ = Define `
+ ((AArch32_TakeUndefInstrException__0:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (ExceptionSyndrome Exception_Uncategorized) (\ (exception : ExceptionRecord) . 
+   AArch32_TakeUndefInstrException__1 exception)))`;
+
+
+(*val UnallocatedEncoding : unit -> M unit*)
+
+val _ = Define `
+ ((UnallocatedEncoding:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS ((UsingAArch32 () )) ((AArch32_ExecutingCP10or11Instr () ))) (\ (w__2 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__2 then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPEXC_ref  : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
+      sail2_state_monad$write_regS
+        FPEXC_ref
+        ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__3 (( 29 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word)))
+    else sail2_state_monad$returnS () )
+   (sail2_state$and_boolS ((UsingAArch32 () ))
+     ( sail2_state_monad$bindS(AArch32_GeneralExceptionsToAArch64 () ) (\ (w__5 : bool) .  sail2_state_monad$returnS ((~ w__5)))))) (\ (w__6 :
+     bool) . 
+   if w__6 then AArch32_TakeUndefInstrException__0 () 
+   else AArch64_UndefinedFault () ))))`;
+
+
+(*val aarch64_system_exceptions_runtime_hvc : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_exceptions_runtime_hvc:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm=  (sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL0))))))
+     (sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) .  sail2_state_monad$returnS (((w__2.ProcState_EL = EL1)))))
+        ((IsSecure () )))) (\ (w__5 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if w__5 then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if ((HaveEL EL3)) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M) (\ (w__6 : 32 bits) . 
+      sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 8 : int):ii)]  :  1 words$word))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+      sail2_state_monad$returnS ((not_vec (vec_of_bits [access_vec_dec w__7 (( 29 : int):ii)]  :  1 words$word)  :  1 words$word))))) (\ (hvc_enable : 1
+     bits) . 
+   if (((hvc_enable = (vec_of_bits [B0]  :  1 words$word)))) then AArch64_UndefinedFault () 
+   else AArch64_CallHypervisor imm))))`;
+
+
+(*val system_exceptions_runtime_hvc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((system_exceptions_runtime_hvc_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (imm : 16 bits) = imm16 in
+   aarch64_system_exceptions_runtime_hvc imm)))`;
+
+
+(*val aarch64_memory_single_general_register : forall 'regsize. Size 'regsize => AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> itself 'regsize -> ii -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_general_register:AccType -> int -> ExtendType -> int -> MemOp -> int -> bool -> 'regsize itself -> int -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__40 extend_type m memop n postindex regsize shift signed t wback__arg=
+    (if (((l__40 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M) (\ (offset : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__4 : 8
+          bits) . 
+        let data = w__4 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__5 :
+             'regsize words$word) . 
+          aset_X t w__5)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__6 :
+             'regsize words$word) . 
+          aset_X t w__6))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () ))))))))))
+   else if (((l__40 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M) (\ (offset : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__12 : 16
+          bits) . 
+        let data = w__12 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__13 :
+             'regsize words$word) . 
+          aset_X t w__13)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () ))))))))))
+   else if (((l__40 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M) (\ (offset : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__20 : 32
+          bits) . 
+        let data = w__20 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__21 :
+             'regsize words$word) . 
+          aset_X t w__21)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__22 :
+             'regsize words$word) . 
+          aset_X t w__22))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () ))))))))))
+   else if (((l__40 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M) (\ (offset : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__28 : 64
+          bits) . 
+        let data = w__28 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__30 :
+             'regsize words$word) . 
+          aset_X t w__30))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () ))))))))))
+   else if (((l__40 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (ExtendReg (( 64 : int):ii) m extend_type shift  : ( 64 words$word) M) (\ (offset : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__36 : 128
+          bits) . 
+        let data = w__36 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__37 :
+             'regsize words$word) . 
+          aset_X t w__37)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__38 :
+             'regsize words$word) . 
+          aset_X t w__38))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () ))))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__40 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_single_general_immediate_unsigned : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_general_immediate_unsigned:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__35 memop n offset postindex regsize signed t wback__arg=
+    (if (((l__35 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__4 : 8
+          bits) . 
+        let data = w__4 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__5 :
+             'regsize words$word) . 
+          aset_X t w__5)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__6 :
+             'regsize words$word) . 
+          aset_X t w__6))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__35 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__12 : 16
+          bits) . 
+        let data = w__12 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__13 :
+             'regsize words$word) . 
+          aset_X t w__13)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__35 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__20 : 32
+          bits) . 
+        let data = w__20 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__21 :
+             'regsize words$word) . 
+          aset_X t w__21)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__22 :
+             'regsize words$word) . 
+          aset_X t w__22))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__35 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__28 : 64
+          bits) . 
+        let data = w__28 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__30 :
+             'regsize words$word) . 
+          aset_X t w__30))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__35 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__36 : 128
+          bits) . 
+        let data = w__36 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__37 :
+             'regsize words$word) . 
+          aset_X t w__37)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__38 :
+             'regsize words$word) . 
+          aset_X t w__38))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__35 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_single_general_immediate_signed_postidx : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_general_immediate_signed_postidx:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__30 memop n offset postindex regsize signed t wback__arg=
+    (if (((l__30 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__4 : 8
+          bits) . 
+        let data = w__4 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__5 :
+             'regsize words$word) . 
+          aset_X t w__5)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__6 :
+             'regsize words$word) . 
+          aset_X t w__6))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__30 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__12 : 16
+          bits) . 
+        let data = w__12 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__13 :
+             'regsize words$word) . 
+          aset_X t w__13)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__30 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__20 : 32
+          bits) . 
+        let data = w__20 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__21 :
+             'regsize words$word) . 
+          aset_X t w__21)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__22 :
+             'regsize words$word) . 
+          aset_X t w__22))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__30 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__28 : 64
+          bits) . 
+        let data = w__28 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__30 :
+             'regsize words$word) . 
+          aset_X t w__30))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__30 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__36 : 128
+          bits) . 
+        let data = w__36 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__37 :
+             'regsize words$word) . 
+          aset_X t w__37)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__38 :
+             'regsize words$word) . 
+          aset_X t w__38))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__30 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_single_general_immediate_signed_pac : ii -> mword ty64 -> ii -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_general_immediate_signed_pac:int ->(64)words$word -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n offset t use_key_a wback__arg=
+    (let wback = wback__arg in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+   let (wb_unknown : bool) = F in sail2_state_monad$bindS
+   (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+   (if ((((((wback /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+      let c = (ConstrainUnpredictable Unpredictable_WBOVERLAPLD) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_WBSUPPRESS))) \/ ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+      (case c of
+        Constraint_WBSUPPRESS =>
+         let (wback : bool) = F in
+         sail2_state_monad$returnS (wb_unknown, wback)
+      | Constraint_UNKNOWN =>
+         let (wb_unknown : bool) = T in
+         sail2_state_monad$returnS (wb_unknown, wback)
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (wb_unknown, wback))
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS (wb_unknown, wback))
+      )
+    else sail2_state_monad$returnS (wb_unknown, wback)) (\ varstup .  let ((wb_unknown : bool), (wback : bool)) = varstup in sail2_state_monad$bindS
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (if use_key_a then sail2_state_monad$bindS
+      (aget_X (( 64 : int):ii) (( 31 : int):ii)  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+      (AuthDA address w__2  : ( 64 words$word) M))
+    else sail2_state_monad$bindS
+      (aget_X (( 64 : int):ii) (( 31 : int):ii)  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+      (AuthDB address w__4  : ( 64 words$word) M))) (\ (address : 64 bits) . 
+   let address = ((add_vec address offset  :  64 words$word)) in sail2_state_monad$bindS
+   (aget_Mem address (( 8 : int):ii) AccType_NORMAL  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+   let data = w__6 in sail2_state_monad$seqS
+   (aset_X t data)
+   (if wback then sail2_state_monad$bindS
+     (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+     if (((n = (( 31 : int):ii)))) then aset_SP address
+     else aset_X n address)
+   else sail2_state_monad$returnS () ))))))))))`;
+
+
+(*val aarch64_memory_single_general_immediate_signed_offset_unpriv : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_general_immediate_signed_offset_unpriv:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__25 memop n offset postindex regsize signed t wback__arg=
+    (if (((l__25 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__4 : 8
+          bits) . 
+        let data = w__4 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__5 :
+             'regsize words$word) . 
+          aset_X t w__5)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__6 :
+             'regsize words$word) . 
+          aset_X t w__6))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__25 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__12 : 16
+          bits) . 
+        let data = w__12 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__13 :
+             'regsize words$word) . 
+          aset_X t w__13)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__25 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__20 : 32
+          bits) . 
+        let data = w__20 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__21 :
+             'regsize words$word) . 
+          aset_X t w__21)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__22 :
+             'regsize words$word) . 
+          aset_X t w__22))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__25 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__28 : 64
+          bits) . 
+        let data = w__28 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__30 :
+             'regsize words$word) . 
+          aset_X t w__30))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__25 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__36 : 128
+          bits) . 
+        let data = w__36 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__37 :
+             'regsize words$word) . 
+          aset_X t w__37)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__38 :
+             'regsize words$word) . 
+          aset_X t w__38))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__25 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_single_general_immediate_signed_offset_normal : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_single_general_immediate_signed_offset_normal:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__20 memop n offset postindex regsize signed t wback__arg=
+    (if (((l__20 = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype  : ( 8 words$word) M) (\ (w__4 : 8
+          bits) . 
+        let data = w__4 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__5 :
+             'regsize words$word) . 
+          aset_X t w__5)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__6 :
+             'regsize words$word) . 
+          aset_X t w__6))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__20 = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype  : ( 16 words$word) M) (\ (w__12 : 16
+          bits) . 
+        let data = w__12 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__13 :
+             'regsize words$word) . 
+          aset_X t w__13)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__20 = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype  : ( 32 words$word) M) (\ (w__20 : 32
+          bits) . 
+        let data = w__20 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__21 :
+             'regsize words$word) . 
+          aset_X t w__21)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__22 :
+             'regsize words$word) . 
+          aset_X t w__22))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__20 = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype  : ( 64 words$word) M) (\ (w__28 : 64
+          bits) . 
+        let data = w__28 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__30 :
+             'regsize words$word) . 
+          aset_X t w__30))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else if (((l__20 = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (let wback = wback__arg in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (wb_unknown : bool) = F in
+     let (rt_unknown : bool) = F in sail2_state_monad$bindS
+     (undefined_Constraint () ) (\ (c : Constraint) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS wback) (\ (wback : bool) .  sail2_state_monad$bindS
+     (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then
+        let c = Constraint_NONE in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+        (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS
+        (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () 
+         else sail2_state_monad$returnS () )
+        (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+     let (address : 64 bits) =
+       (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+       else address) in sail2_state_monad$seqS
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data)
+     | MemOp_LOAD => sail2_state_monad$bindS
+        (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype  : ( 128 words$word) M) (\ (w__36 : 128
+          bits) . 
+        let data = w__36 in
+        if signed then sail2_state_monad$bindS
+          (SignExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__37 :
+             'regsize words$word) . 
+          aset_X t w__37)
+        else sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__38 :
+             'regsize words$word) . 
+          aset_X t w__38))
+     | MemOp_PREFETCH =>
+        Prefetch address
+          ((GetSlice_int ((make_the_value (( 5 : int):ii)  :  5 itself)) t (( 0 : int):ii)  :  5 words$word))
+     )
+     (if wback then sail2_state_monad$bindS
+       (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+        else
+          let (address : 64 bits) =
+            (if postindex then (add_vec address offset  :  64 words$word)
+            else address) in
+          sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+       if (((n = (( 31 : int):ii)))) then aset_SP address
+       else aset_X n address)
+     else sail2_state_monad$returnS () )))))))))
+   else
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((l__20 / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val aarch64_memory_pair_simdfp_postidx : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_pair_simdfp_postidx:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex t t2 wback=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (CheckFPAdvSIMDEnabled64 () ))
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . 
+   let (rt_unknown : bool) = F in sail2_state_monad$bindS
+   (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then
+      let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+      (case c of
+        Constraint_UNKNOWN => sail2_state_monad$returnS T
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown)
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown)
+      )
+    else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+   let (address : 64 bits) =
+     (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+     else address) in sail2_state_monad$seqS
+   (case memop of
+     MemOp_STORE => sail2_state_monad$bindS
+      (aget_V ((int_of_num (words$word_len data1))) t  : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . 
+      let data1 = w__2 in sail2_state_monad$bindS
+      (aget_V ((int_of_num (words$word_len data1))) t2  : ( 'datasize words$word) M) (\ (w__3 : 'datasize bits) . 
+      let data2 = w__3 in sail2_state_monad$seqS
+      (aset_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype data1)
+      (aset_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype data2)))
+   | MemOp_LOAD => sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__4 : 'datasize
+        bits) . 
+      let data1 = w__4 in sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__5 : 'datasize
+        bits) . 
+      let data2 = w__5 in sail2_state_monad$bindS
+      (if rt_unknown then sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__6 : 'datasize
+           bits) . 
+         let data1 = w__6 in sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__7 : 'datasize
+           bits) . 
+         let (data2 : 'datasize bits) = w__7 in
+         sail2_state_monad$returnS (data1, data2)))
+       else sail2_state_monad$returnS (data1, data2)) (\ varstup .  let ((data1 : 'datasize bits), (data2 : 'datasize
+        bits)) = varstup in sail2_state_monad$seqS
+      (aset_V t data1) (aset_V t2 data2))))
+   )
+   (if wback then
+     let (address : 64 bits) =
+       (if postindex then (add_vec address offset  :  64 words$word)
+       else address) in
+     if (((n = (( 31 : int):ii)))) then aset_SP address
+     else aset_X n address
+   else sail2_state_monad$returnS () ))))))))`;
+
+
+(*val aarch64_memory_pair_simdfp_noalloc : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_pair_simdfp_noalloc:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex t t2 wback=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (CheckFPAdvSIMDEnabled64 () ))
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . 
+   let (rt_unknown : bool) = F in sail2_state_monad$bindS
+   (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then
+      let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+      (case c of
+        Constraint_UNKNOWN => sail2_state_monad$returnS T
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown)
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown)
+      )
+    else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+   let (address : 64 bits) =
+     (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+     else address) in sail2_state_monad$seqS
+   (case memop of
+     MemOp_STORE => sail2_state_monad$bindS
+      (aget_V ((int_of_num (words$word_len data1))) t  : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . 
+      let data1 = w__2 in sail2_state_monad$bindS
+      (aget_V ((int_of_num (words$word_len data1))) t2  : ( 'datasize words$word) M) (\ (w__3 : 'datasize bits) . 
+      let data2 = w__3 in sail2_state_monad$seqS
+      (aset_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype data1)
+      (aset_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype data2)))
+   | MemOp_LOAD => sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__4 : 'datasize
+        bits) . 
+      let data1 = w__4 in sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__5 : 'datasize
+        bits) . 
+      let data2 = w__5 in sail2_state_monad$bindS
+      (if rt_unknown then sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__6 : 'datasize
+           bits) . 
+         let data1 = w__6 in sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__7 : 'datasize
+           bits) . 
+         let (data2 : 'datasize bits) = w__7 in
+         sail2_state_monad$returnS (data1, data2)))
+       else sail2_state_monad$returnS (data1, data2)) (\ varstup .  let ((data1 : 'datasize bits), (data2 : 'datasize
+        bits)) = varstup in sail2_state_monad$seqS
+      (aset_V t data1) (aset_V t2 data2))))
+   )
+   (if wback then
+     let (address : 64 bits) =
+       (if postindex then (add_vec address offset  :  64 words$word)
+       else address) in
+     if (((n = (( 31 : int):ii)))) then aset_SP address
+     else aset_X n address
+   else sail2_state_monad$returnS () ))))))))`;
+
+
+(*val aarch64_memory_pair_general_postidx : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> bool -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_pair_general_postidx:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex signed t t2 wback__arg=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (let wback = wback__arg in sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . 
+   let (rt_unknown : bool) = F in
+   let (wb_unknown : bool) = F in sail2_state_monad$bindS
+   (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ ((((((t = n))) \/ (((t2 = n))))))))) /\ (((n <> (( 31 : int):ii))))))) then
+      let (c : Constraint) = (ConstrainUnpredictable Unpredictable_WBOVERLAPLD) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_WBSUPPRESS))) \/ ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+      (case c of
+        Constraint_WBSUPPRESS =>
+         let (wback : bool) = F in
+         sail2_state_monad$returnS (wb_unknown, wback)
+      | Constraint_UNKNOWN =>
+         let (wb_unknown : bool) = T in
+         sail2_state_monad$returnS (wb_unknown, wback)
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (wb_unknown, wback))
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS (wb_unknown, wback))
+      )
+    else sail2_state_monad$returnS (wb_unknown, wback)) (\ varstup .  let ((wb_unknown : bool), (wback : bool)) = varstup in sail2_state_monad$bindS
+   (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ ((((((t = n))) \/ (((t2 = n))))))))) /\ (((n <> (( 31 : int):ii))))))) then
+      let (c : Constraint) = (ConstrainUnpredictable Unpredictable_WBOVERLAPST) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_NONE))) \/ ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+      (case c of
+        Constraint_NONE => sail2_state_monad$returnS F
+      | Constraint_UNKNOWN => sail2_state_monad$returnS T
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown)
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown)
+      )
+    else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+   (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then
+      let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+      (case c of
+        Constraint_UNKNOWN => sail2_state_monad$returnS T
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown)
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown)
+      )
+    else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+   let (address : 64 bits) =
+     (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+     else address) in sail2_state_monad$seqS
+   (case memop of
+     MemOp_STORE => sail2_state_monad$bindS
+      (if (((rt_unknown /\ (((t = n)))))) then
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M)
+       else (aget_X ((int_of_num (words$word_len data1))) t  : ( 'datasize words$word) M)) (\ (data1 : 'datasize bits) .  sail2_state_monad$bindS
+      (if (((rt_unknown /\ (((t2 = n)))))) then
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M)
+       else (aget_X ((int_of_num (words$word_len data1))) t2  : ( 'datasize words$word) M)) (\ (data2 : 'datasize bits) .  sail2_state_monad$seqS
+      (aset_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype data1)
+      (aset_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype data2)))
+   | MemOp_LOAD => sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__6 : 'datasize
+        bits) . 
+      let data1 = w__6 in sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__7 : 'datasize
+        bits) . 
+      let data2 = w__7 in sail2_state_monad$bindS
+      (if rt_unknown then sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__8 : 'datasize
+           bits) . 
+         let data1 = w__8 in sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__9 : 'datasize
+           bits) . 
+         let (data2 : 'datasize bits) = w__9 in
+         sail2_state_monad$returnS (data1, data2)))
+       else sail2_state_monad$returnS (data1, data2)) (\ varstup .  let ((data1 : 'datasize bits), (data2 : 'datasize
+        bits)) = varstup in
+      if signed then sail2_state_monad$bindS
+        (SignExtend__0 data1 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__10 :
+           64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+        (aset_X t w__10)
+        (SignExtend__0 data2 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M)) (\ (w__11 :
+           64 words$word) . 
+        aset_X t2 w__11))
+      else sail2_state_monad$seqS (aset_X t data1) (aset_X t2 data2))))
+   )
+   (if wback then sail2_state_monad$bindS
+     (if wb_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else
+        let (address : 64 bits) =
+          (if postindex then (add_vec address offset  :  64 words$word)
+          else address) in
+        sail2_state_monad$returnS address) (\ (address : 64 bits) . 
+     if (((n = (( 31 : int):ii)))) then aset_SP address
+     else aset_X n address)
+   else sail2_state_monad$returnS () )))))))))))`;
+
+
+(*val aarch64_memory_pair_general_noalloc : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_pair_general_noalloc:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex t t2 wback=
+    (let datasize = (size_itself_int datasize) in
+   let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "datasize constraint")
+   (sail2_state_monad$assert_expS T "dbytes constraint"))
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector datasize  : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) .  sail2_state_monad$bindS
+   (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . 
+   let (rt_unknown : bool) = F in sail2_state_monad$bindS
+   (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then
+      let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS
+      (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+      (case c of
+        Constraint_UNKNOWN => sail2_state_monad$returnS T
+      | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown)
+      | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown)
+      )
+    else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+   (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+    else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) . 
+   let (address : 64 bits) =
+     (if ((~ postindex)) then (add_vec address offset  :  64 words$word)
+     else address) in sail2_state_monad$seqS
+   (case memop of
+     MemOp_STORE => sail2_state_monad$bindS
+      (if (((rt_unknown /\ (((t = n)))))) then
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M)
+       else (aget_X ((int_of_num (words$word_len data1))) t  : ( 'datasize words$word) M)) (\ (data1 : 'datasize bits) .  sail2_state_monad$bindS
+      (if (((rt_unknown /\ (((t2 = n)))))) then
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M)
+       else (aget_X ((int_of_num (words$word_len data1))) t2  : ( 'datasize words$word) M)) (\ (data2 : 'datasize bits) .  sail2_state_monad$seqS
+      (aset_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype data1)
+      (aset_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype data2)))
+   | MemOp_LOAD => sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__6 : 'datasize
+        bits) . 
+      let data1 = w__6 in sail2_state_monad$bindS
+      (aget_Mem ((add_vec_int address dbytes  :  64 words$word)) dbytes acctype  : ( 'datasize words$word) M) (\ (w__7 : 'datasize
+        bits) . 
+      let data2 = w__7 in sail2_state_monad$bindS
+      (if rt_unknown then sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__8 : 'datasize
+           bits) . 
+         let data1 = w__8 in sail2_state_monad$bindS
+         (undefined_bitvector ((int_of_num (words$word_len data1)))  : ( 'datasize words$word) M) (\ (w__9 : 'datasize
+           bits) . 
+         let (data2 : 'datasize bits) = w__9 in
+         sail2_state_monad$returnS (data1, data2)))
+       else sail2_state_monad$returnS (data1, data2)) (\ varstup .  let ((data1 : 'datasize bits), (data2 : 'datasize
+        bits)) = varstup in sail2_state_monad$seqS
+      (aset_X t data1) (aset_X t2 data2))))
+   )
+   (if wback then
+     let (address : 64 bits) =
+       (if postindex then (add_vec address offset  :  64 words$word)
+       else address) in
+     if (((n = (( 31 : int):ii)))) then aset_SP address
+     else aset_X n address
+   else sail2_state_monad$returnS () ))))))))`;
+
+
+(*val aarch64_memory_exclusive_single : forall 'datasize  'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> integer -> MemOp -> ii -> bool -> itself 'regsize -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_exclusive_single:AccType -> 'datasize itself -> int -> MemOp -> int -> bool -> 'regsize itself -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype p_1 elsize memop n pair regsize s t t2=
+    (if (((((size_itself_int p_1)) = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 8 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t  : ( 4 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t2  : ( 4 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__4 : bool) . 
+           let (data : 8 bits) =
+             (if w__4 then (concat_vec el1 el2  :  8 words$word)
+             else (concat_vec el2 el1  :  8 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__6 : bool) .  sail2_state_monad$bindS
+        (if w__6 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__8 :
+           32 words$word) . 
+        aset_X s w__8))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__9 : 32 bits) . 
+            aset_X t w__9)
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__10 : FaultRecord) . 
+               AArch64_Abort address w__10)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__11 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__11)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__12 :
+               64 words$word) . 
+            aset_X t2 w__12)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 8 words$word) M) (\ (w__13 : 8 bits) . 
+          let data = w__13 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 16 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X v t  : ( 8 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len el1))) t2  : ( 8 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__19 : bool) . 
+           let (data : 16 bits) =
+             (if w__19 then (concat_vec el1 el2  :  16 words$word)
+             else (concat_vec el2 el1  :  16 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__21 : bool) .  sail2_state_monad$bindS
+        (if w__21 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__23 :
+           32 words$word) . 
+        aset_X s w__23))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__24 : 32 bits) . 
+            aset_X t w__24)
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__25 : FaultRecord) . 
+               AArch64_Abort address w__25)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__26 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__26)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__27 :
+               64 words$word) . 
+            aset_X t2 w__27)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 16 words$word) M) (\ (w__28 : 16 bits) . 
+          let data = w__28 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 32 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X v t  : ( 16 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len el1))) t2  : ( 16 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__34 : bool) . 
+           let (data : 32 bits) =
+             (if w__34 then (concat_vec el1 el2  :  32 words$word)
+             else (concat_vec el2 el1  :  32 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__36 : bool) .  sail2_state_monad$bindS
+        (if w__36 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__38 :
+           32 words$word) . 
+        aset_X s w__38))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__39 : 32 bits) . 
+            aset_X t w__39)
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__40 : FaultRecord) . 
+               AArch64_Abort address w__40)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__41 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__41)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__42 :
+               64 words$word) . 
+            aset_X t2 w__42)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 32 words$word) M) (\ (w__43 : 32 bits) . 
+          let data = w__43 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__44 :
+             'regsize words$word) . 
+          aset_X t w__44)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 64 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X v t  : ( 32 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len el1))) t2  : ( 32 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__49 : bool) . 
+           let (data : 64 bits) =
+             (if w__49 then (concat_vec el1 el2  :  64 words$word)
+             else (concat_vec el2 el1  :  64 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__51 : bool) .  sail2_state_monad$bindS
+        (if w__51 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__53 :
+           32 words$word) . 
+        aset_X s w__53))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__54 : 32 bits) . 
+            aset_X t w__54)
+          else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS
+            (aget_Mem address dbytes acctype  : ( 64 words$word) M) (\ (w__55 : 64 bits) . 
+            let data = w__55 in sail2_state_monad$bindS
+            (BigEndian () ) (\ (w__56 : bool) . 
+            if w__56 then sail2_state_monad$seqS
+              (aset_X t
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii)))  :  32 words$word)))
+              (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+            else sail2_state_monad$seqS
+              (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+              (aset_X t2
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii)))  :  32 words$word)))))
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__57 : FaultRecord) . 
+               AArch64_Abort address w__57)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__58 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__58)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__59 :
+               64 words$word) . 
+            aset_X t2 w__59)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 64 words$word) M) (\ (w__60 : 64 bits) . 
+          let data = w__60 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__61 :
+             'regsize words$word) . 
+          aset_X t w__61)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 128 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X ((int_of_num (words$word_len address))) t  : ( 64 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len address))) t2  : ( 64 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__66 : bool) . 
+           let (data : 128 bits) =
+             (if w__66 then (concat_vec el1 el2  :  128 words$word)
+             else (concat_vec el2 el1  :  128 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__68 : bool) .  sail2_state_monad$bindS
+        (if w__68 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__70 :
+           32 words$word) . 
+        aset_X s w__70))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__71 : 32 bits) . 
+            aset_X t w__71)
+          else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS
+            (aget_Mem address dbytes acctype  : ( 128 words$word) M) (\ (w__72 : 128 bits) . 
+            let data = w__72 in sail2_state_monad$bindS
+            (BigEndian () ) (\ (w__73 : bool) . 
+            if w__73 then sail2_state_monad$seqS
+              (aset_X t
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii)))  :  96 words$word)))
+              (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+            else sail2_state_monad$seqS
+              (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+              (aset_X t2
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii)))  :  96 words$word)))))
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__74 : FaultRecord) . 
+               AArch64_Abort address w__74)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__75 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__75)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__76 :
+               64 words$word) . 
+            aset_X t2 w__76)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 128 words$word) M) (\ (w__77 : 128 bits) . 
+          let data = w__77 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__78 :
+             'regsize words$word) . 
+          aset_X t w__78)))
+     ))))))))
+   else
+     let regsize = (size_itself_int regsize) in
+     let datasize = (size_itself_int p_1) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "destsize constraint")
+     (let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val memory_exclusive_single_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_exclusive_single_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDERED
+       else AccType_ATOMIC) in
+     let (pair : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 8 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_exclusive_single acctype ((make_the_value (( 8 : int):ii)  :  8 itself)) (( 8 : int):ii) memop n
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) s t t2)
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDERED
+       else AccType_ATOMIC) in
+     let (pair : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 16 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_exclusive_single acctype ((make_the_value (( 16 : int):ii)  :  16 itself)) (( 16 : int):ii) memop
+       n F ((make_the_value (( 32 : int):ii)  :  32 itself)) s t t2)
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDERED
+       else AccType_ATOMIC) in
+     let (pair : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_exclusive_single acctype ((make_the_value (( 32 : int):ii)  :  32 itself)) (( 32 : int):ii) memop
+       n F ((make_the_value (( 32 : int):ii)  :  32 itself)) s t t2)
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDERED
+       else AccType_ATOMIC) in
+     let (pair : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_exclusive_single acctype ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 64 : int):ii) memop
+       n F ((make_the_value (( 64 : int):ii)  :  64 itself)) s t t2)))`;
+
+
+(*val aarch64_memory_exclusive_pair : forall 'datasize 'regsize . Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> integer -> MemOp -> ii -> bool -> itself 'regsize -> ii -> ii -> ii -> M unit*)
+
+val _ = Define `
+ ((aarch64_memory_exclusive_pair:AccType -> 'datasize itself -> int -> MemOp -> int -> bool -> 'regsize itself -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype p_1 elsize memop n pair regsize s t t2=
+    (if (((((size_itself_int p_1)) = (( 8 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M) (\ (data : 8 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 8 : int):ii)  : ( 8 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 8 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t  : ( 4 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t2  : ( 4 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__4 : bool) . 
+           let (data : 8 bits) =
+             (if w__4 then (concat_vec el1 el2  :  8 words$word)
+             else (concat_vec el2 el1  :  8 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 8 : int):ii) t  : ( 8 words$word) M)) (\ (data : 8 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__6 : bool) .  sail2_state_monad$bindS
+        (if w__6 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__8 :
+           32 words$word) . 
+        aset_X s w__8))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "datasize constraint")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__9 : 32 bits) . 
+            aset_X t w__9)
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__10 : FaultRecord) . 
+               AArch64_Abort address w__10)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__11 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__11)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__12 :
+               64 words$word) . 
+            aset_X t2 w__12)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 8 words$word) M) (\ (w__13 : 8 bits) . 
+          let data = w__13 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__14 :
+             'regsize words$word) . 
+          aset_X t w__14)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 16 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M) (\ (data : 16 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 16 : int):ii)  : ( 16 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 16 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X v t  : ( 8 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len el1))) t2  : ( 8 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__19 : bool) . 
+           let (data : 16 bits) =
+             (if w__19 then (concat_vec el1 el2  :  16 words$word)
+             else (concat_vec el2 el1  :  16 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 16 : int):ii) t  : ( 16 words$word) M)) (\ (data : 16 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__21 : bool) .  sail2_state_monad$bindS
+        (if w__21 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__23 :
+           32 words$word) . 
+        aset_X s w__23))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "datasize constraint")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__24 : 32 bits) . 
+            aset_X t w__24)
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__25 : FaultRecord) . 
+               AArch64_Abort address w__25)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__26 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__26)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__27 :
+               64 words$word) . 
+            aset_X t2 w__27)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 16 words$word) M) (\ (w__28 : 16 bits) . 
+          let data = w__28 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__29 :
+             'regsize words$word) . 
+          aset_X t w__29)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 32 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (data : 32 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 32 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X v t  : ( 16 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len el1))) t2  : ( 16 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__34 : bool) . 
+           let (data : 32 bits) =
+             (if w__34 then (concat_vec el1 el2  :  32 words$word)
+             else (concat_vec el2 el1  :  32 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 32 : int):ii) t  : ( 32 words$word) M)) (\ (data : 32 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__36 : bool) .  sail2_state_monad$bindS
+        (if w__36 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__38 :
+           32 words$word) . 
+        aset_X s w__38))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "datasize constraint")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__39 : 32 bits) . 
+            aset_X t w__39)
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__40 : FaultRecord) . 
+               AArch64_Abort address w__40)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__41 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__41)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__42 :
+               64 words$word) . 
+            aset_X t2 w__42)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 32 words$word) M) (\ (w__43 : 32 bits) . 
+          let data = w__43 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__44 :
+             'regsize words$word) . 
+          aset_X t w__44)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 64 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (data : 64 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 64 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X v t  : ( 32 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len el1))) t2  : ( 32 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__49 : bool) . 
+           let (data : 64 bits) =
+             (if w__49 then (concat_vec el1 el2  :  64 words$word)
+             else (concat_vec el2 el1  :  64 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 64 : int):ii) t  : ( 64 words$word) M)) (\ (data : 64 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__51 : bool) .  sail2_state_monad$bindS
+        (if w__51 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__53 :
+           32 words$word) . 
+        aset_X s w__53))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "datasize constraint")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__54 : 32 bits) . 
+            aset_X t w__54)
+          else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS
+            (aget_Mem address dbytes acctype  : ( 64 words$word) M) (\ (w__55 : 64 bits) . 
+            let data = w__55 in sail2_state_monad$bindS
+            (BigEndian () ) (\ (w__56 : bool) . 
+            if w__56 then sail2_state_monad$seqS
+              (aset_X t
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii)))  :  32 words$word)))
+              (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+            else sail2_state_monad$seqS
+              (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+              (aset_X t2
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii)))  :  32 words$word)))))
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__57 : FaultRecord) . 
+               AArch64_Abort address w__57)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__58 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__58)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__59 :
+               64 words$word) . 
+            aset_X t2 w__59)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 64 words$word) M) (\ (w__60 : 64 bits) . 
+          let data = w__60 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__61 :
+             'regsize words$word) . 
+          aset_X t w__61)))
+     ))))))))
+   else if (((((size_itself_int p_1)) = (( 128 : int):ii)))) then
+     let regsize = (size_itself_int regsize) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "datasize constraint")
+     (sail2_state_monad$assert_expS T "dbytes constraint"))
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M) (\ (data : 128 bits) . 
+     let (rt_unknown : bool) = F in
+     let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then
+        let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS
+        (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))")
+        (UnallocatedEncoding () )
+      else sail2_state_monad$returnS () )
+     (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS
+        (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) .  sail2_state_monad$bindS
+        (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then
+           let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))")
+           (sail2_state_monad$returnS F)
+         else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . 
+        sail2_state_monad$returnS (rn_unknown, rt_unknown)))
+      else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup .  let ((rn_unknown : bool), (rt_unknown :
+       bool)) = varstup in sail2_state_monad$bindS
+     (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) ()   : ( 64 words$word) M)
+      else if rn_unknown then (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)
+      else (aget_X (( 64 : int):ii) n  : ( 64 words$word) M)) (\ (address : 64 bits) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . 
+     (case memop of
+       MemOp_STORE => sail2_state_monad$bindS
+        (if rt_unknown then (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)
+         else if pair then
+           let v = (ex_int (((( 128 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS T "")
+           (aget_X ((int_of_num (words$word_len address))) t  : ( 64 words$word) M)) (\ el1 .  sail2_state_monad$bindS
+           (aget_X ((int_of_num (words$word_len address))) t2  : ( 64 words$word) M) (\ el2 .  sail2_state_monad$bindS
+           (BigEndian () ) (\ (w__66 : bool) . 
+           let (data : 128 bits) =
+             (if w__66 then (concat_vec el1 el2  :  128 words$word)
+             else (concat_vec el2 el1  :  128 words$word)) in
+           sail2_state_monad$returnS data)))
+         else (aget_X (( 128 : int):ii) t  : ( 128 words$word) M)) (\ (data : 128 bits) . 
+        let (status : 1 bits) = ((vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+        (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__68 : bool) .  sail2_state_monad$bindS
+        (if w__68 then sail2_state_monad$seqS
+           (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus ()   : ( 1 words$word) M)
+         else sail2_state_monad$returnS status) (\ (status : 1 bits) .  sail2_state_monad$bindS
+        (ZeroExtend__0 status ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M) (\ (w__70 :
+           32 words$word) . 
+        aset_X s w__70))))
+     | MemOp_LOAD => sail2_state_monad$seqS
+        (AArch64_SetExclusiveMonitors address dbytes)
+        (if pair then sail2_state_monad$seqS
+          (sail2_state_monad$assert_expS T "datasize constraint")
+          (if rt_unknown then sail2_state_monad$bindS
+            (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__71 : 32 bits) . 
+            aset_X t w__71)
+          else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS
+            (aget_Mem address dbytes acctype  : ( 128 words$word) M) (\ (w__72 : 128 bits) . 
+            let data = w__72 in sail2_state_monad$bindS
+            (BigEndian () ) (\ (w__73 : bool) . 
+            if w__73 then sail2_state_monad$seqS
+              (aset_X t
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii)))  :  96 words$word)))
+              (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+            else sail2_state_monad$seqS
+              (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii)  :  32 words$word)))
+              (aset_X t2
+                ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii)))  :  96 words$word)))))
+          else sail2_state_monad$bindS (sail2_state_monad$seqS
+            (if (((address <> ((Align__1 address dbytes  :  64 words$word))))) then
+               let iswrite = F in
+               let secondstage = F in sail2_state_monad$bindS
+               (AArch64_AlignmentFault acctype F F) (\ (w__74 : FaultRecord) . 
+               AArch64_Abort address w__74)
+             else sail2_state_monad$returnS () )
+            (aget_Mem ((add_vec_int address (( 0 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__75 :
+               64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (aset_X t w__75)
+            (aget_Mem ((add_vec_int address (( 8 : int):ii)  :  64 words$word)) (( 8 : int):ii) acctype  : ( 64 words$word) M)) (\ (w__76 :
+               64 words$word) . 
+            aset_X t2 w__76)))
+        else sail2_state_monad$bindS
+          (aget_Mem address dbytes acctype  : ( 128 words$word) M) (\ (w__77 : 128 bits) . 
+          let data = w__77 in sail2_state_monad$bindS
+          (ZeroExtend__0 data ((make_the_value regsize  :  'regsize itself))  : ( 'regsize words$word) M) (\ (w__78 :
+             'regsize words$word) . 
+          aset_X t w__78)))
+     ))))))))
+   else
+     let regsize = (size_itself_int regsize) in
+     let datasize = (size_itself_int p_1) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "regsize constraint")
+     (let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in
+     sail2_state_monad$assert_expS T "datasize constraint")))`;
+
+
+(*val memory_exclusive_pair_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_exclusive_pair_decode:(1)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDERED
+       else AccType_ATOMIC) in
+     let (pair : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_exclusive_pair acctype ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 32 : int):ii) memop n
+       T ((make_the_value (( 32 : int):ii)  :  32 itself)) s t t2)
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (acctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDERED
+       else AccType_ATOMIC) in
+     let (pair : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (elsize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (datasize : ii) = ((( 128 : int):ii)) in
+     aarch64_memory_exclusive_pair acctype ((make_the_value (( 128 : int):ii)  :  128 itself)) (( 64 : int):ii) memop
+       n T ((make_the_value (( 64 : int):ii)  :  64 itself)) s t t2)))`;
+
+
+(*val aarch64_integer_crc : bool -> ii -> ii -> ii -> integer -> M unit*)
+
+val _ = Define `
+ ((aarch64_integer_crc:bool -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) crc32c d m n l__16=
+    (if (((l__16 = (( 8 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (acc : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 8 : int):ii) m  : ( 8 words$word) M) (\ (val_name : 8 bits) . 
+     let (poly : 32 bits) =
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself))
+          (if crc32c then (( 517762881 : int):ii)
+           else (( 79764919 : int):ii)) (( 0 : int):ii)
+         :  32 words$word)) in sail2_state_monad$bindS
+     (BitReverse acc  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+     let (tempacc : 40 bits) =
+       ((concat_vec w__0 ((Zeros__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word))
+         :  40 words$word)) in sail2_state_monad$bindS
+     (BitReverse val_name  : ( 8 words$word) M) (\ (w__1 :  8 words$word) . 
+     let (tempval : 40 bits) =
+       ((concat_vec w__1 ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+         :  40 words$word)) in sail2_state_monad$bindS
+     (Poly32Mod2 ((xor_vec tempacc tempval  :  40 words$word)) poly  : ( 32 words$word) M) (\ (w__2 :
+        32 words$word) .  sail2_state_monad$bindS
+     (BitReverse w__2  : ( 32 words$word) M) (\ (w__3 :  32 words$word) .  aset_X d w__3))))))
+   else if (((l__16 = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (acc : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 16 : int):ii) m  : ( 16 words$word) M) (\ (val_name : 16 bits) . 
+     let (poly : 32 bits) =
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself))
+          (if crc32c then (( 517762881 : int):ii)
+           else (( 79764919 : int):ii)) (( 0 : int):ii)
+         :  32 words$word)) in sail2_state_monad$bindS
+     (BitReverse acc  : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+     let (tempacc : 48 bits) =
+       ((concat_vec w__4 ((Zeros__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+         :  48 words$word)) in sail2_state_monad$bindS
+     (BitReverse val_name  : ( 16 words$word) M) (\ (w__5 :  16 words$word) . 
+     let (tempval : 48 bits) =
+       ((concat_vec w__5 ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+         :  48 words$word)) in sail2_state_monad$bindS
+     (Poly32Mod2 ((xor_vec tempacc tempval  :  48 words$word)) poly  : ( 32 words$word) M) (\ (w__6 :
+        32 words$word) .  sail2_state_monad$bindS
+     (BitReverse w__6  : ( 32 words$word) M) (\ (w__7 :  32 words$word) .  aset_X d w__7))))))
+   else if (((l__16 = (( 32 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (acc : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 32 : int):ii) m  : ( 32 words$word) M) (\ (val_name : 32 bits) . 
+     let (poly : 32 bits) =
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself))
+          (if crc32c then (( 517762881 : int):ii)
+           else (( 79764919 : int):ii)) (( 0 : int):ii)
+         :  32 words$word)) in sail2_state_monad$bindS
+     (BitReverse acc  : ( 32 words$word) M) (\ (w__8 :  32 words$word) . 
+     let (tempacc : 64 bits) =
+       ((concat_vec w__8 ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+         :  64 words$word)) in sail2_state_monad$bindS
+     (BitReverse val_name  : ( 32 words$word) M) (\ (w__9 :  32 words$word) . 
+     let (tempval : 64 bits) =
+       ((concat_vec w__9 ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+         :  64 words$word)) in sail2_state_monad$bindS
+     (Poly32Mod2 ((xor_vec tempacc tempval  :  64 words$word)) poly  : ( 32 words$word) M) (\ (w__10 :
+        32 words$word) .  sail2_state_monad$bindS
+     (BitReverse w__10  : ( 32 words$word) M) (\ (w__11 :  32 words$word) .  aset_X d w__11))))))
+   else if (((l__16 = (( 64 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (aget_X (( 32 : int):ii) n  : ( 32 words$word) M)) (\ (acc : 32 bits) .  sail2_state_monad$bindS
+     (aget_X (( 64 : int):ii) m  : ( 64 words$word) M) (\ (val_name : 64 bits) . 
+     let (poly : 32 bits) =
+       ((GetSlice_int ((make_the_value (( 32 : int):ii)  :  32 itself))
+          (if crc32c then (( 517762881 : int):ii)
+           else (( 79764919 : int):ii)) (( 0 : int):ii)
+         :  32 words$word)) in sail2_state_monad$bindS
+     (BitReverse acc  : ( 32 words$word) M) (\ (w__12 :  32 words$word) . 
+     let (tempacc : 96 bits) =
+       ((concat_vec w__12 ((Zeros__0 ((make_the_value (( 64 : int):ii)  :  64 itself))  :  64 words$word))
+         :  96 words$word)) in sail2_state_monad$bindS
+     (BitReverse val_name  : ( 64 words$word) M) (\ (w__13 :  64 words$word) . 
+     let (tempval : 96 bits) =
+       ((concat_vec w__13 ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+         :  96 words$word)) in sail2_state_monad$bindS
+     (Poly32Mod2 ((xor_vec tempacc tempval  :  96 words$word)) poly  : ( 32 words$word) M) (\ (w__14 :
+        32 words$word) .  sail2_state_monad$bindS
+     (BitReverse w__14  : ( 32 words$word) M) (\ (w__15 :  32 words$word) .  aset_X d w__15))))))
+   else sail2_state_monad$assert_expS T ""))`;
+
+
+(*val system_exceptions_debug_exception_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((system_exceptions_debug_exception_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (target_level : 2 bits) = LL in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if (((LL = (vec_of_bits [B0;B0]  :  2 words$word)))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (Halted () )) (\ (w__0 : bool) .  sail2_state_monad$seqS
+   (if ((~ w__0)) then AArch64_UndefinedFault () 
+    else sail2_state_monad$returnS () )
+   (aarch64_system_exceptions_debug_exception target_level)))))`;
+
+
+(*val system_barriers_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty2 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((system_barriers_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm opc Rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (undefined_MemBarrierOp () )) (\ (op : MemBarrierOp) .  sail2_state_monad$bindS
+   (undefined_MBReqDomain () ) (\ (domain1 : MBReqDomain) .  sail2_state_monad$bindS
+   (undefined_MBReqTypes () ) (\ (types : MBReqTypes) . 
+   let b__0 = opc in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS MemBarrierOp_DSB
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS MemBarrierOp_DMB
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$returnS MemBarrierOp_ISB
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS op)) (\ (op : MemBarrierOp) . 
+   let b__3 = ((slice CRm (( 2 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+   let (domain1 : MBReqDomain) =
+     (if (((b__3 = (vec_of_bits [B0;B0]  :  2 words$word)))) then MBReqDomain_OuterShareable
+     else if (((b__3 = (vec_of_bits [B0;B1]  :  2 words$word)))) then MBReqDomain_Nonshareable
+     else if (((b__3 = (vec_of_bits [B1;B0]  :  2 words$word)))) then MBReqDomain_InnerShareable
+     else MBReqDomain_FullSystem) in
+   let b__7 = ((slice CRm (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+   let ((domain1 : MBReqDomain), (types : MBReqTypes)) =
+     (if (((b__7 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+       let (types : MBReqTypes) = MBReqTypes_Reads in
+       (domain1, types)
+     else
+       let ((domain1 : MBReqDomain), (types : MBReqTypes)) =
+         (if (((b__7 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+           let (types : MBReqTypes) = MBReqTypes_Writes in
+           (domain1, types)
+         else
+           let ((domain1 : MBReqDomain), (types : MBReqTypes)) =
+             (if (((b__7 = (vec_of_bits [B1;B1]  :  2 words$word)))) then
+               let (types : MBReqTypes) = MBReqTypes_All in
+               (domain1, types)
+             else
+               let (types : MBReqTypes) = MBReqTypes_All in
+               let (domain1 : MBReqDomain) = MBReqDomain_FullSystem in
+               (domain1, types)) in
+           (domain1, types)) in
+       (domain1, types)) in
+   sail2_state_monad$returnS ((aarch64_system_barriers domain1 op types))))))))`;
+
+
+(*val memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L R1 Rm b__1 S1 b__2 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__0 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__0 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__1 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__1 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__2 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__2 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__3 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__3 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__4 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__4 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__5 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__5 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__6 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__6 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__7 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__7 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T)))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__8 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__8 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__9 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__9 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__10 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__10 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__11 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__11 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__12 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__12 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__13 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__13 m memop n T ((ex_int selem)) t T))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__14 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__14 m memop n T ((ex_int selem)) t T))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__15 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__15 m memop n T ((ex_int selem)) t T))))))`;
+
+
+(*val memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode:(1)words$word ->(1)words$word ->(1)words$word ->(3)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L R1 b__1 S1 b__2 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__0 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__0 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__1 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__1 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__2 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__2 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__3 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__3 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__4 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__4 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__5 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__5 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__6 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__6 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__7 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__7 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__8 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__8 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__9 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__9 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__10 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__10 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__11 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__11 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__12 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__12 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__13 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__13 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__14 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__14 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__15 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__15 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__16 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__16 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__17 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) w__17 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__18 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__18 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__19 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) w__19 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__20 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__20 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__21 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) w__21 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__22 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__22 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 0 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__23 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 0 : int):ii) w__23 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__24 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__25 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__24 w__25 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__26 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__27 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__26 w__27 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__28 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__29 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__28 w__29 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__30 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__31 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__30 w__31 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__32 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__33 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__32 w__33 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__34 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__35 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__34 w__35 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__36 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__37 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__36 w__37 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__38 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__39 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__38 w__39 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__40 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__40 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__41 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__41 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__42 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__42 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__43 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__43 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__44 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__44 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__45 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__45 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B0]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__46 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__46 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1;B1]  :  2 words$word)
+            :  4 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__47 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) index w__47 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__48 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__48 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__49 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__49 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__50 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__50 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__51 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__51 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__52 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__52 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B0]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__53 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__53 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__54 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__54 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index =
+       (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))
+             (vec_of_bits [B1]  :  1 words$word)
+            :  3 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__55 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) index w__55 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__56 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__56 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__57 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) w__57 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__58 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__58 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__59 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) w__59 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) . 
+     let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__60 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__60 memop n F ((ex_int selem)) t F))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__61 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) w__61 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) S1  :  2 words$word))) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__62 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) index w__62 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let index = ((( 1 : int):ii)) in
+     let scale = ((( 3 : int):ii)) in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__63 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) (( 1 : int):ii) w__63 memop n F ((ex_int selem)) t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__64 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__65 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__64 w__65 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__66 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__67 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__66 w__67 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__68 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__69 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__68 w__69 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B0]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__70 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__71 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__70 w__71 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 0 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__72 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__73 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 8 : int):ii)  :  8 itself)) w__72 w__73 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 1 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__74 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__75 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 16 : int):ii)  :  16 itself)) w__74 w__75 memop n T ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 2 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__76 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__77 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) w__76 w__77 memop n T ((ex_int selem)) t F))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (selem : ii) =
+       (((lem$w2ui ((concat_vec (vec_of_bits [B1]  :  1 words$word) R1  :  2 words$word)))) + (( 1 : int):ii)) in
+     let (replicate : bool) = F in sail2_state_monad$bindS
+     (undefined_int () ) (\ (index : ii) .  sail2_state_monad$seqS
+     (if ((((((L = (vec_of_bits [B0]  :  1 words$word)))) \/ (((S1 = (vec_of_bits [B1]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let scale = ((( 3 : int):ii)) in
+     let replicate = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__78 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (w__79 : ii) . 
+     aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) w__78 w__79 memop n T ((ex_int selem)) t F))))))))`;
+
+
+(*val memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode:(2)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc Rm option_name S1 Rn Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (wback : bool) = F in
+   let (postindex : bool) = F in
+   let (scale : ii) =
+     (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)]  :  1 words$word) size1  :  3 words$word))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+      UnallocatedEncoding () 
+    else sail2_state_monad$returnS () ))
+   (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+   let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then scale else (( 0 : int):ii)) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (t : ii) = (lem$w2ui Rt) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (acctype : AccType) = AccType_VEC in
+   let (memop : MemOp) =
+     (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       MemOp_LOAD
+     else MemOp_STORE) in
+   let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in
+   aarch64_memory_single_simdfp_register acctype datasize extend_type m memop n postindex shift t
+     wback))))`;
+
+
+(*val memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm12 Rn Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (wback : bool) = F in
+   let (postindex : bool) = F in
+   let (scale : ii) =
+     (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)]  :  1 words$word) size1  :  3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M)) (\ (w__0 :
+      64 words$word) .  sail2_state_monad$bindS
+   (LSL w__0 scale  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+   let (n : ii) = (lem$w2ui Rn) in
+   let (t : ii) = (lem$w2ui Rt) in
+   let (acctype : AccType) = AccType_VEC in
+   let (memop : MemOp) =
+     (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       MemOp_LOAD
+     else MemOp_STORE) in
+   let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in
+   aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t
+     wback)))))`;
+
+
+(*val memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm9 Rn Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (wback : bool) = T in
+   let (postindex : bool) = F in
+   let (scale : ii) =
+     (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)]  :  1 words$word) size1  :  3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M)) (\ (offset : 64
+     bits) . 
+   let (n : ii) = (lem$w2ui Rn) in
+   let (t : ii) = (lem$w2ui Rt) in
+   let (acctype : AccType) = AccType_VEC in
+   let (memop : MemOp) =
+     (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       MemOp_LOAD
+     else MemOp_STORE) in
+   let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in
+   aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t
+     wback))))`;
+
+
+(*val memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm9 Rn Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (wback : bool) = T in
+   let (postindex : bool) = T in
+   let (scale : ii) =
+     (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)]  :  1 words$word) size1  :  3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M)) (\ (offset : 64
+     bits) . 
+   let (n : ii) = (lem$w2ui Rn) in
+   let (t : ii) = (lem$w2ui Rt) in
+   let (acctype : AccType) = AccType_VEC in
+   let (memop : MemOp) =
+     (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       MemOp_LOAD
+     else MemOp_STORE) in
+   let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in
+   aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t
+     wback))))`;
+
+
+(*val memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm9 Rn Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (wback : bool) = F in
+   let (postindex : bool) = F in
+   let (scale : ii) =
+     (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)]  :  1 words$word) size1  :  3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M)) (\ (offset : 64
+     bits) . 
+   let (n : ii) = (lem$w2ui Rn) in
+   let (t : ii) = (lem$w2ui Rt) in
+   let (acctype : AccType) = AccType_VEC in
+   let (memop : MemOp) =
+     (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+       MemOp_LOAD
+     else MemOp_STORE) in
+   let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in
+   aarch64_memory_single_simdfp_immediate_signed_offset_normal acctype datasize memop n offset
+     postindex t wback))))`;
+
+
+(*val memory_single_general_register_aarch64_memory_single_general_register__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_register_aarch64_memory_single_general_register__decode:(2)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 Rm option_name S1 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_STORE n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) shift T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_STORE n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) shift T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_STORE n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) shift T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) shift T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_STORE n F
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_LOAD n F
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) shift F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_PREFETCH in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . 
+     aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_PREFETCH n
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) shift w__0 t F))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS
+     (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+     let (shift : ii) = (if (((S1 = (vec_of_bits [B1]  :  1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_PREFETCH in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . 
+     aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_PREFETCH n
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) shift w__1 t F)))))))))`;
+
+
+(*val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode:(2)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm12 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_STORE n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__4 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__4 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_STORE n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__5 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__5 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__6 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__6 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__7 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__7 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__8 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__8 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_STORE n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__9 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__9 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__10 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__10 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__11 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__11 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__12 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__12 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_STORE n offset
+       F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__13 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__13 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__14 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__14 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_PREFETCH in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__15 : bool) . 
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_PREFETCH n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__15 t F)))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__16 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__16 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_PREFETCH in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__17 : bool) . 
+     aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_PREFETCH n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__17 t F))))))))))`;
+
+
+(*val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm12 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 0 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__4 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__4 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__5 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__5 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__6 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__6 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__7 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__7 (( 1 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__8 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__8 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__9 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__9 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__10 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__10 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__11 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__11 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__12 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__12 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__13 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__13 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__14 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__14 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__15 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__16 : bool) . 
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__15 n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__16 t F)))))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__17 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__17 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__18 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__19 : bool) . 
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__18 n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__19 t F)))))))))))`;
+
+
+(*val memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__0 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . 
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__0 n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__1 t T))))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__2 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . 
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__2 n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__3 t T))))))))))`;
+
+
+(*val memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_STORE n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 64 : int):ii)  :  64 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_STORE n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 64 : int):ii)  :  64 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_STORE n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 64 : int):ii)  :  64 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 32 : int):ii)  :  32 itself)) T t T))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_STORE n
+       offset T ((make_the_value (( 64 : int):ii)  :  64 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n
+       offset T ((make_the_value (( 64 : int):ii)  :  64 itself)) F t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__0 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . 
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__0 n offset
+       T ((make_the_value (( 32 : int):ii)  :  32 itself)) w__1 t T))))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__2 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . 
+     aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__2 n offset
+       T ((make_the_value (( 32 : int):ii)  :  32 itself)) w__3 t T))))))))))`;
+
+
+(*val memory_single_general_immediate_signed_pac_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty9 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_signed_pac_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(9)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 M S1 imm9 W1 Rn Rt=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (if (((((~ ((HavePACExt () )))) \/ (((size1 <> (vec_of_bits [B1;B1]  :  2 words$word)))))))
+    then
+      UnallocatedEncoding () 
+    else sail2_state_monad$returnS () ))
+   (let (t : ii) = (lem$w2ui Rt) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (wback : bool) = (W1 = (vec_of_bits [B1]  :  1 words$word)) in
+   let (use_key_a : bool) = (M = (vec_of_bits [B0]  :  1 words$word)) in
+   let (S10 : 10 bits) = ((concat_vec S1 imm9  :  10 words$word)) in
+   let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+   (SignExtend__0 S10 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+      64 words$word) .  sail2_state_monad$bindS
+   (LSL w__0 scale  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+   aarch64_memory_single_general_immediate_signed_pac n offset t use_key_a wback)))))`;
+
+
+(*val memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__3 : bool) . 
+     let (acctype : AccType) = (if w__3 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__4 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__6 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__7 : bool) . 
+     let (acctype : AccType) = (if w__7 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__8 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__10 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__11 : bool) . 
+     let (acctype : AccType) = (if w__11 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__12 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__14 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__15 : bool) . 
+     let (acctype : AccType) = (if w__15 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_LOAD n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__16 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__16 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__18 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__19 : bool) . 
+     let (acctype : AccType) = (if w__19 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__20 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__22 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__22 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__23 : bool) . 
+     let (acctype : AccType) = (if w__23 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__24 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__24 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__26 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__26 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__27 : bool) . 
+     let (acctype : AccType) = (if w__27 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__28 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__28 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__30 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__30 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__31 : bool) . 
+     let (acctype : AccType) = (if w__31 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__32 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__32 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__34 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__34 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__35 : bool) . 
+     let (acctype : AccType) = (if w__35 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__36 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__36 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__38 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__38 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__39 : bool) . 
+     let (acctype : AccType) = (if w__39 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__40 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__40 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__42 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__42 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__43 : bool) . 
+     let (acctype : AccType) = (if w__43 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__44 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__44 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__46 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__46 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__47 : bool) . 
+     let (acctype : AccType) = (if w__47 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F)))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__48 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__48 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__50 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__50 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__51 : bool) . 
+     let (acctype : AccType) = (if w__51 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) MemOp_STORE n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__52 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__52 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__54 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__54 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__55 : bool) . 
+     let (acctype : AccType) = (if w__55 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__56 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__56 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__58 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__58 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__59 : bool) . 
+     let (acctype : AccType) = (if w__59 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__60 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__61 : bool) . 
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) w__60 n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__61 t F)))))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS
+     (sail2_state$and_boolS
+       (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__62 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__62 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+       ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__64 : 64 bits) . 
+        sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__64 (( 43 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__65 : bool) . 
+     let (acctype : AccType) = (if w__65 then AccType_NORMAL else acctype) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) .  sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (w__66 : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__67 : bool) . 
+     aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) w__66 n offset
+       F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__67 t F)))))))))))`;
+
+
+(*val memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_STORE
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n
+       offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_STORE
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((F /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_STORE
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 32 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ F))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 64 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in sail2_state_monad$seqS
+     (if (((T /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let regsize = ((( 32 : int):ii)) in
+     let signed = T in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) T t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_STORE in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii) MemOp_STORE
+       n offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_LOAD in
+     let regsize = ((( 64 : int):ii)) in
+     let signed = F in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii) MemOp_LOAD
+       n offset F ((make_the_value (( 64 : int):ii)  :  64 itself)) F t F)))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_PREFETCH in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . 
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii)
+       MemOp_PREFETCH n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__0 t F))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (offset : 64
+       bits) . 
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS
+     (undefined_MemOp () ) (\ (memop : MemOp) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (regsize : ii) . 
+     let memop = MemOp_PREFETCH in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . 
+     aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii)
+       MemOp_PREFETCH n offset F ((make_the_value (( 32 : int):ii)  :  32 itself)) w__1 t F)))))))))`;
+
+
+(*val memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 : int):ii)  :  32 itself)) memop
+       n offset F t t2 T)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 : int):ii)  :  64 itself)) memop
+       n offset F t t2 T)))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 4 : int):ii)) in
+     let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 4 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 : int):ii)  :  128 itself))
+       memop n offset F t t2 T)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (scale : ii) = ((( 5 : int):ii)) in
+     let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 5 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 : int):ii)  :  256 itself))
+       memop n offset F t t2 T))))))`;
+
+
+(*val memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 : int):ii)  :  32 itself)) memop
+       n offset T t t2 T)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 : int):ii)  :  64 itself)) memop
+       n offset T t t2 T)))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 4 : int):ii)) in
+     let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 4 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 : int):ii)  :  128 itself))
+       memop n offset T t t2 T)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (scale : ii) = ((( 5 : int):ii)) in
+     let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 5 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 : int):ii)  :  256 itself))
+       memop n offset T t t2 T))))))`;
+
+
+(*val memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 : int):ii)  :  32 itself)) memop
+       n offset F t t2 F)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 : int):ii)  :  64 itself)) memop
+       n offset F t t2 F)))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 4 : int):ii)) in
+     let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 4 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 : int):ii)  :  128 itself))
+       memop n offset F t t2 F)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VEC in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (scale : ii) = ((( 5 : int):ii)) in
+     let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 5 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 : int):ii)  :  256 itself))
+       memop n offset F t t2 F))))))`;
+
+
+(*val memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VECSTREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F t t2 F)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VECSTREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F t t2 F)))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VECSTREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 4 : int):ii)) in
+     let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 4 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM
+       ((make_the_value (( 128 : int):ii)  :  128 itself)) memop n offset F t t2 F)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_VECSTREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (scale : ii) = ((( 5 : int):ii)) in
+     let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 5 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM
+       ((make_the_value (( 256 : int):ii)  :  256 itself)) memop n offset F t t2 F))))))`;
+
+
+(*val memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B0]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F F t t2 T))))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B1]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F T t t2 T))))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B0]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F F t t2 T))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B1]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ T))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F T t t2 T))))))`;
+
+
+(*val memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B0]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset T F t t2 T))))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B1]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset T T t t2 T))))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B0]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset T F t t2 T))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = T in
+     let (postindex : bool) = T in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B1]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ T))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset T T t t2 T))))))`;
+
+
+(*val memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B0]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = F in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F F t t2 F))))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B1]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = T in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F T t t2 F))))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B0]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = F in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F F t t2 F))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_NORMAL in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (if ((((((((concat_vec L (vec_of_bits [B1]  :  1 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) \/ T))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (signed : bool) = T in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F T t t2 F))))))`;
+
+
+(*val memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_STREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__0 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__0 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F t t2 F)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_STREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (scale : ii) = ((( 2 : int):ii)) in
+     let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__1 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__1 (( 2 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 32 : int):ii)  :  32 itself))
+       memop n offset F t t2 F))))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_STREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__2 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__2 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F t t2 F)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (wback : bool) = F in
+     let (postindex : bool) = F in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (t2 : ii) = (lem$w2ui Rt2) in
+     let (acctype : AccType) = AccType_STREAM in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (let (scale : ii) = ((( 3 : int):ii)) in
+     let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M) (\ (w__3 :
+        64 words$word) .  sail2_state_monad$bindS
+     (LSL w__3 (( 3 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+     aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 64 : int):ii)  :  64 itself))
+       memop n offset F t t2 F))))))`;
+
+
+(*val memory_literal_simdfp_decode : mword ty2 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_literal_simdfp_decode:(2)words$word ->(1)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc V1 imm19 Rt=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (t : ii) = (lem$w2ui Rt) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (size1 : ii) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (offset : 64 bits) . 
+   let b__0 = opc in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 4 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 8 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS size1)) (\ (size1 : ii) .  sail2_state_monad$bindS
+   (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0]  :  2 words$word)  :  21 words$word))
+      ((make_the_value (( 64 : int):ii)  :  64 itself))
+     : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+   let offset = w__0 in
+   aarch64_memory_literal_simdfp offset ((ex_int size1)) t)))))))`;
+
+
+(*val memory_atomicops_swp_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_atomicops_swp_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 A R1 Rs o3 opc Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_swp (( 8 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii)  :  32 itself)) s
+       stacctype t)
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_swp (( 16 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii)  :  32 itself)) s
+       stacctype t)
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_swp (( 32 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii)  :  32 itself)) s
+       stacctype t)
+   else sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_swp (( 64 : int):ii) ldacctype n ((make_the_value (( 64 : int):ii)  :  64 itself)) s
+       stacctype t)))`;
+
+
+(*val memory_atomicops_st_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_atomicops_st_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 A R1 Rs o3 opc Rn Rt=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () ))
+   (let (n : ii) = (lem$w2ui Rn) in
+   let (s : ii) = (lem$w2ui Rs) in
+   let (datasize : ii) = (shl_int (( 8 : int):ii) ((lem$w2ui size1))) in
+   let (regsize : ii) = (if (((((ex_int datasize)) = (( 64 : int):ii)))) then (( 64 : int):ii) else (( 32 : int):ii)) in
+   let (ldacctype : AccType) = AccType_ATOMICRW in
+   let (stacctype : AccType) =
+     (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+     else AccType_ATOMICRW) in sail2_state_monad$bindS
+   (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . 
+   let b__0 = opc in
+   let (op : MemAtomicOp) =
+     (if (((b__0 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then MemAtomicOp_ADD
+     else if (((b__0 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then MemAtomicOp_BIC
+     else if (((b__0 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then MemAtomicOp_EOR
+     else if (((b__0 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then MemAtomicOp_ORR
+     else if (((b__0 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then MemAtomicOp_SMAX
+     else if (((b__0 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then MemAtomicOp_SMIN
+     else if (((b__0 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then MemAtomicOp_UMAX
+     else MemAtomicOp_UMIN) in
+   aarch64_memory_atomicops_st datasize ldacctype n op s stacctype))))`;
+
+
+(*val memory_atomicops_ld_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_atomicops_ld_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 A R1 Rs o3 opc Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in sail2_state_monad$bindS
+     (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . 
+     let b__1 = opc in
+     let (op : MemAtomicOp) =
+       (if (((b__1 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then MemAtomicOp_ADD
+       else if (((b__1 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then MemAtomicOp_BIC
+       else if (((b__1 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then MemAtomicOp_EOR
+       else if (((b__1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then MemAtomicOp_ORR
+       else if (((b__1 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then MemAtomicOp_SMAX
+       else if (((b__1 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then MemAtomicOp_SMIN
+       else if (((b__1 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then MemAtomicOp_UMAX
+       else MemAtomicOp_UMIN) in
+     aarch64_memory_atomicops_ld (( 8 : int):ii) ldacctype n op ((make_the_value (( 32 : int):ii)  :  32 itself)) s
+       stacctype t))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in sail2_state_monad$bindS
+     (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . 
+     let b__10 = opc in
+     let (op : MemAtomicOp) =
+       (if (((b__10 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then MemAtomicOp_ADD
+       else if (((b__10 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then MemAtomicOp_BIC
+       else if (((b__10 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then MemAtomicOp_EOR
+       else if (((b__10 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then MemAtomicOp_ORR
+       else if (((b__10 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then MemAtomicOp_SMAX
+       else if (((b__10 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then MemAtomicOp_SMIN
+       else if (((b__10 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then MemAtomicOp_UMAX
+       else MemAtomicOp_UMIN) in
+     aarch64_memory_atomicops_ld (( 16 : int):ii) ldacctype n op ((make_the_value (( 32 : int):ii)  :  32 itself)) s
+       stacctype t))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in sail2_state_monad$bindS
+     (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . 
+     let b__19 = opc in
+     let (op : MemAtomicOp) =
+       (if (((b__19 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then MemAtomicOp_ADD
+       else if (((b__19 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then MemAtomicOp_BIC
+       else if (((b__19 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then MemAtomicOp_EOR
+       else if (((b__19 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then MemAtomicOp_ORR
+       else if (((b__19 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then MemAtomicOp_SMAX
+       else if (((b__19 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then MemAtomicOp_SMIN
+       else if (((b__19 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then MemAtomicOp_UMAX
+       else MemAtomicOp_UMIN) in
+     aarch64_memory_atomicops_ld (( 32 : int):ii) ldacctype n op ((make_the_value (( 32 : int):ii)  :  32 itself)) s
+       stacctype t))
+   else sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if ((((((A = (vec_of_bits [B1]  :  1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+         AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((R1 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in sail2_state_monad$bindS
+     (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . 
+     let b__28 = opc in
+     let (op : MemAtomicOp) =
+       (if (((b__28 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then MemAtomicOp_ADD
+       else if (((b__28 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then MemAtomicOp_BIC
+       else if (((b__28 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then MemAtomicOp_EOR
+       else if (((b__28 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then MemAtomicOp_ORR
+       else if (((b__28 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then MemAtomicOp_SMAX
+       else if (((b__28 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then MemAtomicOp_SMIN
+       else if (((b__28 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then MemAtomicOp_UMAX
+       else MemAtomicOp_UMIN) in
+     aarch64_memory_atomicops_ld (( 64 : int):ii) ldacctype n op ((make_the_value (( 64 : int):ii)  :  64 itself)) s
+       stacctype t))))`;
+
+
+(*val memory_atomicops_cas_single_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_atomicops_cas_single_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 8 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_cas_single (( 8 : int):ii) ldacctype n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) s stacctype t)
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 16 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_cas_single (( 16 : int):ii) ldacctype n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) s stacctype t)
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_cas_single (( 32 : int):ii) ldacctype n
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) s stacctype t)
+   else sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_cas_single (( 64 : int):ii) ldacctype n
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) s stacctype t)))`;
+
+
+(*val memory_atomicops_cas_pair_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_atomicops_cas_pair_decode:(1)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt=
+    (if (((b__0 = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (if ((((vec_of_bits [access_vec_dec Rs (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (if ((((vec_of_bits [access_vec_dec Rt (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 32 : int):ii)) in
+     let (regsize : ii) = ((( 32 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_cas_pair (( 32 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii)  :  32 itself))
+       s stacctype t)
+   else sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (if ((((vec_of_bits [access_vec_dec Rs (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (if ((((vec_of_bits [access_vec_dec Rt (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (n : ii) = (lem$w2ui Rn) in
+     let (t : ii) = (lem$w2ui Rt) in
+     let (s : ii) = (lem$w2ui Rs) in
+     let (datasize : ii) = ((( 64 : int):ii)) in
+     let (regsize : ii) = ((( 64 : int):ii)) in
+     let (ldacctype : AccType) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     let (stacctype : AccType) =
+       (if (((o0 = (vec_of_bits [B1]  :  1 words$word)))) then AccType_ORDEREDRW
+       else AccType_ATOMICRW) in
+     aarch64_memory_atomicops_cas_pair (( 64 : int):ii) ldacctype n ((make_the_value (( 64 : int):ii)  :  64 itself))
+       s stacctype t)))`;
+
+
+(*val integer_pac_strip_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_strip_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 D Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (data : bool) = (D = (vec_of_bits [B1]  :  1 words$word)) in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () ))
+   (aarch64_integer_pac_strip_dp_1src d data))))`;
+
+
+(*val integer_pac_pacib_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacib_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_pacib_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_pacia_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacia_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_pacia_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_pacga_dp_2src_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacga_dp_2src_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (let (source_is_sp : bool) = (if (((((ex_int m)) = (( 31 : int):ii)))) then T else source_is_sp) in
+   aarch64_integer_pac_pacga_dp_2src d m n source_is_sp))))`;
+
+
+(*val integer_pac_pacdb_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacdb_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_pacdb_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_pacda_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_pacda_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_pacda_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_autib_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_autib_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_autib_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_autia_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_autia_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_autia_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_autdb_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_autdb_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_autdb_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_pac_autda_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_pac_autda_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (source_is_sp : bool) = F in
+   let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Z = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in
+      sail2_state_monad$returnS source_is_sp
+    else sail2_state_monad$seqS
+      (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . 
+   aarch64_integer_pac_autda_dp_1src d n source_is_sp))))`;
+
+
+(*val integer_insext_insert_movewide_decode : mword ty1 -> mword ty2 -> mword ty2 -> mword ty16 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_insext_insert_movewide_decode:(1)words$word ->(2)words$word ->(2)words$word ->(16)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf opc hw imm16 Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (imm : 16 bits) = imm16 in sail2_state_monad$bindS
+   (undefined_int () ) (\ (pos : ii) .  sail2_state_monad$bindS
+   (undefined_MoveWideOp () ) (\ (opcode : MoveWideOp) . 
+   let b__0 = opc in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS MoveWideOp_N
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$returnS MoveWideOp_Z
+    else if (((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) then sail2_state_monad$returnS MoveWideOp_K
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS opcode)) (\ (opcode : MoveWideOp) .  sail2_state_monad$seqS
+   (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((vec_of_bits [access_vec_dec hw (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+      UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (let pos = (lem$w2ui ((concat_vec hw (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)  :  6 words$word))) in
+   aarch64_integer_insext_insert_movewide d datasize imm opcode pos)))))))`;
+
+
+(*val integer_crc_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_crc_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 C b__0 Rn Rd=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (if ((((((sf = (vec_of_bits [B1]  :  1 words$word)))) /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (size1 : ii) = ((( 8 : int):ii)) in
+     let (crc32c : bool) = (C = (vec_of_bits [B1]  :  1 words$word)) in
+     aarch64_integer_crc crc32c d m n (( 8 : int):ii)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (if ((((((sf = (vec_of_bits [B1]  :  1 words$word)))) /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (size1 : ii) = ((( 16 : int):ii)) in
+     let (crc32c : bool) = (C = (vec_of_bits [B1]  :  1 words$word)) in
+     aarch64_integer_crc crc32c d m n (( 16 : int):ii)))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (if ((((((sf = (vec_of_bits [B1]  :  1 words$word)))) /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (size1 : ii) = ((( 32 : int):ii)) in
+     let (crc32c : bool) = (C = (vec_of_bits [B1]  :  1 words$word)) in
+     aarch64_integer_crc crc32c d m n (( 32 : int):ii)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (if ((((((sf = (vec_of_bits [B1]  :  1 words$word)))) /\ F))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ T))) then UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (size1 : ii) = ((( 64 : int):ii)) in
+     let (crc32c : bool) = (C = (vec_of_bits [B1]  :  1 words$word)) in
+     aarch64_integer_crc crc32c d m n (( 64 : int):ii)))))`;
+
+
+(*val integer_arithmetic_rev_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_rev_decode:(1)words$word ->(1)words$word ->(5)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 opc Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (container_size : ii) . 
+   let b__0 = opc in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (Unreachable () ) (sail2_state_monad$returnS container_size)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 16 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else sail2_state_monad$seqS
+      (if (((sf = (vec_of_bits [B0]  :  1 words$word)))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS (( 64 : int):ii))) (\ (container_size : ii) . 
+   aarch64_integer_arithmetic_rev container_size d datasize n)))))`;
+
+
+(*val float_move_fp_select_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_move_fp_select_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(4)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm cond Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (condition : 4 bits) = cond in
+   aarch64_float_move_fp_select condition d datasize m n)))))`;
+
+
+(*val float_move_fp_imm_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty8 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_move_fp_imm_decode:(1)words$word ->(1)words$word ->(2)words$word ->(8)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 b__0 imm8 imm5 Rd=
+    (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (datasize : ii) . 
+     let datasize = ((( 32 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (VFPExpandImm (( 32 : int):ii) imm8  : ( 32 words$word) M)) (\ (imm : 32 bits) . 
+     aarch64_float_move_fp_imm d ((make_the_value (( 32 : int):ii)  :  32 itself)) imm)))
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (datasize : ii) . 
+     let datasize = ((( 64 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (VFPExpandImm (( 64 : int):ii) imm8  : ( 64 words$word) M)) (\ (imm : 64 bits) . 
+     aarch64_float_move_fp_imm d ((make_the_value (( 64 : int):ii)  :  64 itself)) imm)))
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (datasize : ii) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (sail2_state_monad$assert_expS T ""))
+     (VFPExpandImm (( 32 : int):ii) imm8  : ( 32 words$word) M)) (\ (imm : 32 bits) . 
+     aarch64_float_move_fp_imm d ((make_the_value (( 32 : int):ii)  :  32 itself)) imm)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (datasize : ii) . 
+     let datasize = ((( 16 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (VFPExpandImm (( 16 : int):ii) imm8  : ( 16 words$word) M)) (\ (imm : 16 bits) . 
+     aarch64_float_move_fp_imm d ((make_the_value (( 16 : int):ii)  :  16 itself)) imm)))))`;
+
+
+(*val aarch64_float_convert_int_split : ii -> ii -> ii -> ii -> FPConvOp -> ii -> FPRounding -> bool -> M unit*)
+
+val _ = Define `
+ ((aarch64_float_convert_int_split:int -> int -> int -> int -> FPConvOp -> int -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__0 l__1 n op part rounding unsigned=
+    (if ((((((l__0 = (( 16 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 16 : int):ii)  :  16 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op part rounding unsigned
+   else if ((((((l__0 = (( 16 : int):ii)))) /\ (((l__1 = (( 64 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 16 : int):ii)  :  16 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op part rounding unsigned
+   else if ((((((l__0 = (( 32 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 32 : int):ii)  :  32 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op part rounding unsigned
+   else if ((((((l__0 = (( 32 : int):ii)))) /\ (((l__1 = (( 64 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 32 : int):ii)  :  32 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op part rounding unsigned
+   else if ((((((l__0 = (( 64 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op part rounding unsigned
+   else if ((((((l__0 = (( 64 : int):ii)))) /\ (((l__1 = (( 64 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op part rounding unsigned
+   else if ((((((l__0 = (( 128 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then
+     aarch64_float_convert_int d ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op part rounding unsigned
+   else
+     aarch64_float_convert_int d ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op part rounding unsigned))`;
+
+
+(*val float_convert_int_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_convert_int_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 typ rmode opcode Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (intsize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+   (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+   (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (part : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (if (((((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) <> (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)))) then
+         UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS (( 128 : int):ii))
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS fltsize)) (\ (fltsize : ii) . 
+   let v__98 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+   (if (((((subrange_vec_dec v__98 (( 3 : int):ii) (( 2 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+      let (rounding : FPRounding) = (FPDecodeRounding rmode) in
+      let (unsigned : bool) =
+        ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+      let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+      sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned)
+    else if (((v__98 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+      let (rounding : FPRounding) = (FPRoundingMode w__0) in
+      let (unsigned : bool) =
+        ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+      let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+      sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned))
+    else if (((v__98 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+      let (rounding : FPRounding) = FPRounding_TIEAWAY in
+      let (unsigned : bool) =
+        ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+      let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+      sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned)
+    else if (((v__98 = (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$seqS
+      (if ((((((((ex_int fltsize)) <> (( 16 : int):ii)))) /\ (((((ex_int fltsize)) <> intsize)))))) then
+         UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (let (op : FPConvOp) =
+        (if ((((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+          FPConvOp_MOV_ItoF
+        else FPConvOp_MOV_FtoI) in
+      let (part : ii) = ((( 0 : int):ii)) in
+      sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned))
+    else if (((v__98 = (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)))) then sail2_state_monad$seqS
+      (if ((((((((ex_int intsize)) <> (( 64 : int):ii)))) \/ (((((ex_int fltsize)) <> (( 128 : int):ii))))))) then
+         UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (let (op : FPConvOp) =
+        (if ((((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+          FPConvOp_MOV_ItoF
+        else FPConvOp_MOV_FtoI) in
+      let (part : ii) = ((( 1 : int):ii)) in
+      let (fltsize : ii) = ((( 64 : int):ii)) in
+      sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned))
+    else sail2_state_monad$bindS
+      (if (((v__98 = (vec_of_bits [B1;B1;B1;B1]  :  4 words$word)))) then sail2_state_monad$seqS
+         (if ((~ ((HaveFJCVTZSExt () )))) then UnallocatedEncoding () 
+          else sail2_state_monad$returnS () )
+         (let (rounding : FPRounding) = FPRounding_ZERO in
+         let (unsigned : bool) =
+           ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+         let (op : FPConvOp) = FPConvOp_CVT_FtoI_JS in
+         sail2_state_monad$returnS (op, rounding, unsigned))
+       else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+        FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in
+      sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned))) (\ varstup .  let ((fltsize : ii), (op :
+     FPConvOp), (part : ii), (rounding : FPRounding), (unsigned : bool)) = varstup in
+   let fltsize2 = (ex_int fltsize) in sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS T "")
+   (aarch64_float_convert_int_split d fltsize2 intsize n op part rounding unsigned)))))))))))`;
+
+
+(*val float_convert_fp_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_convert_fp_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 b__0 b__1 Rn Rd=
+    (if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (srcsize : ii) . 
+     let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii)  :  64 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (sail2_state_monad$assert_expS T ""))
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii)  :  16 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 64 : int):ii)  :  64 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (srcsize : ii) . 
+     let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii)  :  64 itself)) n
+       ((make_the_value (( 64 : int):ii)  :  64 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (sail2_state_monad$assert_expS T ""))
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 64 : int):ii)  :  64 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii)  :  16 itself)) n
+       ((make_the_value (( 64 : int):ii)  :  64 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (dstsize : ii) . 
+     let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (dstsize : ii) . 
+     let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii)  :  64 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (srcsize : ii) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (dstsize : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (sail2_state_monad$assert_expS T ""))
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (dstsize : ii) . 
+     let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii)  :  16 itself)) n
+       ((make_the_value (( 32 : int):ii)  :  32 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 16 : int):ii)  :  16 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii)  :  64 itself)) n
+       ((make_the_value (( 16 : int):ii)  :  16 itself))))))
+   else if ((((((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (srcsize : ii) . 
+     let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (sail2_state_monad$assert_expS T ""))
+     (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii)  :  32 itself)) n
+       ((make_the_value (( 16 : int):ii)  :  16 itself))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (undefined_int () )) (\ (srcsize : ii) . 
+     let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (dstsize : ii) . 
+     let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii)  :  16 itself)) n
+       ((make_the_value (( 16 : int):ii)  :  16 itself))))))))`;
+
+
+(*val float_convert_fix_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty3 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_convert_fix_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(3)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 S1 b__1 rmode opcode scale Rn Rd=
+    (if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . 
+     let fltsize = ((( 32 : int):ii)) in sail2_state_monad$seqS
+     (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__2 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__2 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__2 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__0) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii)  :  32 itself)) fracbits
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op rounding unsigned))))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . 
+     let fltsize = ((( 64 : int):ii)) in sail2_state_monad$seqS
+     (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__6 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__6 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__6 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__1) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 64 : int):ii)  :  64 itself)) fracbits
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op rounding unsigned))))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__10 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__10 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__10 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__2) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii)  :  32 itself)) fracbits
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op rounding unsigned))))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . 
+     let fltsize = ((( 16 : int):ii)) in sail2_state_monad$seqS
+     (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__14 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__14 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__14 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__3) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 16 : int):ii)  :  16 itself)) fracbits
+       ((make_the_value (( 32 : int):ii)  :  32 itself)) n op rounding unsigned))))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . 
+     let fltsize = ((( 32 : int):ii)) in sail2_state_monad$seqS
+     (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__18 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__18 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__18 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__4 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__4) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii)  :  32 itself)) fracbits
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op rounding unsigned))))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . 
+     let fltsize = ((( 64 : int):ii)) in sail2_state_monad$seqS
+     (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__22 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__22 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__22 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__5 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__5) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 64 : int):ii)  :  64 itself)) fracbits
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op rounding unsigned))))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+     (UnallocatedEncoding () )
+     (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () ))
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__26 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__26 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__26 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__6) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii)  :  32 itself)) fracbits
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op rounding unsigned))))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (fltsize : ii) .  sail2_state_monad$bindS
+     (undefined_FPConvOp () ) (\ (op : FPConvOp) .  sail2_state_monad$bindS
+     (undefined_FPRounding () ) (\ (rounding : FPRounding) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . 
+     let fltsize = ((( 16 : int):ii)) in sail2_state_monad$seqS
+     (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word))))))) then
+        UnallocatedEncoding () 
+      else sail2_state_monad$returnS () )
+     (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in
+     let b__30 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii)  :  2 words$word)) rmode  :  4 words$word)) in sail2_state_monad$bindS
+     (if (((b__30 = (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)))) then
+        let (rounding : FPRounding) = FPRounding_ZERO in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_FtoI in
+        sail2_state_monad$returnS (op, rounding, unsigned)
+      else if (((b__30 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__7 :  32 words$word) . 
+        let (rounding : FPRounding) = (FPRoundingMode w__7) in
+        let (unsigned : bool) =
+          ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+        let (op : FPConvOp) = FPConvOp_CVT_ItoF in
+        sail2_state_monad$returnS (op, rounding, unsigned))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup .  let ((op :
+       FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS T "")
+     (aarch64_float_convert_fix d ((make_the_value (( 16 : int):ii)  :  16 itself)) fracbits
+       ((make_the_value (( 64 : int):ii)  :  64 itself)) n op rounding unsigned))))))))))`;
+
+
+(*val float_compare_uncond_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((float_compare_uncond_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(2)words$word ->(5)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn opc=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (signal_all_nans : bool) =
+     ((vec_of_bits [access_vec_dec opc (( 1 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+   let (cmp_with_zero : bool) =
+     ((vec_of_bits [access_vec_dec opc (( 0 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_float_compare_uncond cmp_with_zero datasize m n signal_all_nans)))))`;
+
+
+(*val float_compare_cond_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((float_compare_cond_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(4)words$word ->(5)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm cond Rn op nzcv1=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (signal_all_nans : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   let (condition : 4 bits) = cond in
+   let (flags : 4 bits) = nzcv1 in
+   aarch64_float_compare_cond condition datasize flags m n signal_all_nans)))))`;
+
+
+(*val float_arithmetic_unary_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_unary_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ opc Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) .  sail2_state_monad$bindS
+   (undefined_FPUnaryOp () ) (\ (fpop : FPUnaryOp) . 
+   let b__4 = opc in
+   let (fpop : FPUnaryOp) =
+     (if (((b__4 = (vec_of_bits [B0;B0]  :  2 words$word)))) then FPUnaryOp_MOV
+     else if (((b__4 = (vec_of_bits [B0;B1]  :  2 words$word)))) then FPUnaryOp_ABS
+     else if (((b__4 = (vec_of_bits [B1;B0]  :  2 words$word)))) then FPUnaryOp_NEG
+     else FPUnaryOp_SQRT) in
+   aarch64_float_arithmetic_unary d datasize fpop n))))))`;
+
+
+(*val float_arithmetic_round_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_round_decode:(1)words$word ->(1)words$word ->(2)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ rmode Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (exact : bool) = F in sail2_state_monad$bindS
+   (undefined_FPRounding () ) (\ (rounding : FPRounding) . 
+   let v__101 = rmode in sail2_state_monad$bindS
+   (if (((((subrange_vec_dec v__101 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) then
+      let (rounding : FPRounding) = (FPDecodeRounding ((slice rmode (( 0 : int):ii) (( 2 : int):ii)  :  2 words$word))) in
+      sail2_state_monad$returnS (exact, rounding)
+    else if (((v__101 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+      let (rounding : FPRounding) = FPRounding_TIEAWAY in
+      sail2_state_monad$returnS (exact, rounding)
+    else if (((v__101 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS (exact, rounding))
+    else if (((v__101 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+      let (rounding : FPRounding) = (FPRoundingMode w__0) in
+      let (exact : bool) = T in
+      sail2_state_monad$returnS (exact, rounding))
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS FPCR_ref  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+      let (rounding : FPRounding) = (FPRoundingMode w__1) in
+      sail2_state_monad$returnS (exact, rounding))) (\ varstup .  let ((exact : bool), (rounding : FPRounding)) = varstup in
+   aarch64_float_arithmetic_round d datasize exact n rounding)))))))`;
+
+
+(*val float_arithmetic_mul_product_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_mul_product_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (negated : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_float_arithmetic_mul_product d datasize m n negated)))))`;
+
+
+(*val float_arithmetic_mul_addsub_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_mul_addsub_decode:(1)words$word ->(1)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ o1 Rm o0 Ra Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (a : ii) = (lem$w2ui Ra) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (opa_neg : bool) = (o1 = (vec_of_bits [B1]  :  1 words$word)) in
+   let (op1_neg : bool) = (o0 <> o1) in
+   aarch64_float_arithmetic_mul_addsub a d datasize m n op1_neg opa_neg)))))`;
+
+
+(*val float_arithmetic_maxmin_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_maxmin_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) .  sail2_state_monad$bindS
+   (undefined_FPMaxMinOp () ) (\ (operation : FPMaxMinOp) . 
+   let b__4 = op in
+   let (operation : FPMaxMinOp) =
+     (if (((b__4 = (vec_of_bits [B0;B0]  :  2 words$word)))) then FPMaxMinOp_MAX
+     else if (((b__4 = (vec_of_bits [B0;B1]  :  2 words$word)))) then FPMaxMinOp_MIN
+     else if (((b__4 = (vec_of_bits [B1;B0]  :  2 words$word)))) then FPMaxMinOp_MAXNUM
+     else FPMaxMinOp_MINNUM) in
+   aarch64_float_arithmetic_maxmin d datasize m n operation))))))`;
+
+
+(*val float_arithmetic_div_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_div_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   aarch64_float_arithmetic_div d datasize m n)))))`;
+
+
+(*val float_arithmetic_addsub_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((float_arithmetic_addsub_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (datasize : ii) . 
+   let b__0 = typ in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii)
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii)
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$seqS
+      (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)
+    else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii)
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . 
+   let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_float_arithmetic_addsub d datasize m n sub_op)))))`;
+
+
+(*val branch_unconditional_register_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((branch_unconditional_register_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Z opc op op2 op3 A M Rn Rm=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+   (undefined_BranchType () ) (\ (branch_type : BranchType) . 
+   let (m : ii) = (lem$w2ui Rm) in
+   let (pac : bool) = (A = (vec_of_bits [B1]  :  1 words$word)) in
+   let (use_key_a : bool) = (M = (vec_of_bits [B0]  :  1 words$word)) in
+   let (source_is_sp : bool) =
+     ((((Z = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((ex_int m)) = (( 31 : int):ii))))) in sail2_state_monad$seqS
+   (if (((((~ pac)) /\ (((((ex_int m)) <> (( 0 : int):ii))))))) then UnallocatedEncoding () 
+    else if (((pac /\ ((~ ((HavePACExt () ))))))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (let b__0 = op in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then sail2_state_monad$returnS BranchType_JMP
+    else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then sail2_state_monad$returnS BranchType_CALL
+    else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then sail2_state_monad$returnS BranchType_RET
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS branch_type)) (\ (branch_type : BranchType) .  sail2_state_monad$bindS
+   (if pac then sail2_state_monad$seqS
+      (if ((((((Z = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((ex_int m)) <> (( 31 : int):ii)))))))
+       then
+         UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (if (((branch_type = BranchType_RET))) then sail2_state_monad$seqS
+        (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () 
+         else sail2_state_monad$returnS () )
+        (let (n : ii) = ((( 30 : int):ii)) in
+        let (source_is_sp : bool) = T in
+        sail2_state_monad$returnS (n, source_is_sp))
+      else sail2_state_monad$returnS (n, source_is_sp))
+    else sail2_state_monad$returnS (n, source_is_sp)) (\ varstup .  let ((n : ii), (source_is_sp : bool)) = varstup in
+   aarch64_branch_unconditional_register branch_type m n pac source_is_sp use_key_a)))))))`;
+
+
+(*val branch_unconditional_eret_decode : mword ty4 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((branch_unconditional_eret_decode:(4)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc op2 op3 A M Rn op4=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) .  sail2_state_monad$seqS
+   (if (((w__0.ProcState_EL = EL0))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (let (pac : bool) = (A = (vec_of_bits [B1]  :  1 words$word)) in
+   let (use_key_a : bool) = (M = (vec_of_bits [B0]  :  1 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if (((((~ pac)) /\ (((op4 <> (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+      UnallocatedEncoding () 
+    else if (((pac /\ (((((~ ((HavePACExt () )))) \/ (((op4 <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))))))))) then
+      UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if (((Rn <> (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () ))
+   (aarch64_branch_unconditional_eret pac use_key_a)))))`;
+
+
+(*val branch_unconditional_dret_decode : mword ty4 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((branch_unconditional_dret_decode:(4)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc op2 op3 Rt op4=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (sail2_state$or_boolS ( sail2_state_monad$bindS(Halted () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) .  sail2_state_monad$returnS (((w__1.ProcState_EL = EL0))))))) (\ (w__2 :
+     bool) .  sail2_state_monad$seqS
+   (if w__2 then UnallocatedEncoding ()  else sail2_state_monad$returnS () ) (aarch64_branch_unconditional_dret () ))))`;
+
+
+(*val AArch64_CheckSystemAccess : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((AArch64_CheckSystemAccess:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 rt read=
+    (let (unallocated : bool) = F in
+   let (need_secure : bool) = F in sail2_state_monad$bindS
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M) (\ (min_EL : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (rcs_el0_trap : bool) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+              ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+            sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 20 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+        (sail2_state_monad$returnS (((((and_vec op0 (vec_of_bits [B0;B1]  :  2 words$word)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))
+     (sail2_state_monad$returnS (((((and_vec crn (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)  :  4 words$word)) = (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)))))) (\ (w__5 : bool) .  sail2_state_monad$seqS
+   (if w__5 then sail2_state_monad$bindS
+      (sail2_state_monad$undefined_boolS () ) (\ (w__6 : bool) . 
+      let rcs_el0_trap = w__6 in sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) .  sail2_state_monad$returnS (((w__7.ProcState_EL = EL0)))))
+        (sail2_state_monad$returnS rcs_el0_trap)) (\ (w__8 : bool) . 
+      if w__8 then AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . 
+        if (((w__9.ProcState_EL = EL1))) then
+          AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read
+        else sail2_state_monad$returnS () )))
+    else sail2_state_monad$returnS () )
+   (let v__103 = op1 in sail2_state_monad$bindS
+   (if (((((subrange_vec_dec v__103 (( 2 : int):ii) (( 1 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+      let (min_EL : 2 bits) = EL1 in
+      sail2_state_monad$returnS (min_EL, need_secure)
+    else if (((v__103 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+      let (min_EL : 2 bits) = EL1 in
+      sail2_state_monad$returnS (min_EL, need_secure)
+    else if (((v__103 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+      let (min_EL : 2 bits) = EL0 in
+      sail2_state_monad$returnS (min_EL, need_secure)
+    else if (((v__103 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+      let (min_EL : 2 bits) = EL2 in
+      sail2_state_monad$returnS (min_EL, need_secure)
+    else if (((v__103 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then sail2_state_monad$seqS
+      (if ((~ ((HaveVirtHostExt () )))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (let (min_EL : 2 bits) = EL2 in
+      sail2_state_monad$returnS (min_EL, need_secure))
+    else
+      let ((min_EL : 2 bits), (need_secure : bool)) =
+        (if (((v__103 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+          let (min_EL : 2 bits) = EL3 in
+          (min_EL, need_secure)
+        else
+          let (min_EL : 2 bits) = EL1 in
+          let (need_secure : bool) = T in
+          (min_EL, need_secure)) in
+      sail2_state_monad$returnS (min_EL, need_secure)) (\ varstup .  let ((min_EL : 2 bits), (need_secure : bool)) = varstup in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((((lem$w2ui w__10.ProcState_EL)) < ((lem$w2ui min_EL)))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS
+              (sail2_state$and_boolS
+                 (sail2_state$and_boolS
+                    ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+                     sail2_state_monad$returnS (((w__11.ProcState_EL = EL1))))) (sail2_state_monad$returnS (((min_EL = EL2)))))
+                 (sail2_state_monad$returnS ((HaveNVExt () ))))
+              ( sail2_state_monad$bindS(IsSecure () ) (\ (w__14 : bool) .  sail2_state_monad$returnS ((~ w__14))))) (sail2_state_monad$returnS ((HaveEL EL2))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__17 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__18 : bool) . 
+      if w__18 then AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read
+      else UnallocatedEncoding () )
+    else sail2_state_monad$bindS
+      (sail2_state$and_boolS (sail2_state_monad$returnS need_secure) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__19 : bool) .  sail2_state_monad$returnS ((~ w__19))))) (\ (w__20 :
+        bool) . 
+      if w__20 then UnallocatedEncoding () 
+      else sail2_state_monad$bindS
+        (AArch64_CheckUnallocatedSystemAccess op0 op1 crn crm op2 read) (\ (w__21 : bool) . 
+        if w__21 then UnallocatedEncoding () 
+        else sail2_state_monad$returnS () )))
+   (undefined_bitvector (( 2 : int):ii)  : ( 2 words$word) M)) (\ (target_el : 2 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (take_trap : bool) .  sail2_state_monad$bindS
+   (AArch64_CheckAdvSIMDFPSystemRegisterTraps op0 op1 crn crm op2 read  : ((bool #  2 words$word)) M) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let take_trap = tup__0 in
+   let target_el = tup__1 in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if take_trap then AArch64_AdvSIMDFPAccessTrap target_el
+    else sail2_state_monad$returnS () )
+   (AArch64_CheckSystemRegisterTraps op0 op1 crn crm op2 read  : ((bool #  2 words$word)) M)) (\ varstup .  let (tup__0, tup__1) = varstup in
+   let take_trap = tup__0 in
+   let target_el = tup__1 in
+   if take_trap then AArch64_SystemRegisterTrap target_el op0 op2 op1 crn rt crm read
+   else sail2_state_monad$returnS () ))))))))))))`;
+
+
+(*val system_sysops_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((system_sysops_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (AArch64_CheckSystemAccess (vec_of_bits [B0;B1]  :  2 words$word) op1 CRn CRm op2 Rt L))
+   (let (t : ii) = (lem$w2ui Rt) in
+   let (sys_op0 : ii) = ((( 1 : int):ii)) in
+   let (sys_op1 : ii) = (lem$w2ui op1) in
+   let (sys_op2 : ii) = (lem$w2ui op2) in
+   let (sys_crn : ii) = (lem$w2ui CRn) in
+   let (sys_crm : ii) = (lem$w2ui CRm) in
+   let (has_result : bool) = (L = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t)))`;
+
+
+(*val system_register_system_decode : mword ty1 -> mword ty1 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((system_register_system_decode:(1)words$word ->(1)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L o0 op1 CRn CRm op2 Rt=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (AArch64_CheckSystemAccess ((concat_vec (vec_of_bits [B1]  :  1 words$word) o0  :  2 words$word)) op1 CRn
+     CRm op2 Rt L))
+   (let (t : ii) = (lem$w2ui Rt) in
+   let (sys_op0 : ii) = ((( 2 : int):ii) + ((lem$w2ui o0))) in
+   let (sys_op1 : ii) = (lem$w2ui op1) in
+   let (sys_op2 : ii) = (lem$w2ui op2) in
+   let (sys_crn : ii) = (lem$w2ui CRn) in
+   let (sys_crm : ii) = (lem$w2ui CRm) in
+   let (read : bool) = (L = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t)))`;
+
+
+(*val system_register_cpsr_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((system_register_cpsr_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (AArch64_CheckSystemAccess (vec_of_bits [B0;B0]  :  2 words$word) op1
+     (vec_of_bits [B0;B1;B0;B0]  :  4 words$word) CRm op2 (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)
+     (vec_of_bits [B0]  :  1 words$word)))
+   (let (operand : 4 bits) = CRm in sail2_state_monad$bindS
+   (undefined_PSTATEField () ) (\ (field' : PSTATEField) . 
+   let b__0 = ((concat_vec op1 op2  :  6 words$word)) in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word)))) then sail2_state_monad$seqS
+      (if ((~ ((HaveUAOExt () )))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS PSTATEField_UAO)
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0]  :  6 words$word)))) then sail2_state_monad$seqS
+      (if ((~ ((HavePANExt () )))) then UnallocatedEncoding () 
+       else sail2_state_monad$returnS () )
+      (sail2_state_monad$returnS PSTATEField_PAN)
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1]  :  6 words$word)))) then
+      sail2_state_monad$returnS PSTATEField_SP
+    else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0]  :  6 words$word)))) then
+      sail2_state_monad$returnS PSTATEField_DAIFSet
+    else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B1]  :  6 words$word)))) then
+      sail2_state_monad$returnS PSTATEField_DAIFClr
+    else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS field')) (\ (field' : PSTATEField) .  sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS (((op1 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$returnS (((w__0.ProcState_EL = EL0))))))
+     (sail2_state$or_boolS ((IsInHost () ))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL1_ref  : ( 32 words$word) M) (\ (w__3 : 32 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 9 : int):ii)]  :  1 words$word) = (vec_of_bits [B0]  :  1 words$word)))))))) (\ (w__5 : bool) .  sail2_state_monad$seqS
+   (if w__5 then
+      AArch64_SystemRegisterTrap EL1 (vec_of_bits [B0;B0]  :  2 words$word) op2 op1
+        (vec_of_bits [B0;B1;B0;B0]  :  4 words$word) (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) CRm
+        (vec_of_bits [B0]  :  1 words$word)
+    else sail2_state_monad$returnS () )
+   (aarch64_system_register_cpsr field' operand)))))))`;
+
+
+(*val AArch64_CheckForSMCUndefOrTrap : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((AArch64_CheckForSMCUndefOrTrap:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if (((w__0.ProcState_EL = EL0))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$undefined_boolS () )) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (if ((~ ((HaveEL EL3)))) then sail2_state_monad$bindS
+      (sail2_state$and_boolS
+        (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+           ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1)))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) .  sail2_state_monad$returnS (((w__3.ProcState_EL = EL1)))))) (\ (w__4 :
+        bool) . 
+      if w__4 then sail2_state_monad$bindS
+        (sail2_state$and_boolS
+          (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveNVExt () )))
+             ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__5 : 64 bits) . 
+              sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 42 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__7 : 64 bits) . 
+           sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (w__8 : bool) . 
+        if w__8 then sail2_state_monad$returnS T
+        else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS route_to_el2))
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS route_to_el2))
+    else
+      sail2_state$and_boolS
+        (sail2_state$and_boolS
+           (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2)))
+              ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9)))))
+           ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . 
+            sail2_state_monad$returnS (((w__11.ProcState_EL = EL1))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref  : ( 64 words$word) M) (\ (w__13 : 64 bits) . 
+         sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 19 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) (\ (route_to_el2 : bool) .  sail2_state_monad$bindS
+   (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) .  sail2_state_monad$bindS
+   (undefined_int () ) (\ (vect_offset : ii) . 
+   if route_to_el2 then sail2_state_monad$bindS
+     (ThisInstrAddr (( 64 : int):ii) ()   : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . 
+     let vect_offset = ((( 0 : int):ii)) in sail2_state_monad$bindS
+     (ExceptionSyndrome Exception_MonitorCall) (\ (w__15 : ExceptionRecord) . 
+     let exception = w__15 in
+     let (tmp_40 : 25 bits) = (exception.ExceptionRecord_syndrome) in
+     let tmp_40 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_40 (( 0 : int):ii) imm  :  25 words$word)) in
+     let exception = ((exception with<| ExceptionRecord_syndrome := tmp_40|>)) in
+     AArch64_TakeException EL2 exception preferred_exception_return vect_offset))
+   else sail2_state_monad$returnS () )))))))`;
+
+
+(*val aarch64_system_exceptions_runtime_smc : mword ty16 -> M unit*)
+
+val _ = Define `
+ ((aarch64_system_exceptions_runtime_smc:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (AArch64_CheckForSMCUndefOrTrap imm)
+   (sail2_state_monad$read_regS SCR_EL3_ref  : ( 32 words$word) M)) (\ (w__0 : 32 bits) . 
+   if ((((vec_of_bits [access_vec_dec w__0 (( 7 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word)))) then
+     AArch64_UndefinedFault () 
+   else AArch64_CallSecureMonitor imm)))`;
+
+
+(*val system_exceptions_runtime_smc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((system_exceptions_runtime_smc_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (imm : 16 bits) = imm16 in
+   aarch64_system_exceptions_runtime_smc imm)))`;
+
+
+(*val ReservedValue : unit -> M unit*)
+
+val _ = Define `
+ ((ReservedValue:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$and_boolS ((UsingAArch32 () ))
+     ( sail2_state_monad$bindS(AArch32_GeneralExceptionsToAArch64 () ) (\ (w__1 : bool) .  sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 :
+     bool) . 
+   if w__2 then AArch32_TakeUndefInstrException__0 () 
+   else AArch64_UndefinedFault () )))`;
+
+
+(*val memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode:(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L Rm opcode b__1 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__2 = opcode in sail2_state_monad$bindS
+     (if (((b__2 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 8 : int):ii)  :  8 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__11 = opcode in sail2_state_monad$bindS
+     (if (((b__11 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 16 : int):ii)  :  16 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__20 = opcode in sail2_state_monad$bindS
+     (if (((b__20 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 32 : int):ii)  :  32 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__29 = opcode in sail2_state_monad$bindS
+     (if (((b__29 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((T /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 64 : int):ii)  :  64 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__38 = opcode in sail2_state_monad$bindS
+     (if (((b__38 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 8 : int):ii)  :  8 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__47 = opcode in sail2_state_monad$bindS
+     (if (((b__47 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 16 : int):ii)  :  16 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__56 = opcode in sail2_state_monad$bindS
+     (if (((b__56 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 32 : int):ii)  :  32 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (m : ii) = (lem$w2ui Rm) in
+     let (wback : bool) = T in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__65 = opcode in sail2_state_monad$bindS
+     (if (((b__65 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 64 : int):ii)  :  64 itself)) m memop n ((ex_int rpt))
+       ((ex_int selem)) t T)))))))`;
+
+
+(*val memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode : mword ty1 -> mword ty1 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode:(1)words$word ->(1)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L opcode b__1 Rn Rt=
+    (if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__2 = opcode in sail2_state_monad$bindS
+     (if (((b__2 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__2 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__0 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 8 : int):ii)  :  8 itself)) w__0 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__11 = opcode in sail2_state_monad$bindS
+     (if (((b__11 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__11 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__1 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 16 : int):ii)  :  16 itself)) w__1 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__20 = opcode in sail2_state_monad$bindS
+     (if (((b__20 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__20 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__2 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 32 : int):ii)  :  32 itself)) w__2 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     let (elements : ii) = ((( 64 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__29 = opcode in sail2_state_monad$bindS
+     (if (((b__29 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__29 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((T /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__3 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii)  :  64 itself))
+       ((ex_int elements)) ((make_the_value (( 64 : int):ii)  :  64 itself)) w__3 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 8 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__38 = opcode in sail2_state_monad$bindS
+     (if (((b__38 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__38 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__4 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 8 : int):ii)  :  8 itself)) w__4 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 16 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__47 = opcode in sail2_state_monad$bindS
+     (if (((b__47 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__47 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__5 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 16 : int):ii)  :  16 itself)) w__5 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else if ((((((b__0 = (vec_of_bits [B1]  :  1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word))))))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 32 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__56 = opcode in sail2_state_monad$bindS
+     (if (((b__56 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__56 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__6 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 32 : int):ii)  :  32 itself)) w__6 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (t : ii) = (lem$w2ui Rt) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (m : ii) . 
+     let (wback : bool) = F in
+     let (memop : MemOp) =
+       (if (((L = (vec_of_bits [B1]  :  1 words$word)))) then MemOp_LOAD
+       else MemOp_STORE) in
+     let (esize : ii) = ((( 64 : int):ii)) in
+     let (elements : ii) = ((( 128 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS
+     (undefined_int () ) (\ (rpt : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (selem : ii) . 
+     let b__65 = opcode in sail2_state_monad$bindS
+     (if (((b__65 = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 4 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 4 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 3 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 3 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 1 : int):ii)) in
+        let (selem : ii) = ((( 2 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else if (((b__65 = (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)))) then
+        let (rpt : ii) = ((( 2 : int):ii)) in
+        let (selem : ii) = ((( 1 : int):ii)) in
+        sail2_state_monad$returnS (rpt, selem)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup .  let ((rpt : ii), (selem :
+       ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_int () )) (\ (w__7 : ii) . 
+     aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii)  :  128 itself))
+       ((ex_int elements)) ((make_the_value (( 64 : int):ii)  :  64 itself)) w__7 memop n ((ex_int rpt))
+       ((ex_int selem)) t F))))))))`;
+
+
+(*val integer_logical_shiftedreg_decode : mword ty1 -> mword ty2 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_logical_shiftedreg_decode:(1)words$word ->(2)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf opc shift N Rm imm6 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (setflags : bool) .  sail2_state_monad$bindS
+   (undefined_LogicalOp () ) (\ (op : LogicalOp) . 
+   let b__0 = opc in
+   let ((op : LogicalOp), (setflags : bool)) =
+     (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+       let (op : LogicalOp) = LogicalOp_AND in
+       let (setflags : bool) = F in
+       (op, setflags)
+     else
+       let ((op : LogicalOp), (setflags : bool)) =
+         (if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+           let (op : LogicalOp) = LogicalOp_ORR in
+           let (setflags : bool) = F in
+           (op, setflags)
+         else
+           let ((op : LogicalOp), (setflags : bool)) =
+             (if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+               let (op : LogicalOp) = LogicalOp_EOR in
+               let (setflags : bool) = F in
+               (op, setflags)
+             else
+               let (op : LogicalOp) = LogicalOp_AND in
+               let (setflags : bool) = T in
+               (op, setflags)) in
+           (op, setflags)) in
+       (op, setflags)) in sail2_state_monad$seqS
+   (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((vec_of_bits [access_vec_dec imm6 (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+      ReservedValue () 
+    else sail2_state_monad$returnS () )
+   (let (shift_type : ShiftType) = (DecodeShift shift) in
+   let (shift_amount : ii) = (lem$w2ui imm6) in
+   let (invert : bool) = (N = (vec_of_bits [B1]  :  1 words$word)) in
+   aarch64_integer_logical_shiftedreg d datasize invert m n op setflags shift_amount shift_type))))))`;
+
+
+(*val integer_insext_extract_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_insext_extract_immediate_decode:(1)words$word ->(2)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op21 N o0 Rm imms Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in sail2_state_monad$bindS
+   (undefined_int () ) (\ (lsb : ii) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if (((N <> sf))) then UnallocatedEncoding () 
+    else sail2_state_monad$returnS () )
+   (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((vec_of_bits [access_vec_dec imms (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+      ReservedValue () 
+    else sail2_state_monad$returnS () ))
+   (let lsb = (lem$w2ui imms) in
+   aarch64_integer_insext_extract_immediate d datasize lsb m n)))))`;
+
+
+(*val integer_arithmetic_addsub_shiftedreg_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_addsub_shiftedreg_decode:(1)words$word ->(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 shift Rm imm6 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   let (setflags : bool) = (S1 = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if (((shift = (vec_of_bits [B1;B1]  :  2 words$word)))) then ReservedValue () 
+    else sail2_state_monad$returnS () )
+   (if ((((((sf = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((vec_of_bits [access_vec_dec imm6 (( 5 : int):ii)]  :  1 words$word) = (vec_of_bits [B1]  :  1 words$word))))))) then
+      ReservedValue () 
+    else sail2_state_monad$returnS () ))
+   (let (shift_type : ShiftType) = (DecodeShift shift) in
+   let (shift_amount : ii) = (lem$w2ui imm6) in
+   aarch64_integer_arithmetic_addsub_shiftedreg d datasize m n setflags shift_amount shift_type
+     sub_op))))`;
+
+
+(*val integer_arithmetic_addsub_immediate_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_addsub_immediate_decode:(1)words$word ->(1)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 op S1 shift imm12 Rn Rd=
+    (if (((b__0 = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+     let (setflags : bool) = (S1 = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (imm : 32 bits) . 
+     let b__1 = shift in sail2_state_monad$bindS
+     (if (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+        (ZeroExtend__0 imm12 ((make_the_value (( 32 : int):ii)  :  32 itself))  : ( 32 words$word) M)
+      else if (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+        (ZeroExtend__0
+           ((concat_vec imm12 ((Zeros__0 ((make_the_value (( 12 : int):ii)  :  12 itself))  :  12 words$word))
+              :  24 words$word)) ((make_the_value (( 32 : int):ii)  :  32 itself))
+          : ( 32 words$word) M)
+      else sail2_state_monad$seqS (ReservedValue () ) (sail2_state_monad$returnS imm)) (\ (imm : 32 bits) . 
+     aarch64_integer_arithmetic_addsub_immediate d ((make_the_value (( 32 : int):ii)  :  32 itself)) imm n
+       setflags sub_op)))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in
+     let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+     let (setflags : bool) = (S1 = (vec_of_bits [B1]  :  1 words$word)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (imm : 64 bits) . 
+     let b__4 = shift in sail2_state_monad$bindS
+     (if (((b__4 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+        (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii)  :  64 itself))  : ( 64 words$word) M)
+      else if (((b__4 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+        (ZeroExtend__0
+           ((concat_vec imm12 ((Zeros__0 ((make_the_value (( 12 : int):ii)  :  12 itself))  :  12 words$word))
+              :  24 words$word)) ((make_the_value (( 64 : int):ii)  :  64 itself))
+          : ( 64 words$word) M)
+      else sail2_state_monad$seqS (ReservedValue () ) (sail2_state_monad$returnS imm)) (\ (imm : 64 bits) . 
+     aarch64_integer_arithmetic_addsub_immediate d ((make_the_value (( 64 : int):ii)  :  64 itself)) imm n
+       setflags sub_op)))))`;
+
+
+(*val integer_arithmetic_addsub_extendedreg_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_arithmetic_addsub_extendedreg_decode:(1)words$word ->(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(3)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 opt Rm option_name imm3 Rn Rd=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref T)
+   (let (d : ii) = (lem$w2ui Rd) in
+   let (n : ii) = (lem$w2ui Rn) in
+   let (m : ii) = (lem$w2ui Rm) in
+   let (datasize : int) =
+     (if (((sf = (vec_of_bits [B1]  :  1 words$word)))) then (( 64 : int):ii)
+     else (( 32 : int):ii)) in
+   let (sub_op : bool) = (op = (vec_of_bits [B1]  :  1 words$word)) in
+   let (setflags : bool) = (S1 = (vec_of_bits [B1]  :  1 words$word)) in
+   let (extend_type : ExtendType) = (DecodeRegExtend option_name) in
+   let (shift : ii) = (lem$w2ui imm3) in sail2_state_monad$seqS
+   (if ((((ex_int shift)) > (( 4 : int):ii))) then ReservedValue () 
+    else sail2_state_monad$returnS () )
+   (aarch64_integer_arithmetic_addsub_extendedreg d datasize extend_type m n setflags shift sub_op))))`;
+
+
+(*val DecodeBitMasks : forall 'M . Size 'M => integer -> mword ty1 -> mword ty6 -> mword ty6 -> bool -> M (mword 'M * mword 'M)*)
+
+val _ = Define `
+ ((DecodeBitMasks:int ->(1)words$word ->(6)words$word ->(6)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((('M words$word#'M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) immN imms immr immediate=  (sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (tmask : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (wmask : 64 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (tmask_and : 6 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (wmask_and : 6 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (tmask_or : 6 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (wmask_or : 6 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector (( 6 : int):ii)  : ( 6 words$word) M) (\ (levels : 6 bits) .  sail2_state_monad$bindS
+   (HighestSetBit ((concat_vec immN ((not_vec imms  :  6 words$word))  :  7 words$word))) (\ len .  sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS ((len >= (( 0 : int):ii))) "")
+   (if ((len < (( 1 : int):ii))) then ReservedValue () 
+    else sail2_state_monad$returnS () ))
+   (sail2_state_monad$assert_expS ((M__tv >= ((ex_int ((shl_int (( 1 : int):ii) len)))))) "(M >= (1 << len))"))
+   (let levels = ((zext_ones (( 6 : int):ii) len  :  6 words$word)) in sail2_state_monad$seqS
+   (if (((immediate /\ (((((and_vec imms levels  :  6 words$word)) = levels)))))) then
+      ReservedValue () 
+    else sail2_state_monad$returnS () )
+   (let (S1 : ii) = (lem$w2ui ((and_vec imms levels  :  6 words$word))) in
+   let (R1 : ii) = (lem$w2ui ((and_vec immr levels  :  6 words$word))) in
+   let (diff : ii) = (((ex_int S1)) - ((ex_int R1))) in
+   let (tmask_and : 6 bits) =
+     ((or_vec ((GetSlice_int ((make_the_value (( 6 : int):ii)  :  6 itself)) diff (( 0 : int):ii)  :  6 words$word))
+        ((not_vec levels  :  6 words$word))
+       :  6 words$word)) in
+   let (tmask_or : 6 bits) =
+     ((and_vec ((GetSlice_int ((make_the_value (( 6 : int):ii)  :  6 itself)) diff (( 0 : int):ii)  :  6 words$word))
+        levels
+       :  6 words$word)) in
+   let (tmask : 64 bits) = ((Ones__0 ((make_the_value (( 64 : int):ii)  :  64 itself))  :  64 words$word)) in
+   let (tmask : 64 bits) =
+     ((or_vec
+        ((and_vec tmask
+            ((replicate_bits
+                ((concat_vec
+                    ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 0 : int):ii)]  :  1 words$word)
+                        (( 1 : int):ii)
+                       :  1 words$word))
+                    ((Ones__0 ((make_the_value (( 1 : int):ii)  :  1 itself))  :  1 words$word))
+                   :  2 words$word)) (( 32 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec ((Zeros__0 ((make_the_value (( 1 : int):ii)  :  1 itself))  :  1 words$word))
+                ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 0 : int):ii)]  :  1 words$word) (( 1 : int):ii)
+                   :  1 words$word))
+               :  2 words$word)) (( 32 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (tmask : 64 bits) =
+     ((or_vec
+        ((and_vec tmask
+            ((replicate_bits
+                ((concat_vec
+                    ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 1 : int):ii)]  :  1 words$word)
+                        (( 2 : int):ii)
+                       :  2 words$word))
+                    ((Ones__0 ((make_the_value (( 2 : int):ii)  :  2 itself))  :  2 words$word))
+                   :  4 words$word)) (( 16 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec ((Zeros__0 ((make_the_value (( 2 : int):ii)  :  2 itself))  :  2 words$word))
+                ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 1 : int):ii)]  :  1 words$word) (( 2 : int):ii)
+                   :  2 words$word))
+               :  4 words$word)) (( 16 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (tmask : 64 bits) =
+     ((or_vec
+        ((and_vec tmask
+            ((replicate_bits
+                ((concat_vec
+                    ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 2 : int):ii)]  :  1 words$word)
+                        (( 4 : int):ii)
+                       :  4 words$word))
+                    ((Ones__0 ((make_the_value (( 4 : int):ii)  :  4 itself))  :  4 words$word))
+                   :  8 words$word)) (( 8 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec ((Zeros__0 ((make_the_value (( 4 : int):ii)  :  4 itself))  :  4 words$word))
+                ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 2 : int):ii)]  :  1 words$word) (( 4 : int):ii)
+                   :  4 words$word))
+               :  8 words$word)) (( 8 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (tmask : 64 bits) =
+     ((or_vec
+        ((and_vec tmask
+            ((replicate_bits
+                ((concat_vec
+                    ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 3 : int):ii)]  :  1 words$word)
+                        (( 8 : int):ii)
+                       :  8 words$word))
+                    ((Ones__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word))
+                   :  16 words$word)) (( 4 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec ((Zeros__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word))
+                ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 3 : int):ii)]  :  1 words$word) (( 8 : int):ii)
+                   :  8 words$word))
+               :  16 words$word)) (( 4 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (tmask : 64 bits) =
+     ((or_vec
+        ((and_vec tmask
+            ((replicate_bits
+                ((concat_vec
+                    ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 4 : int):ii)]  :  1 words$word)
+                        (( 16 : int):ii)
+                       :  16 words$word))
+                    ((Ones__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+                   :  32 words$word)) (( 2 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec ((Zeros__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+                ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 4 : int):ii)]  :  1 words$word) (( 16 : int):ii)
+                   :  16 words$word))
+               :  32 words$word)) (( 2 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (tmask : 64 bits) =
+     ((or_vec
+        ((and_vec tmask
+            ((replicate_bits
+                ((concat_vec
+                    ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 5 : int):ii)]  :  1 words$word)
+                        (( 32 : int):ii)
+                       :  32 words$word))
+                    ((Ones__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+                   :  64 words$word)) (( 1 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+                ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 5 : int):ii)]  :  1 words$word) (( 32 : int):ii)
+                   :  32 words$word))
+               :  64 words$word)) (( 1 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask_and : 6 bits) = ((or_vec immr ((not_vec levels  :  6 words$word))  :  6 words$word)) in
+   let (wmask_or : 6 bits) = ((and_vec immr levels  :  6 words$word)) in
+   let (wmask : 64 bits) = ((Zeros__0 ((make_the_value (( 64 : int):ii)  :  64 itself))  :  64 words$word)) in
+   let (wmask : 64 bits) =
+     ((or_vec
+        ((and_vec wmask
+            ((replicate_bits
+                ((concat_vec ((Ones__0 ((make_the_value (( 1 : int):ii)  :  1 itself))  :  1 words$word))
+                    ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 0 : int):ii)]  :  1 words$word)
+                        (( 1 : int):ii)
+                       :  1 words$word))
+                   :  2 words$word)) (( 32 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec
+                ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 0 : int):ii)]  :  1 words$word) (( 1 : int):ii)
+                   :  1 words$word)) ((Zeros__0 ((make_the_value (( 1 : int):ii)  :  1 itself))  :  1 words$word))
+               :  2 words$word)) (( 32 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask : 64 bits) =
+     ((or_vec
+        ((and_vec wmask
+            ((replicate_bits
+                ((concat_vec ((Ones__0 ((make_the_value (( 2 : int):ii)  :  2 itself))  :  2 words$word))
+                    ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 1 : int):ii)]  :  1 words$word)
+                        (( 2 : int):ii)
+                       :  2 words$word))
+                   :  4 words$word)) (( 16 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec
+                ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 1 : int):ii)]  :  1 words$word) (( 2 : int):ii)
+                   :  2 words$word)) ((Zeros__0 ((make_the_value (( 2 : int):ii)  :  2 itself))  :  2 words$word))
+               :  4 words$word)) (( 16 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask : 64 bits) =
+     ((or_vec
+        ((and_vec wmask
+            ((replicate_bits
+                ((concat_vec ((Ones__0 ((make_the_value (( 4 : int):ii)  :  4 itself))  :  4 words$word))
+                    ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 2 : int):ii)]  :  1 words$word)
+                        (( 4 : int):ii)
+                       :  4 words$word))
+                   :  8 words$word)) (( 8 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec
+                ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 2 : int):ii)]  :  1 words$word) (( 4 : int):ii)
+                   :  4 words$word)) ((Zeros__0 ((make_the_value (( 4 : int):ii)  :  4 itself))  :  4 words$word))
+               :  8 words$word)) (( 8 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask : 64 bits) =
+     ((or_vec
+        ((and_vec wmask
+            ((replicate_bits
+                ((concat_vec ((Ones__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word))
+                    ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 3 : int):ii)]  :  1 words$word)
+                        (( 8 : int):ii)
+                       :  8 words$word))
+                   :  16 words$word)) (( 4 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec
+                ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 3 : int):ii)]  :  1 words$word) (( 8 : int):ii)
+                   :  8 words$word)) ((Zeros__0 ((make_the_value (( 8 : int):ii)  :  8 itself))  :  8 words$word))
+               :  16 words$word)) (( 4 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask : 64 bits) =
+     ((or_vec
+        ((and_vec wmask
+            ((replicate_bits
+                ((concat_vec ((Ones__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+                    ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 4 : int):ii)]  :  1 words$word)
+                        (( 16 : int):ii)
+                       :  16 words$word))
+                   :  32 words$word)) (( 2 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec
+                ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 4 : int):ii)]  :  1 words$word) (( 16 : int):ii)
+                   :  16 words$word))
+                ((Zeros__0 ((make_the_value (( 16 : int):ii)  :  16 itself))  :  16 words$word))
+               :  32 words$word)) (( 2 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask : 64 bits) =
+     ((or_vec
+        ((and_vec wmask
+            ((replicate_bits
+                ((concat_vec ((Ones__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+                    ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 5 : int):ii)]  :  1 words$word)
+                        (( 32 : int):ii)
+                       :  32 words$word))
+                   :  64 words$word)) (( 1 : int):ii)
+               :  64 words$word))
+           :  64 words$word))
+        ((replicate_bits
+            ((concat_vec
+                ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 5 : int):ii)]  :  1 words$word) (( 32 : int):ii)
+                   :  32 words$word))
+                ((Zeros__0 ((make_the_value (( 32 : int):ii)  :  32 itself))  :  32 words$word))
+               :  64 words$word)) (( 1 : int):ii)
+           :  64 words$word))
+       :  64 words$word)) in
+   let (wmask : 64 bits) =
+     (if (((((GetSlice_int ((make_the_value (( 1 : int):ii)  :  1 itself)) diff (( 6 : int):ii)  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word)))) then
+       (and_vec wmask tmask  :  64 words$word)
+     else (or_vec wmask tmask  :  64 words$word)) in
+   sail2_state_monad$returnS ((slice wmask (( 0 : int):ii) M__tv  :  'M words$word), (slice tmask (( 0 : int):ii) M__tv  :  'M words$word))))))))))))))`;
+
+
+(*val integer_logical_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_logical_immediate_decode:(1)words$word ->(2)words$word ->(1)words$word ->(6)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 opc N immr imms Rn Rd=
+    (if (((b__0 = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (setflags : bool) .  sail2_state_monad$bindS
+     (undefined_LogicalOp () ) (\ (op : LogicalOp) . 
+     let b__1 = opc in
+     let ((op : LogicalOp), (setflags : bool)) =
+       (if (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+         let (op : LogicalOp) = LogicalOp_AND in
+         let (setflags : bool) = F in
+         (op, setflags)
+       else
+         let ((op : LogicalOp), (setflags : bool)) =
+           (if (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+             let (op : LogicalOp) = LogicalOp_ORR in
+             let (setflags : bool) = F in
+             (op, setflags)
+           else
+             let ((op : LogicalOp), (setflags : bool)) =
+               (if (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+                 let (op : LogicalOp) = LogicalOp_EOR in
+                 let (setflags : bool) = F in
+                 (op, setflags)
+               else
+                 let (op : LogicalOp) = LogicalOp_AND in
+                 let (setflags : bool) = T in
+                 (op, setflags)) in
+             (op, setflags)) in
+         (op, setflags)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (imm : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((T /\ (((N <> (vec_of_bits [B0]  :  1 words$word))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (anon10 : 32 bits) .  sail2_state_monad$bindS
+     (DecodeBitMasks (( 32 : int):ii) N imms immr T  : (( 32 words$word #  32 words$word)) M) (\ (w__0 :
+       ( 32 bits # 32 bits)) . 
+     let (tup__0, tup__1) = w__0 in
+     let imm = tup__0 in
+     let anon10 = tup__1 in
+     aarch64_integer_logical_immediate d ((make_the_value (( 32 : int):ii)  :  32 itself)) imm n op setflags))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (setflags : bool) .  sail2_state_monad$bindS
+     (undefined_LogicalOp () ) (\ (op : LogicalOp) . 
+     let b__6 = opc in
+     let ((op : LogicalOp), (setflags : bool)) =
+       (if (((b__6 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+         let (op : LogicalOp) = LogicalOp_AND in
+         let (setflags : bool) = F in
+         (op, setflags)
+       else
+         let ((op : LogicalOp), (setflags : bool)) =
+           (if (((b__6 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+             let (op : LogicalOp) = LogicalOp_ORR in
+             let (setflags : bool) = F in
+             (op, setflags)
+           else
+             let ((op : LogicalOp), (setflags : bool)) =
+               (if (((b__6 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+                 let (op : LogicalOp) = LogicalOp_EOR in
+                 let (setflags : bool) = F in
+                 (op, setflags)
+               else
+                 let (op : LogicalOp) = LogicalOp_AND in
+                 let (setflags : bool) = T in
+                 (op, setflags)) in
+             (op, setflags)) in
+         (op, setflags)) in sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (imm : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (if (((F /\ (((N <> (vec_of_bits [B0]  :  1 words$word))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (anon10 : 64 bits) .  sail2_state_monad$bindS
+     (DecodeBitMasks (( 64 : int):ii) N imms immr T  : (( 64 words$word #  64 words$word)) M) (\ (w__1 :
+       ( 64 bits # 64 bits)) . 
+     let (tup__0, tup__1) = w__1 in
+     let imm = tup__0 in
+     let anon10 = tup__1 in
+     aarch64_integer_logical_immediate d ((make_the_value (( 64 : int):ii)  :  64 itself)) imm n op setflags))))))))`;
+
+
+(*val integer_bitfield_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((integer_bitfield_decode:(1)words$word ->(2)words$word ->(1)words$word ->(6)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 opc N immr imms Rn Rd=
+    (if (((b__0 = (vec_of_bits [B0]  :  1 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (inzero : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (extend : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (R1 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (S1 : ii) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (wmask : 32 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M) (\ (tmask : 32 bits) . 
+     let b__1 = opc in sail2_state_monad$bindS
+     (if (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+        let (inzero : bool) = T in
+        let (extend : bool) = T in
+        sail2_state_monad$returnS (extend, inzero)
+      else if (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+        let (inzero : bool) = F in
+        let (extend : bool) = F in
+        sail2_state_monad$returnS (extend, inzero)
+      else if (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+        let (inzero : bool) = T in
+        let (extend : bool) = F in
+        sail2_state_monad$returnS (extend, inzero)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (extend, inzero))) (\ varstup .  let ((extend : bool), (inzero :
+       bool)) = varstup in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (if (((F /\ (((N <> (vec_of_bits [B1]  :  1 words$word))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (if (((T /\ (((((((((N <> (vec_of_bits [B0]  :  1 words$word)))) \/ ((((vec_of_bits [access_vec_dec immr (( 5 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word))))))) \/ ((((vec_of_bits [access_vec_dec imms (( 5 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)))))))))) then
+        ReservedValue () 
+      else sail2_state_monad$returnS () ))
+     (let R1 = (lem$w2ui immr) in
+     let S1 = (lem$w2ui imms) in sail2_state_monad$bindS
+     (DecodeBitMasks (( 32 : int):ii) N imms immr F  : (( 32 words$word #  32 words$word)) M) (\ (w__0 :
+       ( 32 bits # 32 bits)) . 
+     let (tup__0, tup__1) = w__0 in
+     let wmask = tup__0 in
+     let tmask = tup__1 in
+     aarch64_integer_bitfield R1 S1 d ((make_the_value (( 32 : int):ii)  :  32 itself)) extend inzero n tmask
+       wmask))))))))))
+   else sail2_state_monad$seqS
+     (sail2_state_monad$write_regS unconditional_ref T)
+     (let (d : ii) = (lem$w2ui Rd) in
+     let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (inzero : bool) .  sail2_state_monad$bindS
+     (sail2_state_monad$undefined_boolS () ) (\ (extend : bool) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (R1 : ii) .  sail2_state_monad$bindS
+     (undefined_int () ) (\ (S1 : ii) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (wmask : 64 bits) .  sail2_state_monad$bindS
+     (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M) (\ (tmask : 64 bits) . 
+     let b__6 = opc in sail2_state_monad$bindS
+     (if (((b__6 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+        let (inzero : bool) = T in
+        let (extend : bool) = T in
+        sail2_state_monad$returnS (extend, inzero)
+      else if (((b__6 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+        let (inzero : bool) = F in
+        let (extend : bool) = F in
+        sail2_state_monad$returnS (extend, inzero)
+      else if (((b__6 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+        let (inzero : bool) = T in
+        let (extend : bool) = F in
+        sail2_state_monad$returnS (extend, inzero)
+      else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (extend, inzero))) (\ varstup .  let ((extend : bool), (inzero :
+       bool)) = varstup in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (if (((T /\ (((N <> (vec_of_bits [B1]  :  1 words$word))))))) then ReservedValue () 
+      else sail2_state_monad$returnS () )
+     (if (((F /\ (((((((((N <> (vec_of_bits [B0]  :  1 words$word)))) \/ ((((vec_of_bits [access_vec_dec immr (( 5 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word))))))) \/ ((((vec_of_bits [access_vec_dec imms (( 5 : int):ii)]  :  1 words$word) <> (vec_of_bits [B0]  :  1 words$word)))))))))) then
+        ReservedValue () 
+      else sail2_state_monad$returnS () ))
+     (let R1 = (lem$w2ui immr) in
+     let S1 = (lem$w2ui imms) in sail2_state_monad$bindS
+     (DecodeBitMasks (( 64 : int):ii) N imms immr F  : (( 64 words$word #  64 words$word)) M) (\ (w__1 :
+       ( 64 bits # 64 bits)) . 
+     let (tup__0, tup__1) = w__1 in
+     let wmask = tup__0 in
+     let tmask = tup__1 in
+     aarch64_integer_bitfield R1 S1 d ((make_the_value (( 64 : int):ii)  :  64 itself)) extend inzero n tmask
+       wmask))))))))))))`;
+
+
+(*val decode : mword ty32 -> M unit*)
+
+val _ = Define `
+ ((decode:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op_code=
+    (if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0;B1;B1]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 15 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op54 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (U : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_mul_widening_64128hi_decode sf op54 U Rm o0 Ra Rn Rd
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0;B1]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1;B0]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (option_name : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode size1 V1 opc Rm
+       option_name S1 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1]  :  8 words$word)))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_mul_addsub_decode M S1 typ o1 Rm o0 Ra Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 15 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_atomicops_ld_decode size1 V1 A R1 Rs o3 opc Rn Rt
+   else if (((((subrange_vec_dec op_code (( 31 : int):ii) (( 11 : int):ii)  :  21 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0]
+                 :  21 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (D : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_strip_dp_1src_decode sf S1 opcode2 D Rn Rd
+   else if (((op_code = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;
+                             B1;B1;B1;B1;B1;B1;B1;B1]
+                 :  32 words$word)))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_strip_hint_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacda_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B1]
+                     :  20 words$word)))) /\ (((((subrange_vec_dec op_code (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1]  :  8 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     system_monitors_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode
+       size1 V1 opc imm9 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0;B0]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode opc V1 L imm7 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_mul_product_decode M S1 typ Rm op Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0;B1;B0;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode2 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacga_dp_2src_decode sf op S1 Rm opcode2 Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_atomicops_cas_single_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 19 : int):ii)  :  13 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0]  :  13 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     system_register_cpsr_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1;B0;B0]  :  8 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)]  :  1 words$word)) in
+     let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii)  :  19 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)]  :  1 words$word)) in
+     let (cond : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) in
+     branch_conditional_cond_decode o1 imm19 o0 cond
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))) then
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     system_exceptions_runtime_hvc_decode opc imm16 op2 LL
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+     let (sz : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_exclusive_pair_decode sz o2 L o1 Rs o0 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_autdb_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 10 : int):ii)  :  21 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                 :  21 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_rbit_decode sf S1 opcode2 Rn Rd
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii)  :  12 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode
+       size1 V1 opc imm12 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_autia_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0]
+                     :  20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_autia_hint_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word))))))) then
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     system_exceptions_runtime_svc_decode opc imm16 op2 LL
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 23 : int):ii) (( 23 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0;B0;B0;B0]  :  9 words$word)))))))))) then
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)]  :  1 words$word)) in
+     let (opc : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (op : 2 bits) = ((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii)  :  2 words$word)) in
+     let (op2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op3 : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 : int):ii)]  :  1 words$word)) in
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     branch_unconditional_register_decode Z opc op op2 op3 A M Rn Rm
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 5 : int):ii)  :  8 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm8 : 8 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 13 : int):ii)  :  8 words$word)) in
+     let (imm5 : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_move_fp_imm_decode M S1 typ imm8 imm5 Rd
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 25 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (b5 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)]  :  1 words$word)) in
+     let (b40 : 5 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 19 : int):ii)  :  5 words$word)) in
+     let (imm14 : 14 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 5 : int):ii)  :  14 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     branch_conditional_test_decode b5 op b40 imm14 Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode
+       size1 V1 opc imm9 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode
+       size1 V1 opc imm9 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii)  :  12 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode
+       size1 V1 opc imm12 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii)  :  19 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_literal_general_decode opc V1 imm19 Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0;B1]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 25 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)]  :  1 words$word)) in
+     let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii)  :  19 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     branch_conditional_compare_decode sf op imm19 Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode
+       size1 V1 opc imm9 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacib_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0]
+                     :  20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacib_hint_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode
+       size1 V1 opc imm9 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode
+       size1 V1 opc imm9 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B1]  :  6 words$word)))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii)  :  12 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode
+       size1 V1 opc imm12 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 16 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))))))) then
+     let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (opcode : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode Q L opcode size1 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0;B1]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+     let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode Q L Rm opcode size1
+       Rn Rt
+   else if (((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B1;B0;B1;B0;B0;B1;B1;B1;B1;B1;B0;B0;B0;B0]
+                 :  20 words$word)))) then
+     let (opc : 4 bits) = ((subrange_vec_dec op_code (( 24 : int):ii) (( 21 : int):ii)  :  4 words$word)) in
+     let (op2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op3 : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 : int):ii)]  :  1 words$word)) in
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (op4 : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     branch_unconditional_eret_decode opc op2 op3 A M Rn op4
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 14 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op : 2 bits) = ((subrange_vec_dec op_code (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_maxmin_decode M S1 typ Rm op Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 17 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 16 : int):ii) (( 15 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_unary_decode M S1 typ opc Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word))))))) then
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     system_exceptions_runtime_smc_decode opc imm16 op2 LL
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B1]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_ordered_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (option_name : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_register_aarch64_memory_single_general_register__decode size1 V1 opc Rm
+       option_name S1 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0]  :  7 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii)  :  7 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode opc V1 L imm7 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     system_exceptions_debug_breakpoint_decode opc imm16 op2 LL
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 21 : int):ii)  :  10 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B0;B0;B0]  :  10 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op54 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (op31 : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_mul_uniform_addsub_decode sf op54 op31 Rm o0 Ra Rn Rd
+   else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii)  :  19 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_literal_simdfp_decode opc V1 imm19 Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 22 : int):ii)  :  10 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0]  :  10 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     system_sysops_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (shift : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm6 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_addsub_shiftedreg_decode sf op S1 shift Rm imm6 Rn Rd
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 23 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (immr : 6 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 16 : int):ii)  :  6 words$word)) in
+     let (imms : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_logical_immediate_decode sf opc N immr imms Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii)  :  9 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0;B0;B1;B0]  :  9 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)]  :  1 words$word)) in
+     let (nzcv1 : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) in
+     integer_conditional_compare_register_decode sf op S1 Rm cond o2 Rn o3 nzcv1
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 23 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0]  :  6 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (immr : 6 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 16 : int):ii)  :  6 words$word)) in
+     let (imms : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_bitfield_decode sf opc N immr imms Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 22 : int):ii)  :  10 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0]  :  10 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 19 : int):ii)]  :  1 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     system_register_system_decode L o0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii)  :  9 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0;B0;B1;B0]  :  9 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (imm5 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)]  :  1 words$word)) in
+     let (nzcv1 : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) in
+     integer_conditional_compare_immediate_decode sf op S1 imm5 cond o2 Rn o3 nzcv1
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0]  :  6 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_div_decode M S1 typ Rm Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0]  :  6 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_atomicops_swp_decode size1 V1 A R1 Rs o3 opc Rn Rt
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (shift : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii)  :  12 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_addsub_immediate_decode sf op S1 shift imm12 Rn Rd
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 26 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))) then
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (imm26 : 26 bits) = ((subrange_vec_dec op_code (( 25 : int):ii) (( 0 : int):ii)  :  26 words$word)) in
+     branch_unconditional_immediate_decode op imm26
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_autda_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 11 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]
+                 :  20 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_cnt_decode sf S1 opcode2 op Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 27 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 25 : int):ii) (( 24 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))))))))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_atomicops_st_decode size1 V1 A R1 Rs o3 opc Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B1]
+                     :  20 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     system_barriers_decode L op0 op1 CRn CRm opc Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+     let (sz : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_atomicops_cas_pair_decode sz o2 L o1 Rs o0 Rt2 Rn Rt
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 23 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (hw : 2 bits) = ((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii)  :  2 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_insext_insert_movewide_decode sf opc hw imm16 Rd
+   else if (((op_code = (vec_of_bits [B1;B1;B0;B1;B0;B1;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;
+                             B1;B1;B1;B0;B0;B0;B0;B0]
+                 :  32 words$word)))) then
+     let (opc : 4 bits) = ((subrange_vec_dec op_code (( 24 : int):ii) (( 21 : int):ii)  :  4 words$word)) in
+     let (op2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op3 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (op4 : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     branch_unconditional_dret_decode opc op2 op3 Rt op4
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_move_fp_select_decode M S1 typ Rm cond Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B1;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     system_exceptions_debug_exception_decode opc imm16 op2 LL
+   else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 12 : int):ii)  :  19 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  19 words$word))))
+   then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_rev_decode sf S1 opcode2 opc Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 17 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 16 : int):ii) (( 15 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_convert_fp_decode M S1 typ opc Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacia_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0]
+                     :  20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacia_hint_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 24 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (rmode : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_convert_int_decode sf S1 typ rmode opcode Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii)  :  9 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0;B1;B0;B0]  :  9 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_conditional_select_decode sf op S1 Rm cond o2 Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii)  :  9 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0;B1;B0;B1]  :  9 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_orderedrcpc_decode size1 V1 A R1 Rs o3 opc Rn Rt
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 21 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0;B0;B1]  :  8 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opt : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (option_name : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) in
+     let (imm3 : 3 bits) = ((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_addsub_extendedreg_decode sf op S1 opt Rm option_name imm3 Rn Rd
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) then
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (immlo : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (immhi : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii)  :  19 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_address_pcrel_decode op immlo immhi Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))))))) then
+     let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)]  :  1 words$word)) in
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode Q L R1 opcode S1 size1 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word))))))) then
+     let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)]  :  1 words$word)) in
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode Q L R1 Rm opcode S1 size1
+       Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 10 : int):ii) (( 10 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (W1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_signed_pac_decode size1 V1 M S1 imm9 W1 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_autib_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0]
+                     :  20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_autib_hint_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)]  :  1 words$word)) in
+     let (nzcv1 : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word)) in
+     float_compare_cond_decode M S1 typ Rm cond Rn op nzcv1
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_exclusive_single_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 24 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0]  :  7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (rmode : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (scale : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_convert_fix_decode sf S1 typ rmode opcode scale Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 18 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (rmode : 3 bits) = ((subrange_vec_dec op_code (( 17 : int):ii) (( 15 : int):ii)  :  3 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_round_decode M S1 typ rmode Rn Rd
+   else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (shift : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm6 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_logical_shiftedreg_decode sf opc shift N Rm imm6 Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 21 : int):ii)  :  10 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B1;B1;B0]  :  10 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode2 : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) in
+     let (C : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)]  :  1 words$word)) in
+     let (sz : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_crc_decode sf op S1 Rm opcode2 C sz Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 28 : int):ii) (( 21 : int):ii)  :  8 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0]  :  8 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode2 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_addsub_carry_decode sf op S1 Rm opcode2 Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec op_code (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op : 2 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 14 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
+     float_compare_uncond_decode M S1 typ Rm op Rn opc
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0]
+                     :  20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word))))))) then
+     let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii)  :  2 words$word)) in
+     let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii)  :  3 words$word)) in
+     let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii)  :  3 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     system_hints_decode L op0 op1 CRn CRm op2 Rt
+   else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 21 : int):ii)  :  10 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B1;B1;B0]  :  10 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B1;B0]  :  4 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode2 : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) in
+     let (op2 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_shift_variable_decode sf op S1 Rm opcode2 op2 Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii)  :  18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]
+                     :  18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_pac_pacdb_dp_1src_decode sf S1 opcode2 Z Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))))))))) then
+     let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii)  :  2 words$word)) in
+     let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)]  :  1 words$word)) in
+     let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii)  :  9 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode
+       size1 V1 opc imm9 Rn Rt
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0]  :  8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))))))))) then
+     let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii)  :  2 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     float_arithmetic_addsub_decode M S1 typ Rm op Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 23 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1]  :  8 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op21 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)]  :  1 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imms : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_insext_extract_immediate_decode sf op21 N o0 Rm imms Rn Rd
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii)  :  3 words$word)) in
+     let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii)  :  16 words$word)) in
+     let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     system_exceptions_debug_halt_decode opc imm16 op2 LL
+   else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0;B1;B1]  :  8 words$word)))) /\ (((((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op54 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) in
+     let (U : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)]  :  1 words$word)) in
+     let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii)  :  5 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_mul_widening_3264_decode sf op54 U Rm o0 Ra Rn Rd
+   else
+     let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)]  :  1 words$word)) in
+     let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)]  :  1 words$word)) in
+     let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)]  :  1 words$word)) in
+     let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)]  :  1 words$word)) in
+     let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii)  :  5 words$word)) in
+     let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+     integer_arithmetic_div_decode sf op S1 Rm opcode2 o1 Rn Rd))`;
+
+
+(*val initialize_registers : unit -> M unit*)
+
+val _ = Define `
+ ((initialize_registers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS unconditional_ref w__0)
+   (undefined_bitvector (( 4 : int):ii)  : ( 4 words$word) M)) (\ (w__1 : 4 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS currentCond_ref w__1)
+   (undefined___InstrEnc () )) (\ (w__2 : InstrEnc) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ThisInstrEnc_ref w__2)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__3 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ThisInstr_ref w__3)
+   (sail2_state_monad$undefined_boolS () )) (\ (w__4 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS Sleeping_ref w__4)
+   (sail2_state_monad$undefined_boolS () )) (\ (w__5 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PendingPhysicalSError_ref w__5)
+   (sail2_state_monad$undefined_boolS () )) (\ (w__6 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PendingInterrupt_ref w__6)
+   (undefined_bitvector (( 52 : int):ii)  : ( 52 words$word) M)) (\ (w__7 : 52 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS Memory_ref w__7)
+   (sail2_state_monad$undefined_boolS () )) (\ (w__8 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ExclusiveLocal_ref w__8)
+   (sail2_state_monad$undefined_boolS () )) (\ (w__9 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS BranchTaken_ref w__9)
+   (undefined_bitvector (( 128 : int):ii)  : ( 128 words$word) M)) (\ (w__10 :  128 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 32 : int):ii) w__10  : ( ( 128 words$word)list) M) (\ (w__11 : ( 128 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS V_ref w__11)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__12 :  64 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 31 : int):ii) w__12  : ( ( 64 words$word)list) M) (\ (w__13 : ( 64 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS R_ref w__13)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__14 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PC_ref w__14)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__15 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VTTBR_EL2_ref w__15)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__16 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VTCR_EL2_ref w__16)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__17 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VSESR_EL2_ref w__17)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__18 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VDFSR_ref w__18)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__19 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VBAR_EL3_ref w__19)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__20 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VBAR_EL2_ref w__20)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__21 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VBAR_EL1_ref w__21)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__22 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS VBAR_ref w__22)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__23 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TTBR1_EL2_ref w__23)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__24 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TTBR1_EL1_ref w__24)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__25 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TTBR0_EL3_ref w__25)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__26 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TTBR0_EL2_ref w__26)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__27 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TTBR0_EL1_ref w__27)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__28 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TTBCR_ref w__28)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__29 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TCR_EL3_ref w__29)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__30 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TCR_EL2_ref w__30)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__31 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TCR_EL1_ref w__31)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__32 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_mon_ref w__32)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__33 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_EL3_ref w__33)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__34 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_EL2_ref w__34)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__35 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_EL1_ref w__35)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__36 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SP_EL0_ref w__36)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__37 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_und_ref w__37)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__38 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_svc_ref w__38)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__39 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_mon_ref w__39)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__40 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_irq_ref w__40)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__41 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_hyp_ref w__41)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__42 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_fiq_ref w__42)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__43 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_abt_ref w__43)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__44 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_EL3_ref w__44)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__45 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_EL2_ref w__45)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__46 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPSR_EL1_ref w__46)
+   (undefined_signal () )) (\ (w__47 : signal) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SPIDEN_ref w__47)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__48 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SDER_ref w__48)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__49 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SDCR_ref w__49)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__50 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SCTLR_EL3_ref w__50)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__51 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SCTLR_EL2_ref w__51)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__52 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SCTLR_EL1_ref w__52)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__53 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SCTLR_ref w__53)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__54 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SCR_EL3_ref w__54)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__55 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS SCR_ref w__55)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__56 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RVBAR_EL3_ref w__56)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__57 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RVBAR_EL2_ref w__57)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__58 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RVBAR_EL1_ref w__58)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__59 :  64 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 5 : int):ii) w__59  : ( ( 64 words$word)list) M) (\ (w__60 : ( 64 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS RC_ref w__60)
+   (undefined_ProcState () )) (\ (w__61 : ProcState) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PSTATE_ref w__61)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__62 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS OSLSR_EL1_ref w__62)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__63 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS OSDLR_EL1_ref w__63)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__64 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS MDSCR_EL1_ref w__64)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__65 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS MDCR_EL3_ref w__65)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__66 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS MDCR_EL2_ref w__66)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__67 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS MAIR_EL3_ref w__67)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__68 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS MAIR_EL2_ref w__68)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__69 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS MAIR_EL1_ref w__69)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__70 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LR_mon_ref w__70)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__71 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ID_AA64DFR0_EL1_ref w__71)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__72 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HVBAR_ref w__72)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__73 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HSR_ref w__73)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__74 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HSCTLR_ref w__74)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__75 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HPFAR_EL2_ref w__75)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__76 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HPFAR_ref w__76)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__77 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HIFAR_ref w__77)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__78 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HDFAR_ref w__78)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__79 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HDCR_ref w__79)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__80 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HCR_EL2_ref w__80)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__81 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HCR2_ref w__81)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__82 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HCR_ref w__82)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__83 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FPSR_ref w__83)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__84 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FPSCR_ref w__84)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__85 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FPEXC_ref w__85)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__86 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FPCR_ref w__86)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__87 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FAR_EL3_ref w__87)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__88 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FAR_EL2_ref w__88)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__89 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS FAR_EL1_ref w__89)
+   (undefined_bitvector (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__90 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS EventRegister_ref w__90)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__91 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ESR_EL3_ref w__91)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__92 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ESR_EL2_ref w__92)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__93 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ESR_EL1_ref w__93)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__94 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ELR_hyp_ref w__94)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__95 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ELR_EL3_ref w__95)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__96 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ELR_EL2_ref w__96)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__97 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS ELR_EL1_ref w__97)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__98 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS EDSCR_ref w__98)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__99 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DSPSR_EL0_ref w__99)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__100 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DSPSR_ref w__100)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__101 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DLR_EL0_ref w__101)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__102 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DLR_ref w__102)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__103 :  64 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 16 : int):ii) w__103  : ( ( 64 words$word)list) M) (\ (w__104 : ( 64 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGWVR_EL1_ref w__104)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__105 :  32 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 16 : int):ii) w__105  : ( ( 32 words$word)list) M) (\ (w__106 : ( 32 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGWCR_EL1_ref w__106)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__107 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGPRCR_EL1_ref w__107)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__108 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGPRCR_ref w__108)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__109 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGOSLSR_ref w__109)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__110 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGOSDLR_ref w__110)
+   (undefined_signal () )) (\ (w__111 : signal) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGEN_ref w__111)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__112 :  64 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 16 : int):ii) w__112  : ( ( 64 words$word)list) M) (\ (w__113 : ( 64 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGBVR_EL1_ref w__113)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__114 :  32 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 16 : int):ii) w__114  : ( ( 32 words$word)list) M) (\ (w__115 : ( 32 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DBGBCR_EL1_ref w__115)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__116 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CPTR_EL3_ref w__116)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__117 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CPTR_EL2_ref w__117)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__118 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CPACR_EL1_ref w__118)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__119 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CONTEXTIDR_EL2_ref w__119)
+   (undefined_bitvector (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__120 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CONTEXTIDR_EL1_ref w__120)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__121 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APIBKeyLo_EL1_ref w__121)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__122 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APIBKeyHi_EL1_ref w__122)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__123 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APIAKeyLo_EL1_ref w__123)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__124 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APIAKeyHi_EL1_ref w__124)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__125 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APGAKeyLo_EL1_ref w__125)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__126 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APGAKeyHi_EL1_ref w__126)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__127 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APDBKeyLo_EL1_ref w__127)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__128 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APDBKeyHi_EL1_ref w__128)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__129 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS APDAKeyLo_EL1_ref w__129)
+   (undefined_bitvector (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__130 : 64 bits) . 
+   sail2_state_monad$write_regS APDAKeyHi_EL1_ref w__130)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
+
+
+val _ = Define `
+((initial_regstate:regstate)=
+   (<| APDAKeyHi_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APDAKeyLo_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APDBKeyHi_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APDBKeyLo_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APGAKeyHi_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APGAKeyLo_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APIAKeyHi_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APIAKeyLo_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APIBKeyHi_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     APIBKeyLo_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     CONTEXTIDR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     CONTEXTIDR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     CPACR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     CPTR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     CPTR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DBGBCR_EL1 :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word)]); 
+     DBGBVR_EL1 :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word)]); 
+     DBGEN := LOW; 
+     DBGOSDLR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DBGOSLSR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DBGPRCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DBGPRCR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DBGWCR_EL1 :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0]
+           :  32 words$word)]); 
+     DBGWVR_EL1 :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word)]); 
+     DLR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DLR_EL0 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     DSPSR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     DSPSR_EL0 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     EDSCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     ELR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     ELR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     ELR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     ELR_hyp :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     ESR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     ESR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     ESR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     EventRegister := ((vec_of_bits [B0]  :  1 words$word)); 
+     FAR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     FAR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     FAR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     FPCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     FPEXC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     FPSCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     FPSR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HCR2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HCR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     HDCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HDFAR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HIFAR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HPFAR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HPFAR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     HSCTLR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HSR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     HVBAR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     ID_AA64DFR0_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     LR_mon :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     MAIR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     MAIR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     MAIR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     MDCR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     MDCR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     MDSCR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     OSDLR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     OSLSR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     PSTATE :=
+       (<| ProcState_N := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_Z := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_C := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_V := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_D := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_A := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_I := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_F := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_PAN := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_UAO := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_SS := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_IL := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_EL := ((vec_of_bits [B0;B0]  :  2 words$word)); 
+           ProcState_nRW := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_SP := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_Q := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_GE := ((vec_of_bits [B0;B0;B0;B0]  :  4 words$word)); 
+           ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)); 
+           ProcState_J := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_T := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_E := ((vec_of_bits [B0]  :  1 words$word)); 
+           ProcState_M := ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)) |>); 
+     RC0 :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word)]); 
+     RVBAR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     RVBAR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     RVBAR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     SCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SCR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SCTLR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SCTLR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SCTLR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SCTLR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SDCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SDER :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPIDEN := LOW; 
+     SPSR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_abt :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_fiq :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_hyp :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_irq :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_mon :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_svc :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SPSR_und :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     SP_EL0 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     SP_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     SP_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     SP_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     SP_mon :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     TCR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     TCR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     TCR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     TTBCR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     TTBR0_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     TTBR0_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     TTBR0_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     TTBR1_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     TTBR1_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     VBAR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     VBAR_EL1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     VBAR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     VBAR_EL3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     VDFSR :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     VSESR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     VTCR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     VTTBR_EL2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     PC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     R :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word)]); 
+     V :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  128 words$word)]); 
+     BranchTaken := F; 
+     ExclusiveLocal := F; 
+     Memory :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  52 words$word)); 
+     PendingInterrupt := F; 
+     PendingPhysicalSError := F; 
+     Sleeping := F; 
+     ThisInstr :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     ThisInstrEnc := A64; 
+     currentCond := ((vec_of_bits [B0;B0;B0;B0]  :  4 words$word)); 
+     unconditional := F |>))`;
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml b/snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml
new file mode 100644
index 00000000..1c379bba
--- /dev/null
+++ b/snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml
@@ -0,0 +1,2421 @@
+(*Generated by Lem from aarch64_mono_types.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "aarch64_mono_types"
+
+(*Generated by Sail from aarch64_mono.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+val _ = type_abbrev((*  'n *) "bits" , ``:  'n words$word``);
+
+val _ = Hol_datatype `
+ exception  =
+    Error_Undefined of (unit)
+  | Error_See of (string)
+  | Error_Implementation_Defined of (string)
+  | Error_ReservedEncoding of (unit)
+  | Error_ExceptionTaken of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ boolean = FALSE | TRUE`;
+
+
+
+
+val _ = Hol_datatype `
+ signal = LOW | HIGH`;
+
+
+
+
+val _ = Hol_datatype `
+ RetCode =
+  RC_OK
+  | RC_UNDEFINED
+  | RC_UNPREDICTABLE
+  | RC_SEE
+  | RC_IMPLEMENTATION_DEFINED
+  | RC_SUBARCHITECTURE_DEFINED
+  | RC_EXCEPTION_TAKEN
+  | RC_ASSERT_FAILED
+  | RC_UNMATCHED_CASE`;
+
+
+
+
+val _ = type_abbrev( "CPACRType"  , ``: 32 bits``);
+
+val _ = type_abbrev( "CNTKCTLType"  , ``: 32 bits``);
+
+val _ = type_abbrev( "ESRType"  , ``: 32 bits``);
+
+val _ = type_abbrev( "FPCRType"  , ``: 32 bits``);
+
+val _ = type_abbrev( "MAIRType"  , ``: 64 bits``);
+
+val _ = type_abbrev( "SCRType"  , ``: 32 bits``);
+
+val _ = type_abbrev( "SCTLRType"  , ``: 32 bits``);
+
+val _ = Hol_datatype `
+ FPConvOp =
+  FPConvOp_CVT_FtoI
+  | FPConvOp_CVT_ItoF
+  | FPConvOp_MOV_FtoI
+  | FPConvOp_MOV_ItoF
+  | FPConvOp_CVT_FtoI_JS`;
+
+
+
+
+val _ = Hol_datatype `
+ Exception =
+  Exception_Uncategorized
+  | Exception_WFxTrap
+  | Exception_CP15RTTrap
+  | Exception_CP15RRTTrap
+  | Exception_CP14RTTrap
+  | Exception_CP14DTTrap
+  | Exception_AdvSIMDFPAccessTrap
+  | Exception_FPIDTrap
+  | Exception_PACTrap
+  | Exception_CP14RRTTrap
+  | Exception_IllegalState
+  | Exception_SupervisorCall
+  | Exception_HypervisorCall
+  | Exception_MonitorCall
+  | Exception_SystemRegisterTrap
+  | Exception_ERetTrap
+  | Exception_InstructionAbort
+  | Exception_PCAlignment
+  | Exception_DataAbort
+  | Exception_SPAlignment
+  | Exception_FPTrappedException
+  | Exception_SError
+  | Exception_Breakpoint
+  | Exception_SoftwareStep
+  | Exception_Watchpoint
+  | Exception_SoftwareBreakpoint
+  | Exception_VectorCatch
+  | Exception_IRQ
+  | Exception_FIQ`;
+
+
+
+
+val _ = Hol_datatype `
+ ArchVersion = ARMv8p0 | ARMv8p1 | ARMv8p2 | ARMv8p3`;
+
+
+
+
+val _ = Hol_datatype `
+ Unpredictable =
+  Unpredictable_WBOVERLAPLD
+  | Unpredictable_WBOVERLAPST
+  | Unpredictable_LDPOVERLAP
+  | Unpredictable_BASEOVERLAP
+  | Unpredictable_DATAOVERLAP
+  | Unpredictable_DEVPAGE2
+  | Unpredictable_INSTRDEVICE
+  | Unpredictable_RESCPACR
+  | Unpredictable_RESMAIR
+  | Unpredictable_RESTEXCB
+  | Unpredictable_RESPRRR
+  | Unpredictable_RESDACR
+  | Unpredictable_RESVTCRS
+  | Unpredictable_RESTnSZ
+  | Unpredictable_OORTnSZ
+  | Unpredictable_LARGEIPA
+  | Unpredictable_ESRCONDPASS
+  | Unpredictable_ILZEROIT
+  | Unpredictable_ILZEROT
+  | Unpredictable_BPVECTORCATCHPRI
+  | Unpredictable_VCMATCHHALF
+  | Unpredictable_VCMATCHDAPA
+  | Unpredictable_WPMASKANDBAS
+  | Unpredictable_WPBASCONTIGUOUS
+  | Unpredictable_RESWPMASK
+  | Unpredictable_WPMASKEDBITS
+  | Unpredictable_RESBPWPCTRL
+  | Unpredictable_BPNOTIMPL
+  | Unpredictable_RESBPTYPE
+  | Unpredictable_BPNOTCTXCMP
+  | Unpredictable_BPMATCHHALF
+  | Unpredictable_BPMISMATCHHALF
+  | Unpredictable_RESTARTALIGNPC
+  | Unpredictable_RESTARTZEROUPPERPC
+  | Unpredictable_ZEROUPPER
+  | Unpredictable_ERETZEROUPPERPC
+  | Unpredictable_A32FORCEALIGNPC
+  | Unpredictable_SMD
+  | Unpredictable_AFUPDATE
+  | Unpredictable_IESBinDebug
+  | Unpredictable_ZEROPMSEVFR
+  | Unpredictable_NOOPTYPES
+  | Unpredictable_ZEROMINLATENCY
+  | Unpredictable_CLEARERRITEZERO
+  | Unpredictable_TBD`;
+
+
+
+
+val _ = Hol_datatype `
+ Constraint =
+  Constraint_NONE
+  | Constraint_UNKNOWN
+  | Constraint_UNDEF
+  | Constraint_UNDEFEL0
+  | Constraint_NOP
+  | Constraint_TRUE
+  | Constraint_FALSE
+  | Constraint_DISABLED
+  | Constraint_UNCOND
+  | Constraint_COND
+  | Constraint_ADDITIONAL_DECODE
+  | Constraint_WBSUPPRESS
+  | Constraint_FAULT
+  | Constraint_FORCE
+  | Constraint_FORCENOSLCHECK`;
+
+
+
+
+val _ = Hol_datatype `
+ InstrSet = InstrSet_A64 | InstrSet_A32 | InstrSet_T32`;
+
+
+
+
+val _ = Hol_datatype `
+ ProcState  =
+  <| ProcState_N : 1 bits;
+     ProcState_Z : 1 bits;
+     ProcState_C : 1 bits;
+     ProcState_V : 1 bits;
+     ProcState_D : 1 bits;
+     ProcState_A : 1 bits;
+     ProcState_I : 1 bits;
+     ProcState_F : 1 bits;
+     ProcState_PAN : 1 bits;
+     ProcState_UAO : 1 bits;
+     ProcState_SS : 1 bits;
+     ProcState_IL : 1 bits;
+     ProcState_EL : 2 bits;
+     ProcState_nRW : 1 bits;
+     ProcState_SP : 1 bits;
+     ProcState_Q : 1 bits;
+     ProcState_GE : 4 bits;
+     ProcState_IT : 8 bits;
+     ProcState_J : 1 bits;
+     ProcState_T : 1 bits;
+     ProcState_E : 1 bits;
+     ProcState_M : 5 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ BranchType =
+  BranchType_CALL
+  | BranchType_ERET
+  | BranchType_DBGEXIT
+  | BranchType_RET
+  | BranchType_JMP
+  | BranchType_EXCEPTION
+  | BranchType_UNKNOWN`;
+
+
+
+
+val _ = Hol_datatype `
+ ExceptionRecord  =
+  <| ExceptionRecord_typ : Exception;
+     ExceptionRecord_syndrome : 25 bits;
+     ExceptionRecord_vaddress : 64 bits;
+     ExceptionRecord_ipavalid : bool;
+     ExceptionRecord_ipaddress : 52 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ Fault =
+  Fault_None
+  | Fault_AccessFlag
+  | Fault_Alignment
+  | Fault_Background
+  | Fault_Domain
+  | Fault_Permission
+  | Fault_Translation
+  | Fault_AddressSize
+  | Fault_SyncExternal
+  | Fault_SyncExternalOnWalk
+  | Fault_SyncParity
+  | Fault_SyncParityOnWalk
+  | Fault_AsyncParity
+  | Fault_AsyncExternal
+  | Fault_Debug
+  | Fault_TLBConflict
+  | Fault_Lockdown
+  | Fault_Exclusive
+  | Fault_ICacheMaint`;
+
+
+
+
+val _ = Hol_datatype `
+ AccType =
+  AccType_NORMAL
+  | AccType_VEC
+  | AccType_STREAM
+  | AccType_VECSTREAM
+  | AccType_ATOMIC
+  | AccType_ATOMICRW
+  | AccType_ORDERED
+  | AccType_ORDEREDRW
+  | AccType_LIMITEDORDERED
+  | AccType_UNPRIV
+  | AccType_IFETCH
+  | AccType_PTW
+  | AccType_DC
+  | AccType_IC
+  | AccType_DCZVA
+  | AccType_AT`;
+
+
+
+
+val _ = Hol_datatype `
+ FaultRecord  =
+  <| FaultRecord_typ : Fault;
+     FaultRecord_acctype : AccType;
+     FaultRecord_ipaddress : 52 bits;
+     FaultRecord_s2fs1walk : bool;
+     FaultRecord_write : bool;
+     FaultRecord_level : ii;
+     FaultRecord_extflag : 1 bits;
+     FaultRecord_secondstage : bool;
+     FaultRecord_domain : 4 bits;
+     FaultRecord_errortype : 2 bits;
+     FaultRecord_debugmoe : 4 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ MBReqDomain =
+  MBReqDomain_Nonshareable
+  | MBReqDomain_InnerShareable
+  | MBReqDomain_OuterShareable
+  | MBReqDomain_FullSystem`;
+
+
+
+
+val _ = Hol_datatype `
+ MBReqTypes = MBReqTypes_Reads | MBReqTypes_Writes | MBReqTypes_All`;
+
+
+
+
+val _ = Hol_datatype `
+ MemType = MemType_Normal | MemType_Device`;
+
+
+
+
+val _ = Hol_datatype `
+ DeviceType = DeviceType_GRE | DeviceType_nGRE | DeviceType_nGnRE | DeviceType_nGnRnE`;
+
+
+
+
+val _ = Hol_datatype `
+ MemAttrHints  =
+  <| MemAttrHints_attrs : 2 bits; MemAttrHints_hints : 2 bits; MemAttrHints_transient : bool  |>`;
+
+
+
+val _ = Hol_datatype `
+ MemoryAttributes  =
+  <| MemoryAttributes_typ : MemType;
+     MemoryAttributes_device : DeviceType;
+     MemoryAttributes_inner : MemAttrHints;
+     MemoryAttributes_outer : MemAttrHints;
+     MemoryAttributes_shareable : bool;
+     MemoryAttributes_outershareable : bool  |>`;
+
+
+
+val _ = Hol_datatype `
+ FullAddress  = <| FullAddress_physicaladdress : 52 bits; FullAddress_NS : 1 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ AddressDescriptor  =
+  <| AddressDescriptor_fault : FaultRecord;
+     AddressDescriptor_memattrs : MemoryAttributes;
+     AddressDescriptor_paddress : FullAddress;
+     AddressDescriptor_vaddress : 64 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ DescriptorUpdate  =
+  <| DescriptorUpdate_AF : bool;
+     DescriptorUpdate_AP : bool;
+     DescriptorUpdate_descaddr : AddressDescriptor  |>`;
+
+
+
+val _ = Hol_datatype `
+ MemAtomicOp =
+  MemAtomicOp_ADD
+  | MemAtomicOp_BIC
+  | MemAtomicOp_EOR
+  | MemAtomicOp_ORR
+  | MemAtomicOp_SMAX
+  | MemAtomicOp_SMIN
+  | MemAtomicOp_UMAX
+  | MemAtomicOp_UMIN
+  | MemAtomicOp_SWP`;
+
+
+
+
+val _ = Hol_datatype `
+ FPType = FPType_Nonzero | FPType_Zero | FPType_Infinity | FPType_QNaN | FPType_SNaN`;
+
+
+
+
+val _ = Hol_datatype `
+ FPExc =
+  FPExc_InvalidOp
+  | FPExc_DivideByZero
+  | FPExc_Overflow
+  | FPExc_Underflow
+  | FPExc_Inexact
+  | FPExc_InputDenorm`;
+
+
+
+
+val _ = Hol_datatype `
+ FPRounding =
+  FPRounding_TIEEVEN
+  | FPRounding_POSINF
+  | FPRounding_NEGINF
+  | FPRounding_ZERO
+  | FPRounding_TIEAWAY
+  | FPRounding_ODD`;
+
+
+
+
+val _ = Hol_datatype `
+ SysRegAccess =
+  SysRegAccess_OK
+  | SysRegAccess_UNDEFINED
+  | SysRegAccess_TrapToEL1
+  | SysRegAccess_TrapToEL2
+  | SysRegAccess_TrapToEL3`;
+
+
+
+
+val _ = Hol_datatype `
+ SRType = SRType_LSL | SRType_LSR | SRType_ASR | SRType_ROR | SRType_RRX`;
+
+
+
+
+val _ = Hol_datatype `
+ ShiftType = ShiftType_LSL | ShiftType_LSR | ShiftType_ASR | ShiftType_ROR`;
+
+
+
+
+val _ = Hol_datatype `
+ PrefetchHint = Prefetch_READ | Prefetch_WRITE | Prefetch_EXEC`;
+
+
+
+
+val _ = Hol_datatype `
+ InterruptID =
+  InterruptID_PMUIRQ
+  | InterruptID_COMMIRQ
+  | InterruptID_CTIIRQ
+  | InterruptID_COMMRX
+  | InterruptID_COMMTX`;
+
+
+
+
+val _ = Hol_datatype `
+ CrossTriggerOut =
+  CrossTriggerOut_DebugRequest
+  | CrossTriggerOut_RestartRequest
+  | CrossTriggerOut_IRQ
+  | CrossTriggerOut_RSVD3
+  | CrossTriggerOut_TraceExtIn0
+  | CrossTriggerOut_TraceExtIn1
+  | CrossTriggerOut_TraceExtIn2
+  | CrossTriggerOut_TraceExtIn3`;
+
+
+
+
+val _ = Hol_datatype `
+ CrossTriggerIn =
+  CrossTriggerIn_CrossHalt
+  | CrossTriggerIn_PMUOverflow
+  | CrossTriggerIn_RSVD2
+  | CrossTriggerIn_RSVD3
+  | CrossTriggerIn_TraceExtOut0
+  | CrossTriggerIn_TraceExtOut1
+  | CrossTriggerIn_TraceExtOut2
+  | CrossTriggerIn_TraceExtOut3`;
+
+
+
+
+val _ = Hol_datatype `
+ MemBarrierOp = MemBarrierOp_DSB | MemBarrierOp_DMB | MemBarrierOp_ISB`;
+
+
+
+
+val _ = Hol_datatype `
+ AccessDescriptor  =
+  <| AccessDescriptor_acctype : AccType;
+     AccessDescriptor_page_table_walk : bool;
+     AccessDescriptor_secondstage : bool;
+     AccessDescriptor_s2fs1walk : bool;
+     AccessDescriptor_level : ii  |>`;
+
+
+
+val _ = Hol_datatype `
+ Permissions  =
+  <| Permissions_ap : 3 bits;
+     Permissions_xn : 1 bits;
+     Permissions_xxn : 1 bits;
+     Permissions_pxn : 1 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ TLBRecord  =
+  <| TLBRecord_perms : Permissions;
+     TLBRecord_nG : 1 bits;
+     TLBRecord_domain : 4 bits;
+     TLBRecord_contiguous : bool;
+     TLBRecord_level : ii;
+     TLBRecord_blocksize : ii;
+     TLBRecord_descupdate : DescriptorUpdate;
+     TLBRecord_CnP : 1 bits;
+     TLBRecord_addrdesc : AddressDescriptor  |>`;
+
+
+
+val _ = Hol_datatype `
+ ImmediateOp = ImmediateOp_MOVI | ImmediateOp_MVNI | ImmediateOp_ORR | ImmediateOp_BIC`;
+
+
+
+
+val _ = Hol_datatype `
+ MoveWideOp = MoveWideOp_N | MoveWideOp_Z | MoveWideOp_K`;
+
+
+
+
+val _ = Hol_datatype `
+ SystemAccessType = SystemAccessType_RT | SystemAccessType_RRT | SystemAccessType_DT`;
+
+
+
+
+val _ = Hol_datatype `
+ VBitOp = VBitOp_VBIF | VBitOp_VBIT | VBitOp_VBSL | VBitOp_VEOR`;
+
+
+
+
+val _ = Hol_datatype `
+ TimeStamp = TimeStamp_None | TimeStamp_Virtual | TimeStamp_Physical`;
+
+
+
+
+val _ = Hol_datatype `
+ PrivilegeLevel = PL3 | PL2 | PL1 | PL0`;
+
+
+
+
+val _ = Hol_datatype `
+ AArch32_SErrorSyndrome  =
+  <| AArch32_SErrorSyndrome_AET : 2 bits; AArch32_SErrorSyndrome_ExT : 1 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ SystemOp = Sys_AT | Sys_DC | Sys_IC | Sys_TLBI | Sys_SYS`;
+
+
+
+
+val _ = Hol_datatype `
+ PCSample  =
+  <| PCSample_valid_name : bool;
+     PCSample_pc : 64 bits;
+     PCSample_el : 2 bits;
+     PCSample_rw : 1 bits;
+     PCSample_ns : 1 bits;
+     PCSample_contextidr : 32 bits;
+     PCSample_contextidr_el2 : 32 bits;
+     PCSample_vmid : 16 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ ReduceOp =
+  ReduceOp_FMINNUM | ReduceOp_FMAXNUM | ReduceOp_FMIN | ReduceOp_FMAX | ReduceOp_FADD | ReduceOp_ADD`;
+
+
+
+
+val _ = Hol_datatype `
+ LogicalOp = LogicalOp_AND | LogicalOp_EOR | LogicalOp_ORR`;
+
+
+
+
+val _ = Hol_datatype `
+ ExtendType =
+  ExtendType_SXTB
+  | ExtendType_SXTH
+  | ExtendType_SXTW
+  | ExtendType_SXTX
+  | ExtendType_UXTB
+  | ExtendType_UXTH
+  | ExtendType_UXTW
+  | ExtendType_UXTX`;
+
+
+
+
+val _ = Hol_datatype `
+ SystemHintOp =
+  SystemHintOp_NOP
+  | SystemHintOp_YIELD
+  | SystemHintOp_WFE
+  | SystemHintOp_WFI
+  | SystemHintOp_SEV
+  | SystemHintOp_SEVL
+  | SystemHintOp_ESB
+  | SystemHintOp_PSB`;
+
+
+
+
+val _ = Hol_datatype `
+ MemOp = MemOp_LOAD | MemOp_STORE | MemOp_PREFETCH`;
+
+
+
+
+val _ = Hol_datatype `
+ OpType = OpType_Load | OpType_Store | OpType_LoadAtomic | OpType_Branch | OpType_Other`;
+
+
+
+
+val _ = Hol_datatype `
+ FPUnaryOp = FPUnaryOp_ABS | FPUnaryOp_MOV | FPUnaryOp_NEG | FPUnaryOp_SQRT`;
+
+
+
+
+val _ = Hol_datatype `
+ CompareOp = CompareOp_GT | CompareOp_GE | CompareOp_EQ | CompareOp_LE | CompareOp_LT`;
+
+
+
+
+val _ = Hol_datatype `
+ PSTATEField =
+  PSTATEField_DAIFSet | PSTATEField_DAIFClr | PSTATEField_PAN | PSTATEField_UAO | PSTATEField_SP`;
+
+
+
+
+val _ = Hol_datatype `
+ FPMaxMinOp = FPMaxMinOp_MAX | FPMaxMinOp_MIN | FPMaxMinOp_MAXNUM | FPMaxMinOp_MINNUM`;
+
+
+
+
+val _ = Hol_datatype `
+ CountOp = CountOp_CLZ | CountOp_CLS | CountOp_CNT`;
+
+
+
+
+val _ = Hol_datatype `
+ VFPNegMul = VFPNegMul_VNMLA | VFPNegMul_VNMLS | VFPNegMul_VNMUL`;
+
+
+
+
+val _ = Hol_datatype `
+ VBitOps = VBitOps_VBIF | VBitOps_VBIT | VBitOps_VBSL`;
+
+
+
+
+val _ = Hol_datatype `
+ VCGEtype = VCGEtype_signed | VCGEtype_unsigned | VCGEtype_fp`;
+
+
+
+
+val _ = Hol_datatype `
+ VCGTtype = VCGTtype_signed | VCGTtype_unsigned | VCGTtype_fp`;
+
+
+
+
+val _ = Hol_datatype `
+ InstrEnc = A64 | A32 | T16 | T32`;
+
+
+
+
+
+
+val _ = Hol_datatype `
+ register_value  =
+    Regval_vector of ((ii # bool # register_value list))
+  | Regval_list of ( register_value list)
+  | Regval_option of ( register_value option)
+  | Regval_ProcState of (ProcState)
+  | Regval___InstrEnc of (InstrEnc)
+  | Regval_bool of (bool)
+  | Regval_signal of (signal)
+  | Regval_vector_128_dec_bit of ( 128 words$word)
+  | Regval_vector_1_dec_bit of ( 1 words$word)
+  | Regval_vector_32_dec_bit of ( 32 words$word)
+  | Regval_vector_4_dec_bit of ( 4 words$word)
+  | Regval_vector_52_dec_bit of ( 52 words$word)
+  | Regval_vector_64_dec_bit of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ regstate  =
+  <| APDAKeyHi_EL1 :  64 words$word;
+     APDAKeyLo_EL1 :  64 words$word;
+     APDBKeyHi_EL1 :  64 words$word;
+     APDBKeyLo_EL1 :  64 words$word;
+     APGAKeyHi_EL1 :  64 words$word;
+     APGAKeyLo_EL1 :  64 words$word;
+     APIAKeyHi_EL1 :  64 words$word;
+     APIAKeyLo_EL1 :  64 words$word;
+     APIBKeyHi_EL1 :  64 words$word;
+     APIBKeyLo_EL1 :  64 words$word;
+     CONTEXTIDR_EL1 :  32 words$word;
+     CONTEXTIDR_EL2 :  32 words$word;
+     CPACR_EL1 :  32 words$word;
+     CPTR_EL2 :  32 words$word;
+     CPTR_EL3 :  32 words$word;
+     DBGBCR_EL1 : ( 32 words$word) list;
+     DBGBVR_EL1 : ( 64 words$word) list;
+     DBGEN : signal;
+     DBGOSDLR :  32 words$word;
+     DBGOSLSR :  32 words$word;
+     DBGPRCR :  32 words$word;
+     DBGPRCR_EL1 :  32 words$word;
+     DBGWCR_EL1 : ( 32 words$word) list;
+     DBGWVR_EL1 : ( 64 words$word) list;
+     DLR :  32 words$word;
+     DLR_EL0 :  64 words$word;
+     DSPSR :  32 words$word;
+     DSPSR_EL0 :  32 words$word;
+     EDSCR :  32 words$word;
+     ELR_EL1 :  64 words$word;
+     ELR_EL2 :  64 words$word;
+     ELR_EL3 :  64 words$word;
+     ELR_hyp :  32 words$word;
+     ESR_EL1 :  32 words$word;
+     ESR_EL2 :  32 words$word;
+     ESR_EL3 :  32 words$word;
+     EventRegister :  1 words$word;
+     FAR_EL1 :  64 words$word;
+     FAR_EL2 :  64 words$word;
+     FAR_EL3 :  64 words$word;
+     FPCR :  32 words$word;
+     FPEXC :  32 words$word;
+     FPSCR :  32 words$word;
+     FPSR :  32 words$word;
+     HCR :  32 words$word;
+     HCR2 :  32 words$word;
+     HCR_EL2 :  64 words$word;
+     HDCR :  32 words$word;
+     HDFAR :  32 words$word;
+     HIFAR :  32 words$word;
+     HPFAR :  32 words$word;
+     HPFAR_EL2 :  64 words$word;
+     HSCTLR :  32 words$word;
+     HSR :  32 words$word;
+     HVBAR :  32 words$word;
+     ID_AA64DFR0_EL1 :  64 words$word;
+     LR_mon :  32 words$word;
+     MAIR_EL1 :  64 words$word;
+     MAIR_EL2 :  64 words$word;
+     MAIR_EL3 :  64 words$word;
+     MDCR_EL2 :  32 words$word;
+     MDCR_EL3 :  32 words$word;
+     MDSCR_EL1 :  32 words$word;
+     OSDLR_EL1 :  32 words$word;
+     OSLSR_EL1 :  32 words$word;
+     PSTATE : ProcState;
+     RC0 : ( 64 words$word) list;
+     RVBAR_EL1 :  64 words$word;
+     RVBAR_EL2 :  64 words$word;
+     RVBAR_EL3 :  64 words$word;
+     SCR :  32 words$word;
+     SCR_EL3 :  32 words$word;
+     SCTLR :  32 words$word;
+     SCTLR_EL1 :  32 words$word;
+     SCTLR_EL2 :  32 words$word;
+     SCTLR_EL3 :  32 words$word;
+     SDCR :  32 words$word;
+     SDER :  32 words$word;
+     SPIDEN : signal;
+     SPSR_EL1 :  32 words$word;
+     SPSR_EL2 :  32 words$word;
+     SPSR_EL3 :  32 words$word;
+     SPSR_abt :  32 words$word;
+     SPSR_fiq :  32 words$word;
+     SPSR_hyp :  32 words$word;
+     SPSR_irq :  32 words$word;
+     SPSR_mon :  32 words$word;
+     SPSR_svc :  32 words$word;
+     SPSR_und :  32 words$word;
+     SP_EL0 :  64 words$word;
+     SP_EL1 :  64 words$word;
+     SP_EL2 :  64 words$word;
+     SP_EL3 :  64 words$word;
+     SP_mon :  32 words$word;
+     TCR_EL1 :  64 words$word;
+     TCR_EL2 :  64 words$word;
+     TCR_EL3 :  32 words$word;
+     TTBCR :  32 words$word;
+     TTBR0_EL1 :  64 words$word;
+     TTBR0_EL2 :  64 words$word;
+     TTBR0_EL3 :  64 words$word;
+     TTBR1_EL1 :  64 words$word;
+     TTBR1_EL2 :  64 words$word;
+     VBAR :  32 words$word;
+     VBAR_EL1 :  64 words$word;
+     VBAR_EL2 :  64 words$word;
+     VBAR_EL3 :  64 words$word;
+     VDFSR :  32 words$word;
+     VSESR_EL2 :  32 words$word;
+     VTCR_EL2 :  32 words$word;
+     VTTBR_EL2 :  64 words$word;
+     PC :  64 words$word;
+     R : ( 64 words$word) list;
+     V : ( 128 words$word) list;
+     BranchTaken : bool;
+     ExclusiveLocal : bool;
+     Memory :  52 words$word;
+     PendingInterrupt : bool;
+     PendingPhysicalSError : bool;
+     Sleeping : bool;
+     ThisInstr :  32 words$word;
+     ThisInstrEnc : InstrEnc;
+     currentCond :  4 words$word;
+     unconditional : bool  |>`;
+
+
+
+
+
+(*val ProcState_of_regval : register_value -> maybe ProcState*)
+
+val _ = Define `
+ ((ProcState_of_regval:register_value ->(ProcState)option) merge_var=
+    ((case merge_var of   Regval_ProcState (v) => SOME v | g__281 => NONE )))`;
+
+
+(*val regval_of_ProcState : ProcState -> register_value*)
+
+val _ = Define `
+ ((regval_of_ProcState:ProcState -> register_value) v=  (Regval_ProcState v))`;
+
+
+(*val __InstrEnc_of_regval : register_value -> maybe __InstrEnc*)
+
+val _ = Define `
+ ((InstrEnc_of_regval:register_value ->(InstrEnc)option) merge_var=
+    ((case merge_var of   Regval___InstrEnc (v) => SOME v | g__280 => NONE )))`;
+
+
+(*val regval_of___InstrEnc : __InstrEnc -> register_value*)
+
+val _ = Define `
+ ((regval_of___InstrEnc:InstrEnc -> register_value) v=  (Regval___InstrEnc v))`;
+
+
+(*val bool_of_regval : register_value -> maybe bool*)
+
+val _ = Define `
+ ((bool_of_regval:register_value ->(bool)option) merge_var=
+    ((case merge_var of   Regval_bool (v) => SOME v | g__279 => NONE )))`;
+
+
+(*val regval_of_bool : bool -> register_value*)
+
+val _ = Define `
+ ((regval_of_bool:bool -> register_value) v=  (Regval_bool v))`;
+
+
+(*val signal_of_regval : register_value -> maybe signal*)
+
+val _ = Define `
+ ((signal_of_regval:register_value ->(signal)option) merge_var=
+    ((case merge_var of   Regval_signal (v) => SOME v | g__278 => NONE )))`;
+
+
+(*val regval_of_signal : signal -> register_value*)
+
+val _ = Define `
+ ((regval_of_signal:signal -> register_value) v=  (Regval_signal v))`;
+
+
+(*val vector_128_dec_bit_of_regval : register_value -> maybe (mword ty128)*)
+
+val _ = Define `
+ ((vector_128_dec_bit_of_regval:register_value ->((128)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_128_dec_bit (v) => SOME v | g__277 => NONE )))`;
+
+
+(*val regval_of_vector_128_dec_bit : mword ty128 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_128_dec_bit:(128)words$word -> register_value) v=  (Regval_vector_128_dec_bit v))`;
+
+
+(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*)
+
+val _ = Define `
+ ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_1_dec_bit (v) => SOME v | g__276 => NONE )))`;
+
+
+(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v=  (Regval_vector_1_dec_bit v))`;
+
+
+(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_32_dec_bit (v) => SOME v | g__275 => NONE )))`;
+
+
+(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v=  (Regval_vector_32_dec_bit v))`;
+
+
+(*val vector_4_dec_bit_of_regval : register_value -> maybe (mword ty4)*)
+
+val _ = Define `
+ ((vector_4_dec_bit_of_regval:register_value ->((4)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_4_dec_bit (v) => SOME v | g__274 => NONE )))`;
+
+
+(*val regval_of_vector_4_dec_bit : mword ty4 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_4_dec_bit:(4)words$word -> register_value) v=  (Regval_vector_4_dec_bit v))`;
+
+
+(*val vector_52_dec_bit_of_regval : register_value -> maybe (mword ty52)*)
+
+val _ = Define `
+ ((vector_52_dec_bit_of_regval:register_value ->((52)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_52_dec_bit (v) => SOME v | g__273 => NONE )))`;
+
+
+(*val regval_of_vector_52_dec_bit : mword ty52 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_52_dec_bit:(52)words$word -> register_value) v=  (Regval_vector_52_dec_bit v))`;
+
+
+(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
+
+val _ = Define `
+ ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__272 => NONE )))`;
+
+
+(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v=  (Regval_vector_64_dec_bit v))`;
+
+
+
+
+(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
+  (\x .  (case x of
+               Regval_vector (_, _, v) => just_list (MAP of_regval1 v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`;
+
+
+(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
+  (\x .  (case x of
+               Regval_list v => just_list (MAP of_regval1 v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs=  (Regval_list (MAP regval_of1 xs)))`;
+
+
+(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
+val _ = Define `
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= 
+  (\x .  (case x of
+               Regval_option v => SOME (OPTION_BIND v of_regval1)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
+val _ = Define `
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v=  (Regval_option (OPTION_MAP regval_of1 v)))`;
+
+
+
+val _ = Define `
+ ((APDAKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APDAKeyHi_EL1";
+  read_from := (\ s .  s.APDAKeyHi_EL1);
+  write_to := (\ v s .  (( s with<| APDAKeyHi_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APDAKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APDAKeyLo_EL1";
+  read_from := (\ s .  s.APDAKeyLo_EL1);
+  write_to := (\ v s .  (( s with<| APDAKeyLo_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APDBKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APDBKeyHi_EL1";
+  read_from := (\ s .  s.APDBKeyHi_EL1);
+  write_to := (\ v s .  (( s with<| APDBKeyHi_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APDBKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APDBKeyLo_EL1";
+  read_from := (\ s .  s.APDBKeyLo_EL1);
+  write_to := (\ v s .  (( s with<| APDBKeyLo_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APGAKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APGAKeyHi_EL1";
+  read_from := (\ s .  s.APGAKeyHi_EL1);
+  write_to := (\ v s .  (( s with<| APGAKeyHi_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APGAKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APGAKeyLo_EL1";
+  read_from := (\ s .  s.APGAKeyLo_EL1);
+  write_to := (\ v s .  (( s with<| APGAKeyLo_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APIAKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APIAKeyHi_EL1";
+  read_from := (\ s .  s.APIAKeyHi_EL1);
+  write_to := (\ v s .  (( s with<| APIAKeyHi_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APIAKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APIAKeyLo_EL1";
+  read_from := (\ s .  s.APIAKeyLo_EL1);
+  write_to := (\ v s .  (( s with<| APIAKeyLo_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APIBKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APIBKeyHi_EL1";
+  read_from := (\ s .  s.APIBKeyHi_EL1);
+  write_to := (\ v s .  (( s with<| APIBKeyHi_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((APIBKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "APIBKeyLo_EL1";
+  read_from := (\ s .  s.APIBKeyLo_EL1);
+  write_to := (\ v s .  (( s with<| APIBKeyLo_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CONTEXTIDR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CONTEXTIDR_EL1";
+  read_from := (\ s .  s.CONTEXTIDR_EL1);
+  write_to := (\ v s .  (( s with<| CONTEXTIDR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CONTEXTIDR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CONTEXTIDR_EL2";
+  read_from := (\ s .  s.CONTEXTIDR_EL2);
+  write_to := (\ v s .  (( s with<| CONTEXTIDR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CPACR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CPACR_EL1";
+  read_from := (\ s .  s.CPACR_EL1);
+  write_to := (\ v s .  (( s with<| CPACR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CPTR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CPTR_EL2";
+  read_from := (\ s .  s.CPTR_EL2);
+  write_to := (\ v s .  (( s with<| CPTR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CPTR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CPTR_EL3";
+  read_from := (\ s .  s.CPTR_EL3);
+  write_to := (\ v s .  (( s with<| CPTR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DBGBCR_EL1_ref:((regstate),(register_value),(((32)words$word)list))register_ref)=  (<|
+  name := "DBGBCR_EL1";
+  read_from := (\ s .  s.DBGBCR_EL1);
+  write_to := (\ v s .  (( s with<| DBGBCR_EL1 := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_32_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_32_dec_bit v)(( 16 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((DBGBVR_EL1_ref:((regstate),(register_value),(((64)words$word)list))register_ref)=  (<|
+  name := "DBGBVR_EL1";
+  read_from := (\ s .  s.DBGBVR_EL1);
+  write_to := (\ v s .  (( s with<| DBGBVR_EL1 := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 16 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((DBGEN_ref:((regstate),(register_value),(signal))register_ref)=  (<|
+  name := "DBGEN";
+  read_from := (\ s .  s.DBGEN);
+  write_to := (\ v s .  (( s with<| DBGEN := v |>)));
+  of_regval := (\ v .  signal_of_regval v);
+  regval_of := (\ v .  regval_of_signal v) |>))`;
+
+
+val _ = Define `
+ ((DBGOSDLR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DBGOSDLR";
+  read_from := (\ s .  s.DBGOSDLR);
+  write_to := (\ v s .  (( s with<| DBGOSDLR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DBGOSLSR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DBGOSLSR";
+  read_from := (\ s .  s.DBGOSLSR);
+  write_to := (\ v s .  (( s with<| DBGOSLSR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DBGPRCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DBGPRCR";
+  read_from := (\ s .  s.DBGPRCR);
+  write_to := (\ v s .  (( s with<| DBGPRCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DBGPRCR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DBGPRCR_EL1";
+  read_from := (\ s .  s.DBGPRCR_EL1);
+  write_to := (\ v s .  (( s with<| DBGPRCR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DBGWCR_EL1_ref:((regstate),(register_value),(((32)words$word)list))register_ref)=  (<|
+  name := "DBGWCR_EL1";
+  read_from := (\ s .  s.DBGWCR_EL1);
+  write_to := (\ v s .  (( s with<| DBGWCR_EL1 := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_32_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_32_dec_bit v)(( 16 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((DBGWVR_EL1_ref:((regstate),(register_value),(((64)words$word)list))register_ref)=  (<|
+  name := "DBGWVR_EL1";
+  read_from := (\ s .  s.DBGWVR_EL1);
+  write_to := (\ v s .  (( s with<| DBGWVR_EL1 := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 16 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((DLR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DLR";
+  read_from := (\ s .  s.DLR);
+  write_to := (\ v s .  (( s with<| DLR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DLR_EL0_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "DLR_EL0";
+  read_from := (\ s .  s.DLR_EL0);
+  write_to := (\ v s .  (( s with<| DLR_EL0 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DSPSR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DSPSR";
+  read_from := (\ s .  s.DSPSR);
+  write_to := (\ v s .  (( s with<| DSPSR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((DSPSR_EL0_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "DSPSR_EL0";
+  read_from := (\ s .  s.DSPSR_EL0);
+  write_to := (\ v s .  (( s with<| DSPSR_EL0 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((EDSCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "EDSCR";
+  read_from := (\ s .  s.EDSCR);
+  write_to := (\ v s .  (( s with<| EDSCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ELR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "ELR_EL1";
+  read_from := (\ s .  s.ELR_EL1);
+  write_to := (\ v s .  (( s with<| ELR_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ELR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "ELR_EL2";
+  read_from := (\ s .  s.ELR_EL2);
+  write_to := (\ v s .  (( s with<| ELR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ELR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "ELR_EL3";
+  read_from := (\ s .  s.ELR_EL3);
+  write_to := (\ v s .  (( s with<| ELR_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ELR_hyp_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "ELR_hyp";
+  read_from := (\ s .  s.ELR_hyp);
+  write_to := (\ v s .  (( s with<| ELR_hyp := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ESR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "ESR_EL1";
+  read_from := (\ s .  s.ESR_EL1);
+  write_to := (\ v s .  (( s with<| ESR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ESR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "ESR_EL2";
+  read_from := (\ s .  s.ESR_EL2);
+  write_to := (\ v s .  (( s with<| ESR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ESR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "ESR_EL3";
+  read_from := (\ s .  s.ESR_EL3);
+  write_to := (\ v s .  (( s with<| ESR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((EventRegister_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "EventRegister";
+  read_from := (\ s .  s.EventRegister);
+  write_to := (\ v s .  (( s with<| EventRegister := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FAR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "FAR_EL1";
+  read_from := (\ s .  s.FAR_EL1);
+  write_to := (\ v s .  (( s with<| FAR_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "FAR_EL2";
+  read_from := (\ s .  s.FAR_EL2);
+  write_to := (\ v s .  (( s with<| FAR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FAR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "FAR_EL3";
+  read_from := (\ s .  s.FAR_EL3);
+  write_to := (\ v s .  (( s with<| FAR_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FPCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "FPCR";
+  read_from := (\ s .  s.FPCR);
+  write_to := (\ v s .  (( s with<| FPCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FPEXC_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "FPEXC";
+  read_from := (\ s .  s.FPEXC);
+  write_to := (\ v s .  (( s with<| FPEXC := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FPSCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "FPSCR";
+  read_from := (\ s .  s.FPSCR);
+  write_to := (\ v s .  (( s with<| FPSCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((FPSR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "FPSR";
+  read_from := (\ s .  s.FPSR);
+  write_to := (\ v s .  (( s with<| FPSR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HCR";
+  read_from := (\ s .  s.HCR);
+  write_to := (\ v s .  (( s with<| HCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HCR2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HCR2";
+  read_from := (\ s .  s.HCR2);
+  write_to := (\ v s .  (( s with<| HCR2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HCR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "HCR_EL2";
+  read_from := (\ s .  s.HCR_EL2);
+  write_to := (\ v s .  (( s with<| HCR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HDCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HDCR";
+  read_from := (\ s .  s.HDCR);
+  write_to := (\ v s .  (( s with<| HDCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HDFAR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HDFAR";
+  read_from := (\ s .  s.HDFAR);
+  write_to := (\ v s .  (( s with<| HDFAR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HIFAR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HIFAR";
+  read_from := (\ s .  s.HIFAR);
+  write_to := (\ v s .  (( s with<| HIFAR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HPFAR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HPFAR";
+  read_from := (\ s .  s.HPFAR);
+  write_to := (\ v s .  (( s with<| HPFAR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HPFAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "HPFAR_EL2";
+  read_from := (\ s .  s.HPFAR_EL2);
+  write_to := (\ v s .  (( s with<| HPFAR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HSCTLR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HSCTLR";
+  read_from := (\ s .  s.HSCTLR);
+  write_to := (\ v s .  (( s with<| HSCTLR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HSR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HSR";
+  read_from := (\ s .  s.HSR);
+  write_to := (\ v s .  (( s with<| HSR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HVBAR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "HVBAR";
+  read_from := (\ s .  s.HVBAR);
+  write_to := (\ v s .  (( s with<| HVBAR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ID_AA64DFR0_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "ID_AA64DFR0_EL1";
+  read_from := (\ s .  s.ID_AA64DFR0_EL1);
+  write_to := (\ v s .  (( s with<| ID_AA64DFR0_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((LR_mon_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "LR_mon";
+  read_from := (\ s .  s.LR_mon);
+  write_to := (\ v s .  (( s with<| LR_mon := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((MAIR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "MAIR_EL1";
+  read_from := (\ s .  s.MAIR_EL1);
+  write_to := (\ v s .  (( s with<| MAIR_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((MAIR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "MAIR_EL2";
+  read_from := (\ s .  s.MAIR_EL2);
+  write_to := (\ v s .  (( s with<| MAIR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((MAIR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "MAIR_EL3";
+  read_from := (\ s .  s.MAIR_EL3);
+  write_to := (\ v s .  (( s with<| MAIR_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((MDCR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "MDCR_EL2";
+  read_from := (\ s .  s.MDCR_EL2);
+  write_to := (\ v s .  (( s with<| MDCR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((MDCR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "MDCR_EL3";
+  read_from := (\ s .  s.MDCR_EL3);
+  write_to := (\ v s .  (( s with<| MDCR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((MDSCR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "MDSCR_EL1";
+  read_from := (\ s .  s.MDSCR_EL1);
+  write_to := (\ v s .  (( s with<| MDSCR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((OSDLR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "OSDLR_EL1";
+  read_from := (\ s .  s.OSDLR_EL1);
+  write_to := (\ v s .  (( s with<| OSDLR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((OSLSR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "OSLSR_EL1";
+  read_from := (\ s .  s.OSLSR_EL1);
+  write_to := (\ v s .  (( s with<| OSLSR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PSTATE_ref:((regstate),(register_value),(ProcState))register_ref)=  (<|
+  name := "PSTATE";
+  read_from := (\ s .  s.PSTATE);
+  write_to := (\ v s .  (( s with<| PSTATE := v |>)));
+  of_regval := (\ v .  ProcState_of_regval v);
+  regval_of := (\ v .  regval_of_ProcState v) |>))`;
+
+
+val _ = Define `
+ ((RC_ref:((regstate),(register_value),(((64)words$word)list))register_ref)=  (<|
+  name := "RC";
+  read_from := (\ s .  s.RC0);
+  write_to := (\ v s .  (( s with<| RC0 := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 5 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((RVBAR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "RVBAR_EL1";
+  read_from := (\ s .  s.RVBAR_EL1);
+  write_to := (\ v s .  (( s with<| RVBAR_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((RVBAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "RVBAR_EL2";
+  read_from := (\ s .  s.RVBAR_EL2);
+  write_to := (\ v s .  (( s with<| RVBAR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((RVBAR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "RVBAR_EL3";
+  read_from := (\ s .  s.RVBAR_EL3);
+  write_to := (\ v s .  (( s with<| RVBAR_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SCR";
+  read_from := (\ s .  s.SCR);
+  write_to := (\ v s .  (( s with<| SCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SCR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SCR_EL3";
+  read_from := (\ s .  s.SCR_EL3);
+  write_to := (\ v s .  (( s with<| SCR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SCTLR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SCTLR";
+  read_from := (\ s .  s.SCTLR);
+  write_to := (\ v s .  (( s with<| SCTLR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SCTLR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SCTLR_EL1";
+  read_from := (\ s .  s.SCTLR_EL1);
+  write_to := (\ v s .  (( s with<| SCTLR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SCTLR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SCTLR_EL2";
+  read_from := (\ s .  s.SCTLR_EL2);
+  write_to := (\ v s .  (( s with<| SCTLR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SCTLR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SCTLR_EL3";
+  read_from := (\ s .  s.SCTLR_EL3);
+  write_to := (\ v s .  (( s with<| SCTLR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SDCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SDCR";
+  read_from := (\ s .  s.SDCR);
+  write_to := (\ v s .  (( s with<| SDCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SDER_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SDER";
+  read_from := (\ s .  s.SDER);
+  write_to := (\ v s .  (( s with<| SDER := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPIDEN_ref:((regstate),(register_value),(signal))register_ref)=  (<|
+  name := "SPIDEN";
+  read_from := (\ s .  s.SPIDEN);
+  write_to := (\ v s .  (( s with<| SPIDEN := v |>)));
+  of_regval := (\ v .  signal_of_regval v);
+  regval_of := (\ v .  regval_of_signal v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_EL1";
+  read_from := (\ s .  s.SPSR_EL1);
+  write_to := (\ v s .  (( s with<| SPSR_EL1 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_EL2";
+  read_from := (\ s .  s.SPSR_EL2);
+  write_to := (\ v s .  (( s with<| SPSR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_EL3";
+  read_from := (\ s .  s.SPSR_EL3);
+  write_to := (\ v s .  (( s with<| SPSR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_abt_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_abt";
+  read_from := (\ s .  s.SPSR_abt);
+  write_to := (\ v s .  (( s with<| SPSR_abt := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_fiq_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_fiq";
+  read_from := (\ s .  s.SPSR_fiq);
+  write_to := (\ v s .  (( s with<| SPSR_fiq := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_hyp_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_hyp";
+  read_from := (\ s .  s.SPSR_hyp);
+  write_to := (\ v s .  (( s with<| SPSR_hyp := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_irq_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_irq";
+  read_from := (\ s .  s.SPSR_irq);
+  write_to := (\ v s .  (( s with<| SPSR_irq := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_mon_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_mon";
+  read_from := (\ s .  s.SPSR_mon);
+  write_to := (\ v s .  (( s with<| SPSR_mon := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_svc_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_svc";
+  read_from := (\ s .  s.SPSR_svc);
+  write_to := (\ v s .  (( s with<| SPSR_svc := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SPSR_und_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SPSR_und";
+  read_from := (\ s .  s.SPSR_und);
+  write_to := (\ v s .  (( s with<| SPSR_und := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SP_EL0_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "SP_EL0";
+  read_from := (\ s .  s.SP_EL0);
+  write_to := (\ v s .  (( s with<| SP_EL0 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SP_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "SP_EL1";
+  read_from := (\ s .  s.SP_EL1);
+  write_to := (\ v s .  (( s with<| SP_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SP_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "SP_EL2";
+  read_from := (\ s .  s.SP_EL2);
+  write_to := (\ v s .  (( s with<| SP_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SP_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "SP_EL3";
+  read_from := (\ s .  s.SP_EL3);
+  write_to := (\ v s .  (( s with<| SP_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((SP_mon_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "SP_mon";
+  read_from := (\ s .  s.SP_mon);
+  write_to := (\ v s .  (( s with<| SP_mon := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TCR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TCR_EL1";
+  read_from := (\ s .  s.TCR_EL1);
+  write_to := (\ v s .  (( s with<| TCR_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TCR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TCR_EL2";
+  read_from := (\ s .  s.TCR_EL2);
+  write_to := (\ v s .  (( s with<| TCR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TCR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "TCR_EL3";
+  read_from := (\ s .  s.TCR_EL3);
+  write_to := (\ v s .  (( s with<| TCR_EL3 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TTBCR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "TTBCR";
+  read_from := (\ s .  s.TTBCR);
+  write_to := (\ v s .  (( s with<| TTBCR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TTBR0_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TTBR0_EL1";
+  read_from := (\ s .  s.TTBR0_EL1);
+  write_to := (\ v s .  (( s with<| TTBR0_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TTBR0_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TTBR0_EL2";
+  read_from := (\ s .  s.TTBR0_EL2);
+  write_to := (\ v s .  (( s with<| TTBR0_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TTBR0_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TTBR0_EL3";
+  read_from := (\ s .  s.TTBR0_EL3);
+  write_to := (\ v s .  (( s with<| TTBR0_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TTBR1_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TTBR1_EL1";
+  read_from := (\ s .  s.TTBR1_EL1);
+  write_to := (\ v s .  (( s with<| TTBR1_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TTBR1_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "TTBR1_EL2";
+  read_from := (\ s .  s.TTBR1_EL2);
+  write_to := (\ v s .  (( s with<| TTBR1_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VBAR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "VBAR";
+  read_from := (\ s .  s.VBAR);
+  write_to := (\ v s .  (( s with<| VBAR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VBAR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "VBAR_EL1";
+  read_from := (\ s .  s.VBAR_EL1);
+  write_to := (\ v s .  (( s with<| VBAR_EL1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VBAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "VBAR_EL2";
+  read_from := (\ s .  s.VBAR_EL2);
+  write_to := (\ v s .  (( s with<| VBAR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VBAR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "VBAR_EL3";
+  read_from := (\ s .  s.VBAR_EL3);
+  write_to := (\ v s .  (( s with<| VBAR_EL3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VDFSR_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "VDFSR";
+  read_from := (\ s .  s.VDFSR);
+  write_to := (\ v s .  (( s with<| VDFSR := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VSESR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "VSESR_EL2";
+  read_from := (\ s .  s.VSESR_EL2);
+  write_to := (\ v s .  (( s with<| VSESR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VTCR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "VTCR_EL2";
+  read_from := (\ s .  s.VTCR_EL2);
+  write_to := (\ v s .  (( s with<| VTCR_EL2 := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((VTTBR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "VTTBR_EL2";
+  read_from := (\ s .  s.VTTBR_EL2);
+  write_to := (\ v s .  (( s with<| VTTBR_EL2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "_PC";
+  read_from := (\ s .  s.PC);
+  write_to := (\ v s .  (( s with<| PC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((R_ref:((regstate),(register_value),(((64)words$word)list))register_ref)=  (<|
+  name := "_R";
+  read_from := (\ s .  s.R);
+  write_to := (\ v s .  (( s with<| R := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 31 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((V_ref:((regstate),(register_value),(((128)words$word)list))register_ref)=  (<|
+  name := "_V";
+  read_from := (\ s .  s.V);
+  write_to := (\ v s .  (( s with<| V := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_128_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_128_dec_bit v)(( 32 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((BranchTaken_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "__BranchTaken";
+  read_from := (\ s .  s.BranchTaken);
+  write_to := (\ v s .  (( s with<| BranchTaken := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((ExclusiveLocal_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "__ExclusiveLocal";
+  read_from := (\ s .  s.ExclusiveLocal);
+  write_to := (\ v s .  (( s with<| ExclusiveLocal := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((Memory_ref:((regstate),(register_value),((52)words$word))register_ref)=  (<|
+  name := "__Memory";
+  read_from := (\ s .  s.Memory);
+  write_to := (\ v s .  (( s with<| Memory := v |>)));
+  of_regval := (\ v .  vector_52_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_52_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PendingInterrupt_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "__PendingInterrupt";
+  read_from := (\ s .  s.PendingInterrupt);
+  write_to := (\ v s .  (( s with<| PendingInterrupt := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((PendingPhysicalSError_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "__PendingPhysicalSError";
+  read_from := (\ s .  s.PendingPhysicalSError);
+  write_to := (\ v s .  (( s with<| PendingPhysicalSError := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((Sleeping_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "__Sleeping";
+  read_from := (\ s .  s.Sleeping);
+  write_to := (\ v s .  (( s with<| Sleeping := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((ThisInstr_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "__ThisInstr";
+  read_from := (\ s .  s.ThisInstr);
+  write_to := (\ v s .  (( s with<| ThisInstr := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ThisInstrEnc_ref:((regstate),(register_value),(InstrEnc))register_ref)=  (<|
+  name := "__ThisInstrEnc";
+  read_from := (\ s .  s.ThisInstrEnc);
+  write_to := (\ v s .  (( s with<| ThisInstrEnc := v |>)));
+  of_regval := (\ v .  InstrEnc_of_regval v);
+  regval_of := (\ v .  regval_of___InstrEnc v) |>))`;
+
+
+val _ = Define `
+ ((currentCond_ref:((regstate),(register_value),((4)words$word))register_ref)=  (<|
+  name := "__currentCond";
+  read_from := (\ s .  s.currentCond);
+  write_to := (\ v s .  (( s with<| currentCond := v |>)));
+  of_regval := (\ v .  vector_4_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_4_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((unconditional_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "__unconditional";
+  read_from := (\ s .  s.unconditional);
+  write_to := (\ v s .  (( s with<| unconditional := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+(*val get_regval : string -> regstate -> maybe register_value*)
+val _ = Define `
+ ((get_regval:string -> regstate ->(register_value)option) reg_name s=
+   (if reg_name = "APDAKeyHi_EL1" then SOME (APDAKeyHi_EL1_ref.regval_of (APDAKeyHi_EL1_ref.read_from s)) else
+  if reg_name = "APDAKeyLo_EL1" then SOME (APDAKeyLo_EL1_ref.regval_of (APDAKeyLo_EL1_ref.read_from s)) else
+  if reg_name = "APDBKeyHi_EL1" then SOME (APDBKeyHi_EL1_ref.regval_of (APDBKeyHi_EL1_ref.read_from s)) else
+  if reg_name = "APDBKeyLo_EL1" then SOME (APDBKeyLo_EL1_ref.regval_of (APDBKeyLo_EL1_ref.read_from s)) else
+  if reg_name = "APGAKeyHi_EL1" then SOME (APGAKeyHi_EL1_ref.regval_of (APGAKeyHi_EL1_ref.read_from s)) else
+  if reg_name = "APGAKeyLo_EL1" then SOME (APGAKeyLo_EL1_ref.regval_of (APGAKeyLo_EL1_ref.read_from s)) else
+  if reg_name = "APIAKeyHi_EL1" then SOME (APIAKeyHi_EL1_ref.regval_of (APIAKeyHi_EL1_ref.read_from s)) else
+  if reg_name = "APIAKeyLo_EL1" then SOME (APIAKeyLo_EL1_ref.regval_of (APIAKeyLo_EL1_ref.read_from s)) else
+  if reg_name = "APIBKeyHi_EL1" then SOME (APIBKeyHi_EL1_ref.regval_of (APIBKeyHi_EL1_ref.read_from s)) else
+  if reg_name = "APIBKeyLo_EL1" then SOME (APIBKeyLo_EL1_ref.regval_of (APIBKeyLo_EL1_ref.read_from s)) else
+  if reg_name = "CONTEXTIDR_EL1" then SOME (CONTEXTIDR_EL1_ref.regval_of (CONTEXTIDR_EL1_ref.read_from s)) else
+  if reg_name = "CONTEXTIDR_EL2" then SOME (CONTEXTIDR_EL2_ref.regval_of (CONTEXTIDR_EL2_ref.read_from s)) else
+  if reg_name = "CPACR_EL1" then SOME (CPACR_EL1_ref.regval_of (CPACR_EL1_ref.read_from s)) else
+  if reg_name = "CPTR_EL2" then SOME (CPTR_EL2_ref.regval_of (CPTR_EL2_ref.read_from s)) else
+  if reg_name = "CPTR_EL3" then SOME (CPTR_EL3_ref.regval_of (CPTR_EL3_ref.read_from s)) else
+  if reg_name = "DBGBCR_EL1" then SOME (DBGBCR_EL1_ref.regval_of (DBGBCR_EL1_ref.read_from s)) else
+  if reg_name = "DBGBVR_EL1" then SOME (DBGBVR_EL1_ref.regval_of (DBGBVR_EL1_ref.read_from s)) else
+  if reg_name = "DBGEN" then SOME (DBGEN_ref.regval_of (DBGEN_ref.read_from s)) else
+  if reg_name = "DBGOSDLR" then SOME (DBGOSDLR_ref.regval_of (DBGOSDLR_ref.read_from s)) else
+  if reg_name = "DBGOSLSR" then SOME (DBGOSLSR_ref.regval_of (DBGOSLSR_ref.read_from s)) else
+  if reg_name = "DBGPRCR" then SOME (DBGPRCR_ref.regval_of (DBGPRCR_ref.read_from s)) else
+  if reg_name = "DBGPRCR_EL1" then SOME (DBGPRCR_EL1_ref.regval_of (DBGPRCR_EL1_ref.read_from s)) else
+  if reg_name = "DBGWCR_EL1" then SOME (DBGWCR_EL1_ref.regval_of (DBGWCR_EL1_ref.read_from s)) else
+  if reg_name = "DBGWVR_EL1" then SOME (DBGWVR_EL1_ref.regval_of (DBGWVR_EL1_ref.read_from s)) else
+  if reg_name = "DLR" then SOME (DLR_ref.regval_of (DLR_ref.read_from s)) else
+  if reg_name = "DLR_EL0" then SOME (DLR_EL0_ref.regval_of (DLR_EL0_ref.read_from s)) else
+  if reg_name = "DSPSR" then SOME (DSPSR_ref.regval_of (DSPSR_ref.read_from s)) else
+  if reg_name = "DSPSR_EL0" then SOME (DSPSR_EL0_ref.regval_of (DSPSR_EL0_ref.read_from s)) else
+  if reg_name = "EDSCR" then SOME (EDSCR_ref.regval_of (EDSCR_ref.read_from s)) else
+  if reg_name = "ELR_EL1" then SOME (ELR_EL1_ref.regval_of (ELR_EL1_ref.read_from s)) else
+  if reg_name = "ELR_EL2" then SOME (ELR_EL2_ref.regval_of (ELR_EL2_ref.read_from s)) else
+  if reg_name = "ELR_EL3" then SOME (ELR_EL3_ref.regval_of (ELR_EL3_ref.read_from s)) else
+  if reg_name = "ELR_hyp" then SOME (ELR_hyp_ref.regval_of (ELR_hyp_ref.read_from s)) else
+  if reg_name = "ESR_EL1" then SOME (ESR_EL1_ref.regval_of (ESR_EL1_ref.read_from s)) else
+  if reg_name = "ESR_EL2" then SOME (ESR_EL2_ref.regval_of (ESR_EL2_ref.read_from s)) else
+  if reg_name = "ESR_EL3" then SOME (ESR_EL3_ref.regval_of (ESR_EL3_ref.read_from s)) else
+  if reg_name = "EventRegister" then SOME (EventRegister_ref.regval_of (EventRegister_ref.read_from s)) else
+  if reg_name = "FAR_EL1" then SOME (FAR_EL1_ref.regval_of (FAR_EL1_ref.read_from s)) else
+  if reg_name = "FAR_EL2" then SOME (FAR_EL2_ref.regval_of (FAR_EL2_ref.read_from s)) else
+  if reg_name = "FAR_EL3" then SOME (FAR_EL3_ref.regval_of (FAR_EL3_ref.read_from s)) else
+  if reg_name = "FPCR" then SOME (FPCR_ref.regval_of (FPCR_ref.read_from s)) else
+  if reg_name = "FPEXC" then SOME (FPEXC_ref.regval_of (FPEXC_ref.read_from s)) else
+  if reg_name = "FPSCR" then SOME (FPSCR_ref.regval_of (FPSCR_ref.read_from s)) else
+  if reg_name = "FPSR" then SOME (FPSR_ref.regval_of (FPSR_ref.read_from s)) else
+  if reg_name = "HCR" then SOME (HCR_ref.regval_of (HCR_ref.read_from s)) else
+  if reg_name = "HCR2" then SOME (HCR2_ref.regval_of (HCR2_ref.read_from s)) else
+  if reg_name = "HCR_EL2" then SOME (HCR_EL2_ref.regval_of (HCR_EL2_ref.read_from s)) else
+  if reg_name = "HDCR" then SOME (HDCR_ref.regval_of (HDCR_ref.read_from s)) else
+  if reg_name = "HDFAR" then SOME (HDFAR_ref.regval_of (HDFAR_ref.read_from s)) else
+  if reg_name = "HIFAR" then SOME (HIFAR_ref.regval_of (HIFAR_ref.read_from s)) else
+  if reg_name = "HPFAR" then SOME (HPFAR_ref.regval_of (HPFAR_ref.read_from s)) else
+  if reg_name = "HPFAR_EL2" then SOME (HPFAR_EL2_ref.regval_of (HPFAR_EL2_ref.read_from s)) else
+  if reg_name = "HSCTLR" then SOME (HSCTLR_ref.regval_of (HSCTLR_ref.read_from s)) else
+  if reg_name = "HSR" then SOME (HSR_ref.regval_of (HSR_ref.read_from s)) else
+  if reg_name = "HVBAR" then SOME (HVBAR_ref.regval_of (HVBAR_ref.read_from s)) else
+  if reg_name = "ID_AA64DFR0_EL1" then SOME (ID_AA64DFR0_EL1_ref.regval_of (ID_AA64DFR0_EL1_ref.read_from s)) else
+  if reg_name = "LR_mon" then SOME (LR_mon_ref.regval_of (LR_mon_ref.read_from s)) else
+  if reg_name = "MAIR_EL1" then SOME (MAIR_EL1_ref.regval_of (MAIR_EL1_ref.read_from s)) else
+  if reg_name = "MAIR_EL2" then SOME (MAIR_EL2_ref.regval_of (MAIR_EL2_ref.read_from s)) else
+  if reg_name = "MAIR_EL3" then SOME (MAIR_EL3_ref.regval_of (MAIR_EL3_ref.read_from s)) else
+  if reg_name = "MDCR_EL2" then SOME (MDCR_EL2_ref.regval_of (MDCR_EL2_ref.read_from s)) else
+  if reg_name = "MDCR_EL3" then SOME (MDCR_EL3_ref.regval_of (MDCR_EL3_ref.read_from s)) else
+  if reg_name = "MDSCR_EL1" then SOME (MDSCR_EL1_ref.regval_of (MDSCR_EL1_ref.read_from s)) else
+  if reg_name = "OSDLR_EL1" then SOME (OSDLR_EL1_ref.regval_of (OSDLR_EL1_ref.read_from s)) else
+  if reg_name = "OSLSR_EL1" then SOME (OSLSR_EL1_ref.regval_of (OSLSR_EL1_ref.read_from s)) else
+  if reg_name = "PSTATE" then SOME (PSTATE_ref.regval_of (PSTATE_ref.read_from s)) else
+  if reg_name = "RC" then SOME (RC_ref.regval_of (RC_ref.read_from s)) else
+  if reg_name = "RVBAR_EL1" then SOME (RVBAR_EL1_ref.regval_of (RVBAR_EL1_ref.read_from s)) else
+  if reg_name = "RVBAR_EL2" then SOME (RVBAR_EL2_ref.regval_of (RVBAR_EL2_ref.read_from s)) else
+  if reg_name = "RVBAR_EL3" then SOME (RVBAR_EL3_ref.regval_of (RVBAR_EL3_ref.read_from s)) else
+  if reg_name = "SCR" then SOME (SCR_ref.regval_of (SCR_ref.read_from s)) else
+  if reg_name = "SCR_EL3" then SOME (SCR_EL3_ref.regval_of (SCR_EL3_ref.read_from s)) else
+  if reg_name = "SCTLR" then SOME (SCTLR_ref.regval_of (SCTLR_ref.read_from s)) else
+  if reg_name = "SCTLR_EL1" then SOME (SCTLR_EL1_ref.regval_of (SCTLR_EL1_ref.read_from s)) else
+  if reg_name = "SCTLR_EL2" then SOME (SCTLR_EL2_ref.regval_of (SCTLR_EL2_ref.read_from s)) else
+  if reg_name = "SCTLR_EL3" then SOME (SCTLR_EL3_ref.regval_of (SCTLR_EL3_ref.read_from s)) else
+  if reg_name = "SDCR" then SOME (SDCR_ref.regval_of (SDCR_ref.read_from s)) else
+  if reg_name = "SDER" then SOME (SDER_ref.regval_of (SDER_ref.read_from s)) else
+  if reg_name = "SPIDEN" then SOME (SPIDEN_ref.regval_of (SPIDEN_ref.read_from s)) else
+  if reg_name = "SPSR_EL1" then SOME (SPSR_EL1_ref.regval_of (SPSR_EL1_ref.read_from s)) else
+  if reg_name = "SPSR_EL2" then SOME (SPSR_EL2_ref.regval_of (SPSR_EL2_ref.read_from s)) else
+  if reg_name = "SPSR_EL3" then SOME (SPSR_EL3_ref.regval_of (SPSR_EL3_ref.read_from s)) else
+  if reg_name = "SPSR_abt" then SOME (SPSR_abt_ref.regval_of (SPSR_abt_ref.read_from s)) else
+  if reg_name = "SPSR_fiq" then SOME (SPSR_fiq_ref.regval_of (SPSR_fiq_ref.read_from s)) else
+  if reg_name = "SPSR_hyp" then SOME (SPSR_hyp_ref.regval_of (SPSR_hyp_ref.read_from s)) else
+  if reg_name = "SPSR_irq" then SOME (SPSR_irq_ref.regval_of (SPSR_irq_ref.read_from s)) else
+  if reg_name = "SPSR_mon" then SOME (SPSR_mon_ref.regval_of (SPSR_mon_ref.read_from s)) else
+  if reg_name = "SPSR_svc" then SOME (SPSR_svc_ref.regval_of (SPSR_svc_ref.read_from s)) else
+  if reg_name = "SPSR_und" then SOME (SPSR_und_ref.regval_of (SPSR_und_ref.read_from s)) else
+  if reg_name = "SP_EL0" then SOME (SP_EL0_ref.regval_of (SP_EL0_ref.read_from s)) else
+  if reg_name = "SP_EL1" then SOME (SP_EL1_ref.regval_of (SP_EL1_ref.read_from s)) else
+  if reg_name = "SP_EL2" then SOME (SP_EL2_ref.regval_of (SP_EL2_ref.read_from s)) else
+  if reg_name = "SP_EL3" then SOME (SP_EL3_ref.regval_of (SP_EL3_ref.read_from s)) else
+  if reg_name = "SP_mon" then SOME (SP_mon_ref.regval_of (SP_mon_ref.read_from s)) else
+  if reg_name = "TCR_EL1" then SOME (TCR_EL1_ref.regval_of (TCR_EL1_ref.read_from s)) else
+  if reg_name = "TCR_EL2" then SOME (TCR_EL2_ref.regval_of (TCR_EL2_ref.read_from s)) else
+  if reg_name = "TCR_EL3" then SOME (TCR_EL3_ref.regval_of (TCR_EL3_ref.read_from s)) else
+  if reg_name = "TTBCR" then SOME (TTBCR_ref.regval_of (TTBCR_ref.read_from s)) else
+  if reg_name = "TTBR0_EL1" then SOME (TTBR0_EL1_ref.regval_of (TTBR0_EL1_ref.read_from s)) else
+  if reg_name = "TTBR0_EL2" then SOME (TTBR0_EL2_ref.regval_of (TTBR0_EL2_ref.read_from s)) else
+  if reg_name = "TTBR0_EL3" then SOME (TTBR0_EL3_ref.regval_of (TTBR0_EL3_ref.read_from s)) else
+  if reg_name = "TTBR1_EL1" then SOME (TTBR1_EL1_ref.regval_of (TTBR1_EL1_ref.read_from s)) else
+  if reg_name = "TTBR1_EL2" then SOME (TTBR1_EL2_ref.regval_of (TTBR1_EL2_ref.read_from s)) else
+  if reg_name = "VBAR" then SOME (VBAR_ref.regval_of (VBAR_ref.read_from s)) else
+  if reg_name = "VBAR_EL1" then SOME (VBAR_EL1_ref.regval_of (VBAR_EL1_ref.read_from s)) else
+  if reg_name = "VBAR_EL2" then SOME (VBAR_EL2_ref.regval_of (VBAR_EL2_ref.read_from s)) else
+  if reg_name = "VBAR_EL3" then SOME (VBAR_EL3_ref.regval_of (VBAR_EL3_ref.read_from s)) else
+  if reg_name = "VDFSR" then SOME (VDFSR_ref.regval_of (VDFSR_ref.read_from s)) else
+  if reg_name = "VSESR_EL2" then SOME (VSESR_EL2_ref.regval_of (VSESR_EL2_ref.read_from s)) else
+  if reg_name = "VTCR_EL2" then SOME (VTCR_EL2_ref.regval_of (VTCR_EL2_ref.read_from s)) else
+  if reg_name = "VTTBR_EL2" then SOME (VTTBR_EL2_ref.regval_of (VTTBR_EL2_ref.read_from s)) else
+  if reg_name = "_PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
+  if reg_name = "_R" then SOME (R_ref.regval_of (R_ref.read_from s)) else
+  if reg_name = "_V" then SOME (V_ref.regval_of (V_ref.read_from s)) else
+  if reg_name = "__BranchTaken" then SOME (BranchTaken_ref.regval_of (BranchTaken_ref.read_from s)) else
+  if reg_name = "__ExclusiveLocal" then SOME (ExclusiveLocal_ref.regval_of (ExclusiveLocal_ref.read_from s)) else
+  if reg_name = "__Memory" then SOME (Memory_ref.regval_of (Memory_ref.read_from s)) else
+  if reg_name = "__PendingInterrupt" then SOME (PendingInterrupt_ref.regval_of (PendingInterrupt_ref.read_from s)) else
+  if reg_name = "__PendingPhysicalSError" then SOME (PendingPhysicalSError_ref.regval_of (PendingPhysicalSError_ref.read_from s)) else
+  if reg_name = "__Sleeping" then SOME (Sleeping_ref.regval_of (Sleeping_ref.read_from s)) else
+  if reg_name = "__ThisInstr" then SOME (ThisInstr_ref.regval_of (ThisInstr_ref.read_from s)) else
+  if reg_name = "__ThisInstrEnc" then SOME (ThisInstrEnc_ref.regval_of (ThisInstrEnc_ref.read_from s)) else
+  if reg_name = "__currentCond" then SOME (currentCond_ref.regval_of (currentCond_ref.read_from s)) else
+  if reg_name = "__unconditional" then SOME (unconditional_ref.regval_of (unconditional_ref.read_from s)) else
+  NONE))`;
+
+
+(*val set_regval : string -> register_value -> regstate -> maybe regstate*)
+val _ = Define `
+ ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=
+   (if reg_name = "APDAKeyHi_EL1" then OPTION_MAP (\ v .  APDAKeyHi_EL1_ref.write_to v s) (APDAKeyHi_EL1_ref.of_regval v) else
+  if reg_name = "APDAKeyLo_EL1" then OPTION_MAP (\ v .  APDAKeyLo_EL1_ref.write_to v s) (APDAKeyLo_EL1_ref.of_regval v) else
+  if reg_name = "APDBKeyHi_EL1" then OPTION_MAP (\ v .  APDBKeyHi_EL1_ref.write_to v s) (APDBKeyHi_EL1_ref.of_regval v) else
+  if reg_name = "APDBKeyLo_EL1" then OPTION_MAP (\ v .  APDBKeyLo_EL1_ref.write_to v s) (APDBKeyLo_EL1_ref.of_regval v) else
+  if reg_name = "APGAKeyHi_EL1" then OPTION_MAP (\ v .  APGAKeyHi_EL1_ref.write_to v s) (APGAKeyHi_EL1_ref.of_regval v) else
+  if reg_name = "APGAKeyLo_EL1" then OPTION_MAP (\ v .  APGAKeyLo_EL1_ref.write_to v s) (APGAKeyLo_EL1_ref.of_regval v) else
+  if reg_name = "APIAKeyHi_EL1" then OPTION_MAP (\ v .  APIAKeyHi_EL1_ref.write_to v s) (APIAKeyHi_EL1_ref.of_regval v) else
+  if reg_name = "APIAKeyLo_EL1" then OPTION_MAP (\ v .  APIAKeyLo_EL1_ref.write_to v s) (APIAKeyLo_EL1_ref.of_regval v) else
+  if reg_name = "APIBKeyHi_EL1" then OPTION_MAP (\ v .  APIBKeyHi_EL1_ref.write_to v s) (APIBKeyHi_EL1_ref.of_regval v) else
+  if reg_name = "APIBKeyLo_EL1" then OPTION_MAP (\ v .  APIBKeyLo_EL1_ref.write_to v s) (APIBKeyLo_EL1_ref.of_regval v) else
+  if reg_name = "CONTEXTIDR_EL1" then OPTION_MAP (\ v .  CONTEXTIDR_EL1_ref.write_to v s) (CONTEXTIDR_EL1_ref.of_regval v) else
+  if reg_name = "CONTEXTIDR_EL2" then OPTION_MAP (\ v .  CONTEXTIDR_EL2_ref.write_to v s) (CONTEXTIDR_EL2_ref.of_regval v) else
+  if reg_name = "CPACR_EL1" then OPTION_MAP (\ v .  CPACR_EL1_ref.write_to v s) (CPACR_EL1_ref.of_regval v) else
+  if reg_name = "CPTR_EL2" then OPTION_MAP (\ v .  CPTR_EL2_ref.write_to v s) (CPTR_EL2_ref.of_regval v) else
+  if reg_name = "CPTR_EL3" then OPTION_MAP (\ v .  CPTR_EL3_ref.write_to v s) (CPTR_EL3_ref.of_regval v) else
+  if reg_name = "DBGBCR_EL1" then OPTION_MAP (\ v .  DBGBCR_EL1_ref.write_to v s) (DBGBCR_EL1_ref.of_regval v) else
+  if reg_name = "DBGBVR_EL1" then OPTION_MAP (\ v .  DBGBVR_EL1_ref.write_to v s) (DBGBVR_EL1_ref.of_regval v) else
+  if reg_name = "DBGEN" then OPTION_MAP (\ v .  DBGEN_ref.write_to v s) (DBGEN_ref.of_regval v) else
+  if reg_name = "DBGOSDLR" then OPTION_MAP (\ v .  DBGOSDLR_ref.write_to v s) (DBGOSDLR_ref.of_regval v) else
+  if reg_name = "DBGOSLSR" then OPTION_MAP (\ v .  DBGOSLSR_ref.write_to v s) (DBGOSLSR_ref.of_regval v) else
+  if reg_name = "DBGPRCR" then OPTION_MAP (\ v .  DBGPRCR_ref.write_to v s) (DBGPRCR_ref.of_regval v) else
+  if reg_name = "DBGPRCR_EL1" then OPTION_MAP (\ v .  DBGPRCR_EL1_ref.write_to v s) (DBGPRCR_EL1_ref.of_regval v) else
+  if reg_name = "DBGWCR_EL1" then OPTION_MAP (\ v .  DBGWCR_EL1_ref.write_to v s) (DBGWCR_EL1_ref.of_regval v) else
+  if reg_name = "DBGWVR_EL1" then OPTION_MAP (\ v .  DBGWVR_EL1_ref.write_to v s) (DBGWVR_EL1_ref.of_regval v) else
+  if reg_name = "DLR" then OPTION_MAP (\ v .  DLR_ref.write_to v s) (DLR_ref.of_regval v) else
+  if reg_name = "DLR_EL0" then OPTION_MAP (\ v .  DLR_EL0_ref.write_to v s) (DLR_EL0_ref.of_regval v) else
+  if reg_name = "DSPSR" then OPTION_MAP (\ v .  DSPSR_ref.write_to v s) (DSPSR_ref.of_regval v) else
+  if reg_name = "DSPSR_EL0" then OPTION_MAP (\ v .  DSPSR_EL0_ref.write_to v s) (DSPSR_EL0_ref.of_regval v) else
+  if reg_name = "EDSCR" then OPTION_MAP (\ v .  EDSCR_ref.write_to v s) (EDSCR_ref.of_regval v) else
+  if reg_name = "ELR_EL1" then OPTION_MAP (\ v .  ELR_EL1_ref.write_to v s) (ELR_EL1_ref.of_regval v) else
+  if reg_name = "ELR_EL2" then OPTION_MAP (\ v .  ELR_EL2_ref.write_to v s) (ELR_EL2_ref.of_regval v) else
+  if reg_name = "ELR_EL3" then OPTION_MAP (\ v .  ELR_EL3_ref.write_to v s) (ELR_EL3_ref.of_regval v) else
+  if reg_name = "ELR_hyp" then OPTION_MAP (\ v .  ELR_hyp_ref.write_to v s) (ELR_hyp_ref.of_regval v) else
+  if reg_name = "ESR_EL1" then OPTION_MAP (\ v .  ESR_EL1_ref.write_to v s) (ESR_EL1_ref.of_regval v) else
+  if reg_name = "ESR_EL2" then OPTION_MAP (\ v .  ESR_EL2_ref.write_to v s) (ESR_EL2_ref.of_regval v) else
+  if reg_name = "ESR_EL3" then OPTION_MAP (\ v .  ESR_EL3_ref.write_to v s) (ESR_EL3_ref.of_regval v) else
+  if reg_name = "EventRegister" then OPTION_MAP (\ v .  EventRegister_ref.write_to v s) (EventRegister_ref.of_regval v) else
+  if reg_name = "FAR_EL1" then OPTION_MAP (\ v .  FAR_EL1_ref.write_to v s) (FAR_EL1_ref.of_regval v) else
+  if reg_name = "FAR_EL2" then OPTION_MAP (\ v .  FAR_EL2_ref.write_to v s) (FAR_EL2_ref.of_regval v) else
+  if reg_name = "FAR_EL3" then OPTION_MAP (\ v .  FAR_EL3_ref.write_to v s) (FAR_EL3_ref.of_regval v) else
+  if reg_name = "FPCR" then OPTION_MAP (\ v .  FPCR_ref.write_to v s) (FPCR_ref.of_regval v) else
+  if reg_name = "FPEXC" then OPTION_MAP (\ v .  FPEXC_ref.write_to v s) (FPEXC_ref.of_regval v) else
+  if reg_name = "FPSCR" then OPTION_MAP (\ v .  FPSCR_ref.write_to v s) (FPSCR_ref.of_regval v) else
+  if reg_name = "FPSR" then OPTION_MAP (\ v .  FPSR_ref.write_to v s) (FPSR_ref.of_regval v) else
+  if reg_name = "HCR" then OPTION_MAP (\ v .  HCR_ref.write_to v s) (HCR_ref.of_regval v) else
+  if reg_name = "HCR2" then OPTION_MAP (\ v .  HCR2_ref.write_to v s) (HCR2_ref.of_regval v) else
+  if reg_name = "HCR_EL2" then OPTION_MAP (\ v .  HCR_EL2_ref.write_to v s) (HCR_EL2_ref.of_regval v) else
+  if reg_name = "HDCR" then OPTION_MAP (\ v .  HDCR_ref.write_to v s) (HDCR_ref.of_regval v) else
+  if reg_name = "HDFAR" then OPTION_MAP (\ v .  HDFAR_ref.write_to v s) (HDFAR_ref.of_regval v) else
+  if reg_name = "HIFAR" then OPTION_MAP (\ v .  HIFAR_ref.write_to v s) (HIFAR_ref.of_regval v) else
+  if reg_name = "HPFAR" then OPTION_MAP (\ v .  HPFAR_ref.write_to v s) (HPFAR_ref.of_regval v) else
+  if reg_name = "HPFAR_EL2" then OPTION_MAP (\ v .  HPFAR_EL2_ref.write_to v s) (HPFAR_EL2_ref.of_regval v) else
+  if reg_name = "HSCTLR" then OPTION_MAP (\ v .  HSCTLR_ref.write_to v s) (HSCTLR_ref.of_regval v) else
+  if reg_name = "HSR" then OPTION_MAP (\ v .  HSR_ref.write_to v s) (HSR_ref.of_regval v) else
+  if reg_name = "HVBAR" then OPTION_MAP (\ v .  HVBAR_ref.write_to v s) (HVBAR_ref.of_regval v) else
+  if reg_name = "ID_AA64DFR0_EL1" then OPTION_MAP (\ v .  ID_AA64DFR0_EL1_ref.write_to v s) (ID_AA64DFR0_EL1_ref.of_regval v) else
+  if reg_name = "LR_mon" then OPTION_MAP (\ v .  LR_mon_ref.write_to v s) (LR_mon_ref.of_regval v) else
+  if reg_name = "MAIR_EL1" then OPTION_MAP (\ v .  MAIR_EL1_ref.write_to v s) (MAIR_EL1_ref.of_regval v) else
+  if reg_name = "MAIR_EL2" then OPTION_MAP (\ v .  MAIR_EL2_ref.write_to v s) (MAIR_EL2_ref.of_regval v) else
+  if reg_name = "MAIR_EL3" then OPTION_MAP (\ v .  MAIR_EL3_ref.write_to v s) (MAIR_EL3_ref.of_regval v) else
+  if reg_name = "MDCR_EL2" then OPTION_MAP (\ v .  MDCR_EL2_ref.write_to v s) (MDCR_EL2_ref.of_regval v) else
+  if reg_name = "MDCR_EL3" then OPTION_MAP (\ v .  MDCR_EL3_ref.write_to v s) (MDCR_EL3_ref.of_regval v) else
+  if reg_name = "MDSCR_EL1" then OPTION_MAP (\ v .  MDSCR_EL1_ref.write_to v s) (MDSCR_EL1_ref.of_regval v) else
+  if reg_name = "OSDLR_EL1" then OPTION_MAP (\ v .  OSDLR_EL1_ref.write_to v s) (OSDLR_EL1_ref.of_regval v) else
+  if reg_name = "OSLSR_EL1" then OPTION_MAP (\ v .  OSLSR_EL1_ref.write_to v s) (OSLSR_EL1_ref.of_regval v) else
+  if reg_name = "PSTATE" then OPTION_MAP (\ v .  PSTATE_ref.write_to v s) (PSTATE_ref.of_regval v) else
+  if reg_name = "RC" then OPTION_MAP (\ v .  RC_ref.write_to v s) (RC_ref.of_regval v) else
+  if reg_name = "RVBAR_EL1" then OPTION_MAP (\ v .  RVBAR_EL1_ref.write_to v s) (RVBAR_EL1_ref.of_regval v) else
+  if reg_name = "RVBAR_EL2" then OPTION_MAP (\ v .  RVBAR_EL2_ref.write_to v s) (RVBAR_EL2_ref.of_regval v) else
+  if reg_name = "RVBAR_EL3" then OPTION_MAP (\ v .  RVBAR_EL3_ref.write_to v s) (RVBAR_EL3_ref.of_regval v) else
+  if reg_name = "SCR" then OPTION_MAP (\ v .  SCR_ref.write_to v s) (SCR_ref.of_regval v) else
+  if reg_name = "SCR_EL3" then OPTION_MAP (\ v .  SCR_EL3_ref.write_to v s) (SCR_EL3_ref.of_regval v) else
+  if reg_name = "SCTLR" then OPTION_MAP (\ v .  SCTLR_ref.write_to v s) (SCTLR_ref.of_regval v) else
+  if reg_name = "SCTLR_EL1" then OPTION_MAP (\ v .  SCTLR_EL1_ref.write_to v s) (SCTLR_EL1_ref.of_regval v) else
+  if reg_name = "SCTLR_EL2" then OPTION_MAP (\ v .  SCTLR_EL2_ref.write_to v s) (SCTLR_EL2_ref.of_regval v) else
+  if reg_name = "SCTLR_EL3" then OPTION_MAP (\ v .  SCTLR_EL3_ref.write_to v s) (SCTLR_EL3_ref.of_regval v) else
+  if reg_name = "SDCR" then OPTION_MAP (\ v .  SDCR_ref.write_to v s) (SDCR_ref.of_regval v) else
+  if reg_name = "SDER" then OPTION_MAP (\ v .  SDER_ref.write_to v s) (SDER_ref.of_regval v) else
+  if reg_name = "SPIDEN" then OPTION_MAP (\ v .  SPIDEN_ref.write_to v s) (SPIDEN_ref.of_regval v) else
+  if reg_name = "SPSR_EL1" then OPTION_MAP (\ v .  SPSR_EL1_ref.write_to v s) (SPSR_EL1_ref.of_regval v) else
+  if reg_name = "SPSR_EL2" then OPTION_MAP (\ v .  SPSR_EL2_ref.write_to v s) (SPSR_EL2_ref.of_regval v) else
+  if reg_name = "SPSR_EL3" then OPTION_MAP (\ v .  SPSR_EL3_ref.write_to v s) (SPSR_EL3_ref.of_regval v) else
+  if reg_name = "SPSR_abt" then OPTION_MAP (\ v .  SPSR_abt_ref.write_to v s) (SPSR_abt_ref.of_regval v) else
+  if reg_name = "SPSR_fiq" then OPTION_MAP (\ v .  SPSR_fiq_ref.write_to v s) (SPSR_fiq_ref.of_regval v) else
+  if reg_name = "SPSR_hyp" then OPTION_MAP (\ v .  SPSR_hyp_ref.write_to v s) (SPSR_hyp_ref.of_regval v) else
+  if reg_name = "SPSR_irq" then OPTION_MAP (\ v .  SPSR_irq_ref.write_to v s) (SPSR_irq_ref.of_regval v) else
+  if reg_name = "SPSR_mon" then OPTION_MAP (\ v .  SPSR_mon_ref.write_to v s) (SPSR_mon_ref.of_regval v) else
+  if reg_name = "SPSR_svc" then OPTION_MAP (\ v .  SPSR_svc_ref.write_to v s) (SPSR_svc_ref.of_regval v) else
+  if reg_name = "SPSR_und" then OPTION_MAP (\ v .  SPSR_und_ref.write_to v s) (SPSR_und_ref.of_regval v) else
+  if reg_name = "SP_EL0" then OPTION_MAP (\ v .  SP_EL0_ref.write_to v s) (SP_EL0_ref.of_regval v) else
+  if reg_name = "SP_EL1" then OPTION_MAP (\ v .  SP_EL1_ref.write_to v s) (SP_EL1_ref.of_regval v) else
+  if reg_name = "SP_EL2" then OPTION_MAP (\ v .  SP_EL2_ref.write_to v s) (SP_EL2_ref.of_regval v) else
+  if reg_name = "SP_EL3" then OPTION_MAP (\ v .  SP_EL3_ref.write_to v s) (SP_EL3_ref.of_regval v) else
+  if reg_name = "SP_mon" then OPTION_MAP (\ v .  SP_mon_ref.write_to v s) (SP_mon_ref.of_regval v) else
+  if reg_name = "TCR_EL1" then OPTION_MAP (\ v .  TCR_EL1_ref.write_to v s) (TCR_EL1_ref.of_regval v) else
+  if reg_name = "TCR_EL2" then OPTION_MAP (\ v .  TCR_EL2_ref.write_to v s) (TCR_EL2_ref.of_regval v) else
+  if reg_name = "TCR_EL3" then OPTION_MAP (\ v .  TCR_EL3_ref.write_to v s) (TCR_EL3_ref.of_regval v) else
+  if reg_name = "TTBCR" then OPTION_MAP (\ v .  TTBCR_ref.write_to v s) (TTBCR_ref.of_regval v) else
+  if reg_name = "TTBR0_EL1" then OPTION_MAP (\ v .  TTBR0_EL1_ref.write_to v s) (TTBR0_EL1_ref.of_regval v) else
+  if reg_name = "TTBR0_EL2" then OPTION_MAP (\ v .  TTBR0_EL2_ref.write_to v s) (TTBR0_EL2_ref.of_regval v) else
+  if reg_name = "TTBR0_EL3" then OPTION_MAP (\ v .  TTBR0_EL3_ref.write_to v s) (TTBR0_EL3_ref.of_regval v) else
+  if reg_name = "TTBR1_EL1" then OPTION_MAP (\ v .  TTBR1_EL1_ref.write_to v s) (TTBR1_EL1_ref.of_regval v) else
+  if reg_name = "TTBR1_EL2" then OPTION_MAP (\ v .  TTBR1_EL2_ref.write_to v s) (TTBR1_EL2_ref.of_regval v) else
+  if reg_name = "VBAR" then OPTION_MAP (\ v .  VBAR_ref.write_to v s) (VBAR_ref.of_regval v) else
+  if reg_name = "VBAR_EL1" then OPTION_MAP (\ v .  VBAR_EL1_ref.write_to v s) (VBAR_EL1_ref.of_regval v) else
+  if reg_name = "VBAR_EL2" then OPTION_MAP (\ v .  VBAR_EL2_ref.write_to v s) (VBAR_EL2_ref.of_regval v) else
+  if reg_name = "VBAR_EL3" then OPTION_MAP (\ v .  VBAR_EL3_ref.write_to v s) (VBAR_EL3_ref.of_regval v) else
+  if reg_name = "VDFSR" then OPTION_MAP (\ v .  VDFSR_ref.write_to v s) (VDFSR_ref.of_regval v) else
+  if reg_name = "VSESR_EL2" then OPTION_MAP (\ v .  VSESR_EL2_ref.write_to v s) (VSESR_EL2_ref.of_regval v) else
+  if reg_name = "VTCR_EL2" then OPTION_MAP (\ v .  VTCR_EL2_ref.write_to v s) (VTCR_EL2_ref.of_regval v) else
+  if reg_name = "VTTBR_EL2" then OPTION_MAP (\ v .  VTTBR_EL2_ref.write_to v s) (VTTBR_EL2_ref.of_regval v) else
+  if reg_name = "_PC" then OPTION_MAP (\ v .  PC_ref.write_to v s) (PC_ref.of_regval v) else
+  if reg_name = "_R" then OPTION_MAP (\ v .  R_ref.write_to v s) (R_ref.of_regval v) else
+  if reg_name = "_V" then OPTION_MAP (\ v .  V_ref.write_to v s) (V_ref.of_regval v) else
+  if reg_name = "__BranchTaken" then OPTION_MAP (\ v .  BranchTaken_ref.write_to v s) (BranchTaken_ref.of_regval v) else
+  if reg_name = "__ExclusiveLocal" then OPTION_MAP (\ v .  ExclusiveLocal_ref.write_to v s) (ExclusiveLocal_ref.of_regval v) else
+  if reg_name = "__Memory" then OPTION_MAP (\ v .  Memory_ref.write_to v s) (Memory_ref.of_regval v) else
+  if reg_name = "__PendingInterrupt" then OPTION_MAP (\ v .  PendingInterrupt_ref.write_to v s) (PendingInterrupt_ref.of_regval v) else
+  if reg_name = "__PendingPhysicalSError" then OPTION_MAP (\ v .  PendingPhysicalSError_ref.write_to v s) (PendingPhysicalSError_ref.of_regval v) else
+  if reg_name = "__Sleeping" then OPTION_MAP (\ v .  Sleeping_ref.write_to v s) (Sleeping_ref.of_regval v) else
+  if reg_name = "__ThisInstr" then OPTION_MAP (\ v .  ThisInstr_ref.write_to v s) (ThisInstr_ref.of_regval v) else
+  if reg_name = "__ThisInstrEnc" then OPTION_MAP (\ v .  ThisInstrEnc_ref.write_to v s) (ThisInstrEnc_ref.of_regval v) else
+  if reg_name = "__currentCond" then OPTION_MAP (\ v .  currentCond_ref.write_to v s) (currentCond_ref.of_regval v) else
+  if reg_name = "__unconditional" then OPTION_MAP (\ v .  unconditional_ref.write_to v s) (unconditional_ref.of_regval v) else
+  NONE))`;
+
+
+val _ = Define `
+ ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))=  (get_regval, set_regval))`;
+
+
+
+val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``:  (regstate, 'a, 'r, exception)monadR``);
+val _ = type_abbrev((*  'a *) "M" , ``:  (regstate, 'a, exception)monad``);
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/cheri/cheriScript.sml b/snapshots/hol4/sail/cheri/cheriScript.sml
index d3e724c0..5fa55723 100644
--- a/snapshots/hol4/sail/cheri/cheriScript.sml
+++ b/snapshots/hol4/sail/cheri/cheriScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from cheri.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory cheri_typesTheory mips_extrasTheory;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory cheri_typesTheory mips_extrasTheory;
 
 val _ = numLib.prefer_num();
 
@@ -10,11 +10,12 @@ val _ = new_theory "cheri"
 
 (*Generated by Sail from cheri.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 (*open import Cheri_types*)
 (*open import Mips_extras*)
 
@@ -22,33 +23,49 @@ val _ = Define `
  ((cap_size:int)=  ((( 32 : int):ii)))`;
 
 
-(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*)
 
-val _ = Define `
- ((undefined_option:'a ->(regstate)state_monad$sequential_state ->((('a option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) typ_a=  (state_monad$seqS (undefined_unit () ) (internal_pick [NONE;SOME typ_a])))`;
 
 
 
 
 
+(*val neq_bool : bool -> bool -> bool*)
 
+val _ = Define `
+ ((neq_bool:bool -> bool -> bool) x y=  (~ (((x = y)))))`;
 
 
-(*val neq_bool : bool -> bool -> bool*)
+(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*)
 
 val _ = Define `
- ((neq_bool:bool -> bool -> bool) x y=  (~ (((x = y)))))`;
+ ((undefined_option:'a ->(regstate)sail2_state_monad$sequential_state ->((('a option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ_a=  (sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_0 : unit) . 
+   let (u_1 : 'a) = typ_a in
+   sail2_state$internal_pickS [SOME u_1;NONE])))`;
 
 
+(*val is_none : forall 'a. maybe 'a -> bool*)
 
+val _ = Define `
+ ((is_none:'a option -> bool) opt=  ((case opt of   SOME (_) => F | NONE => T )))`;
+
+
+(*val is_some : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_some:'a option -> bool) opt=  ((case opt of   SOME (_) => T | NONE => F )))`;
 
 
+(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*)
 
-(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
+val _ = Define `
+ ((sail_mask:'len itself -> 'v words$word -> 'len words$word) len v=
+    (let len = (size_itself_int len) in
+   if ((len <= ((int_of_num (words$word_len v))))) then (vector_truncate v len  :  'len words$word)
+   else (zero_extend v len  :  'len words$word)))`;
 
 
 
-(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
 
 
 
@@ -56,29 +73,25 @@ val _ = Define `
 
 val _ = Define `
  ((cast_unit_vec0:bitU ->(1)words$word) b=
-    ((case b of   B0 => (vec_of_bits [B0]  :  1 words$word) | B1 => (vec_of_bits [B1]  :  1 words$word) )))`;
-
-
-(*val DecStr : ii -> string*)
+    ((case b of   B0 => (vec_of_bits [B0]  :  1 words$word) | _ => (vec_of_bits [B1]  :  1 words$word) )))`;
 
-(*val HexStr : ii -> string*)
 
 (*val __MIPS_write : forall  'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*)
 
 val _ = Define `
- ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=
-    (write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width
+ ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+    (write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width
      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
        :  64 words$word) addr data))`;
 
 
-(*val __MIPS_read : forall  'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
+(*val __MIPS_read : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
 
 val _ = Define `
- ((MIPS_read:(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=
-    ((read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width
+ ((MIPS_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width
       (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
@@ -91,28 +104,23 @@ val _ = Define `
 (*val undefined_exception : unit -> M exception*)
 
 val _ = Define `
- ((undefined_exception:unit ->(regstate)state_monad$sequential_state ->(((exception),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS (state_monad$seqS
-   (undefined_unit () )
-   (undefined_string () )) (\ (w__0 : string) .  state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (undefined_unit () )
-   (undefined_unit () ))
-   (undefined_unit () ))
-   (internal_pick
-     [ISAException () ;Error_not_implemented w__0;Error_misaligned_access () ;Error_EBREAK () ;Error_internal_error () ]))))`;
+ ((undefined_exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_string () ) (\ (u_0 : string) .  sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_1 : unit) . 
+   sail2_state$internal_pickS
+     [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1]))))`;
 
 
-(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
 
-(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
 
 val _ = Define `
- ((sign_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((sign_extend0 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv  :  'm words$word)))`;
+ ((mips_sign_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((sign_extend v m__tv  :  'm words$word)))`;
 
 
 val _ = Define `
- ((zero_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((zero_extend0 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv  :  'm words$word)))`;
+ ((mips_zero_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((zero_extend v m__tv  :  'm words$word)))`;
 
 
 (*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*)
@@ -127,13 +135,13 @@ val _ = Define `
  ((ones:int -> unit -> 'n words$word) (n__tv : int) () =  ((replicate_bits (vec_of_bits [B1]  :  1 words$word) n__tv  :  'n words$word)))`;
 
 
-(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
-(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
-(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
-(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
 val _ = Define `
  ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y=  (((integer_word$w2i x)) < ((integer_word$w2i y))))`;
@@ -160,7 +168,7 @@ val _ = Define `
 (*val bit_to_bool : bitU -> bool*)
 
 val _ = Define `
- ((bit_to_bool:bitU -> bool) b=  ((case b of   B1 => T | B0 => F )))`;
+ ((bit_to_bool:bitU -> bool) b=  ((case b of   B1 => T | _ => F )))`;
 
 
 (*val bits_to_bool : mword ty1 -> bool*)
@@ -172,12 +180,12 @@ val _ = Define `
 (*
 \function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits.
 *)
-(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*)
+(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*)
 
 val _ = Define `
  ((to_bits:'l itself -> int -> 'l words$word) l n=
     (let l = (size_itself_int l) in
-   (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii)  :  'l words$word)))`;
+   (get_slice_int0 instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii)  :  'l words$word)))`;
 
 
 (*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*)
@@ -190,167 +198,242 @@ val _ = Define `
 (*val undefined_CauseReg : unit -> M CauseReg*)
 
 val _ = Define `
- ((undefined_CauseReg:unit ->(regstate)state_monad$sequential_state ->(((CauseReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_CauseReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((CauseReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
-   internal_pick [Mk_CauseReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+   sail2_state_monad$returnS (<| CauseReg_CauseReg_chunk_0 := w__0 |>))))`;
 
 
-(*val _get_CauseReg : CauseReg -> mword ty32*)
+(*val Mk_CauseReg : mword ty32 -> CauseReg*)
 
 val _ = Define `
- ((get_CauseReg:CauseReg ->(32)words$word) (Mk_CauseReg (v))=  v)`;
+ ((Mk_CauseReg:(32)words$word -> CauseReg) v=
+    (<| CauseReg_CauseReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) |>))`;
 
 
-(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*)
+(*val _get_CauseReg_bits : CauseReg -> mword ty32*)
 
 val _ = Define `
- ((set_CauseReg:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_CauseReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((get_CauseReg_bits:CauseReg ->(32)words$word) v=
+    ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))`;
 
 
-(*val _get_CapCauseReg : CapCauseReg -> mword ty16*)
+(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*)
 
-(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*)
+val _ = Define `
+ ((set_CauseReg_bits:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_bits:CauseReg ->(32)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _update_CapCauseReg_bits : CapCauseReg -> mword ty16 -> CapCauseReg*)
+
+(*val _get_CapCauseReg_bits : CapCauseReg -> mword ty16*)
+
+(*val _set_CapCauseReg_bits : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*)
 
 (*val _get_CauseReg_BD : CauseReg -> mword ty1*)
 
 val _ = Define `
- ((get_CauseReg_BD:CauseReg ->(1)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)))`;
+ ((get_CauseReg_BD:CauseReg ->(1)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . 
-   let r = ((get_CauseReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 31 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_CauseReg r))))`;
+ ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*)
 
 val _ = Define `
- ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x=
-    (Mk_CauseReg ((update_subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) x  :  32 words$word))))`;
+ ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_CauseReg_CE : CauseReg -> mword ty2*)
 
 val _ = Define `
- ((get_CauseReg_CE:CauseReg ->(2)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 29 : int):ii) (( 28 : int):ii)  :  2 words$word)))`;
+ ((get_CauseReg_CE:CauseReg ->(2)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . 
-   let r = ((get_CauseReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 28 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_CauseReg r))))`;
+ ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*)
 
 val _ = Define `
- ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) (Mk_CauseReg (v)) x=
-    (Mk_CauseReg ((update_subrange_vec_dec v (( 29 : int):ii) (( 28 : int):ii) x  :  32 words$word))))`;
+ ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_CauseReg_IV : CauseReg -> mword ty1*)
 
 val _ = Define `
- ((get_CauseReg_IV:CauseReg ->(1)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii)  :  1 words$word)))`;
+ ((get_CauseReg_IV:CauseReg ->(1)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . 
-   let r = ((get_CauseReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 23 : int):ii) (( 23 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_CauseReg r))))`;
+ ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*)
 
 val _ = Define `
- ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x=
-    (Mk_CauseReg ((update_subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) x  :  32 words$word))))`;
+ ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_CauseReg_WP : CauseReg -> mword ty1*)
 
 val _ = Define `
- ((get_CauseReg_WP:CauseReg ->(1)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
+ ((get_CauseReg_WP:CauseReg ->(1)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . 
-   let r = ((get_CauseReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_CauseReg r))))`;
+ ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*)
 
 val _ = Define `
- ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x=
-    (Mk_CauseReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x  :  32 words$word))))`;
+ ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_CauseReg_IP : CauseReg -> mword ty8*)
 
 val _ = Define `
- ((get_CauseReg_IP:CauseReg ->(8)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
+ ((get_CauseReg_IP:CauseReg ->(8)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
 
 
 (*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . 
-   let r = ((get_CauseReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_CauseReg r))))`;
+ ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*)
 
 val _ = Define `
- ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) (Mk_CauseReg (v)) x=
-    (Mk_CauseReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x  :  32 words$word))))`;
+ ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*)
 
 val _ = Define `
- ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)))`;
+ ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) v=
+    ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)))`;
 
 
 (*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . 
-   let r = ((get_CauseReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 2 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_CauseReg r))))`;
+ ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*)
 
 val _ = Define `
- ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) (Mk_CauseReg (v)) x=
-    (Mk_CauseReg ((update_subrange_vec_dec v (( 6 : int):ii) (( 2 : int):ii) x  :  32 words$word))))`;
+ ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*)
@@ -362,448 +445,673 @@ val _ = Define `
 (*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*)
 
 val _ = Define `
- ((undefined_TLBEntryLoReg:unit ->(regstate)state_monad$sequential_state ->(((TLBEntryLoReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_TLBEntryLoReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryLoReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   internal_pick [Mk_TLBEntryLoReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((Mk_TLBEntryLoReg:(64)words$word -> TLBEntryLoReg) v=
+    (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
-(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*)
+(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*)
 
 val _ = Define `
- ((get_TLBEntryLoReg:TLBEntryLoReg ->(64)words$word) (Mk_TLBEntryLoReg (v))=  v)`;
+ ((get_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*)
+(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_TLBEntryLoReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((set_TLBEntryLoReg_bits:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=
-    ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=
-    ((subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 62 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) (Mk_TLBEntryLoReg (v))=
-    ((subrange_vec_dec v (( 29 : int):ii) (( 6 : int):ii)  :  24 words$word)))`;
+ ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii)  :  24 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 6 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 : int):ii) (( 6 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 3 : int):ii)  :  3 words$word)))`;
+ ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii)  :  3 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 3 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 : int):ii) (( 3 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . 
-   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+ ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
 val _ = Define `
- ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=
-    (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*)
 
 val _ = Define `
- ((undefined_TLBEntryHiReg:unit ->(regstate)state_monad$sequential_state ->(((TLBEntryHiReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_TLBEntryHiReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryHiReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   internal_pick [Mk_TLBEntryHiReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*)
+
+val _ = Define `
+ ((Mk_TLBEntryHiReg:(64)words$word -> TLBEntryHiReg) v=
+    (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*)
+(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_TLBEntryHiReg:TLBEntryHiReg ->(64)words$word) (Mk_TLBEntryHiReg (v))=  v)`;
+ ((set_TLBEntryHiReg_bits:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*)
+(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*)
 
 val _ = Define `
- ((set_TLBEntryHiReg:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_TLBEntryHiReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*)
 
 val _ = Define `
- ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) (Mk_TLBEntryHiReg (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))`;
+ ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . 
-   let r = ((get_TLBEntryHiReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 62 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`;
+ ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*)
 
 val _ = Define `
- ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x=
-    (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*)
 
 val _ = Define `
- ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) (Mk_TLBEntryHiReg (v))=
-    ((subrange_vec_dec v (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word)))`;
+ ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word)))`;
 
 
 (*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . 
-   let r = ((get_TLBEntryHiReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 39 : int):ii) (( 13 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`;
+ ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*)
 
 val _ = Define `
- ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x=
-    (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 : int):ii) (( 13 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*)
 
 val _ = Define `
- ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) (Mk_TLBEntryHiReg (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+ ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
 
 
 (*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . 
-   let r = ((get_TLBEntryHiReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`;
+ ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*)
 
 val _ = Define `
- ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x=
-    (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val undefined_ContextReg : unit -> M ContextReg*)
 
 val _ = Define `
- ((undefined_ContextReg:unit ->(regstate)state_monad$sequential_state ->(((ContextReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_ContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((ContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   internal_pick [Mk_ContextReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| ContextReg_ContextReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_ContextReg : mword ty64 -> ContextReg*)
+
+val _ = Define `
+ ((Mk_ContextReg:(64)words$word -> ContextReg) v=
+    (<| ContextReg_ContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
-(*val _get_ContextReg : ContextReg -> mword ty64*)
+(*val _get_ContextReg_bits : ContextReg -> mword ty64*)
 
 val _ = Define `
- ((get_ContextReg:ContextReg ->(64)words$word) (Mk_ContextReg (v))=  v)`;
+ ((get_ContextReg_bits:ContextReg ->(64)words$word) v=
+    ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*)
+(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((set_ContextReg:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_ContextReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((set_ContextReg_bits:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*)
+
+val _ = Define `
+ ((update_ContextReg_bits:ContextReg ->(64)words$word -> ContextReg) v x=
+    ((v with<|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*)
 
 val _ = Define `
- ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) (Mk_ContextReg (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 23 : int):ii)  :  41 words$word)))`;
+ ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) v=
+    ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii)  :  41 words$word)))`;
 
 
 (*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*)
 
 val _ = Define `
- ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : ContextReg) . 
-   let r = ((get_ContextReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 23 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_ContextReg r))))`;
+ ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii)
+             ((subrange_vec_dec v (( 40 : int):ii) (( 0 : int):ii)  :  41 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*)
 
 val _ = Define `
- ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) (Mk_ContextReg (v)) x=
-    (Mk_ContextReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 23 : int):ii) x  :  64 words$word))))`;
+ ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) v x=
+    ((v with<|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii)
+           ((subrange_vec_dec x (( 40 : int):ii) (( 0 : int):ii)  :  41 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*)
 
 val _ = Define `
- ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) (Mk_ContextReg (v))=  ((subrange_vec_dec v (( 22 : int):ii) (( 4 : int):ii)  :  19 words$word)))`;
+ ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) v=
+    ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii)  :  19 words$word)))`;
 
 
 (*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*)
 
 val _ = Define `
- ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : ContextReg) . 
-   let r = ((get_ContextReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_ContextReg r))))`;
+ ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 18 : int):ii) (( 0 : int):ii)  :  19 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*)
 
 val _ = Define `
- ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) (Mk_ContextReg (v)) x=
-    (Mk_ContextReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) v x=
+    ((v with<|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 18 : int):ii) (( 0 : int):ii)  :  19 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val undefined_XContextReg : unit -> M XContextReg*)
 
 val _ = Define `
- ((undefined_XContextReg:unit ->(regstate)state_monad$sequential_state ->(((XContextReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_XContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((XContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   internal_pick [Mk_XContextReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| XContextReg_XContextReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_XContextReg : mword ty64 -> XContextReg*)
+
+val _ = Define `
+ ((Mk_XContextReg:(64)words$word -> XContextReg) v=
+    (<| XContextReg_XContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
-(*val _get_XContextReg : XContextReg -> mword ty64*)
+(*val _get_XContextReg_bits : XContextReg -> mword ty64*)
 
 val _ = Define `
- ((get_XContextReg:XContextReg ->(64)words$word) (Mk_XContextReg (v))=  v)`;
+ ((get_XContextReg_bits:XContextReg ->(64)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*)
+(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((set_XContextReg:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_XContextReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((set_XContextReg_bits:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_bits:XContextReg ->(64)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*)
 
 val _ = Define `
- ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) (Mk_XContextReg (v))=
-    ((subrange_vec_dec v (( 63 : int):ii) (( 33 : int):ii)  :  31 words$word)))`;
+ ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii)  :  31 words$word)))`;
 
 
 (*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*)
 
 val _ = Define `
- ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . 
-   let r = ((get_XContextReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 33 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_XContextReg r))))`;
+ ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii)
+             ((subrange_vec_dec v (( 30 : int):ii) (( 0 : int):ii)  :  31 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*)
 
 val _ = Define `
- ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) (Mk_XContextReg (v)) x=
-    (Mk_XContextReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 33 : int):ii) x  :  64 words$word))))`;
+ ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii)
+           ((subrange_vec_dec x (( 30 : int):ii) (( 0 : int):ii)  :  31 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_XContextReg_XR : XContextReg -> mword ty2*)
 
 val _ = Define `
- ((get_XContextReg_XR:XContextReg ->(2)words$word) (Mk_XContextReg (v))=  ((subrange_vec_dec v (( 32 : int):ii) (( 31 : int):ii)  :  2 words$word)))`;
+ ((get_XContextReg_XR:XContextReg ->(2)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . 
-   let r = ((get_XContextReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 32 : int):ii) (( 31 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_XContextReg r))))`;
+ ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*)
 
 val _ = Define `
- ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) (Mk_XContextReg (v)) x=
-    (Mk_XContextReg ((update_subrange_vec_dec v (( 32 : int):ii) (( 31 : int):ii) x  :  64 words$word))))`;
+ ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*)
 
 val _ = Define `
- ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) (Mk_XContextReg (v))=
-    ((subrange_vec_dec v (( 30 : int):ii) (( 4 : int):ii)  :  27 words$word)))`;
+ ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii)  :  27 words$word)))`;
 
 
 (*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*)
 
 val _ = Define `
- ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . 
-   let r = ((get_XContextReg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 30 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_XContextReg r))))`;
+ ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*)
 
 val _ = Define `
- ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) (Mk_XContextReg (v)) x=
-    (Mk_XContextReg ((update_subrange_vec_dec v (( 30 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
@@ -835,439 +1143,634 @@ val _ = Define `
 (*val undefined_TLBEntry : unit -> M TLBEntry*)
 
 val _ = Define `
- ((undefined_TLBEntry:unit ->(regstate)state_monad$sequential_state ->(((TLBEntry),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_TLBEntry:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 : int):ii)  : ( 53 words$word) M) (\ (w__0 :  53 words$word) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 : int):ii)  : ( 117 words$word) M) (\ (w__0 :  117 words$word) . 
-   internal_pick [Mk_TLBEntry w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   sail2_state_monad$returnS (<| TLBEntry_TLBEntry_chunk_1 := w__0; 
+              TLBEntry_TLBEntry_chunk_0 := w__1 |>)))))`;
 
 
-(*val _get_TLBEntry : TLBEntry -> mword ty117*)
+(*val Mk_TLBEntry : mword ty117 -> TLBEntry*)
 
 val _ = Define `
- ((get_TLBEntry:TLBEntry ->(117)words$word) (Mk_TLBEntry (v))=  v)`;
+ ((Mk_TLBEntry:(117)words$word -> TLBEntry) v=
+    (<| TLBEntry_TLBEntry_chunk_1 := ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii)  :  53 words$word)); 
+      TLBEntry_TLBEntry_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
-(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*)
+(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*)
 
 val _ = Define `
- ((set_TLBEntry:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_TLBEntry v) in
-   state_monad$write_regS r_ref r)))`;
+ ((get_TLBEntry_bits:TLBEntry ->(117)words$word) v=
+    ((concat_vec ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii)  :  53 words$word))
+      ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+     :  117 words$word)))`;
+
+
+(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_bits:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii)  :  53 words$word))
+            :  53 words$word))|>)) in
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_bits:TLBEntry ->(117)words$word -> TLBEntry) v x=
+    (let v =
+     ((v with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec x (( 116 : int):ii) (( 64 : int):ii)  :  53 words$word))
+            :  53 words$word))|>)) in
+   (v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*)
 
 val _ = Define `
- ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 116 : int):ii) (( 101 : int):ii)  :  16 words$word)))`;
+ ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii)  :  16 words$word)))`;
 
 
 (*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 116 : int):ii) (( 101 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii)
+             ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 116 : int):ii) (( 101 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii)
+           ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+          :  53 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_r : TLBEntry -> mword ty2*)
 
 val _ = Define `
- ((get_TLBEntry_r:TLBEntry ->(2)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 100 : int):ii) (( 99 : int):ii)  :  2 words$word)))`;
+ ((get_TLBEntry_r:TLBEntry ->(2)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 100 : int):ii) (( 99 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 100 : int):ii) (( 99 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  53 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*)
 
 val _ = Define `
- ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 98 : int):ii) (( 72 : int):ii)  :  27 words$word)))`;
+ ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii)  :  27 words$word)))`;
 
 
 (*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 98 : int):ii) (( 72 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 98 : int):ii) (( 72 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  53 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_asid : TLBEntry -> mword ty8*)
 
 val _ = Define `
- ((get_TLBEntry_asid:TLBEntry ->(8)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 71 : int):ii) (( 64 : int):ii)  :  8 words$word)))`;
+ ((get_TLBEntry_asid:TLBEntry ->(8)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
 
 
 (*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 71 : int):ii) (( 64 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 71 : int):ii) (( 64 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  53 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_g : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_g:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_g:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_valid : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_valid:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_valid:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 62 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 61 : int):ii) (( 61 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 61 : int):ii) (( 61 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 61 : int):ii) (( 61 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 60 : int):ii) (( 60 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 60 : int):ii) (( 60 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 60 : int):ii) (( 60 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*)
 
 val _ = Define `
- ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 59 : int):ii) (( 36 : int):ii)  :  24 words$word)))`;
+ ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii)  :  24 words$word)))`;
 
 
 (*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 59 : int):ii) (( 36 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii)
+             ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 59 : int):ii) (( 36 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii)
+           ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*)
 
 val _ = Define `
- ((get_TLBEntry_c1:TLBEntry ->(3)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 35 : int):ii) (( 33 : int):ii)  :  3 words$word)))`;
+ ((get_TLBEntry_c1:TLBEntry ->(3)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii)  :  3 words$word)))`;
 
 
 (*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 35 : int):ii) (( 33 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii)
+             ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 35 : int):ii) (( 33 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii)
+           ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_d1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 32 : int):ii) (( 32 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_d1:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 32 : int):ii) (( 32 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 32 : int):ii) (( 32 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_v1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_v1:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 31 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 30 : int):ii) (( 30 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 30 : int):ii) (( 30 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 30 : int):ii) (( 30 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 29 : int):ii) (( 29 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 29 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 29 : int):ii) (( 29 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*)
 
 val _ = Define `
- ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 28 : int):ii) (( 5 : int):ii)  :  24 words$word)))`;
+ ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii)  :  24 words$word)))`;
 
 
 (*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 28 : int):ii) (( 5 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 28 : int):ii) (( 5 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*)
 
 val _ = Define `
- ((get_TLBEntry_c0:TLBEntry ->(3)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)))`;
+ ((get_TLBEntry_c0:TLBEntry ->(3)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)))`;
 
 
 (*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 2 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 4 : int):ii) (( 2 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_d0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_d0:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*)
 
 val _ = Define `
- ((get_TLBEntry_v0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_TLBEntry_v0:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . 
-   let r = ((get_TLBEntry w__0  :  117 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  117 words$word)) in
-   state_monad$write_regS r_ref (Mk_TLBEntry r))))`;
+ ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
 val _ = Define `
- ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x=
-    (Mk_TLBEntry ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  117 words$word))))`;
+ ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
@@ -1288,262 +1791,376 @@ val _ = Define `
 (*val undefined_StatusReg : unit -> M StatusReg*)
 
 val _ = Define `
- ((undefined_StatusReg:unit ->(regstate)state_monad$sequential_state ->(((StatusReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_StatusReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((StatusReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
-   internal_pick [Mk_StatusReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+   sail2_state_monad$returnS (<| StatusReg_StatusReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_StatusReg : mword ty32 -> StatusReg*)
+
+val _ = Define `
+ ((Mk_StatusReg:(32)words$word -> StatusReg) v=
+    (<| StatusReg_StatusReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) |>))`;
+
 
+(*val _get_StatusReg_bits : StatusReg -> mword ty32*)
+
+val _ = Define `
+ ((get_StatusReg_bits:StatusReg ->(32)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))`;
 
-(*val _get_StatusReg : StatusReg -> mword ty32*)
+
+(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*)
 
 val _ = Define `
- ((get_StatusReg:StatusReg ->(32)words$word) (Mk_StatusReg (v))=  v)`;
+ ((set_StatusReg_bits:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*)
+(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*)
 
 val _ = Define `
- ((set_StatusReg:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_StatusReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_StatusReg_bits:StatusReg ->(32)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_CU : StatusReg -> mword ty4*)
 
 val _ = Define `
- ((get_StatusReg_CU:StatusReg ->(4)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)))`;
+ ((get_StatusReg_CU:StatusReg ->(4)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)))`;
 
 
 (*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 28 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii)
+             ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 31 : int):ii) (( 28 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii)
+           ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_BEV : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_BEV:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_BEV:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_IM : StatusReg -> mword ty8*)
 
 val _ = Define `
- ((get_StatusReg_IM:StatusReg ->(8)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
+ ((get_StatusReg_IM:StatusReg ->(8)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
 
 
 (*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_KX : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_KX:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_KX:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_SX : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_SX:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_SX:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_UX : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_UX:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_UX:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_KSU : StatusReg -> mword ty2*)
 
 val _ = Define `
- ((get_StatusReg_KSU:StatusReg ->(2)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)))`;
+ ((get_StatusReg_KSU:StatusReg ->(2)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 3 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 4 : int):ii) (( 3 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_ERL : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_ERL:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_ERL:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_EXL : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_EXL:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_EXL:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val _get_StatusReg_IE : StatusReg -> mword ty1*)
 
 val _ = Define `
- ((get_StatusReg_IE:StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_StatusReg_IE:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . 
-   let r = ((get_StatusReg w__0  :  32 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  32 words$word)) in
-   state_monad$write_regS r_ref (Mk_StatusReg r))))`;
+ ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*)
 
 val _ = Define `
- ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x=
-    (Mk_StatusReg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  32 words$word))))`;
+ ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
 (*val execute_branch : mword ty64 -> M unit*)
 
 val _ = Define `
- ((execute_branch:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) pc=  (state_monad$seqS
-   (state_monad$write_regS delayedPC_ref pc) (state_monad$write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
+ ((execute_branch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pc=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS delayedPC_ref pc) (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
 
 
 (*val NotWordVal : mword ty64 -> bool*)
@@ -1557,27 +2174,27 @@ val _ = Define `
 (*val rGPR : mword ty5 -> M (mword ty64)*)
 
 val _ = Define `
- ((rGPR:(5)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx=
+ ((rGPR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx=
     (let i = (lem$w2ui idx) in
    if (((i = (( 0 : int):ii)))) then
-     state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+     sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
               :  64 words$word)
-   else state_monad$bindS
-     (state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . 
-     state_monad$returnS ((access_list_dec w__0 i  :  64 words$word)))))`;
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . 
+     sail2_state_monad$returnS ((access_list_dec w__0 i  :  64 words$word)))))`;
 
 
 (*val wGPR : mword ty5 -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((wGPR:(5)words$word ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx v=
+ ((wGPR:(5)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx v=
     (let i = (lem$w2ui idx) in
-   if (((i = (( 0 : int):ii)))) then state_monad$returnS () 
-   else state_monad$bindS
-     (state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . 
-     state_monad$write_regS GPR_ref ((update_list_dec w__0 i v  : ( 64 words$word) list)))))`;
+   if (((i <> (( 0 : int):ii)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . 
+     sail2_state_monad$write_regS GPR_ref ((update_list_dec w__0 i v  : ( 64 words$word) list)))
+   else sail2_state_monad$returnS () ))`;
 
 
 
@@ -1598,25 +2215,25 @@ val _ = Define `
 
 val _ = Define `
  ((Exception_of_num:int -> Exception) arg_=
-    (let l__81 = arg_ in
-   if (((l__81 = (( 0 : int):ii)))) then Interrupt
-   else if (((l__81 = (( 1 : int):ii)))) then TLBMod
-   else if (((l__81 = (( 2 : int):ii)))) then TLBL
-   else if (((l__81 = (( 3 : int):ii)))) then TLBS
-   else if (((l__81 = (( 4 : int):ii)))) then AdEL
-   else if (((l__81 = (( 5 : int):ii)))) then AdES
-   else if (((l__81 = (( 6 : int):ii)))) then Sys
-   else if (((l__81 = (( 7 : int):ii)))) then Bp
-   else if (((l__81 = (( 8 : int):ii)))) then ResI
-   else if (((l__81 = (( 9 : int):ii)))) then CpU
-   else if (((l__81 = (( 10 : int):ii)))) then Ov
-   else if (((l__81 = (( 11 : int):ii)))) then Tr
-   else if (((l__81 = (( 12 : int):ii)))) then C2E
-   else if (((l__81 = (( 13 : int):ii)))) then C2Trap
-   else if (((l__81 = (( 14 : int):ii)))) then XTLBRefillL
-   else if (((l__81 = (( 15 : int):ii)))) then XTLBRefillS
-   else if (((l__81 = (( 16 : int):ii)))) then XTLBInvL
-   else if (((l__81 = (( 17 : int):ii)))) then XTLBInvS
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Interrupt
+   else if (((p0_ = (( 1 : int):ii)))) then TLBMod
+   else if (((p0_ = (( 2 : int):ii)))) then TLBL
+   else if (((p0_ = (( 3 : int):ii)))) then TLBS
+   else if (((p0_ = (( 4 : int):ii)))) then AdEL
+   else if (((p0_ = (( 5 : int):ii)))) then AdES
+   else if (((p0_ = (( 6 : int):ii)))) then Sys
+   else if (((p0_ = (( 7 : int):ii)))) then Bp
+   else if (((p0_ = (( 8 : int):ii)))) then ResI
+   else if (((p0_ = (( 9 : int):ii)))) then CpU
+   else if (((p0_ = (( 10 : int):ii)))) then Ov
+   else if (((p0_ = (( 11 : int):ii)))) then Tr
+   else if (((p0_ = (( 12 : int):ii)))) then C2E
+   else if (((p0_ = (( 13 : int):ii)))) then C2Trap
+   else if (((p0_ = (( 14 : int):ii)))) then XTLBRefillL
+   else if (((p0_ = (( 15 : int):ii)))) then XTLBRefillS
+   else if (((p0_ = (( 16 : int):ii)))) then XTLBInvL
+   else if (((p0_ = (( 17 : int):ii)))) then XTLBInvS
    else MCheck))`;
 
 
@@ -1650,8 +2267,8 @@ val _ = Define `
 (*val undefined_Exception : unit -> M Exception*)
 
 val _ = Define `
- ((undefined_Exception:unit ->(regstate)state_monad$sequential_state ->(((Exception),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =
-    (internal_pick
+ ((undefined_Exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((Exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
      [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`;
 
 
@@ -1687,27 +2304,27 @@ val _ = Define `
 (*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*)
 
 val _ = Define `
- ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex kccBase=  (state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) .  state_monad$bindS (state_monad$seqS
-   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then state_monad$bindS
-      (state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
-      if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then state_monad$bindS
-        (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  state_monad$seqS
-        (state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii)  :  64 words$word)))
+ ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex kccBase=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
+      if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii)  :  64 words$word)))
         (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1]  :  1 words$word)))
-      else state_monad$bindS
-        (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) .  state_monad$seqS
-        (state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0]  :  1 words$word))))
-    else state_monad$returnS () )
-   (state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . 
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) .  sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0]  :  1 words$word))))
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . 
    let vectorOffset =
      (if ((bits_to_bool ((get_StatusReg_EXL w__4  :  1 words$word)))) then
        (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
      else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then
        (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
      else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
-     else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)) in state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . 
+     else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . 
    let (vectorBase : 64 bits) =
      (if ((bits_to_bool ((get_StatusReg_BEV w__5  :  1 words$word)))) then
        (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
@@ -1718,15 +2335,15 @@ val _ = Define `
        (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
                      B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-         :  64 words$word)) in state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS
+         :  64 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      nextPC_ref
      ((sub_vec
-         ((add_vec vectorBase ((sign_extend1 (( 64 : int):ii) vectorOffset  :  64 words$word))  :  64 words$word))
+         ((add_vec vectorBase ((mips_sign_extend (( 64 : int):ii) vectorOffset  :  64 words$word))  :  64 words$word))
          kccBase
         :  64 words$word)))
    (set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex  :  5 words$word))))
-   (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1]  :  1 words$word))) (state_monad$throwS (ISAException () )))))))`;
+   (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1]  :  1 words$word))) (sail2_state_monad$throwS (ISAException () )))))))`;
 
 
 (*val SignalException : forall 'o. Exception -> M 'o*)
@@ -1874,17 +2491,17 @@ val _ = Define `
 
 
 val _ = Define `
- ((SignalException:Exception ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex=  (state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) .  state_monad$bindS (state_monad$seqS
-   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then state_monad$bindS
-      (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ pc .  state_monad$bindS
-      (state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__1 :  257 words$word) . 
+ ((SignalException:Exception ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ pc .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__1 :  257 words$word) . 
       let pcc = (capRegToCapStruct w__1) in
       let (success, epcc) = (setCapOffset pcc pc) in
-      if success then state_monad$write_regS C31_ref ((capStructToCapReg epcc  :  257 words$word))
+      if success then sail2_state_monad$write_regS EPCC_ref ((capStructToCapReg epcc  :  257 words$word))
       else
-        state_monad$write_regS
-          C31_ref
+        sail2_state_monad$write_regS
+          EPCC_ref
           ((capStructToCapReg
               ((int_to_cap
                   ((add_vec_int
@@ -1892,25 +2509,25 @@ val _ = Define `
                          :  64 words$word)) ((lem$w2ui pc))
                      :  64 words$word))))
              :  257 words$word))))
-    else state_monad$returnS () )
-   (state_monad$read_regS C29_ref  : ( 257 words$word) M)) (\ (w__2 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS nextPCC_ref w__2)
-   (state_monad$read_regS C29_ref  : ( 257 words$word) M)) (\ (w__3 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS delayedPCC_ref w__3)
-   (state_monad$read_regS C29_ref  : ( 257 words$word) M)) (\ (w__4 :  257 words$word) . 
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS KCC_ref  : ( 257 words$word) M)) (\ (w__2 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPCC_ref w__2)
+   (sail2_state_monad$read_regS KCC_ref  : ( 257 words$word) M)) (\ (w__3 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS delayedPCC_ref w__3)
+   (sail2_state_monad$read_regS KCC_ref  : ( 257 words$word) M)) (\ (w__4 :  257 words$word) . 
    let base = (getCapBase ((capRegToCapStruct w__4))) in
    SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) base  :  64 words$word))))))))`;
 
 
 val _ = Define `
- ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex badAddr=  (state_monad$seqS (state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`;
+ ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr=  (sail2_state_monad$seqS (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`;
 
 
 (*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*)
 
 val _ = Define `
- ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex badAddr=  (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS CP0BadVAddr_ref badAddr)
+ ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr=  (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr)
    (set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):ii) (( 13 : int):ii)  :  19 words$word))))
    (set_XContextReg_XBadVPN2 TLBXContext_ref
      ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word))))
@@ -1924,9 +2541,9 @@ val _ = Define `
 
 val _ = Define `
  ((MemAccessType_of_num:int -> MemAccessType) arg_=
-    (let l__79 = arg_ in
-   if (((l__79 = (( 0 : int):ii)))) then Instruction
-   else if (((l__79 = (( 1 : int):ii)))) then LoadData
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Instruction
+   else if (((p0_ = (( 1 : int):ii)))) then LoadData
    else StoreData))`;
 
 
@@ -1940,16 +2557,16 @@ val _ = Define `
 (*val undefined_MemAccessType : unit -> M MemAccessType*)
 
 val _ = Define `
- ((undefined_MemAccessType:unit ->(regstate)state_monad$sequential_state ->(((MemAccessType),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (internal_pick [Instruction;LoadData;StoreData]))`;
+ ((undefined_MemAccessType:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAccessType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [Instruction;LoadData;StoreData]))`;
 
 
 (*val AccessLevel_of_num : integer -> AccessLevel*)
 
 val _ = Define `
  ((AccessLevel_of_num:int -> AccessLevel) arg_=
-    (let l__77 = arg_ in
-   if (((l__77 = (( 0 : int):ii)))) then User
-   else if (((l__77 = (( 1 : int):ii)))) then Supervisor
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then User
+   else if (((p0_ = (( 1 : int):ii)))) then Supervisor
    else Kernel))`;
 
 
@@ -1963,7 +2580,7 @@ val _ = Define `
 (*val undefined_AccessLevel : unit -> M AccessLevel*)
 
 val _ = Define `
- ((undefined_AccessLevel:unit ->(regstate)state_monad$sequential_state ->(((AccessLevel),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (internal_pick [User;Supervisor;Kernel]))`;
+ ((undefined_AccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [User;Supervisor;Kernel]))`;
 
 
 (*val int_of_AccessLevel : AccessLevel -> ii*)
@@ -1989,18 +2606,18 @@ Returns the current effective access level determined by accessing the relevant
 (*val getAccessLevel : unit -> M AccessLevel*)
 
 val _ = Define `
- ((getAccessLevel:unit ->(regstate)state_monad$sequential_state ->(((AccessLevel),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state$or_boolS
-     ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
-      state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word))))))
-     ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . 
-      state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1  :  1 words$word))))))) (\ (w__2 : bool) . 
-   if w__2 then state_monad$returnS Kernel
-   else state_monad$bindS
-     (state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . 
-     let p__133 = ((get_StatusReg_KSU w__3  :  2 words$word)) in
-     let b__0 = p__133 in
-     state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then Kernel
+ ((getAccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1  :  1 words$word))))))) (\ (w__2 : bool) . 
+   if w__2 then sail2_state_monad$returnS Kernel
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . 
+     let p__31 = ((get_StatusReg_KSU w__3  :  2 words$word)) in
+     let b__0 = p__31 in
+     sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then Kernel
              else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then Supervisor
              else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then User
              else User)))))`;
@@ -2009,62 +2626,62 @@ val _ = Define `
 (*val checkCP0Access : unit -> M unit*)
 
 val _ = Define `
- ((checkCP0Access:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (getAccessLevel () ) (\ accessLevel .  state_monad$bindS
-   (state$and_boolS (state_monad$returnS (((accessLevel <> Kernel))))
-     ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
-      state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 :
+ ((checkCP0Access:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (getAccessLevel () ) (\ accessLevel .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS (((accessLevel <> Kernel))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+      sail2_state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 :
      bool) . 
-   if w__1 then state_monad$seqS
+   if w__1 then sail2_state_monad$seqS
      (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0]  :  2 words$word)) (SignalException CpU)
-   else state_monad$returnS () ))))`;
+   else sail2_state_monad$returnS () ))))`;
 
 
 (*val incrementCP0Count : unit -> M unit*)
 
 val _ = Define `
- ((incrementCP0Count:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__0 : TLBIndexT) .  state_monad$bindS
-   (state_monad$read_regS TLBWired_ref  : ( 6 words$word) M) (\ (w__1 :  6 words$word) .  state_monad$bindS
-   (if (((w__0 = w__1))) then state_monad$returnS TLBIndexMax
-    else state_monad$bindS
-      (state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__2 :  6 words$word) . 
-      state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii)  :  6 words$word)))) (\ (w__3 :  6 words$word) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBRandom_ref w__3)
-   (state_monad$read_regS CP0Count_ref  : ( 32 words$word) M)) (\ (w__4 :  32 words$word) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii)  :  32 words$word)))
-   (state_monad$read_regS CP0Count_ref  : ( 32 words$word) M)) (\ (w__5 : 32 bits) .  state_monad$bindS
-   (state_monad$read_regS CP0Compare_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  state_monad$bindS (state_monad$seqS
-   (if (((w__5 = w__6))) then state_monad$bindS
-      (state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . 
+ ((incrementCP0Count:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__0 : TLBIndexT) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS TLBWired_ref  : ( 6 words$word) M) (\ (w__1 :  6 words$word) .  sail2_state_monad$bindS
+   (if (((w__0 = w__1))) then sail2_state_monad$returnS TLBIndexMax
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__2 :  6 words$word) . 
+      sail2_state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii)  :  6 words$word)))) (\ (w__3 :  6 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBRandom_ref w__3)
+   (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M)) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii)  :  32 words$word)))
+   (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M)) (\ (w__5 : 32 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Compare_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if (((w__5 = w__6))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . 
       set_CauseReg_IP CP0Cause_ref
         ((or_vec ((get_CauseReg_IP w__7  :  8 words$word))
             (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
            :  8 words$word)))
-    else state_monad$returnS () )
-   (state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . 
-   let ims = ((get_StatusReg_IM w__8  :  8 words$word)) in state_monad$bindS
-   (state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . 
-   let ips = ((get_CauseReg_IP w__9  :  8 words$word)) in state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . 
-   let ie = ((get_StatusReg_IE w__10  :  1 words$word)) in state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . 
-   let exl = ((get_StatusReg_EXL w__11  :  1 words$word)) in state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . 
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . 
+   let ims = ((get_StatusReg_IM w__8  :  8 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . 
+   let ips = ((get_CauseReg_IP w__9  :  8 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . 
+   let ie = ((get_StatusReg_IE w__10  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . 
+   let exl = ((get_StatusReg_EXL w__11  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . 
    let erl = ((get_StatusReg_ERL w__12  :  1 words$word)) in
    if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims  :  8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))))))))) then
      SignalException Interrupt
-   else state_monad$returnS () )))))))))))))`;
+   else sail2_state_monad$returnS () )))))))))))))`;
 
 
 (*val decode_failure_of_num : integer -> decode_failure*)
 
 val _ = Define `
  ((decode_failure_of_num:int -> decode_failure) arg_=
-    (let l__74 = arg_ in
-   if (((l__74 = (( 0 : int):ii)))) then No_matching_pattern
-   else if (((l__74 = (( 1 : int):ii)))) then Unsupported_instruction
-   else if (((l__74 = (( 2 : int):ii)))) then Illegal_instruction
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then No_matching_pattern
+   else if (((p0_ = (( 1 : int):ii)))) then Unsupported_instruction
+   else if (((p0_ = (( 2 : int):ii)))) then Illegal_instruction
    else Internal_error))`;
 
 
@@ -2078,22 +2695,22 @@ val _ = Define `
 (*val undefined_decode_failure : unit -> M decode_failure*)
 
 val _ = Define `
- ((undefined_decode_failure:unit ->(regstate)state_monad$sequential_state ->(((decode_failure),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =
-    (internal_pick [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`;
+ ((undefined_decode_failure:unit ->(regstate)sail2_state_monad$sequential_state ->(((decode_failure),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`;
 
 
 (*val Comparison_of_num : integer -> Comparison*)
 
 val _ = Define `
  ((Comparison_of_num:int -> Comparison) arg_=
-    (let l__67 = arg_ in
-   if (((l__67 = (( 0 : int):ii)))) then EQ'
-   else if (((l__67 = (( 1 : int):ii)))) then NE
-   else if (((l__67 = (( 2 : int):ii)))) then GE
-   else if (((l__67 = (( 3 : int):ii)))) then GEU
-   else if (((l__67 = (( 4 : int):ii)))) then GT'
-   else if (((l__67 = (( 5 : int):ii)))) then LE
-   else if (((l__67 = (( 6 : int):ii)))) then LT'
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then EQ'
+   else if (((p0_ = (( 1 : int):ii)))) then NE
+   else if (((p0_ = (( 2 : int):ii)))) then GE
+   else if (((p0_ = (( 3 : int):ii)))) then GEU
+   else if (((p0_ = (( 4 : int):ii)))) then GT'
+   else if (((p0_ = (( 5 : int):ii)))) then LE
+   else if (((p0_ = (( 6 : int):ii)))) then LT'
    else LTU))`;
 
 
@@ -2116,7 +2733,7 @@ val _ = Define `
 (*val undefined_Comparison : unit -> M Comparison*)
 
 val _ = Define `
- ((undefined_Comparison:unit ->(regstate)state_monad$sequential_state ->(((Comparison),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`;
+ ((undefined_Comparison:unit ->(regstate)sail2_state_monad$sequential_state ->(((Comparison),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`;
 
 
 (*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*)
@@ -2139,10 +2756,10 @@ val _ = Define `
 
 val _ = Define `
  ((WordType_of_num:int -> WordType) arg_=
-    (let l__64 = arg_ in
-   if (((l__64 = (( 0 : int):ii)))) then B
-   else if (((l__64 = (( 1 : int):ii)))) then H
-   else if (((l__64 = (( 2 : int):ii)))) then W0
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then B
+   else if (((p0_ = (( 1 : int):ii)))) then H
+   else if (((p0_ = (( 2 : int):ii)))) then W0
    else D))`;
 
 
@@ -2156,7 +2773,31 @@ val _ = Define `
 (*val undefined_WordType : unit -> M WordType*)
 
 val _ = Define `
- ((undefined_WordType:unit ->(regstate)state_monad$sequential_state ->(((WordType),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (internal_pick [B;H;W0;D]))`;
+ ((undefined_WordType:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [B;H;W0;D]))`;
+
+
+(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*)
+
+val _ = Define `
+ ((WordTypeUnaligned_of_num:int -> WordTypeUnaligned) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then WL
+   else if (((p0_ = (( 1 : int):ii)))) then WR
+   else if (((p0_ = (( 2 : int):ii)))) then DL
+   else DR))`;
+
+
+(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*)
+
+val _ = Define `
+ ((num_of_WordTypeUnaligned:WordTypeUnaligned -> int) arg_=
+    ((case arg_ of   WL => (( 0 : int):ii) | WR => (( 1 : int):ii) | DL => (( 2 : int):ii) | DR => (( 3 : int):ii) )))`;
+
+
+(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*)
+
+val _ = Define `
+ ((undefined_WordTypeUnaligned:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordTypeUnaligned),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [WL;WR;DL;DR]))`;
 
 
 (*val wordWidthBytes : WordType -> integer*)
@@ -2181,15 +2822,15 @@ val _ = Define `
 (*val MEMr_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*)
 
 val _ = Define `
- ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1=
+ ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1=
     (if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-            :  64 words$word)))) then state_monad$bindS
-     (state_monad$read_regS UART_RVALID_ref  : ( 1 words$word) M) (\ rvalid .  state_monad$bindS (state_monad$seqS
-     (state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0]  :  1 words$word))
-     (state_monad$read_regS UART_RDATA_ref  : ( 8 words$word) M)) (\ (w__0 : 8 bits) . 
-     state_monad$returnS ((mask p8_times_n___tv
+            :  64 words$word)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS UART_RVALID_ref  : ( 1 words$word) M) (\ rvalid .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0]  :  1 words$word))
+     (sail2_state_monad$read_regS UART_RDATA_ref  : ( 8 words$word) M)) (\ (w__0 : 8 bits) . 
+     sail2_state_monad$returnS ((mask p8_times_n___tv
                 ((concat_vec
                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
@@ -2208,29 +2849,29 @@ val _ = Define `
                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;
                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]
                  :  64 words$word)))) then
-     state_monad$returnS ((mask p8_times_n___tv
+     sail2_state_monad$returnS ((mask p8_times_n___tv
                 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
                               B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]
                   :  64 words$word)
                :  'p8_times_n_ words$word))
-   else state_monad$bindS
-     (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) M) (\ w__1 . 
-     state_monad$returnS ((reverse_endianness w__1  :  'p8_times_n_ words$word)))))`;
+   else sail2_state_monad$bindS
+     (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) M) (\ w__1 . 
+     sail2_state_monad$returnS ((reverse_endianness w__1  :  'p8_times_n_ words$word)))))`;
 
 
 (*val MEMr_reserve_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
 
 val _ = Define `
- ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1=  (state_monad$bindS
-   (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) M) (\ w__0 . 
-   state_monad$returnS ((reverse_endianness w__0  :  'p8_times_n_ words$word)))))`;
+ ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1=  (sail2_state_monad$bindS
+   (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) M) (\ w__0 . 
+   sail2_state_monad$returnS ((reverse_endianness w__0  :  'p8_times_n_ words$word)))))`;
 
 
 (*val init_cp0_state : unit -> M unit*)
 
 val _ = Define `
- ((init_cp0_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1  :  1 words$word))))`;
+ ((init_cp0_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1  :  1 words$word))))`;
 
 
 (*val init_cp2_state : unit -> M unit*)
@@ -2413,66 +3054,66 @@ val _ = Define `
    let entryASID = ((get_TLBEntry_asid entry  :  8 words$word)) in
    let entryG = ((get_TLBEntry_g entry  :  1 words$word)) in
    let (vpnMask : 27 bits) =
-     ((not_vec ((zero_extend1 (( 27 : int):ii) entryMask  :  27 words$word))  :  27 words$word)) in
+     ((not_vec ((mips_zero_extend (( 27 : int):ii) entryMask  :  27 words$word))  :  27 words$word)) in
    (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask  :  27 words$word)) = ((and_vec entryVPN vpnMask  :  27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`;
 
 
 (*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*)
 
 val _ = Define `
- ((tlbSearch:(64)words$word ->(regstate)state_monad$sequential_state ->(((((6)words$word)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) VAddr=
-    (state_monad$catch_early_returnS
+ ((tlbSearch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((6)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) VAddr=
+    (sail2_state_monad$catch_early_returnS
      (let r = ((subrange_vec_dec VAddr (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)) in
-     let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word)) in state_monad$bindS
-     (state_monad$liftRS (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . 
-     let asid = ((get_TLBEntryHiReg_ASID w__0  :  8 words$word)) in state_monad$seqS
-     (state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () 
-       (\ idx unit_var .  state_monad$bindS
-         (state_monad$liftRS (state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . 
+     let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . 
+     let asid = ((get_TLBEntryHiReg_ASID w__0  :  8 words$word)) in sail2_state_monad$seqS
+     (sail2_state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () 
+       (\ idx unit_var .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . 
          if ((tlbEntryMatch r vpn2 asid w__1)) then
-           (state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii)  :  6 itself)) idx  :  6 words$word))) : (unit, ( ( 6 words$word)option))
+           (sail2_state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii)  :  6 itself)) idx  :  6 words$word))) : (unit, ( ( 6 words$word)option))
              MR)
-         else state_monad$returnS () )))
-     (state_monad$returnS NONE)))))`;
+         else sail2_state_monad$returnS () )))
+     (sail2_state_monad$returnS NONE)))))`;
 
 
 (*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*)
 
 val _ = Define `
- ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word#bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType=  (state_monad$bindS
+ ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType=  (sail2_state_monad$bindS
    (tlbSearch vAddr  : ( ( 6 words$word)option) M) (\ idx . 
    (case idx of
      SOME (idx) =>
-      let i = (lem$w2ui idx) in state_monad$bindS
-      (state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . 
+      let i = (lem$w2ui idx) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . 
       let entryMask = ((get_TLBEntry_pagemask entry  :  16 words$word)) in
-      let b__0 = entryMask in state_monad$bindS
+      let b__0 = entryMask in sail2_state_monad$bindS
       (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) then
-         state_monad$returnS (( 12 : int):ii)
+         sail2_state_monad$returnS (( 12 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 14 : int):ii)
+         sail2_state_monad$returnS (( 14 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 16 : int):ii)
+         sail2_state_monad$returnS (( 16 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 18 : int):ii)
+         sail2_state_monad$returnS (( 18 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 20 : int):ii)
+         sail2_state_monad$returnS (( 20 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 22 : int):ii)
+         sail2_state_monad$returnS (( 22 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 24 : int):ii)
+         sail2_state_monad$returnS (( 24 : int):ii)
        else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 26 : int):ii)
+         sail2_state_monad$returnS (( 26 : int):ii)
        else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
        then
-         state_monad$returnS (( 28 : int):ii)
+         sail2_state_monad$returnS (( 28 : int):ii)
        else undefined_range (( 12 : int):ii) (( 28 : int):ii)) (\ (evenOddBit : int) . 
       let isOdd = (access_vec_dec vAddr evenOddBit) in
       let ((caps : 1 bits), (capl : 1 bits), (pfn : 24 bits), (d : 1 bits), (v : 1 bits)) =
@@ -2495,7 +3136,7 @@ val _ = Define `
         (SignalExceptionTLB TLBMod vAddr  : (( 64 words$word # bool)) M)
       else
         let (res : 64 bits) =
-          ((zero_extend1 (( 64 : int):ii)
+          ((mips_zero_extend (( 64 : int):ii)
              ((subrange_subrange_concat
                  (((((((( 23 : int):ii) -
                              ((((evenOddBit - (( 12 : int):ii))) - (( 1 : int):ii)))))
@@ -2506,7 +3147,7 @@ val _ = Define `
                  ((evenOddBit - (( 1 : int):ii))) (( 0 : int):ii)
                 :  36 words$word))
             :  64 words$word)) in
-        state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl))))
+        sail2_state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl))))
    | NONE =>
       (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr
         : (( 64 words$word # bool)) M)
@@ -2516,7 +3157,7 @@ val _ = Define `
 (*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*)
 
 val _ = Define `
- ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word#bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType=  (state_monad$bindS
+ ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType=  (sail2_state_monad$bindS
    (getAccessLevel () ) (\ currentAccessLevel . 
    let compat32 =
      (((subrange_vec_dec vAddr (( 61 : int):ii) (( 31 : int):ii)  :  31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
@@ -2539,7 +3180,7 @@ val _ = Define `
                           ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii)  :  29 words$word))
                          :  32 words$word))
                      :  64 words$word)))
-          else
+          else if (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
             (Kernel,
              SOME ((concat_vec
                       (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -2549,7 +3190,8 @@ val _ = Define `
                           ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii)  :  29 words$word))
                          :  32 words$word))
                      :  64 words$word)))
-       | (g__131, g__132) => (Kernel, NONE)
+          else (case (T, b__1) of   (g__29, g__30) => (Kernel, NONE) )
+       | (g__29, g__30) => (Kernel, NONE)
        )
      else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
        (Kernel,
@@ -2561,9 +3203,9 @@ val _ = Define `
    if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then
      (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
        : (( 64 words$word # bool)) M)
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (case addr of
-       SOME (a) => state_monad$returnS (a, F)
+       SOME (a) => sail2_state_monad$returnS (a, F)
      | NONE =>
         if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):ii) (( 0 : int):ii)  :  62 words$word)))) > MAX_VA))))) then
           (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
@@ -2573,29 +3215,29 @@ val _ = Define `
      if ((((lem$w2ui pa)) > MAX_PA)) then
        (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
          : (( 64 words$word # bool)) M)
-     else state_monad$returnS (pa, c)))))`;
+     else sail2_state_monad$returnS (pa, c)))))`;
 
 
 (*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*)
 
 val _ = Define `
- ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType=  (state_monad$bindS
+ ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType=  (sail2_state_monad$bindS
    (TLBTranslateC vAddr accessType  : (( 64 words$word # bool)) M) (\ varstup .  let (addr, c) = varstup in
-   state_monad$returnS addr)))`;
+   sail2_state_monad$returnS addr)))`;
 
 
 (*val CPtrCmpOp_of_num : integer -> CPtrCmpOp*)
 
 val _ = Define `
  ((CPtrCmpOp_of_num:int -> CPtrCmpOp) arg_=
-    (let l__57 = arg_ in
-   if (((l__57 = (( 0 : int):ii)))) then CEQ
-   else if (((l__57 = (( 1 : int):ii)))) then CNE
-   else if (((l__57 = (( 2 : int):ii)))) then CLT
-   else if (((l__57 = (( 3 : int):ii)))) then CLE
-   else if (((l__57 = (( 4 : int):ii)))) then CLTU
-   else if (((l__57 = (( 5 : int):ii)))) then CLEU
-   else if (((l__57 = (( 6 : int):ii)))) then CEXEQ
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CEQ
+   else if (((p0_ = (( 1 : int):ii)))) then CNE
+   else if (((p0_ = (( 2 : int):ii)))) then CLT
+   else if (((p0_ = (( 3 : int):ii)))) then CLE
+   else if (((p0_ = (( 4 : int):ii)))) then CLTU
+   else if (((p0_ = (( 5 : int):ii)))) then CLEU
+   else if (((p0_ = (( 6 : int):ii)))) then CEXEQ
    else CNEXEQ))`;
 
 
@@ -2618,17 +3260,17 @@ val _ = Define `
 (*val undefined_CPtrCmpOp : unit -> M CPtrCmpOp*)
 
 val _ = Define `
- ((undefined_CPtrCmpOp:unit ->(regstate)state_monad$sequential_state ->(((CPtrCmpOp),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`;
+ ((undefined_CPtrCmpOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((CPtrCmpOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`;
 
 
 (*val ClearRegSet_of_num : integer -> ClearRegSet*)
 
 val _ = Define `
  ((ClearRegSet_of_num:int -> ClearRegSet) arg_=
-    (let l__54 = arg_ in
-   if (((l__54 = (( 0 : int):ii)))) then GPLo
-   else if (((l__54 = (( 1 : int):ii)))) then GPHi
-   else if (((l__54 = (( 2 : int):ii)))) then CLo
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then GPLo
+   else if (((p0_ = (( 1 : int):ii)))) then GPHi
+   else if (((p0_ = (( 2 : int):ii)))) then CLo
    else CHi))`;
 
 
@@ -2642,41 +3284,41 @@ val _ = Define `
 (*val undefined_ClearRegSet : unit -> M ClearRegSet*)
 
 val _ = Define `
- ((undefined_ClearRegSet:unit ->(regstate)state_monad$sequential_state ->(((ClearRegSet),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (internal_pick [GPLo;GPHi;CLo;CHi]))`;
+ ((undefined_ClearRegSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((ClearRegSet),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [GPLo;GPHi;CLo;CHi]))`;
 
 
 (*val undefined_CapStruct : unit -> M CapStruct*)
 
 val _ = Define `
- ((undefined_CapStruct:unit ->(regstate)state_monad$sequential_state ->(((CapStruct),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__0 : bool) .  state_monad$bindS
+ ((undefined_CapStruct:unit ->(regstate)sail2_state_monad$sequential_state ->(((CapStruct),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M) (\ (w__1 : 8 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M) (\ (w__1 : 8 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 : int):ii)  : ( 24 words$word) M) (\ (w__2 : 24 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 24 : int):ii)  : ( 24 words$word) M) (\ (w__2 : 24 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__3 : 16 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__3 : 16 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__4 : 4 bits) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__5 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__6 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__7 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__8 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__9 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__10 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__11 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__12 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__13 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__14 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__15 : bool) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__16 : bool) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 4 : int):ii)  : ( 4 words$word) M) (\ (w__4 : 4 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__5 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__6 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__7 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__8 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__9 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__10 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__11 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__12 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__13 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__14 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__15 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (w__16 : bool) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__17 : 64 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__17 : 64 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__18 : 64 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__18 : 64 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__19 : 64 bits) . 
-   state_monad$returnS (<| CapStruct_tag := w__0; 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__19 : 64 bits) . 
+   sail2_state_monad$returnS (<| CapStruct_tag := w__0; 
               CapStruct_padding := w__1; 
               CapStruct_otype := w__2; 
               CapStruct_uperms := w__3; 
@@ -2704,7 +3346,7 @@ val _ = Define `
      CapStruct_padding := ((zeros0 (( 8 : int):ii) ()   :  8 words$word)); 
      CapStruct_otype := ((zeros0 (( 24 : int):ii) ()   :  24 words$word)); 
      CapStruct_uperms := ((ones (( 16 : int):ii) ()   :  16 words$word)); 
-     CapStruct_perm_reserved11_14 := ((ones (( 4 : int):ii) ()   :  4 words$word)); 
+     CapStruct_perm_reserved11_14 := ((zeros0 (( 4 : int):ii) ()   :  4 words$word)); 
      CapStruct_access_system_regs := T; 
      CapStruct_permit_unseal := T; 
      CapStruct_permit_ccall := T; 
@@ -2729,797 +3371,132 @@ val _ = Define `
 val _ = Define `
 ((null_cap_bits:(256)words$word)=  ((capStructToMemBits256 null_cap  :  256 words$word)))`;
 
-
-(*val capStructToMemBits : CapStruct -> mword ty256*)
-
-val _ = Define `
- ((capStructToMemBits:CapStruct ->(256)words$word) cap=
-    ((xor_vec ((capStructToMemBits256 cap  :  256 words$word)) null_cap_bits  :  256 words$word)))`;
-
-
-(*val memBitsToCapBits : bool -> mword ty256 -> mword ty257*)
-
-val _ = Define `
- ((memBitsToCapBits:bool ->(256)words$word ->(257)words$word) tag b=
-    ((concat_vec ((bool_to_bits tag  :  1 words$word)) ((xor_vec b null_cap_bits  :  256 words$word))
-     :  257 words$word)))`;
-
-
-(*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*)
-
-val _ = Define `
- ((setCapPerms:CapStruct ->(31)words$word -> CapStruct) cap perms=
-    ((cap with<|
-     CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):ii) (( 15 : int):ii)  :  16 words$word)); CapStruct_perm_reserved11_14 :=
-       ((subrange_vec_dec perms (( 14 : int):ii) (( 11 : int):ii)  :  4 words$word)); CapStruct_access_system_regs :=
-       ((bit_to_bool ((access_vec_dec perms (( 10 : int):ii))))); CapStruct_permit_unseal :=
-       ((bit_to_bool ((access_vec_dec perms (( 9 : int):ii))))); CapStruct_permit_ccall :=
-       ((bit_to_bool ((access_vec_dec perms (( 8 : int):ii))))); CapStruct_permit_seal :=
-       ((bit_to_bool ((access_vec_dec perms (( 7 : int):ii))))); CapStruct_permit_store_local_cap :=
-       ((bit_to_bool ((access_vec_dec perms (( 6 : int):ii))))); CapStruct_permit_store_cap :=
-       ((bit_to_bool ((access_vec_dec perms (( 5 : int):ii))))); CapStruct_permit_load_cap :=
-       ((bit_to_bool ((access_vec_dec perms (( 4 : int):ii))))); CapStruct_permit_store :=
-       ((bit_to_bool ((access_vec_dec perms (( 3 : int):ii))))); CapStruct_permit_load :=
-       ((bit_to_bool ((access_vec_dec perms (( 2 : int):ii))))); CapStruct_permit_execute :=
-       ((bit_to_bool ((access_vec_dec perms (( 1 : int):ii))))); CapStruct_global :=
-       ((bit_to_bool ((access_vec_dec perms (( 0 : int):ii)))))|>)))`;
-
-
-(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*)
-
-val _ = Define `
- ((sealCap:CapStruct ->(24)words$word -> bool#CapStruct) cap otype=  (T, (cap with<| CapStruct_sealed := T; CapStruct_otype := otype|>)))`;
-
-
-(*val getCapTop : CapStruct -> integer*)
-
-val _ = Define `
- ((getCapTop:CapStruct -> int) c=  (((lem$w2ui c.CapStruct_base)) + ((lem$w2ui c.CapStruct_length))))`;
-
-
-(*val getCapOffset : CapStruct -> integer*)
-
-val _ = Define `
- ((getCapOffset:CapStruct -> int) c=
-    (hardware_mod ((((lem$w2ui c.CapStruct_address)) - ((lem$w2ui c.CapStruct_base))))
-     ((pow2 (( 64 : int):ii)))))`;
-
-
-(*val getCapLength : CapStruct -> integer*)
-
-val _ = Define `
- ((getCapLength:CapStruct -> int) c=  (lem$w2ui c.CapStruct_length))`;
-
-
-(*val getCapCursor : CapStruct -> integer*)
-
-val _ = Define `
- ((getCapCursor:CapStruct -> int) c=  (lem$w2ui c.CapStruct_address))`;
-
-
-(*
-\function{incCapOffset} is the same as \function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic).
- *)
-(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*)
-
-val _ = Define `
- ((incCapOffset:CapStruct ->(64)words$word -> bool#CapStruct) c delta=
-    (let (newAddr : 64 bits) = ((add_vec c.CapStruct_address delta  :  64 words$word)) in
-   (T, (c with<| CapStruct_address := newAddr|>))))`;
-
-
-(*
-Returns a capability derived from the given capability by setting the base and top to values provided.  The offset of the resulting capability is zero.  In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values.
- *)
-(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*)
-
-val _ = Define `
- ((setCapBounds:CapStruct ->(64)words$word ->(65)words$word -> bool#CapStruct) cap base top=
-    (let (length : 65 bits) =
-     ((sub_vec top ((concat_vec (vec_of_bits [B0]  :  1 words$word) base  :  65 words$word))  :  65 words$word)) in
-   (T,
-    (cap with<|
-      CapStruct_base := base; CapStruct_length :=
-        ((subrange_vec_dec length (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)); CapStruct_address := base|>))))`;
-
-
-(*val undefined_ast : unit -> M ast*)
-
-val _ = Define `
- ((undefined_ast:unit ->(regstate)state_monad$sequential_state ->(((ast),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__0 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__1 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__2 :  16 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__3 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__4 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__5 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__6 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__7 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__8 :  16 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__9 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__10 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__11 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__12 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__13 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__14 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__15 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__16 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__17 :  16 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__18 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__19 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__20 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__21 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__22 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__23 :  16 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__24 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__25 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__26 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__27 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__28 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__29 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__30 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__31 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__32 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__33 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__34 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__35 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__36 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__37 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__38 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__39 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__40 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__41 :  16 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__42 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__43 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__44 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__45 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__46 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__47 :  16 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__48 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__49 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__50 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__51 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__52 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__53 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__54 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__299 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__302 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__304 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__309 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__313 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__315 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):ii)  : ( 11 words$word) M) (\ (w__316 :  11 words$word) .  state_monad$bindS (state_monad$seqS
-   (undefined_unit () )
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M)) (\ (w__317 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__318 :  16 words$word) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__319 : bool) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__320 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__321 :  16 words$word) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__322 : bool) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__323 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__324 :  5 words$word) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__325 : bool) .  state_monad$bindS
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__327 :  5 words$word) .  state_monad$bindS
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-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M) (\ (w__329 :  8 words$word) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__330 : bool) .  state_monad$bindS
-   (undefined_WordType () ) (\ (w__331 : WordType) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__332 : bool) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__333 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__334 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__335 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__336 :  5 words$word) .  state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M) (\ (w__337 :  8 words$word) .  state_monad$bindS
-   (undefined_WordType () ) (\ (w__338 : WordType) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__339 : bool) .  state_monad$bindS
+
+(*val capStructToMemBits : CapStruct -> mword ty256*)
+
+val _ = Define `
+ ((capStructToMemBits:CapStruct ->(256)words$word) cap=
+    ((xor_vec ((capStructToMemBits256 cap  :  256 words$word)) null_cap_bits  :  256 words$word)))`;
+
+
+(*val memBitsToCapBits : bool -> mword ty256 -> mword ty257*)
+
+val _ = Define `
+ ((memBitsToCapBits:bool ->(256)words$word ->(257)words$word) tag b=
+    ((concat_vec ((bool_to_bits tag  :  1 words$word)) ((xor_vec b null_cap_bits  :  256 words$word))
+     :  257 words$word)))`;
+
+
+(*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*)
+
+val _ = Define `
+ ((setCapPerms:CapStruct ->(31)words$word -> CapStruct) cap perms=
+    ((cap with<|
+     CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):ii) (( 15 : int):ii)  :  16 words$word)); CapStruct_access_system_regs :=
+       ((bit_to_bool ((access_vec_dec perms (( 10 : int):ii))))); CapStruct_permit_unseal :=
+       ((bit_to_bool ((access_vec_dec perms (( 9 : int):ii))))); CapStruct_permit_ccall :=
+       ((bit_to_bool ((access_vec_dec perms (( 8 : int):ii))))); CapStruct_permit_seal :=
+       ((bit_to_bool ((access_vec_dec perms (( 7 : int):ii))))); CapStruct_permit_store_local_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 6 : int):ii))))); CapStruct_permit_store_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 5 : int):ii))))); CapStruct_permit_load_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 4 : int):ii))))); CapStruct_permit_store :=
+       ((bit_to_bool ((access_vec_dec perms (( 3 : int):ii))))); CapStruct_permit_load :=
+       ((bit_to_bool ((access_vec_dec perms (( 2 : int):ii))))); CapStruct_permit_execute :=
+       ((bit_to_bool ((access_vec_dec perms (( 1 : int):ii))))); CapStruct_global :=
+       ((bit_to_bool ((access_vec_dec perms (( 0 : int):ii)))))|>)))`;
+
+
+(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*)
+
+val _ = Define `
+ ((sealCap:CapStruct ->(24)words$word -> bool#CapStruct) cap otype=  (T, (cap with<| CapStruct_sealed := T; CapStruct_otype := otype|>)))`;
+
+
+(*val getCapTop : CapStruct -> integer*)
+
+val _ = Define `
+ ((getCapTop:CapStruct -> int) c=  (((lem$w2ui c.CapStruct_base)) + ((lem$w2ui c.CapStruct_length))))`;
+
+
+(*val getCapOffset : CapStruct -> integer*)
+
+val _ = Define `
+ ((getCapOffset:CapStruct -> int) c=
+    (hardware_mod ((((lem$w2ui c.CapStruct_address)) - ((lem$w2ui c.CapStruct_base))))
+     ((pow2 (( 64 : int):ii)))))`;
+
+
+(*val getCapLength : CapStruct -> integer*)
+
+val _ = Define `
+ ((getCapLength:CapStruct -> int) c=  (lem$w2ui c.CapStruct_length))`;
+
+
+(*val getCapCursor : CapStruct -> integer*)
+
+val _ = Define `
+ ((getCapCursor:CapStruct -> int) c=  (lem$w2ui c.CapStruct_address))`;
+
+
+(*
+\function{incCapOffset} is the same as \function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic).
+ *)
+(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*)
+
+val _ = Define `
+ ((incCapOffset:CapStruct ->(64)words$word -> bool#CapStruct) c delta=
+    (let (newAddr : 64 bits) = ((add_vec c.CapStruct_address delta  :  64 words$word)) in
+   (T, (c with<| CapStruct_address := newAddr|>))))`;
+
+
+(*
+Returns a capability derived from the given capability by setting the base and top to values provided.  The offset of the resulting capability is zero.  In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values.
+ *)
+(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*)
+
+val _ = Define `
+ ((setCapBounds:CapStruct ->(64)words$word ->(65)words$word -> bool#CapStruct) cap base top=
+    (let (length : 65 bits) =
+     ((sub_vec top ((concat_vec (vec_of_bits [B0]  :  1 words$word) base  :  65 words$word))  :  65 words$word)) in
+   (T,
+    (cap with<|
+      CapStruct_base := base; CapStruct_length :=
+        ((subrange_vec_dec length (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)); CapStruct_address := base|>))))`;
+
+
+(*val undefined_ast : unit -> M ast*)
+
+val _ = Define `
+ ((undefined_ast:unit ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_CPtrCmpOp () ) (\ (u_0 : CPtrCmpOp) .  sail2_state_monad$bindS
+   (undefined_ClearRegSet () ) (\ (u_1 : ClearRegSet) .  sail2_state_monad$bindS
+   (undefined_Comparison () ) (\ (u_2 : Comparison) .  sail2_state_monad$bindS
+   (undefined_WordType () ) (\ (u_3 : WordType) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (u_5 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (u_4 : bool) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__340 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (u_6 : imm16) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__341 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_10 : regno) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__342 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_9 : regno) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__343 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_8 : regno) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):ii)  : ( 11 words$word) M) (\ (w__344 :  11 words$word) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__345 : bool) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_7 : regno) .  sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_11 : unit) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__346 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii)  : ( 3 words$word) M) (\ (u_12 : 3 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__347 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M) (\ (u_13 : 8 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__348 :  5 words$word) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 11 : int):ii)  : ( 11 words$word) M) (\ (u_14 : 11 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):ii)  : ( 11 words$word) M) (\ (w__349 :  11 words$word) .  state_monad$bindS
-   (state_monad$undefined_boolS () ) (\ (w__350 : bool) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (u_15 : 16 bits) .  sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (w__351 :  5 words$word) .  state_monad$seqS
-   (undefined_unit () )
-   (internal_pick
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+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 : int):ii)  : ( 26 words$word) M) (\ (u_16 : 26 bits) . 
+   sail2_state$internal_pickS
+     [DADDIU (u_8,u_7,u_6);DADDU (u_9,u_8,u_7);DADDI (u_8,u_7,u_15);DADD (u_9,u_8,u_7);ADD (u_9,u_8,u_7);ADDI (u_8,u_7,u_15);ADDU (u_9,u_8,u_7);ADDIU (u_8,u_7,u_15);DSUBU (u_9,u_8,u_7);DSUB (u_9,u_8,u_7);SUB0 (u_9,u_8,u_7);SUBU (u_9,u_8,u_7);AND (u_9,u_8,u_7);ANDI (u_8,u_7,u_15);OR (u_9,u_8,u_7);ORI (u_8,u_7,u_15);NOR (u_9,u_8,u_7);XOR (u_9,u_8,u_7);XORI (u_8,u_7,u_15);LUI (u_7,u_6);DSLL (u_9,u_8,u_7);DSLL32 (u_9,u_8,u_7);DSLLV (u_9,u_8,u_7);DSRA (u_9,u_8,u_7);DSRA32 (u_9,u_8,u_7);DSRAV (u_9,u_8,u_7);DSRL (u_9,u_8,u_7);DSRL32 (u_9,u_8,u_7);DSRLV (u_9,u_8,u_7);SLL (u_9,u_8,u_7);SLLV (u_9,u_8,u_7);SRA (u_9,u_8,u_7);SRAV (u_9,u_8,u_7);SRL (u_9,u_8,u_7);SRLV (u_9,u_8,u_7);SLT (u_9,u_8,u_7);SLTI (u_8,u_7,u_15);SLTU (u_9,u_8,u_7);SLTIU (u_8,u_7,u_15);MOVN (u_9,u_8,u_7);MOVZ (u_9,u_8,u_7);MFHI u_7;MFLO u_7;MTHI u_7;MTLO u_7;MUL (u_9,u_8,u_7);MULT (u_8,u_7);MULTU (u_8,u_7);DMULT (u_8,u_7);DMULTU (u_8,u_7);MADD (u_8,u_7);MADDU (u_8,u_7);MSUB (u_8,u_7);MSUBU (u_8,u_7);DIV0 (u_8,u_7);DIVU (u_8,u_7);DDIV (u_8,u_7);DDIVU (u_8,u_7);J u_16;JAL u_16;JR u_7;JALR (u_8,u_7);BEQ (u_8,u_7,u_6,u_5,u_4);BCMPZ (u_7,u_6,u_2,u_5,u_4);SYSCALL u_11;BREAK u_11;WAIT u_11;TRAPREG (u_8,u_7,u_2);TRAPIMM (u_7,u_6,u_2);Load (u_3,u_5,u_4,u_8,u_7,u_6);Store (u_3,u_4,u_8,u_7,u_6);LWL (u_8,u_7,u_15);LWR (u_8,u_7,u_15);SWL (u_8,u_7,u_15);SWR (u_8,u_7,u_15);LDL (u_8,u_7,u_15);LDR (u_8,u_7,u_15);SDL (u_8,u_7,u_15);SDR (u_8,u_7,u_15);CACHE (u_8,u_7,u_15);SYNC u_11;MFC0 (u_8,u_7,u_12,u_4);HCF u_11;MTC0 (u_8,u_7,u_12,u_4);TLBWI u_11;TLBWR u_11;TLBR u_11;TLBP u_11;RDHWR (u_8,u_7);ERET u_11;CGetPerm (u_8,u_7);CGetType (u_8,u_7);CGetBase (u_8,u_7);CGetLen (u_8,u_7);CGetTag (u_8,u_7);CGetSealed (u_8,u_7);CGetOffset (u_8,u_7);CGetAddr (u_8,u_7);CGetPCC u_7;CGetPCCSetOffset (u_8,u_7);CGetCause u_7;CSetCause u_7;CReadHwr (u_8,u_7);CWriteHwr (u_8,u_7);CAndPerm (u_9,u_8,u_7);CToPtr (u_9,u_8,u_7);CSub (u_9,u_8,u_7);CPtrCmp (u_9,u_8,u_7,u_0);CIncOffset (u_9,u_8,u_7);CIncOffsetImmediate (u_8,u_7,u_14);CSetOffset (u_9,u_8,u_7);CSetBounds (u_9,u_8,u_7);CSetBoundsImmediate (u_8,u_7,u_14);CSetBoundsExact (u_9,u_8,u_7);CClearTag (u_8,u_7);CMOVX (u_9,u_8,u_7,u_4);ClearRegs (u_1,u_15);CFromPtr (u_9,u_8,u_7);CBuildCap (u_9,u_8,u_7);CCopyType (u_9,u_8,u_7);CCheckPerm (u_8,u_7);CCheckType (u_8,u_7);CTestSubset (u_9,u_8,u_7);CSeal (u_9,u_8,u_7);CCSeal (u_9,u_8,u_7);CUnseal (u_9,u_8,u_7);CCall (u_8,u_7,u_14);CReturn u_11;CBX (u_7,u_15,u_4);CBZ (u_7,u_15,u_4);CJALR (u_8,u_7,u_4);CLoad (u_9,u_8,u_7,u_13,u_5,u_3,u_4);CStore (u_10,u_9,u_8,u_7,u_13,u_3,u_4);CSC (u_10,u_9,u_8,u_7,u_14,u_4);CLC (u_9,u_8,u_7,u_15,u_4);C2Dump u_7;RI u_11])))))))))))))))))))`;
 
 
 (*val execute : ast -> M unit*)
@@ -3527,38 +3504,34 @@ val _ = Define `
 (*val decode : mword ty32 -> maybe ast*)
 
 val _ = Define `
-((DDC:(5)words$word)=  ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))`;
-
-
-val _ = Define `
-((IDC:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))`;
+((IDCNO:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))`;
 
 
 val _ = Define `
-((KR1C:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))`;
+((KR1CNO:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))`;
 
 
 val _ = Define `
-((KR2C:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))`;
+((KR2CNO:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))`;
 
 
 val _ = Define `
-((KCC:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))`;
+((KCCNO:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))`;
 
 
 val _ = Define `
-((KDC:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))`;
+((KDCNO:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))`;
 
 
 val _ = Define `
-((EPCC:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))`;
+((EPCCNO:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))`;
 
 
 val _ = Define `
 ((CapRegs:(((regstate),(register_value),(CapReg))register_ref)list)=
    ([C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref;
    C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref;C10_ref;C09_ref;C08_ref;
-   C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;C00_ref]))`;
+   C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;DDC_ref]))`;
 
 
 val _ = Define `
@@ -3571,54 +3544,74 @@ val _ = Define `
 
 (*
 This function reads a given capability register and returns its contents converted to a CapStruct.
+If the argument is zero then the null capability is returned.
 *)
 (*val readCapReg : mword ty5 -> M CapStruct*)
 
 val _ = Define `
- ((readCapReg:(5)words$word ->(regstate)state_monad$sequential_state ->(((CapStruct),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) n=
-    (let i = (lem$w2ui n) in state_monad$bindS
-   (state_monad$read_regS ((access_list_dec CapRegs i  : (regstate, register_value, ( 257 words$word)) register_ref))
+ ((readCapReg:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((CapStruct),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n=
+    (if (((n = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then sail2_state_monad$returnS null_cap
+   else
+     let i = (lem$w2ui n) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS ((access_list_dec CapRegs i  : (regstate, register_value, ( 257 words$word)) register_ref))
+       : ( 257 words$word) M) (\ (w__0 :  257 words$word) . 
+     sail2_state_monad$returnS ((capRegToCapStruct w__0)))))`;
+
+
+(*
+This is the same as readCapReg except that when the argument is zero the value of DDC is returned 
+instead of the null capability. This is used for instructions that expect an address, where using
+null would always generate an exception.
+*)
+(*val readCapRegDDC : mword ty5 -> M CapStruct*)
+
+val _ = Define `
+ ((readCapRegDDC:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((CapStruct),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n=
+    (let i = (lem$w2ui n) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS ((access_list_dec CapRegs i  : (regstate, register_value, ( 257 words$word)) register_ref))
      : ( 257 words$word) M) (\ (w__0 :  257 words$word) . 
-   state_monad$returnS ((capRegToCapStruct w__0)))))`;
+   sail2_state_monad$returnS ((capRegToCapStruct w__0)))))`;
 
 
 (*val writeCapReg : mword ty5 -> CapStruct -> M unit*)
 
 val _ = Define `
- ((writeCapReg:(5)words$word -> CapStruct ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) n cap=
-    (let i = (lem$w2ui n) in
-   state_monad$write_regS
-     ((access_list_dec CapRegs i  : (regstate, register_value, ( 257 words$word)) register_ref))
-     ((capStructToCapReg cap  :  257 words$word))))`;
+ ((writeCapReg:(5)words$word -> CapStruct ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n cap=
+    (if (((n = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then sail2_state_monad$returnS () 
+   else
+     let i = (lem$w2ui n) in
+     sail2_state_monad$write_regS
+       ((access_list_dec CapRegs i  : (regstate, register_value, ( 257 words$word)) register_ref))
+       ((capStructToCapReg cap  :  257 words$word))))`;
 
 
 (*val CapEx_of_num : integer -> CapEx*)
 
 val _ = Define `
  ((CapEx_of_num:int -> CapEx) arg_=
-    (let l__32 = arg_ in
-   if (((l__32 = (( 0 : int):ii)))) then CapEx_None
-   else if (((l__32 = (( 1 : int):ii)))) then CapEx_LengthViolation
-   else if (((l__32 = (( 2 : int):ii)))) then CapEx_TagViolation
-   else if (((l__32 = (( 3 : int):ii)))) then CapEx_SealViolation
-   else if (((l__32 = (( 4 : int):ii)))) then CapEx_TypeViolation
-   else if (((l__32 = (( 5 : int):ii)))) then CapEx_CallTrap
-   else if (((l__32 = (( 6 : int):ii)))) then CapEx_ReturnTrap
-   else if (((l__32 = (( 7 : int):ii)))) then CapEx_TSSUnderFlow
-   else if (((l__32 = (( 8 : int):ii)))) then CapEx_UserDefViolation
-   else if (((l__32 = (( 9 : int):ii)))) then CapEx_TLBNoStoreCap
-   else if (((l__32 = (( 10 : int):ii)))) then CapEx_InexactBounds
-   else if (((l__32 = (( 11 : int):ii)))) then CapEx_GlobalViolation
-   else if (((l__32 = (( 12 : int):ii)))) then CapEx_PermitExecuteViolation
-   else if (((l__32 = (( 13 : int):ii)))) then CapEx_PermitLoadViolation
-   else if (((l__32 = (( 14 : int):ii)))) then CapEx_PermitStoreViolation
-   else if (((l__32 = (( 15 : int):ii)))) then CapEx_PermitLoadCapViolation
-   else if (((l__32 = (( 16 : int):ii)))) then CapEx_PermitStoreCapViolation
-   else if (((l__32 = (( 17 : int):ii)))) then CapEx_PermitStoreLocalCapViolation
-   else if (((l__32 = (( 18 : int):ii)))) then CapEx_PermitSealViolation
-   else if (((l__32 = (( 19 : int):ii)))) then CapEx_AccessSystemRegsViolation
-   else if (((l__32 = (( 20 : int):ii)))) then CapEx_PermitCCallViolation
-   else if (((l__32 = (( 21 : int):ii)))) then CapEx_AccessCCallIDCViolation
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CapEx_None
+   else if (((p0_ = (( 1 : int):ii)))) then CapEx_LengthViolation
+   else if (((p0_ = (( 2 : int):ii)))) then CapEx_TagViolation
+   else if (((p0_ = (( 3 : int):ii)))) then CapEx_SealViolation
+   else if (((p0_ = (( 4 : int):ii)))) then CapEx_TypeViolation
+   else if (((p0_ = (( 5 : int):ii)))) then CapEx_CallTrap
+   else if (((p0_ = (( 6 : int):ii)))) then CapEx_ReturnTrap
+   else if (((p0_ = (( 7 : int):ii)))) then CapEx_TSSUnderFlow
+   else if (((p0_ = (( 8 : int):ii)))) then CapEx_UserDefViolation
+   else if (((p0_ = (( 9 : int):ii)))) then CapEx_TLBNoStoreCap
+   else if (((p0_ = (( 10 : int):ii)))) then CapEx_InexactBounds
+   else if (((p0_ = (( 11 : int):ii)))) then CapEx_GlobalViolation
+   else if (((p0_ = (( 12 : int):ii)))) then CapEx_PermitExecuteViolation
+   else if (((p0_ = (( 13 : int):ii)))) then CapEx_PermitLoadViolation
+   else if (((p0_ = (( 14 : int):ii)))) then CapEx_PermitStoreViolation
+   else if (((p0_ = (( 15 : int):ii)))) then CapEx_PermitLoadCapViolation
+   else if (((p0_ = (( 16 : int):ii)))) then CapEx_PermitStoreCapViolation
+   else if (((p0_ = (( 17 : int):ii)))) then CapEx_PermitStoreLocalCapViolation
+   else if (((p0_ = (( 18 : int):ii)))) then CapEx_PermitSealViolation
+   else if (((p0_ = (( 19 : int):ii)))) then CapEx_AccessSystemRegsViolation
+   else if (((p0_ = (( 20 : int):ii)))) then CapEx_PermitCCallViolation
+   else if (((p0_ = (( 21 : int):ii)))) then CapEx_AccessCCallIDCViolation
    else CapEx_PermitUnsealViolation))`;
 
 
@@ -3656,8 +3649,8 @@ val _ = Define `
 (*val undefined_CapEx : unit -> M CapEx*)
 
 val _ = Define `
- ((undefined_CapEx:unit ->(regstate)state_monad$sequential_state ->(((CapEx),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =
-    (internal_pick
+ ((undefined_CapEx:unit ->(regstate)sail2_state_monad$sequential_state ->(((CapEx),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
      [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation]))`;
 
 
@@ -3695,87 +3688,127 @@ val _ = Define `
 (*val undefined_CapCauseReg : unit -> M CapCauseReg*)
 
 val _ = Define `
- ((undefined_CapCauseReg:unit ->(regstate)state_monad$sequential_state ->(((CapCauseReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
+ ((undefined_CapCauseReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((CapCauseReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__0 :  16 words$word) . 
-   internal_pick [Mk_CapCauseReg w__0])))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (w__0 :  16 words$word) . 
+   sail2_state_monad$returnS (<| CapCauseReg_CapCauseReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_CapCauseReg : mword ty16 -> CapCauseReg*)
+
+val _ = Define `
+ ((Mk_CapCauseReg:(16)words$word -> CapCauseReg) v=
+    (<| CapCauseReg_CapCauseReg_chunk_0 := ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) |>))`;
+
+
+val _ = Define `
+ ((get_CapCauseReg_bits:CapCauseReg ->(16)words$word) v=
+    ((subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)))`;
 
 
 val _ = Define `
- ((get_CapCauseReg:CapCauseReg ->(16)words$word) (Mk_CapCauseReg (v))=  v)`;
+ ((set_CapCauseReg_bits:((regstate),(register_value),(CapCauseReg))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CapCauseReg_CapCauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+            :  16 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((set_CapCauseReg:((regstate),(register_value),(CapCauseReg))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_CapCauseReg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_CapCauseReg_bits:CapCauseReg ->(16)words$word -> CapCauseReg) v x=
+    ((v with<|
+     CapCauseReg_CapCauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+          :  16 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))=  ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
+ ((get_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word) v=
+    ((subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
 
 
 val _ = Define `
- ((set_CapCauseReg_ExcCode:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CapCauseReg) . 
-   let r = ((get_CapCauseReg w__0  :  16 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v  :  16 words$word)) in
-   state_monad$write_regS r_ref (Mk_CapCauseReg r))))`;
+ ((set_CapCauseReg_ExcCode:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CapCauseReg_CapCauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  16 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word -> CapCauseReg) (Mk_CapCauseReg (v)) x=
-    (Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x  :  16 words$word))))`;
+ ((update_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word -> CapCauseReg) v x=
+    ((v with<|
+     CapCauseReg_CapCauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  16 words$word))|>)))`;
 
 
 (*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*)
 
 val _ = Define `
- ((get_CapCauseReg_RegNum:CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+ ((get_CapCauseReg_RegNum:CapCauseReg ->(8)words$word) v=
+    ((subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
 
 
 (*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((set_CapCauseReg_RegNum:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : CapCauseReg) . 
-   let r = ((get_CapCauseReg w__0  :  16 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v  :  16 words$word)) in
-   state_monad$write_regS r_ref (Mk_CapCauseReg r))))`;
+ ((set_CapCauseReg_RegNum:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CapCauseReg_CapCauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CapCauseReg_CapCauseReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  16 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*)
 
 val _ = Define `
- ((update_CapCauseReg_RegNum:CapCauseReg ->(8)words$word -> CapCauseReg) (Mk_CapCauseReg (v)) x=
-    (Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x  :  16 words$word))))`;
+ ((update_CapCauseReg_RegNum:CapCauseReg ->(8)words$word -> CapCauseReg) v x=
+    ((v with<|
+     CapCauseReg_CapCauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  16 words$word))|>)))`;
 
 
 (*val execute_branch_pcc : CapStruct -> M unit*)
 
 val _ = Define `
- ((execute_branch_pcc:CapStruct ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) newPCC=  (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS
+ ((execute_branch_pcc:CapStruct ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) newPCC=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      delayedPC_ref
      ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ((getCapOffset newPCC))  :  64 words$word)))
-   (state_monad$write_regS delayedPCC_ref ((capStructToCapReg newPCC  :  257 words$word))))
-   (state_monad$write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
+   (sail2_state_monad$write_regS delayedPCC_ref ((capStructToCapReg newPCC  :  257 words$word))))
+   (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
 
 
 (*val ERETHook : unit -> M unit*)
 
 val _ = Define `
- ((ERETHook:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS C31_ref  : ( 257 words$word) M) (\ (w__0 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS nextPCC_ref w__0)
-   (state_monad$read_regS C31_ref  : ( 257 words$word) M)) (\ (w__1 : CapReg) .  state_monad$write_regS delayedPCC_ref w__1))))`;
+ ((ERETHook:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS EPCC_ref  : ( 257 words$word) M) (\ (w__0 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPCC_ref w__0)
+   (sail2_state_monad$read_regS EPCC_ref  : ( 257 words$word) M)) (\ (w__1 : CapReg) .  sail2_state_monad$write_regS delayedPCC_ref w__1))))`;
 
 
 (*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*)
 
 val _ = Define `
- ((raise_c2_exception8:CapEx ->(8)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx regnum=  (state_monad$seqS (state_monad$seqS
+ ((raise_c2_exception8:CapEx ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) capEx regnum=  (sail2_state_monad$seqS (sail2_state_monad$seqS
    (set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx  :  8 words$word)))
    (set_CapCauseReg_RegNum CapCause_ref regnum))
    (let mipsEx =
@@ -3787,9 +3820,9 @@ val _ = Define `
 (*val raise_c2_exception : forall 'o. CapEx -> mword ty5 -> M 'o*)
 
 val _ = Define `
- ((raise_c2_exception:CapEx ->(5)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx regnum=
+ ((raise_c2_exception:CapEx ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) capEx regnum=
     (let reg8 = ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word) regnum  :  8 words$word)) in
-   if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDC)))))) then
+   if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDCNO)))))) then
      raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8
    else raise_c2_exception8 capEx reg8))`;
 
@@ -3797,17 +3830,17 @@ val _ = Define `
 (*val raise_c2_exception_noreg : forall 'o. CapEx -> M 'o*)
 
 val _ = Define `
- ((raise_c2_exception_noreg:CapEx ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx=
+ ((raise_c2_exception_noreg:CapEx ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) capEx=
     (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1]  :  8 words$word)))`;
 
 
 (*val pcc_access_system_regs : unit -> M bool*)
 
 val _ = Define `
- ((pcc_access_system_regs:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__0 :  257 words$word) . 
+ ((pcc_access_system_regs:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__0 :  257 words$word) . 
    let pcc = (capRegToCapStruct w__0) in
-   state_monad$returnS pcc.CapStruct_access_system_regs)))`;
+   sail2_state_monad$returnS pcc.CapStruct_access_system_regs)))`;
 
 
 (*
@@ -3816,57 +3849,57 @@ The following function should be called before reading or writing any capability
 (*val register_inaccessible : mword ty5 -> M bool*)
 
 val _ = Define `
- ((register_inaccessible:(5)words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r=
-    (state$or_boolS
-     (state$and_boolS (state_monad$returnS (((r = IDC))))
-        ( state_monad$bindS(state_monad$read_regS inCCallDelay_ref  : ( 1 words$word) M) (\ (w__0 :  1 words$word) . 
-         state_monad$returnS ((bits_to_bool w__0)))))
-     (state$and_boolS
-        (state_monad$returnS ((((((r = KR1C))) \/ ((((((r = KR2C))) \/ ((((((r = KDC))) \/ ((((((r = KCC))) \/ (((r = EPCC))))))))))))))))
-        ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__2 : bool) .  state_monad$returnS ((~ w__2)))))))`;
+ ((register_inaccessible:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r=
+    (sail2_state$or_boolS
+     (sail2_state$and_boolS (sail2_state_monad$returnS (((r = IDCNO))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS inCCallDelay_ref  : ( 1 words$word) M) (\ (w__0 :  1 words$word) . 
+         sail2_state_monad$returnS ((bits_to_bool w__0)))))
+     (sail2_state$and_boolS
+        (sail2_state_monad$returnS ((((((r = KR1CNO))) \/ ((((((r = KR2CNO))) \/ ((((((r = KDCNO))) \/ ((((((r = KCCNO))) \/ (((r = EPCCNO))))))))))))))))
+        ( sail2_state_monad$bindS(pcc_access_system_regs () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))))`;
 
 
 (*val MEMr_tagged : mword ty64 -> M (bool * mword ty256)*)
 
 val _ = Define `
- ((MEMr_tagged:(64)words$word ->(regstate)state_monad$sequential_state ->(((bool#(256)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr=  (state_monad$bindS (state_monad$seqS
-   (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
-   (read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag .  state_monad$bindS
-   (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size  : ( 256 words$word) M) (\ data . 
-   state_monad$returnS (tag, (reverse_endianness data  :  256 words$word))))))`;
+ ((MEMr_tagged:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(256)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
+   (read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr)) (\ tag .  sail2_state_monad$bindS
+   (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size  : ( 256 words$word) M) (\ data . 
+   sail2_state_monad$returnS (tag, (reverse_endianness data  :  256 words$word))))))`;
 
 
 (*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*)
 
 val _ = Define `
- ((MEMr_tagged_reserve:(64)words$word ->(regstate)state_monad$sequential_state ->(((bool#(256)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr=  (state_monad$bindS (state_monad$seqS
-   (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
-   (read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag .  state_monad$bindS
-   (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size  : ( 256 words$word) M) (\ data . 
-   state_monad$returnS (tag, (reverse_endianness data  :  256 words$word))))))`;
+ ((MEMr_tagged_reserve:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(256)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
+   (read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr)) (\ tag .  sail2_state_monad$bindS
+   (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size  : ( 256 words$word) M) (\ data . 
+   sail2_state_monad$returnS (tag, (reverse_endianness data  :  256 words$word))))))`;
 
 
 (*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*)
 
 val _ = Define `
- ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr tag data=  (state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
-   (MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size))
-   (MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  :  256 words$word)))) (write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag)))`;
+ ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr tag data=  (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
+   (MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size))
+   (MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  :  256 words$word)))) (write_tag_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag)))`;
 
 
 (*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*)
 
 val _ = Define `
- ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr tag data=  (state_monad$bindS (state_monad$seqS (state_monad$seqS
-   (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
+ ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr tag data=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "")
    (MEMea_conditional 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size))
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size))
    (MEMval_conditional 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  :  256 words$word)))) (\ success .  state_monad$seqS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  :  256 words$word)))) (\ success .  sail2_state_monad$seqS
    (if success then write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else state_monad$returnS () ) (state_monad$returnS success))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag else sail2_state_monad$returnS () ) (sail2_state_monad$returnS success))))`;
 
 
 val _ = Define `
@@ -3878,32 +3911,32 @@ val _ = Define `
 (*val MEMw_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*)
 
 val _ = Define `
- ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1 data=
+ ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data=
     (let ledata = ((reverse_endianness data  :  'p8_times_n_ words$word)) in
    if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-            :  64 words$word)))) then state_monad$seqS
-     (state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))
-     (state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B1]  :  1 words$word))
-   else state_monad$seqS (state_monad$seqS (state_monad$seqS
-     (state_monad$assert_expS (((((and_vec addr cap_addr_mask  :  64 words$word)) = ((and_vec
+            :  64 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))
+     (sail2_state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B1]  :  1 words$word))
+   else sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS (((((and_vec addr cap_addr_mask  :  64 words$word)) = ((and_vec
                         ((add_vec addr
                             ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself))
                                 ((size1 - (( 1 : int):ii)))
                                :  64 words$word))
                            :  64 words$word)) cap_addr_mask
                        :  64 words$word))))) "")
-     (MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1))
-     (MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  :  64 words$word)) F)))`;
+     (MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1))
+     (MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  :  64 words$word)) F)))`;
 
 
 (*val MEMw_conditional_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*)
 
 val _ = Define `
- ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1 data=  (state_monad$bindS (state_monad$seqS (state_monad$seqS
-   (state_monad$assert_expS (((((and_vec addr cap_addr_mask  :  64 words$word)) = ((and_vec
+ ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$assert_expS (((((and_vec addr cap_addr_mask  :  64 words$word)) = ((and_vec
                       ((add_vec addr
                           ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself))
                               ((size1 - (( 1 : int):ii)))
@@ -3911,53 +3944,93 @@ val _ = Define `
                          :  64 words$word)) cap_addr_mask
                      :  64 words$word))))) "")
    (MEMea_conditional 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1))
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1))
    (MEMval_conditional 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data  :  'p8_times_n_ words$word)))) (\ success .  state_monad$seqS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data  :  'p8_times_n_ words$word)))) (\ success .  sail2_state_monad$seqS
    (if success then write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  :  64 words$word)) F
-    else state_monad$returnS () )
-   (state_monad$returnS success))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  :  64 words$word)) F
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$returnS success))))`;
 
 
-(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*)
+(*val checkDDCPerms : CapStruct -> MemAccessType -> M unit*)
 
 val _ = Define `
- ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr accessType width=
-    (let capno = ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)) in state_monad$bindS
-   (readCapReg capno) (\ cap .  state_monad$seqS (state_monad$seqS
-   (if ((~ cap.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation capno
-    else if cap.CapStruct_sealed then raise_c2_exception CapEx_SealViolation capno
-    else state_monad$returnS () )
+ ((checkDDCPerms:CapStruct -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (ddc : CapStruct) (accessType : MemAccessType)=  (sail2_state_monad$seqS
+   (if ((~ ddc.CapStruct_tag)) then
+      raise_c2_exception CapEx_TagViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+    else if ddc.CapStruct_sealed then
+      raise_c2_exception CapEx_SealViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+    else sail2_state_monad$returnS () )
    (case accessType of
-     Instruction =>
-      if ((~ cap.CapStruct_permit_execute)) then
-        raise_c2_exception CapEx_PermitExecuteViolation capno
-      else state_monad$returnS () 
+     Instruction => sail2_state_monad$assert_expS F ""
    | LoadData =>
-      if ((~ cap.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation capno
-      else state_monad$returnS () 
+      if ((~ ddc.CapStruct_permit_load)) then
+        raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+      else sail2_state_monad$returnS () 
    | StoreData =>
-      if ((~ cap.CapStruct_permit_store)) then raise_c2_exception CapEx_PermitStoreViolation capno
-      else state_monad$returnS () 
-   ))
-   (let cursor = (getCapCursor cap) in
+      if ((~ ddc.CapStruct_permit_store)) then
+        raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+      else sail2_state_monad$returnS () 
+   )))`;
+
+
+(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*)
+
+val _ = Define `
+ ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr accessType width=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DDC_ref  : ( 257 words$word) M) (\ (w__0 :  257 words$word) . 
+   let ddc = (capRegToCapStruct w__0) in sail2_state_monad$seqS
+   (checkDDCPerms ddc accessType)
+   (let cursor = (getCapCursor ddc) in
    let vAddr = (((cursor + ((lem$w2ui addr)))) % ((pow2 (( 64 : int):ii)))) in
    let size1 = (wordWidthBytes width) in
-   let base = (getCapBase cap) in
-   let top = (getCapTop cap) in
+   let base = (getCapBase ddc) in
+   let top = (getCapTop ddc) in
    if ((((vAddr + size1)) > top)) then
-     (raise_c2_exception CapEx_LengthViolation capno  : ( 64 words$word) M)
-   else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno  : ( 64 words$word) M)
-   else state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) vAddr  :  64 words$word))))))`;
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+       : ( 64 words$word) M)
+   else if ((vAddr < base)) then
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+       : ( 64 words$word) M)
+   else sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) vAddr  :  64 words$word))))))`;
+
+
+(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> M (mword ty64)*)
+
+val _ = Define `
+ ((addrWrapperUnaligned:(64)words$word -> MemAccessType -> WordTypeUnaligned ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr accessType width=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS DDC_ref  : ( 257 words$word) M) (\ (w__0 :  257 words$word) . 
+   let ddc = (capRegToCapStruct w__0) in sail2_state_monad$seqS
+   (checkDDCPerms ddc accessType)
+   (let cursor = (getCapCursor ddc) in
+   let vAddr = (((cursor + ((lem$w2ui addr)))) % ((pow2 (( 64 : int):ii)))) in
+   let woffset = (vAddr % (( 4 : int):ii)) in
+   let doffset = (vAddr % (( 8 : int):ii)) in
+   let ((waddr : ii), (size1 : ii)) =
+     ((case width of
+       WL => (vAddr, (( 4 : int):ii) - woffset)
+     | WR => (vAddr - woffset, woffset + (( 1 : int):ii))
+     | DL => (vAddr, (( 8 : int):ii) - doffset)
+     | DR => (vAddr - doffset, doffset + (( 1 : int):ii))
+     )) in
+   let base = (getCapBase ddc) in
+   let top = (getCapTop ddc) in
+   if ((((waddr + size1)) > top)) then
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+       : ( 64 words$word) M)
+   else if ((waddr < base)) then
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+       : ( 64 words$word) M)
+   else sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) vAddr  :  64 words$word))))))`;
 
 
 (*val TranslatePC : mword ty64 -> M (mword ty64)*)
 
 val _ = Define `
- ((TranslatePC:(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr=  (state_monad$bindS (state_monad$seqS
+ ((TranslatePC:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (incrementCP0Count () )
-   (state_monad$read_regS PCC_ref  : ( 257 words$word) M)) (\ (w__0 :  257 words$word) . 
+   (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M)) (\ (w__0 :  257 words$word) . 
    let pcc = (capRegToCapStruct w__0) in
    let base = (getCapBase pcc) in
    let top = (getCapTop pcc) in
@@ -3986,75 +4059,79 @@ capability context for processes that use capabilities.
 (*val checkCP2usable : unit -> M unit*)
 
 val _ = Define `
- ((checkCP2usable:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
-   if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 2 : int):ii))))))) then state_monad$seqS
+ ((checkCP2usable:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+   if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 2 : int):ii))))))) then sail2_state_monad$seqS
      (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0]  :  2 words$word)) (SignalException CpU)
-   else state_monad$returnS () )))`;
-
-
-val _ = Define `
- ((init_cp2_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =
-    (let defaultBits = ((capStructToCapReg default_cap  :  257 words$word)) in state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS PCC_ref defaultBits)
-   (state_monad$write_regS nextPCC_ref defaultBits))
-   (state_monad$write_regS delayedPCC_ref defaultBits))
-   (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
+   else sail2_state_monad$returnS () )))`;
+
+
+val _ = Define `
+ ((init_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (let defaultBits = ((capStructToCapReg default_cap  :  257 words$word)) in
+   let nullBits = ((capStructToCapReg null_cap  :  257 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PCC_ref defaultBits)
+   (sail2_state_monad$write_regS nextPCC_ref defaultBits))
+   (sail2_state_monad$write_regS delayedPCC_ref defaultBits))
+   (sail2_state_monad$write_regS DDC_ref defaultBits))
+   (sail2_state_monad$write_regS KCC_ref defaultBits))
+   (sail2_state_monad$write_regS EPCC_ref defaultBits))
+   (sail2_state_monad$write_regS KDC_ref nullBits))
+   (sail2_state_monad$write_regS KR1C_ref nullBits))
+   (sail2_state_monad$write_regS KR2C_ref nullBits))
+   (sail2_state_monad$write_regS CTLSP_ref nullBits))
+   (sail2_state_monad$write_regS CTLSU_ref nullBits))
+   (sail2_state$foreachS (index_list (( 1 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
      (\ i unit_var . 
        let idx = ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) i  :  5 words$word)) in
-       writeCapReg idx default_cap))))`;
+       writeCapReg idx null_cap))))`;
 
 
 val _ = Define `
- ((cp2_next_pc:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS nextPCC_ref  : ( 257 words$word) M) (\ (w__0 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS PCC_ref w__0)
-   (state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M)) (\ (w__1 :  1 words$word) . 
-   if ((bits_to_bool w__1)) then state_monad$bindS
-     (state_monad$read_regS delayedPCC_ref  : ( 257 words$word) M) (\ (w__2 : CapReg) . 
-     state_monad$write_regS nextPCC_ref w__2)
-   else state_monad$write_regS inCCallDelay_ref (vec_of_bits [B0]  :  1 words$word)))))`;
+ ((cp2_next_pc:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS nextPCC_ref  : ( 257 words$word) M) (\ (w__0 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PCC_ref w__0)
+   (sail2_state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M)) (\ (w__1 :  1 words$word) . 
+   if ((bits_to_bool w__1)) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS delayedPCC_ref  : ( 257 words$word) M) (\ (w__2 : CapReg) . 
+     sail2_state_monad$write_regS nextPCC_ref w__2)
+   else sail2_state_monad$write_regS inCCallDelay_ref (vec_of_bits [B0]  :  1 words$word)))))`;
 
 
 (*val capToString : CapStruct -> M string*)
 
 val _ = Define `
- ((capToString:CapStruct ->(regstate)state_monad$sequential_state ->(((string),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cap=  (state_monad$seqS
+ ((capToString:CapStruct ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cap=  (sail2_state_monad$seqS
    (skip () )
-   (state_monad$returnS ((STRCAT " t:"
+   (sail2_state_monad$returnS ((STRCAT " t:"
               ((STRCAT (if cap.CapStruct_tag then "1" else "0")
                   ((STRCAT " s:"
                       ((STRCAT (if cap.CapStruct_sealed then "1" else "0")
                           ((STRCAT " perms:"
                               ((STRCAT
-                                  ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                  ((string_of_bits
                                       ((concat_vec (vec_of_bits [B0]  :  1 words$word)
                                           ((getCapPerms cap  :  31 words$word))
                                          :  32 words$word))))
                                   ((STRCAT " type:"
-                                      ((STRCAT ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict cap.CapStruct_otype))
+                                      ((STRCAT ((string_of_bits cap.CapStruct_otype))
                                           ((STRCAT " offset:"
                                               ((STRCAT
-                                                  ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                  ((string_of_bits
                                                       ((to_bits
                                                           ((make_the_value (( 64 : int):ii)  :  64 itself))
                                                           ((getCapOffset cap))
                                                          :  64 words$word))))
                                                   ((STRCAT " base:"
                                                       ((STRCAT
-                                                          ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                          ((string_of_bits
                                                               ((to_bits
                                                                   ((make_the_value (( 64 : int):ii)
                                                                      :  64 itself))
                                                                   ((getCapBase cap))
                                                                  :  64 words$word))))
                                                           ((STRCAT " length:"
-                                                              ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                              ((string_of_bits
                                                                   ((to_bits
                                                                       ((make_the_value (( 64 : int):ii)
                                                                          :  64 itself))
@@ -4064,94 +4141,118 @@ val _ = Define `
 
 
 val _ = Define `
- ((dump_cp2_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__0 :  257 words$word) .  state_monad$bindS
+ ((dump_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__0 :  257 words$word) .  sail2_state_monad$bindS
    (capToString ((capRegToCapStruct w__0))) (\ (w__1 : string) . 
-   let (_ : unit) = (prerr_endline ((STRCAT "DEBUG CAP PCC" w__1))) in
-   (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
-     (\ i unit_var .  state_monad$bindS
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP PCC" w__1))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
+     (\ i unit_var .  sail2_state_monad$bindS
        (readCapReg ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) i  :  5 words$word))) (\ (w__2 :
-         CapStruct) .  state_monad$bindS
+         CapStruct) .  sail2_state_monad$bindS
        (capToString w__2) (\ (w__3 : string) . 
-       state_monad$returnS (let _ =
-         (prerr_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int 
+       sail2_state_monad$returnS (let _ =
+         (print_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int 
   instance_Show_Show_Num_integer_dict i)) w__3))))) in
-       () )))))))))`;
+       () )))))
+   (sail2_state_monad$read_regS DDC_ref  : ( 257 words$word) M)) (\ (w__4 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__4))) (\ (w__5 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 00" w__5))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CTLSU_ref  : ( 257 words$word) M) (\ (w__6 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__6))) (\ (w__7 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 01" w__7))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CTLSP_ref  : ( 257 words$word) M) (\ (w__8 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__8))) (\ (w__9 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 08" w__9))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS KR1C_ref  : ( 257 words$word) M) (\ (w__10 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__10))) (\ (w__11 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 22" w__11))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS KR2C_ref  : ( 257 words$word) M) (\ (w__12 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__12))) (\ (w__13 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 23" w__13))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS KCC_ref  : ( 257 words$word) M) (\ (w__14 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__14))) (\ (w__15 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 29" w__15))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS KDC_ref  : ( 257 words$word) M) (\ (w__16 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__16))) (\ (w__17 : string) . 
+   let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 30" w__17))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS EPCC_ref  : ( 257 words$word) M) (\ (w__18 :  257 words$word) .  sail2_state_monad$bindS
+   (capToString ((capRegToCapStruct w__18))) (\ (w__19 : string) . 
+   sail2_state_monad$returnS ((print_endline ((STRCAT "DEBUG CAP HWREG 31" w__19))))))))))))))))))))))))`;
 
 
 (*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*)
 
 val _ = Define `
  ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign=
-    (if sign then (sign_extend1 (( 64 : int):ii) memResult  :  64 words$word)
-   else (zero_extend1 (( 64 : int):ii) memResult  :  64 words$word)))`;
+    (if sign then (mips_sign_extend (( 64 : int):ii) memResult  :  64 words$word)
+   else (mips_zero_extend (( 64 : int):ii) memResult  :  64 words$word)))`;
 
 
 (*val TLBWriteEntry : mword ty6 -> M unit*)
 
 val _ = Define `
- ((TLBWriteEntry:(6)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx=  (state_monad$bindS
-   (state_monad$read_regS TLBPageMask_ref  : ( 16 words$word) M) (\ pagemask . 
-   let b__0 = pagemask in state_monad$seqS
+ ((TLBWriteEntry:(6)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS TLBPageMask_ref  : ( 16 words$word) M) (\ pagemask . 
+   let b__0 = pagemask in sail2_state_monad$seqS
    (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word))))
     then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
-      state_monad$returnS () 
+      sail2_state_monad$returnS () 
     else SignalException MCheck)
    (let i = (lem$w2ui idx) in
-   let entry = (access_list_dec TLBEntries i) in state_monad$bindS (state_monad$seqS
+   let entry = (access_list_dec TLBEntries i) in sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_pagemask entry pagemask)
-   (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0  :  2 words$word)))
-   (state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1  :  27 words$word)))
-   (state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2  :  8 words$word)))
-   (state$and_boolS
-     ( state_monad$bindS(state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . 
-      state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3  :  1 words$word))))))
-     ( state_monad$bindS(state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . 
-      state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4  :  1 words$word)))))))) (\ (w__5 : bool) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
+   (sail2_state$and_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4  :  1 words$word)))))))) (\ (w__5 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
    (set_TLBEntry_g entry ((bool_to_bits w__5  :  1 words$word)))
    (set_TLBEntry_valid entry ((cast_unit_vec0 B1  :  1 words$word))))
-   (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8  :  24 words$word)))
-   (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9  :  3 words$word)))
-   (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14  :  24 words$word)))
-   (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15  :  3 words$word)))
-   (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16  :  1 words$word)))
-   (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . 
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . 
    set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17  :  1 words$word))))))))))))))))))))))`;
 
 
@@ -4521,10 +4622,6 @@ val _ = Define `
      let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
      let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
      SOME (BCMPZ (rs,imm,LE,F,T))
-   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
-                             B1;B1;B0;B0;B1;B1;B0;B0]
-                 :  32 words$word)))) then
-     SOME (SYSCALL_THREAD_START () )
    else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word))))))) then
      SOME (SYSCALL () )
    else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word))))))) then
@@ -4701,11 +4798,6 @@ val _ = Define `
      let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
      let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
      SOME (CACHE (base,op,imm))
-   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1]  :  6 words$word)))) then
-     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
-     let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
-     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
-     SOME (PREF (base,op,imm))
    else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 11 : int):ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
                      :  21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word))))))) then
      SOME (SYNC () )
@@ -5299,13 +5391,19 @@ val _ = Define `
      let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
      let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
      let (offset : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) in
-     SOME (CLC (cd,cb,rt,offset,F))
+     SOME (CLC (cd,cb,rt,(mips_sign_extend (( 16 : int):ii) offset  :  16 words$word),F))
    else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  11 words$word))))))) then
      let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
      let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
      SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;
-                                                                                B0;B0;B0;B0]
-                                                                    :  11 words$word),T))
+                                                                                B0;B0;B0;B0;B0;B0;B0;
+                                                                                B0;B0]
+                                                                    :  16 words$word),T))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1]  :  6 words$word)))) then
+     let (cd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),offset,F))
    else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  :  16 words$word)))))))
    then
      let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
@@ -5316,16 +5414,16 @@ val _ = Define `
 (*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+   wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
 
 
 (*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd ((xor_vec w__0 w__1  :  64 words$word))))))`;
 
@@ -5333,57 +5431,57 @@ val _ = Define `
 (*val execute_WAIT : unit -> M unit*)
 
 val _ = Define `
- ((execute_WAIT:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__121=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  state_monad$write_regS nextPC_ref w__0)))`;
+ ((execute_WAIT:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__19=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$write_regS nextPC_ref w__0)))`;
 
 
 (*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*)
 
 val _ = Define `
- ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt cmp=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rs_val .  state_monad$bindS
+ ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt cmp=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rs_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ rt_val . 
    let condition = (compare cmp rs_val rt_val) in
    if condition then SignalException Tr
-   else state_monad$returnS () ))))`;
+   else sail2_state_monad$returnS () ))))`;
 
 
 (*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*)
 
 val _ = Define `
- ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs imm cmp=  (state_monad$bindS
+ ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ rs_val . 
-   let (imm_val : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm  :  64 words$word)) in
+   let (imm_val : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word)) in
    let condition = (compare cmp rs_val imm_val) in
    if condition then SignalException Tr
-   else state_monad$returnS () )))`;
+   else sail2_state_monad$returnS () )))`;
 
 
 (*val execute_TLBWR : unit -> M unit*)
 
 val _ = Define `
- ((execute_TLBWR:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__125=  (state_monad$bindS (state_monad$seqS
+ ((execute_TLBWR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__23=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP0Access () )
-   (state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
+   (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
 
 
 (*val execute_TLBWI : unit -> M unit*)
 
 val _ = Define `
- ((execute_TLBWI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__124=  (state_monad$bindS (state_monad$seqS
+ ((execute_TLBWI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__22=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP0Access () )
-   (state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
+   (sail2_state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
 
 
 (*val execute_TLBR : unit -> M unit*)
 
 val _ = Define `
- ((execute_TLBR:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__126=  (state_monad$bindS (state_monad$seqS
+ ((execute_TLBR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__24=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP0Access () )
-   (state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . 
-   let i = (lem$w2ui w__0) in state_monad$bindS
-   (state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry .  state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry  :  16 words$word)))
+   (sail2_state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . 
+   let i = (lem$w2ui w__0) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry .  sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry  :  16 words$word)))
    (set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry  :  2 words$word))))
    (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry  :  27 words$word))))
    (set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry  :  8 words$word))))
@@ -5406,48 +5504,43 @@ val _ = Define `
 (*val execute_TLBP : unit -> M unit*)
 
 val _ = Define `
- ((execute_TLBP:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__127=  (state_monad$bindS (state_monad$seqS
+ ((execute_TLBP:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__25=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP0Access () )
-   (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) .  state_monad$bindS
-   (tlbSearch ((get_TLBEntryHiReg w__0  :  64 words$word))  : ( ( 6 words$word)option) M) (\ result . 
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) .  sail2_state_monad$bindS
+   (tlbSearch ((get_TLBEntryHiReg_bits w__0  :  64 words$word))  : ( ( 6 words$word)option) M) (\ result . 
    (case result of
-     SOME (idx) => state_monad$seqS
-      (state_monad$write_regS TLBProbe_ref (vec_of_bits [B0]  :  1 words$word)) (state_monad$write_regS TLBIndex_ref idx)
-   | NONE => state_monad$seqS
-      (state_monad$write_regS TLBProbe_ref (vec_of_bits [B1]  :  1 words$word))
-      (state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))
+     SOME (idx) => sail2_state_monad$seqS
+      (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B0]  :  1 words$word)) (sail2_state_monad$write_regS TLBIndex_ref idx)
+   | NONE => sail2_state_monad$seqS
+      (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B1]  :  1 words$word))
+      (sail2_state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))
    )))))`;
 
 
 (*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) width conditional base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
+ ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width conditional base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
       StoreData width
-     : ( 64 words$word) M) (\ (vAddr : 64 bits) .  state_monad$bindS
+     : ( 64 words$word) M) (\ (vAddr : 64 bits) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ rt_val . 
    if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr . 
-     if conditional then state_monad$bindS
-       (state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  state_monad$bindS
+     if conditional then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS
        (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then
           (case width of
-            B =>
-             MEMw_conditional_wrapper pAddr (( 1 : int):ii)
-               ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
-          | H =>
-             MEMw_conditional_wrapper pAddr (( 2 : int):ii)
-               ((subrange_vec_dec rt_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
-          | W0 =>
+            W0 =>
              MEMw_conditional_wrapper pAddr (( 4 : int):ii)
                ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
           | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rt_val
+          | _ => sail2_state_monad$throwS (Error_internal_error () )
           )
-        else state_monad$returnS F) (\ (success : bool) . 
-       wGPR rt ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+        else sail2_state_monad$returnS F) (\ (success : bool) . 
+       wGPR rt ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
      else
        (case width of
          B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
@@ -5457,37 +5550,31 @@ val _ = Define `
        )))))))`;
 
 
-(*val execute_SYSCALL_THREAD_START : unit -> unit*)
-
-val _ = Define `
- ((execute_SYSCALL_THREAD_START:unit -> unit) g__117=  () )`;
-
-
 (*val execute_SYSCALL : unit -> M unit*)
 
 val _ = Define `
- ((execute_SYSCALL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__119=  (SignalException Sys))`;
+ ((execute_SYSCALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__17=  (SignalException Sys))`;
 
 
 (*val execute_SYNC : unit -> M unit*)
 
 val _ = Define `
- ((execute_SYNC:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__122=  (MEM_sync () ))`;
+ ((execute_SYNC:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__20=  (MEM_sync () ))`;
 
 
 (*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
-      StoreData W0
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
+ ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData WR
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
    (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr . 
    let wordAddr =
      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word))
         (vec_of_bits [B0;B0]  :  2 words$word)
-       :  64 words$word)) in state_monad$bindS
+       :  64 words$word)) in sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__12 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
    if (((b__12 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
@@ -5502,12 +5589,12 @@ val _ = Define `
 (*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
-      StoreData W0
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData WL
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__8 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
    if (((b__8 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
@@ -5522,15 +5609,15 @@ val _ = Define `
 (*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ opA .  state_monad$bindS
+ ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ opB . 
-   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
    else
      wGPR rd
-       ((sign_extend1 (( 64 : int):ii)
+       ((mips_sign_extend (( 64 : int):ii)
            ((sub_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
               :  32 words$word))
@@ -5540,99 +5627,101 @@ val _ = Define `
 (*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ opA .  state_monad$bindS
+ ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ opB . 
-   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
    else
      let (temp33 : 33 bits) =
        ((sub_vec
-          ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  33 words$word))
-          ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
          :  33 words$word)) in
      if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):ii)))))
             ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):ii))))))) then
        SignalException Ov
      else
        wGPR rd
-         ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+         ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             :  64 words$word))))))`;
 
 
 (*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ temp .  state_monad$bindS
+ ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
-   if ((NotWordVal temp)) then state_monad$bindS
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
    else
-     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
      (shift_bits_right 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
-     wGPR rd ((sign_extend1 (( 64 : int):ii) w__2  :  64 words$word)))))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2  :  64 words$word)))))))`;
 
 
 (*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
+ ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ temp . 
-   if ((NotWordVal temp)) then state_monad$bindS
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
    else
-     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
      (shift_bits_right 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
-     wGPR rd ((sign_extend1 (( 64 : int):ii) w__1  :  64 words$word))))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1  :  64 words$word))))))`;
 
 
 (*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ temp .  state_monad$bindS
+ ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
-   if ((NotWordVal temp)) then state_monad$bindS
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
    else
-     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
      (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
-     wGPR rd ((sign_extend1 (( 64 : int):ii) w__2  :  64 words$word)))))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2  :  64 words$word)))))))`;
 
 
 (*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
+ ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ temp . 
-   if ((NotWordVal temp)) then state_monad$bindS
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
    else
-     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
      (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
-     wGPR rd ((sign_extend1 (( 64 : int):ii) w__1  :  64 words$word))))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1  :  64 words$word))))))`;
 
 
 (*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rs_val .  state_monad$bindS
+ ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rs_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ rt_val . 
    wGPR rd
-     ((zero_extend1 (( 64 : int):ii)
+     ((mips_zero_extend (( 64 : int):ii)
          (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1]  :  1 words$word)
           else (vec_of_bits [B0]  :  1 words$word))
         :  64 words$word))))))`;
@@ -5641,11 +5730,11 @@ val _ = Define `
 (*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ rs_val . 
-   let (immext : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm  :  64 words$word)) in
+   let (immext : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word)) in
    wGPR rt
-     ((zero_extend1 (( 64 : int):ii)
+     ((mips_zero_extend (( 64 : int):ii)
          (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1]  :  1 words$word)
           else (vec_of_bits [B0]  :  1 words$word))
         :  64 words$word)))))`;
@@ -5654,12 +5743,12 @@ val _ = Define `
 (*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=
-    (let imm_val = (integer_word$w2i imm) in state_monad$bindS
+ ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=
+    (let imm_val = (integer_word$w2i imm) in sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let rs_val = (integer_word$w2i w__0) in
    wGPR rt
-     ((zero_extend1 (( 64 : int):ii)
+     ((mips_zero_extend (( 64 : int):ii)
          (if ((rs_val < imm_val)) then (vec_of_bits [B1]  :  1 words$word)
           else (vec_of_bits [B0]  :  1 words$word))
         :  64 words$word)))))`;
@@ -5668,11 +5757,11 @@ val _ = Define `
 (*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd
-     ((zero_extend1 (( 64 : int):ii)
+     ((mips_zero_extend (( 64 : int):ii)
          (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1]  :  1 words$word)
           else (vec_of_bits [B0]  :  1 words$word))
         :  64 words$word))))))`;
@@ -5681,34 +5770,34 @@ val _ = Define `
 (*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
+ ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in state_monad$bindS
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
-   let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
-   wGPR rd ((sign_extend1 (( 64 : int):ii) w__2  :  64 words$word)))))))`;
+   let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+   wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2  :  64 words$word)))))))`;
 
 
 (*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
+ ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
-   wGPR rd ((sign_extend1 (( 64 : int):ii) w__1  :  64 words$word))))))`;
+   let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+   wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1  :  64 words$word))))))`;
 
 
 (*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
-      StoreData D
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData DR
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let wordAddr =
      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii)  :  61 words$word))
@@ -5735,12 +5824,12 @@ val _ = Define `
 (*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
-      StoreData D
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData DL
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__32 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
    if (((b__32 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
@@ -5763,57 +5852,52 @@ val _ = Define `
 (*val execute_RI : unit -> M unit*)
 
 val _ = Define `
- ((execute_RI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__130=  (SignalException ResI))`;
+ ((execute_RI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__28=  (SignalException ResI))`;
 
 
 (*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd=  (state_monad$bindS
+ ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd=  (sail2_state_monad$bindS
    (getAccessLevel () ) (\ accessLevel . 
-   let (haveAccessLevel : bool) = (accessLevel = Kernel) in state_monad$bindS
-   (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
-   let (haveCU0 : bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):ii)))) in
-   let rdi = (lem$w2ui rd) in state_monad$bindS
-   (state_monad$read_regS CP0HWREna_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
-   let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in state_monad$seqS
+   let (haveAccessLevel : bool) = (accessLevel = Kernel) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+   let (haveCU0 : bool) =
+     (B1 = ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):ii)))) in
+   let rdi = (lem$w2ui rd) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0HWREna_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+   let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in sail2_state_monad$seqS
    (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI
-    else state_monad$returnS () )
-   (let b__146 = rd in state_monad$bindS
+    else sail2_state_monad$returnS () )
+   (let b__146 = rd in sail2_state_monad$bindS
    (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then
-      state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
     else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) then
-      state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
-    else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) then state_monad$bindS
-      (state_monad$read_regS CP0Count_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
-      state_monad$returnS ((zero_extend1 (( 64 : int):ii) w__2  :  64 words$word)))
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2  :  64 words$word)))
     else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) then
-      state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word))
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word))
     else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))) then
-      (state_monad$read_regS CP0UserLocal_ref  : ( 64 words$word) M)
+      (sail2_state_monad$read_regS CP0UserLocal_ref  : ( 64 words$word) M)
     else (SignalException ResI  : ( 64 words$word) M)) (\ (temp : 64 bits) . 
    wGPR rt temp)))))))`;
 
 
-(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*)
-
-val _ = Define `
- ((execute_PREF:(5)words$word ->(5)words$word ->(16)words$word -> unit) base op imm=  () )`;
-
-
 (*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+   wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
 
 
 (*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd ((or_vec w__0 w__1  :  64 words$word))))))`;
 
@@ -5821,8 +5905,8 @@ val _ = Define `
 (*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd ((not_vec ((or_vec w__0 w__1  :  64 words$word))  :  64 words$word))))))`;
 
@@ -5830,62 +5914,66 @@ val _ = Define `
 (*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                  ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                :  64 words$word))) (\ (result : 64 bits) .  state_monad$seqS
-   (state_monad$write_regS
+                :  64 words$word))) (\ (result : 64 bits) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      HI_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))  :  64 words$word)))
-   (state_monad$write_regS
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
      LO_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))))`;
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))`;
 
 
 (*val execute_MULT : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                  ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                :  64 words$word))) (\ (result : 64 bits) .  state_monad$seqS
-   (state_monad$write_regS
+                :  64 words$word))) (\ (result : 64 bits) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      HI_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))  :  64 words$word)))
-   (state_monad$write_regS
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
      LO_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))))`;
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))`;
 
 
 (*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ rtVal . 
    let (result : 64 bits) =
-     ((sign_extend1 (( 64 : int):ii)
+     ((mips_sign_extend (( 64 : int):ii)
         ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
            :  64 words$word))
-       :  64 words$word)) in state_monad$bindS
+       :  64 words$word)) in sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                 :  64 words$word))) (\ (w__1 :  64 words$word) . 
    wGPR rd w__1)))))`;
 
@@ -5893,933 +5981,496 @@ val _ = Define `
 (*val execute_MTLO : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MTLO:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  state_monad$write_regS LO_ref w__0)))`;
+ ((execute_MTLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$write_regS LO_ref w__0)))`;
 
 
 (*val execute_MTHI : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MTHI:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  state_monad$write_regS HI_ref w__0)))`;
+ ((execute_MTHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$write_regS HI_ref w__0)))`;
 
 
 (*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sel double=  (state_monad$bindS (state_monad$seqS
+ ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP0Access () )
-   (rGPR rt  : ( 64 words$word) M)) (\ reg_val .  
-  (case (rd, sel) of
-        (b__108, b__109) =>
-  if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\
-          (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-    state_monad$write_regS TLBIndex_ref
-      ((mask (( 6 : int): ii) reg_val : 6 words$word)) else
-    if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\
-            (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-      state_monad$returnS ()  else
-      if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\
-              (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-        set_TLBEntryLoReg TLBEntryLo0_ref reg_val else
-        if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\
-                (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-          set_TLBEntryLoReg TLBEntryLo1_ref reg_val else
-          if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
-                  /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-            set_ContextReg_PTEBase TLBContext_ref
-              ((subrange_vec_dec reg_val (( 63 : int): ii) (( 23 : int): ii) : 41 words$word))
-          else
-            if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
-                    /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then
-              state_monad$write_regS CP0UserLocal_ref reg_val else
-              if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word))))
-                      /\
-                      (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                state_monad$write_regS TLBPageMask_ref
-                  ((subrange_vec_dec reg_val (( 28 : int): ii)
-                      (( 13 : int): ii) : 16 words$word)) else
-                if ((((((b__108 =
-                           (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word))))
-                        /\
-                        (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                  state_monad$seqS
-                    (state_monad$write_regS TLBWired_ref
-                       ((mask (( 6 : int): ii) reg_val : 6 words$word)))
-                    (state_monad$write_regS TLBRandom_ref TLBIndexMax) else
-                  if ((((((b__108 =
-                             (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word))))
-                          /\
-                          (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                    state_monad$write_regS CP0HWREna_ref
-                      ((concat_vec
-                          ((subrange_vec_dec reg_val (( 31 : int): ii)
-                              (( 29 : int): ii) : 3 words$word))
-                          ((concat_vec
-                              (vec_of_bits
-                                 [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0] : 25 words$word)
-                              ((subrange_vec_dec reg_val (( 3 : int): ii)
-                                  (( 0 : int): ii) : 4 words$word))
-                           : 29 words$word)) : 32 words$word)) else
-                    if ((((((b__108 =
-                               (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))
-                            /\
-                            (((b__109 =
-                                 (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                      state_monad$returnS ()  else
-                      if ((((((b__108 =
-                                 (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))
-                              /\
-                              (((b__109 =
-                                   (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                        state_monad$write_regS CP0Count_ref
-                          ((subrange_vec_dec reg_val (( 31 : int): ii)
-                              (( 0 : int): ii) : 32 words$word)) else
-                        if ((((((b__108 =
-                                   (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))
-                                /\
-                                (((b__109 =
-                                     (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                          state_monad$seqS
-                            (state_monad$seqS
-                               (set_TLBEntryHiReg_R TLBEntryHi_ref
-                                  ((subrange_vec_dec reg_val
-                                      (( 63 : int): ii) (( 62 : int): ii) : 2 words$word)))
-                               (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref
-                                  ((subrange_vec_dec reg_val
-                                      (( 39 : int): ii) (( 13 : int): ii) : 27 words$word))))
-                            (set_TLBEntryHiReg_ASID TLBEntryHi_ref
-                               ((subrange_vec_dec reg_val (( 7 : int): ii)
-                                   (( 0 : int): ii) : 8 words$word))) else
-                          if ((((((b__108 =
-                                     (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))
-                                  /\
-                                  (((b__109 =
-                                       (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                            state_monad$bindS
-                              (state_monad$seqS
-                                 (state_monad$write_regS CP0Compare_ref
-                                    ((subrange_vec_dec reg_val
-                                        (( 31 : int): ii) (( 0 : int): ii) : 32 words$word)))
-                                 (state_monad$read_regS CP0Cause_ref))
-                              (\ (w__0 : CauseReg) . 
-                               set_CauseReg_IP CP0Cause_ref
-                                 ((and_vec
-                                     ((get_CauseReg_IP w__0 : 8 words$word))
-                                     (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word)
-                                  : 8 words$word))) else
-                            if ((((((b__108 =
-                                       (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))
-                                    /\
-                                    (((b__109 =
-                                         (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                              state_monad$seqS
-                                (state_monad$seqS
-                                   (state_monad$seqS
-                                      (state_monad$seqS
-                                         (state_monad$seqS
-                                            (state_monad$seqS
-                                               (state_monad$seqS
-                                                  (state_monad$seqS
-                                                     (state_monad$seqS
-                                                        (set_StatusReg_CU
-                                                           CP0Status_ref
-                                                           ((subrange_vec_dec
-                                                               reg_val
-                                                               (( 31 : int): ii)
-                                                               (( 28 : int): ii) : 4 words$word)))
-                                                        (set_StatusReg_BEV
-                                                           CP0Status_ref
-                                                           ((cast_unit_vec0
-                                                               ((access_vec_dec
-                                                                   reg_val
-                                                                   ((
-                                                                     22 : int): ii))) : 1 words$word))))
-                                                     (set_StatusReg_IM
-                                                        CP0Status_ref
-                                                        ((subrange_vec_dec
-                                                            reg_val
-                                                            (( 15 : int): ii)
-                                                            (( 8 : int): ii) : 8 words$word))))
-                                                  (set_StatusReg_KX
-                                                     CP0Status_ref
-                                                     ((cast_unit_vec0
-                                                         ((access_vec_dec
-                                                             reg_val
-                                                             (( 7 : int): ii))) : 1 words$word))))
-                                               (set_StatusReg_SX
-                                                  CP0Status_ref
-                                                  ((cast_unit_vec0
-                                                      ((access_vec_dec
-                                                          reg_val
-                                                          (( 6 : int): ii))) : 1 words$word))))
-                                            (set_StatusReg_UX CP0Status_ref
-                                               ((cast_unit_vec0
-                                                   ((access_vec_dec reg_val
-                                                       (( 5 : int): ii))) : 1 words$word))))
-                                         (set_StatusReg_KSU CP0Status_ref
-                                            ((subrange_vec_dec reg_val
-                                                (( 4 : int): ii)
-                                                (( 3 : int): ii) : 2 words$word))))
-                                      (set_StatusReg_ERL CP0Status_ref
-                                         ((cast_unit_vec0
-                                             ((access_vec_dec reg_val
-                                                 (( 2 : int): ii))) : 1 words$word))))
-                                   (set_StatusReg_EXL CP0Status_ref
-                                      ((cast_unit_vec0
-                                          ((access_vec_dec reg_val
-                                              (( 1 : int): ii))) : 1 words$word))))
-                                (set_StatusReg_IE CP0Status_ref
-                                   ((cast_unit_vec0
-                                       ((access_vec_dec reg_val
-                                           (( 0 : int): ii))) : 1 words$word)))
-                            else
-                              if ((((((b__108 =
-                                         (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word))))
-                                      /\
-                                      (((b__109 =
-                                           (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                state_monad$bindS
-                                  (state_monad$seqS
-                                     (set_CauseReg_IV CP0Cause_ref
-                                        ((cast_unit_vec0
-                                            ((access_vec_dec reg_val
-                                                (( 23 : int): ii))) : 1 words$word)))
-                                     (state_monad$read_regS CP0Cause_ref))
-                                  (\ (w__1 : CauseReg) . 
-                                   let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in
-                                   set_CauseReg_IP CP0Cause_ref
-                                     ((concat_vec
-                                         ((subrange_vec_dec ip
-                                             (( 7 : int): ii)
-                                             (( 2 : int): ii) : 6 words$word))
-                                         ((subrange_vec_dec reg_val
-                                             (( 9 : int): ii)
-                                             (( 8 : int): ii) : 2 words$word))
-                                      : 8 words$word))) else
-                                if ((((((b__108 =
-                                           (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))
-                                        /\
-                                        (((b__109 =
-                                             (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                  state_monad$write_regS CP0EPC_ref reg_val
-                                else
-                                  if ((((((b__108 =
-                                             (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word))))
-                                          /\
-                                          (((b__109 =
-                                               (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                    state_monad$returnS ()  else
-                                    if ((((((b__108 =
-                                               (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word))))
-                                            /\
-                                            (((b__109 =
-                                                 (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                      set_XContextReg_XPTEBase
-                                        TLBXContext_ref
-                                        ((subrange_vec_dec reg_val
-                                            (( 63 : int): ii)
-                                            (( 33 : int): ii) : 31 words$word))
-                                    else
-                                      state_monad$write_regS CP0ErrorEPC_ref
-                                        reg_val
-  ))))`;
+   (rGPR rt  : ( 64 words$word) M)) (\ reg_val . 
+   (case (rd, sel) of
+     (b__108, b__109) =>
+      if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS TLBIndex_ref ((mask (( 6 : int):ii) reg_val  :  6 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS () 
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_ContextReg_PTEBase TLBContext_ref
+          ((subrange_vec_dec reg_val (( 63 : int):ii) (( 23 : int):ii)  :  41 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0UserLocal_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 : int):ii) (( 13 : int):ii)  :  16 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$seqS
+        (sail2_state_monad$write_regS TLBWired_ref ((mask (( 6 : int):ii) reg_val  :  6 words$word)))
+        (sail2_state_monad$write_regS TLBRandom_ref TLBIndexMax)
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS
+          CP0HWREna_ref
+          ((concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 29 : int):ii)  :  3 words$word))
+              ((concat_vec
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0]
+                    :  25 words$word) ((subrange_vec_dec reg_val (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+                 :  29 words$word))
+             :  32 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS () 
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0Count_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+        (set_TLBEntryHiReg_R TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))
+        (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word))))
+        (set_TLBEntryHiReg_ASID TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0Compare_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))
+        (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__0 : CauseReg) . 
+        set_CauseReg_IP CP0Cause_ref
+          ((and_vec ((get_CauseReg_IP w__0  :  8 words$word))
+              (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1]  :  8 words$word)
+             :  8 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+        (set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)))
+        (set_StatusReg_BEV CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word))))
+        (set_StatusReg_KX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_SX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_UX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word))))
+        (set_StatusReg_ERL CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_EXL CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_IE CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 : int):ii)))  :  1 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+        (set_CauseReg_IV CP0Cause_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 : int):ii)))  :  1 words$word)))
+        (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__1 : CauseReg) . 
+        let ip = ((get_CauseReg_IP w__1  :  8 words$word)) in
+        set_CauseReg_IP CP0Cause_ref
+          ((concat_vec ((subrange_vec_dec ip (( 7 : int):ii) (( 2 : int):ii)  :  6 words$word))
+              ((subrange_vec_dec reg_val (( 9 : int):ii) (( 8 : int):ii)  :  2 words$word))
+             :  8 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0EPC_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+      else if ((((((b__108 = (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_XContextReg_XPTEBase TLBXContext_ref
+          ((subrange_vec_dec reg_val (( 63 : int):ii) (( 33 : int):ii)  :  31 words$word))
+      else if ((((((b__108 = (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0ErrorEPC_ref reg_val
+      else SignalException ResI
+   ))))`;
 
 
 (*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                  ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                :  64 words$word))) (\ (mul_result : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
    let result =
      ((sub_vec
         ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
            :  64 words$word)) mul_result
-       :  64 words$word)) in state_monad$seqS
-   (state_monad$write_regS
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      HI_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))  :  64 words$word)))
-   (state_monad$write_regS
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
      LO_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))))))`;
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
 
 
 (*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                  ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                :  64 words$word))) (\ (mul_result : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
    let result =
      ((sub_vec
         ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
            :  64 words$word)) mul_result
-       :  64 words$word)) in state_monad$seqS
-   (state_monad$write_regS
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      HI_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))  :  64 words$word)))
-   (state_monad$write_regS
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
      LO_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))))))`;
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
 
 
 (*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
+ ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-            :  64 words$word)))) then state_monad$bindS
+            :  64 words$word)))) then sail2_state_monad$bindS
      (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
-   else state_monad$returnS () )))`;
+   else sail2_state_monad$returnS () )))`;
 
 
 (*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
+ ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-            :  64 words$word)))) then state_monad$bindS
+            :  64 words$word)))) then sail2_state_monad$bindS
      (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
-   else state_monad$returnS () )))`;
+   else sail2_state_monad$returnS () )))`;
 
 
 (*val execute_MFLO : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MFLO:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd=  (state_monad$bindS
-   (state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
+ ((execute_MFLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
 
 
 (*val execute_MFHI : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MFHI:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd=  (state_monad$bindS
-   (state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
+ ((execute_MFHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
 
 
 (*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sel double=  (state_monad$bindS (state_monad$seqS
-   (checkCP0Access () ) 
-  (case (rd, sel) of
-        (b__48, b__49) =>
-  if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\
-          (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-    state_monad$bindS
-      (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)
-      (\ (w__0 : TLBIndexT) . 
-       let (idx : 31 bits) = ((zero_extend1 (( 31 : int): ii) w__0 : 31 words$word)) in
-       state_monad$bindS
-         (state_monad$read_regS TLBProbe_ref : ( 1 words$word) M)
-         (\ (w__1 : 1 bits) . 
-          state_monad$returnS
-            ((concat_vec
-                (vec_of_bits
-                   [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 32 words$word)
-                ((concat_vec w__1 idx : 32 words$word)) : 64 words$word))))
-  else
-    if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\
-            (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-      state_monad$bindS
-        (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M)
-        (\ (w__2 : TLBIndexT) . 
-         state_monad$returnS
-           ((zero_extend1 (( 64 : int): ii) w__2 : 64 words$word))) else
-      if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\
-              (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-        state_monad$bindS (state_monad$read_regS TLBEntryLo0_ref)
-          (\ (w__3 : TLBEntryLoReg) . 
-           state_monad$returnS ((get_TLBEntryLoReg w__3 : 64 words$word)))
-      else
-        if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\
-                (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-          state_monad$bindS (state_monad$read_regS TLBEntryLo1_ref)
-            (\ (w__4 : TLBEntryLoReg) . 
-             state_monad$returnS ((get_TLBEntryLoReg w__4 : 64 words$word)))
-        else
-          if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
-                  /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-            state_monad$bindS (state_monad$read_regS TLBContext_ref)
-              (\ (w__5 : ContextReg) . 
-               state_monad$returnS ((get_ContextReg w__5 : 64 words$word)))
-          else
-            if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
-                    /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then
-              (state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M)
-            else
-              if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word))))
-                      /\
-                      (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                state_monad$bindS
-                  (state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M)
-                  (\ (w__7 : 16 bits) . 
-                   state_monad$returnS
-                     ((zero_extend1 (( 64 : int): ii)
-                         ((concat_vec w__7
-                             (vec_of_bits
-                                [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
-                          : 28 words$word)) : 64 words$word))) else
-                if ((((((b__48 =
-                           (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word))))
-                        /\
-                        (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                  state_monad$bindS
-                    (state_monad$read_regS TLBWired_ref : ( 6 words$word) M)
-                    (\ (w__8 : TLBIndexT) . 
-                     state_monad$returnS
-                       ((zero_extend1 (( 64 : int): ii) w__8 : 64 words$word)))
-                else
-                  if ((((((b__48 =
-                             (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word))))
-                          /\
-                          (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                    state_monad$bindS
-                      (state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M)
-                      (\ (w__9 : 32 bits) . 
-                       state_monad$returnS
-                         ((zero_extend1 (( 64 : int): ii) w__9 : 64 words$word)))
-                  else
-                    if ((((((b__48 =
-                               (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))
-                            /\
-                            (((b__49 =
-                                 (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                      (state_monad$read_regS CP0BadVAddr_ref : ( 64 words$word) M)
-                    else
-                      if ((((((b__48 =
-                                 (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))
-                              /\
-                              (((b__49 =
-                                   (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then
-                        state_monad$returnS
-                          ((zero_extend1 (( 64 : int): ii)
-                              (vec_of_bits [B0] : 1 words$word) : 64 words$word))
-                      else
-                        if ((((((b__48 =
-                                   (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))
-                                /\
-                                (((b__49 =
-                                     (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                          state_monad$bindS
-                            (state_monad$read_regS CP0Count_ref : ( 32 words$word) M)
-                            (\ (w__11 : 32 bits) . 
-                             state_monad$returnS
-                               ((zero_extend1 (( 64 : int): ii) w__11 : 64 words$word)))
-                        else
-                          if ((((((b__48 =
-                                     (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))
-                                  /\
-                                  (((b__49 =
-                                       (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                            state_monad$bindS
-                              (state_monad$read_regS TLBEntryHi_ref)
-                              (\ (w__12 : TLBEntryHiReg) . 
-                               state_monad$returnS
-                                 ((get_TLBEntryHiReg w__12 : 64 words$word)))
-                          else
-                            if ((((((b__48 =
-                                       (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))
-                                    /\
-                                    (((b__49 =
-                                         (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                              state_monad$bindS
-                                (state_monad$read_regS CP0Compare_ref : ( 32 words$word) M)
-                                (\ (w__13 : 32 bits) . 
-                                 state_monad$returnS
-                                   ((zero_extend1 (( 64 : int): ii) w__13 : 64 words$word)))
-                            else
-                              if ((((((b__48 =
-                                         (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))
-                                      /\
-                                      (((b__49 =
-                                           (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                state_monad$bindS
-                                  (state_monad$read_regS CP0Status_ref)
-                                  (\ (w__14 : StatusReg) . 
-                                   state_monad$returnS
-                                     ((zero_extend1 (( 64 : int): ii)
-                                         ((get_StatusReg w__14 : 32 words$word)) : 64 words$word)))
-                              else
-                                if ((((((b__48 =
-                                           (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word))))
-                                        /\
-                                        (((b__49 =
-                                             (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                  state_monad$bindS
-                                    (state_monad$read_regS CP0Cause_ref)
-                                    (\ (w__15 : CauseReg) . 
-                                     state_monad$returnS
-                                       ((zero_extend1 (( 64 : int): ii)
-                                           ((get_CauseReg w__15 : 32 words$word)) : 64 words$word)))
-                                else
-                                  if ((((((b__48 =
-                                             (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))
-                                          /\
-                                          (((b__49 =
-                                               (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                    (state_monad$read_regS CP0EPC_ref : ( 64 words$word) M)
-                                  else
-                                    if ((((((b__48 =
-                                               (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word))))
-                                            /\
-                                            (((b__49 =
-                                                 (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
-                                      state_monad$returnS
-                                        ((zero_extend1 (( 64 : int): ii)
-                                            (vec_of_bits
-                                               [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
-                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                                            : 32 words$word) : 64 words$word))
-                                    else
-                                      if ((((((b__48 =
-                                                 (vec_of_bits
-                                                    [B0;B1;B1;B1;B1] : 5 words$word))))
-                                              /\
-                                              (((b__49 =
-                                                   (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then
-                                        state_monad$returnS
-                                          ((zero_extend1 (( 64 : int): ii)
-                                              (vec_of_bits [B0] : 1 words$word) : 64 words$word))
-                                      else
-                                        if ((((((b__48 =
-                                                   (vec_of_bits
-                                                      [B0;B1;B1;B1;B1] : 5 words$word))))
-                                                /\
-                                                (((b__49 =
-                                                     (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then
-                                          state_monad$returnS
-                                            ((zero_extend1 (( 64 : int): ii)
-                                                (vec_of_bits [B0] : 1 words$word) : 64 words$word))
-                                        else
-                                          if ((((((b__48 =
-                                                     (vec_of_bits
-                                                        [B1;B0;B0;B0;B0] : 5 words$word))))
-                                                  /\
-                                                  (((b__49 =
-                                                       (vec_of_bits
-                                                          [B0;B0;B0] : 3 words$word))))))) then
-                                            state_monad$returnS
-                                              ((zero_extend1
-                                                  (( 64 : int): ii)
-                                                  ((concat_vec
-                                                      (vec_of_bits [B1] : 1 words$word)
-                                                      ((concat_vec
-                                                          (vec_of_bits
-                                                             [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 15 words$word)
-                                                          ((concat_vec
-                                                              (vec_of_bits
-                                                                 [B1] : 1 words$word)
-                                                              ((concat_vec
-                                                                  (vec_of_bits
-                                                                    [B1;B0] : 2 words$word)
-                                                                  ((concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B1] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    : 7 words$word))
-                                                                    : 10 words$word))
-                                                                   : 13 words$word))
-                                                               : 15 words$word))
-                                                           : 16 words$word))
-                                                       : 31 words$word))
-                                                   : 32 words$word))
-                                               : 64 words$word)) else
-                                            if ((((((b__48 =
-                                                       (vec_of_bits
-                                                          [B1;B0;B0;B0;B0] : 5 words$word))))
-                                                    /\
-                                                    (((b__49 =
-                                                         (vec_of_bits
-                                                            [B0;B0;B1] : 3 words$word))))))) then
-                                              state_monad$returnS
-                                                ((zero_extend1
-                                                    (( 64 : int): ii)
-                                                    ((concat_vec
-                                                        (vec_of_bits [B1] : 1 words$word)
-                                                        ((concat_vec
-                                                            TLBIndexMax
-                                                            ((concat_vec
-                                                                (vec_of_bits
-                                                                   [B0;B0;B0] : 3 words$word)
-                                                                ((concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    (
-                                                                    bool_to_bits
-                                                                    have_cp2 : 1 words$word))
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0] : 1 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0] : 1 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0] : 1 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0]
-                                                                    : 1 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0]
-                                                                    : 1 words$word)
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0]
-                                                                    : 1 words$word)
-                                                                    : 2 words$word))
-                                                                    : 3 words$word))
-                                                                    : 4 words$word))
-                                                                    : 5 words$word))
-                                                                    : 6 words$word))
-                                                                    : 7 words$word))
-                                                                    : 10 words$word))
-                                                                    : 13 words$word))
-                                                                    : 16 words$word))
-                                                                    : 19 words$word))
-                                                                 : 22 words$word))
-                                                             : 25 words$word))
-                                                         : 31 words$word))
-                                                     : 32 words$word))
-                                                 : 64 words$word)) else
-                                              if ((((((b__48 =
-                                                         (vec_of_bits
-                                                            [B1;B0;B0;B0;B0] : 5 words$word))))
-                                                      /\
-                                                      (((b__49 =
-                                                           (vec_of_bits
-                                                              [B0;B1;B0] : 3 words$word))))))) then
-                                                state_monad$returnS
-                                                  ((zero_extend1
-                                                      (( 64 : int): ii)
-                                                      ((concat_vec
-                                                          (vec_of_bits [B1] : 1 words$word)
-                                                          ((concat_vec
-                                                              (vec_of_bits
-                                                                 [B0;B0;B0] : 3 words$word)
-                                                              ((concat_vec
-                                                                  (vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                  ((concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0;B0] : 4 words$word)
-                                                                    : 8 words$word))
-                                                                    : 12 words$word))
-                                                                    : 16 words$word))
-                                                                    : 20 words$word))
-                                                                   : 24 words$word))
-                                                               : 28 words$word))
-                                                           : 31 words$word))
-                                                       : 32 words$word))
-                                                   : 64 words$word)) else
-                                                if ((((((b__48 =
-                                                           (vec_of_bits
-                                                              [B1;B0;B0;B0;B0] : 5 words$word))))
-                                                        /\
-                                                        (((b__49 =
-                                                             (vec_of_bits
-                                                                [B0;B1;B1] : 3 words$word))))))) then
-                                                  state_monad$returnS
-                                                    (vec_of_bits
-                                                       [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                                       B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                                                    : 64 words$word) else
-                                                  if ((((((b__48 =
-                                                             (vec_of_bits
-                                                                [B1;B0;B0;B0;B0] : 5 words$word))))
-                                                          /\
-                                                          (((b__49 =
-                                                               (vec_of_bits
-                                                                  [B1;B0;B1] : 3 words$word))))))) then
-                                                    state_monad$returnS
-                                                      (vec_of_bits
-                                                         [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                                                      : 64 words$word) else
-                                                    if ((((((b__48 =
-                                                               (vec_of_bits
-                                                                  [B1;B0;B0;B0;B1] : 5 words$word))))
-                                                            /\
-                                                            (((b__49 =
-                                                                 (vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word))))))) then
-                                                      (state_monad$read_regS
-                                                         CP0LLAddr_ref : ( 64 words$word) M)
-                                                    else
-                                                      if ((((((b__48 =
-                                                                 (vec_of_bits
-                                                                    [B1;B0;B0;B1;B0] : 5 words$word))))
-                                                              /\
-                                                              (((b__49 =
-                                                                   (vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word))))))) then
-                                                        state_monad$returnS
-                                                          ((zero_extend1
-                                                              (( 64 : int): ii)
-                                                              (vec_of_bits
-                                                                 [B0] : 1 words$word) : 64 words$word))
-                                                      else
-                                                        if ((((((b__48 =
-                                                                   (vec_of_bits
-                                                                    [B1;B0;B0;B1;B1] : 5 words$word))))
-                                                                /\
-                                                                (((b__49 =
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word))))))) then
-                                                          state_monad$returnS
-                                                            ((zero_extend1
-                                                                (( 64 : int): ii)
-                                                                (vec_of_bits
-                                                                   [B0] : 1 words$word) : 64 words$word))
-                                                        else
-                                                          if ((((((b__48 =
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B1;B0;B1;B0;B0] : 5 words$word))))
-                                                                  /\
-                                                                  (((
-                                                                    b__49 =
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0;B0;B0] : 3 words$word))))))) then
-                                                            state_monad$bindS
-                                                              (state_monad$read_regS
-                                                                 TLBXContext_ref)
-                                                              (\ (w__18 : XContextReg) . 
-                                                               state_monad$returnS
-                                                                 ((get_XContextReg
-                                                                    w__18 : 64 words$word)))
-                                                          else
-                                                            (state_monad$read_regS
-                                                               CP0ErrorEPC_ref : ( 64 words$word) M)
-  )) (\ (result : 64 bits) . 
+ ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (case (rd, sel) of
+     (b__48, b__49) =>
+      if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . 
+        let (idx : 31 bits) = ((mips_zero_extend (( 31 : int):ii) w__0  :  31 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBProbe_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
+        sail2_state_monad$returnS ((concat_vec
+                   (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  32 words$word) ((concat_vec w__1 idx  :  32 words$word))
+                  :  64 words$word))))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__2 : TLBIndexT) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . 
+        sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__3  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . 
+        sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__4  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBContext_ref) (\ (w__5 : ContextReg) . 
+        sail2_state_monad$returnS ((get_ContextReg_bits w__5  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0UserLocal_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBPageMask_ref  : ( 16 words$word) M) (\ (w__7 : 16 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec w__7
+                       (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+                      :  28 words$word))
+                  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBWired_ref  : ( 6 words$word) M) (\ (w__8 : TLBIndexT) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__8  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0HWREna_ref  : ( 32 words$word) M) (\ (w__9 : 32 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__9  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0BadVAddr_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M) (\ (w__11 : 32 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__11  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBEntryHi_ref) (\ (w__12 : TLBEntryHiReg) . 
+        sail2_state_monad$returnS ((get_TLBEntryHiReg_bits w__12  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Compare_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__13  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Status_ref) (\ (w__14 : StatusReg) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_StatusReg_bits w__14  :  32 words$word))  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__15 : CauseReg) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_CauseReg_bits w__15  :  32 words$word))  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0EPC_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  32 words$word)
+                  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0ConfigK0_ref  : ( 3 words$word) M) (\ (w__17 : 3 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                       ((concat_vec
+                           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  15 words$word)
+                           ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                               ((concat_vec (vec_of_bits [B1;B0]  :  2 words$word)
+                                   ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                       ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                                           ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                               w__17
+                                              :  7 words$word))
+                                          :  10 words$word))
+                                      :  13 words$word))
+                                  :  15 words$word))
+                              :  16 words$word))
+                          :  31 words$word))
+                      :  32 words$word))
+                  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                       ((concat_vec TLBIndexMax
+                           ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                               ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                   ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                       ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                           ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                               ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                                   ((concat_vec
+                                                       ((bool_to_bits have_cp2  :  1 words$word))
+                                                       ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                                                           ((concat_vec
+                                                               (vec_of_bits [B0]  :  1 words$word)
+                                                               ((concat_vec
+                                                                   (vec_of_bits [B0]  :  1 words$word)
+                                                                   ((concat_vec
+                                                                       (vec_of_bits [B0]
+                                                                         :  1 words$word)
+                                                                       ((concat_vec
+                                                                           (vec_of_bits [B0]
+                                                                             :  1 words$word)
+                                                                           (vec_of_bits [B0]
+                                                                             :  1 words$word)
+                                                                          :  2 words$word))
+                                                                      :  3 words$word))
+                                                                  :  4 words$word))
+                                                              :  5 words$word))
+                                                          :  6 words$word))
+                                                      :  7 words$word))
+                                                  :  10 words$word))
+                                              :  13 words$word))
+                                          :  16 words$word))
+                                      :  19 words$word))
+                                  :  22 words$word))
+                              :  25 words$word))
+                          :  31 words$word))
+                      :  32 words$word))
+                  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                       ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                           ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                               ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                   ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                       ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                           ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                               ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                                   (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                                  :  8 words$word))
+                                              :  12 words$word))
+                                          :  16 words$word))
+                                      :  20 words$word))
+                                  :  24 words$word))
+                              :  28 words$word))
+                          :  31 words$word))
+                      :  32 words$word))
+                  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                 :  64 words$word)
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                 :  64 words$word)
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0LLAddr_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBXContext_ref) (\ (w__19 : XContextReg) . 
+        sail2_state_monad$returnS ((get_XContextReg_bits w__19  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0ErrorEPC_ref  : ( 64 words$word) M)
+      else (SignalException ResI  : ( 64 words$word) M)
+   )) (\ (result : 64 bits) . 
    wGPR rt
      (if double then result
       else
-        (sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word)))))`;
+        (mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  64 words$word)))))`;
 
 
 (*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                  ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                :  64 words$word))) (\ (mul_result : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
    let result =
      ((add_vec mul_result
         ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
            :  64 words$word))
-       :  64 words$word)) in state_monad$seqS
-   (state_monad$write_regS
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      HI_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))  :  64 words$word)))
-   (state_monad$write_regS
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
      LO_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))))))`;
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
 
 
 (*val execute_MADD : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
     else
-      state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                  ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                :  64 words$word))) (\ (mul_result : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  state_monad$bindS
-   (state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
    let result =
      ((add_vec mul_result
         ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
            :  64 words$word))
-       :  64 words$word)) in state_monad$seqS
-   (state_monad$write_regS
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      HI_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))  :  64 words$word)))
-   (state_monad$write_regS
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
      LO_ref
-     ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))))))`;
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
 
 
 (*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) width sign linked base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
-      width
+ ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width sign linked base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
+      LoadData width
      : ( 64 words$word) M) (\ (vAddr : 64 bits) . 
    if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr
-   else state_monad$bindS
-     (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
-     (if linked then state_monad$seqS (state_monad$seqS
-        (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
-        (state_monad$write_regS CP0LLAddr_ref pAddr))
+   else sail2_state_monad$bindS
+     (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+     (if linked then sail2_state_monad$seqS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+        (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
         (case width of
-          B => state_monad$bindS
-           (MEMr_reserve_wrapper pAddr (( 1 : int):ii)  : ( 8 words$word) M) (\ (w__1 :  8 words$word) . 
-           state_monad$returnS ((extendLoad w__1 sign  :  64 words$word)))
-        | H => state_monad$bindS
-           (MEMr_reserve_wrapper pAddr (( 2 : int):ii)  : ( 16 words$word) M) (\ (w__2 :  16 words$word) . 
-           state_monad$returnS ((extendLoad w__2 sign  :  64 words$word)))
-        | W0 => state_monad$bindS
-           (MEMr_reserve_wrapper pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
-           state_monad$returnS ((extendLoad w__3 sign  :  64 words$word)))
-        | D => state_monad$bindS
-           (MEMr_reserve_wrapper pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
-           state_monad$returnS ((extendLoad w__4 sign  :  64 words$word)))
+          W0 => sail2_state_monad$bindS
+           (MEMr_reserve_wrapper pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__1 sign  :  64 words$word)))
+        | D => sail2_state_monad$bindS
+           (MEMr_reserve_wrapper pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__2 sign  :  64 words$word)))
+        | _ => sail2_state_monad$throwS (Error_internal_error () )
         )
       else
         (case width of
-          B => state_monad$bindS
-           (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii)  : ( 8 words$word) M) (\ (w__6 :  8 words$word) . 
-           state_monad$returnS ((extendLoad w__6 sign  :  64 words$word)))
-        | H => state_monad$bindS
-           (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii)  : ( 16 words$word) M) (\ (w__7 :  16 words$word) . 
-           state_monad$returnS ((extendLoad w__7 sign  :  64 words$word)))
-        | W0 => state_monad$bindS
-           (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__8 :  32 words$word) . 
-           state_monad$returnS ((extendLoad w__8 sign  :  64 words$word)))
-        | D => state_monad$bindS
-           (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__9 :  64 words$word) . 
-           state_monad$returnS ((extendLoad w__9 sign  :  64 words$word)))
+          B => sail2_state_monad$bindS
+           (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii)  : ( 8 words$word) M) (\ (w__5 :  8 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__5 sign  :  64 words$word)))
+        | H => sail2_state_monad$bindS
+           (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii)  : ( 16 words$word) M) (\ (w__6 :  16 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__6 sign  :  64 words$word)))
+        | W0 => sail2_state_monad$bindS
+           (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__7 :  32 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__7 sign  :  64 words$word)))
+        | D => sail2_state_monad$bindS
+           (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__8 :  64 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__8 sign  :  64 words$word)))
         )) (\ (memResult : 64 bits) . 
      wGPR rt memResult))))))`;
 
@@ -6827,17 +6478,17 @@ val _ = Define `
 (*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
-      W0
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData WR
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (MEMr_wrapper (( 32 : int):ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word))
           (vec_of_bits [B0;B0]  :  2 words$word)
          :  64 words$word)) (( 4 : int):ii)
-     : ( 32 words$word) M) (\ mem_val .  state_monad$bindS
+     : ( 32 words$word) M) (\ mem_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__4 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
    let (result : 32 bits) =
@@ -6854,23 +6505,23 @@ val _ = Define `
           ((subrange_vec_dec mem_val (( 31 : int):ii) (( 8 : int):ii)  :  24 words$word))
          :  32 words$word)
      else mem_val) in
-   wGPR rt ((sign_extend1 (( 64 : int):ii) result  :  64 words$word)))))))))`;
+   wGPR rt ((mips_sign_extend (( 64 : int):ii) result  :  64 words$word)))))))))`;
 
 
 (*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
-      W0
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData WL
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (MEMr_wrapper (( 32 : int):ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word))
           (vec_of_bits [B0;B0]  :  2 words$word)
          :  64 words$word)) (( 4 : int):ii)
-     : ( 32 words$word) M) (\ mem_val .  state_monad$bindS
+     : ( 32 words$word) M) (\ mem_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__0 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
    let (result : 32 bits) =
@@ -6887,15 +6538,15 @@ val _ = Define `
        (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
           ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
          :  32 words$word)) in
-   wGPR rt ((sign_extend1 (( 64 : int):ii) result  :  64 words$word)))))))))`;
+   wGPR rt ((mips_sign_extend (( 64 : int):ii) result  :  64 words$word)))))))))`;
 
 
 (*val execute_LUI : mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt imm=
+ ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt imm=
     (wGPR rt
-     ((sign_extend1 (( 64 : int):ii)
+     ((mips_sign_extend (( 64 : int):ii)
          ((concat_vec imm
              (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)
             :  32 words$word))
@@ -6905,17 +6556,17 @@ val _ = Define `
 (*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
-      D
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData DR
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (MEMr_wrapper (( 64 : int):ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii)  :  61 words$word))
           (vec_of_bits [B0;B0;B0]  :  3 words$word)
          :  64 words$word)) (( 8 : int):ii)
-     : ( 64 words$word) M) (\ mem_val .  state_monad$bindS
+     : ( 64 words$word) M) (\ mem_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__24 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
    wGPR rt
@@ -6953,17 +6604,17 @@ val _ = Define `
 (*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset=  (state_monad$bindS
-   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
-      D
-     : ( 64 words$word) M) (\ vAddr .  state_monad$bindS
-   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+ ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData DL
+     : ( 64 words$word) M) (\ vAddr .  sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
    (MEMr_wrapper (( 64 : int):ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii)  :  61 words$word))
           (vec_of_bits [B0;B0;B0]  :  3 words$word)
          :  64 words$word)) (( 8 : int):ii)
-     : ( 64 words$word) M) (\ mem_val .  state_monad$bindS
+     : ( 64 words$word) M) (\ mem_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
    let b__16 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
    wGPR rt
@@ -7001,38 +6652,38 @@ val _ = Define `
 (*val execute_JR : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_JR:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs=  (state_monad$bindS (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  execute_branch w__0)))`;
+ ((execute_JR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs=  (sail2_state_monad$bindS (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  execute_branch w__0)))`;
 
 
 (*val execute_JALR : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS (state_monad$seqS
+ ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (execute_branch w__0)
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
    wGPR rd ((add_vec_int w__1 (( 8 : int):ii)  :  64 words$word))))))`;
 
 
 (*val execute_JAL : mword ty26 -> M unit*)
 
 val _ = Define `
- ((execute_JAL:(26)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) offset=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  state_monad$bindS (state_monad$seqS
+ ((execute_JAL:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (execute_branch
      ((concat_vec
          ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii)  :  64 words$word)) (( 63 : int):ii) (( 28 : int):ii)  :  36 words$word))
          ((concat_vec offset (vec_of_bits [B0;B0]  :  2 words$word)  :  28 words$word))
         :  64 words$word)))
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
    wGPR (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) ((add_vec_int w__1 (( 8 : int):ii)  :  64 words$word))))))`;
 
 
 (*val execute_J : mword ty26 -> M unit*)
 
 val _ = Define `
- ((execute_J:(26)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) offset=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+ ((execute_J:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
    execute_branch
      ((concat_vec
          ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii)  :  64 words$word)) (( 63 : int):ii) (( 28 : int):ii)  :  36 words$word))
@@ -7040,39 +6691,33 @@ val _ = Define `
         :  64 words$word)))))`;
 
 
-(*val execute_ImplementationDefinedStopFetching : unit -> unit*)
-
-val _ = Define `
- ((execute_ImplementationDefinedStopFetching:unit -> unit) g__118=  () )`;
-
-
 (*val execute_HCF : unit -> unit*)
 
 val _ = Define `
- ((execute_HCF:unit -> unit) g__123=  () )`;
+ ((execute_HCF:unit -> unit) g__21=  () )`;
 
 
 (*val execute_ERET : unit -> M unit*)
 
 val _ = Define `
- ((execute_ERET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__128=  (state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS
+ ((execute_ERET:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__26=  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
    (checkCP0Access () )
    (ERETHook () ))
-   (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0]  :  1 words$word)))
-   (state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . 
-   if (((((bits_to_bool ((get_StatusReg_ERL w__0  :  1 words$word)))) = ((bit_to_bool B1))))) then state_monad$bindS
-     (state_monad$read_regS CP0ErrorEPC_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  state_monad$seqS
-     (state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0]  :  1 words$word)))
-   else state_monad$bindS
-     (state_monad$read_regS CP0EPC_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  state_monad$seqS
-     (state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0]  :  1 words$word))))))`;
+   (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0]  :  1 words$word)))
+   (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . 
+   if (((((bits_to_bool ((get_StatusReg_ERL w__0  :  1 words$word)))) = ((bit_to_bool B1))))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CP0ErrorEPC_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$seqS
+     (sail2_state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0]  :  1 words$word)))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CP0EPC_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$seqS
+     (sail2_state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0]  :  1 words$word))))))`;
 
 
 (*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd ((sub_vec w__0 w__1  :  64 words$word))))))`;
 
@@ -7080,11 +6725,12 @@ val _ = Define `
 (*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    let (temp65 : 65 bits) =
-     ((sub_vec ((sign_extend1 (( 65 : int):ii) w__0  :  65 words$word)) ((sign_extend1 (( 65 : int):ii) w__1  :  65 words$word))
+     ((sub_vec ((mips_sign_extend (( 65 : int):ii) w__0  :  65 words$word))
+        ((mips_sign_extend (( 65 : int):ii) w__1  :  65 words$word))
        :  65 words$word)) in
    if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):ii)))))
           ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):ii))))))) then
@@ -7095,67 +6741,67 @@ val _ = Define `
 (*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ temp .  state_monad$bindS
+ ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) in state_monad$bindS
-   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
+   let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) in sail2_state_monad$bindS
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
 
 
 (*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
+ ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ temp . 
-   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in state_monad$bindS
-   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in sail2_state_monad$bindS
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
 
 
 (*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ temp .  state_monad$bindS
-   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+ ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
 
 
 (*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ temp .  state_monad$bindS
+ ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) in state_monad$bindS
+   let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) in sail2_state_monad$bindS
    (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
 
 
 (*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
+ ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ temp . 
-   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in state_monad$bindS
+   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in sail2_state_monad$bindS
    (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
 
 
 (*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ temp .  state_monad$bindS
+ ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
    (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
 
 
 (*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  state_monad$bindS
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))  : ( 64 words$word) M) (\ (w__2 :
+ ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))  : ( 64 words$word) M) (\ (w__2 :
       64 words$word) . 
    wGPR rd w__2)))))`;
 
@@ -7163,9 +6809,9 @@ val _ = Define `
 (*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word))
+ ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word))
      : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd w__1))))`;
 
@@ -7173,134 +6819,134 @@ val _ = Define `
 (*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa=  (state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1))))`;
+ ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1))))`;
 
 
 (*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
-   let result = ((mult_vec w__0 w__1  :  128 words$word)) in state_monad$seqS
-   (state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)))
-   (state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
+   let result = ((mult_vec w__0 w__1  :  128 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
 
 
 (*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
-   let result = ((mults_vec w__0 w__1  :  128 words$word)) in state_monad$seqS
-   (state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)))
-   (state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
+   let result = ((mults_vec w__0 w__1  :  128 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
 
 
 (*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                     :  64 words$word)))))))))) then state_monad$bindS
+                     :  64 words$word)))))))))) then sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 : 32 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 : 32 bits) .  sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
-      state_monad$returnS (w__0, w__1)))
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS (w__0, w__1)))
     else
       let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
       let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
       let qi = (hardware_quot si ti) in
       let ri = (hardware_mod si ti) in
-      state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) qi  :  32 words$word),
-              (to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in state_monad$seqS
-   (state_monad$write_regS HI_ref ((sign_extend1 (( 64 : int):ii) r  :  64 words$word)))
-   (state_monad$write_regS LO_ref ((sign_extend1 (( 64 : int):ii) q  :  64 words$word))))))))`;
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) qi  :  32 words$word),
+              (to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q  :  64 words$word))))))))`;
 
 
 (*val execute_DIV : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  state_monad$bindS
+ ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
    (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                     :  64 words$word)))))))))) then state_monad$bindS
+                     :  64 words$word)))))))))) then sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 : 32 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 : 32 bits) .  sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
-      state_monad$returnS (w__0, w__1)))
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS (w__0, w__1)))
     else
       let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
       let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
       let qi = (hardware_quot si ti) in
       let ri = (si - ((ti * qi))) in
-      state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) qi  :  32 words$word),
-              (to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in state_monad$seqS
-   (state_monad$write_regS HI_ref ((sign_extend1 (( 64 : int):ii) r  :  64 words$word)))
-   (state_monad$write_regS LO_ref ((sign_extend1 (( 64 : int):ii) q  :  64 words$word))))))))`;
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) qi  :  32 words$word),
+              (to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q  :  64 words$word))))))))`;
 
 
 (*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
+ ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rsVal = (lem$w2ui w__0) in state_monad$bindS
+   let rsVal = (lem$w2ui w__0) in sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
-   let rtVal = (lem$w2ui w__1) in state_monad$bindS
-   (if (((rtVal = (( 0 : int):ii)))) then state_monad$bindS
+   let rtVal = (lem$w2ui w__1) in sail2_state_monad$bindS
+   (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
-      state_monad$returnS (w__2, w__3)))
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+      sail2_state_monad$returnS (w__2, w__3)))
     else
       let qi = (hardware_quot rsVal rtVal) in
       let ri = (hardware_mod rsVal rtVal) in
-      state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) qi  :  64 words$word),
-              (to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in state_monad$seqS
-   (state_monad$write_regS LO_ref q) (state_monad$write_regS HI_ref r))))))`;
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) qi  :  64 words$word),
+              (to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`;
 
 
 (*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt=  (state_monad$bindS
+ ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rsVal = (integer_word$w2i w__0) in state_monad$bindS
+   let rsVal = (integer_word$w2i w__0) in sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
-   let rtVal = (integer_word$w2i w__1) in state_monad$bindS
-   (if (((rtVal = (( 0 : int):ii)))) then state_monad$bindS
+   let rtVal = (integer_word$w2i w__1) in sail2_state_monad$bindS
+   (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
-      state_monad$returnS (w__2, w__3)))
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+      sail2_state_monad$returnS (w__2, w__3)))
     else
       let qi = (hardware_quot rsVal rtVal) in
       let ri = (rsVal - ((qi * rtVal))) in
-      state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) qi  :  64 words$word),
-              (to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in state_monad$seqS
-   (state_monad$write_regS LO_ref q) (state_monad$write_regS HI_ref r))))))`;
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) qi  :  64 words$word),
+              (to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`;
 
 
 (*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd ((add_vec w__0 w__1  :  64 words$word))))))`;
 
@@ -7308,18 +6954,19 @@ val _ = Define `
 (*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+   wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
 
 
 (*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let (sum65 : 65 bits) =
-     ((add_vec ((sign_extend1 (( 65 : int):ii) w__0  :  65 words$word)) ((sign_extend1 (( 65 : int):ii) imm  :  65 words$word))
+     ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0  :  65 words$word))
+        ((mips_sign_extend (( 65 : int):ii) imm  :  65 words$word))
        :  65 words$word)) in
    if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii)))))
           ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then
@@ -7330,11 +6977,12 @@ val _ = Define `
 (*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    let (sum65 : 65 bits) =
-     ((add_vec ((sign_extend1 (( 65 : int):ii) w__0  :  65 words$word)) ((sign_extend1 (( 65 : int):ii) w__1  :  65 words$word))
+     ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0  :  65 words$word))
+        ((mips_sign_extend (( 65 : int):ii) w__1  :  65 words$word))
        :  65 words$word)) in
    if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii)))))
           ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then
@@ -7345,20 +6993,20 @@ val _ = Define `
 (*val execute_ClearRegs : ClearRegSet -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_ClearRegs:ClearRegSet ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) regset m=  (state_monad$seqS (state_monad$seqS
+ ((execute_ClearRegs:ClearRegSet ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regset m=  (sail2_state_monad$seqS (sail2_state_monad$seqS
    (if ((((((regset = CLo))) \/ (((regset = CHi)))))) then checkCP2usable () 
-    else state_monad$returnS () )
+    else sail2_state_monad$returnS () )
    (if (((regset = CHi))) then
-      (state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () 
+      (sail2_state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () 
         (\ i unit_var . 
           let r =
-            ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) ((i + (( 16 : int):ii)))  :  5 words$word)) in state_monad$bindS
-          (state$and_boolS (state_monad$returnS ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r))) (\ (w__1 :
+            ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) ((i + (( 16 : int):ii)))  :  5 words$word)) in sail2_state_monad$bindS
+          (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r))) (\ (w__1 :
             bool) . 
           if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation r
-          else state_monad$returnS () )))
-    else state_monad$returnS () ))
-   (state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () 
+          else sail2_state_monad$returnS () )))
+    else sail2_state_monad$returnS () ))
+   (sail2_state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () 
      (\ i unit_var . 
        if ((bit_to_bool ((access_vec_dec m i)))) then
          (case regset of
@@ -7370,72 +7018,80 @@ val _ = Define `
               ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) ((i + (( 16 : int):ii)))
                  :  5 words$word)) ((zeros0 (( 64 : int):ii) ()   :  64 words$word))
          | CLo =>
-            writeCapReg ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) i  :  5 words$word)) null_cap
+            if (((i = (( 0 : int):ii)))) then sail2_state_monad$write_regS DDC_ref ((capStructToCapReg null_cap  :  257 words$word))
+            else
+              writeCapReg ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) i  :  5 words$word))
+                null_cap
          | CHi =>
             writeCapReg
               ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) ((i + (( 16 : int):ii)))
                  :  5 words$word)) null_cap
          )
-       else state_monad$returnS () ))))`;
+       else sail2_state_monad$returnS () ))))`;
 
 
 (*val execute_CWriteHwr : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb sel=  (state_monad$seqS
+ ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cb sel=  (sail2_state_monad$seqS
    (checkCP2usable () )
-   (let l__24 = (lem$w2ui sel) in state_monad$bindS
-   (if (((l__24 = (( 0 : int):ii)))) then state_monad$returnS (F, F)
-    else if (((l__24 = (( 1 : int):ii)))) then state_monad$returnS (F, F)
-    else if (((l__24 = (( 8 : int):ii)))) then state_monad$returnS (F, T)
-    else if (((l__24 = (( 22 : int):ii)))) then state_monad$returnS (T, F)
-    else if (((l__24 = (( 23 : int):ii)))) then state_monad$returnS (T, F)
-    else if (((l__24 = (( 29 : int):ii)))) then state_monad$returnS (T, T)
-    else if (((l__24 = (( 30 : int):ii)))) then state_monad$returnS (T, T)
-    else if (((l__24 = (( 31 : int):ii)))) then state_monad$returnS (T, T)
-    else SignalException ResI) (\ varstup .  let ((needSup : bool), (needAccessSys : bool)) = varstup in state_monad$bindS
+   (let p0_ = (lem$w2ui sel) in sail2_state_monad$bindS
+   (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS (F, F)
+    else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$returnS (F, F)
+    else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$returnS (F, T)
+    else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$returnS (T, F)
+    else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$returnS (T, F)
+    else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$returnS (T, T)
+    else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$returnS (T, T)
+    else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$returnS (T, T)
+    else SignalException ResI) (\ varstup .  let ((needSup : bool), (needAccessSys : bool)) = varstup in sail2_state_monad$bindS
    (register_inaccessible cb) (\ (w__8 : bool) . 
    if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
-     (state$and_boolS (state_monad$returnS needAccessSys)
-       ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) .  state_monad$returnS ((~ w__9))))) (\ (w__10 :
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state_monad$returnS needAccessSys)
+       ( sail2_state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9))))) (\ (w__10 :
        bool) . 
      if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel
-     else state_monad$bindS
-       (state$and_boolS (state_monad$returnS needSup)
-         ( state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . 
-          state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . 
+     else sail2_state_monad$bindS
+       (sail2_state$and_boolS (sail2_state_monad$returnS needSup)
+         ( sail2_state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . 
+          sail2_state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . 
        if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel
-       else state_monad$bindS
+       else sail2_state_monad$bindS
          (readCapReg cb) (\ capVal . 
-         let l__16 = (lem$w2ui sel) in
-         if (((l__16 = (( 0 : int):ii)))) then writeCapReg DDC capVal
-         else if (((l__16 = (( 1 : int):ii)))) then
-           state_monad$write_regS CTLSU_ref ((capStructToCapReg capVal  :  257 words$word))
-         else if (((l__16 = (( 8 : int):ii)))) then
-           state_monad$write_regS CTLSP_ref ((capStructToCapReg capVal  :  257 words$word))
-         else if (((l__16 = (( 22 : int):ii)))) then writeCapReg KR1C capVal
-         else if (((l__16 = (( 23 : int):ii)))) then writeCapReg KR2C capVal
-         else if (((l__16 = (( 29 : int):ii)))) then writeCapReg KCC capVal
-         else if (((l__16 = (( 30 : int):ii)))) then writeCapReg KDC capVal
-         else if (((l__16 = (( 31 : int):ii)))) then writeCapReg EPCC capVal
-         else state_monad$assert_expS F "should be unreachable code"))))))))`;
+         let p0_ = (lem$w2ui sel) in
+         if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$write_regS DDC_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 1 : int):ii)))) then
+           sail2_state_monad$write_regS CTLSU_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 8 : int):ii)))) then
+           sail2_state_monad$write_regS CTLSP_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 22 : int):ii)))) then
+           sail2_state_monad$write_regS KR1C_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 23 : int):ii)))) then
+           sail2_state_monad$write_regS KR2C_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 29 : int):ii)))) then
+           sail2_state_monad$write_regS KCC_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 30 : int):ii)))) then
+           sail2_state_monad$write_regS KDC_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((p0_ = (( 31 : int):ii)))) then
+           sail2_state_monad$write_regS EPCC_ref ((capStructToCapReg capVal  :  257 words$word))
+         else sail2_state_monad$assert_expS F "should be unreachable code"))))))))`;
 
 
 (*val execute_CUnseal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cs ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cs)) (\ cs_val .  state_monad$bindS
+   (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
    (readCapReg ct) (\ ct_val . 
-   let ct_cursor = (getCapCursor ct_val) in state_monad$bindS
+   let ct_cursor = (getCapCursor ct_val) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cs) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible ct) (\ (w__2 : bool) . 
        if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
        else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
@@ -7460,13 +7116,13 @@ val _ = Define `
 (*val execute_CToPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg ct)) (\ ct_val .  state_monad$bindS
-   (readCapReg cb) (\ cb_val .  state_monad$bindS
+   (readCapRegDDC ct)) (\ ct_val .  sail2_state_monad$bindS
+   (readCapReg cb) (\ cb_val .  sail2_state_monad$bindS
    (register_inaccessible cb) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible ct) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
      else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct
@@ -7489,19 +7145,19 @@ val _ = Define `
 (*val execute_CTestSubset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
    (readCapReg ct) (\ ct_val . 
    let ct_top = (getCapTop ct_val) in
    let ct_base = (getCapBase ct_val) in
    let ct_perms = ((getCapPerms ct_val  :  31 words$word)) in
    let cb_top = (getCapTop cb_val) in
    let cb_base = (getCapBase cb_val) in
-   let cb_perms = ((getCapPerms cb_val  :  31 words$word)) in state_monad$bindS
+   let cb_perms = ((getCapPerms cb_val  :  31 words$word)) in sail2_state_monad$bindS
    (register_inaccessible cb) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible ct) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
      else
@@ -7513,19 +7169,19 @@ val _ = Define `
          else if (((((and_vec ct_perms cb_perms  :  31 words$word)) <> ct_perms))) then
            (vec_of_bits [B0]  :  1 words$word)
          else (vec_of_bits [B1]  :  1 words$word)) in
-       wGPR rd ((zero_extend1 (( 64 : int):ii) result  :  64 words$word))))))))`;
+       wGPR rd ((mips_zero_extend (( 64 : int):ii) result  :  64 words$word))))))))`;
 
 
 (*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg ct)) (\ ct_val .  state_monad$bindS
-   (readCapReg cb) (\ cb_val .  state_monad$bindS
+   (readCapReg ct)) (\ ct_val .  sail2_state_monad$bindS
+   (readCapReg cb) (\ cb_val .  sail2_state_monad$bindS
    (register_inaccessible cb) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible ct) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
      else
@@ -7538,9 +7194,9 @@ val _ = Define `
 (*val execute_CStore : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> WordType -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> WordType -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs cb rt rd offset width conditional=  (state_monad$bindS (state_monad$seqS
+ ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> WordType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs cb rt rd offset width conditional=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
    (register_inaccessible cb) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
    else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7549,7 +7205,7 @@ val _ = Define `
      raise_c2_exception CapEx_PermitStoreViolation cb
    else
      let size1 = (wordWidthBytes width) in
-     let cursor = (getCapCursor cb_val) in state_monad$bindS
+     let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
      (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
      let vAddr =
        (((((cursor + ((lem$w2ui w__1)))) + ((size1 * ((integer_word$w2i offset))))))
@@ -7560,11 +7216,11 @@ val _ = Define `
        raise_c2_exception CapEx_LengthViolation cb
      else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
      else if ((~ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64
-     else state_monad$bindS
-       (TLBTranslate vAddr64 StoreData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
+     else sail2_state_monad$bindS
+       (TLBTranslate vAddr64 StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
        (rGPR rs  : ( 64 words$word) M) (\ rs_val . 
-       if conditional then state_monad$bindS
-         (state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__2 : 1 bits) .  state_monad$bindS
+       if conditional then sail2_state_monad$bindS
+         (sail2_state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__2 : 1 bits) .  sail2_state_monad$bindS
          (if ((bit_to_bool ((access_vec_dec w__2 (( 0 : int):ii))))) then
             (case width of
               B =>
@@ -7578,8 +7234,8 @@ val _ = Define `
                  ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
             | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rs_val
             )
-          else state_monad$returnS F) (\ (success : bool) . 
-         wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+          else sail2_state_monad$returnS F) (\ (success : bool) . 
+         wGPR rd ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
        else
          (case width of
            B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rs_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
@@ -7592,13 +7248,13 @@ val _ = Define `
 (*val execute_CSetOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  state_monad$bindS
+   (readCapReg cb)) (\ cb_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then
@@ -7618,12 +7274,12 @@ val _ = Define `
 (*val execute_CSetCause : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CSetCause:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSetCause:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (pcc_access_system_regs () )) (\ (w__0 : bool) . 
    if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation
-   else state_monad$bindS
-     (rGPR rt  : ( 64 words$word) M) (\ rt_val .  state_monad$seqS
+   else sail2_state_monad$bindS
+     (rGPR rt  : ( 64 words$word) M) (\ rt_val .  sail2_state_monad$seqS
      (set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))
      (set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))))))`;
 
@@ -7631,17 +7287,17 @@ val _ = Define `
 (*val execute_CSetBoundsImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*)
 
 val _ = Define `
- ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb imm=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb imm=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (readCapReg cb)) (\ cb_val . 
    let immU = (lem$w2ui imm) in
    let cursor = (getCapCursor cb_val) in
    let base = (getCapBase cb_val) in
    let top = (getCapTop cb_val) in
-   let newTop = (cursor + immU) in state_monad$bindS
+   let newTop = (cursor + immU) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7660,18 +7316,18 @@ val _ = Define `
 (*val execute_CSetBoundsExact : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapReg cb)) (\ cb_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let rt_val = (lem$w2ui w__0) in
    let cursor = (getCapCursor cb_val) in
    let base = (getCapBase cb_val) in
    let top = (getCapTop cb_val) in
-   let newTop = (cursor + rt_val) in state_monad$bindS
+   let newTop = (cursor + rt_val) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__1 : bool) . 
    if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__2 : bool) . 
      if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7690,18 +7346,18 @@ val _ = Define `
 (*val execute_CSetBounds : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapReg cb)) (\ cb_val .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let rt_val = (lem$w2ui w__0) in
    let cursor = (getCapCursor cb_val) in
    let base = (getCapBase cb_val) in
    let top = (getCapTop cb_val) in
-   let newTop = (cursor + rt_val) in state_monad$bindS
+   let newTop = (cursor + rt_val) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__1 : bool) . 
    if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__2 : bool) . 
      if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7720,19 +7376,19 @@ val _ = Define `
 (*val execute_CSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cs ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cs)) (\ cs_val .  state_monad$bindS
+   (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
    (readCapReg ct) (\ ct_val . 
    let ct_cursor = (getCapCursor ct_val) in
    let ct_top = (getCapTop ct_val) in
-   let ct_base = (getCapBase ct_val) in state_monad$bindS
+   let ct_base = (getCapBase ct_val) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cs) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible ct) (\ (w__2 : bool) . 
        if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
        else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
@@ -7755,13 +7411,13 @@ val _ = Define `
 (*val execute_CSC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb rt rd offset conditional=  (state_monad$bindS (state_monad$seqS
+ ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs cb rt rd offset conditional=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cs)) (\ cs_val .  state_monad$bindS
-   (readCapReg cb) (\ cb_val .  state_monad$bindS
+   (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
+   (readCapRegDDC cb) (\ cb_val .  sail2_state_monad$bindS
    (register_inaccessible cs) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7773,7 +7429,7 @@ val _ = Define `
      else if (((((~ cb_val.CapStruct_permit_store_local_cap)) /\ (((cs_val.CapStruct_tag /\ ((~ cs_val.CapStruct_global)))))))) then
        raise_c2_exception CapEx_PermitStoreLocalCapViolation cb
      else
-       let cursor = (getCapCursor cb_val) in state_monad$bindS
+       let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
        (rGPR rt  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
        let vAddr =
          (((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):ii) * ((integer_word$w2i offset))))))
@@ -7784,68 +7440,80 @@ val _ = Define `
          raise_c2_exception CapEx_LengthViolation cb
        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
        else if (((((vAddr % cap_size)) <> (( 0 : int):ii)))) then SignalExceptionBadAddr AdES vAddr64
-       else state_monad$bindS
+       else sail2_state_monad$bindS
          (TLBTranslateC vAddr64 StoreData  : (( 64 words$word # bool)) M) (\ varstup .  let (pAddr, noStoreCap) = varstup in
          if (((cs_val.CapStruct_tag /\ noStoreCap))) then
            raise_c2_exception CapEx_TLBNoStoreCap cs
-         else if conditional then state_monad$bindS
-           (state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__3 : 1 bits) .  state_monad$bindS
+         else if conditional then sail2_state_monad$bindS
+           (sail2_state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__3 : 1 bits) .  sail2_state_monad$bindS
            (if ((bit_to_bool ((access_vec_dec w__3 (( 0 : int):ii))))) then
               MEMw_tagged_conditional pAddr cs_val.CapStruct_tag
                 ((capStructToMemBits cs_val  :  256 words$word))
-            else state_monad$returnS F) (\ success . 
-           wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+            else sail2_state_monad$returnS F) (\ success . 
+           wGPR rd ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
          else MEMw_tagged pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val  :  256 words$word))))))))))`;
 
 
 (*val execute_CReturn : unit -> M unit*)
 
 val _ = Define `
- ((execute_CReturn:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__129=  (state_monad$seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`;
+ ((execute_CReturn:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__27=  (sail2_state_monad$seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`;
 
 
 (*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CReadHwr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd sel=  (state_monad$seqS
+ ((execute_CReadHwr:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd sel=  (sail2_state_monad$seqS
    (checkCP2usable () )
-   (let l__8 = (lem$w2ui sel) in state_monad$bindS
-   (if (((l__8 = (( 0 : int):ii)))) then state_monad$returnS (F, F)
-    else if (((l__8 = (( 1 : int):ii)))) then state_monad$returnS (F, F)
-    else if (((l__8 = (( 8 : int):ii)))) then state_monad$returnS (F, T)
-    else if (((l__8 = (( 22 : int):ii)))) then state_monad$returnS (T, F)
-    else if (((l__8 = (( 23 : int):ii)))) then state_monad$returnS (T, F)
-    else if (((l__8 = (( 29 : int):ii)))) then state_monad$returnS (T, T)
-    else if (((l__8 = (( 30 : int):ii)))) then state_monad$returnS (T, T)
-    else if (((l__8 = (( 31 : int):ii)))) then state_monad$returnS (T, T)
-    else SignalException ResI) (\ varstup .  let ((needSup : bool), (needAccessSys : bool)) = varstup in state_monad$bindS
+   (let p0_ = (lem$w2ui sel) in sail2_state_monad$bindS
+   (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS (F, F)
+    else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$returnS (F, F)
+    else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$returnS (F, T)
+    else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$returnS (T, F)
+    else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$returnS (T, F)
+    else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$returnS (T, T)
+    else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$returnS (T, T)
+    else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$returnS (T, T)
+    else SignalException ResI) (\ varstup .  let ((needSup : bool), (needAccessSys : bool)) = varstup in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__8 : bool) . 
    if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
-     (state$and_boolS (state_monad$returnS needAccessSys)
-       ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) .  state_monad$returnS ((~ w__9))))) (\ (w__10 :
+   else sail2_state_monad$bindS
+     (sail2_state$and_boolS (sail2_state_monad$returnS needAccessSys)
+       ( sail2_state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) .  sail2_state_monad$returnS ((~ w__9))))) (\ (w__10 :
        bool) . 
      if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel
-     else state_monad$bindS
-       (state$and_boolS (state_monad$returnS needSup)
-         ( state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . 
-          state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . 
+     else sail2_state_monad$bindS
+       (sail2_state$and_boolS (sail2_state_monad$returnS needSup)
+         ( sail2_state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . 
+          sail2_state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . 
        if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel
        else
-         let l__0 = (lem$w2ui sel) in state_monad$bindS
-         (if (((l__0 = (( 0 : int):ii)))) then readCapReg DDC
-          else if (((l__0 = (( 1 : int):ii)))) then state_monad$bindS
-            (state_monad$read_regS CTLSU_ref  : ( 257 words$word) M) (\ (w__14 :  257 words$word) . 
-            state_monad$returnS ((capRegToCapStruct w__14)))
-          else if (((l__0 = (( 8 : int):ii)))) then state_monad$bindS
-            (state_monad$read_regS CTLSP_ref  : ( 257 words$word) M) (\ (w__15 :  257 words$word) . 
-            state_monad$returnS ((capRegToCapStruct w__15)))
-          else if (((l__0 = (( 22 : int):ii)))) then readCapReg KR1C
-          else if (((l__0 = (( 23 : int):ii)))) then readCapReg KR2C
-          else if (((l__0 = (( 29 : int):ii)))) then readCapReg KCC
-          else if (((l__0 = (( 30 : int):ii)))) then readCapReg KDC
-          else if (((l__0 = (( 31 : int):ii)))) then readCapReg EPCC
-          else state_monad$seqS (state_monad$assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal :
+         let p0_ = (lem$w2ui sel) in sail2_state_monad$bindS
+         (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS DDC_ref  : ( 257 words$word) M) (\ (w__13 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__13)))
+          else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS CTLSU_ref  : ( 257 words$word) M) (\ (w__14 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__14)))
+          else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS CTLSP_ref  : ( 257 words$word) M) (\ (w__15 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__15)))
+          else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS KR1C_ref  : ( 257 words$word) M) (\ (w__16 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__16)))
+          else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS KR2C_ref  : ( 257 words$word) M) (\ (w__17 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__17)))
+          else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS KCC_ref  : ( 257 words$word) M) (\ (w__18 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__18)))
+          else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS KDC_ref  : ( 257 words$word) M) (\ (w__19 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__19)))
+          else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$bindS
+            (sail2_state_monad$read_regS EPCC_ref  : ( 257 words$word) M) (\ (w__20 :  257 words$word) . 
+            sail2_state_monad$returnS ((capRegToCapStruct w__20)))
+          else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal :
            CapStruct) . 
          writeCapReg cd capVal))))))))`;
 
@@ -7853,15 +7521,15 @@ val _ = Define `
 (*val execute_CPtrCmp : mword ty5 -> mword ty5 -> mword ty5 -> CPtrCmpOp -> M unit*)
 
 val _ = Define `
- ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> CPtrCmpOp ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct op=  (state_monad$bindS (state_monad$seqS
+ ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> CPtrCmpOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct op=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible ct) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
-     else state_monad$bindS
-       (readCapReg cb) (\ cb_val .  state_monad$bindS
+     else sail2_state_monad$bindS
+       (readCapReg cb) (\ cb_val .  sail2_state_monad$bindS
        (readCapReg ct) (\ ct_val . 
        let equal = F in
        let ltu = F in
@@ -7895,39 +7563,39 @@ val _ = Define `
          | CEXEQ => (cb_val = ct_val)
          | CNEXEQ => (cb_val <> ct_val)
          )) in
-       wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits cmp  :  1 words$word))  :  64 words$word))))))))`;
+       wGPR rd ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits cmp  :  1 words$word))  :  64 words$word))))))))`;
 
 
 (*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt ismovn=  (state_monad$bindS (state_monad$seqS
+ ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt ismovn=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cd)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (rGPR rt  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
        if ((bits_to_bool
               ((xor_vec
                   ((bool_to_bits (((w__2 = ((zeros0 (( 64 : int):ii) ()   :  64 words$word)))))  :  1 words$word))
                   ((bool_to_bits ismovn  :  1 words$word))
-                 :  1 words$word)))) then state_monad$bindS
+                 :  1 words$word)))) then sail2_state_monad$bindS
          (readCapReg cb) (\ (w__3 : CapStruct) .  writeCapReg cd w__3)
-       else state_monad$returnS () )))))`;
+       else sail2_state_monad$returnS () )))))`;
 
 
 (*val execute_CLoad : mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> bool -> WordType -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> WordType -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6=
+ ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> WordType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6=
     (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in
    (case merge_var of
-     (rd, cb, rt, offset, signext, B, linked) => state_monad$bindS (state_monad$seqS
+     (rd, cb, rt, offset, signext, B, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS
       (checkCP2usable () )
-      (readCapReg cb)) (\ cb_val .  state_monad$bindS
+      (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
       (register_inaccessible cb) (\ (w__0 : bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7935,7 +7603,7 @@ val _ = Define `
       else if ((~ cb_val.CapStruct_permit_load)) then
         raise_c2_exception CapEx_PermitLoadViolation cb
       else
-        let cursor = (getCapCursor cb_val) in state_monad$bindS
+        let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
         (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
         let vAddr =
           (((((cursor + ((lem$w2ui w__1)))) + (((( 1 : int):ii) * ((integer_word$w2i offset))))))
@@ -7946,20 +7614,20 @@ val _ = Define `
           raise_c2_exception CapEx_LengthViolation cb
         else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
         else if ((~ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64
-        else state_monad$bindS
-          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
-          (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS
-             (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
-             (state_monad$write_regS CP0LLAddr_ref pAddr))
+        else sail2_state_monad$bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+          (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+             (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+             (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
              (MEMr_reserve_wrapper pAddr (( 1 : int):ii)  : ( 8 words$word) M)) (\ (w__2 :  8 words$word) . 
-             state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
-           else state_monad$bindS
+             sail2_state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else sail2_state_monad$bindS
              (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii)  : ( 8 words$word) M) (\ (w__3 :  8 words$word) . 
-             state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
+             sail2_state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
           wGPR rd memResult)))))
-   | (rd, cb, rt, offset, signext, D, linked) => state_monad$bindS (state_monad$seqS
+   | (rd, cb, rt, offset, signext, D, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS
       (checkCP2usable () )
-      (readCapReg cb)) (\ cb_val .  state_monad$bindS
+      (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
       (register_inaccessible cb) (\ (w__0 : bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7967,7 +7635,7 @@ val _ = Define `
       else if ((~ cb_val.CapStruct_permit_load)) then
         raise_c2_exception CapEx_PermitLoadViolation cb
       else
-        let cursor = (getCapCursor cb_val) in state_monad$bindS
+        let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
         (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
         let vAddr =
           (((((cursor + ((lem$w2ui w__1)))) + (((( 8 : int):ii) * ((integer_word$w2i offset))))))
@@ -7978,20 +7646,20 @@ val _ = Define `
           raise_c2_exception CapEx_LengthViolation cb
         else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
         else if ((~ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64
-        else state_monad$bindS
-          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
-          (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS
-             (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
-             (state_monad$write_regS CP0LLAddr_ref pAddr))
+        else sail2_state_monad$bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+          (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+             (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+             (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
              (MEMr_reserve_wrapper pAddr (( 8 : int):ii)  : ( 64 words$word) M)) (\ (w__2 :  64 words$word) . 
-             state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
-           else state_monad$bindS
+             sail2_state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else sail2_state_monad$bindS
              (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
-             state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
+             sail2_state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
           wGPR rd memResult)))))
-   | (rd, cb, rt, offset, signext, H, linked) => state_monad$bindS (state_monad$seqS
+   | (rd, cb, rt, offset, signext, H, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS
       (checkCP2usable () )
-      (readCapReg cb)) (\ cb_val .  state_monad$bindS
+      (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
       (register_inaccessible cb) (\ (w__0 : bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -7999,7 +7667,7 @@ val _ = Define `
       else if ((~ cb_val.CapStruct_permit_load)) then
         raise_c2_exception CapEx_PermitLoadViolation cb
       else
-        let cursor = (getCapCursor cb_val) in state_monad$bindS
+        let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
         (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
         let vAddr =
           (((((cursor + ((lem$w2ui w__1)))) + (((( 2 : int):ii) * ((integer_word$w2i offset))))))
@@ -8010,20 +7678,20 @@ val _ = Define `
           raise_c2_exception CapEx_LengthViolation cb
         else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
         else if ((~ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64
-        else state_monad$bindS
-          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
-          (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS
-             (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
-             (state_monad$write_regS CP0LLAddr_ref pAddr))
+        else sail2_state_monad$bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+          (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+             (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+             (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
              (MEMr_reserve_wrapper pAddr (( 2 : int):ii)  : ( 16 words$word) M)) (\ (w__2 :  16 words$word) . 
-             state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
-           else state_monad$bindS
+             sail2_state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else sail2_state_monad$bindS
              (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii)  : ( 16 words$word) M) (\ (w__3 :  16 words$word) . 
-             state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
+             sail2_state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
           wGPR rd memResult)))))
-   | (rd, cb, rt, offset, signext, W0, linked) => state_monad$bindS (state_monad$seqS
+   | (rd, cb, rt, offset, signext, W0, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS
       (checkCP2usable () )
-      (readCapReg cb)) (\ cb_val .  state_monad$bindS
+      (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
       (register_inaccessible cb) (\ (w__0 : bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -8031,7 +7699,7 @@ val _ = Define `
       else if ((~ cb_val.CapStruct_permit_load)) then
         raise_c2_exception CapEx_PermitLoadViolation cb
       else
-        let cursor = (getCapCursor cb_val) in state_monad$bindS
+        let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
         (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
         let vAddr =
           (((((cursor + ((lem$w2ui w__1)))) + (((( 4 : int):ii) * ((integer_word$w2i offset))))))
@@ -8042,29 +7710,29 @@ val _ = Define `
           raise_c2_exception CapEx_LengthViolation cb
         else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
         else if ((~ ((isAddressAligned vAddr64 W0)))) then SignalExceptionBadAddr AdEL vAddr64
-        else state_monad$bindS
-          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  state_monad$bindS
-          (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS
-             (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
-             (state_monad$write_regS CP0LLAddr_ref pAddr))
+        else sail2_state_monad$bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+          (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+             (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+             (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
              (MEMr_reserve_wrapper pAddr (( 4 : int):ii)  : ( 32 words$word) M)) (\ (w__2 :  32 words$word) . 
-             state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
-           else state_monad$bindS
+             sail2_state_monad$returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else sail2_state_monad$bindS
              (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__3 :  32 words$word) . 
-             state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
+             sail2_state_monad$returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 bits) . 
           wGPR rd memResult)))))
    )))`;
 
 
-(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*)
+(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty16 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt offset linked=  (state_monad$bindS (state_monad$seqS
+ ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(16)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt offset linked=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -8072,7 +7740,7 @@ val _ = Define `
      else if ((~ cb_val.CapStruct_permit_load)) then
        raise_c2_exception CapEx_PermitLoadViolation cb
      else
-       let cursor = (getCapCursor cb_val) in state_monad$bindS
+       let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS
        (rGPR rt  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
        let vAddr =
          (((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):ii) * ((integer_word$w2i offset))))))
@@ -8083,22 +7751,22 @@ val _ = Define `
          raise_c2_exception CapEx_LengthViolation cb
        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
        else if (((((vAddr % cap_size)) <> (( 0 : int):ii)))) then SignalExceptionBadAddr AdEL vAddr64
-       else state_monad$bindS
+       else sail2_state_monad$bindS
          (TLBTranslateC vAddr64 LoadData  : (( 64 words$word # bool)) M) (\ varstup .  let (pAddr, suppressTag) = varstup in
          let cd = (lem$w2ui cd) in
-         if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS
-           (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
-           (state_monad$write_regS CP0LLAddr_ref pAddr))
+         if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+           (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+           (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
            (MEMr_tagged_reserve pAddr  : ((bool #  256 words$word)) M)) (\ varstup .  let (tag, mem) = varstup in
-           state_monad$write_regS
+           sail2_state_monad$write_regS
              ((access_list_dec CapRegs cd  : (regstate, register_value, ( 257 words$word)) register_ref))
              ((memBitsToCapBits
                  (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag))))))))
                  mem
                 :  257 words$word)))
-         else state_monad$bindS
+         else sail2_state_monad$bindS
            (MEMr_tagged pAddr  : ((bool #  256 words$word)) M) (\ varstup .  let (tag, mem) = varstup in
-           state_monad$write_regS
+           sail2_state_monad$write_regS
              ((access_list_dec CapRegs cd  : (regstate, register_value, ( 257 words$word)) register_ref))
              ((memBitsToCapBits
                  (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag))))))))
@@ -8109,15 +7777,15 @@ val _ = Define `
 (*val execute_CJALR : mword ty5 -> mword ty5 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb link=  (state_monad$bindS (state_monad$seqS
+ ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb link=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (readCapReg cb)) (\ cb_val . 
    let cb_ptr = (getCapCursor cb_val) in
    let cb_top = (getCapTop cb_val) in
-   let cb_base = (getCapBase cb_val) in state_monad$bindS
-   (state$and_boolS (state_monad$returnS link) ((register_inaccessible cd))) (\ (w__1 : bool) . 
+   let cb_base = (getCapBase cb_val) in sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS link) ((register_inaccessible cd))) (\ (w__1 : bool) . 
    if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__2 : bool) . 
      if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -8128,28 +7796,28 @@ val _ = Define `
      else if ((((cb_ptr + (( 4 : int):ii))) > cb_top)) then
        raise_c2_exception CapEx_LengthViolation cb
      else if (((((cb_ptr % (( 4 : int):ii))) <> (( 0 : int):ii)))) then SignalException AdEL
-     else state_monad$seqS
-       (if link then state_monad$bindS
-          (state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__3 :  257 words$word) . 
-          let pcc = (capRegToCapStruct w__3) in state_monad$bindS
-          (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+     else sail2_state_monad$seqS
+       (if link then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__3 :  257 words$word) . 
+          let pcc = (capRegToCapStruct w__3) in sail2_state_monad$bindS
+          (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
           let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__4 (( 8 : int):ii)  :  64 words$word))) in
           if success then writeCapReg cd linkCap
-          else state_monad$assert_expS F ""))
-        else state_monad$returnS () )
+          else sail2_state_monad$assert_expS F ""))
+        else sail2_state_monad$returnS () )
        (execute_branch_pcc cb_val))))))`;
 
 
 (*val execute_CIncOffsetImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*)
 
 val _ = Define `
- ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb imm=  (state_monad$bindS (state_monad$seqS
+ ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb imm=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (readCapReg cb)) (\ cb_val . 
-   let (imm64 : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm  :  64 words$word)) in state_monad$bindS
+   let (imm64 : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word)) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then
@@ -8169,13 +7837,13 @@ val _ = Define `
 (*val execute_CIncOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  state_monad$bindS
+   (readCapReg cb)) (\ cb_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if (((cb_val.CapStruct_tag /\ (((cb_val.CapStruct_sealed /\ (((rt_val <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -8199,65 +7867,67 @@ val _ = Define `
 (*val execute_CGetType : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetType:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetType:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      wGPR rd
-       (if capVal.CapStruct_sealed then (zero_extend1 (( 64 : int):ii) capVal.CapStruct_otype  :  64 words$word)
+       (if capVal.CapStruct_sealed then
+          (mips_zero_extend (( 64 : int):ii) capVal.CapStruct_otype  :  64 words$word)
         else (replicate_bits ((cast_unit_vec0 B1  :  1 words$word)) (( 64 : int):ii)  :  64 words$word))))))`;
 
 
 (*val execute_CGetTag : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetTag:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetTag:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      wGPR rd
-       ((zero_extend1 (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_tag  :  1 words$word))  :  64 words$word))))))`;
+       ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_tag  :  1 words$word))  :  64 words$word))))))`;
 
 
 (*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetSealed:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetSealed:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      wGPR rd
-       ((zero_extend1 (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_sealed  :  1 words$word))  :  64 words$word))))))`;
+       ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_sealed  :  1 words$word))
+          :  64 words$word))))))`;
 
 
 (*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetPerm:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetPerm:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
-     wGPR rd ((zero_extend1 (( 64 : int):ii) ((getCapPerms capVal  :  31 words$word))  :  64 words$word))))))`;
+     wGPR rd ((mips_zero_extend (( 64 : int):ii) ((getCapPerms capVal  :  31 words$word))  :  64 words$word))))))`;
 
 
 (*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd rs=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd rs=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cd)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
-     (state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__1 :  257 words$word) . 
-     let pcc = (capRegToCapStruct w__1) in state_monad$bindS
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__1 :  257 words$word) . 
+     let pcc = (capRegToCapStruct w__1) in sail2_state_monad$bindS
      (rGPR rs  : ( 64 words$word) M) (\ rs_val . 
      let (success, newPCC) = (setCapOffset pcc rs_val) in
      if success then writeCapReg cd newPCC
@@ -8267,26 +7937,26 @@ val _ = Define `
 (*val execute_CGetPCC : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetPCC:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetPCC:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cd)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
-     (state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__1 :  257 words$word) . 
-     let pcc = (capRegToCapStruct w__1) in state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
-     let (success, pcc2) = (setCapOffset pcc w__2) in state_monad$seqS
-     (state_monad$assert_expS success "") (writeCapReg cd pcc2))))))`;
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PCC_ref  : ( 257 words$word) M) (\ (w__1 :  257 words$word) . 
+     let pcc = (capRegToCapStruct w__1) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+     let (success, pcc2) = (setCapOffset pcc w__2) in sail2_state_monad$seqS
+     (sail2_state_monad$assert_expS success "") (writeCapReg cd pcc2))))))`;
 
 
 (*val execute_CGetOffset : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetOffset:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetOffset:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      wGPR rd
        ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ((getCapOffset capVal))  :  64 words$word))))))`;
@@ -8295,11 +7965,11 @@ val _ = Define `
 (*val execute_CGetLen : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetLen:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetLen:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      let len65 = (getCapLength capVal) in
      wGPR rd
@@ -8312,23 +7982,23 @@ val _ = Define `
 (*val execute_CGetCause : mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetCause:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetCause:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (pcc_access_system_regs () )) (\ (w__0 : bool) . 
    if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation
-   else state_monad$bindS
-     (state_monad$read_regS CapCause_ref) (\ (w__1 : CapCauseReg) . 
-     wGPR rd ((zero_extend1 (( 64 : int):ii) ((get_CapCauseReg w__1  :  16 words$word))  :  64 words$word))))))`;
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CapCause_ref) (\ (w__1 : CapCauseReg) . 
+     wGPR rd ((mips_zero_extend (( 64 : int):ii) ((get_CapCauseReg_bits w__1  :  16 words$word))  :  64 words$word))))))`;
 
 
 (*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetBase:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetBase:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      wGPR rd
        ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ((getCapBase capVal))  :  64 words$word))))))`;
@@ -8337,11 +8007,11 @@ val _ = Define `
 (*val execute_CGetAddr : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CGetAddr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CGetAddr:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ capVal . 
      wGPR rd
        ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ((getCapCursor capVal))  :  64 words$word))))))`;
@@ -8350,16 +8020,20 @@ val _ = Define `
 (*val execute_CFromPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  state_monad$bindS
+   (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-     else if (((rt = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then writeCapReg cd null_cap
+     else if (((rt_val = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                   :  64 words$word)))) then
+       writeCapReg cd null_cap
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
      else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
      else
@@ -8377,19 +8051,19 @@ val _ = Define `
 (*val execute_CCopyType : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapReg cb)) (\ cb_val .  sail2_state_monad$bindS
    (readCapReg ct) (\ ct_val . 
    let cb_base = (getCapBase cb_val) in
    let cb_top = (getCapTop cb_val) in
-   let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in state_monad$bindS
+   let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible ct) (\ (w__2 : bool) . 
        if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
        else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -8401,8 +8075,8 @@ val _ = Define `
            let (success, cap) =
              (setCapOffset cb_val
                ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ((ct_otype - cb_base))
-                  :  64 words$word))) in state_monad$seqS
-           (state_monad$assert_expS success "") (writeCapReg cd cap)
+                  :  64 words$word))) in sail2_state_monad$seqS
+           (sail2_state_monad$assert_expS success "") (writeCapReg cd cap)
        else
          writeCapReg cd
            ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1  :  1 words$word)) (( 64 : int):ii)  :  64 words$word)))))))))))`;
@@ -8411,26 +8085,26 @@ val _ = Define `
 (*val execute_CClearTag : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CClearTag:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CClearTag:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cd)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-     else state_monad$bindS (readCapReg cb) (\ cb_val .  writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`;
+     else sail2_state_monad$bindS (readCapReg cb) (\ cb_val .  writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`;
 
 
 (*val execute_CCheckType : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CCheckType:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb=  (state_monad$bindS (state_monad$seqS
+ ((execute_CCheckType:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs cb=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cs)) (\ cs_val .  state_monad$bindS
-   (readCapReg cb) (\ cb_val .  state_monad$bindS
+   (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
+   (readCapReg cb) (\ cb_val .  sail2_state_monad$bindS
    (register_inaccessible cs) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
@@ -8439,38 +8113,38 @@ val _ = Define `
      else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb
      else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then
        raise_c2_exception CapEx_TypeViolation cs
-     else state_monad$returnS () ))))))`;
+     else sail2_state_monad$returnS () ))))))`;
 
 
 (*val execute_CCheckPerm : mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (readCapReg cs)) (\ cs_val . 
    let (cs_perms : 64 bits) =
-     ((zero_extend1 (( 64 : int):ii) ((getCapPerms cs_val  :  31 words$word))  :  64 words$word)) in state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rt_perms .  state_monad$bindS
+     ((mips_zero_extend (( 64 : int):ii) ((getCapPerms cs_val  :  31 words$word))  :  64 words$word)) in sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_perms .  sail2_state_monad$bindS
    (register_inaccessible cs) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
    else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
    else if (((((and_vec cs_perms rt_perms  :  64 words$word)) <> rt_perms))) then
      raise_c2_exception CapEx_UserDefViolation cs
-   else state_monad$returnS () )))))`;
+   else sail2_state_monad$returnS () )))))`;
 
 
 (*val execute_CCall : mword ty5 -> mword ty5 -> mword ty11 -> M unit*)
 
 val _ = Define `
- ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb b__151=
-    (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) then state_monad$bindS (state_monad$seqS
+ ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs cb b__151=
+    (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
      (checkCP2usable () )
-     (readCapReg cs)) (\ cs_val .  state_monad$bindS
+     (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
      (readCapReg cb) (\ cb_val . 
-     let cs_cursor = (getCapCursor cs_val) in state_monad$bindS
+     let cs_cursor = (getCapCursor cs_val) in sail2_state_monad$bindS
      (register_inaccessible cs) (\ (w__0 : bool) . 
      if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible cb) (\ (w__1 : bool) . 
        if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
        else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
@@ -8488,14 +8162,14 @@ val _ = Define `
        else if ((cs_cursor >= ((getCapTop cs_val)))) then
          raise_c2_exception CapEx_LengthViolation cs
        else raise_c2_exception CapEx_CallTrap cs))))
-   else state_monad$bindS (state_monad$seqS
+   else sail2_state_monad$bindS (sail2_state_monad$seqS
      (checkCP2usable () )
-     (readCapReg cs)) (\ cs_val .  state_monad$bindS
+     (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
      (readCapReg cb) (\ cb_val . 
-     let cs_cursor = (getCapCursor cs_val) in state_monad$bindS
+     let cs_cursor = (getCapCursor cs_val) in sail2_state_monad$bindS
      (register_inaccessible cs) (\ (w__2 : bool) . 
      if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible cb) (\ (w__3 : bool) . 
        if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
        else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
@@ -8516,12 +8190,12 @@ val _ = Define `
          raise_c2_exception CapEx_LengthViolation cs
        else if ((cs_cursor >= ((getCapTop cs_val)))) then
          raise_c2_exception CapEx_LengthViolation cs
-       else state_monad$seqS (state_monad$seqS
+       else sail2_state_monad$seqS (sail2_state_monad$seqS
          (execute_branch_pcc
            (cs_val with<|
              CapStruct_sealed := F; CapStruct_otype := ((zeros0 (( 24 : int):ii) ()   :  24 words$word))|>))
-         (state_monad$write_regS inCCallDelay_ref (vec_of_bits [B1]  :  1 words$word)))
-         (state_monad$write_regS
+         (sail2_state_monad$write_regS inCCallDelay_ref (vec_of_bits [B1]  :  1 words$word)))
+         (sail2_state_monad$write_regS
            C26_ref
            ((capStructToCapReg
                (cb_val with<|
@@ -8532,19 +8206,19 @@ val _ = Define `
 (*val execute_CCSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cs ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cs)) (\ cs_val .  state_monad$bindS
+   (readCapReg cs)) (\ cs_val .  sail2_state_monad$bindS
    (readCapReg ct) (\ ct_val . 
    let ct_cursor = (getCapCursor ct_val) in
    let ct_top = (getCapTop ct_val) in
-   let ct_base = (getCapBase ct_val) in state_monad$bindS
+   let ct_base = (getCapBase ct_val) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cs) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible ct) (\ (w__2 : bool) . 
        if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
        else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
@@ -8569,9 +8243,9 @@ val _ = Define `
 (*val execute_CBuildCap : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb ct=  (state_monad$bindS (state_monad$seqS
+ ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb ct=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
+   (readCapRegDDC cb)) (\ cb_val .  sail2_state_monad$bindS
    (readCapReg ct) (\ ct_val . 
    let cb_base = (getCapBase cb_val) in
    let ct_base = (getCapBase ct_val) in
@@ -8579,13 +8253,13 @@ val _ = Define `
    let ct_top = (getCapTop ct_val) in
    let cb_perms = ((getCapPerms cb_val  :  31 words$word)) in
    let ct_perms = ((getCapPerms ct_val  :  31 words$word)) in
-   let ct_offset = (getCapOffset ct_val) in state_monad$bindS
+   let ct_offset = (getCapOffset ct_val) in sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-     else state_monad$bindS
+     else sail2_state_monad$bindS
        (register_inaccessible ct) (\ (w__2 : bool) . 
        if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
        else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -8603,18 +8277,18 @@ val _ = Define `
          let (representable, cd2) =
            (setCapOffset cd1
              ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ct_offset  :  64 words$word))) in
-         let cd3 = (setCapPerms cd2 ct_perms) in state_monad$seqS (state_monad$seqS
-         (state_monad$assert_expS exact "") (state_monad$assert_expS representable "")) (writeCapReg cd cd3))))))))`;
+         let cd3 = (setCapPerms cd2 ct_perms) in sail2_state_monad$seqS (sail2_state_monad$seqS
+         (sail2_state_monad$assert_expS exact "") (sail2_state_monad$assert_expS representable "")) (writeCapReg cd cd3))))))))`;
 
 
 (*val execute_CBZ : mword ty5 -> mword ty16 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb imm notzero=  (state_monad$bindS (state_monad$seqS
+ ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cb imm notzero=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ (w__1 : CapStruct) . 
      if ((bits_to_bool
             ((xor_vec ((bool_to_bits (((w__1 = null_cap)))  :  1 words$word))
@@ -8622,23 +8296,23 @@ val _ = Define `
                :  1 words$word)))) then
        let (offset : 64 bits) =
          ((add_vec_int
-            ((sign_extend1 (( 64 : int):ii)
+            ((mips_sign_extend (( 64 : int):ii)
                 ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
                :  64 words$word)) (( 4 : int):ii)
-           :  64 words$word)) in state_monad$bindS
-       (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+           :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
        execute_branch ((add_vec w__2 offset  :  64 words$word)))
-     else state_monad$returnS () ))))`;
+     else sail2_state_monad$returnS () ))))`;
 
 
 (*val execute_CBX : mword ty5 -> mword ty16 -> bool -> M unit*)
 
 val _ = Define `
- ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb imm notset=  (state_monad$bindS (state_monad$seqS
+ ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cb imm notset=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
    (register_inaccessible cb)) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (readCapReg cb) (\ (w__1 : CapStruct) . 
      if ((bits_to_bool
             ((xor_vec ((bool_to_bits w__1.CapStruct_tag  :  1 words$word))
@@ -8646,25 +8320,25 @@ val _ = Define `
                :  1 words$word)))) then
        let (offset : 64 bits) =
          ((add_vec_int
-            ((sign_extend1 (( 64 : int):ii)
+            ((mips_sign_extend (( 64 : int):ii)
                 ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
                :  64 words$word)) (( 4 : int):ii)
-           :  64 words$word)) in state_monad$bindS
-       (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+           :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
        execute_branch ((add_vec w__2 offset  :  64 words$word)))
-     else state_monad$returnS () ))))`;
+     else sail2_state_monad$returnS () ))))`;
 
 
 (*val execute_CAndPerm : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt=  (state_monad$bindS (state_monad$seqS
+ ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt=  (sail2_state_monad$bindS (sail2_state_monad$seqS
    (checkCP2usable () )
-   (readCapReg cb)) (\ cb_val .  state_monad$bindS
-   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  state_monad$bindS
+   (readCapReg cb)) (\ cb_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val .  sail2_state_monad$bindS
    (register_inaccessible cd) (\ (w__0 : bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
-   else state_monad$bindS
+   else sail2_state_monad$bindS
      (register_inaccessible cb) (\ (w__1 : bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
@@ -8680,7 +8354,7 @@ val _ = Define `
 (*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base op imm=  (checkCP0Access () ))`;
+ ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base op imm=  (checkCP0Access () ))`;
 
 
 (*val execute_C2Dump : mword ty5 -> unit*)
@@ -8692,14 +8366,14 @@ val _ = Define `
 (*val execute_BREAK : unit -> M unit*)
 
 val _ = Define `
- ((execute_BREAK:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__120=  (SignalException Bp))`;
+ ((execute_BREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__18=  (SignalException Bp))`;
 
 
 (*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*)
 
 val _ = Define `
- ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rd imm ne likely=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd imm ne likely=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rd  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    if ((bits_to_bool
           ((xor_vec ((bool_to_bits (((w__0 = w__1)))  :  1 words$word))
@@ -8707,55 +8381,57 @@ val _ = Define `
              :  1 words$word)))) then
      let (offset : 64 bits) =
        ((add_vec_int
-          ((sign_extend1 (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+          ((mips_sign_extend (( 64 : int):ii)
+              ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
              :  64 words$word)) (( 4 : int):ii)
-         :  64 words$word)) in state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+         :  64 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
      execute_branch ((add_vec w__2 offset  :  64 words$word)))
-   else if likely then state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
-     state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii)  :  64 words$word)))
-   else state_monad$returnS () ))))`;
+   else if likely then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
+     sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii)  :  64 words$word)))
+   else sail2_state_monad$returnS () ))))`;
 
 
 (*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*)
 
 val _ = Define `
- ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs imm cmp link likely=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
-   let linkVal = ((add_vec_int w__0 (( 8 : int):ii)  :  64 words$word)) in state_monad$bindS
+ ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp link likely=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+   let linkVal = ((add_vec_int w__0 (( 8 : int):ii)  :  64 words$word)) in sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ regVal . 
    let condition =
-     (compare cmp regVal ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in state_monad$seqS
+     (compare cmp regVal ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in sail2_state_monad$seqS
    (if condition then
       let (offset : 64 bits) =
         ((add_vec_int
-           ((sign_extend1 (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+           ((mips_sign_extend (( 64 : int):ii)
+               ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
               :  64 words$word)) (( 4 : int):ii)
-          :  64 words$word)) in state_monad$bindS
-      (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+          :  64 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
       execute_branch ((add_vec w__1 offset  :  64 words$word)))
-    else if likely then state_monad$bindS
-      (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
-      state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii)  :  64 words$word)))
-    else state_monad$returnS () )
+    else if likely then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+      sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii)  :  64 words$word)))
+    else sail2_state_monad$returnS () )
    (if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) linkVal
-   else state_monad$returnS () )))))`;
+   else sail2_state_monad$returnS () )))))`;
 
 
 (*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+   wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
 
 
 (*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    wGPR rd ((and_vec w__0 w__1  :  64 words$word))))))`;
 
@@ -8763,15 +8439,15 @@ val _ = Define `
 (*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ opA .  state_monad$bindS
+ ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ opB . 
-   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
    else
      wGPR rd
-       ((sign_extend1 (( 64 : int):ii)
+       ((mips_sign_extend (( 64 : int):ii)
            ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
                ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
               :  32 words$word))
@@ -8781,16 +8457,16 @@ val _ = Define `
 (*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ opA . 
-   if ((NotWordVal opA)) then state_monad$bindS
+   if ((NotWordVal opA)) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
    else
      wGPR rt
-       ((sign_extend1 (( 64 : int):ii)
+       ((mips_sign_extend (( 64 : int):ii)
            ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-               ((sign_extend1 (( 32 : int):ii) imm  :  32 words$word))
+               ((mips_sign_extend (( 32 : int):ii) imm  :  32 words$word))
               :  32 words$word))
           :  64 words$word)))))`;
 
@@ -8798,50 +8474,54 @@ val _ = Define `
 (*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm=  (state_monad$bindS
+ ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
    (rGPR rs  : ( 64 words$word) M) (\ opA . 
-   if ((NotWordVal opA)) then state_monad$bindS
+   if ((NotWordVal opA)) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
    else
      let (sum33 : 33 bits) =
        ((add_vec
-          ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  33 words$word))
-          ((sign_extend1 (( 33 : int):ii) imm  :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word)) ((mips_sign_extend (( 33 : int):ii) imm  :  33 words$word))
          :  33 words$word)) in
      if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii)))))
             ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then
        SignalException Ov
      else
        wGPR rt
-         ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word)))))`;
+         ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  64 words$word)))))`;
 
 
 (*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
 
 val _ = Define `
- ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd=  (state_monad$bindS
-   (rGPR rs  : ( 64 words$word) M) (\ (opA : 64 bits) .  state_monad$bindS
+ ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (opA : 64 bits) .  sail2_state_monad$bindS
    (rGPR rt  : ( 64 words$word) M) (\ (opB : 64 bits) . 
-   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
    else
      let (sum33 : 33 bits) =
        ((add_vec
-          ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  33 words$word))
-          ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
          :  33 words$word)) in
      if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii)))))
             ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then
        SignalException Ov
      else
        wGPR rd
-         ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word))))))`;
+         ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  64 words$word))))))`;
 
 
 val _ = Define `
- ((execute:ast ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) merge_var=
+ ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var=
     ((case merge_var of
      DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm
    | DADDU (rs,rt,rd) => execute_DADDU rs rt rd
@@ -8907,12 +8587,9 @@ val _ = Define `
    | JALR (rs,rd) => execute_JALR rs rd
    | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely
    | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely
-   | SYSCALL_THREAD_START (g__117) => state_monad$returnS ((execute_SYSCALL_THREAD_START g__117))
-   | ImplementationDefinedStopFetching (g__118) =>
-      state_monad$returnS ((execute_ImplementationDefinedStopFetching g__118))
-   | SYSCALL (g__119) => execute_SYSCALL g__119
-   | BREAK (g__120) => execute_BREAK g__120
-   | WAIT (g__121) => execute_WAIT g__121
+   | SYSCALL (g__17) => execute_SYSCALL g__17
+   | BREAK (g__18) => execute_BREAK g__18
+   | WAIT (g__19) => execute_WAIT g__19
    | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp
    | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp
    | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset
@@ -8926,17 +8603,16 @@ val _ = Define `
    | SDL (base,rt,offset) => execute_SDL base rt offset
    | SDR (base,rt,offset) => execute_SDR base rt offset
    | CACHE (base,op,imm) => execute_CACHE base op imm
-   | PREF (base,op,imm) => state_monad$returnS ((execute_PREF base op imm))
-   | SYNC (g__122) => execute_SYNC g__122
+   | SYNC (g__20) => execute_SYNC g__20
    | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double
-   | HCF (g__123) => state_monad$returnS ((execute_HCF g__123))
+   | HCF (g__21) => sail2_state_monad$returnS ((execute_HCF g__21))
    | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double
-   | TLBWI (g__124) => execute_TLBWI g__124
-   | TLBWR (g__125) => execute_TLBWR g__125
-   | TLBR (g__126) => execute_TLBR g__126
-   | TLBP (g__127) => execute_TLBP g__127
+   | TLBWI (g__22) => execute_TLBWI g__22
+   | TLBWR (g__23) => execute_TLBWR g__23
+   | TLBR (g__24) => execute_TLBR g__24
+   | TLBP (g__25) => execute_TLBP g__25
    | RDHWR (rt,rd) => execute_RDHWR rt rd
-   | ERET (g__128) => execute_ERET g__128
+   | ERET (g__26) => execute_ERET g__26
    | CGetPerm (rd,cb) => execute_CGetPerm rd cb
    | CGetType (rd,cb) => execute_CGetType rd cb
    | CGetBase (rd,cb) => execute_CGetBase rd cb
@@ -8974,7 +8650,7 @@ val _ = Define `
    | CCSeal (cd,cs,ct) => execute_CCSeal cd cs ct
    | CUnseal (cd,cs,ct) => execute_CUnseal cd cs ct
    | CCall (cs,cb,b__151) => execute_CCall cs cb b__151
-   | CReturn (g__129) => execute_CReturn g__129
+   | CReturn (g__27) => execute_CReturn g__27
    | CBX (cb,imm,notset) => execute_CBX cb imm notset
    | CBZ (cb,imm,notzero) => execute_CBZ cb imm notzero
    | CJALR (cd,cb,link) => execute_CJALR cd cb link
@@ -8984,8 +8660,8 @@ val _ = Define `
       execute_CStore rs cb rt rd offset width conditional
    | CSC (cs,cb,rt,rd,offset,conditional) => execute_CSC cs cb rt rd offset conditional
    | CLC (cd,cb,rt,offset,linked) => execute_CLC cd cb rt offset linked
-   | C2Dump (rt) => state_monad$returnS ((execute_C2Dump rt))
-   | RI (g__130) => execute_RI g__130
+   | C2Dump (rt) => sail2_state_monad$returnS ((execute_C2Dump rt))
+   | RI (g__28) => execute_RI g__28
    )))`;
 
 
@@ -8995,451 +8671,531 @@ val _ = Define `
  ((supported_instructions:ast ->(ast)option) instr=  (SOME instr))`;
 
 
+(*val cycle_limit_reached : unit -> bool*)
+
+val _ = Define `
+ ((cycle_limit_reached:unit -> bool) () =  F)`;
+
+
 (*val fetch_and_execute : unit -> M bool*)
 
 val _ = Define `
- ((fetch_and_execute:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS PC_ref w__0)
-   (state_monad$read_regS branchPending_ref  : ( 1 words$word) M)) (\ (w__1 : 1 bits) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS inBranchDelay_ref w__1)
-   (state_monad$write_regS branchPending_ref (vec_of_bits [B0]  :  1 words$word)))
-   (state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M)) (\ (w__2 :  1 words$word) .  state_monad$bindS
-   (if ((bits_to_bool w__2)) then (state_monad$read_regS delayedPC_ref  : ( 64 words$word) M)
-    else state_monad$bindS
-      (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
-      state_monad$returnS ((add_vec_int w__4 (( 4 : int):ii)  :  64 words$word)))) (\ (w__5 :  64 words$word) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS nextPC_ref w__5)
+ ((fetch_and_execute:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PC_ref w__0)
+   (sail2_state_monad$read_regS branchPending_ref  : ( 1 words$word) M)) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS inBranchDelay_ref w__1)
+   (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B0]  :  1 words$word)))
+   (sail2_state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M)) (\ (w__2 :  1 words$word) .  sail2_state_monad$bindS
+   (if ((bits_to_bool w__2)) then (sail2_state_monad$read_regS delayedPC_ref  : ( 64 words$word) M)
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
+      sail2_state_monad$returnS ((add_vec_int w__4 (( 4 : int):ii)  :  64 words$word)))) (\ (w__5 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPC_ref w__5)
    (cp2_next_pc () ))
-   (state_monad$read_regS instCount_ref)) (\ (w__6 : ii) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS instCount_ref ((w__6 + (( 1 : int):ii))))
-   (state_monad$read_regS UART_WRITTEN_ref  : ( 1 words$word) M)) (\ (w__7 :  1 words$word) .  state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (if ((bits_to_bool w__7)) then state_monad$bindS
-      (state_monad$read_regS UART_WDATA_ref  : ( 8 words$word) M) (\ (w__8 : 8 bits) . 
+   (sail2_state_monad$read_regS instCount_ref)) (\ (w__6 : ii) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS instCount_ref ((w__6 + (( 1 : int):ii))))
+   (sail2_state_monad$read_regS UART_WRITTEN_ref  : ( 1 words$word) M)) (\ (w__7 :  1 words$word) .  sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (if ((bits_to_bool w__7)) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS UART_WDATA_ref  : ( 8 words$word) M) (\ (w__8 : 8 bits) . 
       let (_ : unit) = (putchar ((lem$w2ui w__8))) in
-      state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B0]  :  1 words$word))
-    else state_monad$returnS () )
+      sail2_state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B0]  :  1 words$word))
+    else sail2_state_monad$returnS () )
    (skip () ))
    (skip () ))
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__9 : 64 bits) . 
-   let (_ : unit) = (print_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict "PC: " w__9) in
-   state_monad$try_catchS ( state_monad$bindS(state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__10 :  64 words$word) .  state_monad$bindS
-              (TranslatePC w__10  : ( 64 words$word) M) (\ pc_pa .  state_monad$bindS
+   (let loop_again = T in sail2_state_monad$bindS
+   (sail2_state_monad$try_catchS ( sail2_state_monad$bindS(sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__9 :  64 words$word) .  sail2_state_monad$bindS
+              (TranslatePC w__9  : ( 64 words$word) M) (\ pc_pa .  sail2_state_monad$bindS
               (MEMr_wrapper (( 32 : int):ii) pc_pa (( 4 : int):ii)  : ( 32 words$word) M) (\ instr . 
               let instr_ast = (decode instr) in
               (case instr_ast of
                 SOME ((HCF (_))) =>
-                 let (_ : unit) = (prerr_endline "simulation stopped due to halt instruction.") in
-                 state_monad$returnS F
-              | SOME (ast) => state_monad$seqS (execute ast) (state_monad$returnS T)
+                 let (_ : unit) = (print_endline "simulation stopped due to halt instruction.") in
+                 sail2_state_monad$returnS F
+              | SOME (ast) => sail2_state_monad$seqS (execute ast) (sail2_state_monad$returnS loop_again)
               | NONE =>
-                 let (_ : unit) = (prerr_endline "Decode failed") in
-                 state_monad$exitS () 
+                 let (_ : unit) = (print_endline "Decode failed") in
+                 sail2_state_monad$returnS F
               ))))) (\x .  
-  (case x of
-        ISAException (_) =>
-  let (_ : unit) = (prerr_endline "EXCEPTION") in state_monad$returnS T
-  )))))))))))`;
+  (case x of   ISAException (_) => sail2_state_monad$returnS loop_again ))) (\ (loop_again : bool) . 
+   sail2_state_monad$returnS (((loop_again /\ ((~ ((cycle_limit_reached () )))))))))))))))))`;
 
 
 (*val init_registers : mword ty64 -> M unit*)
 
 val _ = Define `
- ((init_registers:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) initialPC=  (state_monad$seqS (state_monad$seqS
-   (init_cp0_state () ) (init_cp2_state () )) (state_monad$write_regS nextPC_ref initialPC)))`;
+ ((init_registers:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) initialPC=  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (init_cp0_state () ) (init_cp2_state () )) (sail2_state_monad$write_regS nextPC_ref initialPC)))`;
 
 
 (*val dump_mips_state : unit -> M unit*)
 
 val _ = Define `
- ((dump_mips_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+ ((dump_mips_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
    let (_ : unit) = (print_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict "DEBUG MIPS PC " w__0) in
-   (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
-     (\ idx unit_var .  state_monad$bindS
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict "DEBUG MIPS PC " w__0) in
+   (sail2_state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () 
+     (\ idx unit_var .  sail2_state_monad$bindS
        (rGPR ((to_bits ((make_the_value (( 5 : int):ii)  :  5 itself)) idx  :  5 words$word))  : ( 64 words$word) M) (\ (w__1 :
           64 words$word) . 
-       state_monad$returnS (let _ =
-         (prerr_endline
+       sail2_state_monad$returnS (let _ =
+         (print_endline
            ((STRCAT "DEBUG MIPS REG "
                ((STRCAT ((string_of_int 
-  instance_Show_Show_Num_integer_dict idx)) ((STRCAT " " ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in
+  instance_Show_Show_Num_integer_dict idx)) ((STRCAT " " ((string_of_bits w__1))))))))) in
        () )))))))`;
 
 
 (*val main : unit -> M unit*)
 
 val _ = Define `
- ((main:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$seqS
+ ((main:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS
    (init_registers
      ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ((elf_entry () ))  :  64 words$word)))
-   (let startTime = (get_time_ns () ) in state_monad$seqS
-   (state$whileS ()  (\ unit_var .  fetch_and_execute () ) (\ unit_var .  state_monad$returnS () ))
+   (let startTime = (get_time_ns () ) in sail2_state_monad$seqS
+   (sail2_state$whileS ()  (\ unit_var .  fetch_and_execute () ) (\ unit_var .  sail2_state_monad$returnS () ))
    (let endTime = (get_time_ns () ) in
-   let elapsed = (endTime - startTime) in state_monad$bindS
-   (state_monad$read_regS instCount_ref) (\ (w__1 : ii) . 
+   let elapsed = (endTime - startTime) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS instCount_ref) (\ (w__1 : ii) . 
    let inst_1e9 = (w__1 * (( 1000000000 : int):ii)) in
-   let ips = (inst_1e9 / elapsed) in state_monad$bindS (state_monad$seqS (state_monad$seqS
+   let ips = (inst_1e9 / elapsed) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
    (dump_mips_state () )
    (dump_cp2_state () ))
-   (state_monad$read_regS instCount_ref)) (\ (w__2 : ii) . 
+   (sail2_state_monad$read_regS instCount_ref)) (\ (w__2 : ii) . 
    let (_ : unit) = (print_int "Executed instructions: " w__2) in
    let (_ : unit) = (print_int "Nanoseconds elapsed: " elapsed) in
-   state_monad$returnS ((print_int "Instructions per second: " ips))))))))`;
+   sail2_state_monad$returnS ((print_int "Instructions per second: " ips))))))))`;
 
 
 (*val initialize_registers : unit -> M unit*)
 
 val _ = Define `
- ((initialize_registers:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS PC_ref w__0)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__1 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS nextPC_ref w__1)
+ ((initialize_registers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PC_ref w__0)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPC_ref w__1)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__2 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBProbe_ref w__2)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBIndex_ref w__3)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBRandom_ref w__4)
+   (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntryLo0_ref w__5)
+   (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntryLo1_ref w__6)
+   (undefined_ContextReg () )) (\ (w__7 : ContextReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBContext_ref w__7)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M)) (\ (w__8 : 16 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBPageMask_ref w__8)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBWired_ref w__9)
+   (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntryHi_ref w__10)
+   (undefined_XContextReg () )) (\ (w__11 : XContextReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBXContext_ref w__11)
+   (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry00_ref w__12)
+   (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry01_ref w__13)
+   (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry02_ref w__14)
+   (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry03_ref w__15)
+   (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry04_ref w__16)
+   (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry05_ref w__17)
+   (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry06_ref w__18)
+   (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry07_ref w__19)
+   (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry08_ref w__20)
+   (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry09_ref w__21)
+   (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry10_ref w__22)
+   (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry11_ref w__23)
+   (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry12_ref w__24)
+   (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry13_ref w__25)
+   (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry14_ref w__26)
+   (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry15_ref w__27)
+   (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry16_ref w__28)
+   (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry17_ref w__29)
+   (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry18_ref w__30)
+   (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry19_ref w__31)
+   (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry20_ref w__32)
+   (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry21_ref w__33)
+   (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry22_ref w__34)
+   (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry23_ref w__35)
+   (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry24_ref w__36)
+   (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry25_ref w__37)
+   (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry26_ref w__38)
+   (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry27_ref w__39)
+   (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry28_ref w__40)
+   (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry29_ref w__41)
+   (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry30_ref w__42)
+   (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry31_ref w__43)
+   (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry32_ref w__44)
+   (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry33_ref w__45)
+   (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry34_ref w__46)
+   (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry35_ref w__47)
+   (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry36_ref w__48)
+   (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry37_ref w__49)
+   (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry38_ref w__50)
+   (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry39_ref w__51)
+   (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry40_ref w__52)
+   (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry41_ref w__53)
+   (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry42_ref w__54)
+   (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry43_ref w__55)
+   (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry44_ref w__56)
+   (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry45_ref w__57)
+   (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry46_ref w__58)
+   (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry47_ref w__59)
+   (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry48_ref w__60)
+   (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry49_ref w__61)
+   (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry50_ref w__62)
+   (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry51_ref w__63)
+   (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry52_ref w__64)
+   (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry53_ref w__65)
+   (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry54_ref w__66)
+   (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry55_ref w__67)
+   (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry56_ref w__68)
+   (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry57_ref w__69)
+   (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry58_ref w__70)
+   (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry59_ref w__71)
+   (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry60_ref w__72)
+   (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry61_ref w__73)
+   (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry62_ref w__74)
+   (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry63_ref w__75)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__76 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Compare_ref w__76)
+   (undefined_CauseReg () )) (\ (w__77 : CauseReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Cause_ref w__77)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__78 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0EPC_ref w__78)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__79 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0ErrorEPC_ref w__79)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__80 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0LLBit_ref w__80)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__81 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0LLAddr_ref w__81)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__82 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0BadVAddr_ref w__82)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__83 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Count_ref w__83)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__84 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0HWREna_ref w__84)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__85 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0UserLocal_ref w__85)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii)  : ( 3 words$word) M)) (\ (w__86 : 3 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0ConfigK0_ref w__86)
+   (undefined_StatusReg () )) (\ (w__87 : StatusReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Status_ref w__87)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__88 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS branchPending_ref w__88)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__89 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS inBranchDelay_ref w__89)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__90 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS delayedPC_ref w__90)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__91 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref w__91)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__92 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LO_ref w__92)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__93 :  64 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 32 : int):ii) w__93  : ( ( 64 words$word)list) M) (\ (w__94 : ( 64 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS GPR_ref w__94)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__2 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBProbe_ref w__2)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M)) (\ (w__95 : 8 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_WDATA_ref w__95)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBIndex_ref w__3)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__96 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_WRITTEN_ref w__96)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBRandom_ref w__4)
-   (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntryLo0_ref w__5)
-   (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntryLo1_ref w__6)
-   (undefined_ContextReg () )) (\ (w__7 : ContextReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBContext_ref w__7)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M)) (\ (w__97 : 8 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_RDATA_ref w__97)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M)) (\ (w__8 : 16 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBPageMask_ref w__8)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__98 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_RVALID_ref w__98)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBWired_ref w__9)
-   (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntryHi_ref w__10)
-   (undefined_XContextReg () )) (\ (w__11 : XContextReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBXContext_ref w__11)
-   (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry00_ref w__12)
-   (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry01_ref w__13)
-   (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry02_ref w__14)
-   (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry03_ref w__15)
-   (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry04_ref w__16)
-   (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry05_ref w__17)
-   (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry06_ref w__18)
-   (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry07_ref w__19)
-   (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry08_ref w__20)
-   (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry09_ref w__21)
-   (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry10_ref w__22)
-   (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry11_ref w__23)
-   (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry12_ref w__24)
-   (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry13_ref w__25)
-   (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry14_ref w__26)
-   (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry15_ref w__27)
-   (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry16_ref w__28)
-   (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry17_ref w__29)
-   (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry18_ref w__30)
-   (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry19_ref w__31)
-   (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry20_ref w__32)
-   (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry21_ref w__33)
-   (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry22_ref w__34)
-   (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry23_ref w__35)
-   (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry24_ref w__36)
-   (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry25_ref w__37)
-   (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry26_ref w__38)
-   (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry27_ref w__39)
-   (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry28_ref w__40)
-   (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry29_ref w__41)
-   (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry30_ref w__42)
-   (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry31_ref w__43)
-   (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry32_ref w__44)
-   (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry33_ref w__45)
-   (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry34_ref w__46)
-   (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry35_ref w__47)
-   (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry36_ref w__48)
-   (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry37_ref w__49)
-   (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry38_ref w__50)
-   (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry39_ref w__51)
-   (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry40_ref w__52)
-   (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry41_ref w__53)
-   (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry42_ref w__54)
-   (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry43_ref w__55)
-   (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry44_ref w__56)
-   (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry45_ref w__57)
-   (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry46_ref w__58)
-   (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry47_ref w__59)
-   (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry48_ref w__60)
-   (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry49_ref w__61)
-   (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry50_ref w__62)
-   (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry51_ref w__63)
-   (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry52_ref w__64)
-   (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry53_ref w__65)
-   (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry54_ref w__66)
-   (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry55_ref w__67)
-   (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry56_ref w__68)
-   (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry57_ref w__69)
-   (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry58_ref w__70)
-   (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry59_ref w__71)
-   (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry60_ref w__72)
-   (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry61_ref w__73)
-   (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry62_ref w__74)
-   (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS TLBEntry63_ref w__75)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__99 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PCC_ref w__99)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__76 : 32 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0Compare_ref w__76)
-   (undefined_CauseReg () )) (\ (w__77 : CauseReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0Cause_ref w__77)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__100 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPCC_ref w__100)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__78 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0EPC_ref w__78)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__101 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS delayedPCC_ref w__101)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__79 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0ErrorEPC_ref w__79)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__102 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS inCCallDelay_ref w__102)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__80 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0LLBit_ref w__80)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__103 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS DDC_ref w__103)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__81 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0LLAddr_ref w__81)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__104 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C01_ref w__104)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__82 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0BadVAddr_ref w__82)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__105 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C02_ref w__105)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__83 : 32 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0Count_ref w__83)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__106 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C03_ref w__106)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__84 : 32 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0HWREna_ref w__84)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__107 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C04_ref w__107)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__85 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0UserLocal_ref w__85)
-   (undefined_StatusReg () )) (\ (w__86 : StatusReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CP0Status_ref w__86)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__108 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C05_ref w__108)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__87 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS branchPending_ref w__87)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__109 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C06_ref w__109)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__88 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS inBranchDelay_ref w__88)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__110 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C07_ref w__110)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__89 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS delayedPC_ref w__89)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__111 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C08_ref w__111)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__90 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS HI_ref w__90)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__112 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C09_ref w__112)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__91 : 64 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS LO_ref w__91)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__113 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C10_ref w__113)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__92 :  64 words$word) .  state_monad$bindS
-   (undefined_vector (( 32 : int):ii) w__92  : ( ( 64 words$word)list) M) (\ (w__93 : ( 64 bits) list) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS GPR_ref w__93)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__114 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C11_ref w__114)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M)) (\ (w__94 : 8 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS UART_WDATA_ref w__94)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__115 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C12_ref w__115)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__95 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS UART_WRITTEN_ref w__95)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__116 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C13_ref w__116)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M)) (\ (w__96 : 8 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS UART_RDATA_ref w__96)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__117 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C14_ref w__117)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__97 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS UART_RVALID_ref w__97)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__118 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C15_ref w__118)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__98 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS PCC_ref w__98)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__119 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C16_ref w__119)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__99 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS nextPCC_ref w__99)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__120 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C17_ref w__120)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__100 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS delayedPCC_ref w__100)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__121 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C18_ref w__121)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__101 : 1 bits) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS inCCallDelay_ref w__101)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__122 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C19_ref w__122)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__102 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C00_ref w__102)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__123 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C20_ref w__123)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__103 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C01_ref w__103)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__124 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C21_ref w__124)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__104 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C02_ref w__104)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__125 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C22_ref w__125)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__105 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C03_ref w__105)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__126 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C23_ref w__126)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__106 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C04_ref w__106)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__127 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C24_ref w__127)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__107 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C05_ref w__107)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__128 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C25_ref w__128)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__108 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C06_ref w__108)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__129 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C26_ref w__129)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__109 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C07_ref w__109)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__130 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C27_ref w__130)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__110 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C08_ref w__110)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__131 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C28_ref w__131)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__111 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C09_ref w__111)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__132 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C29_ref w__132)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__112 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C10_ref w__112)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__133 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C30_ref w__133)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__113 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C11_ref w__113)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__134 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS C31_ref w__134)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__114 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C12_ref w__114)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__135 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CTLSU_ref w__135)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__115 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C13_ref w__115)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__136 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CTLSP_ref w__136)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__116 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C14_ref w__116)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__137 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS KR1C_ref w__137)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__117 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C15_ref w__117)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__138 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS KR2C_ref w__138)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__118 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C16_ref w__118)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__139 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS KCC_ref w__139)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__119 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C17_ref w__119)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__140 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS KDC_ref w__140)
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__120 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C18_ref w__120)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__121 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C19_ref w__121)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__122 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C20_ref w__122)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__123 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C21_ref w__123)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__124 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C22_ref w__124)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__125 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C23_ref w__125)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__126 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C24_ref w__126)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__127 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C25_ref w__127)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__128 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C26_ref w__128)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__129 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C27_ref w__129)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__130 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C28_ref w__130)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__131 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C29_ref w__131)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__132 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C30_ref w__132)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__133 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS C31_ref w__133)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__134 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CTLSU_ref w__134)
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__135 : CapReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CTLSP_ref w__135)
-   (undefined_CapCauseReg () )) (\ (w__136 : CapCauseReg) .  state_monad$bindS (state_monad$seqS
-   (state_monad$write_regS CapCause_ref w__136)
-   (undefined_int () )) (\ (w__137 : ii) .  state_monad$write_regS instCount_ref w__137))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii)  : ( 257 words$word) M)) (\ (w__141 : CapReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS EPCC_ref w__141)
+   (undefined_CapCauseReg () )) (\ (w__142 : CapCauseReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CapCause_ref w__142)
+   (undefined_int () )) (\ (w__143 : ii) .  sail2_state_monad$write_regS instCount_ref w__143))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
 
 
 val _ = Define `
 ((initial_regstate:regstate)=
    (<| instCount := ((( 0 : int):ii)); 
      CapCause :=
-       (Mk_CapCauseReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)); 
+       (<| CapCauseReg_CapCauseReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)) |>); 
+     EPCC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  257 words$word)); 
+     KDC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  257 words$word)); 
+     KCC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  257 words$word)); 
+     KR2C :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  257 words$word)); 
+     KR1C :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  257 words$word)); 
      CTLSP :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -9836,7 +9592,7 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  257 words$word)); 
-     C00 :=
+     DDC :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -10036,9 +9792,11 @@ val _ = Define `
      inBranchDelay := ((vec_of_bits [B0]  :  1 words$word)); 
      branchPending := ((vec_of_bits [B0]  :  1 words$word)); 
      CP0Status :=
-       (Mk_StatusReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                       :  32 words$word)); 
+       (<| StatusReg_StatusReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0]
+               :  32 words$word)) |>); 
+     CP0ConfigK0 := ((vec_of_bits [B0;B0;B0]  :  3 words$word)); 
      CP0UserLocal :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -10074,557 +9832,750 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
      CP0Cause :=
-       (Mk_CauseReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                      :  32 words$word)); 
+       (<| CauseReg_CauseReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0]
+               :  32 words$word)) |>); 
      CP0Compare :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0]
          :  32 words$word)); 
      TLBEntry63 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry62 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry61 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry60 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry59 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry58 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry57 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry56 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry55 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry54 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry53 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry52 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry51 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry50 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry49 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry48 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry47 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry46 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry45 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry44 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry43 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry42 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry41 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry40 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry39 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry38 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry37 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry36 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry35 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry34 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry33 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry32 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry31 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry30 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry29 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry28 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry27 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry26 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry25 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry24 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry23 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry22 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry21 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry20 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry19 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry18 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry17 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry16 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry15 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry14 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry13 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry12 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry11 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry10 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry09 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry08 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry07 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry06 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry05 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry04 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry03 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry02 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry01 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntry00 :=
-       (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                  B0;B0;B0;B0;B0;B0;B0]
-                      :  117 words$word)); 
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBXContext :=
-       (Mk_XContextReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0]
-                         :  64 words$word)); 
+       (<| XContextReg_XContextReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntryHi :=
-       (Mk_TLBEntryHiReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0]
-                           :  64 words$word)); 
+       (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBWired := ((vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)); 
      TLBPageMask := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)); 
      TLBContext :=
-       (Mk_ContextReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                    B0]
-                        :  64 words$word)); 
+       (<| ContextReg_ContextReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntryLo1 :=
-       (Mk_TLBEntryLoReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0]
-                           :  64 words$word)); 
+       (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBEntryLo0 :=
-       (Mk_TLBEntryLoReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                       B0;B0;B0;B0]
-                           :  64 words$word)); 
+       (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      TLBRandom := ((vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)); 
      TLBIndex := ((vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)); 
      TLBProbe := ((vec_of_bits [B0]  :  1 words$word)); 
diff --git a/snapshots/hol4/sail/cheri/cheri_typesScript.sml b/snapshots/hol4/sail/cheri/cheri_typesScript.sml
index 2bc764e0..fce47ce3 100644
--- a/snapshots/hol4/sail/cheri/cheri_typesScript.sml
+++ b/snapshots/hol4/sail/cheri/cheri_typesScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from cheri_types.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory;
 
 val _ = numLib.prefer_num();
 
@@ -10,11 +10,12 @@ val _ = new_theory "cheri_types"
 
 (*Generated by Sail from cheri.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 val _ = type_abbrev((*  'n *) "bits" , ``:  'n words$word``);
 
 
@@ -31,52 +32,45 @@ val _ = Hol_datatype `
 
 
 val _ = Hol_datatype `
- CauseReg  =   Mk_CauseReg of ( 32 words$word)`;
-
+ CauseReg  = <| CauseReg_CauseReg_chunk_0 :  32 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- CapCauseReg  =   Mk_CapCauseReg of ( 16 words$word)`;
-
+ CapCauseReg  = <| CapCauseReg_CapCauseReg_chunk_0 :  16 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- TLBEntryLoReg  =   Mk_TLBEntryLoReg of ( 64 words$word)`;
-
+ TLBEntryLoReg  = <| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- TLBEntryHiReg  =   Mk_TLBEntryHiReg of ( 64 words$word)`;
-
+ TLBEntryHiReg  = <| TLBEntryHiReg_TLBEntryHiReg_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- ContextReg  =   Mk_ContextReg of ( 64 words$word)`;
-
+ ContextReg  = <| ContextReg_ContextReg_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- XContextReg  =   Mk_XContextReg of ( 64 words$word)`;
-
+ XContextReg  = <| XContextReg_XContextReg_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = type_abbrev( "TLBIndexT"  , ``: 6 bits``);
 
 val _ = Hol_datatype `
- TLBEntry  =   Mk_TLBEntry of ( 117 words$word)`;
-
+ TLBEntry  =
+  <| TLBEntry_TLBEntry_chunk_1 :  53 words$word; TLBEntry_TLBEntry_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- StatusReg  =   Mk_StatusReg of ( 32 words$word)`;
-
+ StatusReg  = <| StatusReg_StatusReg_chunk_0 :  32 words$word  |>`;
 
 
 
@@ -171,6 +165,12 @@ val _ = Hol_datatype `
 
 
 
+val _ = Hol_datatype `
+ WordTypeUnaligned = WL | WR | DL | DR`;
+
+
+
+
 val _ = type_abbrev( "CapLen"  , ``: int``);
 
 val _ = type_abbrev( "uint64"  , ``: int``);
@@ -253,8 +253,6 @@ val _ = Hol_datatype `
   | JALR of ((regno # regno))
   | BEQ of ((regno # regno # imm16 # bool # bool))
   | BCMPZ of ((regno # imm16 # Comparison # bool # bool))
-  | SYSCALL_THREAD_START of (unit)
-  | ImplementationDefinedStopFetching of (unit)
   | SYSCALL of (unit)
   | BREAK of (unit)
   | WAIT of (unit)
@@ -271,7 +269,6 @@ val _ = Hol_datatype `
   | SDL of ((regno # regno # 16 bits))
   | SDR of ((regno # regno # 16 bits))
   | CACHE of ((regno # regno # 16 bits))
-  | PREF of ((regno # regno # 16 bits))
   | SYNC of (unit)
   | MFC0 of ((regno # regno # 3 bits # bool))
   | HCF of (unit)
@@ -326,7 +323,7 @@ val _ = Hol_datatype `
   | CLoad of ((regno # regno # regno # 8 bits # bool # WordType # bool))
   | CStore of ((regno # regno # regno # regno # 8 bits # WordType # bool))
   | CSC of ((regno # regno # regno # regno # 11 bits # bool))
-  | CLC of ((regno # regno # regno # 11 bits # bool))
+  | CLC of ((regno # regno # regno # 16 bits # bool))
   | C2Dump of (regno)
   | RI of (unit)`;
 
@@ -380,6 +377,7 @@ val _ = Hol_datatype `
   | Regval_vector_1_dec_bit of ( 1 words$word)
   | Regval_vector_257_dec_bit of ( 257 words$word)
   | Regval_vector_32_dec_bit of ( 32 words$word)
+  | Regval_vector_3_dec_bit of ( 3 words$word)
   | Regval_vector_64_dec_bit of ( 64 words$word)
   | Regval_vector_6_dec_bit of ( 6 words$word)
   | Regval_vector_8_dec_bit of ( 8 words$word)`;
@@ -391,6 +389,11 @@ val _ = Hol_datatype `
  regstate  =
   <| instCount : ii;
      CapCause : CapCauseReg;
+     EPCC :  257 words$word;
+     KDC :  257 words$word;
+     KCC :  257 words$word;
+     KR2C :  257 words$word;
+     KR1C :  257 words$word;
      CTLSP :  257 words$word;
      CTLSU :  257 words$word;
      C31 :  257 words$word;
@@ -424,7 +427,7 @@ val _ = Hol_datatype `
      C03 :  257 words$word;
      C02 :  257 words$word;
      C01 :  257 words$word;
-     C00 :  257 words$word;
+     DDC :  257 words$word;
      inCCallDelay :  1 words$word;
      delayedPCC :  257 words$word;
      nextPCC :  257 words$word;
@@ -440,6 +443,7 @@ val _ = Hol_datatype `
      inBranchDelay :  1 words$word;
      branchPending :  1 words$word;
      CP0Status : StatusReg;
+     CP0ConfigK0 :  3 words$word;
      CP0UserLocal :  64 words$word;
      CP0HWREna :  32 words$word;
      CP0Count :  32 words$word;
@@ -535,7 +539,7 @@ val _ = Hol_datatype `
 
 val _ = Define `
  ((CapCauseReg_of_regval:register_value ->(CapCauseReg)option) merge_var=
-    ((case merge_var of   Regval_CapCauseReg (v) => SOME v | g__114 => NONE )))`;
+    ((case merge_var of   Regval_CapCauseReg (v) => SOME v | g__16 => NONE )))`;
 
 
 (*val regval_of_CapCauseReg : CapCauseReg -> register_value*)
@@ -548,7 +552,7 @@ val _ = Define `
 
 val _ = Define `
  ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var=
-    ((case merge_var of   Regval_CauseReg (v) => SOME v | g__113 => NONE )))`;
+    ((case merge_var of   Regval_CauseReg (v) => SOME v | g__15 => NONE )))`;
 
 
 (*val regval_of_CauseReg : CauseReg -> register_value*)
@@ -561,7 +565,7 @@ val _ = Define `
 
 val _ = Define `
  ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var=
-    ((case merge_var of   Regval_ContextReg (v) => SOME v | g__112 => NONE )))`;
+    ((case merge_var of   Regval_ContextReg (v) => SOME v | g__14 => NONE )))`;
 
 
 (*val regval_of_ContextReg : ContextReg -> register_value*)
@@ -574,7 +578,7 @@ val _ = Define `
 
 val _ = Define `
  ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var=
-    ((case merge_var of   Regval_StatusReg (v) => SOME v | g__111 => NONE )))`;
+    ((case merge_var of   Regval_StatusReg (v) => SOME v | g__13 => NONE )))`;
 
 
 (*val regval_of_StatusReg : StatusReg -> register_value*)
@@ -587,7 +591,7 @@ val _ = Define `
 
 val _ = Define `
  ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var=
-    ((case merge_var of   Regval_TLBEntry (v) => SOME v | g__110 => NONE )))`;
+    ((case merge_var of   Regval_TLBEntry (v) => SOME v | g__12 => NONE )))`;
 
 
 (*val regval_of_TLBEntry : TLBEntry -> register_value*)
@@ -600,7 +604,7 @@ val _ = Define `
 
 val _ = Define `
  ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var=
-    ((case merge_var of   Regval_TLBEntryHiReg (v) => SOME v | g__109 => NONE )))`;
+    ((case merge_var of   Regval_TLBEntryHiReg (v) => SOME v | g__11 => NONE )))`;
 
 
 (*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*)
@@ -613,7 +617,7 @@ val _ = Define `
 
 val _ = Define `
  ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var=
-    ((case merge_var of   Regval_TLBEntryLoReg (v) => SOME v | g__108 => NONE )))`;
+    ((case merge_var of   Regval_TLBEntryLoReg (v) => SOME v | g__10 => NONE )))`;
 
 
 (*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*)
@@ -626,7 +630,7 @@ val _ = Define `
 
 val _ = Define `
  ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var=
-    ((case merge_var of   Regval_XContextReg (v) => SOME v | g__107 => NONE )))`;
+    ((case merge_var of   Regval_XContextReg (v) => SOME v | g__9 => NONE )))`;
 
 
 (*val regval_of_XContextReg : XContextReg -> register_value*)
@@ -638,8 +642,7 @@ val _ = Define `
 (*val int_of_regval : register_value -> maybe ii*)
 
 val _ = Define `
- ((int_of_regval:register_value ->(int)option) merge_var=
-    ((case merge_var of   Regval_int (v) => SOME v | g__106 => NONE )))`;
+ ((int_of_regval:register_value ->(int)option) merge_var=  ((case merge_var of   Regval_int (v) => SOME v | g__8 => NONE )))`;
 
 
 (*val regval_of_int : ii -> register_value*)
@@ -652,7 +655,7 @@ val _ = Define `
 
 val _ = Define `
  ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_16_dec_bit (v) => SOME v | g__105 => NONE )))`;
+    ((case merge_var of   Regval_vector_16_dec_bit (v) => SOME v | g__7 => NONE )))`;
 
 
 (*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*)
@@ -665,7 +668,7 @@ val _ = Define `
 
 val _ = Define `
  ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_1_dec_bit (v) => SOME v | g__104 => NONE )))`;
+    ((case merge_var of   Regval_vector_1_dec_bit (v) => SOME v | g__6 => NONE )))`;
 
 
 (*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*)
@@ -678,7 +681,7 @@ val _ = Define `
 
 val _ = Define `
  ((vector_257_dec_bit_of_regval:register_value ->((257)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_257_dec_bit (v) => SOME v | g__103 => NONE )))`;
+    ((case merge_var of   Regval_vector_257_dec_bit (v) => SOME v | g__5 => NONE )))`;
 
 
 (*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*)
@@ -691,7 +694,7 @@ val _ = Define `
 
 val _ = Define `
  ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_32_dec_bit (v) => SOME v | g__102 => NONE )))`;
+    ((case merge_var of   Regval_vector_32_dec_bit (v) => SOME v | g__4 => NONE )))`;
 
 
 (*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
@@ -700,11 +703,24 @@ val _ = Define `
  ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v=  (Regval_vector_32_dec_bit v))`;
 
 
+(*val vector_3_dec_bit_of_regval : register_value -> maybe (mword ty3)*)
+
+val _ = Define `
+ ((vector_3_dec_bit_of_regval:register_value ->((3)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_3_dec_bit (v) => SOME v | g__3 => NONE )))`;
+
+
+(*val regval_of_vector_3_dec_bit : mword ty3 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_3_dec_bit:(3)words$word -> register_value) v=  (Regval_vector_3_dec_bit v))`;
+
+
 (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
 
 val _ = Define `
  ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__101 => NONE )))`;
+    ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__2 => NONE )))`;
 
 
 (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
@@ -717,7 +733,7 @@ val _ = Define `
 
 val _ = Define `
  ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_6_dec_bit (v) => SOME v | g__100 => NONE )))`;
+    ((case merge_var of   Regval_vector_6_dec_bit (v) => SOME v | g__1 => NONE )))`;
 
 
 (*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*)
@@ -730,7 +746,7 @@ val _ = Define `
 
 val _ = Define `
  ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_8_dec_bit (v) => SOME v | g__99 => NONE )))`;
+    ((case merge_var of   Regval_vector_8_dec_bit (v) => SOME v | g__0 => NONE )))`;
 
 
 (*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*)
@@ -743,44 +759,44 @@ val _ = Define `
 
 (*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
 val _ = Define `
- ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
   (\x .  (case x of
-               Regval_vector (_, _, v) => just_list (MAP of_regval v)
+               Regval_vector (_, _, v) => just_list (MAP of_regval1 v)
            | _ => NONE
          )))`;
 
 
 (*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
 val _ = Define `
- ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of xs)))`;
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`;
 
 
 (*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
 val _ = Define `
- ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
   (\x .  (case x of
-               Regval_list v => just_list (MAP of_regval v)
+               Regval_list v => just_list (MAP of_regval1 v)
            | _ => NONE
          )))`;
 
 
 (*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
 val _ = Define `
- ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs=  (Regval_list (MAP regval_of xs)))`;
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs=  (Regval_list (MAP regval_of1 xs)))`;
 
 
 (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
 val _ = Define `
- ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= 
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= 
   (\x .  (case x of
-               Regval_option v => SOME (OPTION_BIND v of_regval)
+               Regval_option v => SOME (OPTION_BIND v of_regval1)
            | _ => NONE
          )))`;
 
 
 (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
 val _ = Define `
- ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v=  (Regval_option (OPTION_MAP regval_of v)))`;
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v=  (Regval_option (OPTION_MAP regval_of1 v)))`;
 
 
 
@@ -802,6 +818,33 @@ val _ = Define `
   regval_of := (\ v .  regval_of_CapCauseReg v) |>))`;
 
 
+val _ = Define `
+ ((KDC_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "KDC";
+  read_from := (\ s .  s.KDC);
+  write_to := (\ v s .  (( s with<| KDC := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((KR2C_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "KR2C";
+  read_from := (\ s .  s.KR2C);
+  write_to := (\ v s .  (( s with<| KR2C := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((KR1C_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "KR1C";
+  read_from := (\ s .  s.KR1C);
+  write_to := (\ v s .  (( s with<| KR1C := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
 val _ = Define `
  ((CTLSP_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
   name := "CTLSP";
@@ -820,6 +863,15 @@ val _ = Define `
   regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
 
 
+val _ = Define `
+ ((C31_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "C31";
+  read_from := (\ s .  s.C31);
+  write_to := (\ v s .  (( s with<| C31 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
 val _ = Define `
  ((C30_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
   name := "C30";
@@ -829,6 +881,15 @@ val _ = Define `
   regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
 
 
+val _ = Define `
+ ((C29_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "C29";
+  read_from := (\ s .  s.C29);
+  write_to := (\ v s .  (( s with<| C29 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
 val _ = Define `
  ((C28_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
   name := "C28";
@@ -1082,10 +1143,10 @@ val _ = Define `
 
 
 val _ = Define `
- ((C00_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
-  name := "C00";
-  read_from := (\ s .  s.C00);
-  write_to := (\ v s .  (( s with<| C00 := v |>)));
+ ((DDC_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "DDC";
+  read_from := (\ s .  s.DDC);
+  write_to := (\ v s .  (( s with<| DDC := v |>)));
   of_regval := (\ v .  vector_257_dec_bit_of_regval v);
   regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
 
@@ -1127,19 +1188,19 @@ val _ = Define `
 
 
 val _ = Define `
- ((C31_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
-  name := "C31";
-  read_from := (\ s .  s.C31);
-  write_to := (\ v s .  (( s with<| C31 := v |>)));
+ ((KCC_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "KCC";
+  read_from := (\ s .  s.KCC);
+  write_to := (\ v s .  (( s with<| KCC := v |>)));
   of_regval := (\ v .  vector_257_dec_bit_of_regval v);
   regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
 
 
 val _ = Define `
- ((C29_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
-  name := "C29";
-  read_from := (\ s .  s.C29);
-  write_to := (\ v s .  (( s with<| C29 := v |>)));
+ ((EPCC_ref:((regstate),(register_value),((257)words$word))register_ref)=  (<|
+  name := "EPCC";
+  read_from := (\ s .  s.EPCC);
+  write_to := (\ v s .  (( s with<| EPCC := v |>)));
   of_regval := (\ v .  vector_257_dec_bit_of_regval v);
   regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
 
@@ -1243,6 +1304,15 @@ val _ = Define `
   regval_of := (\ v .  regval_of_StatusReg v) |>))`;
 
 
+val _ = Define `
+ ((CP0ConfigK0_ref:((regstate),(register_value),((3)words$word))register_ref)=  (<|
+  name := "CP0ConfigK0";
+  read_from := (\ s .  s.CP0ConfigK0);
+  write_to := (\ v s .  (( s with<| CP0ConfigK0 := v |>)));
+  of_regval := (\ v .  vector_3_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_3_dec_bit v) |>))`;
+
+
 val _ = Define `
  ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
   name := "CP0UserLocal";
@@ -2022,9 +2092,14 @@ val _ = Define `
  ((get_regval:string -> regstate ->(register_value)option) reg_name s=
    (if reg_name = "instCount" then SOME (instCount_ref.regval_of (instCount_ref.read_from s)) else
   if reg_name = "CapCause" then SOME (CapCause_ref.regval_of (CapCause_ref.read_from s)) else
+  if reg_name = "KDC" then SOME (KDC_ref.regval_of (KDC_ref.read_from s)) else
+  if reg_name = "KR2C" then SOME (KR2C_ref.regval_of (KR2C_ref.read_from s)) else
+  if reg_name = "KR1C" then SOME (KR1C_ref.regval_of (KR1C_ref.read_from s)) else
   if reg_name = "CTLSP" then SOME (CTLSP_ref.regval_of (CTLSP_ref.read_from s)) else
   if reg_name = "CTLSU" then SOME (CTLSU_ref.regval_of (CTLSU_ref.read_from s)) else
+  if reg_name = "C31" then SOME (C31_ref.regval_of (C31_ref.read_from s)) else
   if reg_name = "C30" then SOME (C30_ref.regval_of (C30_ref.read_from s)) else
+  if reg_name = "C29" then SOME (C29_ref.regval_of (C29_ref.read_from s)) else
   if reg_name = "C28" then SOME (C28_ref.regval_of (C28_ref.read_from s)) else
   if reg_name = "C27" then SOME (C27_ref.regval_of (C27_ref.read_from s)) else
   if reg_name = "C26" then SOME (C26_ref.regval_of (C26_ref.read_from s)) else
@@ -2053,13 +2128,13 @@ val _ = Define `
   if reg_name = "C03" then SOME (C03_ref.regval_of (C03_ref.read_from s)) else
   if reg_name = "C02" then SOME (C02_ref.regval_of (C02_ref.read_from s)) else
   if reg_name = "C01" then SOME (C01_ref.regval_of (C01_ref.read_from s)) else
-  if reg_name = "C00" then SOME (C00_ref.regval_of (C00_ref.read_from s)) else
+  if reg_name = "DDC" then SOME (DDC_ref.regval_of (DDC_ref.read_from s)) else
   if reg_name = "inCCallDelay" then SOME (inCCallDelay_ref.regval_of (inCCallDelay_ref.read_from s)) else
   if reg_name = "nextPCC" then SOME (nextPCC_ref.regval_of (nextPCC_ref.read_from s)) else
   if reg_name = "delayedPCC" then SOME (delayedPCC_ref.regval_of (delayedPCC_ref.read_from s)) else
   if reg_name = "PCC" then SOME (PCC_ref.regval_of (PCC_ref.read_from s)) else
-  if reg_name = "C31" then SOME (C31_ref.regval_of (C31_ref.read_from s)) else
-  if reg_name = "C29" then SOME (C29_ref.regval_of (C29_ref.read_from s)) else
+  if reg_name = "KCC" then SOME (KCC_ref.regval_of (KCC_ref.read_from s)) else
+  if reg_name = "EPCC" then SOME (EPCC_ref.regval_of (EPCC_ref.read_from s)) else
   if reg_name = "UART_RVALID" then SOME (UART_RVALID_ref.regval_of (UART_RVALID_ref.read_from s)) else
   if reg_name = "UART_RDATA" then SOME (UART_RDATA_ref.regval_of (UART_RDATA_ref.read_from s)) else
   if reg_name = "UART_WRITTEN" then SOME (UART_WRITTEN_ref.regval_of (UART_WRITTEN_ref.read_from s)) else
@@ -2071,6 +2146,7 @@ val _ = Define `
   if reg_name = "inBranchDelay" then SOME (inBranchDelay_ref.regval_of (inBranchDelay_ref.read_from s)) else
   if reg_name = "branchPending" then SOME (branchPending_ref.regval_of (branchPending_ref.read_from s)) else
   if reg_name = "CP0Status" then SOME (CP0Status_ref.regval_of (CP0Status_ref.read_from s)) else
+  if reg_name = "CP0ConfigK0" then SOME (CP0ConfigK0_ref.regval_of (CP0ConfigK0_ref.read_from s)) else
   if reg_name = "CP0UserLocal" then SOME (CP0UserLocal_ref.regval_of (CP0UserLocal_ref.read_from s)) else
   if reg_name = "CP0HWREna" then SOME (CP0HWREna_ref.regval_of (CP0HWREna_ref.read_from s)) else
   if reg_name = "CP0Count" then SOME (CP0Count_ref.regval_of (CP0Count_ref.read_from s)) else
@@ -2165,9 +2241,14 @@ val _ = Define `
  ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=
    (if reg_name = "instCount" then OPTION_MAP (\ v .  instCount_ref.write_to v s) (instCount_ref.of_regval v) else
   if reg_name = "CapCause" then OPTION_MAP (\ v .  CapCause_ref.write_to v s) (CapCause_ref.of_regval v) else
+  if reg_name = "KDC" then OPTION_MAP (\ v .  KDC_ref.write_to v s) (KDC_ref.of_regval v) else
+  if reg_name = "KR2C" then OPTION_MAP (\ v .  KR2C_ref.write_to v s) (KR2C_ref.of_regval v) else
+  if reg_name = "KR1C" then OPTION_MAP (\ v .  KR1C_ref.write_to v s) (KR1C_ref.of_regval v) else
   if reg_name = "CTLSP" then OPTION_MAP (\ v .  CTLSP_ref.write_to v s) (CTLSP_ref.of_regval v) else
   if reg_name = "CTLSU" then OPTION_MAP (\ v .  CTLSU_ref.write_to v s) (CTLSU_ref.of_regval v) else
+  if reg_name = "C31" then OPTION_MAP (\ v .  C31_ref.write_to v s) (C31_ref.of_regval v) else
   if reg_name = "C30" then OPTION_MAP (\ v .  C30_ref.write_to v s) (C30_ref.of_regval v) else
+  if reg_name = "C29" then OPTION_MAP (\ v .  C29_ref.write_to v s) (C29_ref.of_regval v) else
   if reg_name = "C28" then OPTION_MAP (\ v .  C28_ref.write_to v s) (C28_ref.of_regval v) else
   if reg_name = "C27" then OPTION_MAP (\ v .  C27_ref.write_to v s) (C27_ref.of_regval v) else
   if reg_name = "C26" then OPTION_MAP (\ v .  C26_ref.write_to v s) (C26_ref.of_regval v) else
@@ -2196,13 +2277,13 @@ val _ = Define `
   if reg_name = "C03" then OPTION_MAP (\ v .  C03_ref.write_to v s) (C03_ref.of_regval v) else
   if reg_name = "C02" then OPTION_MAP (\ v .  C02_ref.write_to v s) (C02_ref.of_regval v) else
   if reg_name = "C01" then OPTION_MAP (\ v .  C01_ref.write_to v s) (C01_ref.of_regval v) else
-  if reg_name = "C00" then OPTION_MAP (\ v .  C00_ref.write_to v s) (C00_ref.of_regval v) else
+  if reg_name = "DDC" then OPTION_MAP (\ v .  DDC_ref.write_to v s) (DDC_ref.of_regval v) else
   if reg_name = "inCCallDelay" then OPTION_MAP (\ v .  inCCallDelay_ref.write_to v s) (inCCallDelay_ref.of_regval v) else
   if reg_name = "nextPCC" then OPTION_MAP (\ v .  nextPCC_ref.write_to v s) (nextPCC_ref.of_regval v) else
   if reg_name = "delayedPCC" then OPTION_MAP (\ v .  delayedPCC_ref.write_to v s) (delayedPCC_ref.of_regval v) else
   if reg_name = "PCC" then OPTION_MAP (\ v .  PCC_ref.write_to v s) (PCC_ref.of_regval v) else
-  if reg_name = "C31" then OPTION_MAP (\ v .  C31_ref.write_to v s) (C31_ref.of_regval v) else
-  if reg_name = "C29" then OPTION_MAP (\ v .  C29_ref.write_to v s) (C29_ref.of_regval v) else
+  if reg_name = "KCC" then OPTION_MAP (\ v .  KCC_ref.write_to v s) (KCC_ref.of_regval v) else
+  if reg_name = "EPCC" then OPTION_MAP (\ v .  EPCC_ref.write_to v s) (EPCC_ref.of_regval v) else
   if reg_name = "UART_RVALID" then OPTION_MAP (\ v .  UART_RVALID_ref.write_to v s) (UART_RVALID_ref.of_regval v) else
   if reg_name = "UART_RDATA" then OPTION_MAP (\ v .  UART_RDATA_ref.write_to v s) (UART_RDATA_ref.of_regval v) else
   if reg_name = "UART_WRITTEN" then OPTION_MAP (\ v .  UART_WRITTEN_ref.write_to v s) (UART_WRITTEN_ref.of_regval v) else
@@ -2214,6 +2295,7 @@ val _ = Define `
   if reg_name = "inBranchDelay" then OPTION_MAP (\ v .  inBranchDelay_ref.write_to v s) (inBranchDelay_ref.of_regval v) else
   if reg_name = "branchPending" then OPTION_MAP (\ v .  branchPending_ref.write_to v s) (branchPending_ref.of_regval v) else
   if reg_name = "CP0Status" then OPTION_MAP (\ v .  CP0Status_ref.write_to v s) (CP0Status_ref.of_regval v) else
+  if reg_name = "CP0ConfigK0" then OPTION_MAP (\ v .  CP0ConfigK0_ref.write_to v s) (CP0ConfigK0_ref.of_regval v) else
   if reg_name = "CP0UserLocal" then OPTION_MAP (\ v .  CP0UserLocal_ref.write_to v s) (CP0UserLocal_ref.of_regval v) else
   if reg_name = "CP0HWREna" then OPTION_MAP (\ v .  CP0HWREna_ref.write_to v s) (CP0HWREna_ref.of_regval v) else
   if reg_name = "CP0Count" then OPTION_MAP (\ v .  CP0Count_ref.write_to v s) (CP0Count_ref.of_regval v) else
diff --git a/snapshots/hol4/sail/cheri/mips_extrasScript.sml b/snapshots/hol4/sail/cheri/mips_extrasScript.sml
index 399ecc93..aef40b53 100644
--- a/snapshots/hol4/sail/cheri/mips_extrasScript.sml
+++ b/snapshots/hol4/sail/cheri/mips_extrasScript.sml
@@ -1,6 +1,6 @@
-(*Generated by Lem from /usr/local/google/home/ramanakumar/cheri/sail/mips/mips_extras.lem.*)
+(*Generated by Lem from mips_extras.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory prompt_monadTheory promptTheory sail_operatorsTheory;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_promptTheory sail2_operatorsTheory;
 
 val _ = numLib.prefer_num();
 
@@ -10,11 +10,11 @@ val _ = new_theory "mips_extras"
 
 (*open import Pervasives*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 
 (*val MEMr             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*)
 (*val MEMr_reserve     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*)
@@ -22,43 +22,43 @@ val _ = new_theory "mips_extras"
 (*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*)
 
 val _ = Define `
- ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=              (state_monad$read_memS 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1))`;
+ ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=              (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1))`;
 
 val _ = Define `
- ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=      (state_monad$read_memS 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1))`;
+ ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=      (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_reserve addr size1))`;
 
 
 (*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*)
 val _ = Define `
- ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a addr=  (state_monad$bindS
-  (state_monad$read_tagS 
-  dict_Sail_values_Bitvector_a addr) (\ t . 
-  state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`;
+ ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a addr=  (sail2_state_monad$bindS
+  (sail2_state_monad$read_tagS 
+  dict_Sail2_values_Bitvector_a addr) (\ t . 
+  sail2_state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`;
 
 
 (*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*)
 val _ = Define `
- ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr t=  (state_monad$bindS (state_monad$write_tagS 
-  dict_Sail_values_Bitvector_a addr (bitU_of_bool t)) 
-  (\b .  (case (b ) of ( _ ) => state_monad$returnS ()  ))))`;
+ ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr t=  (sail2_state_monad$bindS (sail2_state_monad$write_tagS 
+  dict_Sail2_values_Bitvector_a addr (bitU_of_bool t)) 
+  (\b .  (case (b ) of ( _ ) => sail2_state_monad$returnS ()  ))))`;
 
 
 val _ = Define `
- ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=  (state_monad$bindS
-  (state_monad$read_memS 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v .  state_monad$bindS
-  (read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . 
-  state_monad$returnS (t, v)))))`;
+ ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=  (sail2_state_monad$bindS
+  (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v .  sail2_state_monad$bindS
+  (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . 
+  sail2_state_monad$returnS (t, v)))))`;
 
 
 val _ = Define `
- ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=  (state_monad$bindS
-  (state_monad$read_memS 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v .  state_monad$bindS
-  (read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . 
-  state_monad$returnS (t, v)))))`;
+ ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=  (sail2_state_monad$bindS
+  (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v .  sail2_state_monad$bindS
+  (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . 
+  sail2_state_monad$returnS (t, v)))))`;
 
 
 
@@ -68,21 +68,21 @@ val _ = Define `
 (*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*)
 
 val _ = Define `
- ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1=                  (state_monad$write_mem_eaS 
-  dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
+ ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=                  (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
 
 val _ = Define `
- ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1=      (state_monad$write_mem_eaS 
-  dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
+ ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=      (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
 
 
 val _ = Define `
- ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1=              (state_monad$write_mem_eaS 
-  dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
+ ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=              (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
 
 val _ = Define `
- ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1=  (state_monad$write_mem_eaS 
-  dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
+ ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=  (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
 
 
 
@@ -92,33 +92,35 @@ val _ = Define `
 (*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*)
 
 val _ = Define `
- ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v=                       (state_monad$bindS (state_monad$write_mem_valS 
-  dict_Sail_values_Bitvector_b v) (\b .  (case (b ) of ( _ ) => state_monad$returnS ()  ))))`;
+ ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v=                       (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\b .  (case (b ) of ( _ ) => sail2_state_monad$returnS ()  ))))`;
 
 val _ = Define `
- ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v=           (state_monad$bindS (state_monad$write_mem_valS 
-  dict_Sail_values_Bitvector_b v) (\ b .  state_monad$returnS (if b then T else F))))`;
+ ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v=           (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\ b .  sail2_state_monad$returnS (if b then T else F))))`;
 
 val _ = Define `
- ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v=              (state_monad$bindS (state_monad$write_mem_valS 
-  dict_Sail_values_Bitvector_b v) (\b .  (case (b ) of
-            ( _ ) => state_monad$bindS
-                       (write_tag_bool dict_Sail_values_Bitvector_a addr t)
+ ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v=              (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\b .  (case (b ) of
+            ( _ ) => sail2_state_monad$bindS
+                       (write_tag_bool dict_Sail2_values_Bitvector_a addr t)
                        (\u .  (case (u ) of
-                                  ( _ ) => state_monad$returnS () 
+                                  ( _ ) => sail2_state_monad$returnS () 
                               ))
         ))))`;
 
 val _ = Define `
- ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v=  (state_monad$bindS (state_monad$write_mem_valS 
-  dict_Sail_values_Bitvector_b v) (\ b .  state_monad$bindS (write_tag_bool 
-  dict_Sail_values_Bitvector_a addr t) (\u .  (case (u ) of ( _ ) => state_monad$returnS (if b then T else F) )))))`;
+ ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v=  (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\ b .  sail2_state_monad$bindS (write_tag_bool 
+  dict_Sail2_values_Bitvector_a addr t) (\u .  (case (u ) of
+            ( _ ) => sail2_state_monad$returnS (if b then T else F)
+        )))))`;
 
 
 (*val MEM_sync  : forall 'regval 'e. unit -> monad 'regval unit 'e*)
 
 val _ = Define `
- ((MEM_sync:unit -> 'regval state_monad$sequential_state ->(((unit),'e)state_monad$result#'regval state_monad$sequential_state)set) () =  (barrier Barrier_MIPS_SYNC))`;
+ ((MEM_sync:unit -> 'regval sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'regval sail2_state_monad$sequential_state)set) () =  (barrier Barrier_MIPS_SYNC))`;
 
 
 (* Some wrappers copied from aarch64_extras *)
@@ -134,104 +136,87 @@ val _ = Define `
 
 (*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
 val _ = Define `
- ((get_slice_int0:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo=  (
-  dict_Sail_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`;
+ ((get_slice_int0:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo=  (
+  dict_Sail2_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`;
 
 
 val _ = Define `
- ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd state_monad$sequential_state ->(((unit),'c)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data=  (state_monad$seqS
-  (MEMea dict_Sail_values_Bitvector_b addr size1)
-  (MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data)))`;
+ ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd sail2_state_monad$sequential_state ->(((unit),'c)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 _ addr data=  (sail2_state_monad$seqS
+  (MEMea dict_Sail2_values_Bitvector_b addr size1)
+  (MEMval dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a addr size1 data)))`;
 
 
 val _ = Define `
- ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd state_monad$sequential_state ->(('c,'b)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr=  (MEMr 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1))`;
+ ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd sail2_state_monad$sequential_state ->(('c,'b)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c _ size1 _ addr=  (MEMr 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c addr size1))`;
 
 
-val _ = Define `
- ((string_of_bits:'a Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a bs=  (string_of_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (dict_Sail_values_Bitvector_a.bits_of_method bs)))`;
-
 val _ = Define `
  ((string_of_int:'a Show_class -> 'a -> string)dict_Show_Show_a= 
   (dict_Show_Show_a.show_method))`;
 
 
 val _ = Define `
- ((sign_extend0:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len=  (maybe_failwith (
-  dict_Sail_values_Bitvector_b.of_bits_method (exts_bv dict_Sail_values_Bitvector_a len bits))))`;
-
-val _ = Define `
- ((zero_extend0:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len=  (maybe_failwith (
-  dict_Sail_values_Bitvector_b.of_bits_method (extz_bv dict_Sail_values_Bitvector_a len bits))))`;
-
-
-val _ = Define `
- ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n=
+ ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n=
    (let r = (OPTION_BIND (
-  dict_Sail_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail_values_Bitvector_d v n))) in
-  state_monad$maybe_failS "shift_bits_left" r))`;
+  dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail2_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail2_values_Bitvector_d v n))) in
+  sail2_state_monad$maybe_failS "shift_bits_left" r))`;
 
 val _ = Define `
- ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n=
+ ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n=
    (let r = (OPTION_BIND (
-  dict_Sail_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail_values_Bitvector_d v n))) in
-  state_monad$maybe_failS "shift_bits_right" r))`;
+  dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail2_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail2_values_Bitvector_d v n))) in
+  sail2_state_monad$maybe_failS "shift_bits_right" r))`;
 
 val _ = Define `
- ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n=
+ ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n=
    (let r = (OPTION_BIND (
-  dict_Sail_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in
-  state_monad$maybe_failS "shift_bits_right_arith" r))`;
+  dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail2_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail2_values_Bitvector_d v n))) in
+  sail2_state_monad$maybe_failS "shift_bits_right_arith" r))`;
 
 
 (* Use constants for undefined values for now *)
 val _ = Define `
- ((internal_pick:'a list -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) vs=  (state_monad$returnS (HD vs)))`;
-
-val _ = Define `
- ((undefined_string:unit -> 'a state_monad$sequential_state ->(((string),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS ""))`;
+ ((undefined_string:unit -> 'a sail2_state_monad$sequential_state ->(((string),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS ""))`;
 
 val _ = Define `
- ((undefined_unit:unit -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS () ))`;
+ ((undefined_unit:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS () ))`;
 
 val _ = Define `
- ((undefined_int:unit -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS (( 0 : int):ii)))`;
+ ((undefined_int:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (( 0 : int):ii)))`;
 
 (*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
 val _ = Define `
- ((undefined_vector:int -> 'a -> 'rv state_monad$sequential_state ->((('a list),'e)state_monad$result#'rv state_monad$sequential_state)set) len u=  (state_monad$returnS (repeat [u] len)))`;
+ ((undefined_vector:int -> 'a -> 'rv sail2_state_monad$sequential_state ->((('a list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len u=  (sail2_state_monad$returnS (repeat [u] len)))`;
 
 (*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
 val _ = Define `
- ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail_values_Bitvector_a len=  (state_monad$returnS (
-  dict_Sail_values_Bitvector_a.of_bools_method (repeat [F] len))))`;
+ ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a len=  (sail2_state_monad$returnS (
+  dict_Sail2_values_Bitvector_a.of_bools_method (repeat [F] len))))`;
 
 (*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
 val _ = Define `
- ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail_values_Bitvector_a= 
-  (undefined_bitvector dict_Sail_values_Bitvector_a))`;
+ ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a= 
+  (undefined_bitvector dict_Sail2_values_Bitvector_a))`;
 
 val _ = Define `
- ((undefined_bit:unit -> 'a state_monad$sequential_state ->(((bitU),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS B0))`;
+ ((undefined_bit:unit -> 'a sail2_state_monad$sequential_state ->(((bitU),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS B0))`;
 
 val _ = Define `
- ((undefined_real:unit -> 'a state_monad$sequential_state ->(((real),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`;
+ ((undefined_real:unit -> 'a sail2_state_monad$sequential_state ->(((real),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`;
 
 val _ = Define `
- ((undefined_range:'a -> 'd -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) i j=  (state_monad$returnS i))`;
+ ((undefined_range:'a -> 'd -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i j=  (sail2_state_monad$returnS i))`;
 
 val _ = Define `
- ((undefined_atom:'a -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) i=  (state_monad$returnS i))`;
+ ((undefined_atom:'a -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i=  (sail2_state_monad$returnS i))`;
 
 val _ = Define `
- ((undefined_nat:unit -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS (( 0 : int):ii)))`;
+ ((undefined_nat:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (( 0 : int):ii)))`;
 
 
 val _ = Define `
- ((skip:unit -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$returnS () ))`;
+ ((skip:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS () ))`;
 
 
 (*val elf_entry : unit -> integer*)
@@ -240,13 +225,18 @@ val _ = Define `
 
 
 val _ = Define `
- ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bits 
-  dict_Sail_values_Bitvector_a bs))))`;
+ ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bv 
+  dict_Sail2_values_Bitvector_a bs))))`;
 
 
 (*val get_time_ns : unit -> integer*)
 val _ = Define `
  ((get_time_ns:unit -> int) () = (( 0 : int)))`;
 
+
+(*val cycle_count : unit -> unit*)
+val _ = Define `
+ ((cycle_count:unit -> unit) _=  () )`;
+
 val _ = export_theory()
 
diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile
index 161de9d3..0e95ba5e 100644
--- a/snapshots/hol4/sail/lib/hol/Holmakefile
+++ b/snapshots/hol4/sail/lib/hol/Holmakefile
@@ -1,11 +1,12 @@
-LEM_SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \
-  sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \
-  state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml
+LEM_SCRIPTS = sail2_instr_kindsScript.sml sail2_valuesScript.sml sail2_operatorsScript.sml \
+  sail2_operators_mwordsScript.sml sail2_operators_bitlistsScript.sml \
+  sail2_state_monadScript.sml sail2_stateScript.sml sail2_promptScript.sml sail2_prompt_monadScript.sml \
+  sail2_stringScript.sml
 
 LEM_CLEANS = $(LEM_SCRIPTS)
 
 SCRIPTS = $(LEM_SCRIPTS) \
-  sail_valuesAuxiliaryScript.sml stateAuxiliaryScript.sml
+  sail2_valuesAuxiliaryScript.sml sail2_stateAuxiliaryScript.sml
 
 THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
 
diff --git a/snapshots/hol4/sail/lib/hol/promptScript.sml b/snapshots/hol4/sail/lib/hol/promptScript.sml
deleted file mode 100644
index 95d6e752..00000000
--- a/snapshots/hol4/sail/lib/hol/promptScript.sml
+++ /dev/null
@@ -1,15 +0,0 @@
-(*Generated by Lem from prompt.lem.*)
-open HolKernel Parse boolLib bossLib;
-open prompt_monadTheory state_monadTheory stateTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "prompt"
-
-(*open import Prompt_monad*)
-(*open import State_monad*)
-(*open import State*)
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml b/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml
deleted file mode 100644
index 7c18567b..00000000
--- a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml
+++ /dev/null
@@ -1,31 +0,0 @@
-(*Generated by Lem from prompt_monad.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_valuesTheory sail_instr_kindsTheory state_monadTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "prompt_monad"
-
-(*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import State_monad*)
-
-(* Fake interface of the prompt monad by redirecting to the state monad, since
-   the former is not currently supported by HOL4 *)
-
-val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e) *) "monad" , ``:('a_rv,'b_a,'c_e) monadS``);
-val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e, 'd_r) *) "monadR" , ``:('a_rv,'b_a,'c_e,'d_r) monadRS``);
-
-(* We need to use a target_rep for these because HOL doesn't handle unused
-   type parameters well. *)
-
-(*type base_monad 'regval 'regstate 'a 'e = monad 'regstate 'a 'e*)
-(*type base_monadR 'regval 'regstate 'a 'r 'e = monadR 'regstate 'a 'r 'e*)
-val _ = Define `
- ((barrier:'c -> 'a sequential_state ->(((unit),'b)result#'a sequential_state)set) _=  (returnS () ))`;
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/sail2_instr_kindsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_instr_kindsScript.sml
new file mode 100644
index 00000000..b8a643ef
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_instr_kindsScript.sml
@@ -0,0 +1,448 @@
+(*Generated by Lem from ../../src/lem_interp/sail2_instr_kinds.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_instr_kinds"
+
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(*open import Pervasives_extra*)
+
+
+val _ = Hol_datatype `
+(*  'a *) EnumerationType_class= <|
+  toNat_method : 'a -> num
+|>`;
+
+
+
+(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*)
+val _ = Define `
+ ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> ordering)dict_Sail2_instr_kinds_EnumerationType_a e1 e2=
+   (genericCompare (<) (=) (
+  dict_Sail2_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail2_instr_kinds_EnumerationType_a.toNat_method e2)))`;
+
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a Ord_class)dict_Sail2_instr_kinds_EnumerationType_a= (<|
+
+  compare_method := 
+  (enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a);
+
+  isLess_method := (\  r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = LESS);
+
+  isLessEqual_method := (\ r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) <> GREATER);
+
+  isGreater_method := (\  r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = GREATER);
+
+  isGreaterEqual_method := (\ r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) <> LESS)|>))`;
+
+
+
+(* Data structures for building up instructions *)
+
+(* careful: changes in the read/write/barrier kinds have to be
+   reflected in deep_shallow_convert *)
+val _ = Hol_datatype `
+ read_kind =
+  (* common reads *)
+    Read_plain
+  (* Power reads *)
+  | Read_reserve
+  (* AArch64 reads *)
+  | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+  (* RISC-V reads *)
+  | Read_RISCV_acquire  | Read_RISCV_strong_acquire
+  | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+  | Read_RISCV_reserved_strong_acquire
+  (* x86 reads *)
+  | Read_X86_locked`;
+ (* the read part of a lock'd instruction (rmw) *)
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_read_kind_dict:(read_kind)Show_class)= (<|
+
+  show_method := (\x .  
+  (case x of
+        Read_plain => "Read_plain"
+    | Read_reserve => "Read_reserve"
+    | Read_acquire => "Read_acquire"
+    | Read_exclusive => "Read_exclusive"
+    | Read_exclusive_acquire => "Read_exclusive_acquire"
+    | Read_stream => "Read_stream"
+    | Read_RISCV_acquire => "Read_RISCV_acquire"
+    | Read_RISCV_strong_acquire => "Read_RISCV_strong_acquire"
+    | Read_RISCV_reserved => "Read_RISCV_reserved"
+    | Read_RISCV_reserved_acquire => "Read_RISCV_reserved_acquire"
+    | Read_RISCV_reserved_strong_acquire => "Read_RISCV_reserved_strong_acquire"
+    | Read_X86_locked => "Read_X86_locked"
+  ))|>))`;
+
+
+val _ = Hol_datatype `
+ write_kind =
+  (* common writes *)
+    Write_plain
+  (* Power writes *)
+  | Write_conditional
+  (* AArch64 writes *)
+  | Write_release | Write_exclusive | Write_exclusive_release
+  (* RISC-V *)
+  | Write_RISCV_release     | Write_RISCV_strong_release
+  | Write_RISCV_conditional | Write_RISCV_conditional_release
+  | Write_RISCV_conditional_strong_release
+  (* x86 writes *)
+  | Write_X86_locked`;
+ (* the write part of a lock'd instruction (rmw) *)
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_write_kind_dict:(write_kind)Show_class)= (<|
+
+  show_method := (\x .  
+  (case x of
+        Write_plain => "Write_plain"
+    | Write_conditional => "Write_conditional"
+    | Write_release => "Write_release"
+    | Write_exclusive => "Write_exclusive"
+    | Write_exclusive_release => "Write_exclusive_release"
+    | Write_RISCV_release => "Write_RISCV_release"
+    | Write_RISCV_strong_release => "Write_RISCV_strong_release"
+    | Write_RISCV_conditional => "Write_RISCV_conditional"
+    | Write_RISCV_conditional_release => "Write_RISCV_conditional_release"
+    | Write_RISCV_conditional_strong_release => "Write_RISCV_conditional_strong_release"
+    | Write_X86_locked => "Write_X86_locked"
+  ))|>))`;
+
+
+val _ = Hol_datatype `
+ barrier_kind =
+  (* Power barriers *)
+  Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
+  (* AArch64 barriers *)
+  | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
+  | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
+  | Barrier_TM_COMMIT
+  (* MIPS barriers *)
+  | Barrier_MIPS_SYNC
+  (* RISC-V barriers *)
+  | Barrier_RISCV_rw_rw
+  | Barrier_RISCV_r_rw
+  | Barrier_RISCV_r_r
+  | Barrier_RISCV_rw_w
+  | Barrier_RISCV_w_w
+  | Barrier_RISCV_w_rw
+  | Barrier_RISCV_rw_r
+  | Barrier_RISCV_r_w
+  | Barrier_RISCV_w_r
+  | Barrier_RISCV_i
+  (* X86 *)
+  | Barrier_x86_MFENCE`;
+
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict:(barrier_kind)Show_class)= (<|
+
+  show_method := (\x .  
+  (case x of
+        Barrier_Sync => "Barrier_Sync"
+    | Barrier_LwSync => "Barrier_LwSync"
+    | Barrier_Eieio => "Barrier_Eieio"
+    | Barrier_Isync => "Barrier_Isync"
+    | Barrier_DMB => "Barrier_DMB"
+    | Barrier_DMB_ST => "Barrier_DMB_ST"
+    | Barrier_DMB_LD => "Barrier_DMB_LD"
+    | Barrier_DSB => "Barrier_DSB"
+    | Barrier_DSB_ST => "Barrier_DSB_ST"
+    | Barrier_DSB_LD => "Barrier_DSB_LD"
+    | Barrier_ISB => "Barrier_ISB"
+    | Barrier_TM_COMMIT => "Barrier_TM_COMMIT"
+    | Barrier_MIPS_SYNC => "Barrier_MIPS_SYNC"
+    | Barrier_RISCV_rw_rw => "Barrier_RISCV_rw_rw"
+    | Barrier_RISCV_r_rw => "Barrier_RISCV_r_rw"
+    | Barrier_RISCV_r_r => "Barrier_RISCV_r_r"
+    | Barrier_RISCV_rw_w => "Barrier_RISCV_rw_w"
+    | Barrier_RISCV_w_w => "Barrier_RISCV_w_w"
+    | Barrier_RISCV_w_rw => "Barrier_RISCV_w_rw"
+    | Barrier_RISCV_rw_r => "Barrier_RISCV_rw_r"
+    | Barrier_RISCV_r_w => "Barrier_RISCV_r_w"
+    | Barrier_RISCV_w_r => "Barrier_RISCV_w_r"
+    | Barrier_RISCV_i => "Barrier_RISCV_i"
+    | Barrier_x86_MFENCE => "Barrier_x86_MFENCE"
+  ))|>))`;
+
+
+val _ = Hol_datatype `
+ trans_kind =
+  (* AArch64 *)
+    Transaction_start | Transaction_commit | Transaction_abort`;
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_trans_kind_dict:(trans_kind)Show_class)= (<|
+
+  show_method := (\x .  
+  (case x of
+        Transaction_start => "Transaction_start"
+    | Transaction_commit => "Transaction_commit"
+    | Transaction_abort => "Transaction_abort"
+  ))|>))`;
+
+
+val _ = Hol_datatype `
+ instruction_kind =
+    IK_barrier   of barrier_kind
+  | IK_mem_read  of read_kind
+  | IK_mem_write of write_kind
+  | IK_mem_rmw   of (read_kind # write_kind)
+  | IK_branch    of unit(* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+  indirect/computed-branch (single nia of kind NIA_indirect_address)
+  and branch/jump (single nia of kind NIA_concrete_address) *)
+  | IK_trans     of trans_kind
+  | IK_simple    of unit`;
+
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict:(instruction_kind)Show_class)= (<|
+
+  show_method := (\x .  
+  (case x of
+        IK_barrier barrier_kind => STRCAT "IK_barrier "
+                                     (((\x .  (case x of
+                                                    Barrier_Sync => "Barrier_Sync"
+                                                | Barrier_LwSync => "Barrier_LwSync"
+                                                | Barrier_Eieio => "Barrier_Eieio"
+                                                | Barrier_Isync => "Barrier_Isync"
+                                                | Barrier_DMB => "Barrier_DMB"
+                                                | Barrier_DMB_ST => "Barrier_DMB_ST"
+                                                | Barrier_DMB_LD => "Barrier_DMB_LD"
+                                                | Barrier_DSB => "Barrier_DSB"
+                                                | Barrier_DSB_ST => "Barrier_DSB_ST"
+                                                | Barrier_DSB_LD => "Barrier_DSB_LD"
+                                                | Barrier_ISB => "Barrier_ISB"
+                                                | Barrier_TM_COMMIT => 
+                                              "Barrier_TM_COMMIT"
+                                                | Barrier_MIPS_SYNC => 
+                                              "Barrier_MIPS_SYNC"
+                                                | Barrier_RISCV_rw_rw => 
+                                              "Barrier_RISCV_rw_rw"
+                                                | Barrier_RISCV_r_rw => 
+                                              "Barrier_RISCV_r_rw"
+                                                | Barrier_RISCV_r_r => 
+                                              "Barrier_RISCV_r_r"
+                                                | Barrier_RISCV_rw_w => 
+                                              "Barrier_RISCV_rw_w"
+                                                | Barrier_RISCV_w_w => 
+                                              "Barrier_RISCV_w_w"
+                                                | Barrier_RISCV_w_rw => 
+                                              "Barrier_RISCV_w_rw"
+                                                | Barrier_RISCV_rw_r => 
+                                              "Barrier_RISCV_rw_r"
+                                                | Barrier_RISCV_r_w => 
+                                              "Barrier_RISCV_r_w"
+                                                | Barrier_RISCV_w_r => 
+                                              "Barrier_RISCV_w_r"
+                                                | Barrier_RISCV_i => 
+                                              "Barrier_RISCV_i"
+                                                | Barrier_x86_MFENCE => 
+                                              "Barrier_x86_MFENCE"
+                                              )) barrier_kind))
+    | IK_mem_read read_kind => STRCAT "IK_mem_read "
+                                 (((\x .  (case x of
+                                                Read_plain => "Read_plain"
+                                            | Read_reserve => "Read_reserve"
+                                            | Read_acquire => "Read_acquire"
+                                            | Read_exclusive => "Read_exclusive"
+                                            | Read_exclusive_acquire => 
+                                          "Read_exclusive_acquire"
+                                            | Read_stream => "Read_stream"
+                                            | Read_RISCV_acquire => "Read_RISCV_acquire"
+                                            | Read_RISCV_strong_acquire => 
+                                          "Read_RISCV_strong_acquire"
+                                            | Read_RISCV_reserved => 
+                                          "Read_RISCV_reserved"
+                                            | Read_RISCV_reserved_acquire => 
+                                          "Read_RISCV_reserved_acquire"
+                                            | Read_RISCV_reserved_strong_acquire => 
+                                          "Read_RISCV_reserved_strong_acquire"
+                                            | Read_X86_locked => "Read_X86_locked"
+                                          )) read_kind))
+    | IK_mem_write write_kind => STRCAT "IK_mem_write "
+                                   (((\x .  (case x of
+                                                  Write_plain => "Write_plain"
+                                              | Write_conditional => 
+                                            "Write_conditional"
+                                              | Write_release => "Write_release"
+                                              | Write_exclusive => "Write_exclusive"
+                                              | Write_exclusive_release => 
+                                            "Write_exclusive_release"
+                                              | Write_RISCV_release => 
+                                            "Write_RISCV_release"
+                                              | Write_RISCV_strong_release => 
+                                            "Write_RISCV_strong_release"
+                                              | Write_RISCV_conditional => 
+                                            "Write_RISCV_conditional"
+                                              | Write_RISCV_conditional_release => 
+                                            "Write_RISCV_conditional_release"
+                                              | Write_RISCV_conditional_strong_release => 
+                                            "Write_RISCV_conditional_strong_release"
+                                              | Write_X86_locked => "Write_X86_locked"
+                                            )) write_kind))
+    | IK_mem_rmw (r, w) => STRCAT "IK_mem_rmw "
+                             (STRCAT
+                                (((\x .  (case x of
+                                               Read_plain => "Read_plain"
+                                           | Read_reserve => "Read_reserve"
+                                           | Read_acquire => "Read_acquire"
+                                           | Read_exclusive => "Read_exclusive"
+                                           | Read_exclusive_acquire => 
+                                         "Read_exclusive_acquire"
+                                           | Read_stream => "Read_stream"
+                                           | Read_RISCV_acquire => "Read_RISCV_acquire"
+                                           | Read_RISCV_strong_acquire => 
+                                         "Read_RISCV_strong_acquire"
+                                           | Read_RISCV_reserved => "Read_RISCV_reserved"
+                                           | Read_RISCV_reserved_acquire => 
+                                         "Read_RISCV_reserved_acquire"
+                                           | Read_RISCV_reserved_strong_acquire => 
+                                         "Read_RISCV_reserved_strong_acquire"
+                                           | Read_X86_locked => "Read_X86_locked"
+                                         )) r))
+                                (STRCAT " "
+                                   (((\x .  (case x of
+                                                  Write_plain => "Write_plain"
+                                              | Write_conditional => 
+                                            "Write_conditional"
+                                              | Write_release => "Write_release"
+                                              | Write_exclusive => "Write_exclusive"
+                                              | Write_exclusive_release => 
+                                            "Write_exclusive_release"
+                                              | Write_RISCV_release => 
+                                            "Write_RISCV_release"
+                                              | Write_RISCV_strong_release => 
+                                            "Write_RISCV_strong_release"
+                                              | Write_RISCV_conditional => 
+                                            "Write_RISCV_conditional"
+                                              | Write_RISCV_conditional_release => 
+                                            "Write_RISCV_conditional_release"
+                                              | Write_RISCV_conditional_strong_release => 
+                                            "Write_RISCV_conditional_strong_release"
+                                              | Write_X86_locked => "Write_X86_locked"
+                                            )) w))))
+    | IK_branch ()  => "IK_branch"
+    | IK_trans trans_kind => STRCAT "IK_trans "
+                               (((\x .  (case x of
+                                              Transaction_start => "Transaction_start"
+                                          | Transaction_commit => "Transaction_commit"
+                                          | Transaction_abort => "Transaction_abort"
+                                        )) trans_kind))
+    | IK_simple ()  => "IK_simple"
+  ))|>))`;
+
+
+
+val _ = Define `
+ ((read_is_exclusive:read_kind -> bool)= 
+  (\x .  (case x of
+               Read_plain => F
+           | Read_reserve => T
+           | Read_acquire => F
+           | Read_exclusive => T
+           | Read_exclusive_acquire => T
+           | Read_stream => F
+           | Read_RISCV_acquire => F
+           | Read_RISCV_strong_acquire => F
+           | Read_RISCV_reserved => T
+           | Read_RISCV_reserved_acquire => T
+           | Read_RISCV_reserved_strong_acquire => T
+           | Read_X86_locked => T
+         )))`;
+
+
+
+
+val _ = Define `
+((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict:(read_kind)EnumerationType_class)= (<|
+
+  toNat_method := (\x .  
+  (case x of
+        Read_plain =>( 0 : num)
+    | Read_reserve =>( 1 : num)
+    | Read_acquire =>( 2 : num)
+    | Read_exclusive =>( 3 : num)
+    | Read_exclusive_acquire =>( 4 : num)
+    | Read_stream =>( 5 : num)
+    | Read_RISCV_acquire =>( 6 : num)
+    | Read_RISCV_strong_acquire =>( 7 : num)
+    | Read_RISCV_reserved =>( 8 : num)
+    | Read_RISCV_reserved_acquire =>( 9 : num)
+    | Read_RISCV_reserved_strong_acquire =>( 10 : num)
+    | Read_X86_locked =>( 11 : num)
+  ))|>))`;
+
+
+val _ = Define `
+((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict:(write_kind)EnumerationType_class)= (<|
+
+  toNat_method := (\x .  
+  (case x of
+        Write_plain =>( 0 : num)
+    | Write_conditional =>( 1 : num)
+    | Write_release =>( 2 : num)
+    | Write_exclusive =>( 3 : num)
+    | Write_exclusive_release =>( 4 : num)
+    | Write_RISCV_release =>( 5 : num)
+    | Write_RISCV_strong_release =>( 6 : num)
+    | Write_RISCV_conditional =>( 7 : num)
+    | Write_RISCV_conditional_release =>( 8 : num)
+    | Write_RISCV_conditional_strong_release =>( 9 : num)
+    | Write_X86_locked =>( 10 : num)
+  ))|>))`;
+
+
+val _ = Define `
+((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict:(barrier_kind)EnumerationType_class)= (<|
+
+  toNat_method := (\x .  
+  (case x of
+        Barrier_Sync =>( 0 : num)
+    | Barrier_LwSync =>( 1 : num)
+    | Barrier_Eieio =>( 2 : num)
+    | Barrier_Isync =>( 3 : num)
+    | Barrier_DMB =>( 4 : num)
+    | Barrier_DMB_ST =>( 5 : num)
+    | Barrier_DMB_LD =>( 6 : num)
+    | Barrier_DSB =>( 7 : num)
+    | Barrier_DSB_ST =>( 8 : num)
+    | Barrier_DSB_LD =>( 9 : num)
+    | Barrier_ISB =>( 10 : num)
+    | Barrier_TM_COMMIT =>( 11 : num)
+    | Barrier_MIPS_SYNC =>( 12 : num)
+    | Barrier_RISCV_rw_rw =>( 13 : num)
+    | Barrier_RISCV_r_rw =>( 14 : num)
+    | Barrier_RISCV_r_r =>( 15 : num)
+    | Barrier_RISCV_rw_w =>( 16 : num)
+    | Barrier_RISCV_w_w =>( 17 : num)
+    | Barrier_RISCV_w_rw =>( 18 : num)
+    | Barrier_RISCV_rw_r =>( 19 : num)
+    | Barrier_RISCV_r_w =>( 20 : num)
+    | Barrier_RISCV_w_r =>( 21 : num)
+    | Barrier_RISCV_i =>( 22 : num)
+    | Barrier_x86_MFENCE =>( 23 : num)
+  ))|>))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_operatorsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operatorsScript.sml
new file mode 100644
index 00000000..c2c3a727
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_operatorsScript.sml
@@ -0,0 +1,327 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_operators.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_operators"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+
+(*** Bit vector operations *)
+
+(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*)
+val _ = Define `
+ ((concat_bv:'a Bitvector_class -> 'b Bitvector_class -> 'a -> 'b ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b l r=  (
+  dict_Sail2_values_Bitvector_a.bits_of_method l ++ dict_Sail2_values_Bitvector_b.bits_of_method r))`;
+
+
+(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*)
+val _ = Define `
+ ((cons_bv:'a Bitvector_class -> bitU -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a b v=  (b :: 
+  dict_Sail2_values_Bitvector_a.bits_of_method v))`;
+
+
+(*val cast_unit_bv : bitU -> list bitU*)
+val _ = Define `
+ ((cast_unit_bv:bitU ->(bitU)list) b=  ([b]))`;
+
+
+(*val bv_of_bit : integer -> bitU -> list bitU*)
+val _ = Define `
+ ((bv_of_bit:int -> bitU ->(bitU)list) len b=  (extz_bits len [b]))`;
+
+
+val _ = Define `
+ ((most_significant:'a Bitvector_class -> 'a -> bitU)dict_Sail2_values_Bitvector_a v=  ((case  
+  dict_Sail2_values_Bitvector_a.bits_of_method v of
+    b :: _ => b
+  | _ => B0 (* Treat empty bitvector as all zeros *)
+  )))`;
+
+
+val _ = Define `
+ ((get_max_representable_in:bool -> int -> int) sign (n : int) : int=
+   (if (n =( 64 : int)) then (case sign of   T => max_64 | F => max_64u )
+  else if (n=( 32 : int)) then (case sign of   T => max_32 | F => max_32u )
+  else if (n=( 8 : int)) then max_8
+  else if (n=( 5 : int)) then max_5
+  else (case sign of   T => (( 2 : int))** ((Num (ABS (I n))) -( 1 : num))
+                       | F => (( 2 : int))** (Num (ABS (I n)))
+       )))`;
+
+
+val _ = Define `
+ ((get_min_representable_in:'a -> int -> int) _ (n : int) : int=
+   (if n =( 64 : int) then min_64
+  else if n =( 32 : int) then min_32
+  else if n =( 8 : int) then min_8
+  else if n =( 5 : int) then min_5
+  else( 0 : int) - ((( 2 : int))** (Num (ABS (I n))))))`;
+
+
+(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
+val _ = Define `
+ ((arith_op_bv_int:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail2_values_Bitvector_a op sign l r=
+   (let r' = (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method l) r) in  dict_Sail2_values_Bitvector_a.arith_op_bv_method op sign l r'))`;
+
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
+val _ = Define `
+ ((arith_op_int_bv:'a Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail2_values_Bitvector_a op sign l r=
+   (let l' = (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method r) l) in  dict_Sail2_values_Bitvector_a.arith_op_bv_method op sign l' r))`;
+
+
+val _ = Define `
+ ((arith_op_bv_bool:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a op sign l r=  (arith_op_bv_int 
+  dict_Sail2_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`;
+
+val _ = Define `
+ ((arith_op_bv_bit:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a op sign l r=  (OPTION_MAP (arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a op sign l) (bool_of_bitU r)))`;
+
+
+(* TODO (or just omit and define it per spec if needed)
+val arith_op_overflow_bv : forall 'a. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv op sign size l r =
+  let len = length l in
+  let act_size = len * size in
+  match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with
+    | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) ->
+       let n = op l_sign r_sign in
+       let n_unsign = op l_unsign r_unsign in
+       let correct_size = of_int act_size n in
+       let one_more_size_u = bits_of_int (act_size + 1) n_unsign in
+       let overflow =
+         if n <= get_max_representable_in sign len &&
+              n >= get_min_representable_in sign len
+         then B0 else B1 in
+       let c_out = most_significant one_more_size_u in
+       (correct_size,overflow,c_out)
+    | (_, _, _, _) ->
+       (repeat [BU] act_size, BU, BU)
+  end
+
+let add_overflow_bv = arith_op_overflow_bv integerAdd false 1
+let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1
+let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1
+let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1
+let mult_overflow_bv = arith_op_overflow_bv integerMult false 2
+let mults_overflow_bv = arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv_bit op sign size l r_bit =
+  let act_size = length l * size in
+  match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with
+    | (Just l', Just l_u, false) ->
+       let (n, nu, changed) = match r_bit with
+         | B1 -> (op l' 1, op l_u 1, true)
+         | B0 -> (l', l_u, false)
+         | BU -> (* unreachable due to check above *)
+            failwith "arith_op_overflow_bv_bit applied to undefined bit"
+         end in
+       let correct_size = of_int act_size n in
+       let one_larger = bits_of_int (act_size + 1) nu in
+       let overflow =
+         if changed
+         then
+           if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+           then B0 else B1
+         else B0 in
+       (correct_size, overflow, most_significant one_larger)
+    | (_, _, _) ->
+       (repeat [BU] act_size, BU, BU)
+  end
+
+let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1
+let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1
+let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1
+let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*)
+
+val _ = Hol_datatype `
+ shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot`;
+
+
+val _ = Define `
+ ((invert_shift:shift -> shift)= 
+  (\x .  (case x of
+               LL_shift => RR_shift
+           | RR_shift => LL_shift
+           | RR_shift_arith => LL_shift
+           | LL_rot => RR_rot
+           | RR_rot => LL_rot
+         )))`;
+
+
+(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*)
+val _ = Define `
+ ((shift_op_bv:'a Bitvector_class -> shift -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a op v n=
+   (let v = (dict_Sail2_values_Bitvector_a.bits_of_method v) in
+  if n =( 0 : int) then v else
+  let (op, n) = (if n >( 0 : int) then (op, n) else (invert_shift op, ~ n)) in
+  (case op of
+    LL_shift =>
+     subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ repeat [B0] n
+  | RR_shift =>
+     repeat [B0] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int))
+  | RR_shift_arith =>
+     repeat [most_significant 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) v] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int))
+  | LL_rot =>
+     subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ subrange_list T v(( 0 : int)) (n -( 1 : int))
+  | RR_rot =>
+     subrange_list F v(( 0 : int)) (n -( 1 : int)) ++ subrange_list F v n (int_of_num (LENGTH v) -( 1 : int))
+  )))`;
+
+
+val _ = Define `
+ ((shiftl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a=  (shift_op_bv 
+  dict_Sail2_values_Bitvector_a LL_shift))`;
+ (*"<<"*)
+val _ = Define `
+ ((shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a=  (shift_op_bv 
+  dict_Sail2_values_Bitvector_a RR_shift))`;
+ (*">>"*)
+val _ = Define `
+ ((arith_shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a=  (shift_op_bv 
+  dict_Sail2_values_Bitvector_a RR_shift_arith))`;
+
+val _ = Define `
+ ((rotl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a=  (shift_op_bv 
+  dict_Sail2_values_Bitvector_a LL_rot))`;
+ (*"<<<"*)
+val _ = Define `
+ ((rotr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a=  (shift_op_bv 
+  dict_Sail2_values_Bitvector_a LL_rot))`;
+ (*">>>"*)
+
+val _ = Define `
+ ((shiftl_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_lsl w (nat_of_int n)))`;
+
+val _ = Define `
+ ((shiftr_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_lsr w (nat_of_int n)))`;
+
+val _ = Define `
+ ((arith_shiftr_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_asr w (nat_of_int n)))`;
+
+val _ = Define `
+ ((rotl_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_rol w (nat_of_int n)))`;
+
+val _ = Define `
+ ((rotr_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_ror w (nat_of_int n)))`;
+
+
+ val _ = Define `
+ ((arith_op_no0:(int -> int -> int) -> int -> int ->(int)option) (op : int -> int -> int) l r=
+   (if r =( 0 : int)
+  then NONE
+  else SOME (op l r)))`;
+
+
+(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*)
+val _ = Define `
+ ((arith_op_bv_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l r=
+   (OPTION_BIND (int_of_bv 
+  dict_Sail2_values_Bitvector_a sign l) (\ l' . 
+  OPTION_BIND (int_of_bv 
+  dict_Sail2_values_Bitvector_a sign r) (\ r' . 
+  if r' =( 0 : int) then NONE else SOME (
+  dict_Sail2_values_Bitvector_b.of_int_method (dict_Sail2_values_Bitvector_a.length_method l * size1) (op l' r'))))))`;
+
+
+val _ = Define `
+ ((mod_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b=  (arith_op_bv_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod F(( 1 : int))))`;
+
+val _ = Define `
+ ((quot_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b=  (arith_op_bv_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot F(( 1 : int))))`;
+
+val _ = Define `
+ ((quots_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b=  (arith_op_bv_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot T(( 1 : int))))`;
+
+
+val _ = Define `
+ ((mod_mword:'a words$word -> 'a words$word -> 'a words$word)=  words$word_mod)`;
+
+val _ = Define `
+ ((quot_mword:'a words$word -> 'a words$word -> 'a words$word)=  words$word_div)`;
+
+val _ = Define `
+ ((quots_mword:'a words$word -> 'a words$word -> 'a words$word)=  words$word_quot)`;
+
+
+val _ = Define `
+ ((arith_op_bv_int_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l r=
+   (arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method l) r)))`;
+
+
+val _ = Define `
+ ((quot_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b=  (arith_op_bv_int_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot F(( 1 : int))))`;
+
+val _ = Define `
+ ((mod_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b=  (arith_op_bv_int_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod F(( 1 : int))))`;
+
+
+val _ = Define `
+ ((mod_mword_int:'a words$word -> int -> 'a words$word) l r=  (words$word_mod l (integer_word$i2w r)))`;
+
+val _ = Define `
+ ((quot_mword_int:'a words$word -> int -> 'a words$word) l r=  (words$word_div l (integer_word$i2w r)))`;
+
+val _ = Define `
+ ((quots_mword_int:'a words$word -> int -> 'a words$word) l r=  (words$word_quot l (integer_word$i2w r)))`;
+
+
+val _ = Define `
+ ((replicate_bits_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v count1=  (repeat (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) count1))`;
+
+val _ = Define `
+ ((duplicate_bit_bv:'a BitU_class -> 'a -> int ->(bitU)list)dict_Sail2_values_BitU_a bit len=  (replicate_bits_bv 
+  (instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a) [bit] len))`;
+
+
+(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+val _ = Define `
+ ((eq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail2_values_Bitvector_a l r=  (
+  dict_Sail2_values_Bitvector_a.bits_of_method l = dict_Sail2_values_Bitvector_a.bits_of_method r))`;
+
+
+(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+val _ = Define `
+ ((neq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail2_values_Bitvector_a l r=  (~ (eq_bv 
+  dict_Sail2_values_Bitvector_a l r)))`;
+
+
+(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
+val _ = Define `
+ ((get_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo=
+   (let hi = ((lo + len) -( 1 : int)) in
+  let bs = (bools_of_int (hi +( 1 : int)) n) in  
+  dict_Sail2_values_Bitvector_a.of_bools_method (subrange_list F bs hi lo)))`;
+
+
+(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*)
+val _ = Define `
+ ((set_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a -> int)dict_Sail2_values_Bitvector_a len n lo v=
+   (let hi = ((lo + len) -( 1 : int)) in
+  let bs = (bits_of_int (hi +( 1 : int)) n) in
+  maybe_failwith (signed_of_bits (update_subrange_list F bs hi lo (
+  dict_Sail2_values_Bitvector_a.bits_of_method v)))))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
new file mode 100644
index 00000000..e6b4da4f
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
@@ -0,0 +1,769 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_operators_bitlists.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory sail2_operatorsTheory sail2_prompt_monadTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_operators_bitlists"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+(* Specialisation of operators to bit lists *)
+
+(*val uint_maybe : list bitU -> maybe integer*)
+val _ = Define `
+ ((uint_maybe0:(bitU)list ->(int)option) v=  (unsigned_of_bits (MAP (\ b. b) v)))`;
+
+val _ = Define `
+ ((uint_fail0:'a Bitvector_class -> 'a -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a v=  (sail2_state_monad$maybe_failS "uint" (
+  dict_Sail2_values_Bitvector_a.unsigned_method v)))`;
+
+val _ = Define `
+ ((uint_nondet0:(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$bindS
+  (sail2_state$bools_of_bits_nondetS v) (\ bs . 
+  sail2_state_monad$returnS (int_of_bools F bs))))`;
+
+val _ = Define `
+ ((uint:(bitU)list -> int) v=  (maybe_failwith (uint_maybe0 v)))`;
+
+
+(*val sint_maybe : list bitU -> maybe integer*)
+val _ = Define `
+ ((sint_maybe0:(bitU)list ->(int)option) v=  (signed_of_bits (MAP (\ b. b) v)))`;
+
+val _ = Define `
+ ((sint_fail0:'a Bitvector_class -> 'a -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a v=  (sail2_state_monad$maybe_failS "sint" (
+  dict_Sail2_values_Bitvector_a.signed_method v)))`;
+
+val _ = Define `
+ ((sint_nondet0:(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$bindS
+  (sail2_state$bools_of_bits_nondetS v) (\ bs . 
+  sail2_state_monad$returnS (int_of_bools T bs))))`;
+
+val _ = Define `
+ ((sint:(bitU)list -> int) v=  (maybe_failwith (sint_maybe0 v)))`;
+
+
+(*val extz_vec : integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((extz_vec0:int ->(bitU)list ->(bitU)list)= 
+  (extz_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val exts_vec : integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((exts_vec0:int ->(bitU)list ->(bitU)list)= 
+  (exts_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val zero_extend : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((zero_extend0:(bitU)list -> int ->(bitU)list) bits len=  (extz_bits len bits))`;
+
+
+(*val sign_extend : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((sign_extend0:(bitU)list -> int ->(bitU)list) bits len=  (exts_bits len bits))`;
+
+
+(*val zeros : integer -> list bitU*)
+val _ = Define `
+ ((zeros0:int ->(bitU)list) len=  (repeat [B0] len))`;
+
+
+(*val vector_truncate : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((vector_truncate0:(bitU)list -> int ->(bitU)list) bs len=  (extz_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) len bs))`;
+
+
+(*val vec_of_bits_maybe    : list bitU -> maybe (list bitU)*)
+(*val vec_of_bits_fail     : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
+(*val vec_of_bits_nondet   : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
+(*val vec_of_bits_failwith : list bitU -> list bitU*)
+(*val vec_of_bits          : list bitU -> list bitU*)
+
+(*val access_vec_inc : list bitU -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_inc0:(bitU)list -> int -> bitU)= 
+  (access_bv_inc
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val access_vec_dec : list bitU -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_dec0:(bitU)list -> int -> bitU)= 
+  (access_bv_dec
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*)
+val _ = Define `
+ ((update_vec_inc0:(bitU)list -> int -> bitU ->(bitU)list)= 
+  (update_bv_inc
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((update_vec_inc_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b=  (SOME (update_vec_inc0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_inc_fail0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b=  (sail2_state_monad$returnS (update_vec_inc0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_inc_nondet0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b=  (sail2_state_monad$returnS (update_vec_inc0 v i b)))`;
+
+
+(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*)
+val _ = Define `
+ ((update_vec_dec0:(bitU)list -> int -> bitU ->(bitU)list)= 
+  (update_bv_dec
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((update_vec_dec_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b=  (SOME (update_vec_dec0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_dec_fail0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b=  (sail2_state_monad$returnS (update_vec_dec0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_dec_nondet0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b=  (sail2_state_monad$returnS (update_vec_dec0 v i b)))`;
+
+
+(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list)= 
+  (subrange_bv_inc
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list)= 
+  (subrange_bv_dec
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((update_subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= 
+  (update_subrange_bv_inc
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((update_subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= 
+  (update_subrange_bv_dec
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val concat_vec : list bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((concat_vec0:(bitU)list ->(bitU)list ->(bitU)list)= 
+  (concat_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val cons_vec : bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((cons_vec0:bitU ->(bitU)list ->(bitU)list)= 
+  (cons_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((cons_vec_maybe0:bitU ->(bitU)list ->((bitU)list)option) b v=  (SOME (cons_vec0 b v)))`;
+
+val _ = Define `
+ ((cons_vec_fail0:bitU ->(bitU)list -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b v=  (sail2_state_monad$returnS (cons_vec0 b v)))`;
+
+val _ = Define `
+ ((cons_vec_nondet0:bitU ->(bitU)list -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b v=  (sail2_state_monad$returnS (cons_vec0 b v)))`;
+
+
+(*val cast_unit_vec : bitU -> list bitU*)
+val _ = Define `
+ ((cast_unit_vec0:bitU ->(bitU)list)=  cast_unit_bv)`;
+
+val _ = Define `
+ ((cast_unit_vec_maybe0:bitU ->((bitU)list)option) b=  (SOME (cast_unit_vec0 b)))`;
+
+val _ = Define `
+ ((cast_unit_vec_fail0:bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b=  (sail2_state_monad$returnS (cast_unit_vec0 b)))`;
+
+val _ = Define `
+ ((cast_unit_vec_nondet0:bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b=  (sail2_state_monad$returnS (cast_unit_vec0 b)))`;
+
+
+(*val vec_of_bit : integer -> bitU -> list bitU*)
+val _ = Define `
+ ((vec_of_bit0:int -> bitU ->(bitU)list)=  bv_of_bit)`;
+
+val _ = Define `
+ ((vec_of_bit_maybe0:int -> bitU ->((bitU)list)option) len b=  (SOME (vec_of_bit0 len b)))`;
+
+val _ = Define `
+ ((vec_of_bit_fail0:int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) len b=  (sail2_state_monad$returnS (vec_of_bit0 len b)))`;
+
+val _ = Define `
+ ((vec_of_bit_nondet0:int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) len b=  (sail2_state_monad$returnS (vec_of_bit0 len b)))`;
+
+
+(*val msb : list bitU -> bitU*)
+val _ = Define `
+ ((msb0:(bitU)list -> bitU)= 
+  (most_significant
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*)
+val _ = Define `
+ ((int_of_vec_maybe0:bool ->(bitU)list ->(int)option)= 
+  (int_of_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((int_of_vec_fail0:bool ->(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) sign v=  (sail2_state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`;
+
+val _ = Define `
+ ((int_of_vec_nondet:bool ->(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) sign v=  (sail2_state_monad$bindS (sail2_state$bools_of_bits_nondetS v) (\ v .  sail2_state_monad$returnS (int_of_bools sign v))))`;
+
+val _ = Define `
+ ((int_of_vec0:bool ->(bitU)list -> int) sign v=  (maybe_failwith (int_of_vec_maybe0 sign v)))`;
+
+
+(*val string_of_bits : list bitU -> string*)
+val _ = Define `
+ ((string_of_bits0:(bitU)list -> string)= 
+  (string_of_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val and_vec : list bitU -> list bitU -> list bitU*)
+(*val or_vec  : list bitU -> list bitU -> list bitU*)
+(*val xor_vec : list bitU -> list bitU -> list bitU*)
+(*val not_vec : list bitU -> list bitU*)
+val _ = Define `
+ ((and_vec0:(bitU)list ->(bitU)list ->(bitU)list)=  (binop_list and_bit))`;
+
+val _ = Define `
+ ((or_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (binop_list or_bit))`;
+
+val _ = Define `
+ ((xor_vec0:(bitU)list ->(bitU)list ->(bitU)list)=  (binop_list xor_bit))`;
+
+val _ = Define `
+ ((not_vec0:(bitU)list ->(bitU)list)=  (MAP not_bit))`;
+
+
+(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*)
+val _ = Define `
+ ((arith_op_double_bl:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a op sign l r=
+   (let len =(( 2 : int) * 
+  dict_Sail2_values_Bitvector_a.length_method l) in
+  let l' = (if sign then exts_bv 
+  dict_Sail2_values_Bitvector_a len l else extz_bv dict_Sail2_values_Bitvector_a len l) in
+  let r' = (if sign then exts_bv 
+  dict_Sail2_values_Bitvector_a len r else extz_bv dict_Sail2_values_Bitvector_a len r) in
+  MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`;
+
+
+(*val add_vec   : list bitU -> list bitU -> list bitU*)
+(*val adds_vec  : list bitU -> list bitU -> list bitU*)
+(*val sub_vec   : list bitU -> list bitU -> list bitU*)
+(*val subs_vec  : list bitU -> list bitU -> list bitU*)
+(*val mult_vec  : list bitU -> list bitU -> list bitU*)
+(*val mults_vec : list bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((add_vec0:(bitU)list ->(bitU)list ->(bitU)list)=    (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((adds_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((sub_vec0:(bitU)list ->(bitU)list ->(bitU)list)=    (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((subs_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((mult_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F))`;
+
+val _ = Define `
+ ((mults_vec0:(bitU)list ->(bitU)list ->(bitU)list)=  (arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T))`;
+
+
+(*val add_vec_int       : list bitU -> integer -> list bitU*)
+(*val adds_vec_int      : list bitU -> integer -> list bitU*)
+(*val sub_vec_int       : list bitU -> integer -> list bitU*)
+(*val subs_vec_int      : list bitU -> integer -> list bitU*)
+(*val mult_vec_int      : list bitU -> integer -> list bitU*)
+(*val mults_vec_int     : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((add_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
+
+val _ = Define `
+ ((adds_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`;
+
+val _ = Define `
+ ((sub_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
+
+val _ = Define `
+ ((subs_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`;
+
+val _ = Define `
+ ((mult_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
+
+val _ = Define `
+ ((mults_vec_int0:(bitU)list -> int ->(bitU)list) l r=  (arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
+
+
+(*val add_int_vec       : integer -> list bitU -> list bitU*)
+(*val adds_int_vec      : integer -> list bitU -> list bitU*)
+(*val sub_int_vec       : integer -> list bitU -> list bitU*)
+(*val subs_int_vec      : integer -> list bitU -> list bitU*)
+(*val mult_int_vec      : integer -> list bitU -> list bitU*)
+(*val mults_int_vec     : integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((add_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
+
+val _ = Define `
+ ((adds_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`;
+
+val _ = Define `
+ ((sub_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
+
+val _ = Define `
+ ((subs_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`;
+
+val _ = Define `
+ ((mult_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
+
+val _ = Define `
+ ((mults_int_vec0:int ->(bitU)list ->(bitU)list) l r=  (arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
+
+
+(*val add_vec_bit      : list bitU -> bitU -> list bitU*)
+(*val adds_vec_bit     : list bitU -> bitU -> list bitU*)
+(*val sub_vec_bit      : list bitU -> bitU -> list bitU*)
+(*val subs_vec_bit     : list bitU -> bitU -> list bitU*)
+
+val _ = Define `
+ ((add_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a       l r=  (arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (+) F l r))`;
+
+val _ = Define `
+ ((add_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a  l r=  (arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (+) F l r))`;
+
+val _ = Define `
+ ((add_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a   l r=  (sail2_state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 
+  dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((add_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (add_vec_bool0 
+  dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((add_vec_bit0:(bitU)list -> bitU ->(bitU)list)        l r=  (option_CASE (add_vec_bit_maybe0 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+val _ = Define `
+ ((adds_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a       l r=  (arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (+) T l r))`;
+
+val _ = Define `
+ ((adds_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a  l r=  (arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (+) T l r))`;
+
+val _ = Define `
+ ((adds_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a   l r=  (sail2_state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 
+  dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((adds_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (adds_vec_bool0 
+  dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((adds_vec_bit0:(bitU)list -> bitU ->(bitU)list)        l r=  (option_CASE (adds_vec_bit_maybe0 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+val _ = Define `
+ ((sub_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a        l r=  (arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (-) F l r))`;
+
+val _ = Define `
+ ((sub_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a   l r=  (arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (-) F l r))`;
+
+val _ = Define `
+ ((sub_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a    l r=  (sail2_state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 
+  dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((sub_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a  l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (sub_vec_bool0 
+  dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((sub_vec_bit0:(bitU)list -> bitU ->(bitU)list)         l r=  (option_CASE (sub_vec_bit_maybe0 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+val _ = Define `
+ ((subs_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a       l r=  (arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (-) T l r))`;
+
+val _ = Define `
+ ((subs_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a  l r=  (arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (-) T l r))`;
+
+val _ = Define `
+ ((subs_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a   l r=  (sail2_state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 
+  dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((subs_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (subs_vec_bool0 
+  dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((subs_vec_bit0:(bitU)list -> bitU ->(bitU)list)        l r=  (option_CASE (subs_vec_bit_maybe0 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+(*val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec        : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec         = add_overflow_bv
+let add_overflow_vec_signed  = add_overflow_bv_signed
+let sub_overflow_vec         = sub_overflow_bv
+let sub_overflow_vec_signed  = sub_overflow_bv_signed
+let mult_overflow_vec        = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit         = add_overflow_bv_bit
+let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit         = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
+
+(*val shiftl       : list bitU -> integer -> list bitU*)
+(*val shiftr       : list bitU -> integer -> list bitU*)
+(*val arith_shiftr : list bitU -> integer -> list bitU*)
+(*val rotl         : list bitU -> integer -> list bitU*)
+(*val rotr         : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((shiftl0:(bitU)list -> int ->(bitU)list)= 
+  (shiftl_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((shiftr0:(bitU)list -> int ->(bitU)list)= 
+  (shiftr_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((arith_shiftr0:(bitU)list -> int ->(bitU)list)= 
+  (arith_shiftr_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((rotl0:(bitU)list -> int ->(bitU)list)= 
+  (rotl_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((rotr0:(bitU)list -> int ->(bitU)list)= 
+  (rotr_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val mod_vec        : list bitU -> list bitU -> list bitU*)
+(*val mod_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
+(*val mod_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((mod_vec0:(bitU)list ->(bitU)list ->(bitU)list)        l r=  (option_CASE (mod_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((mod_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option)  l r=  (mod_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((mod_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "mod_vec" (mod_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((mod_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=  (sail2_state$of_bits_nondetS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec0 l r)))`;
+
+
+(*val quot_vec        : list bitU -> list bitU -> list bitU*)
+(*val quot_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
+(*val quot_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((quot_vec0:(bitU)list ->(bitU)list ->(bitU)list)        l r=  (option_CASE (quot_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((quot_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option)  l r=  (quot_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((quot_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "quot_vec" (quot_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((quot_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=  (sail2_state$of_bits_nondetS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec0 l r)))`;
+
+
+(*val quots_vec        : list bitU -> list bitU -> list bitU*)
+(*val quots_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
+(*val quots_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((quots_vec0:(bitU)list ->(bitU)list ->(bitU)list)        l r=  (option_CASE (quots_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((quots_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option)  l r=  (quots_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((quots_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "quots_vec" (quots_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((quots_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=  (sail2_state$of_bits_nondetS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quots_vec0 l r)))`;
+
+
+(*val mod_vec_int        : list bitU -> integer -> list bitU*)
+(*val mod_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
+(*val mod_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+(*val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((mod_vec_int0:(bitU)list -> int ->(bitU)list)        l r=  (option_CASE (mod_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((mod_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option)  l r=  (mod_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((mod_vec_int_fail0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "mod_vec_int" (mod_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((mod_vec_int_nondet0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=  (sail2_state$of_bits_nondetS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec_int0 l r)))`;
+
+
+(*val quot_vec_int        : list bitU -> integer -> list bitU*)
+(*val quot_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
+(*val quot_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+(*val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((quot_vec_int0:(bitU)list -> int ->(bitU)list)        l r=  (option_CASE (quot_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((quot_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option)  l r=  (quot_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((quot_vec_int_fail0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "quot_vec_int" (quot_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((quot_vec_int_nondet0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=  (sail2_state$of_bits_nondetS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec_int0 l r)))`;
+
+
+(*val replicate_bits : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((replicate_bits0:(bitU)list -> int ->(bitU)list)= 
+  (replicate_bits_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val duplicate : bitU -> integer -> list bitU*)
+val _ = Define `
+ ((duplicate0:bitU -> int ->(bitU)list)= 
+  (duplicate_bit_bv instance_Sail2_values_BitU_Sail2_values_bitU_dict))`;
+
+val _ = Define `
+ ((duplicate_maybe0:bitU -> int ->((bitU)list)option) b n=  (SOME (duplicate0 b n)))`;
+
+val _ = Define `
+ ((duplicate_fail0:bitU -> int -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b n=  (sail2_state_monad$returnS (duplicate0 b n)))`;
+
+val _ = Define `
+ ((duplicate_nondet0:bitU -> int -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b n=  (sail2_state_monad$bindS
+  (sail2_state$bool_of_bitU_nondetS b) (\ b . 
+  sail2_state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`;
+
+
+(*val reverse_endianness : list bitU -> list bitU*)
+val _ = Define `
+ ((reverse_endianness0:(bitU)list ->(bitU)list) v=  (reverse_endianness_list v))`;
+
+
+(*val get_slice_int : integer -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((get_slice_int0:int -> int -> int ->(bitU)list)= 
+  (get_slice_int_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*)
+val _ = Define `
+ ((set_slice_int0:int -> int -> int ->(bitU)list -> int)= 
+  (set_slice_int_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val slice : list bitU -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((slice0:(bitU)list -> int -> int ->(bitU)list) v lo len=
+   (subrange_vec_dec0 v ((lo + len) -( 1 : int)) lo))`;
+
+
+(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((set_slice0:int -> int ->(bitU)list -> int ->(bitU)list ->(bitU)list) (out_len:ii) (slice_len:ii) out (n:ii) v=
+   (update_subrange_vec_dec0 out ((n + slice_len) -( 1 : int)) n v))`;
+
+
+(*val eq_vec    : list bitU -> list bitU -> bool*)
+(*val neq_vec   : list bitU -> list bitU -> bool*)
+val _ = Define `
+ ((eq_vec:(bitU)list ->(bitU)list -> bool)= 
+  (eq_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((neq_vec:(bitU)list ->(bitU)list -> bool)= 
+  (neq_bv
+     (instance_Sail2_values_Bitvector_list_dict
+        instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
new file mode 100644
index 00000000..603daf57
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
@@ -0,0 +1,635 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_operators_mwords.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory sail2_operatorsTheory sail2_prompt_monadTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_operators_mwords"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+val _ = Define `
+ ((uint_maybe:'a words$word ->(int)option) v=  (SOME (lem$w2ui v)))`;
+
+val _ = Define `
+ ((uint_fail:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$returnS (lem$w2ui v)))`;
+
+val _ = Define `
+ ((uint_nondet:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$returnS (lem$w2ui v)))`;
+
+val _ = Define `
+ ((sint_maybe:'a words$word ->(int)option) v=  (SOME (integer_word$w2i v)))`;
+
+val _ = Define `
+ ((sint_fail:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$returnS (integer_word$w2i v)))`;
+
+val _ = Define `
+ ((sint_nondet:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$returnS (integer_word$w2i v)))`;
+
+
+(*val vec_of_bits_maybe    : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*)
+(*val vec_of_bits_fail     : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
+(*val vec_of_bits_nondet   : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
+(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*)
+(*val vec_of_bits          : forall 'a. Size 'a => list bitU -> mword 'a*)
+val _ = Define `
+ ((vec_of_bits_maybe:(bitU)list ->('a words$word)option) bits=  (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`;
+
+val _ = Define `
+ ((vec_of_bits_fail:(bitU)list -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) bits=  (sail2_state$of_bits_failS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+val _ = Define `
+ ((vec_of_bits_nondet:(bitU)list -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) bits=  (sail2_state$of_bits_nondetS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+val _ = Define `
+ ((vec_of_bits_failwith:(bitU)list -> 'a words$word) bits=  (of_bits_failwith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+val _ = Define `
+ ((vec_of_bits:(bitU)list -> 'a words$word) bits=  (of_bits_failwith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+
+(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_inc:'a words$word -> int -> bitU)= 
+  (access_bv_inc instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_dec:'a words$word -> int -> bitU)= 
+  (access_bv_dec instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+val _ = Define `
+ ((update_vec_dec_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b=  (update_mword_dec w i b))`;
+
+val _ = Define `
+ ((update_vec_dec_fail:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b=  (sail2_state_monad$bindS
+  (sail2_state$bool_of_bitU_fail b) (\ b . 
+  sail2_state_monad$returnS (update_mword_bool_dec w i b))))`;
+
+val _ = Define `
+ ((update_vec_dec_nondet:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b=  (sail2_state_monad$bindS
+  (sail2_state$bool_of_bitU_nondetS b) (\ b . 
+  sail2_state_monad$returnS (update_mword_bool_dec w i b))))`;
+
+val _ = Define `
+ ((update_vec_dec:'a words$word -> int -> bitU -> 'a words$word) w i b=  (maybe_failwith (update_vec_dec_maybe w i b)))`;
+
+
+val _ = Define `
+ ((update_vec_inc_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b=  (update_mword_inc w i b))`;
+
+val _ = Define `
+ ((update_vec_inc_fail:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b=  (sail2_state_monad$bindS
+  (sail2_state$bool_of_bitU_fail b) (\ b . 
+  sail2_state_monad$returnS (update_mword_bool_inc w i b))))`;
+
+val _ = Define `
+ ((update_vec_inc_nondet:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b=  (sail2_state_monad$bindS
+  (sail2_state$bool_of_bitU_nondetS b) (\ b . 
+  sail2_state_monad$returnS (update_mword_bool_inc w i b))))`;
+
+val _ = Define `
+ ((update_vec_inc:'a words$word -> int -> bitU -> 'a words$word) w i b=  (maybe_failwith (update_vec_inc_maybe w i b)))`;
+
+
+(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((subrange_vec_dec:'a words$word -> int -> int -> 'b words$word) w i j=  (words$word_extract (nat_of_int i) (nat_of_int j) w))`;
+
+
+(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((subrange_vec_inc:'a words$word -> int -> int -> 'b words$word) w i j=  (subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j)))`;
+
+
+(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_subrange_vec_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=  (words$bit_field_insert (nat_of_int i) (nat_of_int j) w' w))`;
+
+
+(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_subrange_vec_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=  (update_subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j) w'))`;
+
+
+(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((extz_vec:int -> 'a words$word -> 'b words$word) _ w=  (words$w2w w))`;
+
+
+(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((exts_vec:int -> 'a words$word -> 'b words$word) _ w=  (words$sw2sw w))`;
+
+
+(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((zero_extend:'a words$word -> int -> 'b words$word) w _=  (words$w2w w))`;
+
+
+(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((sign_extend:'a words$word -> int -> 'b words$word) w _=  (words$sw2sw w))`;
+
+
+(*val zeros : forall 'a. Size 'a => integer -> mword 'a*)
+val _ = Define `
+ ((zeros:int -> 'a words$word) _=  (words$n2w(( 0:num))))`;
+
+
+(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((vector_truncate:'a words$word -> int -> 'b words$word) w _=  (words$w2w w))`;
+
+
+(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
+val _ = Define `
+ ((concat_vec:'a words$word -> 'b words$word -> 'c words$word)=  words$word_concat)`;
+
+
+(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((cons_vec_bool:bool -> 'a words$word -> 'b words$word) b w=  (bitstring$v2w (b :: bitstring$w2v w)))`;
+
+val _ = Define `
+ ((cons_vec_maybe:bitU -> 'c words$word ->('b words$word)option) b w=  (OPTION_MAP (\ b .  cons_vec_bool b w) (bool_of_bitU b)))`;
+
+val _ = Define `
+ ((cons_vec_fail:bitU -> 'c words$word -> 'd sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set) b w=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b .  sail2_state_monad$returnS (cons_vec_bool b w))))`;
+
+val _ = Define `
+ ((cons_vec_nondet:bitU -> 'c words$word -> 'd sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set) b w=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b .  sail2_state_monad$returnS (cons_vec_bool b w))))`;
+
+val _ = Define `
+ ((cons_vec:bitU -> 'a words$word -> 'b words$word) b w=  (maybe_failwith (cons_vec_maybe b w)))`;
+
+
+(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*)
+val _ = Define `
+ ((vec_of_bool:int -> bool -> 'a words$word) _ b=  (bitstring$v2w [b]))`;
+
+val _ = Define `
+ ((vec_of_bit_maybe:int -> bitU ->('a words$word)option) len b=  (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`;
+
+val _ = Define `
+ ((vec_of_bit_fail:int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) len b=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b .  sail2_state_monad$returnS (vec_of_bool len b))))`;
+
+val _ = Define `
+ ((vec_of_bit_nondet:int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) len b=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b .  sail2_state_monad$returnS (vec_of_bool len b))))`;
+
+val _ = Define `
+ ((vec_of_bit:int -> bitU -> 'a words$word) len b=  (maybe_failwith (vec_of_bit_maybe len b)))`;
+
+
+(*val cast_bool_vec : bool -> mword ty1*)
+val _ = Define `
+ ((cast_bool_vec:bool ->(1)words$word) b=  (vec_of_bool(( 1 : int)) b))`;
+
+val _ = Define `
+ ((cast_unit_vec_maybe:bitU ->('a words$word)option) b=  (vec_of_bit_maybe(( 1 : int)) b))`;
+
+val _ = Define `
+ ((cast_unit_vec_fail:bitU -> 'a sail2_state_monad$sequential_state ->((((1)words$word),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b .  sail2_state_monad$returnS (cast_bool_vec b))))`;
+
+val _ = Define `
+ ((cast_unit_vec_nondet:bitU -> 'a sail2_state_monad$sequential_state ->((((1)words$word),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b .  sail2_state_monad$returnS (cast_bool_vec b))))`;
+
+val _ = Define `
+ ((cast_unit_vec:bitU -> 'a words$word) b=  (maybe_failwith (cast_unit_vec_maybe b)))`;
+
+
+(*val msb : forall 'a. Size 'a => mword 'a -> bitU*)
+val _ = Define `
+ ((msb:'a words$word -> bitU)= 
+  (most_significant instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*)
+val _ = Define `
+ ((int_of_vec:bool -> 'a words$word -> int) sign w=
+   (if sign
+  then integer_word$w2i w
+  else lem$w2ui w))`;
+
+val _ = Define `
+ ((int_of_vec_maybe:bool -> 'a words$word ->(int)option) sign w=  (SOME (int_of_vec sign w)))`;
+
+val _ = Define `
+ ((int_of_vec_fail:bool -> 'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) sign w=  (sail2_state_monad$returnS (int_of_vec sign w)))`;
+
+
+(*val string_of_bits : forall 'a. Size 'a => mword 'a -> string*)
+val _ = Define `
+ ((string_of_bits:'a words$word -> string)= 
+  (string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val or_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
+val _ = Define `
+ ((and_vec:'a words$word -> 'a words$word -> 'a words$word)=  words$word_and)`;
+
+val _ = Define `
+ ((or_vec:'a words$word -> 'a words$word -> 'a words$word)=   words$word_or)`;
+
+val _ = Define `
+ ((xor_vec:'a words$word -> 'a words$word -> 'a words$word)=  words$word_xor)`;
+
+val _ = Define `
+ ((not_vec:'a words$word -> 'a words$word)=  words$word_1comp)`;
+
+
+(*val add_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val adds_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val sub_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val subs_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val mult_vec  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((add_vec:'a words$word -> 'a words$word -> 'a words$word)   l r=  (integer_word$i2w ((int_of_mword F l) + (int_of_mword F r))))`;
+
+val _ = Define `
+ ((adds_vec:'a words$word -> 'a words$word -> 'a words$word)  l r=  (integer_word$i2w ((int_of_mword T l) + (int_of_mword T r))))`;
+
+val _ = Define `
+ ((sub_vec:'a words$word -> 'a words$word -> 'a words$word)   l r=  (integer_word$i2w ((int_of_mword F l) - (int_of_mword F r))))`;
+
+val _ = Define `
+ ((subs_vec:'a words$word -> 'a words$word -> 'a words$word)  l r=  (integer_word$i2w ((int_of_mword T l) - (int_of_mword T r))))`;
+
+val _ = Define `
+ ((mult_vec:'a words$word -> 'a words$word -> 'b words$word)  l r=  (integer_word$i2w ((int_of_mword F (words$w2w l :  'b words$word)) * (int_of_mword F (words$w2w r :  'b words$word)))))`;
+
+val _ = Define `
+ ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r=  (integer_word$i2w ((int_of_mword T (words$sw2sw l :  'b words$word)) * (int_of_mword T (words$sw2sw r :  'b words$word)))))`;
+
+
+(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val adds_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val subs_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((add_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
+
+val _ = Define `
+ ((adds_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
+
+val _ = Define `
+ ((sub_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
+
+val _ = Define `
+ ((subs_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
+
+val _ = Define `
+ ((mult_vec_int:'a words$word -> int -> 'b words$word)  l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  F (words$w2w l :  'b words$word) r))`;
+
+val _ = Define `
+ ((mults_vec_int:'a words$word -> int -> 'b words$word) l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  T  (words$sw2sw l :  'b words$word) r))`;
+
+
+(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val adds_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val subs_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((add_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
+
+val _ = Define `
+ ((adds_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
+
+val _ = Define `
+ ((sub_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
+
+val _ = Define `
+ ((subs_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
+
+val _ = Define `
+ ((mult_int_vec:int -> 'a words$word -> 'b words$word)  l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  F l (words$w2w r :  'b words$word)))`;
+
+val _ = Define `
+ ((mults_int_vec:int -> 'a words$word -> 'b words$word) l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  T  l (words$sw2sw r :  'b words$word)))`;
+
+
+(*val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val sub_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+
+val _ = Define `
+ ((add_vec_bool:'a words$word -> bool -> 'a words$word)        l r=  (arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`;
+
+val _ = Define `
+ ((add_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)   l r=  (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((add_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)    l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r .  sail2_state_monad$returnS (add_vec_bool l r))))`;
+
+val _ = Define `
+ ((add_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)  l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (add_vec_bool l r))))`;
+
+val _ = Define `
+ ((add_vec_bit:'a words$word -> bitU -> 'a words$word)         l r=  (maybe_failwith (add_vec_bit_maybe  l r)))`;
+
+
+val _ = Define `
+ ((adds_vec_bool:'a words$word -> bool -> 'a words$word)       l r=  (arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) T  l r))`;
+
+val _ = Define `
+ ((adds_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)  l r=  (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((adds_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r .  sail2_state_monad$returnS (adds_vec_bool l r))))`;
+
+val _ = Define `
+ ((adds_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (adds_vec_bool l r))))`;
+
+val _ = Define `
+ ((adds_vec_bit:'a words$word -> bitU -> 'a words$word)        l r=  (maybe_failwith (adds_vec_bit_maybe l r)))`;
+
+
+val _ = Define `
+ ((sub_vec_bool:'a words$word -> bool -> 'a words$word)        l r=  (arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
+
+val _ = Define `
+ ((sub_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)   l r=  (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((sub_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)    l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r .  sail2_state_monad$returnS (sub_vec_bool l r))))`;
+
+val _ = Define `
+ ((sub_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)  l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (sub_vec_bool l r))))`;
+
+val _ = Define `
+ ((sub_vec_bit:'a words$word -> bitU -> 'a words$word)         l r=  (maybe_failwith (sub_vec_bit_maybe  l r)))`;
+
+
+val _ = Define `
+ ((subs_vec_bool:'a words$word -> bool -> 'a words$word)       l r=  (arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
+
+val _ = Define `
+ ((subs_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)  l r=  (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((subs_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r .  sail2_state_monad$returnS (subs_vec_bool l r))))`;
+
+val _ = Define `
+ ((subs_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r .  sail2_state_monad$returnS (subs_vec_bool l r))))`;
+
+val _ = Define `
+ ((subs_vec_bit:'a words$word -> bitU -> 'a words$word)        l r=  (maybe_failwith (subs_vec_bit_maybe  l r)))`;
+
+
+(* TODO
+val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU)
+let maybe_mword_of_bits_overflow (bits, overflow, carry) =
+  Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits)
+
+val add_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val adds_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val sub_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val subs_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mult_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+let add_overflow_vec   l r = maybe_mword_of_bits_overflow (add_overflow_bv l r)
+let adds_overflow_vec  l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r)
+let sub_overflow_vec   l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r)
+let subs_overflow_vec  l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r)
+let mult_overflow_vec  l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r)
+let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r)
+
+val add_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+let add_overflow_vec_bit         = add_overflow_bv_bit
+let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit         = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
+
+(*val shiftl       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val shiftr       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val rotl         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val rotr         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+val _ = Define `
+ ((shiftl:'a words$word -> int -> 'a words$word)=        shiftl_mword)`;
+
+val _ = Define `
+ ((shiftr:'a words$word -> int -> 'a words$word)=        shiftr_mword)`;
+
+val _ = Define `
+ ((arith_shiftr:'a words$word -> int -> 'a words$word)=  arith_shiftr_mword)`;
+
+val _ = Define `
+ ((rotl:'a words$word -> int -> 'a words$word)=          rotl_mword)`;
+
+val _ = Define `
+ ((rotr:'a words$word -> int -> 'a words$word)=          rotr_mword)`;
+
+
+(*val mod_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val mod_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val mod_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((mod_vec:'a words$word -> 'a words$word -> 'a words$word)        l r=  (mod_mword l r))`;
+
+val _ = Define `
+ ((mod_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option)  l r=  (mod_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((mod_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "mod_vec" (mod_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((mod_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+   ((case (mod_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      SOME w => sail2_state_monad$returnS w
+    | NONE => sail2_state$mword_nondetS () 
+  )))`;
+
+
+(*val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val quot_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val quot_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((quot_vec:'a words$word -> 'a words$word -> 'a words$word)        l r=  (quot_mword l r))`;
+
+val _ = Define `
+ ((quot_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option)  l r=  (quot_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((quot_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "quot_vec" (quot_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((quot_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+   ((case (quot_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      SOME w => sail2_state_monad$returnS w
+    | NONE => sail2_state$mword_nondetS () 
+  )))`;
+
+
+(*val quots_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val quots_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val quots_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((quots_vec:'a words$word -> 'a words$word -> 'a words$word)        l r=  (quots_mword l r))`;
+
+val _ = Define `
+ ((quots_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option)  l r=  (quots_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((quots_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "quots_vec" (quots_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((quots_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+   ((case (quots_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      SOME w => sail2_state_monad$returnS w
+    | NONE => sail2_state$mword_nondetS () 
+  )))`;
+
+
+(*val mod_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mod_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
+(*val mod_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+(*val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((mod_vec_int:'a words$word -> int -> 'a words$word)        l r=  (mod_mword_int l r))`;
+
+val _ = Define `
+ ((mod_vec_int_maybe:'a words$word -> int ->('a words$word)option)  l r=  (mod_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((mod_vec_int_fail:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "mod_vec_int" (mod_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((mod_vec_int_nondet:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+   ((case (mod_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      SOME w => sail2_state_monad$returnS w
+    | NONE => sail2_state$mword_nondetS () 
+  )))`;
+
+
+(*val quot_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val quot_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
+(*val quot_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+(*val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((quot_vec_int:'a words$word -> int -> 'a words$word)        l r=  (quot_mword_int l r))`;
+
+val _ = Define `
+ ((quot_vec_int_maybe:'a words$word -> int ->('a words$word)option)  l r=  (quot_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((quot_vec_int_fail:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set)   l r=  (sail2_state_monad$maybe_failS "quot_vec_int" (quot_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((quot_vec_int_nondet:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+   ((case (quot_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      SOME w => sail2_state_monad$returnS w
+    | NONE => sail2_state$mword_nondetS () 
+  )))`;
+
+
+(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((replicate_bits:'a words$word -> int -> 'b words$word) v count1=  (bitstring$v2w (repeat (bitstring$w2v v) count1)))`;
+
+
+(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*)
+val _ = Define `
+ ((duplicate_bool:bool -> int -> 'a words$word)   b n=  (bitstring$v2w (repeat [b] n)))`;
+
+val _ = Define `
+ ((duplicate_maybe:bitU -> int ->('a words$word)option)  b n=  (OPTION_MAP (\ b .  duplicate_bool b n) (bool_of_bitU b)))`;
+
+val _ = Define `
+ ((duplicate_fail:bitU -> int -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   b n=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b .  sail2_state_monad$returnS (duplicate_bool b n))))`;
+
+val _ = Define `
+ ((duplicate_nondet:bitU -> int -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) b n=  (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b .  sail2_state_monad$returnS (duplicate_bool b n))))`;
+
+val _ = Define `
+ ((duplicate:bitU -> int -> 'a words$word)        b n=  (maybe_failwith (duplicate_maybe b n)))`;
+
+
+(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*)
+val _ = Define `
+ ((reverse_endianness:'a words$word -> 'a words$word) v=  (bitstring$v2w (reverse_endianness_list (bitstring$w2v v))))`;
+
+
+(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*)
+val _ = Define `
+ ((get_slice_int:int -> int -> int -> 'a words$word)= 
+  (get_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*)
+val _ = Define `
+ ((set_slice_int:int -> int -> int -> 'a words$word -> int)= 
+  (set_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice:'a words$word -> int -> int -> 'b words$word) v lo len=
+   (subrange_vec_dec v ((lo + len) -( 1 : int)) lo))`;
+
+
+(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((set_slice:int -> int -> 'a words$word -> int -> 'b words$word -> 'a words$word) (out_len:ii) (slice_len:ii) out (n:ii) v=
+   (update_subrange_vec_dec out ((n + slice_len) -( 1 : int)) n v))`;
+
+
+(*val eq_vec    : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+(*val neq_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_promptScript.sml b/snapshots/hol4/sail/lib/hol/sail2_promptScript.sml
new file mode 100644
index 00000000..629c9028
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_promptScript.sml
@@ -0,0 +1,15 @@
+(*Generated by Lem from sail2_prompt.lem.*)
+open HolKernel Parse boolLib bossLib;
+open sail2_prompt_monadTheory sail2_state_monadTheory sail2_stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_prompt"
+
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_state_monad*)
+(*open import Sail2_state*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_prompt_monadScript.sml b/snapshots/hol4/sail/lib/hol/sail2_prompt_monadScript.sml
new file mode 100644
index 00000000..c6d6bc44
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_prompt_monadScript.sml
@@ -0,0 +1,31 @@
+(*Generated by Lem from sail2_prompt_monad.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_instr_kindsTheory sail2_state_monadTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_prompt_monad"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_state_monad*)
+
+(* Fake interface of the prompt monad by redirecting to the state monad, since
+   the former is not currently supported by HOL4 *)
+
+val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e) *) "monad" , ``:('a_rv,'b_a,'c_e) monadS``);
+val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e, 'd_r) *) "monadR" , ``:('a_rv,'b_a,'c_e,'d_r) monadRS``);
+
+(* We need to use a target_rep for these because HOL doesn't handle unused
+   type parameters well. *)
+
+(*type base_monad 'regval 'regstate 'a 'e = monad 'regstate 'a 'e*)
+(*type base_monadR 'regval 'regstate 'a 'r 'e = monadR 'regstate 'a 'r 'e*)
+val _ = Define `
+ ((barrier:'c -> 'a sequential_state ->(((unit),'b)result#'a sequential_state)set) _=  (returnS () ))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_stateAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/sail2_stateAuxiliaryScript.sml
new file mode 100644
index 00000000..4d70b033
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_stateAuxiliaryScript.sml
@@ -0,0 +1,61 @@
+(*Generated by Lem from ../../src/gen_lib/state.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory sail2_stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "sail2_stateAuxiliary"
+
+
+(****************************************************)
+(*                                                  *)
+(* Termination Proofs                               *)
+(*                                                  *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (iterS_aux_def, iterS_aux_ind) *)
+val (iterS_aux_rw, iterS_aux_ind_rw) =
+  Defn.tprove_no_defn ((iterS_aux_def, iterS_aux_ind),
+    WF_REL_TAC`measure (LENGTH o SND o SND)` \\ rw[]
+  )
+val iterS_aux_rw = save_thm ("iterS_aux_rw", iterS_aux_rw);
+val iterS_aux_ind_rw = save_thm ("iterS_aux_ind_rw", iterS_aux_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (foreachS_def, foreachS_ind) *)
+val (foreachS_rw, foreachS_ind_rw) =
+  Defn.tprove_no_defn ((foreachS_def, foreachS_ind),
+    WF_REL_TAC`measure (LENGTH o FST)` \\ rw[]
+  )
+val foreachS_rw = save_thm ("foreachS_rw", foreachS_rw);
+val foreachS_ind_rw = save_thm ("foreachS_ind_rw", foreachS_ind_rw);
+
+
+(*
+These are unprovable.
+
+(* val gst = Defn.tgoal_no_defn (whileS_def, whileS_ind) *)
+val (whileS_rw, whileS_ind_rw) =
+  Defn.tprove_no_defn ((whileS_def, whileS_ind),
+    cheat (* the termination proof *)
+  )
+val whileS_rw = save_thm ("whileS_rw", whileS_rw);
+val whileS_ind_rw = save_thm ("whileS_ind_rw", whileS_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (untilS_def, untilS_ind) *)
+val (untilS_rw, untilS_ind_rw) =
+  Defn.tprove_no_defn ((untilS_def, untilS_ind),
+    cheat (* the termination proof *)
+  )
+val untilS_rw = save_thm ("untilS_rw", untilS_rw);
+val untilS_ind_rw = save_thm ("untilS_ind_rw", untilS_ind_rw);
+*)
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_stateScript.sml b/snapshots/hol4/sail/lib/hol/sail2_stateScript.sml
new file mode 100644
index 00000000..dfe0cd7d
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_stateScript.sml
@@ -0,0 +1,141 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_state.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_state"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_values*)
+(*open import Sail2_state_monad*)
+(*open import {isabelle} `Sail2_state_monad_lemmas`*)
+
+(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+ val iterS_aux_defn = Hol_defn "iterS_aux" `
+ ((iterS_aux:int ->(int -> 'a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) i f xs=  ((case xs of
+    x :: xs => seqS (f i x) (iterS_aux (i +( 1 : int)) f xs)
+  | [] => returnS () 
+  )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn iterS_aux_defn;
+
+(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+val _ = Define `
+ ((iteriS:(int -> 'a ->('rv,(unit),'e)monadS) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs=  (iterS_aux(( 0 : int)) f xs))`;
+
+
+(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+val _ = Define `
+ ((iterS:('a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs=  (iteriS (\i x .  
+  (case (i ,x ) of ( _ , x ) => f x )) xs))`;
+
+
+(*val foreachS : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+ val foreachS_defn = Hol_defn "foreachS" `
+ ((foreachS:'a list -> 'vars ->('a -> 'vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) xs vars body=  ((case xs of
+    [] => returnS vars
+  | x :: xs => bindS
+     (body x vars) (\ vars . 
+     foreachS xs vars body)
+)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreachS_defn;
+
+(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((and_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r=  (bindS l (\ l .  if l then r else returnS F)))`;
+
+
+(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((or_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r=  (bindS l (\ l .  if l then returnS T else r)))`;
+
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((bool_of_bitU_fail:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= 
+  (\x .  (case x of
+               B0 => returnS F
+           | B1 => returnS T
+           | BU => failS "bool_of_bitU"
+         )))`;
+
+
+(*val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((bool_of_bitU_nondetS:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= 
+  (\x .  (case x of
+               B0 => returnS F
+           | B1 => returnS T
+           | BU => undefined_boolS () 
+         )))`;
+
+
+(*val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*)
+val _ = Define `
+ ((bools_of_bits_nondetS:(bitU)list -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) bits=
+   (foreachS bits []
+    (\ b bools .  bindS
+      (bool_of_bitU_nondetS b) (\ b . 
+      returnS (bools ++ [b])))))`;
+
+
+(*val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+val _ = Define `
+ ((of_bits_nondetS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail2_values_Bitvector_a bits=  (bindS
+  (bools_of_bits_nondetS bits) (\ bs . 
+  returnS (dict_Sail2_values_Bitvector_a.of_bools_method bs))))`;
+
+
+(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+val _ = Define `
+ ((of_bits_failS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail2_values_Bitvector_a bits=  (maybe_failS "of_bits" (
+  dict_Sail2_values_Bitvector_a.of_bits_method bits)))`;
+
+
+(*val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((mword_nondetS:unit -> 'rv sequential_state ->((('a words$word),'e)result#'rv sequential_state)set) () =  (bindS
+  (bools_of_bits_nondetS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . 
+  returnS (bitstring$v2w bs))))`;
+
+
+
+(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+ val whileS_defn = Hol_defn "whileS" `
+ ((whileS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s=
+   (( bindS(cond vars) (\ cond_val s' . 
+  if cond_val then
+    ( bindS(body vars) (\ vars s'' .  whileS vars cond body s'')) s'
+  else returnS vars s')) s))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn whileS_defn;
+
+(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+ val untilS_defn = Hol_defn "untilS" `
+ ((untilS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s=
+   (( bindS(body vars) (\ vars s' . 
+  ( bindS(cond vars) (\ cond_val s'' . 
+  if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn untilS_defn;
+
+(*val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e*)
+val _ = Define `
+ ((internal_pickS:'a list -> 'rv sequential_state ->(('a,'e)result#'rv sequential_state)set) xs=  (bindS
+  (
+  (* Use sufficiently many undefined bits and convert into an index into the list *)bools_of_bits_nondetS (repeat [BU] (int_of_num (LENGTH xs)))) (\ bs . 
+  let idx = ((((nat_of_bools bs):num)) MOD LENGTH xs) in
+  (case list_index xs idx of
+      SOME x => returnS x
+    | NONE => failS "internal_pick"
+  ))))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_state_monadScript.sml b/snapshots/hol4/sail/lib/hol/sail2_state_monadScript.sml
new file mode 100644
index 00000000..c3e3603d
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_state_monadScript.sml
@@ -0,0 +1,359 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_state_monad.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_instr_kindsTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_state_monad"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+
+(* 'a is result type *)
+
+val _ = type_abbrev( "memstate" , ``: (int, memory_byte) fmap``);
+val _ = type_abbrev( "tagstate" , ``: (int, bitU) fmap``);
+(* type regstate = map string (vector bitU) *)
+
+val _ = Hol_datatype `
+(*  'regs *) sequential_state =
+  <| regstate : 'regs;
+     memstate : memstate;
+     tagstate : tagstate;
+     write_ea :  (write_kind # int # int)option;
+     last_exclusive_operation_was_load : bool |>`;
+
+
+(*val init_state : forall 'regs. 'regs -> sequential_state 'regs*)
+val _ = Define `
+ ((init_state:'regs -> 'regs sequential_state) regs=
+   (<| regstate := regs;
+     memstate := FEMPTY;
+     tagstate := FEMPTY;
+     write_ea := NONE;
+     last_exclusive_operation_was_load := F |>))`;
+
+
+val _ = Hol_datatype `
+ ex =
+    Failure of string
+  | Throw of 'e`;
+
+
+val _ = Hol_datatype `
+ result =
+    Value of 'a
+  | Ex of ( 'e ex)`;
+
+
+(* State, nondeterminism and exception monad with result value type 'a
+   and exception type 'e. *)
+val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_e) *) "monadS" , ``:'a_regs sequential_state -> (('b_a,'c_e)result #'a_regs sequential_state) set``);
+
+(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((returnS:'a -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) a s=  ({(Value a,s)}))`;
+
+
+(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*)
+val _ = Define `
+ ((bindS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) ->('a -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m f (s : 'regs sequential_state)=
+   (BIGUNION (IMAGE (\x .  
+  (case x of   (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s))))`;
+
+
+(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*)
+val _ = Define `
+ ((seqS:('regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) ->('regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m n=  (bindS m (\u .  
+  (case (u ) of ( (_ : unit) ) => n ))))`;
+
+
+(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((chooseS:'a set -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) xs s=  (IMAGE (\ x .  (Value x, s)) xs))`;
+
+
+(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((readS:('regs sequential_state -> 'a) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) f=  (\ s .  returnS (f s) s))`;
+
+
+(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((updateS:('regs sequential_state -> 'regs sequential_state) -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) f=  (\ s .  returnS ()  (f s)))`;
+
+
+(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((failS:string -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg s=  ({(Ex (Failure msg), s)}))`;
+
+
+(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () =  (chooseS {F; T}))`;
+
+
+(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((exitS:unit -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) () =  (failS "exit"))`;
+
+
+(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((throwS:'e -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) e s=  ({(Ex (Throw e), s)}))`;
+
+
+(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) ->  monadS 'regs 'a 'e2*)
+val _ = Define `
+ ((try_catchS:('regs sequential_state ->(('a,'e1)result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) m h s=
+   (BIGUNION (IMAGE (\x .  
+  (case x of
+        (Value a, s') => returnS a s'
+    | (Ex (Throw e), s') => h e s'
+    | (Ex (Failure msg), s') => {(Ex (Failure msg), s')}
+  )) (m s))))`;
+
+
+(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((assert_expS:bool -> string -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) exp msg=  (if exp then returnS ()  else failS msg))`;
+
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is "either 'r 'e", where "Right e"
+   represents a proper exception and "Left r" an early return of value "r". *)
+val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_r, 'd_e) *) "monadRS" , ``:('a_regs,'b_a, (('c_r,'d_e)sum)) monadS``);
+
+(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*)
+val _ = Define `
+ ((early_returnS:'r -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) r=  (throwS (INL r)))`;
+
+
+(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((catch_early_returnS:('regs sequential_state ->(('a,(('a,'e)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) m=
+   (try_catchS m
+    (\x .  (case x of   INL a => returnS a | INR e => throwS e ))))`;
+
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*)
+val _ = Define `
+ ((liftRS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) m=  (try_catchS m (\ e .  throwS (INR e))))`;
+
+
+(* Catch exceptions in the presence of early returns *)
+(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) ->  monadRS 'regs 'a 'r 'e2*)
+val _ = Define `
+ ((try_catchRS:('regs sequential_state ->(('a,(('r,'e1)sum))result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) m h=
+   (try_catchS m
+    (\x .  (case x of   INL r => throwS (INL r) | INR e => h e ))))`;
+
+
+(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((maybe_failS:string -> 'a option -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg= 
+  (\x .  (case x of   SOME a => returnS a | NONE => failS msg )))`;
+
+
+(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*)
+val _ = Define `
+ ((read_tagS:'a Bitvector_class -> 'a ->('regs,(bitU),'e)monadS)dict_Sail2_values_Bitvector_a addr=  (bindS
+  (maybe_failS "unsigned" (
+  dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . 
+  readS (\ s .  option_CASE (FLOOKUP s.tagstate addr) B0 I))))`;
+
+
+(* Read bytes from memory and return in little endian order *)
+(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*)
+val _ = Define `
+ ((read_mem_bytesS:'a Bitvector_class -> read_kind -> 'a -> num ->('regs,((memory_byte)list),'e)monadS)dict_Sail2_values_Bitvector_a read_kind addr sz=  (bindS
+  (maybe_failS "unsigned" (
+  dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . 
+  let sz = (int_of_num sz) in
+  let addrs = (index_list addr ((addr+sz)-( 1 : int))(( 1 : int))) in  
+  let read_byte = (\ s addr .  FLOOKUP s.memstate addr) in
+  bindS (readS (\ s .  just_list (MAP (read_byte s) addrs)))
+    (\x .  (case x of
+                 SOME mem_val => seqS
+                                   (updateS
+                                      (\ s . 
+                                       if read_is_exclusive read_kind then
+                                         ( s with<| last_exclusive_operation_was_load := T |>)
+                                       else s)) (returnS mem_val)
+             | NONE => failS "read_memS"
+           )))))`;
+
+
+(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*)
+val _ = Define `
+ ((read_memS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz=  (bindS
+  (read_mem_bytesS dict_Sail2_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . 
+  maybe_failS "bits_of_mem_bytes" (
+  dict_Sail2_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes)))))`;
+
+
+(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((excl_resultS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () =  (bindS
+  (readS (\ s .  s.last_exclusive_operation_was_load)) (\ excl_load .  seqS
+  (updateS (\ s .  ( s with<| last_exclusive_operation_was_load := F |>)))
+  (chooseS (if excl_load then {F; T} else {F})))))`;
+
+
+(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((write_mem_eaS:'a Bitvector_class -> write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail2_values_Bitvector_a write_kind addr sz=  (bindS
+  (maybe_failS "unsigned" (
+  dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . 
+  let sz = (int_of_num sz) in
+  updateS (\ s .  ( s with<| write_ea := (SOME (write_kind, addr, sz)) |>)))))`;
+
+
+(* Write little-endian list of bytes to previously announced address *)
+(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_mem_bytesS:((bitU)list)list -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) v=  (bindS
+  (readS (\ s .  s.write_ea)) (\x .  
+  (case x of
+        NONE => failS "write ea has not been announced yet"
+    | SOME (_, addr, sz) =>
+  let addrs = (index_list addr ((addr + sz) - ( 1 : int)) (( 1 : int))) in
+  (*let v = external_mem_value (bits_of v) in*)
+  let a_v = (lem_list$list_combine addrs v) in
+  let write_byte = (\mem p .  (case (mem ,p ) of
+                                  ( mem , (addr, v) ) => mem  |+ ( addr ,  
+                                                        v )
+                              )) in
+  seqS
+    (updateS
+       (\ s .  ( s with<| memstate := (FOLDL write_byte s.memstate a_v) |>)))
+    (returnS T)
+  ))))`;
+
+
+(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_mem_valS:'a Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail2_values_Bitvector_a v=  ((case mem_bytes_of_bits 
+  dict_Sail2_values_Bitvector_a v of
+    SOME v => write_mem_bytesS v
+  | NONE => failS "write_mem_val"
+)))`;
+
+
+(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_tagS:'a Bitvector_class -> 'a -> bitU ->('regs,(bool),'e)monadS)dict_Sail2_values_Bitvector_a addr t=  (bindS
+   (maybe_failS "unsigned" (
+  dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr .  seqS
+   (updateS (\ s .  ( s with<| tagstate := (s.tagstate |+ (addr, t)) |>)))
+   (returnS T))))`;
+
+
+(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((read_regS:('regs,'rv,'a)register_ref -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) reg=  (readS (\ s .  reg.read_from s.regstate)))`;
+
+
+(* TODO
+let read_reg_range reg i j state =
+  let v = slice (get_reg state (name_of_reg reg)) i j in
+  [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+  let v = access (get_reg state (name_of_reg reg)) i in
+  [(Value v,state)]
+let read_reg_field reg regfield =
+  let (i,j) = register_field_indices reg regfield in
+  read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+  let (i,_) = register_field_indices reg regfield in
+  read_reg_bit reg i *)
+
+(*val read_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*)
+val _ = Define `
+ ((read_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'regs sequential_state ->(('rv,'e)result#'regs sequential_state)set) (read, _) reg=  (bindS
+  (readS (\ s .  read reg s.regstate)) (\x .  
+  (case x of
+        SOME v => returnS v
+    | NONE => failS ( STRCAT "read_regvalS " reg)
+  ))))`;
+
+
+(*val write_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((write_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'rv -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) (_, write) reg v=  (bindS
+  (readS (\ s .  write reg v s.regstate)) (\x .  
+  (case x of
+        SOME rs' => updateS (\ s .  ( s with<| regstate := rs' |>))
+    | NONE => failS ( STRCAT "write_regvalS " reg)
+  ))))`;
+
+
+(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((write_regS:('regs,'rv,'a)register_ref -> 'a -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) reg v=
+   (updateS (\ s .  ( s with<| regstate := (reg.write_to v s.regstate) |>))))`;
+
+
+(* TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+  let current_value = get_reg state reg in
+  let new_value = f current_value v in
+  [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
+
+(* TODO Add Show typeclass for value and exception type *)
+(*val show_result : forall 'a 'e. result 'a 'e -> string*)
+val _ = Define `
+ ((show_result:('a,'e)result -> string)= 
+  (\x .  (case x of
+               Value _ => "Value ()"
+           | Ex (Failure msg) => STRCAT "Failure " msg
+           | Ex (Throw _) => "Throw"
+         )))`;
+
+
+(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*)
+val _ = Define `
+ ((prerr_results:(('a,'e)result#'s)set -> unit) rs=
+   (let _ = (IMAGE (\p .  
+  (case (p ) of ( (r, _) ) => let _ = (prerr_endline (show_result r)) in ()  )) rs) in
+  () ))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_stringScript.sml b/snapshots/hol4/sail/lib/hol/sail2_stringScript.sml
new file mode 100644
index 00000000..dc1cba63
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_stringScript.sml
@@ -0,0 +1,215 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_string.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_listTheory sail2_valuesTheory sail2_operatorsTheory lem_list_extraTheory lem_stringTheory lem_string_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_string"
+
+(*open import Pervasives*)
+(*open import List*)
+(*open import List_extra*)
+(*open import String*)
+(*open import String_extra*)
+
+(*open import Sail2_operators*)
+(*open import Sail2_values*)
+
+(*val string_sub : string -> ii -> ii -> string*)
+val _ = Define `
+ ((string_sub:string -> int -> int -> string) str start len=
+   (IMPLODE (TAKE (Num (ABS (I len))) (DROP (Num (ABS (I start))) (EXPLODE str)))))`;
+
+
+(*val string_startswith : string -> string -> bool*)
+val _ = Define `
+ ((string_startswith:string -> string -> bool) str1 str2=
+   (let prefix = (string_sub str1(( 0 : int)) (int_of_num (STRLEN str2))) in
+  (prefix = str2)))`;
+
+
+(*val string_drop : string -> ii -> string*)
+val _ = Define `
+ ((string_drop:string -> int -> string) str n=
+   (IMPLODE (DROP (Num (ABS (I n))) (EXPLODE str))))`;
+
+
+(*val string_length : string -> ii*)
+val _ = Define `
+ ((string_length:string -> int) s=  (int_of_num (STRLEN s)))`;
+
+
+val _ = Define `
+ ((string_append:string -> string -> string)=  STRCAT)`;
+
+
+(***********************************************
+ * Begin stuff that should be in Lem Num_extra *
+ ***********************************************)
+
+(*val maybeIntegerOfString : string -> maybe integer*)
+val _ = Define `
+ ((maybeIntegerOfString:string ->(int)option) _=  NONE)`;
+
+
+(***********************************************
+ * end stuff that should be in Lem Num_extra   *
+ ***********************************************)
+
+ val maybe_int_of_prefix_defn = Hol_defn "maybe_int_of_prefix" `
+ ((maybe_int_of_prefix:string ->(int#int)option) s=
+   ((case s of
+    "" => NONE
+  | str =>
+     let len = (string_length str) in
+     (case maybeIntegerOfString str of
+       SOME n => SOME (n, len)
+     | NONE => maybe_int_of_prefix (string_sub str(( 0 : int)) (len -( 1 : int)))
+     )
+  )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn maybe_int_of_prefix_defn;
+
+val _ = Define `
+ ((maybe_int_of_string:string ->(int)option)=  maybeIntegerOfString)`;
+
+
+(*val n_leading_spaces : string -> ii*)
+ val n_leading_spaces_defn = Hol_defn "n_leading_spaces" `
+ ((n_leading_spaces:string -> int) s=
+   (let len = (string_length s) in
+  if len =( 0 : int) then( 0 : int) else
+    if len =( 1 : int) then
+      (case s of
+           " " =>( 1 : int)
+         | _ =>( 0 : int)
+      )
+    else
+      (* match len with
+   *     (\* | 0 -> 0 *\)
+   * (\* | 1 -> *\) 
+   * | len -> *)
+           (* Isabelle generation for pattern matching on characters
+              is currently broken, so use an if-expression *)
+           if SUB (s, (( 0 : num))) = #" "
+           then( 1 : int) + (n_leading_spaces (string_sub s(( 1 : int)) (len -( 1 : int))))
+           else( 0 : int)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn n_leading_spaces_defn;
+  (* end *)
+
+val _ = Define `
+ ((opt_spc_matches_prefix:string ->(unit#int)option) s=
+   (SOME (() , n_leading_spaces s)))`;
+
+
+val _ = Define `
+ ((spc_matches_prefix:string ->(unit#int)option) s=
+   (let n = (n_leading_spaces s) in
+  (* match n with *)
+(* | 0 -> Nothing *)
+  if n =( 0 : int) then NONE else
+  (* | n -> *) SOME (() , n)))`;
+
+  (* end *)
+
+val _ = Define `
+ ((hex_bits_5_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 32 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 5 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+val _ = Define `
+ ((hex_bits_6_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 64 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 6 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+val _ = Define `
+ ((hex_bits_12_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 4096 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 12 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+val _ = Define `
+ ((hex_bits_13_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 8192 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 13 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+val _ = Define `
+ ((hex_bits_16_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 65536 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 16 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+
+val _ = Define `
+ ((hex_bits_20_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 1048576 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 20 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+val _ = Define `
+ ((hex_bits_21_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 2097152 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 21 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+
+val _ = Define `
+ ((hex_bits_32_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+   ((case maybe_int_of_prefix s of
+    NONE => NONE
+  | SOME (n, len) =>
+     if(( 0 : int) <= n) /\ (n <( 4294967296 : int)) then
+       SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 2147483648 : int)) n, len))
+     else
+       NONE
+  )))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_valuesAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/sail2_valuesAuxiliaryScript.sml
new file mode 100644
index 00000000..b475c5ea
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_valuesAuxiliaryScript.sml
@@ -0,0 +1,139 @@
+(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory;
+open intLib;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "sail2_valuesAuxiliary"
+
+
+(****************************************************)
+(*                                                  *)
+(* Termination Proofs                               *)
+(*                                                  *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (shr_int_def, shr_int_ind) *)
+val (shr_int_rw, shr_int_ind_rw) =
+  Defn.tprove_no_defn ((shr_int_def, shr_int_ind),
+    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+  )
+val shr_int_rw = save_thm ("shr_int_rw", shr_int_rw);
+val shr_int_ind_rw = save_thm ("shr_int_ind_rw", shr_int_ind_rw);
+val () = computeLib.add_persistent_funs["shr_int_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (shl_int_def, shl_int_ind) *)
+val (shl_int_rw, shl_int_ind_rw) =
+  Defn.tprove_no_defn ((shl_int_def, shl_int_ind),
+    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+  )
+val shl_int_rw = save_thm ("shl_int_rw", shl_int_rw);
+val shl_int_ind_rw = save_thm ("shl_int_ind_rw", shl_int_ind_rw);
+val () = computeLib.add_persistent_funs["shl_int_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (repeat_def, repeat_ind) *)
+val (repeat_rw, repeat_ind_rw) =
+  Defn.tprove_no_defn ((repeat_def, repeat_ind),
+    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+  )
+val repeat_rw = save_thm ("repeat_rw", repeat_rw);
+val repeat_ind_rw = save_thm ("repeat_ind_rw", repeat_ind_rw);
+val () = computeLib.add_persistent_funs["repeat_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (bools_of_nat_aux_def, bools_of_nat_aux_ind) *)
+val (bools_of_nat_aux_rw, bools_of_nat_aux_ind_rw) =
+  Defn.tprove_no_defn ((bools_of_nat_aux_def, bools_of_nat_aux_ind),
+    WF_REL_TAC`measure (Num o FST)` \\ COOPER_TAC
+  )
+val bools_of_nat_aux_rw = save_thm ("bools_of_nat_aux_rw", bools_of_nat_aux_rw);
+val bools_of_nat_aux_ind_rw = save_thm ("bools_of_nat_aux_ind_rw", bools_of_nat_aux_ind_rw);
+val () = computeLib.add_persistent_funs["bools_of_nat_aux_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (pad_list_def, pad_list_ind) *)
+val (pad_list_rw, pad_list_ind_rw) =
+  Defn.tprove_no_defn ((pad_list_def, pad_list_ind),
+    WF_REL_TAC`measure (Num o SND o SND)` \\ COOPER_TAC
+  )
+val pad_list_rw = save_thm ("pad_list_rw", pad_list_rw);
+val pad_list_ind_rw = save_thm ("pad_list_ind_rw", pad_list_ind_rw);
+val () = computeLib.add_persistent_funs["pad_list_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (reverse_endianness_list_def, reverse_endianness_list_ind) *)
+val (reverse_endianness_list_rw, reverse_endianness_list_ind_rw) =
+  Defn.tprove_no_defn ((reverse_endianness_list_def, reverse_endianness_list_ind),
+    WF_REL_TAC`measure LENGTH` \\ rw[drop_list_def,nat_of_int_def]
+  )
+val reverse_endianness_list_rw = save_thm ("reverse_endianness_list_rw", reverse_endianness_list_rw);
+val reverse_endianness_list_ind_rw = save_thm ("reverse_endianness_list_ind_rw", reverse_endianness_list_ind_rw);
+val () = computeLib.add_persistent_funs["reverse_endianness_list_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (index_list_def, index_list_ind) *)
+val (index_list_rw, index_list_ind_rw) =
+  Defn.tprove_no_defn ((index_list_def, index_list_ind),
+    WF_REL_TAC`measure (λ(x,y,z). Num(1+(if z > 0 then int_max (-1) (y - x) else int_max (-1) (x - y))))`
+    \\ rw[integerTheory.INT_MAX]
+    \\ intLib.COOPER_TAC
+  )
+val index_list_rw = save_thm ("index_list_rw", index_list_rw);
+val index_list_ind_rw = save_thm ("index_list_ind_rw", index_list_ind_rw);
+val () = computeLib.add_persistent_funs["index_list_rw"];
+
+
+(*
+(* val gst = Defn.tgoal_no_defn (while_def, while_ind) *)
+val (while_rw, while_ind_rw) =
+  Defn.tprove_no_defn ((while_def, while_ind),
+    cheat (* the termination proof *)
+  )
+val while_rw = save_thm ("while_rw", while_rw);
+val while_ind_rw = save_thm ("while_ind_rw", while_ind_rw);
+*)
+
+
+(*
+(* val gst = Defn.tgoal_no_defn (until_def, until_ind) *)
+val (until_rw, until_ind_rw) =
+  Defn.tprove_no_defn ((until_def, until_ind),
+    cheat (* the termination proof *)
+  )
+val until_rw = save_thm ("until_rw", until_rw);
+val until_ind_rw = save_thm ("until_ind_rw", until_ind_rw);
+*)
+
+
+(****************************************************)
+(*                                                  *)
+(* Lemmata                                          *)
+(*                                                  *)
+(****************************************************)
+
+val just_list_spec = store_thm("just_list_spec",
+``((! xs. (just_list xs = NONE) <=> MEM NONE xs) /\
+   (! xs es. (just_list xs = SOME es) <=> (xs = MAP SOME es)))``,
+  (* Theorem: just_list_spec*)
+  conj_tac
+  \\ ho_match_mp_tac just_list_ind
+  \\ Cases \\ rw[]
+  \\ rw[Once just_list_def]
+  >- ( CASE_TAC \\ fs[] \\ CASE_TAC )
+  >- PROVE_TAC[]
+  \\ Cases_on`es` \\ fs[]
+  \\ CASE_TAC \\ fs[]
+  \\ CASE_TAC \\ fs[]
+);
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml b/snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml
new file mode 100644
index 00000000..1d6293df
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml
@@ -0,0 +1,1246 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_values.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_values"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail_impl_base*)
+
+
+val _ = type_abbrev( "ii" , ``: int``);
+val _ = type_abbrev( "nn" , ``: num``);
+
+(*val nat_of_int : integer -> nat*)
+val _ = Define `
+ ((nat_of_int:int -> num) i=  (if i <( 0 : int) then( 0 : num) else Num (ABS (I i))))`;
+
+
+(*val pow : integer -> integer -> integer*)
+val _ = Define `
+ ((pow0:int -> int -> int) m n=  (m ** (nat_of_int n)))`;
+
+
+val _ = Define `
+ ((pow2:int -> int) n=  (pow0(( 2 : int)) n))`;
+
+
+(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
+
+(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
+
+(*let add_int l r = integerAdd l r
+let add_signed l r = integerAdd l r
+let sub_int l r = integerMinus l r
+let mult_int l r = integerMult l r
+let div_int l r = integerDiv l r
+let div_nat l r = natDiv l r
+let power_int_nat l r = integerPow l r
+let power_int_int l r = integerPow l (nat_of_int r)
+let negate_int i = integerNegate i
+let min_int l r = integerMin l r
+let max_int l r = integerMax l r
+
+let add_real l r = realAdd l r
+let sub_real l r = realMinus l r
+let mult_real l r = realMult l r
+let div_real l r = realDiv l r
+let negate_real r = realNegate r
+let abs_real r = realAbs r
+let power_real b e = realPowInteger b e*)
+
+(*val print_endline : string -> unit*)
+val _ = Define `
+ ((print_endline:string -> unit) _=  () )`;
+
+(* declare ocaml target_rep function print_endline = `print_endline` *)
+
+(*val prerr_endline : string -> unit*)
+val _ = Define `
+ ((prerr_endline:string -> unit) _=  () )`;
+
+
+val _ = Define `
+ ((prerr:string -> unit) x=  (prerr_endline x))`;
+
+
+(*val print_int : string -> integer -> unit*)
+val _ = Define `
+ ((print_int:string -> int -> unit) msg i=  (print_endline ( STRCAT msg (stringFromInteger i))))`;
+
+
+(*val prerr_int : string -> integer -> unit*)
+val _ = Define `
+ ((prerr_int:string -> int -> unit) msg i=  (prerr_endline ( STRCAT msg (stringFromInteger i))))`;
+
+
+(*val putchar : integer -> unit*)
+val _ = Define `
+ ((putchar:int -> unit) _=  () )`;
+
+
+(*val shr_int : ii -> ii -> ii*)
+ val shr_int_defn = Hol_defn "shr_int" `
+ ((shr_int:int -> int -> int) x s=  (if s >( 0 : int) then shr_int (x /( 2 : int)) (s -( 1 : int)) else x))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shr_int_defn;
+
+(*val shl_int : integer -> integer -> integer*)
+ val shl_int_defn = Hol_defn "shl_int" `
+ ((shl_int:int -> int -> int) i shift=  (if shift >( 0 : int) then( 2 : int) * shl_int i (shift -( 1 : int)) else i))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shl_int_defn;
+val _ = Define `
+ ((take_list:int -> 'a list -> 'a list) n xs=  (TAKE (nat_of_int n) xs))`;
+
+val _ = Define `
+ ((drop_list:int -> 'a list -> 'a list) n xs=  (DROP (nat_of_int n) xs))`;
+
+
+(*val repeat : forall 'a. list 'a -> integer -> list 'a*)
+ val repeat_defn = Hol_defn "repeat" `
+ ((repeat:'a list -> int -> 'a list) xs n=
+   (if n <=( 0 : int) then []
+  else xs ++ repeat xs (n -( 1 : int))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn repeat_defn;
+
+val _ = Define `
+ ((duplicate_to_list:'a -> int -> 'a list) bit length=  (repeat [bit] length))`;
+
+
+ val _ = Define `
+ ((replace:'a list -> int -> 'a -> 'a list) bs (n : int) b'=  ((case bs of
+    [] => []
+  | b :: bs =>
+     if n =( 0 : int) then b' :: bs
+              else b :: replace bs (n -( 1 : int)) b'
+  )))`;
+
+
+val _ = Define `
+ ((upper:'a -> 'a) n=  n)`;
+
+
+(* Modulus operation corresponding to quot below -- result
+   has sign of dividend. *)
+val _ = Define `
+ ((hardware_mod:int -> int -> int) (a: int) (b:int) : int=
+   (let m = ((ABS a) % (ABS b)) in
+  if a <( 0 : int) then ~ m else m))`;
+
+
+(* There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that *)
+val _ = Define `
+ ((hardware_quot:int -> int -> int) (a:int) (b:int) : int=
+   (let q = ((ABS a) / (ABS b)) in
+  if ((a<( 0 : int)) <=> (b<( 0 : int))) then
+    q  (* same sign -- result positive *)
+  else
+    ~ q))`;
+ (* different sign -- result negative *)
+
+val _ = Define `
+ ((max_64u:int)=  (((( 2 : int))**(( 64 : num))) -( 1 : int)))`;
+
+val _ = Define `
+ ((max_64:int)=   (((( 2 : int))**(( 63 : num))) -( 1 : int)))`;
+
+val _ = Define `
+ ((min_64:int)=  (( 0 : int) - ((( 2 : int))**(( 63 : num)))))`;
+
+val _ = Define `
+ ((max_32u:int)=  ((( 4294967295 : int) : int)))`;
+
+val _ = Define `
+ ((max_32:int)=   ((( 2147483647 : int) : int)))`;
+
+val _ = Define `
+ ((min_32:int)=   ((( 0 : int) -( 2147483648 : int) : int)))`;
+
+val _ = Define `
+ ((max_8:int)=    ((( 127 : int) : int)))`;
+
+val _ = Define `
+ ((min_8:int)=    ((( 0 : int) -( 128 : int) : int)))`;
+
+val _ = Define `
+ ((max_5:int)=    ((( 31 : int) : int)))`;
+
+val _ = Define `
+ ((min_5:int)=    ((( 0 : int) -( 32 : int) : int)))`;
+
+
+(* just_list takes a list of maybes and returns Just xs if all elements have
+   a value, and Nothing if one of the elements is Nothing. *)
+(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*)
+ val _ = Define `
+ ((just_list:('a option)list ->('a list)option) l=  ((case l of
+    [] => SOME []
+  | (x :: xs) =>
+    (case (x, just_list xs) of
+        (SOME x, SOME xs) => SOME (x :: xs)
+      | (_, _) => NONE
+    )
+  )))`;
+
+
+(*val maybe_failwith : forall 'a. maybe 'a -> 'a*)
+val _ = Define `
+ ((maybe_failwith:'a option -> 'a)= 
+  (\x .  (case x of   SOME a => a | NONE => failwith "maybe_failwith" )))`;
+
+
+(*** Bits *)
+val _ = Hol_datatype `
+ bitU = B0 | B1 | BU`;
+
+
+val _ = Define `
+ ((showBitU:bitU -> string)= 
+  (\x .  (case x of   B0 => "O" | B1 => "I" | BU => "U" )))`;
+
+
+val _ = Define `
+ ((bitU_char:bitU -> char)= 
+  (\x .  (case x of   B0 => #"0" | B1 => #"1" | BU => #"?" )))`;
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_values_bitU_dict:(bitU)Show_class)= (<|
+
+  show_method := showBitU|>))`;
+
+
+(*val compare_bitU : bitU -> bitU -> ordering*)
+val _ = Define `
+ ((compare_bitU:bitU -> bitU -> ordering) l r=  ((case (l, r) of
+    (BU, BU) => EQUAL
+  | (B0, B0) => EQUAL
+  | (B1, B1) => EQUAL
+  | (BU, _)  => LESS
+  | (_, BU)  => GREATER
+  | (B0, _)  => LESS
+  | (_, _)   => GREATER
+)))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_Sail2_values_bitU_dict:(bitU)Ord_class)= (<|
+
+  compare_method := compare_bitU;
+
+  isLess_method := (\  l r. (compare_bitU l r) = LESS);
+
+  isLessEqual_method := (\ l r. (compare_bitU l r) <> GREATER);
+
+  isGreater_method := (\  l r. (compare_bitU l r) = GREATER);
+
+  isGreaterEqual_method := (\ l r. (compare_bitU l r) <> LESS)|>))`;
+
+
+val _ = Hol_datatype `
+(*  'a *) BitU_class= <|
+  to_bitU_method : 'a -> bitU;
+  of_bitU_method : bitU -> 'a
+|>`;
+
+
+val _ = Define `
+((instance_Sail2_values_BitU_Sail2_values_bitU_dict:(bitU)BitU_class)= (<|
+
+  to_bitU_method := (\ b. b);
+
+  of_bitU_method := (\ b. b)|>))`;
+
+
+val _ = Define `
+ ((bool_of_bitU:bitU ->(bool)option)= 
+  (\x .  (case x of   B0 => SOME F | B1 => SOME T | BU => NONE )))`;
+
+
+val _ = Define `
+ ((bitU_of_bool:bool -> bitU) b=  (if b then B1 else B0))`;
+
+
+(*instance (BitU bool)
+  let to_bitU = bitU_of_bool
+  let of_bitU = bool_of_bitU
+end*)
+
+val _ = Define `
+ ((cast_bit_bool:bitU ->(bool)option)=  bool_of_bitU)`;
+
+
+val _ = Define `
+ ((not_bit:bitU -> bitU)= 
+  (\x .  (case x of   B1 => B0 | B0 => B1 | BU => BU )))`;
+
+
+(*val is_one : integer -> bitU*)
+val _ = Define `
+ ((is_one:int -> bitU) i=
+   (if i =( 1 : int) then B1 else B0))`;
+
+
+(*val and_bit : bitU -> bitU -> bitU*)
+val _ = Define `
+ ((and_bit:bitU -> bitU -> bitU) x y=
+   ((case (x, y) of
+      (B0, _) => B0
+    | (_, B0) => B0
+    | (B1, B1) => B1
+    | (_, _) => BU
+  )))`;
+
+
+(*val or_bit : bitU -> bitU -> bitU*)
+val _ = Define `
+ ((or_bit:bitU -> bitU -> bitU) x y=
+   ((case (x, y) of
+      (B1, _) => B1
+    | (_, B1) => B1
+    | (B0, B0) => B0
+    | (_, _) => BU
+  )))`;
+
+
+(*val xor_bit : bitU -> bitU -> bitU*)
+val _ = Define `
+ ((xor_bit:bitU -> bitU -> bitU) x y=
+  ((case (x, y) of
+      (B0, B0) => B0
+    | (B0, B1) => B1
+    | (B1, B0) => B1
+    | (B1, B1) => B0
+    | (_, _) => BU
+  )))`;
+
+
+(*val &. : bitU -> bitU -> bitU*)
+
+(*val |. : bitU -> bitU -> bitU*)
+
+(*val +. : bitU -> bitU -> bitU*)
+
+
+(*** Bool lists ***)
+
+(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
+ val bools_of_nat_aux_defn = Hol_defn "bools_of_nat_aux" `
+ ((bools_of_nat_aux:int -> num ->(bool)list ->(bool)list) len x acc=
+   (if len <=( 0 : int) then acc
+  else bools_of_nat_aux (len -( 1 : int)) (x DIV( 2:num)) ((if (x MOD( 2:num)) =( 1:num) then T else F) :: acc)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn bools_of_nat_aux_defn;
+val _ = Define `
+ ((bools_of_nat:int -> num ->(bool)list) len n=  (bools_of_nat_aux len n []))`;
+ (*List.reverse (bools_of_nat_aux n)*)
+
+(*val nat_of_bools_aux : natural -> list bool -> natural*)
+ val _ = Define `
+ ((nat_of_bools_aux:num ->(bool)list -> num) acc bs=  ((case bs of
+    [] => acc
+  | T :: bs => nat_of_bools_aux ((( 2:num) * acc) +( 1:num)) bs
+  | F :: bs => nat_of_bools_aux (( 2:num) * acc) bs
+)))`;
+
+val _ = Define `
+ ((nat_of_bools:(bool)list -> num) bs=  (nat_of_bools_aux(( 0:num)) bs))`;
+
+
+(*val unsigned_of_bools : list bool -> integer*)
+val _ = Define `
+ ((unsigned_of_bools:(bool)list -> int) bs=  (int_of_num (nat_of_bools bs)))`;
+
+
+(*val signed_of_bools : list bool -> integer*)
+val _ = Define `
+ ((signed_of_bools:(bool)list -> int) bs=
+   ((case bs of
+      T :: _  =>( 0 : int) - (( 1 : int) + (unsigned_of_bools (MAP (\ x. ~ x) bs)))
+    | F :: _ => unsigned_of_bools bs
+    | [] =>( 0 : int) (* Treat empty list as all zeros *)
+  )))`;
+
+
+(*val int_of_bools : bool -> list bool -> integer*)
+val _ = Define `
+ ((int_of_bools:bool ->(bool)list -> int) sign bs=  (if sign then signed_of_bools bs else unsigned_of_bools bs))`;
+
+
+(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
+ val pad_list_defn = Hol_defn "pad_list" `
+ ((pad_list:'a -> 'a list -> int -> 'a list) x xs n=
+   (if n <=( 0 : int) then xs else pad_list x (x :: xs) (n -( 1 : int))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn pad_list_defn;
+
+val _ = Define `
+ ((ext_list:'a -> int -> 'a list -> 'a list) pad len xs=
+   (let longer = (len - (int_of_num (LENGTH xs))) in
+  if longer <( 0 : int) then DROP (nat_of_int (ABS (longer))) xs
+  else pad_list pad xs longer))`;
+
+
+val _ = Define `
+ ((extz_bools:int ->(bool)list ->(bool)list) len bs=  (ext_list F len bs))`;
+
+val _ = Define `
+ ((exts_bools:int ->(bool)list ->(bool)list) len bs=
+   ((case bs of
+      T :: _ => ext_list T len bs
+    | _ => ext_list F len bs
+  )))`;
+
+
+ val _ = Define `
+ ((add_one_bool_ignore_overflow_aux:(bool)list ->(bool)list) bits=  ((case bits of
+    [] => []
+  | F :: bits => T :: bits
+  | T :: bits => F :: add_one_bool_ignore_overflow_aux bits
+)))`;
+
+
+val _ = Define `
+ ((add_one_bool_ignore_overflow:(bool)list ->(bool)list) bits=
+   (REVERSE (add_one_bool_ignore_overflow_aux (REVERSE bits))))`;
+
+
+(*let bool_list_of_int n =
+  let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
+  if n >= (0 : integer) then bs_abs
+  else add_one_bool_ignore_overflow (List.map not bs_abs)
+let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
+val _ = Define `
+ ((bools_of_int:int -> int ->(bool)list) len n=
+   (let bs_abs = (bools_of_nat len (Num (ABS (ABS n)))) in
+  if n >= (( 0 : int) : int) then bs_abs
+  else add_one_bool_ignore_overflow (MAP (\ x. ~ x) bs_abs)))`;
+
+
+(*** Bit lists ***)
+
+(*val has_undefined_bits : list bitU -> bool*)
+val _ = Define `
+ ((has_undefined_bits:(bitU)list -> bool) bs=  (EXISTS (\x .  
+  (case x of BU => T | _ => F )) bs))`;
+
+
+val _ = Define `
+ ((bits_of_nat:int -> num ->(bitU)list) len n=  (MAP bitU_of_bool (bools_of_nat len n)))`;
+
+
+val _ = Define `
+ ((nat_of_bits:(bitU)list ->(num)option) bits=
+   ((case (just_list (MAP bool_of_bitU bits)) of
+      SOME bs => SOME (nat_of_bools bs)
+    | NONE => NONE
+  )))`;
+
+
+val _ = Define `
+ ((not_bits:(bitU)list ->(bitU)list)=  (MAP not_bit))`;
+
+
+(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*)
+val _ = Define `
+ ((binop_list:('a -> 'a -> 'a) -> 'a list -> 'a list -> 'a list) op xs ys=
+   (FOLDR (\ (x, y) acc .  op x y :: acc) [] (list_combine xs ys)))`;
+
+
+val _ = Define `
+ ((unsigned_of_bits:(bitU)list ->(int)option) bits=
+   ((case (just_list (MAP bool_of_bitU bits)) of
+      SOME bs => SOME (unsigned_of_bools bs)
+    | NONE => NONE
+  )))`;
+
+
+val _ = Define `
+ ((signed_of_bits:(bitU)list ->(int)option) bits=
+   ((case (just_list (MAP bool_of_bitU bits)) of
+      SOME bs => SOME (signed_of_bools bs)
+    | NONE => NONE
+  )))`;
+
+
+(*val int_of_bits : bool -> list bitU -> maybe integer*)
+val _ = Define `
+ ((int_of_bits:bool ->(bitU)list ->(int)option) sign bs=  (if sign then signed_of_bits bs else unsigned_of_bits bs))`;
+
+
+val _ = Define `
+ ((extz_bits:int ->(bitU)list ->(bitU)list) len bits=  (ext_list B0 len bits))`;
+
+val _ = Define `
+ ((exts_bits:int ->(bitU)list ->(bitU)list) len bits=
+   ((case bits of
+    BU :: _ => ext_list BU len bits
+  | B1 :: _ => ext_list B1 len bits
+  | _ => ext_list B0 len bits
+  )))`;
+
+
+ val _ = Define `
+ ((add_one_bit_ignore_overflow_aux:(bitU)list ->(bitU)list) bits=  ((case bits of
+    [] => []
+  | B0 :: bits => B1 :: bits
+  | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits
+  | BU :: bits => BU :: MAP (\b .  
+  (case (b ) of ( _ ) => BU )) bits
+)))`;
+
+
+val _ = Define `
+ ((add_one_bit_ignore_overflow:(bitU)list ->(bitU)list) bits=
+   (REVERSE (add_one_bit_ignore_overflow_aux (REVERSE bits))))`;
+
+
+(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n)
+let bits_of_int len n = exts_bits len (bit_list_of_int n)*)
+val _ = Define `
+ ((bits_of_int:int -> int ->(bitU)list) len n=  (MAP bitU_of_bool (bools_of_int len n)))`;
+
+
+(*val arith_op_bits :
+  (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((arith_op_bits:(int -> int -> int) -> bool ->(bitU)list ->(bitU)list ->(bitU)list) op sign l r=
+   ((case (int_of_bits sign l, int_of_bits sign r) of
+      (SOME li, SOME ri) => bits_of_int (int_of_num (LENGTH l)) (op li ri)
+    | (_, _) => repeat [BU] (int_of_num (LENGTH l))
+  )))`;
+
+
+val _ = Define `
+ ((char_of_nibble:bitU#bitU#bitU#bitU ->(char)option)= 
+  (\x .  (case x of
+               (B0, B0, B0, B0) => SOME #"0"
+           | (B0, B0, B0, B1) => SOME #"1"
+           | (B0, B0, B1, B0) => SOME #"2"
+           | (B0, B0, B1, B1) => SOME #"3"
+           | (B0, B1, B0, B0) => SOME #"4"
+           | (B0, B1, B0, B1) => SOME #"5"
+           | (B0, B1, B1, B0) => SOME #"6"
+           | (B0, B1, B1, B1) => SOME #"7"
+           | (B1, B0, B0, B0) => SOME #"8"
+           | (B1, B0, B0, B1) => SOME #"9"
+           | (B1, B0, B1, B0) => SOME #"A"
+           | (B1, B0, B1, B1) => SOME #"B"
+           | (B1, B1, B0, B0) => SOME #"C"
+           | (B1, B1, B0, B1) => SOME #"D"
+           | (B1, B1, B1, B0) => SOME #"E"
+           | (B1, B1, B1, B1) => SOME #"F"
+           | _ => NONE
+         )))`;
+
+
+ val _ = Define `
+ ((hexstring_of_bits:(bitU)list ->((char)list)option) bs=  ((case bs of
+    b1 :: b2 :: b3 :: b4 :: bs =>
+     let n = (char_of_nibble (b1, b2, b3, b4)) in
+     let s = (hexstring_of_bits bs) in
+     (case (n, s) of
+       (SOME n, SOME s) => SOME (n :: s)
+     | _ => NONE
+     )
+  | [] => SOME []
+  | _ => NONE
+  )))`;
+
+
+val _ = Define `
+ ((show_bitlist:(bitU)list -> string) bs=
+   ((case hexstring_of_bits bs of
+    SOME s => IMPLODE (#"0" :: (#"x" :: s))
+  | NONE => IMPLODE (#"0" :: (#"b" :: MAP bitU_char bs))
+  )))`;
+
+
+(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*)
+val _ = Define `
+ ((subrange_list_inc:'a list -> int -> int -> 'a list) xs i j=
+   (let (toJ,suffix0) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in
+  let (prefix0,fromItoJ) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in
+  fromItoJ))`;
+
+
+(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*)
+val _ = Define `
+ ((subrange_list_dec:'a list -> int -> int -> 'a list) xs i j=
+   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+  subrange_list_inc xs (top - i) (top - j)))`;
+
+
+(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*)
+val _ = Define `
+ ((subrange_list:bool -> 'a list -> int -> int -> 'a list) is_inc xs i j=  (if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j))`;
+
+
+(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
+val _ = Define `
+ ((update_subrange_list_inc:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'=
+   (let (toJ,suffix) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in
+  let (prefix,fromItoJ0) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in
+  (prefix ++ xs') ++ suffix))`;
+
+
+(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
+val _ = Define `
+ ((update_subrange_list_dec:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'=
+   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+  update_subrange_list_inc xs (top - i) (top - j) xs'))`;
+
+
+(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*)
+val _ = Define `
+ ((update_subrange_list:bool -> 'a list -> int -> int -> 'a list -> 'a list) is_inc xs i j xs'=
+   (if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'))`;
+
+
+(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*)
+val _ = Define `
+ ((access_list_inc:'a list -> int -> 'a) xs n=  (EL (nat_of_int n) xs))`;
+
+
+(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*)
+val _ = Define `
+ ((access_list_dec:'a list -> int -> 'a) xs n=
+   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+  access_list_inc xs (top - n)))`;
+
+
+(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*)
+val _ = Define `
+ ((access_list:bool -> 'a list -> int -> 'a) is_inc xs n=
+   (if is_inc then access_list_inc xs n else access_list_dec xs n))`;
+
+
+(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*)
+val _ = Define `
+ ((update_list_inc:'a list -> int -> 'a -> 'a list) xs n x=  (LUPDATE x (nat_of_int n) xs))`;
+
+
+(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*)
+val _ = Define `
+ ((update_list_dec:'a list -> int -> 'a -> 'a list) xs n x=
+   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+  update_list_inc xs (top - n) x))`;
+
+
+(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*)
+val _ = Define `
+ ((update_list:bool -> 'a list -> int -> 'a -> 'a list) is_inc xs n x=
+   (if is_inc then update_list_inc xs n x else update_list_dec xs n x))`;
+
+
+val _ = Define `
+ ((extract_only_bit:(bitU)list -> bitU)= 
+  (\x .  (case x of   [] => BU | [e] => e | _ => BU )))`;
+
+
+(*** Machine words *)
+
+(*val length_mword : forall 'a. mword 'a -> integer*)
+
+(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice_mword_dec:'a words$word -> int -> int -> 'b words$word) w i j=  (words$word_extract (nat_of_int j) (nat_of_int i) w))`;
+
+
+(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice_mword_inc:'a words$word -> int -> int -> 'b words$word) w i j=
+   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+  slice_mword_dec w (top - i) (top - j)))`;
+
+
+(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word) is_inc w i j=  (if is_inc then slice_mword_inc w i j else slice_mword_dec w i j))`;
+
+
+(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_slice_mword_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=  (words$bit_field_insert (nat_of_int j) (nat_of_int i) w' w))`;
+
+
+(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_slice_mword_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=
+   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+  update_slice_mword_dec w (top - i) (top - j) w'))`;
+
+
+(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word -> 'a words$word) is_inc w i j w'=
+   (if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'))`;
+
+
+(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_mword_dec:'a words$word -> int -> bitU) w n=  (bitU_of_bool (words$word_bit (nat_of_int n) w)))`;
+
+
+(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_mword_inc:'a words$word -> int -> bitU) w n=
+   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+  access_mword_dec w (top - n)))`;
+
+
+(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_mword:bool -> 'a words$word -> int -> bitU) is_inc w n=
+   (if is_inc then access_mword_inc w n else access_mword_dec w n))`;
+
+
+(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+val _ = Define `
+ ((update_mword_bool_dec:'a words$word -> int -> bool -> 'a words$word) w n b=  ($:+ (nat_of_int n) b w))`;
+
+val _ = Define `
+ ((update_mword_dec:'a words$word -> int -> bitU ->('a words$word)option) w n b=  (OPTION_MAP (update_mword_bool_dec w n) (bool_of_bitU b)))`;
+
+
+(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+val _ = Define `
+ ((update_mword_bool_inc:'a words$word -> int -> bool -> 'a words$word) w n b=
+   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+  update_mword_bool_dec w (top - n) b))`;
+
+val _ = Define `
+ ((update_mword_inc:'a words$word -> int -> bitU ->('a words$word)option) w n b=  (OPTION_MAP (update_mword_bool_inc w n) (bool_of_bitU b)))`;
+
+
+(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
+val _ = Define `
+ ((int_of_mword:bool -> 'a words$word -> int) sign w=
+   (if sign then integer_word$w2i w else lem$w2ui w))`;
+
+
+(* Translating between a type level number (itself 'n) and an integer *)
+
+val _ = Define `
+ ((size_itself_int:'a itself -> int) x=  (int_of_num (size_itself x)))`;
+
+
+(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n),
+   the actual integer is ignored. *)
+
+(*val make_the_value : forall 'n. integer -> itself 'n*)
+val _ = Define `
+ ((make_the_value:int -> 'n itself) _=  the_value)`;
+
+
+(*** Bitvectors *)
+
+val _ = Hol_datatype `
+(*  'a *) Bitvector_class= <|
+  bits_of_method : 'a -> bitU list;
+  (* We allow of_bits to be partial, as not all bitvector representations
+     support undefined bits *)
+  of_bits_method : bitU list ->  'a option;
+  of_bools_method : bool list -> 'a;
+  length_method : 'a -> int;
+  (* of_int: the first parameter specifies the desired length of the bitvector *)
+  of_int_method : int -> int -> 'a;
+  (* Conversion to integers is undefined if any bit is undefined *)
+  unsigned_method : 'a ->  int option;
+  signed_method : 'a ->  int option;
+  (* Lifting of integer operations to bitvectors:  The boolean flag indicates
+     whether to treat the bitvectors as signed (true) or not (false). *)
+  arith_op_bv_method : (int -> int -> int) -> bool -> 'a -> 'a -> 'a
+|>`;
+
+
+(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*)
+val _ = Define `
+ ((of_bits_failwith:'a Bitvector_class ->(bitU)list -> 'a)dict_Sail2_values_Bitvector_a bits=  (maybe_failwith (
+  dict_Sail2_values_Bitvector_a.of_bits_method bits)))`;
+
+
+val _ = Define `
+ ((int_of_bv:'a Bitvector_class -> bool -> 'a ->(int)option)dict_Sail2_values_Bitvector_a sign=  (if sign then  
+  dict_Sail2_values_Bitvector_a.signed_method else  dict_Sail2_values_Bitvector_a.unsigned_method))`;
+
+
+val _ = Define `
+((instance_Sail2_values_Bitvector_list_dict:'a BitU_class ->('a list)Bitvector_class)dict_Sail2_values_BitU_a= (<|
+
+  bits_of_method := (\ v. MAP  
+  dict_Sail2_values_BitU_a.to_bitU_method v);
+
+  of_bits_method := (\ v. SOME (MAP  
+  dict_Sail2_values_BitU_a.of_bitU_method v));
+
+  of_bools_method := (\ v. MAP  
+  dict_Sail2_values_BitU_a.of_bitU_method (MAP bitU_of_bool v));
+
+  length_method := (\ xs. int_of_num (LENGTH xs));
+
+  of_int_method := (\ len n. MAP  
+  dict_Sail2_values_BitU_a.of_bitU_method (bits_of_int len n));
+
+  unsigned_method := (\ v. unsigned_of_bits (MAP  
+  dict_Sail2_values_BitU_a.to_bitU_method v));
+
+  signed_method := (\ v. signed_of_bits (MAP  
+  dict_Sail2_values_BitU_a.to_bitU_method v));
+
+  arith_op_bv_method := (\ op sign l r. MAP  
+  dict_Sail2_values_BitU_a.of_bitU_method (arith_op_bits op sign (MAP  
+  dict_Sail2_values_BitU_a.to_bitU_method l) (MAP  dict_Sail2_values_BitU_a.to_bitU_method r)))|>))`;
+
+
+val _ = Define `
+((instance_Sail2_values_Bitvector_Machine_word_mword_dict:('a words$word)Bitvector_class)= (<|
+
+  bits_of_method := (\ v. MAP bitU_of_bool (bitstring$w2v v));
+
+  of_bits_method := (\ v. OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU v)));
+
+  of_bools_method := (\ v. bitstring$v2w v);
+
+  length_method := (\ v. int_of_num (words$word_len v));
+
+  of_int_method := (\i n .  
+  (case (i ,n ) of ( _ , n ) => integer_word$i2w n ));
+
+  unsigned_method := (\ v. SOME (lem$w2ui v));
+
+  signed_method := (\ v. SOME (integer_word$w2i v));
+
+  arith_op_bv_method := (\ op sign l r. integer_word$i2w (op (int_of_mword sign l) (int_of_mword sign r)))|>))`;
+
+
+val _ = Define `
+ ((access_bv_inc:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail2_values_Bitvector_a v n=  (access_list T  (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) n))`;
+
+val _ = Define `
+ ((access_bv_dec:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail2_values_Bitvector_a v n=  (access_list F (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) n))`;
+
+
+val _ = Define `
+ ((update_bv_inc:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail2_values_Bitvector_a v n b=  (update_list T  (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) n b))`;
+
+val _ = Define `
+ ((update_bv_dec:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail2_values_Bitvector_a v n b=  (update_list F (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) n b))`;
+
+
+val _ = Define `
+ ((subrange_bv_inc:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v i j=  (subrange_list T  (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) i j))`;
+
+val _ = Define `
+ ((subrange_bv_dec:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v i j=  (subrange_list F (
+  dict_Sail2_values_Bitvector_a.bits_of_method v) i j))`;
+
+
+val _ = Define `
+ ((update_subrange_bv_inc:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v'=  (update_subrange_list T  (
+  dict_Sail2_values_Bitvector_b.bits_of_method v) i j (dict_Sail2_values_Bitvector_a.bits_of_method v')))`;
+
+val _ = Define `
+ ((update_subrange_bv_dec:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v'=  (update_subrange_list F (
+  dict_Sail2_values_Bitvector_b.bits_of_method v) i j (dict_Sail2_values_Bitvector_a.bits_of_method v')))`;
+
+
+(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
+val _ = Define `
+ ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a n v=  (extz_bits n (
+  dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
+val _ = Define `
+ ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a n v=  (exts_bits n (
+  dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*)
+val _ = Define `
+ ((string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail2_values_Bitvector_a v=  (show_bitlist (
+  dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*** Bytes and addresses *)
+
+val _ = type_abbrev( "memory_byte" , ``: bitU list``);
+
+(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*)
+ val _ = Define `
+ ((byte_chunks:'a list ->(('a list)list)option) bs=  ((case bs of
+    [] => SOME []
+  | a::b::c::d::e::f::g::h::rest =>
+     OPTION_BIND (byte_chunks rest) (\ rest .  SOME ([a;b;c;d;e;f;g;h] :: rest))
+  | _ => NONE
+)))`;
+
+
+(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*)
+val _ = Define `
+ ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail2_values_Bitvector_a bs=  (byte_chunks (
+  dict_Sail2_values_Bitvector_a.bits_of_method bs)))`;
+
+
+(*val bits_of_bytes : list memory_byte -> list bitU*)
+val _ = Define `
+ ((bits_of_bytes:((bitU)list)list ->(bitU)list) bs=  (FLAT (MAP (\ v. MAP (\ b. b) v) bs)))`;
+
+
+val _ = Define `
+ ((mem_bytes_of_bits:'a Bitvector_class -> 'a ->(((bitU)list)list)option)dict_Sail2_values_Bitvector_a bs=  (OPTION_MAP REVERSE (bytes_of_bits 
+  dict_Sail2_values_Bitvector_a bs)))`;
+
+val _ = Define `
+ ((bits_of_mem_bytes:((bitU)list)list ->(bitU)list) bs=  (bits_of_bytes (REVERSE bs)))`;
+
+
+(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+let bitv_of_byte_lifteds v =
+  foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+let bitv_of_bytes v =
+  foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+let byte_lifteds_of_bitv bits =
+  let bits = List.map bit_lifted_of_bitU bits in
+  byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+let bytes_of_bitv bits =
+  let bits = List.map bit_of_bitU bits in
+  bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+let address_lifted_of_bitv v =
+  let byte_lifteds = byte_lifteds_of_bitv v in
+  let maybe_address_integer =
+    match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+    | Just bs -> Just (integer_of_byte_list bs)
+    | _ -> Nothing
+    end in
+  Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+let address_of_bitv v =
+  let bytes = bytes_of_bitv v in
+  address_of_byte_list bytes*)
+
+ val reverse_endianness_list_defn = Hol_defn "reverse_endianness_list" `
+ ((reverse_endianness_list:'a list -> 'a list) bits=
+   (if LENGTH bits <=( 8 : num) then bits else
+    reverse_endianness_list (drop_list(( 8 : int)) bits) ++ take_list(( 8 : int)) bits))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn reverse_endianness_list_defn;
+
+
+(*** Registers *)
+
+(*type register_field = string
+type register_field_index = string * (integer * integer) (* name, start and end *)
+
+type register =
+  | Register of string * (* name *)
+                integer * (* length *)
+                integer * (* start index *)
+                bool * (* is increasing *)
+                  list register_field_index
+  | UndefinedRegister of integer (* length *)
+  | RegisterPair of register * register*)
+
+val _ = Hol_datatype `
+(* ( 'a_regstate, 'b_regval, 'c_a) *) register_ref =
+  <| name : string;
+     (*is_inc : bool;*)
+     read_from :'a_regstate -> 'c_a;
+     write_to :'c_a -> 'a_regstate -> 'a_regstate;
+     of_regval :'b_regval -> 'c_a option;
+     regval_of :'c_a -> 'b_regval |>`;
+
+
+(* Register accessors: pair of functions for reading and writing register values *)
+val _ = type_abbrev((* ( 'regstate, 'regval) *) "register_accessors" , ``:
+  ((string -> 'regstate ->  'regval option) #
+   (string -> 'regval -> 'regstate ->  'regstate option))``);
+
+val _ = Hol_datatype `
+(* ( 'a_regtype, 'b_a) *) field_ref =
+  <| field_name : string;
+     field_start : int;
+     field_is_inc : bool;
+     get_field :'a_regtype -> 'b_a;
+     set_field :'a_regtype -> 'b_a -> 'a_regtype |>`;
+
+
+(*let name_of_reg = function
+  | Register name _ _ _ _ -> name
+  | UndefinedRegister _ -> failwith "name_of_reg UndefinedRegister"
+  | RegisterPair _ _ -> failwith "name_of_reg RegisterPair"
+end
+
+let size_of_reg = function
+  | Register _ size _ _ _ -> size
+  | UndefinedRegister size -> size
+  | RegisterPair _ _ -> failwith "size_of_reg RegisterPair"
+end
+
+let start_of_reg = function
+  | Register _ _ start _ _ -> start
+  | UndefinedRegister _ -> failwith "start_of_reg UndefinedRegister"
+  | RegisterPair _ _ -> failwith "start_of_reg RegisterPair"
+end
+
+let is_inc_of_reg = function
+  | Register _ _ _ is_inc _ -> is_inc
+  | UndefinedRegister _ -> failwith "is_inc_of_reg UndefinedRegister"
+  | RegisterPair _ _ -> failwith "in_inc_of_reg RegisterPair"
+end
+
+let dir_of_reg = function
+  | Register _ _ _ is_inc _ -> dir_of_bool is_inc
+  | UndefinedRegister _ -> failwith "dir_of_reg UndefinedRegister"
+  | RegisterPair _ _ -> failwith "dir_of_reg RegisterPair"
+end
+
+let size_of_reg_nat reg = natFromInteger (size_of_reg reg)
+let start_of_reg_nat reg = natFromInteger (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> maybe (integer * integer)
+let rec register_field_indices_aux register rfield =
+  match register with
+  | Register _ _ _ _ rfields -> List.lookup rfield rfields
+  | RegisterPair r1 r2 ->
+      let m_indices = register_field_indices_aux r1 rfield in
+      if isJust m_indices then m_indices else register_field_indices_aux r2 rfield
+  | UndefinedRegister _ -> Nothing
+  end
+
+val register_field_indices : register -> register_field -> integer * integer
+let register_field_indices register rfield =
+  match register_field_indices_aux register rfield with
+  | Just indices -> indices
+  | Nothing -> failwith "Invalid register/register-field combination"
+  end
+
+let register_field_indices_nat reg regfield=
+  let (i,j) = register_field_indices reg regfield in
+  (natFromInteger i,natFromInteger j)*)
+
+(*let rec external_reg_value reg_name v =
+  let (internal_start, external_start, direction) =
+    match reg_name with
+     | Reg _ start size dir ->
+        (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+     | Reg_slice _ reg_start dir (slice_start, _) ->
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_field _ reg_start dir _ (slice_start, _) ->
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_f_slice _ reg_start dir _ _ (slice_start, _) ->
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     end in
+  let bits = bit_lifteds_of_bitv v in
+  <| rv_bits           = bits;
+     rv_dir            = direction;
+     rv_start          = external_start;
+     rv_start_internal = internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+let internal_reg_value v =
+  List.map bitU_of_bit_lifted v.rv_bits
+         (*(integerFromNat v.rv_start_internal)
+         (v.rv_dir = D_increasing)*)
+
+
+let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) =
+  match d with
+  (*This is the case the thread/concurrecny model expects, so no change needed*)
+  | D_increasing -> (i,j)
+  | D_decreasing -> let slice_i = start - i in
+                    let slice_j = (i - j) + slice_i in
+                    (slice_i,slice_j)
+  end *)
+
+(* TODO
+let external_reg_whole r =
+  Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc)
+
+let external_reg_slice r (i,j) =
+  let start = natFromInteger r.start in
+  let dir = dir_of_bool r.is_inc in
+  Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+let external_reg_field_whole reg rfield =
+  let (m,n) = register_field_indices_nat reg rfield in
+  let start = start_of_reg_nat reg in
+  let dir = dir_of_reg reg in
+  Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+let external_reg_field_slice reg rfield (i,j) =
+  let (m,n) = register_field_indices_nat reg rfield in
+  let start = start_of_reg_nat reg in
+  let dir = dir_of_reg reg in
+  Reg_f_slice (name_of_reg reg) start dir rfield
+              (external_slice dir start (m,n))
+              (external_slice dir start (i,j))*)
+
+(*val external_mem_value : list bitU -> memory_value
+let external_mem_value v =
+  byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+let internal_mem_value bytes =
+  List.reverse bytes $> bitv_of_byte_lifteds*)
+
+
+(*val foreach : forall 'a 'vars.
+  (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*)
+ val _ = Define `
+ ((foreach:'a list -> 'vars ->('a -> 'vars -> 'vars) -> 'vars) l vars body=
+   ((case l of
+      [] => vars
+    | (x :: xs) => foreach xs (body x vars) body
+  )))`;
+
+
+(*val index_list : integer -> integer -> integer -> list integer*)
+ val index_list_defn = Hol_defn "index_list" `
+ ((index_list:int -> int -> int ->(int)list) from to step=
+   (if ((step >( 0 : int)) /\ (from <= to)) \/ ((step <( 0 : int)) /\ (to <= from)) then
+    from :: index_list (from + step) to step
+  else []))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn index_list_defn;
+
+(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
+ val while_defn = Hol_defn "while" `
+ ((while:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body=
+   (if cond vars then while (body vars) cond body else vars))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn while_defn;
+
+(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
+ val until_defn = Hol_defn "until" `
+ ((until:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body=
+   (let vars = (body vars) in
+  if cond vars then vars else until (body vars) cond body))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn until_defn;
+
+
+(* convert numbers unsafely to naturals *)
+
+val _ = Hol_datatype `
+(*  'a *) ToNatural_class= <| toNatural_method : 'a -> num |>`;
+
+(* eta-expanded for Isabelle output, otherwise it breaks *)
+val _ = Define `
+((instance_Sail2_values_ToNatural_Num_integer_dict:(int)ToNatural_class)= (<|
+
+  toNatural_method := (\ n .  Num (ABS n))|>))`;
+
+val _ = Define `
+((instance_Sail2_values_ToNatural_Num_int_dict:(int)ToNatural_class)= (<|
+
+  toNatural_method := (\ n .  ((Num (ABS n)):num))|>))`;
+
+val _ = Define `
+((instance_Sail2_values_ToNatural_nat_dict:(num)ToNatural_class)= (<|
+
+  toNatural_method := (\ n .  ( n:num))|>))`;
+
+val _ = Define `
+((instance_Sail2_values_ToNatural_Num_natural_dict:(num)ToNatural_class)= (<|
+
+  toNatural_method := (\ n .  n)|>))`;
+
+
+val _ = Define `
+ ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail2_values_ToNatural_a dict_Sail2_values_ToNatural_b dict_Sail2_values_ToNatural_c dict_Sail2_values_ToNatural_d dict_Sail2_values_ToNatural_e (n1,n2,n3,n4,n5)=
+   (dict_Sail2_values_ToNatural_d.toNatural_method n1, dict_Sail2_values_ToNatural_c.toNatural_method n2, dict_Sail2_values_ToNatural_b.toNatural_method n3, dict_Sail2_values_ToNatural_a.toNatural_method n4, dict_Sail2_values_ToNatural_e.toNatural_method n5))`;
+
+
+(* Let the following types be generated by Sail per spec, using either bitlists
+   or machine words as bitvector representation *)
+(*type regfp =
+  | RFull of (string)
+  | RSlice of (string * integer * integer)
+  | RSliceBit of (string * integer)
+  | RField of (string * string)
+
+type niafp =
+  | NIAFP_successor
+  | NIAFP_concrete_address of vector bitU
+  | NIAFP_indirect_address
+
+(* only for MIPS *)
+type diafp =
+  | DIAFP_none
+  | DIAFP_concrete of vector bitU
+  | DIAFP_reg of regfp
+
+let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function
+  | RFull name ->
+     let (start,length,direction,_) = reg_info name Nothing in
+     Reg name start length direction
+  | RSlice (name,i,j) ->
+     let i = natFromInteger i in
+     let j = natFromInteger j in
+     let (start,length,direction,_) = reg_info name Nothing in
+     let slice = external_slice direction start (i,j) in
+     Reg_slice name start direction slice
+  | RSliceBit (name,i) ->
+     let i = natFromInteger i in
+     let (start,length,direction,_) = reg_info name Nothing in
+     let slice = external_slice direction start (i,i) in
+     Reg_slice name start direction slice
+  | RField (name,field_name) ->
+     let (start,length,direction,span) = reg_info name (Just field_name) in
+     let slice = external_slice direction start span in
+     Reg_field name start direction field_name slice
+end
+
+let niafp_to_nia reginfo = function
+  | NIAFP_successor -> NIA_successor
+  | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v)
+  | NIAFP_indirect_address -> NIA_indirect_address
+end
+
+let diafp_to_dia reginfo = function
+  | DIAFP_none -> DIA_none
+  | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v)
+  | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r)
+end
+*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml b/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml
deleted file mode 100644
index 5a119d61..00000000
--- a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml
+++ /dev/null
@@ -1,473 +0,0 @@
-(*Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "sail_instr_kinds"
-
-(*========================================================================*)
-(*     Sail                                                               *)
-(*                                                                        *)
-(*  Copyright (c) 2013-2017                                               *)
-(*    Kathyrn Gray                                                        *)
-(*    Shaked Flur                                                         *)
-(*    Stephen Kell                                                        *)
-(*    Gabriel Kerneis                                                     *)
-(*    Robert Norton-Wright                                                *)
-(*    Christopher Pulte                                                   *)
-(*    Peter Sewell                                                        *)
-(*    Alasdair Armstrong                                                  *)
-(*    Brian Campbell                                                      *)
-(*    Thomas Bauereiss                                                    *)
-(*    Anthony Fox                                                         *)
-(*    Jon French                                                          *)
-(*    Dominic Mulligan                                                    *)
-(*    Stephen Kell                                                        *)
-(*    Mark Wassell                                                        *)
-(*                                                                        *)
-(*  All rights reserved.                                                  *)
-(*                                                                        *)
-(*  This software was developed by the University of Cambridge Computer   *)
-(*  Laboratory as part of the Rigorous Engineering of Mainstream Systems  *)
-(*  (REMS) project, funded by EPSRC grant EP/K008528/1.                   *)
-(*                                                                        *)
-(*  Redistribution and use in source and binary forms, with or without    *)
-(*  modification, are permitted provided that the following conditions    *)
-(*  are met:                                                              *)
-(*  1. Redistributions of source code must retain the above copyright     *)
-(*     notice, this list of conditions and the following disclaimer.      *)
-(*  2. Redistributions in binary form must reproduce the above copyright  *)
-(*     notice, this list of conditions and the following disclaimer in    *)
-(*     the documentation and/or other materials provided with the         *)
-(*     distribution.                                                      *)
-(*                                                                        *)
-(*  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''    *)
-(*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     *)
-(*  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A       *)
-(*  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR   *)
-(*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,          *)
-(*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      *)
-(*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF      *)
-(*  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   *)
-(*  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,    *)
-(*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    *)
-(*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    *)
-(*  SUCH DAMAGE.                                                          *)
-(*========================================================================*)
-
-(*open import Pervasives_extra*)
-
-
-val _ = Hol_datatype `
-(*  'a *) EnumerationType_class= <|
-  toNat_method : 'a -> num
-|>`;
-
-
-
-(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*)
-val _ = Define `
- ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> ordering)dict_Sail_instr_kinds_EnumerationType_a e1 e2=
-   (genericCompare (<) (=) (
-  dict_Sail_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail_instr_kinds_EnumerationType_a.toNat_method e2)))`;
-
-
-
-val _ = Define `
-((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a Ord_class)dict_Sail_instr_kinds_EnumerationType_a= (<|
-
-  compare_method := 
-  (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a);
-
-  isLess_method := (\  r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LESS);
-
-  isLessEqual_method := (\ r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> GREATER);
-
-  isGreater_method := (\  r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GREATER);
-
-  isGreaterEqual_method := (\ r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> LESS)|>))`;
-
-
-
-(* Data structures for building up instructions *)
-
-(* careful: changes in the read/write/barrier kinds have to be
-   reflected in deep_shallow_convert *)
-val _ = Hol_datatype `
- read_kind =
-  (* common reads *)
-    Read_plain
-  (* Power reads *)
-  | Read_reserve
-  (* AArch64 reads *)
-  | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
-  (* RISC-V reads *)
-  | Read_RISCV_acquire  | Read_RISCV_strong_acquire
-  | Read_RISCV_reserved | Read_RISCV_reserved_acquire
-  | Read_RISCV_reserved_strong_acquire
-  (* x86 reads *)
-  | Read_X86_locked`;
- (* the read part of a lock'd instruction (rmw) *)
-
-val _ = Define `
-((instance_Show_Show_Sail_instr_kinds_read_kind_dict:(read_kind)Show_class)= (<|
-
-  show_method := (\x .  
-  (case x of
-        Read_plain => "Read_plain"
-    | Read_reserve => "Read_reserve"
-    | Read_acquire => "Read_acquire"
-    | Read_exclusive => "Read_exclusive"
-    | Read_exclusive_acquire => "Read_exclusive_acquire"
-    | Read_stream => "Read_stream"
-    | Read_RISCV_acquire => "Read_RISCV_acquire"
-    | Read_RISCV_strong_acquire => "Read_RISCV_strong_acquire"
-    | Read_RISCV_reserved => "Read_RISCV_reserved"
-    | Read_RISCV_reserved_acquire => "Read_RISCV_reserved_acquire"
-    | Read_RISCV_reserved_strong_acquire => "Read_RISCV_reserved_strong_acquire"
-    | Read_X86_locked => "Read_X86_locked"
-  ))|>))`;
-
-
-val _ = Hol_datatype `
- write_kind =
-  (* common writes *)
-    Write_plain
-  (* Power writes *)
-  | Write_conditional
-  (* AArch64 writes *)
-  | Write_release | Write_exclusive | Write_exclusive_release
-  (* RISC-V *)
-  | Write_RISCV_release     | Write_RISCV_strong_release
-  | Write_RISCV_conditional | Write_RISCV_conditional_release
-  | Write_RISCV_conditional_strong_release
-  (* x86 writes *)
-  | Write_X86_locked`;
- (* the write part of a lock'd instruction (rmw) *)
-
-val _ = Define `
-((instance_Show_Show_Sail_instr_kinds_write_kind_dict:(write_kind)Show_class)= (<|
-
-  show_method := (\x .  
-  (case x of
-        Write_plain => "Write_plain"
-    | Write_conditional => "Write_conditional"
-    | Write_release => "Write_release"
-    | Write_exclusive => "Write_exclusive"
-    | Write_exclusive_release => "Write_exclusive_release"
-    | Write_RISCV_release => "Write_RISCV_release"
-    | Write_RISCV_strong_release => "Write_RISCV_strong_release"
-    | Write_RISCV_conditional => "Write_RISCV_conditional"
-    | Write_RISCV_conditional_release => "Write_RISCV_conditional_release"
-    | Write_RISCV_conditional_strong_release => "Write_RISCV_conditional_strong_release"
-    | Write_X86_locked => "Write_X86_locked"
-  ))|>))`;
-
-
-val _ = Hol_datatype `
- barrier_kind =
-  (* Power barriers *)
-  Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
-  (* AArch64 barriers *)
-  | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
-  | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
-  | Barrier_TM_COMMIT
-  (* MIPS barriers *)
-  | Barrier_MIPS_SYNC
-  (* RISC-V barriers *)
-  | Barrier_RISCV_rw_rw
-  | Barrier_RISCV_r_rw
-  | Barrier_RISCV_r_r
-  | Barrier_RISCV_rw_w
-  | Barrier_RISCV_w_w
-  | Barrier_RISCV_i
-  (* X86 *)
-  | Barrier_x86_MFENCE`;
-
-
-
-val _ = Define `
-((instance_Show_Show_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)Show_class)= (<|
-
-  show_method := (\x .  
-  (case x of
-        Barrier_Sync => "Barrier_Sync"
-    | Barrier_LwSync => "Barrier_LwSync"
-    | Barrier_Eieio => "Barrier_Eieio"
-    | Barrier_Isync => "Barrier_Isync"
-    | Barrier_DMB => "Barrier_DMB"
-    | Barrier_DMB_ST => "Barrier_DMB_ST"
-    | Barrier_DMB_LD => "Barrier_DMB_LD"
-    | Barrier_DSB => "Barrier_DSB"
-    | Barrier_DSB_ST => "Barrier_DSB_ST"
-    | Barrier_DSB_LD => "Barrier_DSB_LD"
-    | Barrier_ISB => "Barrier_ISB"
-    | Barrier_TM_COMMIT => "Barrier_TM_COMMIT"
-    | Barrier_MIPS_SYNC => "Barrier_MIPS_SYNC"
-    | Barrier_RISCV_rw_rw => "Barrier_RISCV_rw_rw"
-    | Barrier_RISCV_r_rw => "Barrier_RISCV_r_rw"
-    | Barrier_RISCV_r_r => "Barrier_RISCV_r_r"
-    | Barrier_RISCV_rw_w => "Barrier_RISCV_rw_w"
-    | Barrier_RISCV_w_w => "Barrier_RISCV_w_w"
-    | Barrier_RISCV_i => "Barrier_RISCV_i"
-    | Barrier_x86_MFENCE => "Barrier_x86_MFENCE"
-  ))|>))`;
-
-
-val _ = Hol_datatype `
- trans_kind =
-  (* AArch64 *)
-    Transaction_start | Transaction_commit | Transaction_abort`;
-
-
-val _ = Define `
-((instance_Show_Show_Sail_instr_kinds_trans_kind_dict:(trans_kind)Show_class)= (<|
-
-  show_method := (\x .  
-  (case x of
-        Transaction_start => "Transaction_start"
-    | Transaction_commit => "Transaction_commit"
-    | Transaction_abort => "Transaction_abort"
-  ))|>))`;
-
-
-val _ = Hol_datatype `
- instruction_kind =
-    IK_barrier   of barrier_kind
-  | IK_mem_read  of read_kind
-  | IK_mem_write of write_kind
-  | IK_mem_rmw   of (read_kind # write_kind)
-  | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
-  indirect/computed-branch (single nia of kind NIA_indirect_address)
-  and branch/jump (single nia of kind NIA_concrete_address) *)
-  | IK_trans     of trans_kind
-  | IK_simple`;
-
-
-
-val _ = Define `
-((instance_Show_Show_Sail_instr_kinds_instruction_kind_dict:(instruction_kind)Show_class)= (<|
-
-  show_method := (\x .  
-  (case x of
-        IK_barrier barrier_kind => STRCAT "IK_barrier "
-                                     (((\x .  (case x of
-                                                    Barrier_Sync => "Barrier_Sync"
-                                                | Barrier_LwSync => "Barrier_LwSync"
-                                                | Barrier_Eieio => "Barrier_Eieio"
-                                                | Barrier_Isync => "Barrier_Isync"
-                                                | Barrier_DMB => "Barrier_DMB"
-                                                | Barrier_DMB_ST => "Barrier_DMB_ST"
-                                                | Barrier_DMB_LD => "Barrier_DMB_LD"
-                                                | Barrier_DSB => "Barrier_DSB"
-                                                | Barrier_DSB_ST => "Barrier_DSB_ST"
-                                                | Barrier_DSB_LD => "Barrier_DSB_LD"
-                                                | Barrier_ISB => "Barrier_ISB"
-                                                | Barrier_TM_COMMIT => 
-                                              "Barrier_TM_COMMIT"
-                                                | Barrier_MIPS_SYNC => 
-                                              "Barrier_MIPS_SYNC"
-                                                | Barrier_RISCV_rw_rw => 
-                                              "Barrier_RISCV_rw_rw"
-                                                | Barrier_RISCV_r_rw => 
-                                              "Barrier_RISCV_r_rw"
-                                                | Barrier_RISCV_r_r => 
-                                              "Barrier_RISCV_r_r"
-                                                | Barrier_RISCV_rw_w => 
-                                              "Barrier_RISCV_rw_w"
-                                                | Barrier_RISCV_w_w => 
-                                              "Barrier_RISCV_w_w"
-                                                | Barrier_RISCV_i => 
-                                              "Barrier_RISCV_i"
-                                                | Barrier_x86_MFENCE => 
-                                              "Barrier_x86_MFENCE"
-                                              )) barrier_kind))
-    | IK_mem_read read_kind => STRCAT "IK_mem_read "
-                                 (((\x .  (case x of
-                                                Read_plain => "Read_plain"
-                                            | Read_reserve => "Read_reserve"
-                                            | Read_acquire => "Read_acquire"
-                                            | Read_exclusive => "Read_exclusive"
-                                            | Read_exclusive_acquire => 
-                                          "Read_exclusive_acquire"
-                                            | Read_stream => "Read_stream"
-                                            | Read_RISCV_acquire => "Read_RISCV_acquire"
-                                            | Read_RISCV_strong_acquire => 
-                                          "Read_RISCV_strong_acquire"
-                                            | Read_RISCV_reserved => 
-                                          "Read_RISCV_reserved"
-                                            | Read_RISCV_reserved_acquire => 
-                                          "Read_RISCV_reserved_acquire"
-                                            | Read_RISCV_reserved_strong_acquire => 
-                                          "Read_RISCV_reserved_strong_acquire"
-                                            | Read_X86_locked => "Read_X86_locked"
-                                          )) read_kind))
-    | IK_mem_write write_kind => STRCAT "IK_mem_write "
-                                   (((\x .  (case x of
-                                                  Write_plain => "Write_plain"
-                                              | Write_conditional => 
-                                            "Write_conditional"
-                                              | Write_release => "Write_release"
-                                              | Write_exclusive => "Write_exclusive"
-                                              | Write_exclusive_release => 
-                                            "Write_exclusive_release"
-                                              | Write_RISCV_release => 
-                                            "Write_RISCV_release"
-                                              | Write_RISCV_strong_release => 
-                                            "Write_RISCV_strong_release"
-                                              | Write_RISCV_conditional => 
-                                            "Write_RISCV_conditional"
-                                              | Write_RISCV_conditional_release => 
-                                            "Write_RISCV_conditional_release"
-                                              | Write_RISCV_conditional_strong_release => 
-                                            "Write_RISCV_conditional_strong_release"
-                                              | Write_X86_locked => "Write_X86_locked"
-                                            )) write_kind))
-    | IK_mem_rmw (r, w) => STRCAT "IK_mem_rmw "
-                             (STRCAT
-                                (((\x .  (case x of
-                                               Read_plain => "Read_plain"
-                                           | Read_reserve => "Read_reserve"
-                                           | Read_acquire => "Read_acquire"
-                                           | Read_exclusive => "Read_exclusive"
-                                           | Read_exclusive_acquire => 
-                                         "Read_exclusive_acquire"
-                                           | Read_stream => "Read_stream"
-                                           | Read_RISCV_acquire => "Read_RISCV_acquire"
-                                           | Read_RISCV_strong_acquire => 
-                                         "Read_RISCV_strong_acquire"
-                                           | Read_RISCV_reserved => "Read_RISCV_reserved"
-                                           | Read_RISCV_reserved_acquire => 
-                                         "Read_RISCV_reserved_acquire"
-                                           | Read_RISCV_reserved_strong_acquire => 
-                                         "Read_RISCV_reserved_strong_acquire"
-                                           | Read_X86_locked => "Read_X86_locked"
-                                         )) r))
-                                (STRCAT " "
-                                   (((\x .  (case x of
-                                                  Write_plain => "Write_plain"
-                                              | Write_conditional => 
-                                            "Write_conditional"
-                                              | Write_release => "Write_release"
-                                              | Write_exclusive => "Write_exclusive"
-                                              | Write_exclusive_release => 
-                                            "Write_exclusive_release"
-                                              | Write_RISCV_release => 
-                                            "Write_RISCV_release"
-                                              | Write_RISCV_strong_release => 
-                                            "Write_RISCV_strong_release"
-                                              | Write_RISCV_conditional => 
-                                            "Write_RISCV_conditional"
-                                              | Write_RISCV_conditional_release => 
-                                            "Write_RISCV_conditional_release"
-                                              | Write_RISCV_conditional_strong_release => 
-                                            "Write_RISCV_conditional_strong_release"
-                                              | Write_X86_locked => "Write_X86_locked"
-                                            )) w))))
-    | IK_branch => "IK_branch"
-    | IK_trans trans_kind => STRCAT "IK_trans "
-                               (((\x .  (case x of
-                                              Transaction_start => "Transaction_start"
-                                          | Transaction_commit => "Transaction_commit"
-                                          | Transaction_abort => "Transaction_abort"
-                                        )) trans_kind))
-    | IK_simple => "IK_simple"
-  ))|>))`;
-
-
-
-val _ = Define `
- ((read_is_exclusive:read_kind -> bool)= 
-  (\x .  (case x of
-               Read_plain => F
-           | Read_reserve => T
-           | Read_acquire => F
-           | Read_exclusive => T
-           | Read_exclusive_acquire => T
-           | Read_stream => F
-           | Read_RISCV_acquire => F
-           | Read_RISCV_strong_acquire => F
-           | Read_RISCV_reserved => T
-           | Read_RISCV_reserved_acquire => T
-           | Read_RISCV_reserved_strong_acquire => T
-           | Read_X86_locked => T
-         )))`;
-
-
-
-
-val _ = Define `
-((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict:(read_kind)EnumerationType_class)= (<|
-
-  toNat_method := (\x .  
-  (case x of
-        Read_plain =>( 0 : num)
-    | Read_reserve =>( 1 : num)
-    | Read_acquire =>( 2 : num)
-    | Read_exclusive =>( 3 : num)
-    | Read_exclusive_acquire =>( 4 : num)
-    | Read_stream =>( 5 : num)
-    | Read_RISCV_acquire =>( 6 : num)
-    | Read_RISCV_strong_acquire =>( 7 : num)
-    | Read_RISCV_reserved =>( 8 : num)
-    | Read_RISCV_reserved_acquire =>( 9 : num)
-    | Read_RISCV_reserved_strong_acquire =>( 10 : num)
-    | Read_X86_locked =>( 11 : num)
-  ))|>))`;
-
-
-val _ = Define `
-((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict:(write_kind)EnumerationType_class)= (<|
-
-  toNat_method := (\x .  
-  (case x of
-        Write_plain =>( 0 : num)
-    | Write_conditional =>( 1 : num)
-    | Write_release =>( 2 : num)
-    | Write_exclusive =>( 3 : num)
-    | Write_exclusive_release =>( 4 : num)
-    | Write_RISCV_release =>( 5 : num)
-    | Write_RISCV_strong_release =>( 6 : num)
-    | Write_RISCV_conditional =>( 7 : num)
-    | Write_RISCV_conditional_release =>( 8 : num)
-    | Write_RISCV_conditional_strong_release =>( 9 : num)
-    | Write_X86_locked =>( 10 : num)
-  ))|>))`;
-
-
-val _ = Define `
-((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)EnumerationType_class)= (<|
-
-  toNat_method := (\x .  
-  (case x of
-        Barrier_Sync =>( 0 : num)
-    | Barrier_LwSync =>( 1 : num)
-    | Barrier_Eieio =>( 2 : num)
-    | Barrier_Isync =>( 3 : num)
-    | Barrier_DMB =>( 4 : num)
-    | Barrier_DMB_ST =>( 5 : num)
-    | Barrier_DMB_LD =>( 6 : num)
-    | Barrier_DSB =>( 7 : num)
-    | Barrier_DSB_ST =>( 8 : num)
-    | Barrier_DSB_LD =>( 9 : num)
-    | Barrier_ISB =>( 10 : num)
-    | Barrier_TM_COMMIT =>( 11 : num)
-    | Barrier_MIPS_SYNC =>( 12 : num)
-    | Barrier_RISCV_rw_rw =>( 13 : num)
-    | Barrier_RISCV_r_rw =>( 14 : num)
-    | Barrier_RISCV_r_r =>( 15 : num)
-    | Barrier_RISCV_rw_w =>( 16 : num)
-    | Barrier_RISCV_w_w =>( 17 : num)
-    | Barrier_RISCV_i =>( 18 : num)
-    | Barrier_x86_MFENCE =>( 19 : num)
-  ))|>))`;
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml
deleted file mode 100644
index 78109827..00000000
--- a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml
+++ /dev/null
@@ -1,327 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/sail_operators.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "sail_operators"
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_values*)
-
-(*** Bit vector operations *)
-
-(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*)
-val _ = Define `
- ((concat_bv:'a Bitvector_class -> 'b Bitvector_class -> 'a -> 'b ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r=  (
-  dict_Sail_values_Bitvector_a.bits_of_method l ++ dict_Sail_values_Bitvector_b.bits_of_method r))`;
-
-
-(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*)
-val _ = Define `
- ((cons_bv:'a Bitvector_class -> bitU -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a b v=  (b :: 
-  dict_Sail_values_Bitvector_a.bits_of_method v))`;
-
-
-(*val cast_unit_bv : bitU -> list bitU*)
-val _ = Define `
- ((cast_unit_bv:bitU ->(bitU)list) b=  ([b]))`;
-
-
-(*val bv_of_bit : integer -> bitU -> list bitU*)
-val _ = Define `
- ((bv_of_bit:int -> bitU ->(bitU)list) len b=  (extz_bits len [b]))`;
-
-
-val _ = Define `
- ((most_significant:'a Bitvector_class -> 'a -> bitU)dict_Sail_values_Bitvector_a v=  ((case  
-  dict_Sail_values_Bitvector_a.bits_of_method v of
-    b :: _ => b
-  | _ => B0 (* Treat empty bitvector as all zeros *)
-  )))`;
-
-
-val _ = Define `
- ((get_max_representable_in:bool -> int -> int) sign (n : int) : int=
-   (if (n =( 64 : int)) then (case sign of   T => max_64 | F => max_64u )
-  else if (n=( 32 : int)) then (case sign of   T => max_32 | F => max_32u )
-  else if (n=( 8 : int)) then max_8
-  else if (n=( 5 : int)) then max_5
-  else (case sign of   T => (( 2 : int))** ((Num (ABS (I n))) -( 1 : num))
-                       | F => (( 2 : int))** (Num (ABS (I n)))
-       )))`;
-
-
-val _ = Define `
- ((get_min_representable_in:'a -> int -> int) _ (n : int) : int=
-   (if n =( 64 : int) then min_64
-  else if n =( 32 : int) then min_32
-  else if n =( 8 : int) then min_8
-  else if n =( 5 : int) then min_5
-  else( 0 : int) - ((( 2 : int))** (Num (ABS (I n))))))`;
-
-
-(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
-val _ = Define `
- ((arith_op_bv_int:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail_values_Bitvector_a op sign l r=
-   (let r' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r) in  dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l r'))`;
-
-
-(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
-val _ = Define `
- ((arith_op_int_bv:'a Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail_values_Bitvector_a op sign l r=
-   (let l' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method r) l) in  dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l' r))`;
-
-
-val _ = Define `
- ((arith_op_bv_bool:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a op sign l r=  (arith_op_bv_int 
-  dict_Sail_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`;
-
-val _ = Define `
- ((arith_op_bv_bit:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a op sign l r=  (OPTION_MAP (arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a op sign l) (bool_of_bitU r)))`;
-
-
-(* TODO (or just omit and define it per spec if needed)
-val arith_op_overflow_bv : forall 'a. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU)
-let arith_op_overflow_bv op sign size l r =
-  let len = length l in
-  let act_size = len * size in
-  match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with
-    | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) ->
-       let n = op l_sign r_sign in
-       let n_unsign = op l_unsign r_unsign in
-       let correct_size = of_int act_size n in
-       let one_more_size_u = bits_of_int (act_size + 1) n_unsign in
-       let overflow =
-         if n <= get_max_representable_in sign len &&
-              n >= get_min_representable_in sign len
-         then B0 else B1 in
-       let c_out = most_significant one_more_size_u in
-       (correct_size,overflow,c_out)
-    | (_, _, _, _) ->
-       (repeat [BU] act_size, BU, BU)
-  end
-
-let add_overflow_bv = arith_op_overflow_bv integerAdd false 1
-let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1
-let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1
-let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1
-let mult_overflow_bv = arith_op_overflow_bv integerMult false 2
-let mults_overflow_bv = arith_op_overflow_bv integerMult true 2
-
-val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU)
-let arith_op_overflow_bv_bit op sign size l r_bit =
-  let act_size = length l * size in
-  match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with
-    | (Just l', Just l_u, false) ->
-       let (n, nu, changed) = match r_bit with
-         | B1 -> (op l' 1, op l_u 1, true)
-         | B0 -> (l', l_u, false)
-         | BU -> (* unreachable due to check above *)
-            failwith "arith_op_overflow_bv_bit applied to undefined bit"
-         end in
-       let correct_size = of_int act_size n in
-       let one_larger = bits_of_int (act_size + 1) nu in
-       let overflow =
-         if changed
-         then
-           if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
-           then B0 else B1
-         else B0 in
-       (correct_size, overflow, most_significant one_larger)
-    | (_, _, _) ->
-       (repeat [BU] act_size, BU, BU)
-  end
-
-let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1
-let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1
-let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1
-let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*)
-
-val _ = Hol_datatype `
- shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot`;
-
-
-val _ = Define `
- ((invert_shift:shift -> shift)= 
-  (\x .  (case x of
-               LL_shift => RR_shift
-           | RR_shift => LL_shift
-           | RR_shift_arith => LL_shift
-           | LL_rot => RR_rot
-           | RR_rot => LL_rot
-         )))`;
-
-
-(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*)
-val _ = Define `
- ((shift_op_bv:'a Bitvector_class -> shift -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a op v n=
-   (let v = (dict_Sail_values_Bitvector_a.bits_of_method v) in
-  if n =( 0 : int) then v else
-  let (op, n) = (if n >( 0 : int) then (op, n) else (invert_shift op, ~ n)) in
-  (case op of
-    LL_shift =>
-     subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ repeat [B0] n
-  | RR_shift =>
-     repeat [B0] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int))
-  | RR_shift_arith =>
-     repeat [most_significant 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) v] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int))
-  | LL_rot =>
-     subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ subrange_list T v(( 0 : int)) (n -( 1 : int))
-  | RR_rot =>
-     subrange_list F v(( 0 : int)) (n -( 1 : int)) ++ subrange_list F v n (int_of_num (LENGTH v) -( 1 : int))
-  )))`;
-
-
-val _ = Define `
- ((shiftl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a=  (shift_op_bv 
-  dict_Sail_values_Bitvector_a LL_shift))`;
- (*"<<"*)
-val _ = Define `
- ((shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a=  (shift_op_bv 
-  dict_Sail_values_Bitvector_a RR_shift))`;
- (*">>"*)
-val _ = Define `
- ((arith_shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a=  (shift_op_bv 
-  dict_Sail_values_Bitvector_a RR_shift_arith))`;
-
-val _ = Define `
- ((rotl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a=  (shift_op_bv 
-  dict_Sail_values_Bitvector_a LL_rot))`;
- (*"<<<"*)
-val _ = Define `
- ((rotr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a=  (shift_op_bv 
-  dict_Sail_values_Bitvector_a LL_rot))`;
- (*">>>"*)
-
-val _ = Define `
- ((shiftl_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_lsl w (nat_of_int n)))`;
-
-val _ = Define `
- ((shiftr_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_lsr w (nat_of_int n)))`;
-
-val _ = Define `
- ((arith_shiftr_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_asr w (nat_of_int n)))`;
-
-val _ = Define `
- ((rotl_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_rol w (nat_of_int n)))`;
-
-val _ = Define `
- ((rotr_mword:'a words$word -> int -> 'a words$word) w n=  (words$word_ror w (nat_of_int n)))`;
-
-
- val _ = Define `
- ((arith_op_no0:(int -> int -> int) -> int -> int ->(int)option) (op : int -> int -> int) l r=
-   (if r =( 0 : int)
-  then NONE
-  else SOME (op l r)))`;
-
-
-(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*)
-val _ = Define `
- ((arith_op_bv_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r=
-   (OPTION_BIND (int_of_bv 
-  dict_Sail_values_Bitvector_a sign l) (\ l' . 
-  OPTION_BIND (int_of_bv 
-  dict_Sail_values_Bitvector_a sign r) (\ r' . 
-  if r' =( 0 : int) then NONE else SOME (
-  dict_Sail_values_Bitvector_b.of_int_method (dict_Sail_values_Bitvector_a.length_method l * size1) (op l' r'))))))`;
-
-
-val _ = Define `
- ((mod_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b=  (arith_op_bv_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`;
-
-val _ = Define `
- ((quot_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b=  (arith_op_bv_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`;
-
-val _ = Define `
- ((quots_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b=  (arith_op_bv_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot T(( 1 : int))))`;
-
-
-val _ = Define `
- ((mod_mword:'a words$word -> 'a words$word -> 'a words$word)=  words$word_mod)`;
-
-val _ = Define `
- ((quot_mword:'a words$word -> 'a words$word -> 'a words$word)=  words$word_div)`;
-
-val _ = Define `
- ((quots_mword:'a words$word -> 'a words$word -> 'a words$word)=  words$word_quot)`;
-
-
-val _ = Define `
- ((arith_op_bv_int_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r=
-   (arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r)))`;
-
-
-val _ = Define `
- ((quot_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b=  (arith_op_bv_int_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`;
-
-val _ = Define `
- ((mod_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b=  (arith_op_bv_int_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`;
-
-
-val _ = Define `
- ((mod_mword_int:'a words$word -> int -> 'a words$word) l r=  (words$word_mod l (integer_word$i2w r)))`;
-
-val _ = Define `
- ((quot_mword_int:'a words$word -> int -> 'a words$word) l r=  (words$word_div l (integer_word$i2w r)))`;
-
-val _ = Define `
- ((quots_mword_int:'a words$word -> int -> 'a words$word) l r=  (words$word_quot l (integer_word$i2w r)))`;
-
-
-val _ = Define `
- ((replicate_bits_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a v count1=  (repeat (
-  dict_Sail_values_Bitvector_a.bits_of_method v) count1))`;
-
-val _ = Define `
- ((duplicate_bit_bv:'a BitU_class -> 'a -> int ->(bitU)list)dict_Sail_values_BitU_a bit len=  (replicate_bits_bv 
-  (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len))`;
-
-
-(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
-val _ = Define `
- ((eq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r=  (
-  dict_Sail_values_Bitvector_a.bits_of_method l = dict_Sail_values_Bitvector_a.bits_of_method r))`;
-
-
-(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
-val _ = Define `
- ((neq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r=  (~ (eq_bv 
-  dict_Sail_values_Bitvector_a l r)))`;
-
-
-(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
-val _ = Define `
- ((get_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo=
-   (let hi = ((lo + len) -( 1 : int)) in
-  let bs = (bools_of_int (hi +( 1 : int)) n) in  
-  dict_Sail_values_Bitvector_a.of_bools_method (subrange_list F bs hi lo)))`;
-
-
-(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*)
-val _ = Define `
- ((set_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a -> int)dict_Sail_values_Bitvector_a len n lo v=
-   (let hi = ((lo + len) -( 1 : int)) in
-  let bs = (bits_of_int (hi +( 1 : int)) n) in
-  maybe_failwith (signed_of_bits (update_subrange_list F bs hi lo (
-  dict_Sail_values_Bitvector_a.bits_of_method v)))))`;
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml
deleted file mode 100644
index 48f4c8cb..00000000
--- a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml
+++ /dev/null
@@ -1,769 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory sail_operatorsTheory prompt_monadTheory promptTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "sail_operators_bitlists"
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_values*)
-(*open import Sail_operators*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-
-(* Specialisation of operators to bit lists *)
-
-(*val uint_maybe : list bitU -> maybe integer*)
-val _ = Define `
- ((uint_maybe0:(bitU)list ->(int)option) v=  (unsigned_of_bits (MAP (\ b. b) v)))`;
-
-val _ = Define `
- ((uint_fail0:'a Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v=  (state_monad$maybe_failS "uint" (
-  dict_Sail_values_Bitvector_a.unsigned_method v)))`;
-
-val _ = Define `
- ((uint_oracle0:(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v=  (state_monad$bindS
-  (state$bools_of_bits_oracleS v) (\ bs . 
-  state_monad$returnS (int_of_bools F bs))))`;
-
-val _ = Define `
- ((uint:(bitU)list -> int) v=  (maybe_failwith (uint_maybe0 v)))`;
-
-
-(*val sint_maybe : list bitU -> maybe integer*)
-val _ = Define `
- ((sint_maybe0:(bitU)list ->(int)option) v=  (signed_of_bits (MAP (\ b. b) v)))`;
-
-val _ = Define `
- ((sint_fail0:'a Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v=  (state_monad$maybe_failS "sint" (
-  dict_Sail_values_Bitvector_a.signed_method v)))`;
-
-val _ = Define `
- ((sint_oracle0:(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v=  (state_monad$bindS
-  (state$bools_of_bits_oracleS v) (\ bs . 
-  state_monad$returnS (int_of_bools T bs))))`;
-
-val _ = Define `
- ((sint:(bitU)list -> int) v=  (maybe_failwith (sint_maybe0 v)))`;
-
-
-(*val extz_vec : integer -> list bitU -> list bitU*)
-val _ = Define `
- ((extz_vec0:int ->(bitU)list ->(bitU)list)= 
-  (extz_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val exts_vec : integer -> list bitU -> list bitU*)
-val _ = Define `
- ((exts_vec0:int ->(bitU)list ->(bitU)list)= 
-  (exts_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val zero_extend : list bitU -> integer -> list bitU*)
-val _ = Define `
- ((zero_extend0:(bitU)list -> int ->(bitU)list) bits len=  (extz_bits len bits))`;
-
-
-(*val sign_extend : list bitU -> integer -> list bitU*)
-val _ = Define `
- ((sign_extend0:(bitU)list -> int ->(bitU)list) bits len=  (exts_bits len bits))`;
-
-
-(*val zeros : integer -> list bitU*)
-val _ = Define `
- ((zeros0:int ->(bitU)list) len=  (repeat [B0] len))`;
-
-
-(*val vector_truncate : list bitU -> integer -> list bitU*)
-val _ = Define `
- ((vector_truncate0:(bitU)list -> int ->(bitU)list) bs len=  (extz_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) len bs))`;
-
-
-(*val vec_of_bits_maybe    : list bitU -> maybe (list bitU)*)
-(*val vec_of_bits_fail     : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
-(*val vec_of_bits_oracle   : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
-(*val vec_of_bits_failwith : list bitU -> list bitU*)
-(*val vec_of_bits          : list bitU -> list bitU*)
-
-(*val access_vec_inc : list bitU -> integer -> bitU*)
-val _ = Define `
- ((access_vec_inc0:(bitU)list -> int -> bitU)= 
-  (access_bv_inc
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val access_vec_dec : list bitU -> integer -> bitU*)
-val _ = Define `
- ((access_vec_dec0:(bitU)list -> int -> bitU)= 
-  (access_bv_dec
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*)
-val _ = Define `
- ((update_vec_inc0:(bitU)list -> int -> bitU ->(bitU)list)= 
-  (update_bv_inc
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((update_vec_inc_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b=  (SOME (update_vec_inc0 v i b)))`;
-
-val _ = Define `
- ((update_vec_inc_fail0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b=  (state_monad$returnS (update_vec_inc0 v i b)))`;
-
-val _ = Define `
- ((update_vec_inc_oracle0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b=  (state_monad$returnS (update_vec_inc0 v i b)))`;
-
-
-(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*)
-val _ = Define `
- ((update_vec_dec0:(bitU)list -> int -> bitU ->(bitU)list)= 
-  (update_bv_dec
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((update_vec_dec_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b=  (SOME (update_vec_dec0 v i b)))`;
-
-val _ = Define `
- ((update_vec_dec_fail0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b=  (state_monad$returnS (update_vec_dec0 v i b)))`;
-
-val _ = Define `
- ((update_vec_dec_oracle0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b=  (state_monad$returnS (update_vec_dec0 v i b)))`;
-
-
-(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*)
-val _ = Define `
- ((subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list)= 
-  (subrange_bv_inc
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*)
-val _ = Define `
- ((subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list)= 
-  (subrange_bv_dec
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*)
-val _ = Define `
- ((update_subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= 
-  (update_subrange_bv_inc
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*)
-val _ = Define `
- ((update_subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= 
-  (update_subrange_bv_dec
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val concat_vec : list bitU -> list bitU -> list bitU*)
-val _ = Define `
- ((concat_vec0:(bitU)list ->(bitU)list ->(bitU)list)= 
-  (concat_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val cons_vec : bitU -> list bitU -> list bitU*)
-val _ = Define `
- ((cons_vec0:bitU ->(bitU)list ->(bitU)list)= 
-  (cons_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((cons_vec_maybe0:bitU ->(bitU)list ->((bitU)list)option) b v=  (SOME (cons_vec0 b v)))`;
-
-val _ = Define `
- ((cons_vec_fail0:bitU ->(bitU)list -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v=  (state_monad$returnS (cons_vec0 b v)))`;
-
-val _ = Define `
- ((cons_vec_oracle0:bitU ->(bitU)list -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v=  (state_monad$returnS (cons_vec0 b v)))`;
-
-
-(*val cast_unit_vec : bitU -> list bitU*)
-val _ = Define `
- ((cast_unit_vec0:bitU ->(bitU)list)=  cast_unit_bv)`;
-
-val _ = Define `
- ((cast_unit_vec_maybe0:bitU ->((bitU)list)option) b=  (SOME (cast_unit_vec0 b)))`;
-
-val _ = Define `
- ((cast_unit_vec_fail0:bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b=  (state_monad$returnS (cast_unit_vec0 b)))`;
-
-val _ = Define `
- ((cast_unit_vec_oracle0:bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b=  (state_monad$returnS (cast_unit_vec0 b)))`;
-
-
-(*val vec_of_bit : integer -> bitU -> list bitU*)
-val _ = Define `
- ((vec_of_bit0:int -> bitU ->(bitU)list)=  bv_of_bit)`;
-
-val _ = Define `
- ((vec_of_bit_maybe0:int -> bitU ->((bitU)list)option) len b=  (SOME (vec_of_bit0 len b)))`;
-
-val _ = Define `
- ((vec_of_bit_fail0:int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b=  (state_monad$returnS (vec_of_bit0 len b)))`;
-
-val _ = Define `
- ((vec_of_bit_oracle0:int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b=  (state_monad$returnS (vec_of_bit0 len b)))`;
-
-
-(*val msb : list bitU -> bitU*)
-val _ = Define `
- ((msb0:(bitU)list -> bitU)= 
-  (most_significant
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*)
-val _ = Define `
- ((int_of_vec_maybe0:bool ->(bitU)list ->(int)option)= 
-  (int_of_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((int_of_vec_fail0:bool ->(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v=  (state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`;
-
-val _ = Define `
- ((int_of_vec_oracle:bool ->(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v=  (state_monad$bindS (state$bools_of_bits_oracleS v) (\ v .  state_monad$returnS (int_of_bools sign v))))`;
-
-val _ = Define `
- ((int_of_vec0:bool ->(bitU)list -> int) sign v=  (maybe_failwith (int_of_vec_maybe0 sign v)))`;
-
-
-(*val string_of_vec : list bitU -> string*)
-val _ = Define `
- ((string_of_vec0:(bitU)list -> string)= 
-  (string_of_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val and_vec : list bitU -> list bitU -> list bitU*)
-(*val or_vec  : list bitU -> list bitU -> list bitU*)
-(*val xor_vec : list bitU -> list bitU -> list bitU*)
-(*val not_vec : list bitU -> list bitU*)
-val _ = Define `
- ((and_vec0:(bitU)list ->(bitU)list ->(bitU)list)=  (binop_list and_bit))`;
-
-val _ = Define `
- ((or_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (binop_list or_bit))`;
-
-val _ = Define `
- ((xor_vec0:(bitU)list ->(bitU)list ->(bitU)list)=  (binop_list xor_bit))`;
-
-val _ = Define `
- ((not_vec0:(bitU)list ->(bitU)list)=  (MAP not_bit))`;
-
-
-(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*)
-val _ = Define `
- ((arith_op_double_bl:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a op sign l r=
-   (let len =(( 2 : int) * 
-  dict_Sail_values_Bitvector_a.length_method l) in
-  let l' = (if sign then exts_bv 
-  dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in
-  let r' = (if sign then exts_bv 
-  dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in
-  MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`;
-
-
-(*val add_vec   : list bitU -> list bitU -> list bitU*)
-(*val adds_vec  : list bitU -> list bitU -> list bitU*)
-(*val sub_vec   : list bitU -> list bitU -> list bitU*)
-(*val subs_vec  : list bitU -> list bitU -> list bitU*)
-(*val mult_vec  : list bitU -> list bitU -> list bitU*)
-(*val mults_vec : list bitU -> list bitU -> list bitU*)
-val _ = Define `
- ((add_vec0:(bitU)list ->(bitU)list ->(bitU)list)=    (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
-
-val _ = Define `
- ((adds_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
-
-val _ = Define `
- ((sub_vec0:(bitU)list ->(bitU)list ->(bitU)list)=    (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
-
-val _ = Define `
- ((subs_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
-
-val _ = Define `
- ((mult_vec0:(bitU)list ->(bitU)list ->(bitU)list)=   (arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F))`;
-
-val _ = Define `
- ((mults_vec0:(bitU)list ->(bitU)list ->(bitU)list)=  (arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T))`;
-
-
-(*val add_vec_int       : list bitU -> integer -> list bitU*)
-(*val adds_vec_int      : list bitU -> integer -> list bitU*)
-(*val sub_vec_int       : list bitU -> integer -> list bitU*)
-(*val subs_vec_int      : list bitU -> integer -> list bitU*)
-(*val mult_vec_int      : list bitU -> integer -> list bitU*)
-(*val mults_vec_int     : list bitU -> integer -> list bitU*)
-val _ = Define `
- ((add_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`;
-
-val _ = Define `
- ((adds_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`;
-
-val _ = Define `
- ((sub_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`;
-
-val _ = Define `
- ((subs_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`;
-
-val _ = Define `
- ((mult_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
-
-val _ = Define `
- ((mults_vec_int0:(bitU)list -> int ->(bitU)list) l r=  (arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
-
-
-(*val add_int_vec       : integer -> list bitU -> list bitU*)
-(*val adds_int_vec      : integer -> list bitU -> list bitU*)
-(*val sub_int_vec       : integer -> list bitU -> list bitU*)
-(*val subs_int_vec      : integer -> list bitU -> list bitU*)
-(*val mult_int_vec      : integer -> list bitU -> list bitU*)
-(*val mults_int_vec     : integer -> list bitU -> list bitU*)
-val _ = Define `
- ((add_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`;
-
-val _ = Define `
- ((adds_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`;
-
-val _ = Define `
- ((sub_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`;
-
-val _ = Define `
- ((subs_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`;
-
-val _ = Define `
- ((mult_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
-
-val _ = Define `
- ((mults_int_vec0:int ->(bitU)list ->(bitU)list) l r=  (arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
-
-
-(*val add_vec_bit      : list bitU -> bitU -> list bitU*)
-(*val adds_vec_bit     : list bitU -> bitU -> list bitU*)
-(*val sub_vec_bit      : list bitU -> bitU -> list bitU*)
-(*val subs_vec_bit     : list bitU -> bitU -> list bitU*)
-
-val _ = Define `
- ((add_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a       l r=  (arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (+) F l r))`;
-
-val _ = Define `
- ((add_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a  l r=  (arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (+) F l r))`;
-
-val _ = Define `
- ((add_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a   l r=  (state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 
-  dict_Sail_values_Bitvector_a l r)))`;
-
-val _ = Define `
- ((add_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (add_vec_bool0 
-  dict_Sail_values_Bitvector_a l r))))`;
-
-val _ = Define `
- ((add_vec_bit0:(bitU)list -> bitU ->(bitU)list)        l r=  (option_CASE (add_vec_bit_maybe0 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-
-val _ = Define `
- ((adds_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a       l r=  (arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (+) T l r))`;
-
-val _ = Define `
- ((adds_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a  l r=  (arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (+) T l r))`;
-
-val _ = Define `
- ((adds_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a   l r=  (state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 
-  dict_Sail_values_Bitvector_a l r)))`;
-
-val _ = Define `
- ((adds_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (adds_vec_bool0 
-  dict_Sail_values_Bitvector_a l r))))`;
-
-val _ = Define `
- ((adds_vec_bit0:(bitU)list -> bitU ->(bitU)list)        l r=  (option_CASE (adds_vec_bit_maybe0 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-
-val _ = Define `
- ((sub_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a        l r=  (arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (-) F l r))`;
-
-val _ = Define `
- ((sub_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a   l r=  (arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (-) F l r))`;
-
-val _ = Define `
- ((sub_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a    l r=  (state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 
-  dict_Sail_values_Bitvector_a l r)))`;
-
-val _ = Define `
- ((sub_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a  l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (sub_vec_bool0 
-  dict_Sail_values_Bitvector_a l r))))`;
-
-val _ = Define `
- ((sub_vec_bit0:(bitU)list -> bitU ->(bitU)list)         l r=  (option_CASE (sub_vec_bit_maybe0 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-
-val _ = Define `
- ((subs_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a       l r=  (arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (-) T l r))`;
-
-val _ = Define `
- ((subs_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a  l r=  (arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (-) T l r))`;
-
-val _ = Define `
- ((subs_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a   l r=  (state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 
-  dict_Sail_values_Bitvector_a l r)))`;
-
-val _ = Define `
- ((subs_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (subs_vec_bool0 
-  dict_Sail_values_Bitvector_a l r))))`;
-
-val _ = Define `
- ((subs_vec_bit0:(bitU)list -> bitU ->(bitU)list)        l r=  (option_CASE (subs_vec_bit_maybe0 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-
-(*val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val add_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val mult_overflow_vec        : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
-let add_overflow_vec         = add_overflow_bv
-let add_overflow_vec_signed  = add_overflow_bv_signed
-let sub_overflow_vec         = sub_overflow_bv
-let sub_overflow_vec_signed  = sub_overflow_bv_signed
-let mult_overflow_vec        = mult_overflow_bv
-let mult_overflow_vec_signed = mult_overflow_bv_signed
-
-val add_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
-val add_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
-let add_overflow_vec_bit         = add_overflow_bv_bit
-let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
-let sub_overflow_vec_bit         = sub_overflow_bv_bit
-let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
-
-(*val shiftl       : list bitU -> integer -> list bitU*)
-(*val shiftr       : list bitU -> integer -> list bitU*)
-(*val arith_shiftr : list bitU -> integer -> list bitU*)
-(*val rotl         : list bitU -> integer -> list bitU*)
-(*val rotr         : list bitU -> integer -> list bitU*)
-val _ = Define `
- ((shiftl0:(bitU)list -> int ->(bitU)list)= 
-  (shiftl_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((shiftr0:(bitU)list -> int ->(bitU)list)= 
-  (shiftr_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((arith_shiftr0:(bitU)list -> int ->(bitU)list)= 
-  (arith_shiftr_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((rotl0:(bitU)list -> int ->(bitU)list)= 
-  (rotl_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((rotr0:(bitU)list -> int ->(bitU)list)= 
-  (rotr_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val mod_vec        : list bitU -> list bitU -> list bitU*)
-(*val mod_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
-(*val mod_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-val _ = Define `
- ((mod_vec0:(bitU)list ->(bitU)list ->(bitU)list)        l r=  (option_CASE (mod_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-val _ = Define `
- ((mod_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option)  l r=  (mod_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`;
-
-val _ = Define `
- ((mod_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "mod_vec" (mod_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`;
-
-val _ = Define `
- ((mod_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=  (state$of_bits_oracleS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec0 l r)))`;
-
-
-(*val quot_vec        : list bitU -> list bitU -> list bitU*)
-(*val quot_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
-(*val quot_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-val _ = Define `
- ((quot_vec0:(bitU)list ->(bitU)list ->(bitU)list)        l r=  (option_CASE (quot_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-val _ = Define `
- ((quot_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option)  l r=  (quot_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`;
-
-val _ = Define `
- ((quot_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "quot_vec" (quot_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`;
-
-val _ = Define `
- ((quot_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=  (state$of_bits_oracleS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec0 l r)))`;
-
-
-(*val quots_vec        : list bitU -> list bitU -> list bitU*)
-(*val quots_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
-(*val quots_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-val _ = Define `
- ((quots_vec0:(bitU)list ->(bitU)list ->(bitU)list)        l r=  (option_CASE (quots_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-val _ = Define `
- ((quots_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option)  l r=  (quots_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`;
-
-val _ = Define `
- ((quots_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "quots_vec" (quots_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`;
-
-val _ = Define `
- ((quots_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=  (state$of_bits_oracleS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec0 l r)))`;
-
-
-(*val mod_vec_int        : list bitU -> integer -> list bitU*)
-(*val mod_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
-(*val mod_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-val _ = Define `
- ((mod_vec_int0:(bitU)list -> int ->(bitU)list)        l r=  (option_CASE (mod_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-val _ = Define `
- ((mod_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option)  l r=  (mod_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`;
-
-val _ = Define `
- ((mod_vec_int_fail0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "mod_vec_int" (mod_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`;
-
-val _ = Define `
- ((mod_vec_int_oracle0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=  (state$of_bits_oracleS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int0 l r)))`;
-
-
-(*val quot_vec_int        : list bitU -> integer -> list bitU*)
-(*val quot_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
-(*val quot_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-val _ = Define `
- ((quot_vec_int0:(bitU)list -> int ->(bitU)list)        l r=  (option_CASE (quot_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
-
-val _ = Define `
- ((quot_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option)  l r=  (quot_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`;
-
-val _ = Define `
- ((quot_vec_int_fail0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "quot_vec_int" (quot_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`;
-
-val _ = Define `
- ((quot_vec_int_oracle0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=  (state$of_bits_oracleS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int0 l r)))`;
-
-
-(*val replicate_bits : list bitU -> integer -> list bitU*)
-val _ = Define `
- ((replicate_bits0:(bitU)list -> int ->(bitU)list)= 
-  (replicate_bits_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val duplicate : bitU -> integer -> list bitU*)
-val _ = Define `
- ((duplicate0:bitU -> int ->(bitU)list)= 
-  (duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict))`;
-
-val _ = Define `
- ((duplicate_maybe0:bitU -> int ->((bitU)list)option) b n=  (SOME (duplicate0 b n)))`;
-
-val _ = Define `
- ((duplicate_fail0:bitU -> int -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n=  (state_monad$returnS (duplicate0 b n)))`;
-
-val _ = Define `
- ((duplicate_oracle0:bitU -> int -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n=  (state_monad$bindS
-  (state$bool_of_bitU_oracleS b) (\ b . 
-  state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`;
-
-
-(*val reverse_endianness : list bitU -> list bitU*)
-val _ = Define `
- ((reverse_endianness0:(bitU)list ->(bitU)list) v=  (reverse_endianness_list v))`;
-
-
-(*val get_slice_int : integer -> integer -> integer -> list bitU*)
-val _ = Define `
- ((get_slice_int0:int -> int -> int ->(bitU)list)= 
-  (get_slice_int_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*)
-val _ = Define `
- ((set_slice_int0:int -> int -> int ->(bitU)list -> int)= 
-  (set_slice_int_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-
-(*val slice : list bitU -> integer -> integer -> list bitU*)
-val _ = Define `
- ((slice0:(bitU)list -> int -> int ->(bitU)list) v lo len=
-   (subrange_vec_dec0 v ((lo + len) -( 1 : int)) lo))`;
-
-
-(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*)
-val _ = Define `
- ((set_slice0:int -> int ->(bitU)list -> int ->(bitU)list ->(bitU)list) (out_len:ii) (slice_len:ii) out (n:ii) v=
-   (update_subrange_vec_dec0 out ((n + slice_len) -( 1 : int)) n v))`;
-
-
-(*val eq_vec    : list bitU -> list bitU -> bool*)
-(*val neq_vec   : list bitU -> list bitU -> bool*)
-val _ = Define `
- ((eq_vec:(bitU)list ->(bitU)list -> bool)= 
-  (eq_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = Define `
- ((neq_vec:(bitU)list ->(bitU)list -> bool)= 
-  (neq_bv
-     (instance_Sail_values_Bitvector_list_dict
-        instance_Sail_values_BitU_Sail_values_bitU_dict)))`;
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml
deleted file mode 100644
index a35707f0..00000000
--- a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml
+++ /dev/null
@@ -1,635 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory sail_operatorsTheory prompt_monadTheory promptTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "sail_operators_mwords"
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_values*)
-(*open import Sail_operators*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-val _ = Define `
- ((uint_maybe:'a words$word ->(int)option) v=  (SOME (lem$w2ui v)))`;
-
-val _ = Define `
- ((uint_fail:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v=  (state_monad$returnS (lem$w2ui v)))`;
-
-val _ = Define `
- ((uint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v=  (state_monad$returnS (lem$w2ui v)))`;
-
-val _ = Define `
- ((sint_maybe:'a words$word ->(int)option) v=  (SOME (integer_word$w2i v)))`;
-
-val _ = Define `
- ((sint_fail:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v=  (state_monad$returnS (integer_word$w2i v)))`;
-
-val _ = Define `
- ((sint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v=  (state_monad$returnS (integer_word$w2i v)))`;
-
-
-(*val vec_of_bits_maybe    : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*)
-(*val vec_of_bits_fail     : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
-(*val vec_of_bits_oracle   : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
-(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*)
-(*val vec_of_bits          : forall 'a. Size 'a => list bitU -> mword 'a*)
-val _ = Define `
- ((vec_of_bits_maybe:(bitU)list ->('a words$word)option) bits=  (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`;
-
-val _ = Define `
- ((vec_of_bits_fail:(bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits=  (state$of_bits_failS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`;
-
-val _ = Define `
- ((vec_of_bits_oracle:(bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits=  (state$of_bits_oracleS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`;
-
-val _ = Define `
- ((vec_of_bits_failwith:(bitU)list -> 'a words$word) bits=  (of_bits_failwith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`;
-
-val _ = Define `
- ((vec_of_bits:(bitU)list -> 'a words$word) bits=  (of_bits_failwith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`;
-
-
-(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
-val _ = Define `
- ((access_vec_inc:'a words$word -> int -> bitU)= 
-  (access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict))`;
-
-
-(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
-val _ = Define `
- ((access_vec_dec:'a words$word -> int -> bitU)= 
-  (access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict))`;
-
-
-val _ = Define `
- ((update_vec_dec_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b=  (update_mword_dec w i b))`;
-
-val _ = Define `
- ((update_vec_dec_fail:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b=  (state_monad$bindS
-  (state$bool_of_bitU_fail b) (\ b . 
-  state_monad$returnS (update_mword_bool_dec w i b))))`;
-
-val _ = Define `
- ((update_vec_dec_oracle:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b=  (state_monad$bindS
-  (state$bool_of_bitU_oracleS b) (\ b . 
-  state_monad$returnS (update_mword_bool_dec w i b))))`;
-
-val _ = Define `
- ((update_vec_dec:'a words$word -> int -> bitU -> 'a words$word) w i b=  (maybe_failwith (update_vec_dec_maybe w i b)))`;
-
-
-val _ = Define `
- ((update_vec_inc_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b=  (update_mword_inc w i b))`;
-
-val _ = Define `
- ((update_vec_inc_fail:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b=  (state_monad$bindS
-  (state$bool_of_bitU_fail b) (\ b . 
-  state_monad$returnS (update_mword_bool_inc w i b))))`;
-
-val _ = Define `
- ((update_vec_inc_oracle:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b=  (state_monad$bindS
-  (state$bool_of_bitU_oracleS b) (\ b . 
-  state_monad$returnS (update_mword_bool_inc w i b))))`;
-
-val _ = Define `
- ((update_vec_inc:'a words$word -> int -> bitU -> 'a words$word) w i b=  (maybe_failwith (update_vec_inc_maybe w i b)))`;
-
-
-(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-val _ = Define `
- ((subrange_vec_dec:'a words$word -> int -> int -> 'b words$word) w i j=  (words$word_extract (nat_of_int i) (nat_of_int j) w))`;
-
-
-(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-val _ = Define `
- ((subrange_vec_inc:'a words$word -> int -> int -> 'b words$word) w i j=  (subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j)))`;
-
-
-(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-val _ = Define `
- ((update_subrange_vec_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=  (words$bit_field_insert (nat_of_int i) (nat_of_int j) w' w))`;
-
-
-(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-val _ = Define `
- ((update_subrange_vec_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=  (update_subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j) w'))`;
-
-
-(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-val _ = Define `
- ((extz_vec:int -> 'a words$word -> 'b words$word) _ w=  (words$w2w w))`;
-
-
-(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-val _ = Define `
- ((exts_vec:int -> 'a words$word -> 'b words$word) _ w=  (words$sw2sw w))`;
-
-
-(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-val _ = Define `
- ((zero_extend:'a words$word -> int -> 'b words$word) w _=  (words$w2w w))`;
-
-
-(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-val _ = Define `
- ((sign_extend:'a words$word -> int -> 'b words$word) w _=  (words$sw2sw w))`;
-
-
-(*val zeros : forall 'a. Size 'a => integer -> mword 'a*)
-val _ = Define `
- ((zeros:int -> 'a words$word) _=  (words$n2w(( 0:num))))`;
-
-
-(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-val _ = Define `
- ((vector_truncate:'a words$word -> int -> 'b words$word) w _=  (words$w2w w))`;
-
-
-(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
-val _ = Define `
- ((concat_vec:'a words$word -> 'b words$word -> 'c words$word)=  words$word_concat)`;
-
-
-(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*)
-val _ = Define `
- ((cons_vec_bool:bool -> 'a words$word -> 'b words$word) b w=  (bitstring$v2w (b :: bitstring$w2v w)))`;
-
-val _ = Define `
- ((cons_vec_maybe:bitU -> 'c words$word ->('b words$word)option) b w=  (OPTION_MAP (\ b .  cons_vec_bool b w) (bool_of_bitU b)))`;
-
-val _ = Define `
- ((cons_vec_fail:bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w=  (state_monad$bindS (state$bool_of_bitU_fail b) (\ b .  state_monad$returnS (cons_vec_bool b w))))`;
-
-val _ = Define `
- ((cons_vec_oracle:bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w=  (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b .  state_monad$returnS (cons_vec_bool b w))))`;
-
-val _ = Define `
- ((cons_vec:bitU -> 'a words$word -> 'b words$word) b w=  (maybe_failwith (cons_vec_maybe b w)))`;
-
-
-(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*)
-val _ = Define `
- ((vec_of_bool:int -> bool -> 'a words$word) _ b=  (bitstring$v2w [b]))`;
-
-val _ = Define `
- ((vec_of_bit_maybe:int -> bitU ->('a words$word)option) len b=  (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`;
-
-val _ = Define `
- ((vec_of_bit_fail:int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b=  (state_monad$bindS (state$bool_of_bitU_fail b) (\ b .  state_monad$returnS (vec_of_bool len b))))`;
-
-val _ = Define `
- ((vec_of_bit_oracle:int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b=  (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b .  state_monad$returnS (vec_of_bool len b))))`;
-
-val _ = Define `
- ((vec_of_bit:int -> bitU -> 'a words$word) len b=  (maybe_failwith (vec_of_bit_maybe len b)))`;
-
-
-(*val cast_bool_vec : bool -> mword ty1*)
-val _ = Define `
- ((cast_bool_vec:bool ->(1)words$word) b=  (vec_of_bool(( 1 : int)) b))`;
-
-val _ = Define `
- ((cast_unit_vec_maybe:bitU ->('a words$word)option) b=  (vec_of_bit_maybe(( 1 : int)) b))`;
-
-val _ = Define `
- ((cast_unit_vec_fail:bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b=  (state_monad$bindS (state$bool_of_bitU_fail b) (\ b .  state_monad$returnS (cast_bool_vec b))))`;
-
-val _ = Define `
- ((cast_unit_vec_oracle:bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b=  (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b .  state_monad$returnS (cast_bool_vec b))))`;
-
-val _ = Define `
- ((cast_unit_vec:bitU -> 'a words$word) b=  (maybe_failwith (cast_unit_vec_maybe b)))`;
-
-
-(*val msb : forall 'a. Size 'a => mword 'a -> bitU*)
-val _ = Define `
- ((msb:'a words$word -> bitU)= 
-  (most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict))`;
-
-
-(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*)
-val _ = Define `
- ((int_of_vec:bool -> 'a words$word -> int) sign w=
-   (if sign
-  then integer_word$w2i w
-  else lem$w2ui w))`;
-
-val _ = Define `
- ((int_of_vec_maybe:bool -> 'a words$word ->(int)option) sign w=  (SOME (int_of_vec sign w)))`;
-
-val _ = Define `
- ((int_of_vec_fail:bool -> 'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) sign w=  (state_monad$returnS (int_of_vec sign w)))`;
-
-
-(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*)
-val _ = Define `
- ((string_of_vec:'a words$word -> string)= 
-  (string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`;
-
-
-(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val or_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
-val _ = Define `
- ((and_vec:'a words$word -> 'a words$word -> 'a words$word)=  words$word_and)`;
-
-val _ = Define `
- ((or_vec:'a words$word -> 'a words$word -> 'a words$word)=   words$word_or)`;
-
-val _ = Define `
- ((xor_vec:'a words$word -> 'a words$word -> 'a words$word)=  words$word_xor)`;
-
-val _ = Define `
- ((not_vec:'a words$word -> 'a words$word)=  words$word_1comp)`;
-
-
-(*val add_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val adds_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val sub_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val subs_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val mult_vec  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
-(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
-val _ = Define `
- ((add_vec:'a words$word -> 'a words$word -> 'a words$word)   l r=  (integer_word$i2w ((int_of_mword F l) + (int_of_mword F r))))`;
-
-val _ = Define `
- ((adds_vec:'a words$word -> 'a words$word -> 'a words$word)  l r=  (integer_word$i2w ((int_of_mword T l) + (int_of_mword T r))))`;
-
-val _ = Define `
- ((sub_vec:'a words$word -> 'a words$word -> 'a words$word)   l r=  (integer_word$i2w ((int_of_mword F l) - (int_of_mword F r))))`;
-
-val _ = Define `
- ((subs_vec:'a words$word -> 'a words$word -> 'a words$word)  l r=  (integer_word$i2w ((int_of_mword T l) - (int_of_mword T r))))`;
-
-val _ = Define `
- ((mult_vec:'a words$word -> 'a words$word -> 'b words$word)  l r=  (integer_word$i2w ((int_of_mword F (words$w2w l :  'b words$word)) * (int_of_mword F (words$w2w r :  'b words$word)))))`;
-
-val _ = Define `
- ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r=  (integer_word$i2w ((int_of_mword T (words$sw2sw l :  'b words$word)) * (int_of_mword T (words$sw2sw r :  'b words$word)))))`;
-
-
-(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val adds_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val subs_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-val _ = Define `
- ((add_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
-
-val _ = Define `
- ((adds_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
-
-val _ = Define `
- ((sub_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
-
-val _ = Define `
- ((subs_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
-
-val _ = Define `
- ((mult_vec_int:'a words$word -> int -> 'b words$word)  l r=  (arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ( * )  F (words$w2w l :  'b words$word) r))`;
-
-val _ = Define `
- ((mults_vec_int:'a words$word -> int -> 'b words$word) l r=  (arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ( * )  T  (words$sw2sw l :  'b words$word) r))`;
-
-
-(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val adds_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val subs_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-val _ = Define `
- ((add_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
-
-val _ = Define `
- ((adds_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
-
-val _ = Define `
- ((sub_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
-
-val _ = Define `
- ((subs_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
-
-val _ = Define `
- ((mult_int_vec:int -> 'a words$word -> 'b words$word)  l r=  (arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ( * )  F l (words$w2w r :  'b words$word)))`;
-
-val _ = Define `
- ((mults_int_vec:int -> 'a words$word -> 'b words$word) l r=  (arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ( * )  T  l (words$sw2sw r :  'b words$word)))`;
-
-
-(*val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-(*val sub_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-
-val _ = Define `
- ((add_vec_bool:'a words$word -> bool -> 'a words$word)        l r=  (arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`;
-
-val _ = Define `
- ((add_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)   l r=  (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`;
-
-val _ = Define `
- ((add_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)    l r=  (state_monad$bindS (state$bool_of_bitU_fail r) (\ r .  state_monad$returnS (add_vec_bool l r))))`;
-
-val _ = Define `
- ((add_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)  l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (add_vec_bool l r))))`;
-
-val _ = Define `
- ((add_vec_bit:'a words$word -> bitU -> 'a words$word)         l r=  (maybe_failwith (add_vec_bit_maybe  l r)))`;
-
-
-val _ = Define `
- ((adds_vec_bool:'a words$word -> bool -> 'a words$word)       l r=  (arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T  l r))`;
-
-val _ = Define `
- ((adds_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)  l r=  (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`;
-
-val _ = Define `
- ((adds_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)   l r=  (state_monad$bindS (state$bool_of_bitU_fail r) (\ r .  state_monad$returnS (adds_vec_bool l r))))`;
-
-val _ = Define `
- ((adds_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (adds_vec_bool l r))))`;
-
-val _ = Define `
- ((adds_vec_bit:'a words$word -> bitU -> 'a words$word)        l r=  (maybe_failwith (adds_vec_bit_maybe l r)))`;
-
-
-val _ = Define `
- ((sub_vec_bool:'a words$word -> bool -> 'a words$word)        l r=  (arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
-
-val _ = Define `
- ((sub_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)   l r=  (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`;
-
-val _ = Define `
- ((sub_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)    l r=  (state_monad$bindS (state$bool_of_bitU_fail r) (\ r .  state_monad$returnS (sub_vec_bool l r))))`;
-
-val _ = Define `
- ((sub_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)  l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (sub_vec_bool l r))))`;
-
-val _ = Define `
- ((sub_vec_bit:'a words$word -> bitU -> 'a words$word)         l r=  (maybe_failwith (sub_vec_bit_maybe  l r)))`;
-
-
-val _ = Define `
- ((subs_vec_bool:'a words$word -> bool -> 'a words$word)       l r=  (arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
-
-val _ = Define `
- ((subs_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option)  l r=  (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`;
-
-val _ = Define `
- ((subs_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)   l r=  (state_monad$bindS (state$bool_of_bitU_fail r) (\ r .  state_monad$returnS (subs_vec_bool l r))))`;
-
-val _ = Define `
- ((subs_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r=  (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r .  state_monad$returnS (subs_vec_bool l r))))`;
-
-val _ = Define `
- ((subs_vec_bit:'a words$word -> bitU -> 'a words$word)        l r=  (maybe_failwith (subs_vec_bit_maybe  l r)))`;
-
-
-(* TODO
-val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU)
-let maybe_mword_of_bits_overflow (bits, overflow, carry) =
-  Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits)
-
-val add_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val adds_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val sub_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val subs_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val mult_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-let add_overflow_vec   l r = maybe_mword_of_bits_overflow (add_overflow_bv l r)
-let adds_overflow_vec  l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r)
-let sub_overflow_vec   l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r)
-let subs_overflow_vec  l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r)
-let mult_overflow_vec  l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r)
-let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r)
-
-val add_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-val add_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-val sub_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-val sub_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-let add_overflow_vec_bit         = add_overflow_bv_bit
-let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
-let sub_overflow_vec_bit         = sub_overflow_bv_bit
-let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
-
-(*val shiftl       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val shiftr       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val rotl         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val rotr         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-val _ = Define `
- ((shiftl:'a words$word -> int -> 'a words$word)=        shiftl_mword)`;
-
-val _ = Define `
- ((shiftr:'a words$word -> int -> 'a words$word)=        shiftr_mword)`;
-
-val _ = Define `
- ((arith_shiftr:'a words$word -> int -> 'a words$word)=  arith_shiftr_mword)`;
-
-val _ = Define `
- ((rotl:'a words$word -> int -> 'a words$word)=          rotl_mword)`;
-
-val _ = Define `
- ((rotr:'a words$word -> int -> 'a words$word)=          rotr_mword)`;
-
-
-(*val mod_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val mod_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
-(*val mod_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-val _ = Define `
- ((mod_vec:'a words$word -> 'a words$word -> 'a words$word)        l r=  (mod_mword l r))`;
-
-val _ = Define `
- ((mod_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option)  l r=  (mod_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`;
-
-val _ = Define `
- ((mod_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "mod_vec" (mod_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`;
-
-val _ = Define `
- ((mod_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=
-   ((case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      SOME w => state_monad$returnS w
-    | NONE => state$mword_oracleS () 
-  )))`;
-
-
-(*val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val quot_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
-(*val quot_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-val _ = Define `
- ((quot_vec:'a words$word -> 'a words$word -> 'a words$word)        l r=  (quot_mword l r))`;
-
-val _ = Define `
- ((quot_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option)  l r=  (quot_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`;
-
-val _ = Define `
- ((quot_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "quot_vec" (quot_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`;
-
-val _ = Define `
- ((quot_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=
-   ((case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      SOME w => state_monad$returnS w
-    | NONE => state$mword_oracleS () 
-  )))`;
-
-
-(*val quots_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val quots_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
-(*val quots_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-val _ = Define `
- ((quots_vec:'a words$word -> 'a words$word -> 'a words$word)        l r=  (quots_mword l r))`;
-
-val _ = Define `
- ((quots_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option)  l r=  (quots_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`;
-
-val _ = Define `
- ((quots_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "quots_vec" (quots_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`;
-
-val _ = Define `
- ((quots_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=
-   ((case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      SOME w => state_monad$returnS w
-    | NONE => state$mword_oracleS () 
-  )))`;
-
-
-(*val mod_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mod_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
-(*val mod_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-val _ = Define `
- ((mod_vec_int:'a words$word -> int -> 'a words$word)        l r=  (mod_mword_int l r))`;
-
-val _ = Define `
- ((mod_vec_int_maybe:'a words$word -> int ->('a words$word)option)  l r=  (mod_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`;
-
-val _ = Define `
- ((mod_vec_int_fail:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "mod_vec_int" (mod_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`;
-
-val _ = Define `
- ((mod_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=
-   ((case (mod_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      SOME w => state_monad$returnS w
-    | NONE => state$mword_oracleS () 
-  )))`;
-
-
-(*val quot_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val quot_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
-(*val quot_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-val _ = Define `
- ((quot_vec_int:'a words$word -> int -> 'a words$word)        l r=  (quot_mword_int l r))`;
-
-val _ = Define `
- ((quot_vec_int_maybe:'a words$word -> int ->('a words$word)option)  l r=  (quot_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`;
-
-val _ = Define `
- ((quot_vec_int_fail:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set)   l r=  (state_monad$maybe_failS "quot_vec_int" (quot_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`;
-
-val _ = Define `
- ((quot_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r=
-   ((case (quot_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      SOME w => state_monad$returnS w
-    | NONE => state$mword_oracleS () 
-  )))`;
-
-
-(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-val _ = Define `
- ((replicate_bits:'a words$word -> int -> 'b words$word) v count1=  (bitstring$v2w (repeat (bitstring$w2v v) count1)))`;
-
-
-(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*)
-val _ = Define `
- ((duplicate_bool:bool -> int -> 'a words$word)   b n=  (bitstring$v2w (repeat [b] n)))`;
-
-val _ = Define `
- ((duplicate_maybe:bitU -> int ->('a words$word)option)  b n=  (OPTION_MAP (\ b .  duplicate_bool b n) (bool_of_bitU b)))`;
-
-val _ = Define `
- ((duplicate_fail:bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set)   b n=  (state_monad$bindS (state$bool_of_bitU_fail b) (\ b .  state_monad$returnS (duplicate_bool b n))))`;
-
-val _ = Define `
- ((duplicate_oracle:bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n=  (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b .  state_monad$returnS (duplicate_bool b n))))`;
-
-val _ = Define `
- ((duplicate:bitU -> int -> 'a words$word)        b n=  (maybe_failwith (duplicate_maybe b n)))`;
-
-
-(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*)
-val _ = Define `
- ((reverse_endianness:'a words$word -> 'a words$word) v=  (bitstring$v2w (reverse_endianness_list (bitstring$w2v v))))`;
-
-
-(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*)
-val _ = Define `
- ((get_slice_int:int -> int -> int -> 'a words$word)= 
-  (get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`;
-
-
-(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*)
-val _ = Define `
- ((set_slice_int:int -> int -> int -> 'a words$word -> int)= 
-  (set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`;
-
-
-(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-val _ = Define `
- ((slice:'a words$word -> int -> int -> 'b words$word) v lo len=
-   (subrange_vec_dec v ((lo + len) -( 1 : int)) lo))`;
-
-
-(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*)
-val _ = Define `
- ((set_slice:int -> int -> 'a words$word -> int -> 'b words$word -> 'a words$word) (out_len:ii) (slice_len:ii) out (n:ii) v=
-   (update_subrange_vec_dec out ((n + slice_len) -( 1 : int)) n v))`;
-
-
-(*val eq_vec    : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
-(*val neq_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml
deleted file mode 100644
index aa169979..00000000
--- a/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml
+++ /dev/null
@@ -1,139 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory;
-open intLib;
-
-val _ = numLib.prefer_num();
-
-
-
-open lemLib;
-(* val _ = lemLib.run_interactive := true; *)
-val _ = new_theory "sail_valuesAuxiliary"
-
-
-(****************************************************)
-(*                                                  *)
-(* Termination Proofs                               *)
-(*                                                  *)
-(****************************************************)
-
-(* val gst = Defn.tgoal_no_defn (shr_int_def, shr_int_ind) *)
-val (shr_int_rw, shr_int_ind_rw) =
-  Defn.tprove_no_defn ((shr_int_def, shr_int_ind),
-    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
-  )
-val shr_int_rw = save_thm ("shr_int_rw", shr_int_rw);
-val shr_int_ind_rw = save_thm ("shr_int_ind_rw", shr_int_ind_rw);
-val () = computeLib.add_persistent_funs["shr_int_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (shl_int_def, shl_int_ind) *)
-val (shl_int_rw, shl_int_ind_rw) =
-  Defn.tprove_no_defn ((shl_int_def, shl_int_ind),
-    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
-  )
-val shl_int_rw = save_thm ("shl_int_rw", shl_int_rw);
-val shl_int_ind_rw = save_thm ("shl_int_ind_rw", shl_int_ind_rw);
-val () = computeLib.add_persistent_funs["shl_int_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (repeat_def, repeat_ind) *)
-val (repeat_rw, repeat_ind_rw) =
-  Defn.tprove_no_defn ((repeat_def, repeat_ind),
-    WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
-  )
-val repeat_rw = save_thm ("repeat_rw", repeat_rw);
-val repeat_ind_rw = save_thm ("repeat_ind_rw", repeat_ind_rw);
-val () = computeLib.add_persistent_funs["repeat_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (bools_of_nat_aux_def, bools_of_nat_aux_ind) *)
-val (bools_of_nat_aux_rw, bools_of_nat_aux_ind_rw) =
-  Defn.tprove_no_defn ((bools_of_nat_aux_def, bools_of_nat_aux_ind),
-    WF_REL_TAC`measure (Num o FST)` \\ COOPER_TAC
-  )
-val bools_of_nat_aux_rw = save_thm ("bools_of_nat_aux_rw", bools_of_nat_aux_rw);
-val bools_of_nat_aux_ind_rw = save_thm ("bools_of_nat_aux_ind_rw", bools_of_nat_aux_ind_rw);
-val () = computeLib.add_persistent_funs["bools_of_nat_aux_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (pad_list_def, pad_list_ind) *)
-val (pad_list_rw, pad_list_ind_rw) =
-  Defn.tprove_no_defn ((pad_list_def, pad_list_ind),
-    WF_REL_TAC`measure (Num o SND o SND)` \\ COOPER_TAC
-  )
-val pad_list_rw = save_thm ("pad_list_rw", pad_list_rw);
-val pad_list_ind_rw = save_thm ("pad_list_ind_rw", pad_list_ind_rw);
-val () = computeLib.add_persistent_funs["pad_list_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (reverse_endianness_list_def, reverse_endianness_list_ind) *)
-val (reverse_endianness_list_rw, reverse_endianness_list_ind_rw) =
-  Defn.tprove_no_defn ((reverse_endianness_list_def, reverse_endianness_list_ind),
-    WF_REL_TAC`measure LENGTH` \\ rw[drop_list_def,nat_of_int_def]
-  )
-val reverse_endianness_list_rw = save_thm ("reverse_endianness_list_rw", reverse_endianness_list_rw);
-val reverse_endianness_list_ind_rw = save_thm ("reverse_endianness_list_ind_rw", reverse_endianness_list_ind_rw);
-val () = computeLib.add_persistent_funs["reverse_endianness_list_rw"];
-
-
-(* val gst = Defn.tgoal_no_defn (index_list_def, index_list_ind) *)
-val (index_list_rw, index_list_ind_rw) =
-  Defn.tprove_no_defn ((index_list_def, index_list_ind),
-    WF_REL_TAC`measure (λ(x,y,z). Num(1+(if z > 0 then int_max (-1) (y - x) else int_max (-1) (x - y))))`
-    \\ rw[integerTheory.INT_MAX]
-    \\ intLib.COOPER_TAC
-  )
-val index_list_rw = save_thm ("index_list_rw", index_list_rw);
-val index_list_ind_rw = save_thm ("index_list_ind_rw", index_list_ind_rw);
-val () = computeLib.add_persistent_funs["index_list_rw"];
-
-
-(*
-(* val gst = Defn.tgoal_no_defn (while_def, while_ind) *)
-val (while_rw, while_ind_rw) =
-  Defn.tprove_no_defn ((while_def, while_ind),
-    cheat (* the termination proof *)
-  )
-val while_rw = save_thm ("while_rw", while_rw);
-val while_ind_rw = save_thm ("while_ind_rw", while_ind_rw);
-*)
-
-
-(*
-(* val gst = Defn.tgoal_no_defn (until_def, until_ind) *)
-val (until_rw, until_ind_rw) =
-  Defn.tprove_no_defn ((until_def, until_ind),
-    cheat (* the termination proof *)
-  )
-val until_rw = save_thm ("until_rw", until_rw);
-val until_ind_rw = save_thm ("until_ind_rw", until_ind_rw);
-*)
-
-
-(****************************************************)
-(*                                                  *)
-(* Lemmata                                          *)
-(*                                                  *)
-(****************************************************)
-
-val just_list_spec = store_thm("just_list_spec",
-``((! xs. (just_list xs = NONE) <=> MEM NONE xs) /\
-   (! xs es. (just_list xs = SOME es) <=> (xs = MAP SOME es)))``,
-  (* Theorem: just_list_spec*)
-  conj_tac
-  \\ ho_match_mp_tac just_list_ind
-  \\ Cases \\ rw[]
-  \\ rw[Once just_list_def]
-  >- ( CASE_TAC \\ fs[] \\ CASE_TAC )
-  >- PROVE_TAC[]
-  \\ Cases_on`es` \\ fs[]
-  \\ CASE_TAC \\ fs[]
-  \\ CASE_TAC \\ fs[]
-);
-
-
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml b/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml
deleted file mode 100644
index f178a336..00000000
--- a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml
+++ /dev/null
@@ -1,1231 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory lem_machine_wordTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "sail_values"
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_impl_base*)
-
-
-val _ = type_abbrev( "ii" , ``: int``);
-val _ = type_abbrev( "nn" , ``: num``);
-
-(*val nat_of_int : integer -> nat*)
-val _ = Define `
- ((nat_of_int:int -> num) i=  (if i <( 0 : int) then( 0 : num) else Num (ABS (I i))))`;
-
-
-(*val pow : integer -> integer -> integer*)
-val _ = Define `
- ((pow0:int -> int -> int) m n=  (m ** (nat_of_int n)))`;
-
-
-val _ = Define `
- ((pow2:int -> int) n=  (pow0(( 2 : int)) n))`;
-
-
-(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
-
-(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
-
-(*let add_int l r = integerAdd l r
-let add_signed l r = integerAdd l r
-let sub_int l r = integerMinus l r
-let mult_int l r = integerMult l r
-let div_int l r = integerDiv l r
-let div_nat l r = natDiv l r
-let power_int_nat l r = integerPow l r
-let power_int_int l r = integerPow l (nat_of_int r)
-let negate_int i = integerNegate i
-let min_int l r = integerMin l r
-let max_int l r = integerMax l r
-
-let add_real l r = realAdd l r
-let sub_real l r = realMinus l r
-let mult_real l r = realMult l r
-let div_real l r = realDiv l r
-let negate_real r = realNegate r
-let abs_real r = realAbs r
-let power_real b e = realPowInteger b e*)
-
-(*val prerr_endline : string -> unit*)
-val _ = Define `
- ((prerr_endline:string -> unit) _=  () )`;
-
-
-(*val print_int : string -> integer -> unit*)
-val _ = Define `
- ((print_int:string -> int -> unit) msg i=  (prerr_endline ( STRCAT msg (stringFromInteger i))))`;
-
-
-(*val putchar : integer -> unit*)
-val _ = Define `
- ((putchar:int -> unit) _=  () )`;
-
-
-(*val shr_int : ii -> ii -> ii*)
- val shr_int_defn = Hol_defn "shr_int" `
- ((shr_int:int -> int -> int) x s=  (if s >( 0 : int) then shr_int (x /( 2 : int)) (s -( 1 : int)) else x))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shr_int_defn;
-
-(*val shl_int : integer -> integer -> integer*)
- val shl_int_defn = Hol_defn "shl_int" `
- ((shl_int:int -> int -> int) i shift=  (if shift >( 0 : int) then( 2 : int) * shl_int i (shift -( 1 : int)) else i))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shl_int_defn;
-val _ = Define `
- ((take_list:int -> 'a list -> 'a list) n xs=  (TAKE (nat_of_int n) xs))`;
-
-val _ = Define `
- ((drop_list:int -> 'a list -> 'a list) n xs=  (DROP (nat_of_int n) xs))`;
-
-
-(*val repeat : forall 'a. list 'a -> integer -> list 'a*)
- val repeat_defn = Hol_defn "repeat" `
- ((repeat:'a list -> int -> 'a list) xs n=
-   (if n <=( 0 : int) then []
-  else xs ++ repeat xs (n -( 1 : int))))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn repeat_defn;
-
-val _ = Define `
- ((duplicate_to_list:'a -> int -> 'a list) bit length=  (repeat [bit] length))`;
-
-
- val _ = Define `
- ((replace:'a list -> int -> 'a -> 'a list) bs (n : int) b'=  ((case bs of
-    [] => []
-  | b :: bs =>
-     if n =( 0 : int) then b' :: bs
-              else b :: replace bs (n -( 1 : int)) b'
-  )))`;
-
-
-val _ = Define `
- ((upper:'a -> 'a) n=  n)`;
-
-
-(* Modulus operation corresponding to quot below -- result
-   has sign of dividend. *)
-val _ = Define `
- ((hardware_mod:int -> int -> int) (a: int) (b:int) : int=
-   (let m = ((ABS a) % (ABS b)) in
-  if a <( 0 : int) then ~ m else m))`;
-
-
-(* There are different possible answers for integer divide regarding
-rounding behaviour on negative operands. Positive operands always
-round down so derive the one we want (trucation towards zero) from
-that *)
-val _ = Define `
- ((hardware_quot:int -> int -> int) (a:int) (b:int) : int=
-   (let q = ((ABS a) / (ABS b)) in
-  if ((a<( 0 : int)) <=> (b<( 0 : int))) then
-    q  (* same sign -- result positive *)
-  else
-    ~ q))`;
- (* different sign -- result negative *)
-
-val _ = Define `
- ((max_64u:int)=  (((( 2 : int))**(( 64 : num))) -( 1 : int)))`;
-
-val _ = Define `
- ((max_64:int)=   (((( 2 : int))**(( 63 : num))) -( 1 : int)))`;
-
-val _ = Define `
- ((min_64:int)=  (( 0 : int) - ((( 2 : int))**(( 63 : num)))))`;
-
-val _ = Define `
- ((max_32u:int)=  ((( 4294967295 : int) : int)))`;
-
-val _ = Define `
- ((max_32:int)=   ((( 2147483647 : int) : int)))`;
-
-val _ = Define `
- ((min_32:int)=   ((( 0 : int) -( 2147483648 : int) : int)))`;
-
-val _ = Define `
- ((max_8:int)=    ((( 127 : int) : int)))`;
-
-val _ = Define `
- ((min_8:int)=    ((( 0 : int) -( 128 : int) : int)))`;
-
-val _ = Define `
- ((max_5:int)=    ((( 31 : int) : int)))`;
-
-val _ = Define `
- ((min_5:int)=    ((( 0 : int) -( 32 : int) : int)))`;
-
-
-(* just_list takes a list of maybes and returns Just xs if all elements have
-   a value, and Nothing if one of the elements is Nothing. *)
-(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*)
- val _ = Define `
- ((just_list:('a option)list ->('a list)option) l=  ((case l of
-    [] => SOME []
-  | (x :: xs) =>
-    (case (x, just_list xs) of
-        (SOME x, SOME xs) => SOME (x :: xs)
-      | (_, _) => NONE
-    )
-  )))`;
-
-
-(*val maybe_failwith : forall 'a. maybe 'a -> 'a*)
-val _ = Define `
- ((maybe_failwith:'a option -> 'a)= 
-  (\x .  (case x of   SOME a => a | NONE => failwith "maybe_failwith" )))`;
-
-
-(*** Bits *)
-val _ = Hol_datatype `
- bitU = B0 | B1 | BU`;
-
-
-val _ = Define `
- ((showBitU:bitU -> string)= 
-  (\x .  (case x of   B0 => "O" | B1 => "I" | BU => "U" )))`;
-
-
-val _ = Define `
- ((bitU_char:bitU -> char)= 
-  (\x .  (case x of   B0 => #"0" | B1 => #"1" | BU => #"?" )))`;
-
-
-val _ = Define `
-((instance_Show_Show_Sail_values_bitU_dict:(bitU)Show_class)= (<|
-
-  show_method := showBitU|>))`;
-
-
-(*val compare_bitU : bitU -> bitU -> ordering*)
-val _ = Define `
- ((compare_bitU:bitU -> bitU -> ordering) l r=  ((case (l, r) of
-    (BU, BU) => EQUAL
-  | (B0, B0) => EQUAL
-  | (B1, B1) => EQUAL
-  | (BU, _)  => LESS
-  | (_, BU)  => GREATER
-  | (B0, _)  => LESS
-  | (_, _)   => GREATER
-)))`;
-
-
-val _ = Define `
-((instance_Basic_classes_Ord_Sail_values_bitU_dict:(bitU)Ord_class)= (<|
-
-  compare_method := compare_bitU;
-
-  isLess_method := (\  l r. (compare_bitU l r) = LESS);
-
-  isLessEqual_method := (\ l r. (compare_bitU l r) <> GREATER);
-
-  isGreater_method := (\  l r. (compare_bitU l r) = GREATER);
-
-  isGreaterEqual_method := (\ l r. (compare_bitU l r) <> LESS)|>))`;
-
-
-val _ = Hol_datatype `
-(*  'a *) BitU_class= <|
-  to_bitU_method : 'a -> bitU;
-  of_bitU_method : bitU -> 'a
-|>`;
-
-
-val _ = Define `
-((instance_Sail_values_BitU_Sail_values_bitU_dict:(bitU)BitU_class)= (<|
-
-  to_bitU_method := (\ b. b);
-
-  of_bitU_method := (\ b. b)|>))`;
-
-
-val _ = Define `
- ((bool_of_bitU:bitU ->(bool)option)= 
-  (\x .  (case x of   B0 => SOME F | B1 => SOME T | BU => NONE )))`;
-
-
-val _ = Define `
- ((bitU_of_bool:bool -> bitU) b=  (if b then B1 else B0))`;
-
-
-(*instance (BitU bool)
-  let to_bitU = bitU_of_bool
-  let of_bitU = bool_of_bitU
-end*)
-
-val _ = Define `
- ((cast_bit_bool:bitU ->(bool)option)=  bool_of_bitU)`;
-
-
-val _ = Define `
- ((not_bit:bitU -> bitU)= 
-  (\x .  (case x of   B1 => B0 | B0 => B1 | BU => BU )))`;
-
-
-(*val is_one : integer -> bitU*)
-val _ = Define `
- ((is_one:int -> bitU) i=
-   (if i =( 1 : int) then B1 else B0))`;
-
-
-(*val and_bit : bitU -> bitU -> bitU*)
-val _ = Define `
- ((and_bit:bitU -> bitU -> bitU) x y=
-   ((case (x, y) of
-      (B0, _) => B0
-    | (_, B0) => B0
-    | (B1, B1) => B1
-    | (_, _) => BU
-  )))`;
-
-
-(*val or_bit : bitU -> bitU -> bitU*)
-val _ = Define `
- ((or_bit:bitU -> bitU -> bitU) x y=
-   ((case (x, y) of
-      (B1, _) => B1
-    | (_, B1) => B1
-    | (B0, B0) => B0
-    | (_, _) => BU
-  )))`;
-
-
-(*val xor_bit : bitU -> bitU -> bitU*)
-val _ = Define `
- ((xor_bit:bitU -> bitU -> bitU) x y=
-  ((case (x, y) of
-      (B0, B0) => B0
-    | (B0, B1) => B1
-    | (B1, B0) => B1
-    | (B1, B1) => B0
-    | (_, _) => BU
-  )))`;
-
-
-(*val &. : bitU -> bitU -> bitU*)
-
-(*val |. : bitU -> bitU -> bitU*)
-
-(*val +. : bitU -> bitU -> bitU*)
-
-
-(*** Bool lists ***)
-
-(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
- val bools_of_nat_aux_defn = Hol_defn "bools_of_nat_aux" `
- ((bools_of_nat_aux:int -> num ->(bool)list ->(bool)list) len x acc=
-   (if len <=( 0 : int) then acc
-  else bools_of_nat_aux (len -( 1 : int)) (x DIV( 2:num)) ((if (x MOD( 2:num)) =( 1:num) then T else F) :: acc)))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn bools_of_nat_aux_defn;
-val _ = Define `
- ((bools_of_nat:int -> num ->(bool)list) len n=  (bools_of_nat_aux len n []))`;
- (*List.reverse (bools_of_nat_aux n)*)
-
-(*val nat_of_bools_aux : natural -> list bool -> natural*)
- val _ = Define `
- ((nat_of_bools_aux:num ->(bool)list -> num) acc bs=  ((case bs of
-    [] => acc
-  | T :: bs => nat_of_bools_aux ((( 2:num) * acc) +( 1:num)) bs
-  | F :: bs => nat_of_bools_aux (( 2:num) * acc) bs
-)))`;
-
-val _ = Define `
- ((nat_of_bools:(bool)list -> num) bs=  (nat_of_bools_aux(( 0:num)) bs))`;
-
-
-(*val unsigned_of_bools : list bool -> integer*)
-val _ = Define `
- ((unsigned_of_bools:(bool)list -> int) bs=  (int_of_num (nat_of_bools bs)))`;
-
-
-(*val signed_of_bools : list bool -> integer*)
-val _ = Define `
- ((signed_of_bools:(bool)list -> int) bs=
-   ((case bs of
-      T :: _  =>( 0 : int) - (( 1 : int) + (unsigned_of_bools (MAP (\ x. ~ x) bs)))
-    | F :: _ => unsigned_of_bools bs
-    | [] =>( 0 : int) (* Treat empty list as all zeros *)
-  )))`;
-
-
-(*val int_of_bools : bool -> list bool -> integer*)
-val _ = Define `
- ((int_of_bools:bool ->(bool)list -> int) sign bs=  (if sign then signed_of_bools bs else unsigned_of_bools bs))`;
-
-
-(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
- val pad_list_defn = Hol_defn "pad_list" `
- ((pad_list:'a -> 'a list -> int -> 'a list) x xs n=
-   (if n <=( 0 : int) then xs else pad_list x (x :: xs) (n -( 1 : int))))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn pad_list_defn;
-
-val _ = Define `
- ((ext_list:'a -> int -> 'a list -> 'a list) pad len xs=
-   (let longer = (len - (int_of_num (LENGTH xs))) in
-  if longer <( 0 : int) then DROP (nat_of_int (ABS (longer))) xs
-  else pad_list pad xs longer))`;
-
-
-val _ = Define `
- ((extz_bools:int ->(bool)list ->(bool)list) len bs=  (ext_list F len bs))`;
-
-val _ = Define `
- ((exts_bools:int ->(bool)list ->(bool)list) len bs=
-   ((case bs of
-      T :: _ => ext_list T len bs
-    | _ => ext_list F len bs
-  )))`;
-
-
- val _ = Define `
- ((add_one_bool_ignore_overflow_aux:(bool)list ->(bool)list) bits=  ((case bits of
-    [] => []
-  | F :: bits => T :: bits
-  | T :: bits => F :: add_one_bool_ignore_overflow_aux bits
-)))`;
-
-
-val _ = Define `
- ((add_one_bool_ignore_overflow:(bool)list ->(bool)list) bits=
-   (REVERSE (add_one_bool_ignore_overflow_aux (REVERSE bits))))`;
-
-
-(*let bool_list_of_int n =
-  let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
-  if n >= (0 : integer) then bs_abs
-  else add_one_bool_ignore_overflow (List.map not bs_abs)
-let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
-val _ = Define `
- ((bools_of_int:int -> int ->(bool)list) len n=
-   (let bs_abs = (bools_of_nat len (Num (ABS (ABS n)))) in
-  if n >= (( 0 : int) : int) then bs_abs
-  else add_one_bool_ignore_overflow (MAP (\ x. ~ x) bs_abs)))`;
-
-
-(*** Bit lists ***)
-
-(*val has_undefined_bits : list bitU -> bool*)
-val _ = Define `
- ((has_undefined_bits:(bitU)list -> bool) bs=  (EXISTS (\x .  
-  (case x of BU => T | _ => F )) bs))`;
-
-
-val _ = Define `
- ((bits_of_nat:int -> num ->(bitU)list) len n=  (MAP bitU_of_bool (bools_of_nat len n)))`;
-
-
-val _ = Define `
- ((nat_of_bits:(bitU)list ->(num)option) bits=
-   ((case (just_list (MAP bool_of_bitU bits)) of
-      SOME bs => SOME (nat_of_bools bs)
-    | NONE => NONE
-  )))`;
-
-
-val _ = Define `
- ((not_bits:(bitU)list ->(bitU)list)=  (MAP not_bit))`;
-
-
-(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*)
-val _ = Define `
- ((binop_list:('a -> 'a -> 'a) -> 'a list -> 'a list -> 'a list) op xs ys=
-   (FOLDR (\ (x, y) acc .  op x y :: acc) [] (list_combine xs ys)))`;
-
-
-val _ = Define `
- ((unsigned_of_bits:(bitU)list ->(int)option) bits=
-   ((case (just_list (MAP bool_of_bitU bits)) of
-      SOME bs => SOME (unsigned_of_bools bs)
-    | NONE => NONE
-  )))`;
-
-
-val _ = Define `
- ((signed_of_bits:(bitU)list ->(int)option) bits=
-   ((case (just_list (MAP bool_of_bitU bits)) of
-      SOME bs => SOME (signed_of_bools bs)
-    | NONE => NONE
-  )))`;
-
-
-(*val int_of_bits : bool -> list bitU -> maybe integer*)
-val _ = Define `
- ((int_of_bits:bool ->(bitU)list ->(int)option) sign bs=  (if sign then signed_of_bits bs else unsigned_of_bits bs))`;
-
-
-val _ = Define `
- ((extz_bits:int ->(bitU)list ->(bitU)list) len bits=  (ext_list B0 len bits))`;
-
-val _ = Define `
- ((exts_bits:int ->(bitU)list ->(bitU)list) len bits=
-   ((case bits of
-    BU :: _ => ext_list BU len bits
-  | B1 :: _ => ext_list B1 len bits
-  | _ => ext_list B0 len bits
-  )))`;
-
-
- val _ = Define `
- ((add_one_bit_ignore_overflow_aux:(bitU)list ->(bitU)list) bits=  ((case bits of
-    [] => []
-  | B0 :: bits => B1 :: bits
-  | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits
-  | BU :: bits => BU :: MAP (\b .  
-  (case (b ) of ( _ ) => BU )) bits
-)))`;
-
-
-val _ = Define `
- ((add_one_bit_ignore_overflow:(bitU)list ->(bitU)list) bits=
-   (REVERSE (add_one_bit_ignore_overflow_aux (REVERSE bits))))`;
-
-
-(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n)
-let bits_of_int len n = exts_bits len (bit_list_of_int n)*)
-val _ = Define `
- ((bits_of_int:int -> int ->(bitU)list) len n=  (MAP bitU_of_bool (bools_of_int len n)))`;
-
-
-(*val arith_op_bits :
-  (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
-val _ = Define `
- ((arith_op_bits:(int -> int -> int) -> bool ->(bitU)list ->(bitU)list ->(bitU)list) op sign l r=
-   ((case (int_of_bits sign l, int_of_bits sign r) of
-      (SOME li, SOME ri) => bits_of_int (int_of_num (LENGTH l)) (op li ri)
-    | (_, _) => repeat [BU] (int_of_num (LENGTH l))
-  )))`;
-
-
-val _ = Define `
- ((char_of_nibble:bitU#bitU#bitU#bitU ->(char)option)= 
-  (\x .  (case x of
-               (B0, B0, B0, B0) => SOME #"0"
-           | (B0, B0, B0, B1) => SOME #"1"
-           | (B0, B0, B1, B0) => SOME #"2"
-           | (B0, B0, B1, B1) => SOME #"3"
-           | (B0, B1, B0, B0) => SOME #"4"
-           | (B0, B1, B0, B1) => SOME #"5"
-           | (B0, B1, B1, B0) => SOME #"6"
-           | (B0, B1, B1, B1) => SOME #"7"
-           | (B1, B0, B0, B0) => SOME #"8"
-           | (B1, B0, B0, B1) => SOME #"9"
-           | (B1, B0, B1, B0) => SOME #"A"
-           | (B1, B0, B1, B1) => SOME #"B"
-           | (B1, B1, B0, B0) => SOME #"C"
-           | (B1, B1, B0, B1) => SOME #"D"
-           | (B1, B1, B1, B0) => SOME #"E"
-           | (B1, B1, B1, B1) => SOME #"F"
-           | _ => NONE
-         )))`;
-
-
- val _ = Define `
- ((hexstring_of_bits:(bitU)list ->((char)list)option) bs=  ((case bs of
-    b1 :: b2 :: b3 :: b4 :: bs =>
-     let n = (char_of_nibble (b1, b2, b3, b4)) in
-     let s = (hexstring_of_bits bs) in
-     (case (n, s) of
-       (SOME n, SOME s) => SOME (n :: s)
-     | _ => NONE
-     )
-  | [] => SOME []
-  | _ => NONE
-  )))`;
-
-
-val _ = Define `
- ((show_bitlist:(bitU)list -> string) bs=
-   ((case hexstring_of_bits bs of
-    SOME s => IMPLODE (#"0" :: (#"x" :: s))
-  | NONE => IMPLODE (#"0" :: (#"b" :: MAP bitU_char bs))
-  )))`;
-
-
-(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*)
-val _ = Define `
- ((subrange_list_inc:'a list -> int -> int -> 'a list) xs i j=
-   (let (toJ,suffix0) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in
-  let (prefix0,fromItoJ) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in
-  fromItoJ))`;
-
-
-(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*)
-val _ = Define `
- ((subrange_list_dec:'a list -> int -> int -> 'a list) xs i j=
-   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
-  subrange_list_inc xs (top - i) (top - j)))`;
-
-
-(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*)
-val _ = Define `
- ((subrange_list:bool -> 'a list -> int -> int -> 'a list) is_inc xs i j=  (if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j))`;
-
-
-(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
-val _ = Define `
- ((update_subrange_list_inc:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'=
-   (let (toJ,suffix) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in
-  let (prefix,fromItoJ0) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in
-  (prefix ++ xs') ++ suffix))`;
-
-
-(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
-val _ = Define `
- ((update_subrange_list_dec:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'=
-   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
-  update_subrange_list_inc xs (top - i) (top - j) xs'))`;
-
-
-(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*)
-val _ = Define `
- ((update_subrange_list:bool -> 'a list -> int -> int -> 'a list -> 'a list) is_inc xs i j xs'=
-   (if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'))`;
-
-
-(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*)
-val _ = Define `
- ((access_list_inc:'a list -> int -> 'a) xs n=  (EL (nat_of_int n) xs))`;
-
-
-(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*)
-val _ = Define `
- ((access_list_dec:'a list -> int -> 'a) xs n=
-   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
-  access_list_inc xs (top - n)))`;
-
-
-(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*)
-val _ = Define `
- ((access_list:bool -> 'a list -> int -> 'a) is_inc xs n=
-   (if is_inc then access_list_inc xs n else access_list_dec xs n))`;
-
-
-(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*)
-val _ = Define `
- ((update_list_inc:'a list -> int -> 'a -> 'a list) xs n x=  (LUPDATE x (nat_of_int n) xs))`;
-
-
-(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*)
-val _ = Define `
- ((update_list_dec:'a list -> int -> 'a -> 'a list) xs n x=
-   (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
-  update_list_inc xs (top - n) x))`;
-
-
-(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*)
-val _ = Define `
- ((update_list:bool -> 'a list -> int -> 'a -> 'a list) is_inc xs n x=
-   (if is_inc then update_list_inc xs n x else update_list_dec xs n x))`;
-
-
-val _ = Define `
- ((extract_only_bit:(bitU)list -> bitU)= 
-  (\x .  (case x of   [] => BU | [e] => e | _ => BU )))`;
-
-
-(*** Machine words *)
-
-(*val length_mword : forall 'a. mword 'a -> integer*)
-
-(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
-val _ = Define `
- ((slice_mword_dec:'a words$word -> int -> int -> 'b words$word) w i j=  (words$word_extract (nat_of_int j) (nat_of_int i) w))`;
-
-
-(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
-val _ = Define `
- ((slice_mword_inc:'a words$word -> int -> int -> 'b words$word) w i j=
-   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
-  slice_mword_dec w (top - i) (top - j)))`;
-
-
-(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*)
-val _ = Define `
- ((slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word) is_inc w i j=  (if is_inc then slice_mword_inc w i j else slice_mword_dec w i j))`;
-
-
-(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-val _ = Define `
- ((update_slice_mword_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=  (words$bit_field_insert (nat_of_int j) (nat_of_int i) w' w))`;
-
-
-(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-val _ = Define `
- ((update_slice_mword_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=
-   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
-  update_slice_mword_dec w (top - i) (top - j) w'))`;
-
-
-(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-val _ = Define `
- ((update_slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word -> 'a words$word) is_inc w i j w'=
-   (if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'))`;
-
-
-(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*)
-val _ = Define `
- ((access_mword_dec:'a words$word -> int -> bitU) w n=  (bitU_of_bool (words$word_bit (nat_of_int n) w)))`;
-
-
-(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*)
-val _ = Define `
- ((access_mword_inc:'a words$word -> int -> bitU) w n=
-   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
-  access_mword_dec w (top - n)))`;
-
-
-(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*)
-val _ = Define `
- ((access_mword:bool -> 'a words$word -> int -> bitU) is_inc w n=
-   (if is_inc then access_mword_inc w n else access_mword_dec w n))`;
-
-
-(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
-val _ = Define `
- ((update_mword_bool_dec:'a words$word -> int -> bool -> 'a words$word) w n b=  ($:+ (nat_of_int n) b w))`;
-
-val _ = Define `
- ((update_mword_dec:'a words$word -> int -> bitU ->('a words$word)option) w n b=  (OPTION_MAP (update_mword_bool_dec w n) (bool_of_bitU b)))`;
-
-
-(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
-val _ = Define `
- ((update_mword_bool_inc:'a words$word -> int -> bool -> 'a words$word) w n b=
-   (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
-  update_mword_bool_dec w (top - n) b))`;
-
-val _ = Define `
- ((update_mword_inc:'a words$word -> int -> bitU ->('a words$word)option) w n b=  (OPTION_MAP (update_mword_bool_inc w n) (bool_of_bitU b)))`;
-
-
-(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
-val _ = Define `
- ((int_of_mword:bool -> 'a words$word -> int) sign w=
-   (if sign then integer_word$w2i w else lem$w2ui w))`;
-
-
-(* Translating between a type level number (itself 'n) and an integer *)
-
-val _ = Define `
- ((size_itself_int:'a itself -> int) x=  (int_of_num (size_itself x)))`;
-
-
-(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n),
-   the actual integer is ignored. *)
-
-(*val make_the_value : forall 'n. integer -> itself 'n*)
-val _ = Define `
- ((make_the_value:int -> 'n itself) _=  the_value)`;
-
-
-(*** Bitvectors *)
-
-val _ = Hol_datatype `
-(*  'a *) Bitvector_class= <|
-  bits_of_method : 'a -> bitU list;
-  (* We allow of_bits to be partial, as not all bitvector representations
-     support undefined bits *)
-  of_bits_method : bitU list ->  'a option;
-  of_bools_method : bool list -> 'a;
-  length_method : 'a -> int;
-  (* of_int: the first parameter specifies the desired length of the bitvector *)
-  of_int_method : int -> int -> 'a;
-  (* Conversion to integers is undefined if any bit is undefined *)
-  unsigned_method : 'a ->  int option;
-  signed_method : 'a ->  int option;
-  (* Lifting of integer operations to bitvectors:  The boolean flag indicates
-     whether to treat the bitvectors as signed (true) or not (false). *)
-  arith_op_bv_method : (int -> int -> int) -> bool -> 'a -> 'a -> 'a
-|>`;
-
-
-(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*)
-val _ = Define `
- ((of_bits_failwith:'a Bitvector_class ->(bitU)list -> 'a)dict_Sail_values_Bitvector_a bits=  (maybe_failwith (
-  dict_Sail_values_Bitvector_a.of_bits_method bits)))`;
-
-
-val _ = Define `
- ((int_of_bv:'a Bitvector_class -> bool -> 'a ->(int)option)dict_Sail_values_Bitvector_a sign=  (if sign then  
-  dict_Sail_values_Bitvector_a.signed_method else  dict_Sail_values_Bitvector_a.unsigned_method))`;
-
-
-val _ = Define `
-((instance_Sail_values_Bitvector_list_dict:'a BitU_class ->('a list)Bitvector_class)dict_Sail_values_BitU_a= (<|
-
-  bits_of_method := (\ v. MAP  
-  dict_Sail_values_BitU_a.to_bitU_method v);
-
-  of_bits_method := (\ v. SOME (MAP  
-  dict_Sail_values_BitU_a.of_bitU_method v));
-
-  of_bools_method := (\ v. MAP  
-  dict_Sail_values_BitU_a.of_bitU_method (MAP bitU_of_bool v));
-
-  length_method := (\ xs. int_of_num (LENGTH xs));
-
-  of_int_method := (\ len n. MAP  
-  dict_Sail_values_BitU_a.of_bitU_method (bits_of_int len n));
-
-  unsigned_method := (\ v. unsigned_of_bits (MAP  
-  dict_Sail_values_BitU_a.to_bitU_method v));
-
-  signed_method := (\ v. signed_of_bits (MAP  
-  dict_Sail_values_BitU_a.to_bitU_method v));
-
-  arith_op_bv_method := (\ op sign l r. MAP  
-  dict_Sail_values_BitU_a.of_bitU_method (arith_op_bits op sign (MAP  
-  dict_Sail_values_BitU_a.to_bitU_method l) (MAP  dict_Sail_values_BitU_a.to_bitU_method r)))|>))`;
-
-
-val _ = Define `
-((instance_Sail_values_Bitvector_Machine_word_mword_dict:('a words$word)Bitvector_class)= (<|
-
-  bits_of_method := (\ v. MAP bitU_of_bool (bitstring$w2v v));
-
-  of_bits_method := (\ v. OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU v)));
-
-  of_bools_method := (\ v. bitstring$v2w v);
-
-  length_method := (\ v. int_of_num (words$word_len v));
-
-  of_int_method := (\i n .  
-  (case (i ,n ) of ( _ , n ) => integer_word$i2w n ));
-
-  unsigned_method := (\ v. SOME (lem$w2ui v));
-
-  signed_method := (\ v. SOME (integer_word$w2i v));
-
-  arith_op_bv_method := (\ op sign l r. integer_word$i2w (op (int_of_mword sign l) (int_of_mword sign r)))|>))`;
-
-
-val _ = Define `
- ((access_bv_inc:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail_values_Bitvector_a v n=  (access_list T  (
-  dict_Sail_values_Bitvector_a.bits_of_method v) n))`;
-
-val _ = Define `
- ((access_bv_dec:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail_values_Bitvector_a v n=  (access_list F (
-  dict_Sail_values_Bitvector_a.bits_of_method v) n))`;
-
-
-val _ = Define `
- ((update_bv_inc:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail_values_Bitvector_a v n b=  (update_list T  (
-  dict_Sail_values_Bitvector_a.bits_of_method v) n b))`;
-
-val _ = Define `
- ((update_bv_dec:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail_values_Bitvector_a v n b=  (update_list F (
-  dict_Sail_values_Bitvector_a.bits_of_method v) n b))`;
-
-
-val _ = Define `
- ((subrange_bv_inc:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail_values_Bitvector_a v i j=  (subrange_list T  (
-  dict_Sail_values_Bitvector_a.bits_of_method v) i j))`;
-
-val _ = Define `
- ((subrange_bv_dec:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail_values_Bitvector_a v i j=  (subrange_list F (
-  dict_Sail_values_Bitvector_a.bits_of_method v) i j))`;
-
-
-val _ = Define `
- ((update_subrange_bv_inc:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v'=  (update_subrange_list T  (
-  dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`;
-
-val _ = Define `
- ((update_subrange_bv_dec:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v'=  (update_subrange_list F (
-  dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`;
-
-
-(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
-val _ = Define `
- ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v=  (extz_bits n (
-  dict_Sail_values_Bitvector_a.bits_of_method v)))`;
-
-
-(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
-val _ = Define `
- ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v=  (exts_bits n (
-  dict_Sail_values_Bitvector_a.bits_of_method v)))`;
-
-
-(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*)
-val _ = Define `
- ((string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a v=  (show_bitlist (
-  dict_Sail_values_Bitvector_a.bits_of_method v)))`;
-
-
-(*** Bytes and addresses *)
-
-val _ = type_abbrev( "memory_byte" , ``: bitU list``);
-
-(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*)
- val _ = Define `
- ((byte_chunks:'a list ->(('a list)list)option) bs=  ((case bs of
-    [] => SOME []
-  | a::b::c::d::e::f::g::h::rest =>
-     OPTION_BIND (byte_chunks rest) (\ rest .  SOME ([a;b;c;d;e;f;g;h] :: rest))
-  | _ => NONE
-)))`;
-
-
-(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*)
-val _ = Define `
- ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail_values_Bitvector_a bs=  (byte_chunks (
-  dict_Sail_values_Bitvector_a.bits_of_method bs)))`;
-
-
-(*val bits_of_bytes : list memory_byte -> list bitU*)
-val _ = Define `
- ((bits_of_bytes:((bitU)list)list ->(bitU)list) bs=  (FLAT (MAP (\ v. MAP (\ b. b) v) bs)))`;
-
-
-val _ = Define `
- ((mem_bytes_of_bits:'a Bitvector_class -> 'a ->(((bitU)list)list)option)dict_Sail_values_Bitvector_a bs=  (OPTION_MAP REVERSE (bytes_of_bits 
-  dict_Sail_values_Bitvector_a bs)))`;
-
-val _ = Define `
- ((bits_of_mem_bytes:((bitU)list)list ->(bitU)list) bs=  (bits_of_bytes (REVERSE bs)))`;
-
-
-(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
-let bitv_of_byte_lifteds v =
-  foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v
-
-val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
-let bitv_of_bytes v =
-  foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v
-
-val byte_lifteds_of_bitv : list bitU -> list byte_lifted
-let byte_lifteds_of_bitv bits =
-  let bits = List.map bit_lifted_of_bitU bits in
-  byte_lifteds_of_bit_lifteds bits
-
-val bytes_of_bitv : list bitU -> list byte
-let bytes_of_bitv bits =
-  let bits = List.map bit_of_bitU bits in
-  bytes_of_bits bits
-
-val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
-let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits
-
-val bit_lifteds_of_bitv : list bitU -> list bit_lifted
-let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v
-
-
-val address_lifted_of_bitv : list bitU -> address_lifted
-let address_lifted_of_bitv v =
-  let byte_lifteds = byte_lifteds_of_bitv v in
-  let maybe_address_integer =
-    match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
-    | Just bs -> Just (integer_of_byte_list bs)
-    | _ -> Nothing
-    end in
-  Address_lifted byte_lifteds maybe_address_integer
-
-val bitv_of_address_lifted : address_lifted -> list bitU
-let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs
-
-val address_of_bitv : list bitU -> address
-let address_of_bitv v =
-  let bytes = bytes_of_bitv v in
-  address_of_byte_list bytes*)
-
- val reverse_endianness_list_defn = Hol_defn "reverse_endianness_list" `
- ((reverse_endianness_list:'a list -> 'a list) bits=
-   (if LENGTH bits <=( 8 : num) then bits else
-    reverse_endianness_list (drop_list(( 8 : int)) bits) ++ take_list(( 8 : int)) bits))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn reverse_endianness_list_defn;
-
-
-(*** Registers *)
-
-(*type register_field = string
-type register_field_index = string * (integer * integer) (* name, start and end *)
-
-type register =
-  | Register of string * (* name *)
-                integer * (* length *)
-                integer * (* start index *)
-                bool * (* is increasing *)
-                  list register_field_index
-  | UndefinedRegister of integer (* length *)
-  | RegisterPair of register * register*)
-
-val _ = Hol_datatype `
-(* ( 'a_regstate, 'b_regval, 'c_a) *) register_ref =
-  <| name : string;
-     (*is_inc : bool;*)
-     read_from :'a_regstate -> 'c_a;
-     write_to :'c_a -> 'a_regstate -> 'a_regstate;
-     of_regval :'b_regval -> 'c_a option;
-     regval_of :'c_a -> 'b_regval |>`;
-
-
-(* Register accessors: pair of functions for reading and writing register values *)
-val _ = type_abbrev((* ( 'regstate, 'regval) *) "register_accessors" , ``:
-  ((string -> 'regstate ->  'regval option) #
-   (string -> 'regval -> 'regstate ->  'regstate option))``);
-
-val _ = Hol_datatype `
-(* ( 'a_regtype, 'b_a) *) field_ref =
-  <| field_name : string;
-     field_start : int;
-     field_is_inc : bool;
-     get_field :'a_regtype -> 'b_a;
-     set_field :'a_regtype -> 'b_a -> 'a_regtype |>`;
-
-
-(*let name_of_reg = function
-  | Register name _ _ _ _ -> name
-  | UndefinedRegister _ -> failwith "name_of_reg UndefinedRegister"
-  | RegisterPair _ _ -> failwith "name_of_reg RegisterPair"
-end
-
-let size_of_reg = function
-  | Register _ size _ _ _ -> size
-  | UndefinedRegister size -> size
-  | RegisterPair _ _ -> failwith "size_of_reg RegisterPair"
-end
-
-let start_of_reg = function
-  | Register _ _ start _ _ -> start
-  | UndefinedRegister _ -> failwith "start_of_reg UndefinedRegister"
-  | RegisterPair _ _ -> failwith "start_of_reg RegisterPair"
-end
-
-let is_inc_of_reg = function
-  | Register _ _ _ is_inc _ -> is_inc
-  | UndefinedRegister _ -> failwith "is_inc_of_reg UndefinedRegister"
-  | RegisterPair _ _ -> failwith "in_inc_of_reg RegisterPair"
-end
-
-let dir_of_reg = function
-  | Register _ _ _ is_inc _ -> dir_of_bool is_inc
-  | UndefinedRegister _ -> failwith "dir_of_reg UndefinedRegister"
-  | RegisterPair _ _ -> failwith "dir_of_reg RegisterPair"
-end
-
-let size_of_reg_nat reg = natFromInteger (size_of_reg reg)
-let start_of_reg_nat reg = natFromInteger (start_of_reg reg)
-
-val register_field_indices_aux : register -> register_field -> maybe (integer * integer)
-let rec register_field_indices_aux register rfield =
-  match register with
-  | Register _ _ _ _ rfields -> List.lookup rfield rfields
-  | RegisterPair r1 r2 ->
-      let m_indices = register_field_indices_aux r1 rfield in
-      if isJust m_indices then m_indices else register_field_indices_aux r2 rfield
-  | UndefinedRegister _ -> Nothing
-  end
-
-val register_field_indices : register -> register_field -> integer * integer
-let register_field_indices register rfield =
-  match register_field_indices_aux register rfield with
-  | Just indices -> indices
-  | Nothing -> failwith "Invalid register/register-field combination"
-  end
-
-let register_field_indices_nat reg regfield=
-  let (i,j) = register_field_indices reg regfield in
-  (natFromInteger i,natFromInteger j)*)
-
-(*let rec external_reg_value reg_name v =
-  let (internal_start, external_start, direction) =
-    match reg_name with
-     | Reg _ start size dir ->
-        (start, (if dir = D_increasing then start else (start - (size +1))), dir)
-     | Reg_slice _ reg_start dir (slice_start, _) ->
-        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
-         slice_start, dir)
-     | Reg_field _ reg_start dir _ (slice_start, _) ->
-        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
-         slice_start, dir)
-     | Reg_f_slice _ reg_start dir _ _ (slice_start, _) ->
-        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
-         slice_start, dir)
-     end in
-  let bits = bit_lifteds_of_bitv v in
-  <| rv_bits           = bits;
-     rv_dir            = direction;
-     rv_start          = external_start;
-     rv_start_internal = internal_start |>
-
-val internal_reg_value : register_value -> list bitU
-let internal_reg_value v =
-  List.map bitU_of_bit_lifted v.rv_bits
-         (*(integerFromNat v.rv_start_internal)
-         (v.rv_dir = D_increasing)*)
-
-
-let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) =
-  match d with
-  (*This is the case the thread/concurrecny model expects, so no change needed*)
-  | D_increasing -> (i,j)
-  | D_decreasing -> let slice_i = start - i in
-                    let slice_j = (i - j) + slice_i in
-                    (slice_i,slice_j)
-  end *)
-
-(* TODO
-let external_reg_whole r =
-  Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc)
-
-let external_reg_slice r (i,j) =
-  let start = natFromInteger r.start in
-  let dir = dir_of_bool r.is_inc in
-  Reg_slice (r.name) start dir (external_slice dir start (i,j))
-
-let external_reg_field_whole reg rfield =
-  let (m,n) = register_field_indices_nat reg rfield in
-  let start = start_of_reg_nat reg in
-  let dir = dir_of_reg reg in
-  Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
-
-let external_reg_field_slice reg rfield (i,j) =
-  let (m,n) = register_field_indices_nat reg rfield in
-  let start = start_of_reg_nat reg in
-  let dir = dir_of_reg reg in
-  Reg_f_slice (name_of_reg reg) start dir rfield
-              (external_slice dir start (m,n))
-              (external_slice dir start (i,j))*)
-
-(*val external_mem_value : list bitU -> memory_value
-let external_mem_value v =
-  byte_lifteds_of_bitv v $> List.reverse
-
-val internal_mem_value : memory_value -> list bitU
-let internal_mem_value bytes =
-  List.reverse bytes $> bitv_of_byte_lifteds*)
-
-
-(*val foreach : forall 'a 'vars.
-  (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*)
- val _ = Define `
- ((foreach:'a list -> 'vars ->('a -> 'vars -> 'vars) -> 'vars) l vars body=
-   ((case l of
-      [] => vars
-    | (x :: xs) => foreach xs (body x vars) body
-  )))`;
-
-
-(*val index_list : integer -> integer -> integer -> list integer*)
- val index_list_defn = Hol_defn "index_list" `
- ((index_list:int -> int -> int ->(int)list) from to step=
-   (if ((step >( 0 : int)) /\ (from <= to)) \/ ((step <( 0 : int)) /\ (to <= from)) then
-    from :: index_list (from + step) to step
-  else []))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn index_list_defn;
-
-(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
- val while_defn = Hol_defn "while" `
- ((while:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body=
-   (if cond vars then while (body vars) cond body else vars))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn while_defn;
-
-(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
- val until_defn = Hol_defn "until" `
- ((until:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body=
-   (let vars = (body vars) in
-  if cond vars then vars else until (body vars) cond body))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn until_defn;
-
-
-(* convert numbers unsafely to naturals *)
-
-val _ = Hol_datatype `
-(*  'a *) ToNatural_class= <| toNatural_method : 'a -> num |>`;
-
-(* eta-expanded for Isabelle output, otherwise it breaks *)
-val _ = Define `
-((instance_Sail_values_ToNatural_Num_integer_dict:(int)ToNatural_class)= (<|
-
-  toNatural_method := (\ n .  Num (ABS n))|>))`;
-
-val _ = Define `
-((instance_Sail_values_ToNatural_Num_int_dict:(int)ToNatural_class)= (<|
-
-  toNatural_method := (\ n .  ((Num (ABS n)):num))|>))`;
-
-val _ = Define `
-((instance_Sail_values_ToNatural_nat_dict:(num)ToNatural_class)= (<|
-
-  toNatural_method := (\ n .  ( n:num))|>))`;
-
-val _ = Define `
-((instance_Sail_values_ToNatural_Num_natural_dict:(num)ToNatural_class)= (<|
-
-  toNatural_method := (\ n .  n)|>))`;
-
-
-val _ = Define `
- ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5)=
-   (dict_Sail_values_ToNatural_d.toNatural_method n1, dict_Sail_values_ToNatural_c.toNatural_method n2, dict_Sail_values_ToNatural_b.toNatural_method n3, dict_Sail_values_ToNatural_a.toNatural_method n4, dict_Sail_values_ToNatural_e.toNatural_method n5))`;
-
-
-(* Let the following types be generated by Sail per spec, using either bitlists
-   or machine words as bitvector representation *)
-(*type regfp =
-  | RFull of (string)
-  | RSlice of (string * integer * integer)
-  | RSliceBit of (string * integer)
-  | RField of (string * string)
-
-type niafp =
-  | NIAFP_successor
-  | NIAFP_concrete_address of vector bitU
-  | NIAFP_indirect_address
-
-(* only for MIPS *)
-type diafp =
-  | DIAFP_none
-  | DIAFP_concrete of vector bitU
-  | DIAFP_reg of regfp
-
-let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function
-  | RFull name ->
-     let (start,length,direction,_) = reg_info name Nothing in
-     Reg name start length direction
-  | RSlice (name,i,j) ->
-     let i = natFromInteger i in
-     let j = natFromInteger j in
-     let (start,length,direction,_) = reg_info name Nothing in
-     let slice = external_slice direction start (i,j) in
-     Reg_slice name start direction slice
-  | RSliceBit (name,i) ->
-     let i = natFromInteger i in
-     let (start,length,direction,_) = reg_info name Nothing in
-     let slice = external_slice direction start (i,i) in
-     Reg_slice name start direction slice
-  | RField (name,field_name) ->
-     let (start,length,direction,span) = reg_info name (Just field_name) in
-     let slice = external_slice direction start span in
-     Reg_field name start direction field_name slice
-end
-
-let niafp_to_nia reginfo = function
-  | NIAFP_successor -> NIA_successor
-  | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v)
-  | NIAFP_indirect_address -> NIA_indirect_address
-end
-
-let diafp_to_dia reginfo = function
-  | DIAFP_none -> DIA_none
-  | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v)
-  | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r)
-end
-*)
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/stateAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/stateAuxiliaryScript.sml
deleted file mode 100644
index c8269750..00000000
--- a/snapshots/hol4/sail/lib/hol/stateAuxiliaryScript.sml
+++ /dev/null
@@ -1,61 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/state.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_valuesTheory state_monadTheory stateTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-open lemLib;
-(* val _ = lemLib.run_interactive := true; *)
-val _ = new_theory "stateAuxiliary"
-
-
-(****************************************************)
-(*                                                  *)
-(* Termination Proofs                               *)
-(*                                                  *)
-(****************************************************)
-
-(* val gst = Defn.tgoal_no_defn (iterS_aux_def, iterS_aux_ind) *)
-val (iterS_aux_rw, iterS_aux_ind_rw) =
-  Defn.tprove_no_defn ((iterS_aux_def, iterS_aux_ind),
-    WF_REL_TAC`measure (LENGTH o SND o SND)` \\ rw[]
-  )
-val iterS_aux_rw = save_thm ("iterS_aux_rw", iterS_aux_rw);
-val iterS_aux_ind_rw = save_thm ("iterS_aux_ind_rw", iterS_aux_ind_rw);
-
-
-(* val gst = Defn.tgoal_no_defn (foreachS_def, foreachS_ind) *)
-val (foreachS_rw, foreachS_ind_rw) =
-  Defn.tprove_no_defn ((foreachS_def, foreachS_ind),
-    WF_REL_TAC`measure (LENGTH o FST)` \\ rw[]
-  )
-val foreachS_rw = save_thm ("foreachS_rw", foreachS_rw);
-val foreachS_ind_rw = save_thm ("foreachS_ind_rw", foreachS_ind_rw);
-
-
-(*
-These are unprovable.
-
-(* val gst = Defn.tgoal_no_defn (whileS_def, whileS_ind) *)
-val (whileS_rw, whileS_ind_rw) =
-  Defn.tprove_no_defn ((whileS_def, whileS_ind),
-    cheat (* the termination proof *)
-  )
-val whileS_rw = save_thm ("whileS_rw", whileS_rw);
-val whileS_ind_rw = save_thm ("whileS_ind_rw", whileS_ind_rw);
-
-
-(* val gst = Defn.tgoal_no_defn (untilS_def, untilS_ind) *)
-val (untilS_rw, untilS_ind_rw) =
-  Defn.tprove_no_defn ((untilS_def, untilS_ind),
-    cheat (* the termination proof *)
-  )
-val untilS_rw = save_thm ("untilS_rw", untilS_rw);
-val untilS_ind_rw = save_thm ("untilS_ind_rw", untilS_ind_rw);
-*)
-
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/stateScript.sml b/snapshots/hol4/sail/lib/hol/stateScript.sml
deleted file mode 100644
index ec3e6c26..00000000
--- a/snapshots/hol4/sail/lib/hol/stateScript.sml
+++ /dev/null
@@ -1,129 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/state.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_valuesTheory state_monadTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "state"
-
-(*open import Pervasives_extra*)
-(*open import Sail_values*)
-(*open import State_monad*)
-(*open import {isabelle} `State_monad_lemmas`*)
-
-(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
- val iterS_aux_defn = Hol_defn "iterS_aux" `
- ((iterS_aux:int ->(int -> 'a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) i f xs=  ((case xs of
-    x :: xs => seqS (f i x) (iterS_aux (i +( 1 : int)) f xs)
-  | [] => returnS () 
-  )))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn iterS_aux_defn;
-
-(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
-val _ = Define `
- ((iteriS:(int -> 'a ->('rv,(unit),'e)monadS) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs=  (iterS_aux(( 0 : int)) f xs))`;
-
-
-(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
-val _ = Define `
- ((iterS:('a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs=  (iteriS (\i x .  
-  (case (i ,x ) of ( _ , x ) => f x )) xs))`;
-
-
-(*val foreachS : forall 'a 'rv 'vars 'e.
-  list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
- val foreachS_defn = Hol_defn "foreachS" `
- ((foreachS:'a list -> 'vars ->('a -> 'vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) xs vars body=  ((case xs of
-    [] => returnS vars
-  | x :: xs => bindS
-     (body x vars) (\ vars . 
-     foreachS xs vars body)
-)))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreachS_defn;
-
-(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
-val _ = Define `
- ((and_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r=  (bindS l (\ l .  if l then r else returnS F)))`;
-
-
-(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
-val _ = Define `
- ((or_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r=  (bindS l (\ l .  if l then returnS T else r)))`;
-
-
-(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
-val _ = Define `
- ((bool_of_bitU_fail:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= 
-  (\x .  (case x of
-               B0 => returnS F
-           | B1 => returnS T
-           | BU => failS "bool_of_bitU"
-         )))`;
-
-
-(*val bool_of_bitU_oracleS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
-val _ = Define `
- ((bool_of_bitU_oracleS:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= 
-  (\x .  (case x of
-               B0 => returnS F
-           | B1 => returnS T
-           | BU => undefined_boolS () 
-         )))`;
-
-
-(*val bools_of_bits_oracleS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*)
-val _ = Define `
- ((bools_of_bits_oracleS:(bitU)list -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) bits=
-   (foreachS bits []
-    (\ b bools .  bindS
-      (bool_of_bitU_oracleS b) (\ b . 
-      returnS (bools ++ [b])))))`;
-
-
-(*val of_bits_oracleS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
-val _ = Define `
- ((of_bits_oracleS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail_values_Bitvector_a bits=  (bindS
-  (bools_of_bits_oracleS bits) (\ bs . 
-  returnS (dict_Sail_values_Bitvector_a.of_bools_method bs))))`;
-
-
-(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
-val _ = Define `
- ((of_bits_failS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail_values_Bitvector_a bits=  (maybe_failS "of_bits" (
-  dict_Sail_values_Bitvector_a.of_bits_method bits)))`;
-
-
-(*val mword_oracleS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*)
-val _ = Define `
- ((mword_oracleS:unit -> 'rv sequential_state ->((('a words$word),'e)result#'rv sequential_state)set) () =  (bindS
-  (bools_of_bits_oracleS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . 
-  returnS (bitstring$v2w bs))))`;
-
-
-
-(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
-                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
- val whileS_defn = Hol_defn "whileS" `
- ((whileS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s=
-   (( bindS(cond vars) (\ cond_val s' . 
-  if cond_val then
-    ( bindS(body vars) (\ vars s'' .  whileS vars cond body s'')) s'
-  else returnS vars s')) s))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn whileS_defn;
-
-(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
-                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
- val untilS_defn = Hol_defn "untilS" `
- ((untilS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s=
-   (( bindS(body vars) (\ vars s' . 
-  ( bindS(cond vars) (\ cond_val s'' . 
-  if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s))`;
-
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn untilS_defn;
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/lib/hol/state_monadScript.sml b/snapshots/hol4/sail/lib/hol/state_monadScript.sml
deleted file mode 100644
index ba687761..00000000
--- a/snapshots/hol4/sail/lib/hol/state_monadScript.sml
+++ /dev/null
@@ -1,367 +0,0 @@
-(*Generated by Lem from ../../src/gen_lib/state_monad.lem.*)
-open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_valuesTheory sail_instr_kindsTheory;
-
-val _ = numLib.prefer_num();
-
-
-
-val _ = new_theory "state_monad"
-
-(*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-
-(* 'a is result type *)
-
-val _ = type_abbrev( "memstate" , ``: (int, memory_byte) fmap``);
-val _ = type_abbrev( "tagstate" , ``: (int, bitU) fmap``);
-(* type regstate = map string (vector bitU) *)
-
-val _ = Hol_datatype `
-(*  'regs *) sequential_state =
-  <| regstate : 'regs;
-     memstate : memstate;
-     tagstate : tagstate;
-     write_ea :  (write_kind # int # int)option;
-     last_exclusive_operation_was_load : bool;
-     (* Random bool generator for use as an undefined bit oracle *)
-     next_bool : num -> (bool # num);
-     seed : num |>`;
-
-
-(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*)
-val _ = Define `
- ((init_state:'regs ->(num -> bool#num) -> num -> 'regs sequential_state) regs o1 s=
-   (<| regstate := regs;
-     memstate := FEMPTY;
-     tagstate := FEMPTY;
-     write_ea := NONE;
-     last_exclusive_operation_was_load := F;
-     next_bool := o1;
-     seed := s |>))`;
-
-
-val _ = Hol_datatype `
- ex =
-    Failure of string
-  | Throw of 'e`;
-
-
-val _ = Hol_datatype `
- result =
-    Value of 'a
-  | Ex of ( 'e ex)`;
-
-
-(* State, nondeterminism and exception monad with result value type 'a
-   and exception type 'e. *)
-val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_e) *) "monadS" , ``:'a_regs sequential_state -> (('b_a,'c_e)result #'a_regs sequential_state) set``);
-
-(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((returnS:'a -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) a s=  ({(Value a,s)}))`;
-
-
-(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*)
-val _ = Define `
- ((bindS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) ->('a -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m f (s : 'regs sequential_state)=
-   (BIGUNION (IMAGE (\x .  
-  (case x of   (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s))))`;
-
-
-(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*)
-val _ = Define `
- ((seqS:('regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) ->('regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m n=  (bindS m (\u .  
-  (case (u ) of ( (_ : unit) ) => n ))))`;
-
-
-(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((chooseS:'a set -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) xs s=  (IMAGE (\ x .  (Value x, s)) xs))`;
-
-
-(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((readS:('regs sequential_state -> 'a) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) f=  (\ s .  returnS (f s) s))`;
-
-
-(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*)
-val _ = Define `
- ((updateS:('regs sequential_state -> 'regs sequential_state) -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) f=  (\ s .  returnS ()  (f s)))`;
-
-
-(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((failS:string -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg s=  ({(Ex (Failure msg), s)}))`;
-
-
-(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*)
-val _ = Define `
- ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () =  (bindS
-  (readS (\ s .  s.next_bool (s.seed))) (\ (b, seed) .  seqS
-  (updateS (\ s .  ( s with<| seed := seed |>)))
-  (returnS b))))`;
-
-
-(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((exitS:unit -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) () =  (failS "exit"))`;
-
-
-(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((throwS:'e -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) e s=  ({(Ex (Throw e), s)}))`;
-
-
-(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) ->  monadS 'regs 'a 'e2*)
-val _ = Define `
- ((try_catchS:('regs sequential_state ->(('a,'e1)result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) m h s=
-   (BIGUNION (IMAGE (\x .  
-  (case x of
-        (Value a, s') => returnS a s'
-    | (Ex (Throw e), s') => h e s'
-    | (Ex (Failure msg), s') => {(Ex (Failure msg), s')}
-  )) (m s))))`;
-
-
-(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*)
-val _ = Define `
- ((assert_expS:bool -> string -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) exp msg=  (if exp then returnS ()  else failS msg))`;
-
-
-(* For early return, we abuse exceptions by throwing and catching
-   the return value. The exception type is "either 'r 'e", where "Right e"
-   represents a proper exception and "Left r" an early return of value "r". *)
-val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_r, 'd_e) *) "monadRS" , ``:('a_regs,'b_a, (('c_r,'d_e)sum)) monadS``);
-
-(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*)
-val _ = Define `
- ((early_returnS:'r -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) r=  (throwS (INL r)))`;
-
-
-(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((catch_early_returnS:('regs sequential_state ->(('a,(('a,'e)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) m=
-   (try_catchS m
-    (\x .  (case x of   INL a => returnS a | INR e => throwS e ))))`;
-
-
-(* Lift to monad with early return by wrapping exceptions *)
-(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*)
-val _ = Define `
- ((liftRS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) m=  (try_catchS m (\ e .  throwS (INR e))))`;
-
-
-(* Catch exceptions in the presence of early returns *)
-(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) ->  monadRS 'regs 'a 'r 'e2*)
-val _ = Define `
- ((try_catchRS:('regs sequential_state ->(('a,(('r,'e1)sum))result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) m h=
-   (try_catchS m
-    (\x .  (case x of   INL r => throwS (INL r) | INR e => h e ))))`;
-
-
-(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((maybe_failS:string -> 'a option -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg= 
-  (\x .  (case x of   SOME a => returnS a | NONE => failS msg )))`;
-
-
-(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*)
-val _ = Define `
- ((read_tagS:'a Bitvector_class -> 'a ->('regs,(bitU),'e)monadS)dict_Sail_values_Bitvector_a addr=  (bindS
-  (maybe_failS "unsigned" (
-  dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . 
-  readS (\ s .  option_CASE (FLOOKUP s.tagstate addr) B0 I))))`;
-
-
-(* Read bytes from memory and return in little endian order *)
-(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*)
-val _ = Define `
- ((read_mem_bytesS:'a Bitvector_class -> read_kind -> 'a -> num ->('regs,((memory_byte)list),'e)monadS)dict_Sail_values_Bitvector_a read_kind addr sz=  (bindS
-  (maybe_failS "unsigned" (
-  dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . 
-  let sz = (int_of_num sz) in
-  let addrs = (index_list addr ((addr+sz)-( 1 : int))(( 1 : int))) in  
-  let read_byte = (\ s addr .  FLOOKUP s.memstate addr) in
-  bindS (readS (\ s .  just_list (MAP (read_byte s) addrs)))
-    (\x .  (case x of
-                 SOME mem_val => seqS
-                                   (updateS
-                                      (\ s . 
-                                       if read_is_exclusive read_kind then
-                                         ( s with<| last_exclusive_operation_was_load := T |>)
-                                       else s)) (returnS mem_val)
-             | NONE => failS "read_memS"
-           )))))`;
-
-
-(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*)
-val _ = Define `
- ((read_memS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz=  (bindS
-  (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . 
-  maybe_failS "bits_of_mem_bytes" (
-  dict_Sail_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes)))))`;
-
-
-(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*)
-val _ = Define `
- ((excl_resultS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () =  (bindS
-  (readS (\ s .  s.last_exclusive_operation_was_load)) (\ excl_load .  seqS
-  (updateS (\ s .  ( s with<| last_exclusive_operation_was_load := F |>)))
-  (chooseS (if excl_load then {F; T} else {F})))))`;
-
-
-(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*)
-val _ = Define `
- ((write_mem_eaS:'a Bitvector_class -> write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail_values_Bitvector_a write_kind addr sz=  (bindS
-  (maybe_failS "unsigned" (
-  dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . 
-  let sz = (int_of_num sz) in
-  updateS (\ s .  ( s with<| write_ea := (SOME (write_kind, addr, sz)) |>)))))`;
-
-
-(* Write little-endian list of bytes to previously announced address *)
-(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*)
-val _ = Define `
- ((write_mem_bytesS:((bitU)list)list -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) v=  (bindS
-  (readS (\ s .  s.write_ea)) (\x .  
-  (case x of
-        NONE => failS "write ea has not been announced yet"
-    | SOME (_, addr, sz) =>
-  let addrs = (index_list addr ((addr + sz) - ( 1 : int)) (( 1 : int))) in
-  (*let v = external_mem_value (bits_of v) in*)
-  let a_v = (lem_list$list_combine addrs v) in
-  let write_byte = (\mem p .  (case (mem ,p ) of
-                                  ( mem , (addr, v) ) => mem  |+ ( addr ,  
-                                                        v )
-                              )) in
-  seqS
-    (updateS
-       (\ s .  ( s with<| memstate := (FOLDL write_byte s.memstate a_v) |>)))
-    (returnS T)
-  ))))`;
-
-
-(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*)
-val _ = Define `
- ((write_mem_valS:'a Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a v=  ((case mem_bytes_of_bits 
-  dict_Sail_values_Bitvector_a v of
-    SOME v => write_mem_bytesS v
-  | NONE => failS "write_mem_val"
-)))`;
-
-
-(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*)
-val _ = Define `
- ((write_tagS:'a Bitvector_class -> 'a -> bitU ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a addr t=  (bindS
-   (maybe_failS "unsigned" (
-  dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr .  seqS
-   (updateS (\ s .  ( s with<| tagstate := (s.tagstate |+ (addr, t)) |>)))
-   (returnS T))))`;
-
-
-(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*)
-val _ = Define `
- ((read_regS:('regs,'rv,'a)register_ref -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) reg=  (readS (\ s .  reg.read_from s.regstate)))`;
-
-
-(* TODO
-let read_reg_range reg i j state =
-  let v = slice (get_reg state (name_of_reg reg)) i j in
-  [(Value (vec_to_bvec v),state)]
-let read_reg_bit reg i state =
-  let v = access (get_reg state (name_of_reg reg)) i in
-  [(Value v,state)]
-let read_reg_field reg regfield =
-  let (i,j) = register_field_indices reg regfield in
-  read_reg_range reg i j
-let read_reg_bitfield reg regfield =
-  let (i,_) = register_field_indices reg regfield in
-  read_reg_bit reg i *)
-
-(*val read_regvalS : forall 'regs 'rv 'e.
-  register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*)
-val _ = Define `
- ((read_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'regs sequential_state ->(('rv,'e)result#'regs sequential_state)set) (read, _) reg=  (bindS
-  (readS (\ s .  read reg s.regstate)) (\x .  
-  (case x of
-        SOME v => returnS v
-    | NONE => failS ( STRCAT "read_regvalS " reg)
-  ))))`;
-
-
-(*val write_regvalS : forall 'regs 'rv 'e.
-  register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*)
-val _ = Define `
- ((write_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'rv -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) (_, write) reg v=  (bindS
-  (readS (\ s .  write reg v s.regstate)) (\x .  
-  (case x of
-        SOME rs' => updateS (\ s .  ( s with<| regstate := rs' |>))
-    | NONE => failS ( STRCAT "write_regvalS " reg)
-  ))))`;
-
-
-(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*)
-val _ = Define `
- ((write_regS:('regs,'rv,'a)register_ref -> 'a -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) reg v=
-   (updateS (\ s .  ( s with<| regstate := (reg.write_to v s.regstate) |>))))`;
-
-
-(* TODO
-val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
-let update_reg reg f v state =
-  let current_value = get_reg state reg in
-  let new_value = f current_value v in
-  [(Value (), set_reg state reg new_value)]
-
-let write_reg_field reg regfield = update_reg reg regfield.set_field
-
-val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
-let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
-let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
-
-let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
-let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
-
-let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
-let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
-
-let update_reg_field_range regfield i j reg_val new_val =
-  let current_field_value = regfield.get_field reg_val in
-  let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
-  regfield.set_field reg_val new_field_value
-let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
-
-let update_reg_field_pos regfield i reg_val x =
-  let current_field_value = regfield.get_field reg_val in
-  let new_field_value = update_list regfield.field_is_inc current_field_value i x in
-  regfield.set_field reg_val new_field_value
-let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
-
-let update_reg_field_bit regfield i reg_val bit =
-  let current_field_value = regfield.get_field reg_val in
-  let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
-  regfield.set_field reg_val new_field_value
-let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
-
-(* TODO Add Show typeclass for value and exception type *)
-(*val show_result : forall 'a 'e. result 'a 'e -> string*)
-val _ = Define `
- ((show_result:('a,'e)result -> string)= 
-  (\x .  (case x of
-               Value _ => "Value ()"
-           | Ex (Failure msg) => STRCAT "Failure " msg
-           | Ex (Throw _) => "Throw"
-         )))`;
-
-
-(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*)
-val _ = Define `
- ((prerr_results:(('a,'e)result#'s)set -> unit) rs=
-   (let _ = (IMAGE (\p .  
-  (case (p ) of ( (r, _) ) => let _ = (prerr_endline (show_result r)) in ()  )) rs) in
-  () ))`;
-
-val _ = export_theory()
-
diff --git a/snapshots/hol4/sail/mips/Holmakefile b/snapshots/hol4/sail/mips/Holmakefile
new file mode 100644
index 00000000..a31bfd4f
--- /dev/null
+++ b/snapshots/hol4/sail/mips/Holmakefile
@@ -0,0 +1,11 @@
+LEMDIR=../../lem/hol-lib
+
+INCLUDES = $(LEMDIR) ../lib/hol
+
+all: mipsTheory.uo
+.PHONY: all
+
+ifdef POLY
+BASE_HEAP = ../lib/hol/sail-heap
+
+endif
diff --git a/snapshots/hol4/sail/mips/mipsScript.sml b/snapshots/hol4/sail/mips/mipsScript.sml
new file mode 100644
index 00000000..928a7276
--- /dev/null
+++ b/snapshots/hol4/sail/mips/mipsScript.sml
@@ -0,0 +1,6871 @@
+(*Generated by Lem from mips.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory mips_typesTheory mips_extrasTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "mips"
+
+(*Generated by Sail from mips.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+(*open import Mips_types*)
+(*open import Mips_extras*)
+
+
+
+
+
+
+
+(*val neq_bool : bool -> bool -> bool*)
+
+val _ = Define `
+ ((neq_bool:bool -> bool -> bool) x y=  (~ (((x = y)))))`;
+
+
+(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*)
+
+val _ = Define `
+ ((undefined_option:'a ->(regstate)sail2_state_monad$sequential_state ->((('a option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ_a=  (sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_0 : unit) . 
+   let (u_1 : 'a) = typ_a in
+   sail2_state$internal_pickS [SOME u_1;NONE])))`;
+
+
+(*val is_none : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_none:'a option -> bool) opt=  ((case opt of   SOME (_) => F | NONE => T )))`;
+
+
+(*val is_some : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_some:'a option -> bool) opt=  ((case opt of   SOME (_) => T | NONE => F )))`;
+
+
+(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*)
+
+val _ = Define `
+ ((sail_mask:'len itself -> 'v words$word -> 'len words$word) len v=
+    (let len = (size_itself_int len) in
+   if ((len <= ((int_of_num (words$word_len v))))) then (vector_truncate v len  :  'len words$word)
+   else (zero_extend v len  :  'len words$word)))`;
+
+
+
+
+
+
+(*val cast_unit_vec : bitU -> mword ty1*)
+
+val _ = Define `
+ ((cast_unit_vec0:bitU ->(1)words$word) b=
+    ((case b of   B0 => (vec_of_bits [B0]  :  1 words$word) | _ => (vec_of_bits [B1]  :  1 words$word) )))`;
+
+
+(*val __MIPS_write : forall  'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*)
+
+val _ = Define `
+ ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+    (write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       :  64 words$word) addr data))`;
+
+
+(*val __MIPS_read : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((MIPS_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+        :  64 words$word) addr
+     : ( 'p8_times_n_ words$word) M)))`;
+
+
+
+
+(*val undefined_exception : unit -> M exception*)
+
+val _ = Define `
+ ((undefined_exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_string () ) (\ (u_0 : string) .  sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_1 : unit) . 
+   sail2_state$internal_pickS
+     [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1]))))`;
+
+
+(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((mips_sign_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((sign_extend v m__tv  :  'm words$word)))`;
+
+
+val _ = Define `
+ ((mips_zero_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((zero_extend v m__tv  :  'm words$word)))`;
+
+
+(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*)
+
+val _ = Define `
+ ((zeros0:int -> unit -> 'n words$word) (n__tv : int) () =  ((replicate_bits (vec_of_bits [B0]  :  1 words$word) n__tv  :  'n words$word)))`;
+
+
+(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*)
+
+val _ = Define `
+ ((ones:int -> unit -> 'n words$word) (n__tv : int) () =  ((replicate_bits (vec_of_bits [B1]  :  1 words$word) n__tv  :  'n words$word)))`;
+
+
+(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
+
+val _ = Define `
+ ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y=  (((integer_word$w2i x)) < ((integer_word$w2i y))))`;
+
+
+val _ = Define `
+ ((zopz0zKzJ_s:'n words$word -> 'n words$word -> bool) x y=  (((integer_word$w2i x)) >= ((integer_word$w2i y))))`;
+
+
+val _ = Define `
+ ((zopz0zI_u:'n words$word -> 'n words$word -> bool) x y=  (((lem$w2ui x)) < ((lem$w2ui y))))`;
+
+
+val _ = Define `
+ ((zopz0zKzJ_u:'n words$word -> 'n words$word -> bool) x y=  (((lem$w2ui x)) >= ((lem$w2ui y))))`;
+
+
+(*val bool_to_bits : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_to_bits:bool ->(1)words$word) x=  (if x then (vec_of_bits [B1]  :  1 words$word) else (vec_of_bits [B0]  :  1 words$word)))`;
+
+
+(*val bit_to_bool : bitU -> bool*)
+
+val _ = Define `
+ ((bit_to_bool:bitU -> bool) b=  ((case b of   B1 => T | _ => F )))`;
+
+
+(*val bits_to_bool : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bits_to_bool:(1)words$word -> bool) x=  (bit_to_bool ((access_vec_dec x (( 0 : int):ii)))))`;
+
+
+(*
+\function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits.
+*)
+(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*)
+
+val _ = Define `
+ ((to_bits:'l itself -> int -> 'l words$word) l n=
+    (let l = (size_itself_int l) in
+   (get_slice_int instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii)  :  'l words$word)))`;
+
+
+(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*)
+
+val _ = Define `
+ ((mask:int -> 'm words$word -> 'n words$word) (n__tv : int) bs=
+    ((subrange_vec_dec bs ((n__tv - (( 1 : int):ii))) (( 0 : int):ii)  :  'n words$word)))`;
+
+
+(*val undefined_CauseReg : unit -> M CauseReg*)
+
+val _ = Define `
+ ((undefined_CauseReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((CauseReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+   sail2_state_monad$returnS (<| CauseReg_CauseReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_CauseReg : mword ty32 -> CauseReg*)
+
+val _ = Define `
+ ((Mk_CauseReg:(32)words$word -> CauseReg) v=
+    (<| CauseReg_CauseReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) |>))`;
+
+
+(*val _get_CauseReg_bits : CauseReg -> mword ty32*)
+
+val _ = Define `
+ ((get_CauseReg_bits:CauseReg ->(32)words$word) v=
+    ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))`;
+
+
+(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_bits:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_bits:CauseReg ->(32)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*)
+
+(*val _get_StatusReg_bits : StatusReg -> mword ty32*)
+
+(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*)
+
+(*val _get_CauseReg_BD : CauseReg -> mword ty1*)
+
+val _ = Define `
+ ((get_CauseReg_BD:CauseReg ->(1)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_CauseReg_CE : CauseReg -> mword ty2*)
+
+val _ = Define `
+ ((get_CauseReg_CE:CauseReg ->(2)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii)  :  2 words$word)))`;
+
+
+(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_CauseReg_IV : CauseReg -> mword ty1*)
+
+val _ = Define `
+ ((get_CauseReg_IV:CauseReg ->(1)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_CauseReg_WP : CauseReg -> mword ty1*)
+
+val _ = Define `
+ ((get_CauseReg_WP:CauseReg ->(1)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_CauseReg_IP : CauseReg -> mword ty8*)
+
+val _ = Define `
+ ((get_CauseReg_IP:CauseReg ->(8)words$word) v=  ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
+
+
+(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*)
+
+val _ = Define `
+ ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) v=
+    ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)))`;
+
+
+(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) v x=
+    ((v with<|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*)
+
+val _ = Define `
+ ((undefined_TLBEntryLoReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryLoReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((Mk_TLBEntryLoReg:(64)words$word -> TLBEntryLoReg) v=
+    (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_bits:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii)  :  24 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii)  :  3 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x=
+    ((v with<|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*)
+
+val _ = Define `
+ ((undefined_TLBEntryHiReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryHiReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*)
+
+val _ = Define `
+ ((Mk_TLBEntryHiReg:(64)words$word -> TLBEntryHiReg) v=
+    (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_bits:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) v=
+    ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) v x=
+    ((v with<|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val undefined_ContextReg : unit -> M ContextReg*)
+
+val _ = Define `
+ ((undefined_ContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((ContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| ContextReg_ContextReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_ContextReg : mword ty64 -> ContextReg*)
+
+val _ = Define `
+ ((Mk_ContextReg:(64)words$word -> ContextReg) v=
+    (<| ContextReg_ContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_ContextReg_bits : ContextReg -> mword ty64*)
+
+val _ = Define `
+ ((get_ContextReg_bits:ContextReg ->(64)words$word) v=
+    ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_ContextReg_bits:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*)
+
+val _ = Define `
+ ((update_ContextReg_bits:ContextReg ->(64)words$word -> ContextReg) v x=
+    ((v with<|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*)
+
+val _ = Define `
+ ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) v=
+    ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii)  :  41 words$word)))`;
+
+
+(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*)
+
+val _ = Define `
+ ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii)
+             ((subrange_vec_dec v (( 40 : int):ii) (( 0 : int):ii)  :  41 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*)
+
+val _ = Define `
+ ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) v x=
+    ((v with<|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii)
+           ((subrange_vec_dec x (( 40 : int):ii) (( 0 : int):ii)  :  41 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*)
+
+val _ = Define `
+ ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) v=
+    ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii)  :  19 words$word)))`;
+
+
+(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*)
+
+val _ = Define `
+ ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 18 : int):ii) (( 0 : int):ii)  :  19 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*)
+
+val _ = Define `
+ ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) v x=
+    ((v with<|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 18 : int):ii) (( 0 : int):ii)  :  19 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val undefined_XContextReg : unit -> M XContextReg*)
+
+val _ = Define `
+ ((undefined_XContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((XContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   sail2_state_monad$returnS (<| XContextReg_XContextReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_XContextReg : mword ty64 -> XContextReg*)
+
+val _ = Define `
+ ((Mk_XContextReg:(64)words$word -> XContextReg) v=
+    (<| XContextReg_XContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_XContextReg_bits : XContextReg -> mword ty64*)
+
+val _ = Define `
+ ((get_XContextReg_bits:XContextReg ->(64)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_XContextReg_bits:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_bits:XContextReg ->(64)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*)
+
+val _ = Define `
+ ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii)  :  31 words$word)))`;
+
+
+(*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*)
+
+val _ = Define `
+ ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii)
+             ((subrange_vec_dec v (( 30 : int):ii) (( 0 : int):ii)  :  31 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii)
+           ((subrange_vec_dec x (( 30 : int):ii) (( 0 : int):ii)  :  31 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_XContextReg_XR : XContextReg -> mword ty2*)
+
+val _ = Define `
+ ((get_XContextReg_XR:XContextReg ->(2)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii)  :  2 words$word)))`;
+
+
+(*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*)
+
+val _ = Define `
+ ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) v=
+    ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii)  :  27 words$word)))`;
+
+
+(*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*)
+
+val _ = Define `
+ ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) v x=
+    ((v with<|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((TLBNumEntries:int)=  ((( 64 : int):ii)))`;
+
+
+val _ = Define `
+((TLBIndexMax:(6)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B1;B1]  :  6 words$word)))`;
+
+
+(*val MAX : integer -> integer*)
+
+val _ = Define `
+ ((MAX0:int -> int) n=  (((pow2 n)) - (( 1 : int):ii)))`;
+
+
+val _ = Define `
+ ((MAX_U64:int)=  (MAX0 (( 64 : int):ii)))`;
+
+
+val _ = Define `
+ ((MAX_VA:int)=  (MAX0 (( 40 : int):ii)))`;
+
+
+val _ = Define `
+ ((MAX_PA:int)=  (MAX0 (( 36 : int):ii)))`;
+
+
+(*val undefined_TLBEntry : unit -> M TLBEntry*)
+
+val _ = Define `
+ ((undefined_TLBEntry:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 : int):ii)  : ( 53 words$word) M) (\ (w__0 :  53 words$word) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   sail2_state_monad$returnS (<| TLBEntry_TLBEntry_chunk_1 := w__0; 
+              TLBEntry_TLBEntry_chunk_0 := w__1 |>)))))`;
+
+
+(*val Mk_TLBEntry : mword ty117 -> TLBEntry*)
+
+val _ = Define `
+ ((Mk_TLBEntry:(117)words$word -> TLBEntry) v=
+    (<| TLBEntry_TLBEntry_chunk_1 := ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii)  :  53 words$word)); 
+      TLBEntry_TLBEntry_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*)
+
+val _ = Define `
+ ((get_TLBEntry_bits:TLBEntry ->(117)words$word) v=
+    ((concat_vec ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii)  :  53 words$word))
+      ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+     :  117 words$word)))`;
+
+
+(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_bits:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii)  :  53 words$word))
+            :  53 words$word))|>)) in
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_bits:TLBEntry ->(117)words$word -> TLBEntry) v x=
+    (let v =
+     ((v with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec x (( 116 : int):ii) (( 64 : int):ii)  :  53 words$word))
+            :  53 words$word))|>)) in
+   (v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*)
+
+val _ = Define `
+ ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii)  :  16 words$word)))`;
+
+
+(*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii)
+             ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii)
+           ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+          :  53 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_r : TLBEntry -> mword ty2*)
+
+val _ = Define `
+ ((get_TLBEntry_r:TLBEntry ->(2)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii)  :  2 words$word)))`;
+
+
+(*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  53 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*)
+
+val _ = Define `
+ ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii)  :  27 words$word)))`;
+
+
+(*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  53 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_asid : TLBEntry -> mword ty8*)
+
+val _ = Define `
+ ((get_TLBEntry_asid:TLBEntry ->(8)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+
+
+(*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  53 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  53 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_g : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_g:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_valid : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_valid:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*)
+
+val _ = Define `
+ ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii)  :  24 words$word)))`;
+
+
+(*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii)
+             ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii)
+           ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*)
+
+val _ = Define `
+ ((get_TLBEntry_c1:TLBEntry ->(3)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii)  :  3 words$word)))`;
+
+
+(*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii)
+             ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii)
+           ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_d1:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_v1:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*)
+
+val _ = Define `
+ ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) v=
+    ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii)  :  24 words$word)))`;
+
+
+(*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*)
+
+val _ = Define `
+ ((get_TLBEntry_c0:TLBEntry ->(3)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)))`;
+
+
+(*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_d0:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_v0:TLBEntry ->(1)words$word) v=  ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) v x=
+    ((v with<|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+((TLBEntries:(((regstate),(register_value),(TLBEntry))register_ref)list)=
+   ([TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;
+   TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;
+   TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;
+   TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref;TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;
+   TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;
+   TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;
+   TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref;
+   TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;
+   TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;
+   TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;
+   TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref;TLBEntry00_ref]))`;
+
+
+(*val undefined_StatusReg : unit -> M StatusReg*)
+
+val _ = Define `
+ ((undefined_StatusReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((StatusReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 :  32 words$word) . 
+   sail2_state_monad$returnS (<| StatusReg_StatusReg_chunk_0 := w__0 |>))))`;
+
+
+(*val Mk_StatusReg : mword ty32 -> StatusReg*)
+
+val _ = Define `
+ ((Mk_StatusReg:(32)words$word -> StatusReg) v=
+    (<| StatusReg_StatusReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) |>))`;
+
+
+val _ = Define `
+ ((get_StatusReg_bits:StatusReg ->(32)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))`;
+
+
+val _ = Define `
+ ((set_StatusReg_bits:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_StatusReg_bits:StatusReg ->(32)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_CU : StatusReg -> mword ty4*)
+
+val _ = Define `
+ ((get_StatusReg_CU:StatusReg ->(4)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)))`;
+
+
+(*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii)
+             ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii)
+           ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_BEV : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_BEV:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_IM : StatusReg -> mword ty8*)
+
+val _ = Define `
+ ((get_StatusReg_IM:StatusReg ->(8)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)))`;
+
+
+(*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_KX : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_KX:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_SX : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_SX:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_UX : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_UX:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_KSU : StatusReg -> mword ty2*)
+
+val _ = Define `
+ ((get_StatusReg_KSU:StatusReg ->(2)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)))`;
+
+
+(*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_ERL : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_ERL:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_EXL : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_EXL:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val _get_StatusReg_IE : StatusReg -> mword ty1*)
+
+val _ = Define `
+ ((get_StatusReg_IE:StatusReg ->(1)words$word) v=
+    ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) v x=
+    ((v with<|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
+
+(*val execute_branch : mword ty64 -> M unit*)
+
+val _ = Define `
+ ((execute_branch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pc=  (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS delayedPC_ref pc) (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
+
+
+(*val NotWordVal : mword ty64 -> bool*)
+
+val _ = Define `
+ ((NotWordVal:(64)words$word -> bool) word=
+    (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word (( 31 : int):ii)))  :  1 words$word)) (( 32 : int):ii)
+        :  32 words$word)) <> ((subrange_vec_dec word (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))))`;
+
+
+(*val rGPR : mword ty5 -> M (mword ty64)*)
+
+val _ = Define `
+ ((rGPR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx=
+    (let i = (lem$w2ui idx) in
+   if (((i = (( 0 : int):ii)))) then
+     sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                          B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                          B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+              :  64 words$word)
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . 
+     sail2_state_monad$returnS ((access_list_dec w__0 i  :  64 words$word)))))`;
+
+
+(*val wGPR : mword ty5 -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((wGPR:(5)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx v=
+    (let i = (lem$w2ui idx) in
+   if (((i <> (( 0 : int):ii)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . 
+     sail2_state_monad$write_regS GPR_ref ((update_list_dec w__0 i v  : ( 64 words$word) list)))
+   else sail2_state_monad$returnS () ))`;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+(*val Exception_of_num : integer -> Exception*)
+
+val _ = Define `
+ ((Exception_of_num:int -> Exception) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Interrupt
+   else if (((p0_ = (( 1 : int):ii)))) then TLBMod
+   else if (((p0_ = (( 2 : int):ii)))) then TLBL
+   else if (((p0_ = (( 3 : int):ii)))) then TLBS
+   else if (((p0_ = (( 4 : int):ii)))) then AdEL
+   else if (((p0_ = (( 5 : int):ii)))) then AdES
+   else if (((p0_ = (( 6 : int):ii)))) then Sys
+   else if (((p0_ = (( 7 : int):ii)))) then Bp
+   else if (((p0_ = (( 8 : int):ii)))) then ResI
+   else if (((p0_ = (( 9 : int):ii)))) then CpU
+   else if (((p0_ = (( 10 : int):ii)))) then Ov
+   else if (((p0_ = (( 11 : int):ii)))) then Tr
+   else if (((p0_ = (( 12 : int):ii)))) then C2E
+   else if (((p0_ = (( 13 : int):ii)))) then C2Trap
+   else if (((p0_ = (( 14 : int):ii)))) then XTLBRefillL
+   else if (((p0_ = (( 15 : int):ii)))) then XTLBRefillS
+   else if (((p0_ = (( 16 : int):ii)))) then XTLBInvL
+   else if (((p0_ = (( 17 : int):ii)))) then XTLBInvS
+   else MCheck))`;
+
+
+(*val num_of_Exception : Exception -> integer*)
+
+val _ = Define `
+ ((num_of_Exception:Exception -> int) arg_=
+    ((case arg_ of
+     Interrupt => (( 0 : int):ii)
+   | TLBMod => (( 1 : int):ii)
+   | TLBL => (( 2 : int):ii)
+   | TLBS => (( 3 : int):ii)
+   | AdEL => (( 4 : int):ii)
+   | AdES => (( 5 : int):ii)
+   | Sys => (( 6 : int):ii)
+   | Bp => (( 7 : int):ii)
+   | ResI => (( 8 : int):ii)
+   | CpU => (( 9 : int):ii)
+   | Ov => (( 10 : int):ii)
+   | Tr => (( 11 : int):ii)
+   | C2E => (( 12 : int):ii)
+   | C2Trap => (( 13 : int):ii)
+   | XTLBRefillL => (( 14 : int):ii)
+   | XTLBRefillS => (( 15 : int):ii)
+   | XTLBInvL => (( 16 : int):ii)
+   | XTLBInvS => (( 17 : int):ii)
+   | MCheck => (( 18 : int):ii)
+   )))`;
+
+
+(*val undefined_Exception : unit -> M Exception*)
+
+val _ = Define `
+ ((undefined_Exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((Exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS
+     [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`;
+
+
+(*val ExceptionCode : Exception -> mword ty5*)
+
+val _ = Define `
+ ((ExceptionCode:Exception ->(5)words$word) ex=
+    (let (x : 8 bits) =
+     ((case ex of
+       Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+     | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  :  8 words$word)
+     | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+     | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+     | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0]  :  8 words$word)
+     | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1]  :  8 words$word)
+     | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0]  :  8 words$word)
+     | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1]  :  8 words$word)
+     | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0]  :  8 words$word)
+     | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1]  :  8 words$word)
+     | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0]  :  8 words$word)
+     | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1]  :  8 words$word)
+     | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  :  8 words$word)
+     | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  :  8 words$word)
+     | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+     | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+     | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+     | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+     | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0]  :  8 words$word)
+     )) in
+   (subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)))`;
+
+
+(*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*)
+
+val _ = Define `
+ ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex kccBase=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS inBranchDelay_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
+      if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii)  :  64 words$word)))
+        (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1]  :  1 words$word)))
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 : 64 bits) .  sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0]  :  1 words$word))))
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . 
+   let vectorOffset =
+     (if ((bits_to_bool ((get_StatusReg_EXL w__4  :  1 words$word)))) then
+       (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+     else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then
+       (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+     else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+     else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . 
+   let (vectorBase : 64 bits) =
+     (if ((bits_to_bool ((get_StatusReg_BEV w__5  :  1 words$word)))) then
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)
+     else
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     nextPC_ref
+     ((sub_vec
+         ((add_vec vectorBase ((mips_sign_extend (( 64 : int):ii) vectorOffset  :  64 words$word))  :  64 words$word))
+         kccBase
+        :  64 words$word)))
+   (set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex  :  5 words$word))))
+   (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1]  :  1 words$word))) (sail2_state_monad$throwS (ISAException () )))))))`;
+
+
+(*val SignalException : forall 'o. Exception -> M 'o*)
+
+(*val SignalExceptionBadAddr : forall 'o. Exception -> mword ty64 -> M 'o*)
+
+val _ = Define `
+ ((SignalException:Exception ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex=
+    (SignalExceptionMIPS ex
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       :  64 words$word)))`;
+
+
+val _ = Define `
+ ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr=  (sail2_state_monad$seqS (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`;
+
+
+(*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*)
+
+val _ = Define `
+ ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr=  (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr)
+   (set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):ii) (( 13 : int):ii)  :  19 words$word))))
+   (set_XContextReg_XBadVPN2 TLBXContext_ref
+     ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word))))
+   (set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word))))
+   (set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word))))
+   (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word))))
+   (SignalException ex)))`;
+
+
+(*val MemAccessType_of_num : integer -> MemAccessType*)
+
+val _ = Define `
+ ((MemAccessType_of_num:int -> MemAccessType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Instruction
+   else if (((p0_ = (( 1 : int):ii)))) then LoadData
+   else StoreData))`;
+
+
+(*val num_of_MemAccessType : MemAccessType -> integer*)
+
+val _ = Define `
+ ((num_of_MemAccessType:MemAccessType -> int) arg_=
+    ((case arg_ of   Instruction => (( 0 : int):ii) | LoadData => (( 1 : int):ii) | StoreData => (( 2 : int):ii) )))`;
+
+
+(*val undefined_MemAccessType : unit -> M MemAccessType*)
+
+val _ = Define `
+ ((undefined_MemAccessType:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAccessType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [Instruction;LoadData;StoreData]))`;
+
+
+(*val AccessLevel_of_num : integer -> AccessLevel*)
+
+val _ = Define `
+ ((AccessLevel_of_num:int -> AccessLevel) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then User
+   else if (((p0_ = (( 1 : int):ii)))) then Supervisor
+   else Kernel))`;
+
+
+(*val num_of_AccessLevel : AccessLevel -> integer*)
+
+val _ = Define `
+ ((num_of_AccessLevel:AccessLevel -> int) arg_=
+    ((case arg_ of   User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Kernel => (( 2 : int):ii) )))`;
+
+
+(*val undefined_AccessLevel : unit -> M AccessLevel*)
+
+val _ = Define `
+ ((undefined_AccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [User;Supervisor;Kernel]))`;
+
+
+(*val int_of_AccessLevel : AccessLevel -> ii*)
+
+val _ = Define `
+ ((int_of_AccessLevel:AccessLevel -> int) level=
+    ((case level of   User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Kernel => (( 2 : int):ii) )))`;
+
+
+(*
+Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level.
+ *)
+(*val grantsAccess : AccessLevel -> AccessLevel -> bool*)
+
+val _ = Define `
+ ((grantsAccess:AccessLevel -> AccessLevel -> bool) currentLevel requiredLevel=
+    (((int_of_AccessLevel currentLevel)) >= ((int_of_AccessLevel requiredLevel))))`;
+
+
+(*
+Returns the current effective access level determined by accessing the relevant parts of the MIPS status register.
+ *)
+(*val getAccessLevel : unit -> M AccessLevel*)
+
+val _ = Define `
+ ((getAccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1  :  1 words$word))))))) (\ (w__2 : bool) . 
+   if w__2 then sail2_state_monad$returnS Kernel
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . 
+     let p__27 = ((get_StatusReg_KSU w__3  :  2 words$word)) in
+     let b__0 = p__27 in
+     sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then Kernel
+             else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then Supervisor
+             else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then User
+             else User)))))`;
+
+
+(*val checkCP0Access : unit -> M unit*)
+
+val _ = Define `
+ ((checkCP0Access:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (getAccessLevel () ) (\ accessLevel .  sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS (((accessLevel <> Kernel))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+      sail2_state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 :
+     bool) . 
+   if w__1 then sail2_state_monad$seqS
+     (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0]  :  2 words$word)) (SignalException CpU)
+   else sail2_state_monad$returnS () ))))`;
+
+
+(*val incrementCP0Count : unit -> M unit*)
+
+val _ = Define `
+ ((incrementCP0Count:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__0 : TLBIndexT) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS TLBWired_ref  : ( 6 words$word) M) (\ (w__1 :  6 words$word) .  sail2_state_monad$bindS
+   (if (((w__0 = w__1))) then sail2_state_monad$returnS TLBIndexMax
+    else sail2_state_monad$bindS
+      (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__2 :  6 words$word) . 
+      sail2_state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii)  :  6 words$word)))) (\ (w__3 :  6 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBRandom_ref w__3)
+   (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M)) (\ (w__4 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii)  :  32 words$word)))
+   (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M)) (\ (w__5 : 32 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Compare_ref  : ( 32 words$word) M) (\ (w__6 :  32 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (if (((w__5 = w__6))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . 
+      set_CauseReg_IP CP0Cause_ref
+        ((or_vec ((get_CauseReg_IP w__7  :  8 words$word))
+            (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+           :  8 words$word)))
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . 
+   let ims = ((get_StatusReg_IM w__8  :  8 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . 
+   let ips = ((get_CauseReg_IP w__9  :  8 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . 
+   let ie = ((get_StatusReg_IE w__10  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . 
+   let exl = ((get_StatusReg_EXL w__11  :  1 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . 
+   let erl = ((get_StatusReg_ERL w__12  :  1 words$word)) in
+   if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims  :  8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))))))))) then
+     SignalException Interrupt
+   else sail2_state_monad$returnS () )))))))))))))`;
+
+
+(*val decode_failure_of_num : integer -> decode_failure*)
+
+val _ = Define `
+ ((decode_failure_of_num:int -> decode_failure) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then No_matching_pattern
+   else if (((p0_ = (( 1 : int):ii)))) then Unsupported_instruction
+   else if (((p0_ = (( 2 : int):ii)))) then Illegal_instruction
+   else Internal_error))`;
+
+
+(*val num_of_decode_failure : decode_failure -> integer*)
+
+val _ = Define `
+ ((num_of_decode_failure:decode_failure -> int) arg_= 
+  ((case arg_ of   no_matching_pattern => (( 0 : int): ii) )))`;
+
+
+(*val undefined_decode_failure : unit -> M decode_failure*)
+
+val _ = Define `
+ ((undefined_decode_failure:unit ->(regstate)sail2_state_monad$sequential_state ->(((decode_failure),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$internal_pickS [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`;
+
+
+(*val Comparison_of_num : integer -> Comparison*)
+
+val _ = Define `
+ ((Comparison_of_num:int -> Comparison) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then EQ'
+   else if (((p0_ = (( 1 : int):ii)))) then NE
+   else if (((p0_ = (( 2 : int):ii)))) then GE
+   else if (((p0_ = (( 3 : int):ii)))) then GEU
+   else if (((p0_ = (( 4 : int):ii)))) then GT'
+   else if (((p0_ = (( 5 : int):ii)))) then LE
+   else if (((p0_ = (( 6 : int):ii)))) then LT'
+   else LTU))`;
+
+
+(*val num_of_Comparison : Comparison -> integer*)
+
+val _ = Define `
+ ((num_of_Comparison:Comparison -> int) arg_=
+    ((case arg_ of
+     EQ' => (( 0 : int):ii)
+   | NE => (( 1 : int):ii)
+   | GE => (( 2 : int):ii)
+   | GEU => (( 3 : int):ii)
+   | GT' => (( 4 : int):ii)
+   | LE => (( 5 : int):ii)
+   | LT' => (( 6 : int):ii)
+   | LTU => (( 7 : int):ii)
+   )))`;
+
+
+(*val undefined_Comparison : unit -> M Comparison*)
+
+val _ = Define `
+ ((undefined_Comparison:unit ->(regstate)sail2_state_monad$sequential_state ->(((Comparison),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`;
+
+
+(*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*)
+
+val _ = Define `
+ ((compare:Comparison ->(64)words$word ->(64)words$word -> bool) cmp valA valB=
+    ((case cmp of
+     EQ' => (valA = valB)
+   | NE => (valA <> valB)
+   | GE => zopz0zKzJ_s valA valB
+   | GEU => zopz0zKzJ_u valA valB
+   | GT' => zopz0zI_s valB valA
+   | LE => zopz0zKzJ_s valB valA
+   | LT' => zopz0zI_s valA valB
+   | LTU => zopz0zI_u valA valB
+   )))`;
+
+
+(*val WordType_of_num : integer -> WordType*)
+
+val _ = Define `
+ ((WordType_of_num:int -> WordType) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then B
+   else if (((p0_ = (( 1 : int):ii)))) then H
+   else if (((p0_ = (( 2 : int):ii)))) then W0
+   else D))`;
+
+
+(*val num_of_WordType : WordType -> integer*)
+
+val _ = Define `
+ ((num_of_WordType:WordType -> int) arg_=
+    ((case arg_ of   B => (( 0 : int):ii) | H => (( 1 : int):ii) | W0 => (( 2 : int):ii) | D => (( 3 : int):ii) )))`;
+
+
+(*val undefined_WordType : unit -> M WordType*)
+
+val _ = Define `
+ ((undefined_WordType:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [B;H;W0;D]))`;
+
+
+(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*)
+
+val _ = Define `
+ ((WordTypeUnaligned_of_num:int -> WordTypeUnaligned) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then WL
+   else if (((p0_ = (( 1 : int):ii)))) then WR
+   else if (((p0_ = (( 2 : int):ii)))) then DL
+   else DR))`;
+
+
+(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*)
+
+val _ = Define `
+ ((num_of_WordTypeUnaligned:WordTypeUnaligned -> int) arg_=
+    ((case arg_ of   WL => (( 0 : int):ii) | WR => (( 1 : int):ii) | DL => (( 2 : int):ii) | DR => (( 3 : int):ii) )))`;
+
+
+(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*)
+
+val _ = Define `
+ ((undefined_WordTypeUnaligned:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordTypeUnaligned),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state$internal_pickS [WL;WR;DL;DR]))`;
+
+
+(*val wordWidthBytes : WordType -> integer*)
+
+val _ = Define `
+ ((wordWidthBytes:WordType -> int) w=  ((case w of   B => (( 1 : int):ii) | H => (( 2 : int):ii) | W0 => (( 4 : int):ii) | D => (( 8 : int):ii) )))`;
+
+
+val _ = Define `
+ ((alignment_width:int)=  ((( 16 : int):ii)))`;
+
+
+(*val isAddressAligned : mword ty64 -> WordType -> bool*)
+
+val _ = Define `
+ ((isAddressAligned:(64)words$word -> WordType -> bool) addr wordType=
+    (let a = (lem$w2ui addr) in
+   (((a / alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 : int):ii))) /
+         alignment_width)))))`;
+
+
+(*val MEMr_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1=
+    (if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+            :  64 words$word)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS UART_RVALID_ref  : ( 1 words$word) M) (\ rvalid .  sail2_state_monad$bindS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0]  :  1 words$word))
+     (sail2_state_monad$read_regS UART_RDATA_ref  : ( 8 words$word) M)) (\ (w__0 : 8 bits) . 
+     sail2_state_monad$returnS ((mask p8_times_n___tv
+                ((concat_vec
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                      :  32 words$word)
+                    ((concat_vec w__0
+                        ((concat_vec rvalid
+                            ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+                                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                  :  16 words$word)
+                               :  23 words$word))
+                           :  24 words$word))
+                       :  32 words$word))
+                   :  64 words$word))
+               :  'p8_times_n_ words$word))))
+   else if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]
+                 :  64 words$word)))) then
+     sail2_state_monad$returnS ((mask p8_times_n___tv
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+                              B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]
+                  :  64 words$word)
+               :  'p8_times_n_ words$word))
+   else sail2_state_monad$bindS
+     (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) M) (\ w__1 . 
+     sail2_state_monad$returnS ((reverse_endianness w__1  :  'p8_times_n_ words$word)))))`;
+
+
+(*val MEMr_reserve_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1=  (sail2_state_monad$bindS
+   (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) M) (\ w__0 . 
+   sail2_state_monad$returnS ((reverse_endianness w__0  :  'p8_times_n_ words$word)))))`;
+
+
+(*val init_cp0_state : unit -> M unit*)
+
+val _ = Define `
+ ((init_cp0_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1  :  1 words$word))))`;
+
+
+(*val init_cp2_state : unit -> M unit*)
+
+(*val cp2_next_pc : unit -> M unit*)
+
+(*val dump_cp2_state : unit -> M unit*)
+
+(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((extz_vec m__tv v  :  'm words$word)))`;
+
+
+(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((exts_vec m__tv v  :  'm words$word)))`;
+
+
+(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*)
+
+val _ = Define `
+ ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l=
+    (let (one1 : 'n bits) = ((extzv n__tv (vec_of_bits [B1]  :  1 words$word)  :  'n words$word)) in
+   (shiftl ((sub_vec ((shiftl one1 l  :  'n words$word)) one1  :  'n words$word)) i  :  'n words$word)))`;
+
+
+(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
+
+val _ = Define `
+ ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j=
+    (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
+
+
+(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
+
+val _ = Define `
+ ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j=
+    (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i))  :  'n words$word)) in
+   (((and_vec xs m  :  'n words$word)) = m)))`;
+
+
+(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*)
+
+val _ = Define `
+ ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   let ys =
+     ((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l'  :  'm words$word))  :  'm words$word)) i'
+       :  'm words$word)) in
+   (or_vec ((shiftl ((extzv r__tv xs  :  'r words$word)) l'  :  'r words$word)) ((extzv r__tv ys  :  'r words$word))
+     :  'r words$word)))`;
+
+
+(*val slice_zeros_concat : forall 'n   'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*)
+
+val _ = Define `
+ ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (shiftl ((extzv r__tv xs  :  'r words$word)) l'  :  'r words$word)))`;
+
+
+(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*)
+
+val _ = Define `
+ ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   let ys =
+     ((shiftr
+        ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j'))  :  'n words$word))  :  'n words$word))
+        j'
+       :  'n words$word)) in
+   (xs = ys)))`;
+
+
+(*val subrange_subrange_concat : forall 'n   'm   's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*)
+
+val _ = Define `
+ ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   let ys =
+     ((shiftr
+        ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j'))  :  'm words$word))  :  'm words$word))
+        j'
+       :  'm words$word)) in
+   (or_vec
+      ((sub_vec_int ((shiftl ((extzv s__tv xs  :  's words$word)) i'  :  's words$word))
+          ((j' - (( 1 : int):ii)))
+         :  's words$word)) ((extzv s__tv ys  :  's words$word))
+     :  's words$word)))`;
+
+
+(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
+
+
+(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
+
+
+(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (extzv m__tv xs  :  'm words$word)))`;
+
+
+(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
+
+val _ = Define `
+ ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l=
+    (let xs =
+     ((arith_shiftr
+        ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word))
+            ((((((int_of_num (words$word_len xs))) - i)) - l))
+           :  'n words$word)) ((((int_of_num (words$word_len xs))) - l))
+       :  'n words$word)) in
+   (extsv m__tv xs  :  'm words$word)))`;
+
+
+(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+
+val _ = Define `
+ ((unsigned_slice:'n words$word -> int -> int -> int) xs i l=
+    (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   lem$w2ui xs))`;
+
+
+(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+
+val _ = Define `
+ ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j=
+    (let xs =
+     ((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) i
+       :  'n words$word)) in
+   lem$w2ui xs))`;
+
+
+(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*)
+
+val _ = Define `
+ ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m=
+    (let (v : 'n bits) = ((extsv n__tv (vec_of_bits [B1]  :  1 words$word)  :  'n words$word)) in
+   (shiftr v ((((int_of_num (words$word_len v))) - m))  :  'n words$word)))`;
+
+
+(*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*)
+
+val _ = Define `
+ ((tlbEntryMatch:(2)words$word ->(27)words$word ->(8)words$word -> TLBEntry -> bool) r vpn2 asid entry=
+    (let entryValid = ((get_TLBEntry_valid entry  :  1 words$word)) in
+   let entryR = ((get_TLBEntry_r entry  :  2 words$word)) in
+   let entryMask = ((get_TLBEntry_pagemask entry  :  16 words$word)) in
+   let entryVPN = ((get_TLBEntry_vpn2 entry  :  27 words$word)) in
+   let entryASID = ((get_TLBEntry_asid entry  :  8 words$word)) in
+   let entryG = ((get_TLBEntry_g entry  :  1 words$word)) in
+   let (vpnMask : 27 bits) =
+     ((not_vec ((mips_zero_extend (( 27 : int):ii) entryMask  :  27 words$word))  :  27 words$word)) in
+   (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask  :  27 words$word)) = ((and_vec entryVPN vpnMask  :  27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`;
+
+
+(*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*)
+
+val _ = Define `
+ ((tlbSearch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((6)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) VAddr=
+    (sail2_state_monad$catch_early_returnS
+     (let r = ((subrange_vec_dec VAddr (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)) in
+     let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$liftRS (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . 
+     let asid = ((get_TLBEntryHiReg_ASID w__0  :  8 words$word)) in sail2_state_monad$seqS
+     (sail2_state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () 
+       (\ idx unit_var .  sail2_state_monad$bindS
+         (sail2_state_monad$liftRS (sail2_state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . 
+         if ((tlbEntryMatch r vpn2 asid w__1)) then
+           (sail2_state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii)  :  6 itself)) idx  :  6 words$word))) : (unit, ( ( 6 words$word)option))
+             MR)
+         else sail2_state_monad$returnS () )))
+     (sail2_state_monad$returnS NONE)))))`;
+
+
+(*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*)
+
+val _ = Define `
+ ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType=  (sail2_state_monad$bindS
+   (tlbSearch vAddr  : ( ( 6 words$word)option) M) (\ idx . 
+   (case idx of
+     SOME (idx) =>
+      let i = (lem$w2ui idx) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . 
+      let entryMask = ((get_TLBEntry_pagemask entry  :  16 words$word)) in
+      let b__0 = entryMask in sail2_state_monad$bindS
+      (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) then
+         sail2_state_monad$returnS (( 12 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 14 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 16 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 18 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 20 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 22 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 24 : int):ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 26 : int):ii)
+       else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         sail2_state_monad$returnS (( 28 : int):ii)
+       else undefined_range (( 12 : int):ii) (( 28 : int):ii)) (\ (evenOddBit : int) . 
+      let isOdd = (access_vec_dec vAddr evenOddBit) in
+      let ((caps : 1 bits), (capl : 1 bits), (pfn : 24 bits), (d : 1 bits), (v : 1 bits)) =
+        (if ((bit_to_bool isOdd)) then
+          ((get_TLBEntry_caps1 entry  :  1 words$word),
+           (get_TLBEntry_capl1 entry  :  1 words$word),
+           (get_TLBEntry_pfn1 entry  :  24 words$word),
+           (get_TLBEntry_d1 entry  :  1 words$word),
+           (get_TLBEntry_v1 entry  :  1 words$word))
+        else
+          ((get_TLBEntry_caps0 entry  :  1 words$word),
+           (get_TLBEntry_capl0 entry  :  1 words$word),
+           (get_TLBEntry_pfn0 entry  :  24 words$word),
+           (get_TLBEntry_d0 entry  :  1 words$word),
+           (get_TLBEntry_v0 entry  :  1 words$word))) in
+      if ((~ ((bits_to_bool v)))) then
+        (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr
+          : (( 64 words$word # bool)) M)
+      else if ((((((accessType = StoreData))) /\ ((~ ((bits_to_bool d))))))) then
+        (SignalExceptionTLB TLBMod vAddr  : (( 64 words$word # bool)) M)
+      else
+        let (res : 64 bits) =
+          ((mips_zero_extend (( 64 : int):ii)
+             ((subrange_subrange_concat
+                 (((((((( 23 : int):ii) -
+                             ((((evenOddBit - (( 12 : int):ii))) - (( 1 : int):ii)))))
+                         +
+                         ((evenOddBit - (( 1 : int):ii)))))
+                     - (((( 0 : int):ii) - (( 1 : int):ii))))) pfn
+                 (( 23 : int):ii) ((evenOddBit - (( 12 : int):ii))) vAddr
+                 ((evenOddBit - (( 1 : int):ii))) (( 0 : int):ii)
+                :  36 words$word))
+            :  64 words$word)) in
+        sail2_state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl))))
+   | NONE =>
+      (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr
+        : (( 64 words$word # bool)) M)
+   ))))`;
+
+
+(*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*)
+
+val _ = Define `
+ ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType=  (sail2_state_monad$bindS
+   (getAccessLevel () ) (\ currentAccessLevel . 
+   let compat32 =
+     (((subrange_vec_dec vAddr (( 61 : int):ii) (( 31 : int):ii)  :  31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1]
+         :  31 words$word)) in
+   let b__0 = ((subrange_vec_dec vAddr (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)) in
+   let ((requiredLevel : AccessLevel), (addr :  ( 64 bits)option)) =
+     (if (((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) then
+       (case (compat32, (subrange_vec_dec vAddr (( 30 : int):ii) (( 29 : int):ii)  :  2 words$word)) of
+         (T, b__1) =>
+          if (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word)))) then (Kernel, NONE)
+          else if (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word)))) then (Supervisor, NONE)
+          else if (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+            (Kernel,
+             SOME ((concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        :  32 words$word)
+                      ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                          ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii)  :  29 words$word))
+                         :  32 words$word))
+                     :  64 words$word)))
+          else if (((b__1 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+            (Kernel,
+             SOME ((concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        :  32 words$word)
+                      ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                          ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii)  :  29 words$word))
+                         :  32 words$word))
+                     :  64 words$word)))
+          else (case (T, b__1) of   (g__25, g__26) => (Kernel, NONE) )
+       | (g__25, g__26) => (Kernel, NONE)
+       )
+     else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+       (Kernel,
+        SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                 ((subrange_vec_dec vAddr (( 58 : int):ii) (( 0 : int):ii)  :  59 words$word))
+                :  64 words$word)))
+     else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then (Supervisor, NONE)
+     else (User, NONE)) in
+   if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then
+     (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
+       : (( 64 words$word # bool)) M)
+   else sail2_state_monad$bindS
+     (case addr of
+       SOME (a) => sail2_state_monad$returnS (a, F)
+     | NONE =>
+        if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):ii) (( 0 : int):ii)  :  62 words$word)))) > MAX_VA))))) then
+          (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
+            : (( 64 words$word # bool)) M)
+        else (TLBTranslate2 vAddr accessType  : (( 64 words$word # bool)) M)
+     ) (\ varstup .  let ((pa : 64 bits), (c : bool)) = varstup in
+     if ((((lem$w2ui pa)) > MAX_PA)) then
+       (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
+         : (( 64 words$word # bool)) M)
+     else sail2_state_monad$returnS (pa, c)))))`;
+
+
+(*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*)
+
+val _ = Define `
+ ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType=  (sail2_state_monad$bindS
+   (TLBTranslateC vAddr accessType  : (( 64 words$word # bool)) M) (\ varstup .  let (addr, c) = varstup in
+   sail2_state_monad$returnS addr)))`;
+
+
+(*val MEMw_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*)
+
+val _ = Define `
+ ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data=
+    (let ledata = ((reverse_endianness data  :  'p8_times_n_ words$word)) in
+   if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+            :  64 words$word)))) then sail2_state_monad$seqS
+     (sail2_state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))
+     (sail2_state_monad$write_regS UART_WRITTEN_ref ((cast_unit_vec0 B1  :  1 words$word)))
+   else sail2_state_monad$seqS (MEMea 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) (MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata)))`;
+
+
+(*val MEMw_conditional_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*)
+
+val _ = Define `
+ ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data=  (sail2_state_monad$seqS
+   (MEMea_conditional 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1)
+   (MEMval_conditional 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data  :  'p8_times_n_ words$word)))))`;
+
+
+(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> mword ty64*)
+
+val _ = Define `
+ ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(64)words$word) addr accessType width=  addr)`;
+
+
+(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> mword ty64*)
+
+val _ = Define `
+ ((addrWrapperUnaligned:(64)words$word -> MemAccessType -> WordTypeUnaligned ->(64)words$word) addr accessType width=  addr)`;
+
+
+(*val TranslatePC : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((TranslatePC:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr=  (sail2_state_monad$seqS
+   (incrementCP0Count () )
+   (if (((((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) <> (vec_of_bits [B0;B0]  :  2 words$word))))
+   then
+     (SignalExceptionBadAddr AdEL vAddr  : ( 64 words$word) M)
+   else (TLBTranslate vAddr Instruction  : ( 64 words$word) M))))`;
+
+
+val _ = Define `
+ ((have_cp2:bool)=  F)`;
+
+
+(*val ERETHook : unit -> unit*)
+
+val _ = Define `
+ ((ERETHook:unit -> unit) () =  () )`;
+
+
+val _ = Define `
+ ((init_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (skip () ))`;
+
+
+val _ = Define `
+ ((cp2_next_pc:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS (skip () ) (skip () )))`;
+
+
+val _ = Define `
+ ((dump_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS (skip () ) (skip () )))`;
+
+
+(*val undefined_ast : unit -> M ast*)
+
+val _ = Define `
+ ((undefined_ast:unit ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_Comparison () ) (\ (u_0 : Comparison) .  sail2_state_monad$bindS
+   (undefined_WordType () ) (\ (u_1 : WordType) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (u_3 : bool) .  sail2_state_monad$bindS
+   (sail2_state_monad$undefined_boolS () ) (\ (u_2 : bool) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (u_4 : imm16) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_7 : regno) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_6 : regno) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii)  : ( 5 words$word) M) (\ (u_5 : regno) .  sail2_state_monad$bindS
+   (undefined_unit () ) (\ (u_8 : unit) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii)  : ( 3 words$word) M) (\ (u_9 : 3 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M) (\ (u_10 : 16 bits) .  sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 : int):ii)  : ( 26 words$word) M) (\ (u_11 : 26 bits) . 
+   sail2_state$internal_pickS
+     [DADDIU (u_6,u_5,u_4);DADDU (u_7,u_6,u_5);DADDI (u_6,u_5,u_10);DADD (u_7,u_6,u_5);ADD (u_7,u_6,u_5);ADDI (u_6,u_5,u_10);ADDU (u_7,u_6,u_5);ADDIU (u_6,u_5,u_10);DSUBU (u_7,u_6,u_5);DSUB (u_7,u_6,u_5);SUB0 (u_7,u_6,u_5);SUBU (u_7,u_6,u_5);AND (u_7,u_6,u_5);ANDI (u_6,u_5,u_10);OR (u_7,u_6,u_5);ORI (u_6,u_5,u_10);NOR (u_7,u_6,u_5);XOR (u_7,u_6,u_5);XORI (u_6,u_5,u_10);LUI (u_5,u_4);DSLL (u_7,u_6,u_5);DSLL32 (u_7,u_6,u_5);DSLLV (u_7,u_6,u_5);DSRA (u_7,u_6,u_5);DSRA32 (u_7,u_6,u_5);DSRAV (u_7,u_6,u_5);DSRL (u_7,u_6,u_5);DSRL32 (u_7,u_6,u_5);DSRLV (u_7,u_6,u_5);SLL (u_7,u_6,u_5);SLLV (u_7,u_6,u_5);SRA (u_7,u_6,u_5);SRAV (u_7,u_6,u_5);SRL (u_7,u_6,u_5);SRLV (u_7,u_6,u_5);SLT (u_7,u_6,u_5);SLTI (u_6,u_5,u_10);SLTU (u_7,u_6,u_5);SLTIU (u_6,u_5,u_10);MOVN (u_7,u_6,u_5);MOVZ (u_7,u_6,u_5);MFHI u_5;MFLO u_5;MTHI u_5;MTLO u_5;MUL (u_7,u_6,u_5);MULT (u_6,u_5);MULTU (u_6,u_5);DMULT (u_6,u_5);DMULTU (u_6,u_5);MADD (u_6,u_5);MADDU (u_6,u_5);MSUB (u_6,u_5);MSUBU (u_6,u_5);DIV0 (u_6,u_5);DIVU (u_6,u_5);DDIV (u_6,u_5);DDIVU (u_6,u_5);J u_11;JAL u_11;JR u_5;JALR (u_6,u_5);BEQ (u_6,u_5,u_4,u_3,u_2);BCMPZ (u_5,u_4,u_0,u_3,u_2);SYSCALL u_8;BREAK u_8;WAIT u_8;TRAPREG (u_6,u_5,u_0);TRAPIMM (u_5,u_4,u_0);Load (u_1,u_3,u_2,u_6,u_5,u_4);Store (u_1,u_2,u_6,u_5,u_4);LWL (u_6,u_5,u_10);LWR (u_6,u_5,u_10);SWL (u_6,u_5,u_10);SWR (u_6,u_5,u_10);LDL (u_6,u_5,u_10);LDR (u_6,u_5,u_10);SDL (u_6,u_5,u_10);SDR (u_6,u_5,u_10);CACHE (u_6,u_5,u_10);SYNC u_8;MFC0 (u_6,u_5,u_9,u_2);HCF u_8;MTC0 (u_6,u_5,u_9,u_2);TLBWI u_8;TLBWR u_8;TLBR u_8;TLBP u_8;RDHWR (u_6,u_5);ERET u_8;RI u_8]))))))))))))))`;
+
+
+(*val execute : ast -> M unit*)
+
+(*val decode : mword ty32 -> maybe ast*)
+
+(*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*)
+
+val _ = Define `
+ ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign=
+    (if sign then (mips_sign_extend (( 64 : int):ii) memResult  :  64 words$word)
+   else (mips_zero_extend (( 64 : int):ii) memResult  :  64 words$word)))`;
+
+
+(*val TLBWriteEntry : mword ty6 -> M unit*)
+
+val _ = Define `
+ ((TLBWriteEntry:(6)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS TLBPageMask_ref  : ( 16 words$word) M) (\ pagemask . 
+   let b__0 = pagemask in sail2_state_monad$seqS
+   (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word))))
+    then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      sail2_state_monad$returnS () 
+    else SignalException MCheck)
+   (let i = (lem$w2ui idx) in
+   let entry = (access_list_dec TLBEntries i) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_pagemask entry pagemask)
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0  :  2 words$word)))
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1  :  27 words$word)))
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2  :  8 words$word)))
+   (sail2_state$and_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . 
+      sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4  :  1 words$word)))))))) (\ (w__5 : bool) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (set_TLBEntry_g entry ((bool_to_bits w__5  :  1 words$word)))
+   (set_TLBEntry_valid entry ((cast_unit_vec0 B1  :  1 words$word))))
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8  :  24 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9  :  3 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14  :  24 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15  :  3 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16  :  1 words$word)))
+   (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . 
+   set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17  :  1 words$word))))))))))))))))))))))`;
+
+
+val _ = Define `
+ ((decode:(32)words$word ->(ast)option) v__0=
+    (if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (DADDIU (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DADDU (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (DADDI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DADD (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (ADD (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (ADDI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (ADDU (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (ADDIU (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DSUBU (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DSUB (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SUB0 (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SUBU (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (AND (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (ANDI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (OR (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (ORI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (NOR (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (XOR (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (XORI (rs,rt,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (LUI (rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (DSLL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (DSLL32 (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DSLLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B1]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (DSRA (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (DSRA32 (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DSRAV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (DSRL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (DSRL32 (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (DSRLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (SLL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SLLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (SRA (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SRAV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii)  :  5 words$word)) in
+     SOME (SRL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SRLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SLT (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (SLTI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (SLTU (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (SLTIU (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (MOVN (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (MOVZ (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (MFHI rd)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (MFLO rd)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 0 : int):ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1]
+                     :  21 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     SOME (MTHI rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 0 : int):ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1]
+                     :  21 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     SOME (MTLO rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (MUL (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (MULT (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (MULTU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (DMULT (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (DMULTU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (MADD (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (MADDU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (MSUB (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (MSUBU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (DIV0 (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (DIVU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (DDIV (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  :  16 words$word)))))))
+   then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (DDIVU (rs,rt))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word)))) then
+     let (offset : 26 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 0 : int):ii)  :  26 words$word)) in
+     SOME (J offset)
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word)))) then
+     let (offset : 26 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 0 : int):ii)  :  26 words$word)) in
+     SOME (JAL offset)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):ii) (( 11 : int):ii)  :  10 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  10 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0]  :  6 words$word)))))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     SOME (JR rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1]  :  6 words$word)))))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (JALR (rs,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,F,F))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,F,T))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,T,F))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',T,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,T,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GT',F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GT',F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LE,F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word))))))) then
+     SOME (SYSCALL () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word))))))) then
+     SOME (BREAK () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B1;B0;B0;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (WAIT () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,GE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,GEU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,LT'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,LTU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0]  :  6 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,EQ'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0]  :  6 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,NE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,EQ'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,NE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,GE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,GEU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,LT'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word))))))) then
+     let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,LTU))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (B,T,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (B,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (H,T,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (H,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (W0,T,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (W0,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (D,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (W0,T,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Load (D,F,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Store (B,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Store (H,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Store (W0,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Store (D,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Store (W0,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (Store (D,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (LWL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (LWR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (SWL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (SWR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (LDL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (LDR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (SDL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (SDR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B1]  :  6 words$word)))) then
+     let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii)  :  5 words$word)) in
+     let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) in
+     SOME (CACHE (base,op,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 11 : int):ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word))))))) then
+     SOME (SYNC () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+     SOME (MFC0 (rt,rd,sel,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+     SOME (MFC0 (rt,rd,sel,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))))))
+   then
+     SOME (HCF () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))))))
+   then
+     SOME (HCF () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+     SOME (MTC0 (rt,rd,sel,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+     SOME (MTC0 (rt,rd,sel,T))
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B1;B0]
+                 :  32 words$word)))) then
+     SOME (TLBWI () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B1;B1;B0]
+                 :  32 words$word)))) then
+     SOME (TLBWR () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B1]
+                 :  32 words$word)))) then
+     SOME (TLBR () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B1;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (TLBP () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii)  :  5 words$word)) in
+     let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii)  :  5 words$word)) in
+     SOME (RDHWR (rt,rd))
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B1;B1;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (ERET () )
+   else SOME (RI () )))`;
+
+
+(*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((xor_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_WAIT : unit -> M unit*)
+
+val _ = Define `
+ ((execute_WAIT:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__16=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$write_regS nextPC_ref w__0)))`;
+
+
+(*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*)
+
+val _ = Define `
+ ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt cmp=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rs_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val . 
+   let condition = (compare cmp rs_val rt_val) in
+   if condition then SignalException Tr
+   else sail2_state_monad$returnS () ))))`;
+
+
+(*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*)
+
+val _ = Define `
+ ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rs_val . 
+   let (imm_val : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word)) in
+   let condition = (compare cmp rs_val imm_val) in
+   if condition then SignalException Tr
+   else sail2_state_monad$returnS () )))`;
+
+
+(*val execute_TLBWR : unit -> M unit*)
+
+val _ = Define `
+ ((execute_TLBWR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__20=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
+
+
+(*val execute_TLBWI : unit -> M unit*)
+
+val _ = Define `
+ ((execute_TLBWI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__19=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (sail2_state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
+
+
+(*val execute_TLBR : unit -> M unit*)
+
+val _ = Define `
+ ((execute_TLBR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__21=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (sail2_state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . 
+   let i = (lem$w2ui w__0) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry .  sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry  :  16 words$word)))
+   (set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry  :  2 words$word))))
+   (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry  :  27 words$word))))
+   (set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry  :  8 words$word))))
+   (set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry  :  24 words$word))))
+   (set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry  :  3 words$word))))
+   (set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry  :  1 words$word))))
+   (set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry  :  24 words$word))))
+   (set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry  :  3 words$word))))
+   (set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry  :  1 words$word))))
+   (set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry  :  1 words$word)))))))`;
+
+
+(*val execute_TLBP : unit -> M unit*)
+
+val _ = Define `
+ ((execute_TLBP:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__22=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) .  sail2_state_monad$bindS
+   (tlbSearch ((get_TLBEntryHiReg_bits w__0  :  64 words$word))  : ( ( 6 words$word)option) M) (\ result . 
+   (case result of
+     SOME (idx) => sail2_state_monad$seqS
+      (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B0]  :  1 words$word)) (sail2_state_monad$write_regS TLBIndex_ref idx)
+   | NONE => sail2_state_monad$seqS
+      (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B1]  :  1 words$word))
+      (sail2_state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))
+   )))))`;
+
+
+(*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width conditional base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let (vAddr : 64 bits) =
+     ((addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
+        StoreData width
+       :  64 words$word)) in sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val . 
+   if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr
+   else sail2_state_monad$bindS
+     (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr . 
+     if conditional then sail2_state_monad$bindS
+       (sail2_state_monad$read_regS CP0LLBit_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) .  sail2_state_monad$bindS
+       (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then
+          (case width of
+            W0 =>
+             MEMw_conditional_wrapper pAddr (( 4 : int):ii)
+               ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rt_val
+          | _ => sail2_state_monad$throwS (Error_internal_error () )
+          )
+        else sail2_state_monad$returnS F) (\ (success : bool) . 
+       wGPR rt ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+     else
+       (case width of
+         B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+       | H => MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec rt_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+       | W0 => MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+       | D => MEMw_wrapper pAddr (( 8 : int):ii) rt_val
+       ))))))`;
+
+
+(*val execute_SYSCALL : unit -> M unit*)
+
+val _ = Define `
+ ((execute_SYSCALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__14=  (SignalException Sys))`;
+
+
+(*val execute_SYNC : unit -> M unit*)
+
+val _ = Define `
+ ((execute_SYNC:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__17=  (MEM_sync () ))`;
+
+
+(*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData
+        WR
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr . 
+   let wordAddr =
+     ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word))
+        (vec_of_bits [B0;B0]  :  2 words$word)
+       :  64 words$word)) in sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__12 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+   if (((b__12 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+     MEMw_wrapper wordAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+   else if (((b__12 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+     MEMw_wrapper wordAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+   else if (((b__12 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+     MEMw_wrapper wordAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+   else MEMw_wrapper wordAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))))))`;
+
+
+(*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData
+        WL
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__8 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+   if (((b__8 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+     MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+   else if (((b__8 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+     MEMw_wrapper pAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 8 : int):ii)  :  24 words$word))
+   else if (((b__8 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+     MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word))
+   else MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word)))))))`;
+
+
+(*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ opB . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     wGPR rd
+       ((mips_sign_extend (( 64 : int):ii)
+           ((sub_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+               ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+              :  32 words$word))
+          :  64 words$word))))))`;
+
+
+(*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ opB . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let (temp33 : 33 bits) =
+       ((sub_vec
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
+         :  33 words$word)) in
+     if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):ii)))))
+            ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):ii))))))) then
+       SignalException Ov
+     else
+       wGPR rd
+         ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  64 words$word))))))`;
+
+
+(*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+     (shift_bits_right 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2  :  64 words$word)))))))`;
+
+
+(*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp . 
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+     (shift_bits_right 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1  :  64 words$word))))))`;
+
+
+(*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+     (shift_bits_right_arith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2  :  64 words$word)))))))`;
+
+
+(*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp . 
+   if ((NotWordVal temp)) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+     (shift_bits_right_arith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+     wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1  :  64 words$word))))))`;
+
+
+(*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rs_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rt_val . 
+   wGPR rd
+     ((mips_zero_extend (( 64 : int):ii)
+         (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word))))))`;
+
+
+(*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rs_val . 
+   let (immext : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word)) in
+   wGPR rt
+     ((mips_zero_extend (( 64 : int):ii)
+         (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word)))))`;
+
+
+(*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=
+    (let imm_val = (integer_word$w2i imm) in sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let rs_val = (integer_word$w2i w__0) in
+   wGPR rt
+     ((mips_zero_extend (( 64 : int):ii)
+         (if ((rs_val < imm_val)) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word)))))`;
+
+
+(*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd
+     ((mips_zero_extend (( 64 : int):ii)
+         (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word))))))`;
+
+
+(*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__2 :  32 words$word) . 
+   wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2  :  64 words$word)))))))`;
+
+
+(*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+   wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1  :  64 words$word))))))`;
+
+
+(*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData
+        DR
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let wordAddr =
+     ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii)  :  61 words$word))
+        (vec_of_bits [B0;B0;B0]  :  3 words$word)
+       :  64 words$word)) in
+   let b__40 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+   if (((b__40 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+   else if (((b__40 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+   else if (((b__40 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+   else if (((b__40 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+   else if (((b__40 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 5 : int):ii) ((subrange_vec_dec reg_val (( 39 : int):ii) (( 0 : int):ii)  :  40 words$word))
+   else if (((b__40 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 6 : int):ii) ((subrange_vec_dec reg_val (( 47 : int):ii) (( 0 : int):ii)  :  48 words$word))
+   else if (((b__40 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 7 : int):ii) ((subrange_vec_dec reg_val (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word))
+   else MEMw_wrapper wordAddr (( 8 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
+
+
+(*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) StoreData
+        DL
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__32 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+   if (((b__32 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 8 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+   else if (((b__32 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 7 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 8 : int):ii)  :  56 words$word))
+   else if (((b__32 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 6 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 16 : int):ii)  :  48 words$word))
+   else if (((b__32 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 5 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 24 : int):ii)  :  40 words$word))
+   else if (((b__32 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+   else if (((b__32 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 40 : int):ii)  :  24 words$word))
+   else if (((b__32 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 48 : int):ii)  :  16 words$word))
+   else MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word)))))))`;
+
+
+(*val execute_RI : unit -> M unit*)
+
+val _ = Define `
+ ((execute_RI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__24=  (SignalException ResI))`;
+
+
+(*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd=  (sail2_state_monad$bindS
+   (getAccessLevel () ) (\ accessLevel . 
+   let (haveAccessLevel : bool) = (accessLevel = Kernel) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . 
+   let (haveCU0 : bool) =
+     (B1 = ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):ii)))) in
+   let rdi = (lem$w2ui rd) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS CP0HWREna_ref  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+   let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in sail2_state_monad$seqS
+   (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI
+    else sail2_state_monad$returnS () )
+   (let b__146 = rd in sail2_state_monad$bindS
+   (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) then
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M) (\ (w__2 : 32 bits) . 
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2  :  64 words$word)))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) then
+      sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))) then
+      (sail2_state_monad$read_regS CP0UserLocal_ref  : ( 64 words$word) M)
+    else (SignalException ResI  : ( 64 words$word) M)) (\ (temp : 64 bits) . 
+   wGPR rt temp)))))))`;
+
+
+(*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((or_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((not_vec ((or_vec w__0 w__1  :  64 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                 ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (result : 64 bits) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HI_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
+     LO_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))`;
+
+
+(*val execute_MULT : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                 ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (result : 64 bits) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HI_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
+     LO_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))`;
+
+
+(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal . 
+   let (result : 64 bits) =
+     ((mips_sign_extend (( 64 : int):ii)
+        ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+           :  64 words$word))
+       :  64 words$word)) in sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (w__1 :  64 words$word) . 
+   wGPR rd w__1)))))`;
+
+
+(*val execute_MTLO : mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MTLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$write_regS LO_ref w__0)))`;
+
+
+(*val execute_MTHI : mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MTHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$write_regS HI_ref w__0)))`;
+
+
+(*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*)
+
+val _ = Define `
+ ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (rGPR rt  : ( 64 words$word) M)) (\ reg_val . 
+   (case (rd, sel) of
+     (b__108, b__109) =>
+      if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS TLBIndex_ref ((mask (( 6 : int):ii) reg_val  :  6 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS () 
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_ContextReg_PTEBase TLBContext_ref
+          ((subrange_vec_dec reg_val (( 63 : int):ii) (( 23 : int):ii)  :  41 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0UserLocal_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 : int):ii) (( 13 : int):ii)  :  16 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$seqS
+        (sail2_state_monad$write_regS TLBWired_ref ((mask (( 6 : int):ii) reg_val  :  6 words$word)))
+        (sail2_state_monad$write_regS TLBRandom_ref TLBIndexMax)
+      else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS
+          CP0HWREna_ref
+          ((concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 29 : int):ii)  :  3 words$word))
+              ((concat_vec
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0]
+                    :  25 words$word) ((subrange_vec_dec reg_val (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+                 :  29 words$word))
+             :  32 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS () 
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0Count_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+        (set_TLBEntryHiReg_R TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))
+        (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 39 : int):ii) (( 13 : int):ii)  :  27 words$word))))
+        (set_TLBEntryHiReg_ASID TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0Compare_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))
+        (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__0 : CauseReg) . 
+        set_CauseReg_IP CP0Cause_ref
+          ((and_vec ((get_CauseReg_IP w__0  :  8 words$word))
+              (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1]  :  8 words$word)
+             :  8 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+        (set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)))
+        (set_StatusReg_BEV CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word))))
+        (set_StatusReg_KX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_SX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_UX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word))))
+        (set_StatusReg_ERL CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_EXL CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 : int):ii)))  :  1 words$word))))
+        (set_StatusReg_IE CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 : int):ii)))  :  1 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+        (set_CauseReg_IV CP0Cause_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 : int):ii)))  :  1 words$word)))
+        (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__1 : CauseReg) . 
+        let ip = ((get_CauseReg_IP w__1  :  8 words$word)) in
+        set_CauseReg_IP CP0Cause_ref
+          ((concat_vec ((subrange_vec_dec ip (( 7 : int):ii) (( 2 : int):ii)  :  6 words$word))
+              ((subrange_vec_dec reg_val (( 9 : int):ii) (( 8 : int):ii)  :  2 words$word))
+             :  8 words$word)))
+      else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0EPC_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word))
+      else if ((((((b__108 = (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        set_XContextReg_XPTEBase TLBXContext_ref
+          ((subrange_vec_dec reg_val (( 63 : int):ii) (( 33 : int):ii)  :  31 words$word))
+      else if ((((((b__108 = (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$write_regS CP0ErrorEPC_ref reg_val
+      else SignalException ResI
+   ))))`;
+
+
+(*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                 ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+   let result =
+     ((sub_vec
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+           :  64 words$word)) mul_result
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HI_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
+     LO_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
+
+
+(*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                 ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+   let result =
+     ((sub_vec
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+           :  64 words$word)) mul_result
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HI_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
+     LO_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
+
+
+(*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+            :  64 words$word)))) then sail2_state_monad$bindS
+     (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else sail2_state_monad$returnS () )))`;
+
+
+(*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+            :  64 words$word)))) then sail2_state_monad$bindS
+     (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else sail2_state_monad$returnS () )))`;
+
+
+(*val execute_MFLO : mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MFLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
+
+
+(*val execute_MFHI : mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MFHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
+
+
+(*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*)
+
+val _ = Define `
+ ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double=  (sail2_state_monad$bindS (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (case (rd, sel) of
+     (b__48, b__49) =>
+      if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBIndex_ref  : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . 
+        let (idx : 31 bits) = ((mips_zero_extend (( 31 : int):ii) w__0  :  31 words$word)) in sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBProbe_ref  : ( 1 words$word) M) (\ (w__1 : 1 bits) . 
+        sail2_state_monad$returnS ((concat_vec
+                   (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  32 words$word) ((concat_vec w__1 idx  :  32 words$word))
+                  :  64 words$word))))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBRandom_ref  : ( 6 words$word) M) (\ (w__2 : TLBIndexT) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . 
+        sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__3  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . 
+        sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__4  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBContext_ref) (\ (w__5 : ContextReg) . 
+        sail2_state_monad$returnS ((get_ContextReg_bits w__5  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0UserLocal_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBPageMask_ref  : ( 16 words$word) M) (\ (w__7 : 16 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec w__7
+                       (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+                      :  28 words$word))
+                  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBWired_ref  : ( 6 words$word) M) (\ (w__8 : TLBIndexT) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__8  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0HWREna_ref  : ( 32 words$word) M) (\ (w__9 : 32 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__9  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0BadVAddr_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Count_ref  : ( 32 words$word) M) (\ (w__11 : 32 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__11  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBEntryHi_ref) (\ (w__12 : TLBEntryHiReg) . 
+        sail2_state_monad$returnS ((get_TLBEntryHiReg_bits w__12  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Compare_ref  : ( 32 words$word) M) (\ (w__13 : 32 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__13  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Status_ref) (\ (w__14 : StatusReg) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_StatusReg_bits w__14  :  32 words$word))  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__15 : CauseReg) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_CauseReg_bits w__15  :  32 words$word))  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0EPC_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  32 words$word)
+                  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS CP0ConfigK0_ref  : ( 3 words$word) M) (\ (w__17 : 3 bits) . 
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                       ((concat_vec
+                           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  15 words$word)
+                           ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                               ((concat_vec (vec_of_bits [B1;B0]  :  2 words$word)
+                                   ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                       ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                                           ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                               w__17
+                                              :  7 words$word))
+                                          :  10 words$word))
+                                      :  13 words$word))
+                                  :  15 words$word))
+                              :  16 words$word))
+                          :  31 words$word))
+                      :  32 words$word))
+                  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                       ((concat_vec TLBIndexMax
+                           ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                               ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                   ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                       ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                           ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                               ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                                                   ((concat_vec
+                                                       ((bool_to_bits have_cp2  :  1 words$word))
+                                                       ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                                                           ((concat_vec
+                                                               (vec_of_bits [B0]  :  1 words$word)
+                                                               ((concat_vec
+                                                                   (vec_of_bits [B0]  :  1 words$word)
+                                                                   ((concat_vec
+                                                                       (vec_of_bits [B0]
+                                                                         :  1 words$word)
+                                                                       ((concat_vec
+                                                                           (vec_of_bits [B0]
+                                                                             :  1 words$word)
+                                                                           (vec_of_bits [B0]
+                                                                             :  1 words$word)
+                                                                          :  2 words$word))
+                                                                      :  3 words$word))
+                                                                  :  4 words$word))
+                                                              :  5 words$word))
+                                                          :  6 words$word))
+                                                      :  7 words$word))
+                                                  :  10 words$word))
+                                              :  13 words$word))
+                                          :  16 words$word))
+                                      :  19 words$word))
+                                  :  22 words$word))
+                              :  25 words$word))
+                          :  31 words$word))
+                      :  32 words$word))
+                  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii)
+                   ((concat_vec (vec_of_bits [B1]  :  1 words$word)
+                       ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                           ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                               ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                   ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                       ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                           ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                               ((concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                                   (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+                                                  :  8 words$word))
+                                              :  12 words$word))
+                                          :  16 words$word))
+                                      :  20 words$word))
+                                  :  24 words$word))
+                              :  28 words$word))
+                          :  31 words$word))
+                      :  32 words$word))
+                  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                 :  64 words$word)
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) then
+        sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                 :  64 words$word)
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0LLAddr_ref  : ( 64 words$word) M)
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+      else if ((((((b__48 = (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS TLBXContext_ref) (\ (w__19 : XContextReg) . 
+        sail2_state_monad$returnS ((get_XContextReg_bits w__19  :  64 words$word)))
+      else if ((((((b__48 = (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+        (sail2_state_monad$read_regS CP0ErrorEPC_ref  : ( 64 words$word) M)
+      else (SignalException ResI  : ( 64 words$word) M)
+   )) (\ (result : 64 bits) . 
+   wGPR rt
+     (if double then result
+      else
+        (mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  64 words$word)))))`;
+
+
+(*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                 ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+   let result =
+     ((add_vec mul_result
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+           :  64 words$word))
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HI_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
+     LO_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
+
+
+(*val execute_MADD : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)
+    else
+      sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                 ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+                :  64 words$word))) (\ (mul_result : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS HI_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS LO_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) . 
+   let result =
+     ((add_vec mul_result
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+           :  64 words$word))
+       :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
+     HI_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$write_regS
+     LO_ref
+     ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+        :  64 words$word))))))))))`;
+
+
+(*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width sign linked base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let (vAddr : 64 bits) =
+     ((addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word))
+        LoadData width
+       :  64 words$word)) in
+   if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr
+   else sail2_state_monad$bindS
+     (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+     (if linked then sail2_state_monad$seqS (sail2_state_monad$seqS
+        (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))
+        (sail2_state_monad$write_regS CP0LLAddr_ref pAddr))
+        (case width of
+          W0 => sail2_state_monad$bindS
+           (MEMr_reserve_wrapper pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__1 :  32 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__1 sign  :  64 words$word)))
+        | D => sail2_state_monad$bindS
+           (MEMr_reserve_wrapper pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__2 sign  :  64 words$word)))
+        | _ => sail2_state_monad$throwS (Error_internal_error () )
+        )
+      else
+        (case width of
+          B => sail2_state_monad$bindS
+           (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii)  : ( 8 words$word) M) (\ (w__5 :  8 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__5 sign  :  64 words$word)))
+        | H => sail2_state_monad$bindS
+           (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii)  : ( 16 words$word) M) (\ (w__6 :  16 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__6 sign  :  64 words$word)))
+        | W0 => sail2_state_monad$bindS
+           (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii)  : ( 32 words$word) M) (\ (w__7 :  32 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__7 sign  :  64 words$word)))
+        | D => sail2_state_monad$bindS
+           (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii)  : ( 64 words$word) M) (\ (w__8 :  64 words$word) . 
+           sail2_state_monad$returnS ((extendLoad w__8 sign  :  64 words$word)))
+        )) (\ (memResult : 64 bits) . 
+     wGPR rt memResult)))))`;
+
+
+(*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData WR
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (MEMr_wrapper (( 32 : int):ii)
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word))
+          (vec_of_bits [B0;B0]  :  2 words$word)
+         :  64 words$word)) (( 4 : int):ii)
+     : ( 32 words$word) M) (\ mem_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__4 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+   let (result : 32 bits) =
+     (if (((b__4 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 8 : int):ii)  :  24 words$word))
+          ((subrange_vec_dec mem_val (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word))
+         :  32 words$word)
+     else if (((b__4 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word))
+          ((subrange_vec_dec mem_val (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word))
+         :  32 words$word)
+     else if (((b__4 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 24 : int):ii)  :  8 words$word))
+          ((subrange_vec_dec mem_val (( 31 : int):ii) (( 8 : int):ii)  :  24 words$word))
+         :  32 words$word)
+     else mem_val) in
+   wGPR rt ((mips_sign_extend (( 64 : int):ii) result  :  64 words$word))))))))`;
+
+
+(*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData WL
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (MEMr_wrapper (( 32 : int):ii)
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word))
+          (vec_of_bits [B0;B0]  :  2 words$word)
+         :  64 words$word)) (( 4 : int):ii)
+     : ( 32 words$word) M) (\ mem_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__0 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+   let (result : 32 bits) =
+     (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then mem_val
+     else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec mem_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+         :  32 words$word)
+     else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec mem_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+          ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+         :  32 words$word)
+     else
+       (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+         :  32 words$word)) in
+   wGPR rt ((mips_sign_extend (( 64 : int):ii) result  :  64 words$word))))))))`;
+
+
+(*val execute_LUI : mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt imm=
+    (wGPR rt
+     ((mips_sign_extend (( 64 : int):ii)
+         ((concat_vec imm
+             (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)
+            :  32 words$word))
+        :  64 words$word))))`;
+
+
+(*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData DR
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (MEMr_wrapper (( 64 : int):ii)
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii)  :  61 words$word))
+          (vec_of_bits [B0;B0;B0]  :  3 words$word)
+         :  64 words$word)) (( 8 : int):ii)
+     : ( 64 words$word) M) (\ mem_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__24 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+   wGPR rt
+     (if (((b__24 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 8 : int):ii)  :  56 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 16 : int):ii)  :  48 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 48 : int):ii)  :  16 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 24 : int):ii)  :  40 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 40 : int):ii)  :  24 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 32 : int):ii)  :  32 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 40 : int):ii)  :  24 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 24 : int):ii)  :  40 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 48 : int):ii)  :  16 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 16 : int):ii)  :  48 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):ii) (( 8 : int):ii)  :  56 words$word))
+          :  64 words$word)
+      else mem_val)))))))`;
+
+
+(*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset=  (sail2_state_monad$bindS
+   (rGPR base  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let vAddr =
+     ((addrWrapperUnaligned
+        ((add_vec ((mips_sign_extend (( 64 : int):ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData DL
+       :  64 words$word)) in sail2_state_monad$bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) M) (\ pAddr .  sail2_state_monad$bindS
+   (MEMr_wrapper (( 64 : int):ii)
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii)  :  61 words$word))
+          (vec_of_bits [B0;B0;B0]  :  3 words$word)
+         :  64 words$word)) (( 8 : int):ii)
+     : ( 64 words$word) M) (\ mem_val .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ reg_val . 
+   let b__16 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) in
+   wGPR rt
+     (if (((b__16 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then mem_val
+      else if (((b__16 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word))
+           ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 47 : int):ii) (( 0 : int):ii)  :  48 words$word))
+           ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 39 : int):ii) (( 0 : int):ii)  :  40 words$word))
+           ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+           ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 23 : int):ii) (( 0 : int):ii)  :  24 words$word))
+           ((subrange_vec_dec reg_val (( 39 : int):ii) (( 0 : int):ii)  :  40 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+           ((subrange_vec_dec reg_val (( 47 : int):ii) (( 0 : int):ii)  :  48 words$word))
+          :  64 words$word)
+      else
+        (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+           ((subrange_vec_dec reg_val (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word))
+          :  64 words$word))))))))`;
+
+
+(*val execute_JR : mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_JR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs=  (sail2_state_monad$bindS (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  execute_branch w__0)))`;
+
+
+(*val execute_JALR : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (execute_branch w__0)
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((add_vec_int w__1 (( 8 : int):ii)  :  64 words$word))))))`;
+
+
+(*val execute_JAL : mword ty26 -> M unit*)
+
+val _ = Define `
+ ((execute_JAL:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (execute_branch
+     ((concat_vec
+         ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii)  :  64 words$word)) (( 63 : int):ii) (( 28 : int):ii)  :  36 words$word))
+         ((concat_vec offset (vec_of_bits [B0;B0]  :  2 words$word)  :  28 words$word))
+        :  64 words$word)))
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
+   wGPR (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) ((add_vec_int w__1 (( 8 : int):ii)  :  64 words$word))))))`;
+
+
+(*val execute_J : mword ty26 -> M unit*)
+
+val _ = Define `
+ ((execute_J:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+   execute_branch
+     ((concat_vec
+         ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii)  :  64 words$word)) (( 63 : int):ii) (( 28 : int):ii)  :  36 words$word))
+         ((concat_vec offset (vec_of_bits [B0;B0]  :  2 words$word)  :  28 words$word))
+        :  64 words$word)))))`;
+
+
+(*val execute_HCF : unit -> unit*)
+
+val _ = Define `
+ ((execute_HCF:unit -> unit) g__18=  () )`;
+
+
+(*val execute_ERET : unit -> M unit*)
+
+val _ = Define `
+ ((execute_ERET:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__23=  (sail2_state_monad$seqS
+   (checkCP0Access () )
+   (let (_ : unit) = (ERETHook () ) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0]  :  1 words$word))
+   (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . 
+   if (((((bits_to_bool ((get_StatusReg_ERL w__0  :  1 words$word)))) = ((bit_to_bool B1))))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CP0ErrorEPC_ref  : ( 64 words$word) M) (\ (w__1 : 64 bits) .  sail2_state_monad$seqS
+     (sail2_state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0]  :  1 words$word)))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS CP0EPC_ref  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$seqS
+     (sail2_state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0]  :  1 words$word)))))))`;
+
+
+(*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((sub_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let (temp65 : 65 bits) =
+     ((sub_vec ((mips_sign_extend (( 65 : int):ii) w__0  :  65 words$word))
+        ((mips_sign_extend (( 65 : int):ii) w__1  :  65 words$word))
+       :  65 words$word)) in
+   if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):ii)))))
+          ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):ii))))))) then
+     SignalException Ov
+   else wGPR rd ((subrange_vec_dec temp65 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))))))`;
+
+
+(*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) in sail2_state_monad$bindS
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
+
+
+(*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp . 
+   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in sail2_state_monad$bindS
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word)) in sail2_state_monad$bindS
+   (shift_bits_right_arith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
+
+
+(*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp . 
+   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in sail2_state_monad$bindS
+   (shift_bits_right_arith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ temp .  sail2_state_monad$bindS
+   (shift_bits_right_arith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))  : ( 64 words$word) M) (\ (w__2 :
+      64 words$word) . 
+   wGPR rd w__2)))))`;
+
+
+(*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word))
+     : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd w__1))))`;
+
+
+(*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa=  (sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  wGPR rd w__1))))`;
+
+
+(*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let result = ((mult_vec w__0 w__1  :  128 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
+
+
+(*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let result = ((mults_vec w__0 w__1  :  128 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))))`;
+
+
+(*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  64 words$word)))))))))) then sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 : 32 bits) .  sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS (w__0, w__1)))
+    else
+      let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
+      let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
+      let qi = (hardware_quot si ti) in
+      let ri = (hardware_mod si ti) in
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) qi  :  32 words$word),
+              (to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q  :  64 words$word))))))))`;
+
+
+(*val execute_DIV : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ rsVal .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ rtVal .  sail2_state_monad$bindS
+   (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  64 words$word)))))))))) then sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__0 : 32 bits) .  sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M) (\ (w__1 : 32 bits) . 
+      sail2_state_monad$returnS (w__0, w__1)))
+    else
+      let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
+      let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))) in
+      let qi = (hardware_quot si ti) in
+      let ri = (si - ((ti * qi))) in
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) qi  :  32 words$word),
+              (to_bits ((make_the_value (( 32 : int):ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r  :  64 words$word)))
+   (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q  :  64 words$word))))))))`;
+
+
+(*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let rsVal = (lem$w2ui w__0) in sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let rtVal = (lem$w2ui w__1) in sail2_state_monad$bindS
+   (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+      sail2_state_monad$returnS (w__2, w__3)))
+    else
+      let qi = (hardware_quot rsVal rtVal) in
+      let ri = (hardware_mod rsVal rtVal) in
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) qi  :  64 words$word),
+              (to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`;
+
+
+(*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let rsVal = (integer_word$w2i w__0) in sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let rtVal = (integer_word$w2i w__1) in sail2_state_monad$bindS
+   (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__2 : 64 bits) .  sail2_state_monad$bindS
+      (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__3 : 64 bits) . 
+      sail2_state_monad$returnS (w__2, w__3)))
+    else
+      let qi = (hardware_quot rsVal rtVal) in
+      let ri = (rsVal - ((qi * rtVal))) in
+      sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) qi  :  64 words$word),
+              (to_bits ((make_the_value (( 64 : int):ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`;
+
+
+(*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((add_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let (sum65 : 65 bits) =
+     ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0  :  65 words$word))
+        ((mips_sign_extend (( 65 : int):ii) imm  :  65 words$word))
+       :  65 words$word)) in
+   if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii)))))
+          ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then
+     SignalException Ov
+   else wGPR rt ((subrange_vec_dec sum65 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))))`;
+
+
+(*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   let (sum65 : 65 bits) =
+     ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0  :  65 words$word))
+        ((mips_sign_extend (( 65 : int):ii) w__1  :  65 words$word))
+       :  65 words$word)) in
+   if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii)))))
+          ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then
+     SignalException Ov
+   else wGPR rd ((subrange_vec_dec sum65 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))))))`;
+
+
+(*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base op imm=  (checkCP0Access () ))`;
+
+
+(*val execute_BREAK : unit -> M unit*)
+
+val _ = Define `
+ ((execute_BREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__15=  (SignalException Bp))`;
+
+
+(*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd imm ne likely=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rd  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   if ((bits_to_bool
+          ((xor_vec ((bool_to_bits (((w__0 = w__1)))  :  1 words$word))
+              ((bool_to_bits ne  :  1 words$word))
+             :  1 words$word)))) then
+     let (offset : 64 bits) =
+       ((add_vec_int
+          ((mips_sign_extend (( 64 : int):ii)
+              ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+             :  64 words$word)) (( 4 : int):ii)
+         :  64 words$word)) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+     execute_branch ((add_vec w__2 offset  :  64 words$word)))
+   else if likely then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
+     sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii)  :  64 words$word)))
+   else sail2_state_monad$returnS () ))))`;
+
+
+(*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*)
+
+val _ = Define `
+ ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp link likely=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : 64 bits) . 
+   let linkVal = ((add_vec_int w__0 (( 8 : int):ii)  :  64 words$word)) in sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ regVal . 
+   let condition =
+     (compare cmp regVal ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in sail2_state_monad$seqS
+   (if condition then
+      let (offset : 64 bits) =
+        ((add_vec_int
+           ((mips_sign_extend (( 64 : int):ii)
+               ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+              :  64 words$word)) (( 4 : int):ii)
+          :  64 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+      execute_branch ((add_vec w__1 offset  :  64 words$word)))
+    else if likely then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+      sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii)  :  64 words$word)))
+    else sail2_state_monad$returnS () )
+   (if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) linkVal
+   else sail2_state_monad$returnS () )))))`;
+
+
+(*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((and_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ opB . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     wGPR rd
+       ((mips_sign_extend (( 64 : int):ii)
+           ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+               ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+              :  32 words$word))
+          :  64 words$word))))))`;
+
+
+(*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA . 
+   if ((NotWordVal opA)) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
+   else
+     wGPR rt
+       ((mips_sign_extend (( 64 : int):ii)
+           ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+               ((mips_sign_extend (( 32 : int):ii) imm  :  32 words$word))
+              :  32 words$word))
+          :  64 words$word)))))`;
+
+
+(*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ opA . 
+   if ((NotWordVal opA)) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
+   else
+     let (sum33 : 33 bits) =
+       ((add_vec
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word)) ((mips_sign_extend (( 33 : int):ii) imm  :  33 words$word))
+         :  33 words$word)) in
+     if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii)))))
+            ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then
+       SignalException Ov
+     else
+       wGPR rt
+         ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  64 words$word)))))`;
+
+
+(*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+
+val _ = Define `
+ ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd=  (sail2_state_monad$bindS
+   (rGPR rs  : ( 64 words$word) M) (\ (opA : 64 bits) .  sail2_state_monad$bindS
+   (rGPR rt  : ( 64 words$word) M) (\ (opB : 64 bits) . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS
+     (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let (sum33 : 33 bits) =
+       ((add_vec
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
+          ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+             :  33 words$word))
+         :  33 words$word)) in
+     if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii)))))
+            ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then
+       SignalException Ov
+     else
+       wGPR rd
+         ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  64 words$word))))))`;
+
+
+val _ = Define `
+ ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var=
+    ((case merge_var of
+     DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm
+   | DADDU (rs,rt,rd) => execute_DADDU rs rt rd
+   | DADDI (rs,rt,imm) => execute_DADDI rs rt imm
+   | DADD (rs,rt,rd) => execute_DADD rs rt rd
+   | ADD (rs,rt,rd) => execute_ADD rs rt rd
+   | ADDI (rs,rt,imm) => execute_ADDI rs rt imm
+   | ADDU (rs,rt,rd) => execute_ADDU rs rt rd
+   | ADDIU (rs,rt,imm) => execute_ADDIU rs rt imm
+   | DSUBU (rs,rt,rd) => execute_DSUBU rs rt rd
+   | DSUB (rs,rt,rd) => execute_DSUB rs rt rd
+   | SUB0 (rs,rt,rd) => execute_SUB rs rt rd
+   | SUBU (rs,rt,rd) => execute_SUBU rs rt rd
+   | AND (rs,rt,rd) => execute_AND rs rt rd
+   | ANDI (rs,rt,imm) => execute_ANDI rs rt imm
+   | OR (rs,rt,rd) => execute_OR rs rt rd
+   | ORI (rs,rt,imm) => execute_ORI rs rt imm
+   | NOR (rs,rt,rd) => execute_NOR rs rt rd
+   | XOR (rs,rt,rd) => execute_XOR rs rt rd
+   | XORI (rs,rt,imm) => execute_XORI rs rt imm
+   | LUI (rt,imm) => execute_LUI rt imm
+   | DSLL (rt,rd,sa) => execute_DSLL rt rd sa
+   | DSLL32 (rt,rd,sa) => execute_DSLL32 rt rd sa
+   | DSLLV (rs,rt,rd) => execute_DSLLV rs rt rd
+   | DSRA (rt,rd,sa) => execute_DSRA rt rd sa
+   | DSRA32 (rt,rd,sa) => execute_DSRA32 rt rd sa
+   | DSRAV (rs,rt,rd) => execute_DSRAV rs rt rd
+   | DSRL (rt,rd,sa) => execute_DSRL rt rd sa
+   | DSRL32 (rt,rd,sa) => execute_DSRL32 rt rd sa
+   | DSRLV (rs,rt,rd) => execute_DSRLV rs rt rd
+   | SLL (rt,rd,sa) => execute_SLL rt rd sa
+   | SLLV (rs,rt,rd) => execute_SLLV rs rt rd
+   | SRA (rt,rd,sa) => execute_SRA rt rd sa
+   | SRAV (rs,rt,rd) => execute_SRAV rs rt rd
+   | SRL (rt,rd,sa) => execute_SRL rt rd sa
+   | SRLV (rs,rt,rd) => execute_SRLV rs rt rd
+   | SLT (rs,rt,rd) => execute_SLT rs rt rd
+   | SLTI (rs,rt,imm) => execute_SLTI rs rt imm
+   | SLTU (rs,rt,rd) => execute_SLTU rs rt rd
+   | SLTIU (rs,rt,imm) => execute_SLTIU rs rt imm
+   | MOVN (rs,rt,rd) => execute_MOVN rs rt rd
+   | MOVZ (rs,rt,rd) => execute_MOVZ rs rt rd
+   | MFHI (rd) => execute_MFHI rd
+   | MFLO (rd) => execute_MFLO rd
+   | MTHI (rs) => execute_MTHI rs
+   | MTLO (rs) => execute_MTLO rs
+   | MUL (rs,rt,rd) => execute_MUL rs rt rd
+   | MULT (rs,rt) => execute_MULT rs rt
+   | MULTU (rs,rt) => execute_MULTU rs rt
+   | DMULT (rs,rt) => execute_DMULT rs rt
+   | DMULTU (rs,rt) => execute_DMULTU rs rt
+   | MADD (rs,rt) => execute_MADD rs rt
+   | MADDU (rs,rt) => execute_MADDU rs rt
+   | MSUB (rs,rt) => execute_MSUB rs rt
+   | MSUBU (rs,rt) => execute_MSUBU rs rt
+   | DIV0 (rs,rt) => execute_DIV rs rt
+   | DIVU (rs,rt) => execute_DIVU rs rt
+   | DDIV (rs,rt) => execute_DDIV rs rt
+   | DDIVU (rs,rt) => execute_DDIVU rs rt
+   | J (offset) => execute_J offset
+   | JAL (offset) => execute_JAL offset
+   | JR (rs) => execute_JR rs
+   | JALR (rs,rd) => execute_JALR rs rd
+   | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely
+   | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely
+   | SYSCALL (g__14) => execute_SYSCALL g__14
+   | BREAK (g__15) => execute_BREAK g__15
+   | WAIT (g__16) => execute_WAIT g__16
+   | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp
+   | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp
+   | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset
+   | Store (width,conditional,base,rt,offset) => execute_Store width conditional base rt offset
+   | LWL (base,rt,offset) => execute_LWL base rt offset
+   | LWR (base,rt,offset) => execute_LWR base rt offset
+   | SWL (base,rt,offset) => execute_SWL base rt offset
+   | SWR (base,rt,offset) => execute_SWR base rt offset
+   | LDL (base,rt,offset) => execute_LDL base rt offset
+   | LDR (base,rt,offset) => execute_LDR base rt offset
+   | SDL (base,rt,offset) => execute_SDL base rt offset
+   | SDR (base,rt,offset) => execute_SDR base rt offset
+   | CACHE (base,op,imm) => execute_CACHE base op imm
+   | SYNC (g__17) => execute_SYNC g__17
+   | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double
+   | HCF (g__18) => sail2_state_monad$returnS ((execute_HCF g__18))
+   | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double
+   | TLBWI (g__19) => execute_TLBWI g__19
+   | TLBWR (g__20) => execute_TLBWR g__20
+   | TLBR (g__21) => execute_TLBR g__21
+   | TLBP (g__22) => execute_TLBP g__22
+   | RDHWR (rt,rd) => execute_RDHWR rt rd
+   | ERET (g__23) => execute_ERET g__23
+   | RI (g__24) => execute_RI g__24
+   )))`;
+
+
+(*val supported_instructions : ast -> maybe ast*)
+
+val _ = Define `
+ ((supported_instructions:ast ->(ast)option) instr=  (SOME instr))`;
+
+
+(*val initialize_registers : unit -> M unit*)
+
+val _ = Define `
+ ((initialize_registers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M) (\ (w__0 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS PC_ref w__0)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__1 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPC_ref w__1)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__2 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBProbe_ref w__2)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBIndex_ref w__3)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBRandom_ref w__4)
+   (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntryLo0_ref w__5)
+   (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntryLo1_ref w__6)
+   (undefined_ContextReg () )) (\ (w__7 : ContextReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBContext_ref w__7)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii)  : ( 16 words$word) M)) (\ (w__8 : 16 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBPageMask_ref w__8)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii)  : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBWired_ref w__9)
+   (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntryHi_ref w__10)
+   (undefined_XContextReg () )) (\ (w__11 : XContextReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBXContext_ref w__11)
+   (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry00_ref w__12)
+   (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry01_ref w__13)
+   (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry02_ref w__14)
+   (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry03_ref w__15)
+   (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry04_ref w__16)
+   (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry05_ref w__17)
+   (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry06_ref w__18)
+   (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry07_ref w__19)
+   (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry08_ref w__20)
+   (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry09_ref w__21)
+   (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry10_ref w__22)
+   (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry11_ref w__23)
+   (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry12_ref w__24)
+   (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry13_ref w__25)
+   (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry14_ref w__26)
+   (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry15_ref w__27)
+   (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry16_ref w__28)
+   (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry17_ref w__29)
+   (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry18_ref w__30)
+   (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry19_ref w__31)
+   (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry20_ref w__32)
+   (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry21_ref w__33)
+   (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry22_ref w__34)
+   (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry23_ref w__35)
+   (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry24_ref w__36)
+   (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry25_ref w__37)
+   (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry26_ref w__38)
+   (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry27_ref w__39)
+   (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry28_ref w__40)
+   (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry29_ref w__41)
+   (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry30_ref w__42)
+   (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry31_ref w__43)
+   (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry32_ref w__44)
+   (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry33_ref w__45)
+   (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry34_ref w__46)
+   (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry35_ref w__47)
+   (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry36_ref w__48)
+   (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry37_ref w__49)
+   (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry38_ref w__50)
+   (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry39_ref w__51)
+   (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry40_ref w__52)
+   (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry41_ref w__53)
+   (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry42_ref w__54)
+   (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry43_ref w__55)
+   (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry44_ref w__56)
+   (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry45_ref w__57)
+   (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry46_ref w__58)
+   (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry47_ref w__59)
+   (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry48_ref w__60)
+   (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry49_ref w__61)
+   (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry50_ref w__62)
+   (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry51_ref w__63)
+   (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry52_ref w__64)
+   (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry53_ref w__65)
+   (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry54_ref w__66)
+   (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry55_ref w__67)
+   (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry56_ref w__68)
+   (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry57_ref w__69)
+   (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry58_ref w__70)
+   (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry59_ref w__71)
+   (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry60_ref w__72)
+   (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry61_ref w__73)
+   (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry62_ref w__74)
+   (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS TLBEntry63_ref w__75)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__76 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Compare_ref w__76)
+   (undefined_CauseReg () )) (\ (w__77 : CauseReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Cause_ref w__77)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__78 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0EPC_ref w__78)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__79 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0ErrorEPC_ref w__79)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__80 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0LLBit_ref w__80)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__81 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0LLAddr_ref w__81)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__82 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0BadVAddr_ref w__82)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__83 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Count_ref w__83)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii)  : ( 32 words$word) M)) (\ (w__84 : 32 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0HWREna_ref w__84)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__85 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0UserLocal_ref w__85)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii)  : ( 3 words$word) M)) (\ (w__86 : 3 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0ConfigK0_ref w__86)
+   (undefined_StatusReg () )) (\ (w__87 : StatusReg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS CP0Status_ref w__87)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__88 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS branchPending_ref w__88)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__89 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS inBranchDelay_ref w__89)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__90 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS delayedPC_ref w__90)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__91 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS HI_ref w__91)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__92 : 64 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS LO_ref w__92)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii)  : ( 64 words$word) M)) (\ (w__93 :  64 words$word) .  sail2_state_monad$bindS
+   (undefined_vector (( 32 : int):ii) w__93  : ( ( 64 words$word)list) M) (\ (w__94 : ( 64 bits) list) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS GPR_ref w__94)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M)) (\ (w__95 : 8 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_WDATA_ref w__95)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__96 : 1 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_WRITTEN_ref w__96)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii)  : ( 8 words$word) M)) (\ (w__97 : 8 bits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS UART_RDATA_ref w__97)
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii)  : ( 1 words$word) M)) (\ (w__98 : 1 bits) . 
+   sail2_state_monad$write_regS UART_RVALID_ref w__98)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
+
+
+val _ = Define `
+((initial_regstate:regstate)=
+   (<| UART_RVALID := ((vec_of_bits [B0]  :  1 words$word)); 
+     UART_RDATA := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)); 
+     UART_WRITTEN := ((vec_of_bits [B0]  :  1 words$word)); 
+     UART_WDATA := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)); 
+     GPR :=
+       ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word);
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word)]); 
+     LO :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     HI :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     delayedPC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     inBranchDelay := ((vec_of_bits [B0]  :  1 words$word)); 
+     branchPending := ((vec_of_bits [B0]  :  1 words$word)); 
+     CP0Status :=
+       (<| StatusReg_StatusReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0]
+               :  32 words$word)) |>); 
+     CP0ConfigK0 := ((vec_of_bits [B0;B0;B0]  :  3 words$word)); 
+     CP0UserLocal :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     CP0HWREna :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     CP0Count :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     CP0BadVAddr :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     CP0LLAddr :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     CP0LLBit := ((vec_of_bits [B0]  :  1 words$word)); 
+     CP0ErrorEPC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     CP0EPC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     CP0Cause :=
+       (<| CauseReg_CauseReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0]
+               :  32 words$word)) |>); 
+     CP0Compare :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0]
+         :  32 words$word)); 
+     TLBEntry63 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry62 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry61 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry60 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry59 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry58 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry57 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry56 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry55 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry54 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry53 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry52 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry51 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry50 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry49 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry48 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry47 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry46 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry45 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry44 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry43 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry42 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry41 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry40 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry39 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry38 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry37 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry36 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry35 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry34 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry33 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry32 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry31 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry30 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry29 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry28 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry27 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry26 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry25 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry24 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry23 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry22 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry21 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry20 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry19 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry18 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry17 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry16 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry15 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry14 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry13 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry12 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry11 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry10 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry09 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry08 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry07 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry06 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry05 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry04 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry03 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry02 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry01 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntry00 :=
+       (<| TLBEntry_TLBEntry_chunk_1 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0]
+               :  53 words$word)); 
+           TLBEntry_TLBEntry_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBXContext :=
+       (<| XContextReg_XContextReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntryHi :=
+       (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBWired := ((vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)); 
+     TLBPageMask := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)); 
+     TLBContext :=
+       (<| ContextReg_ContextReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntryLo1 :=
+       (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBEntryLo0 :=
+       (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
+     TLBRandom := ((vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)); 
+     TLBIndex := ((vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)); 
+     TLBProbe := ((vec_of_bits [B0]  :  1 words$word)); 
+     nextPC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     PC :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)) |>))`;
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/mips/mips_extrasScript.sml b/snapshots/hol4/sail/mips/mips_extrasScript.sml
new file mode 100644
index 00000000..f89e7b2f
--- /dev/null
+++ b/snapshots/hol4/sail/mips/mips_extrasScript.sml
@@ -0,0 +1,242 @@
+(*Generated by Lem from mips_extras.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_promptTheory sail2_operatorsTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "mips_extras"
+
+(*open import Pervasives*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+(*val MEMr             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*)
+(*val MEMr_reserve     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*)
+(*val MEMr_tag         : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*)
+(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*)
+
+val _ = Define `
+ ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=              (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=      (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_reserve addr size1))`;
+
+
+(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*)
+val _ = Define `
+ ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a addr=  (sail2_state_monad$bindS
+  (sail2_state_monad$read_tagS 
+  dict_Sail2_values_Bitvector_a addr) (\ t . 
+  sail2_state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`;
+
+
+(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*)
+val _ = Define `
+ ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr t=  (sail2_state_monad$bindS (sail2_state_monad$write_tagS 
+  dict_Sail2_values_Bitvector_a addr (bitU_of_bool t)) 
+  (\b .  (case (b ) of ( _ ) => sail2_state_monad$returnS ()  ))))`;
+
+
+val _ = Define `
+ ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=  (sail2_state_monad$bindS
+  (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v .  sail2_state_monad$bindS
+  (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . 
+  sail2_state_monad$returnS (t, v)))))`;
+
+
+val _ = Define `
+ ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1=  (sail2_state_monad$bindS
+  (sail2_state_monad$read_memS 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v .  sail2_state_monad$bindS
+  (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . 
+  sail2_state_monad$returnS (t, v)))))`;
+
+
+
+(*val MEMea                 : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*)
+(*val MEMea_conditional     : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*)
+(*val MEMea_tag             : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*)
+(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*)
+
+val _ = Define `
+ ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=                  (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=      (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
+
+
+val _ = Define `
+ ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=              (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1=  (sail2_state_monad$write_mem_eaS 
+  dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
+
+
+
+(*val MEMval                 : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e*)
+(*val MEMval_conditional     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e*)
+(*val MEMval_tag             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e*)
+(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*)
+
+val _ = Define `
+ ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v=                       (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\b .  (case (b ) of ( _ ) => sail2_state_monad$returnS ()  ))))`;
+
+val _ = Define `
+ ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v=           (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\ b .  sail2_state_monad$returnS (if b then T else F))))`;
+
+val _ = Define `
+ ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v=              (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\b .  (case (b ) of
+            ( _ ) => sail2_state_monad$bindS
+                       (write_tag_bool dict_Sail2_values_Bitvector_a addr t)
+                       (\u .  (case (u ) of
+                                  ( _ ) => sail2_state_monad$returnS () 
+                              ))
+        ))))`;
+
+val _ = Define `
+ ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v=  (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS 
+  dict_Sail2_values_Bitvector_b v) (\ b .  sail2_state_monad$bindS (write_tag_bool 
+  dict_Sail2_values_Bitvector_a addr t) (\u .  (case (u ) of
+            ( _ ) => sail2_state_monad$returnS (if b then T else F)
+        )))))`;
+
+
+(*val MEM_sync  : forall 'regval 'e. unit -> monad 'regval unit 'e*)
+
+val _ = Define `
+ ((MEM_sync:unit -> 'regval sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'regval sail2_state_monad$sequential_state)set) () =  (barrier Barrier_MIPS_SYNC))`;
+
+
+(* Some wrappers copied from aarch64_extras *)
+(* TODO: Harmonise into a common library *)
+
+val _ = Define `
+ ((get_slice_int_bl:int -> int -> int ->(bool)list) len n lo=
+   (
+  (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in
+  let bs = (bools_of_int (hi +( 1 : int)) n) in
+  subrange_list F bs hi lo))`;
+
+
+(*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
+val _ = Define `
+ ((get_slice_int:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo=  (
+  dict_Sail2_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`;
+
+
+val _ = Define `
+ ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd sail2_state_monad$sequential_state ->(((unit),'c)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 _ addr data=  (sail2_state_monad$seqS
+  (MEMea dict_Sail2_values_Bitvector_b addr size1)
+  (MEMval dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a addr size1 data)))`;
+
+
+val _ = Define `
+ ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd sail2_state_monad$sequential_state ->(('c,'b)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c _ size1 _ addr=  (MEMr 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c addr size1))`;
+
+
+val _ = Define `
+ ((string_of_int:'a Show_class -> 'a -> string)dict_Show_Show_a= 
+  (dict_Show_Show_a.show_method))`;
+
+
+val _ = Define `
+ ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n=
+   (let r = (OPTION_BIND (
+  dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail2_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail2_values_Bitvector_d v n))) in
+  sail2_state_monad$maybe_failS "shift_bits_left" r))`;
+
+val _ = Define `
+ ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n=
+   (let r = (OPTION_BIND (
+  dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail2_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail2_values_Bitvector_d v n))) in
+  sail2_state_monad$maybe_failS "shift_bits_right" r))`;
+
+val _ = Define `
+ ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n=
+   (let r = (OPTION_BIND (
+  dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail2_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail2_values_Bitvector_d v n))) in
+  sail2_state_monad$maybe_failS "shift_bits_right_arith" r))`;
+
+
+(* Use constants for undefined values for now *)
+val _ = Define `
+ ((undefined_string:unit -> 'a sail2_state_monad$sequential_state ->(((string),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS ""))`;
+
+val _ = Define `
+ ((undefined_unit:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((undefined_int:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (( 0 : int):ii)))`;
+
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+val _ = Define `
+ ((undefined_vector:int -> 'a -> 'rv sail2_state_monad$sequential_state ->((('a list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len u=  (sail2_state_monad$returnS (repeat [u] len)))`;
+
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+val _ = Define `
+ ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a len=  (sail2_state_monad$returnS (
+  dict_Sail2_values_Bitvector_a.of_bools_method (repeat [F] len))))`;
+
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+val _ = Define `
+ ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a= 
+  (undefined_bitvector dict_Sail2_values_Bitvector_a))`;
+
+val _ = Define `
+ ((undefined_bit:unit -> 'a sail2_state_monad$sequential_state ->(((bitU),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS B0))`;
+
+val _ = Define `
+ ((undefined_real:unit -> 'a sail2_state_monad$sequential_state ->(((real),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`;
+
+val _ = Define `
+ ((undefined_range:'a -> 'd -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i j=  (sail2_state_monad$returnS i))`;
+
+val _ = Define `
+ ((undefined_atom:'a -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i=  (sail2_state_monad$returnS i))`;
+
+val _ = Define `
+ ((undefined_nat:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS (( 0 : int):ii)))`;
+
+
+val _ = Define `
+ ((skip:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$returnS () ))`;
+
+
+(*val elf_entry : unit -> integer*)
+val _ = Define `
+ ((elf_entry:unit -> int) () = (( 0 : int)))`;
+
+
+val _ = Define `
+ ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bv 
+  dict_Sail2_values_Bitvector_a bs))))`;
+
+
+(*val get_time_ns : unit -> integer*)
+val _ = Define `
+ ((get_time_ns:unit -> int) () = (( 0 : int)))`;
+
+
+(*val cycle_count : unit -> unit*)
+val _ = Define `
+ ((cycle_count:unit -> unit) _=  () )`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/mips/mips_typesScript.sml b/snapshots/hol4/sail/mips/mips_typesScript.sml
new file mode 100644
index 00000000..fce6af4b
--- /dev/null
+++ b/snapshots/hol4/sail/mips/mips_typesScript.sml
@@ -0,0 +1,1692 @@
+(*Generated by Lem from mips_types.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "mips_types"
+
+(*Generated by Sail from mips.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+val _ = type_abbrev((*  'n *) "bits" , ``:  'n words$word``);
+
+
+
+val _ = Hol_datatype `
+ exception  =
+    ISAException of (unit)
+  | Error_not_implemented of (string)
+  | Error_misaligned_access of (unit)
+  | Error_EBREAK of (unit)
+  | Error_internal_error of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ CauseReg  = <| CauseReg_CauseReg_chunk_0 :  32 words$word  |>`;
+
+
+
+val _ = Hol_datatype `
+ StatusReg  = <| StatusReg_StatusReg_chunk_0 :  32 words$word  |>`;
+
+
+
+val _ = Hol_datatype `
+ TLBEntryLoReg  = <| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :  64 words$word  |>`;
+
+
+
+val _ = Hol_datatype `
+ TLBEntryHiReg  = <| TLBEntryHiReg_TLBEntryHiReg_chunk_0 :  64 words$word  |>`;
+
+
+
+val _ = Hol_datatype `
+ ContextReg  = <| ContextReg_ContextReg_chunk_0 :  64 words$word  |>`;
+
+
+
+val _ = Hol_datatype `
+ XContextReg  = <| XContextReg_XContextReg_chunk_0 :  64 words$word  |>`;
+
+
+
+val _ = type_abbrev( "TLBIndexT"  , ``: 6 bits``);
+
+val _ = Hol_datatype `
+ TLBEntry  =
+  <| TLBEntry_TLBEntry_chunk_1 :  53 words$word; TLBEntry_TLBEntry_chunk_0 :  64 words$word  |>`;
+
+
+
+val _ = Hol_datatype `
+ Exception =
+  Interrupt
+  | TLBMod
+  | TLBL
+  | TLBS
+  | AdEL
+  | AdES
+  | Sys
+  | Bp
+  | ResI
+  | CpU
+  | Ov
+  | Tr
+  | C2E
+  | C2Trap
+  | XTLBRefillL
+  | XTLBRefillS
+  | XTLBInvL
+  | XTLBInvS
+  | MCheck`;
+
+
+
+
+val _ = Hol_datatype `
+ MemAccessType = Instruction | LoadData | StoreData`;
+
+
+
+
+val _ = Hol_datatype `
+ AccessLevel = User | Supervisor | Kernel`;
+
+
+
+
+val _ = type_abbrev( "regno"  , ``: 5 bits``);
+
+val _ = type_abbrev( "imm16"  , ``: 16 bits``);
+
+val _ = type_abbrev( "regregreg"  , ``: (regno # regno # regno)``);
+
+val _ = type_abbrev( "regregimm16"  , ``: (regno # regno # imm16)``);
+
+val _ = Hol_datatype `
+ decode_failure =
+  No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error`;
+
+
+
+
+val _ = Hol_datatype `
+ Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU`;
+
+
+
+
+val _ = Hol_datatype `
+ WordType = B | H | W0 | D`;
+
+
+
+
+val _ = Hol_datatype `
+ WordTypeUnaligned = WL | WR | DL | DR`;
+
+
+
+
+val _ = Hol_datatype `
+ ast  =
+    DADDIU of ((regno # regno # imm16))
+  | DADDU of ((regno # regno # regno))
+  | DADDI of ((regno # regno # 16 bits))
+  | DADD of ((regno # regno # regno))
+  | ADD of ((regno # regno # regno))
+  | ADDI of ((regno # regno # 16 bits))
+  | ADDU of ((regno # regno # regno))
+  | ADDIU of ((regno # regno # 16 bits))
+  | DSUBU of ((regno # regno # regno))
+  | DSUB of ((regno # regno # regno))
+  | SUB0 of ((regno # regno # regno))
+  | SUBU of ((regno # regno # regno))
+  | AND of ((regno # regno # regno))
+  | ANDI of ((regno # regno # 16 bits))
+  | OR of ((regno # regno # regno))
+  | ORI of ((regno # regno # 16 bits))
+  | NOR of ((regno # regno # regno))
+  | XOR of ((regno # regno # regno))
+  | XORI of ((regno # regno # 16 bits))
+  | LUI of ((regno # imm16))
+  | DSLL of ((regno # regno # regno))
+  | DSLL32 of ((regno # regno # regno))
+  | DSLLV of ((regno # regno # regno))
+  | DSRA of ((regno # regno # regno))
+  | DSRA32 of ((regno # regno # regno))
+  | DSRAV of ((regno # regno # regno))
+  | DSRL of ((regno # regno # regno))
+  | DSRL32 of ((regno # regno # regno))
+  | DSRLV of ((regno # regno # regno))
+  | SLL of ((regno # regno # regno))
+  | SLLV of ((regno # regno # regno))
+  | SRA of ((regno # regno # regno))
+  | SRAV of ((regno # regno # regno))
+  | SRL of ((regno # regno # regno))
+  | SRLV of ((regno # regno # regno))
+  | SLT of ((regno # regno # regno))
+  | SLTI of ((regno # regno # 16 bits))
+  | SLTU of ((regno # regno # regno))
+  | SLTIU of ((regno # regno # 16 bits))
+  | MOVN of ((regno # regno # regno))
+  | MOVZ of ((regno # regno # regno))
+  | MFHI of (regno)
+  | MFLO of (regno)
+  | MTHI of (regno)
+  | MTLO of (regno)
+  | MUL of ((regno # regno # regno))
+  | MULT of ((regno # regno))
+  | MULTU of ((regno # regno))
+  | DMULT of ((regno # regno))
+  | DMULTU of ((regno # regno))
+  | MADD of ((regno # regno))
+  | MADDU of ((regno # regno))
+  | MSUB of ((regno # regno))
+  | MSUBU of ((regno # regno))
+  | DIV0 of ((regno # regno))
+  | DIVU of ((regno # regno))
+  | DDIV of ((regno # regno))
+  | DDIVU of ((regno # regno))
+  | J of ( 26 bits)
+  | JAL of ( 26 bits)
+  | JR of (regno)
+  | JALR of ((regno # regno))
+  | BEQ of ((regno # regno # imm16 # bool # bool))
+  | BCMPZ of ((regno # imm16 # Comparison # bool # bool))
+  | SYSCALL of (unit)
+  | BREAK of (unit)
+  | WAIT of (unit)
+  | TRAPREG of ((regno # regno # Comparison))
+  | TRAPIMM of ((regno # imm16 # Comparison))
+  | Load of ((WordType # bool # bool # regno # regno # imm16))
+  | Store of ((WordType # bool # regno # regno # imm16))
+  | LWL of ((regno # regno # 16 bits))
+  | LWR of ((regno # regno # 16 bits))
+  | SWL of ((regno # regno # 16 bits))
+  | SWR of ((regno # regno # 16 bits))
+  | LDL of ((regno # regno # 16 bits))
+  | LDR of ((regno # regno # 16 bits))
+  | SDL of ((regno # regno # 16 bits))
+  | SDR of ((regno # regno # 16 bits))
+  | CACHE of ((regno # regno # 16 bits))
+  | SYNC of (unit)
+  | MFC0 of ((regno # regno # 3 bits # bool))
+  | HCF of (unit)
+  | MTC0 of ((regno # regno # 3 bits # bool))
+  | TLBWI of (unit)
+  | TLBWR of (unit)
+  | TLBR of (unit)
+  | TLBP of (unit)
+  | RDHWR of ((regno # regno))
+  | ERET of (unit)
+  | RI of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ register_value  =
+    Regval_vector of ((ii # bool # register_value list))
+  | Regval_list of ( register_value list)
+  | Regval_option of ( register_value option)
+  | Regval_CauseReg of (CauseReg)
+  | Regval_ContextReg of (ContextReg)
+  | Regval_StatusReg of (StatusReg)
+  | Regval_TLBEntry of (TLBEntry)
+  | Regval_TLBEntryHiReg of (TLBEntryHiReg)
+  | Regval_TLBEntryLoReg of (TLBEntryLoReg)
+  | Regval_XContextReg of (XContextReg)
+  | Regval_vector_16_dec_bit of ( 16 words$word)
+  | Regval_vector_1_dec_bit of ( 1 words$word)
+  | Regval_vector_32_dec_bit of ( 32 words$word)
+  | Regval_vector_3_dec_bit of ( 3 words$word)
+  | Regval_vector_64_dec_bit of ( 64 words$word)
+  | Regval_vector_6_dec_bit of ( 6 words$word)
+  | Regval_vector_8_dec_bit of ( 8 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ regstate  =
+  <| UART_RVALID :  1 words$word;
+     UART_RDATA :  8 words$word;
+     UART_WRITTEN :  1 words$word;
+     UART_WDATA :  8 words$word;
+     GPR : ( 64 words$word) list;
+     LO :  64 words$word;
+     HI :  64 words$word;
+     delayedPC :  64 words$word;
+     inBranchDelay :  1 words$word;
+     branchPending :  1 words$word;
+     CP0Status : StatusReg;
+     CP0ConfigK0 :  3 words$word;
+     CP0UserLocal :  64 words$word;
+     CP0HWREna :  32 words$word;
+     CP0Count :  32 words$word;
+     CP0BadVAddr :  64 words$word;
+     CP0LLAddr :  64 words$word;
+     CP0LLBit :  1 words$word;
+     CP0ErrorEPC :  64 words$word;
+     CP0EPC :  64 words$word;
+     CP0Cause : CauseReg;
+     CP0Compare :  32 words$word;
+     TLBEntry63 : TLBEntry;
+     TLBEntry62 : TLBEntry;
+     TLBEntry61 : TLBEntry;
+     TLBEntry60 : TLBEntry;
+     TLBEntry59 : TLBEntry;
+     TLBEntry58 : TLBEntry;
+     TLBEntry57 : TLBEntry;
+     TLBEntry56 : TLBEntry;
+     TLBEntry55 : TLBEntry;
+     TLBEntry54 : TLBEntry;
+     TLBEntry53 : TLBEntry;
+     TLBEntry52 : TLBEntry;
+     TLBEntry51 : TLBEntry;
+     TLBEntry50 : TLBEntry;
+     TLBEntry49 : TLBEntry;
+     TLBEntry48 : TLBEntry;
+     TLBEntry47 : TLBEntry;
+     TLBEntry46 : TLBEntry;
+     TLBEntry45 : TLBEntry;
+     TLBEntry44 : TLBEntry;
+     TLBEntry43 : TLBEntry;
+     TLBEntry42 : TLBEntry;
+     TLBEntry41 : TLBEntry;
+     TLBEntry40 : TLBEntry;
+     TLBEntry39 : TLBEntry;
+     TLBEntry38 : TLBEntry;
+     TLBEntry37 : TLBEntry;
+     TLBEntry36 : TLBEntry;
+     TLBEntry35 : TLBEntry;
+     TLBEntry34 : TLBEntry;
+     TLBEntry33 : TLBEntry;
+     TLBEntry32 : TLBEntry;
+     TLBEntry31 : TLBEntry;
+     TLBEntry30 : TLBEntry;
+     TLBEntry29 : TLBEntry;
+     TLBEntry28 : TLBEntry;
+     TLBEntry27 : TLBEntry;
+     TLBEntry26 : TLBEntry;
+     TLBEntry25 : TLBEntry;
+     TLBEntry24 : TLBEntry;
+     TLBEntry23 : TLBEntry;
+     TLBEntry22 : TLBEntry;
+     TLBEntry21 : TLBEntry;
+     TLBEntry20 : TLBEntry;
+     TLBEntry19 : TLBEntry;
+     TLBEntry18 : TLBEntry;
+     TLBEntry17 : TLBEntry;
+     TLBEntry16 : TLBEntry;
+     TLBEntry15 : TLBEntry;
+     TLBEntry14 : TLBEntry;
+     TLBEntry13 : TLBEntry;
+     TLBEntry12 : TLBEntry;
+     TLBEntry11 : TLBEntry;
+     TLBEntry10 : TLBEntry;
+     TLBEntry09 : TLBEntry;
+     TLBEntry08 : TLBEntry;
+     TLBEntry07 : TLBEntry;
+     TLBEntry06 : TLBEntry;
+     TLBEntry05 : TLBEntry;
+     TLBEntry04 : TLBEntry;
+     TLBEntry03 : TLBEntry;
+     TLBEntry02 : TLBEntry;
+     TLBEntry01 : TLBEntry;
+     TLBEntry00 : TLBEntry;
+     TLBXContext : XContextReg;
+     TLBEntryHi : TLBEntryHiReg;
+     TLBWired :  6 words$word;
+     TLBPageMask :  16 words$word;
+     TLBContext : ContextReg;
+     TLBEntryLo1 : TLBEntryLoReg;
+     TLBEntryLo0 : TLBEntryLoReg;
+     TLBRandom :  6 words$word;
+     TLBIndex :  6 words$word;
+     TLBProbe :  1 words$word;
+     nextPC :  64 words$word;
+     PC :  64 words$word  |>`;
+
+
+
+
+
+(*val CauseReg_of_regval : register_value -> maybe CauseReg*)
+
+val _ = Define `
+ ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var=
+    ((case merge_var of   Regval_CauseReg (v) => SOME v | g__13 => NONE )))`;
+
+
+(*val regval_of_CauseReg : CauseReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_CauseReg:CauseReg -> register_value) v=  (Regval_CauseReg v))`;
+
+
+(*val ContextReg_of_regval : register_value -> maybe ContextReg*)
+
+val _ = Define `
+ ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var=
+    ((case merge_var of   Regval_ContextReg (v) => SOME v | g__12 => NONE )))`;
+
+
+(*val regval_of_ContextReg : ContextReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_ContextReg:ContextReg -> register_value) v=  (Regval_ContextReg v))`;
+
+
+(*val StatusReg_of_regval : register_value -> maybe StatusReg*)
+
+val _ = Define `
+ ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var=
+    ((case merge_var of   Regval_StatusReg (v) => SOME v | g__11 => NONE )))`;
+
+
+(*val regval_of_StatusReg : StatusReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_StatusReg:StatusReg -> register_value) v=  (Regval_StatusReg v))`;
+
+
+(*val TLBEntry_of_regval : register_value -> maybe TLBEntry*)
+
+val _ = Define `
+ ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var=
+    ((case merge_var of   Regval_TLBEntry (v) => SOME v | g__10 => NONE )))`;
+
+
+(*val regval_of_TLBEntry : TLBEntry -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLBEntry:TLBEntry -> register_value) v=  (Regval_TLBEntry v))`;
+
+
+(*val TLBEntryHiReg_of_regval : register_value -> maybe TLBEntryHiReg*)
+
+val _ = Define `
+ ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var=
+    ((case merge_var of   Regval_TLBEntryHiReg (v) => SOME v | g__9 => NONE )))`;
+
+
+(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLBEntryHiReg:TLBEntryHiReg -> register_value) v=  (Regval_TLBEntryHiReg v))`;
+
+
+(*val TLBEntryLoReg_of_regval : register_value -> maybe TLBEntryLoReg*)
+
+val _ = Define `
+ ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var=
+    ((case merge_var of   Regval_TLBEntryLoReg (v) => SOME v | g__8 => NONE )))`;
+
+
+(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLBEntryLoReg:TLBEntryLoReg -> register_value) v=  (Regval_TLBEntryLoReg v))`;
+
+
+(*val XContextReg_of_regval : register_value -> maybe XContextReg*)
+
+val _ = Define `
+ ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var=
+    ((case merge_var of   Regval_XContextReg (v) => SOME v | g__7 => NONE )))`;
+
+
+(*val regval_of_XContextReg : XContextReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_XContextReg:XContextReg -> register_value) v=  (Regval_XContextReg v))`;
+
+
+(*val vector_16_dec_bit_of_regval : register_value -> maybe (mword ty16)*)
+
+val _ = Define `
+ ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_16_dec_bit (v) => SOME v | g__6 => NONE )))`;
+
+
+(*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_16_dec_bit:(16)words$word -> register_value) v=  (Regval_vector_16_dec_bit v))`;
+
+
+(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*)
+
+val _ = Define `
+ ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_1_dec_bit (v) => SOME v | g__5 => NONE )))`;
+
+
+(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v=  (Regval_vector_1_dec_bit v))`;
+
+
+(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_32_dec_bit (v) => SOME v | g__4 => NONE )))`;
+
+
+(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v=  (Regval_vector_32_dec_bit v))`;
+
+
+(*val vector_3_dec_bit_of_regval : register_value -> maybe (mword ty3)*)
+
+val _ = Define `
+ ((vector_3_dec_bit_of_regval:register_value ->((3)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_3_dec_bit (v) => SOME v | g__3 => NONE )))`;
+
+
+(*val regval_of_vector_3_dec_bit : mword ty3 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_3_dec_bit:(3)words$word -> register_value) v=  (Regval_vector_3_dec_bit v))`;
+
+
+(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
+
+val _ = Define `
+ ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__2 => NONE )))`;
+
+
+(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v=  (Regval_vector_64_dec_bit v))`;
+
+
+(*val vector_6_dec_bit_of_regval : register_value -> maybe (mword ty6)*)
+
+val _ = Define `
+ ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_6_dec_bit (v) => SOME v | g__1 => NONE )))`;
+
+
+(*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_6_dec_bit:(6)words$word -> register_value) v=  (Regval_vector_6_dec_bit v))`;
+
+
+(*val vector_8_dec_bit_of_regval : register_value -> maybe (mword ty8)*)
+
+val _ = Define `
+ ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var=
+    ((case merge_var of   Regval_vector_8_dec_bit (v) => SOME v | g__0 => NONE )))`;
+
+
+(*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_8_dec_bit:(8)words$word -> register_value) v=  (Regval_vector_8_dec_bit v))`;
+
+
+
+
+(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
+  (\x .  (case x of
+               Regval_vector (_, _, v) => just_list (MAP of_regval1 v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`;
+
+
+(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
+  (\x .  (case x of
+               Regval_list v => just_list (MAP of_regval1 v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs=  (Regval_list (MAP regval_of1 xs)))`;
+
+
+(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
+val _ = Define `
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= 
+  (\x .  (case x of
+               Regval_option v => SOME (OPTION_BIND v of_regval1)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
+val _ = Define `
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v=  (Regval_option (OPTION_MAP regval_of1 v)))`;
+
+
+
+val _ = Define `
+ ((UART_RVALID_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "UART_RVALID";
+  read_from := (\ s .  s.UART_RVALID);
+  write_to := (\ v s .  (( s with<| UART_RVALID := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_RDATA_ref:((regstate),(register_value),((8)words$word))register_ref)=  (<|
+  name := "UART_RDATA";
+  read_from := (\ s .  s.UART_RDATA);
+  write_to := (\ v s .  (( s with<| UART_RDATA := v |>)));
+  of_regval := (\ v .  vector_8_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_8_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_WRITTEN_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "UART_WRITTEN";
+  read_from := (\ s .  s.UART_WRITTEN);
+  write_to := (\ v s .  (( s with<| UART_WRITTEN := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_WDATA_ref:((regstate),(register_value),((8)words$word))register_ref)=  (<|
+  name := "UART_WDATA";
+  read_from := (\ s .  s.UART_WDATA);
+  write_to := (\ v s .  (( s with<| UART_WDATA := v |>)));
+  of_regval := (\ v .  vector_8_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_8_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((GPR_ref:((regstate),(register_value),(((64)words$word)list))register_ref)=  (<|
+  name := "GPR";
+  read_from := (\ s .  s.GPR);
+  write_to := (\ v s .  (( s with<| GPR := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((LO_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "LO";
+  read_from := (\ s .  s.LO);
+  write_to := (\ v s .  (( s with<| LO := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HI_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "HI";
+  read_from := (\ s .  s.HI);
+  write_to := (\ v s .  (( s with<| HI := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((delayedPC_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "delayedPC";
+  read_from := (\ s .  s.delayedPC);
+  write_to := (\ v s .  (( s with<| delayedPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((inBranchDelay_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "inBranchDelay";
+  read_from := (\ s .  s.inBranchDelay);
+  write_to := (\ v s .  (( s with<| inBranchDelay := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((branchPending_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "branchPending";
+  read_from := (\ s .  s.branchPending);
+  write_to := (\ v s .  (( s with<| branchPending := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0Status_ref:((regstate),(register_value),(StatusReg))register_ref)=  (<|
+  name := "CP0Status";
+  read_from := (\ s .  s.CP0Status);
+  write_to := (\ v s .  (( s with<| CP0Status := v |>)));
+  of_regval := (\ v .  StatusReg_of_regval v);
+  regval_of := (\ v .  regval_of_StatusReg v) |>))`;
+
+
+val _ = Define `
+ ((CP0ConfigK0_ref:((regstate),(register_value),((3)words$word))register_ref)=  (<|
+  name := "CP0ConfigK0";
+  read_from := (\ s .  s.CP0ConfigK0);
+  write_to := (\ v s .  (( s with<| CP0ConfigK0 := v |>)));
+  of_regval := (\ v .  vector_3_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_3_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "CP0UserLocal";
+  read_from := (\ s .  s.CP0UserLocal);
+  write_to := (\ v s .  (( s with<| CP0UserLocal := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0HWREna_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CP0HWREna";
+  read_from := (\ s .  s.CP0HWREna);
+  write_to := (\ v s .  (( s with<| CP0HWREna := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0Count_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CP0Count";
+  read_from := (\ s .  s.CP0Count);
+  write_to := (\ v s .  (( s with<| CP0Count := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0BadVAddr_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "CP0BadVAddr";
+  read_from := (\ s .  s.CP0BadVAddr);
+  write_to := (\ v s .  (( s with<| CP0BadVAddr := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0LLAddr_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "CP0LLAddr";
+  read_from := (\ s .  s.CP0LLAddr);
+  write_to := (\ v s .  (( s with<| CP0LLAddr := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0LLBit_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "CP0LLBit";
+  read_from := (\ s .  s.CP0LLBit);
+  write_to := (\ v s .  (( s with<| CP0LLBit := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0ErrorEPC_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "CP0ErrorEPC";
+  read_from := (\ s .  s.CP0ErrorEPC);
+  write_to := (\ v s .  (( s with<| CP0ErrorEPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0EPC_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "CP0EPC";
+  read_from := (\ s .  s.CP0EPC);
+  write_to := (\ v s .  (( s with<| CP0EPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0Cause_ref:((regstate),(register_value),(CauseReg))register_ref)=  (<|
+  name := "CP0Cause";
+  read_from := (\ s .  s.CP0Cause);
+  write_to := (\ v s .  (( s with<| CP0Cause := v |>)));
+  of_regval := (\ v .  CauseReg_of_regval v);
+  regval_of := (\ v .  regval_of_CauseReg v) |>))`;
+
+
+val _ = Define `
+ ((CP0Compare_ref:((regstate),(register_value),((32)words$word))register_ref)=  (<|
+  name := "CP0Compare";
+  read_from := (\ s .  s.CP0Compare);
+  write_to := (\ v s .  (( s with<| CP0Compare := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry63_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry63";
+  read_from := (\ s .  s.TLBEntry63);
+  write_to := (\ v s .  (( s with<| TLBEntry63 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry62_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry62";
+  read_from := (\ s .  s.TLBEntry62);
+  write_to := (\ v s .  (( s with<| TLBEntry62 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry61_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry61";
+  read_from := (\ s .  s.TLBEntry61);
+  write_to := (\ v s .  (( s with<| TLBEntry61 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry60_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry60";
+  read_from := (\ s .  s.TLBEntry60);
+  write_to := (\ v s .  (( s with<| TLBEntry60 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry59_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry59";
+  read_from := (\ s .  s.TLBEntry59);
+  write_to := (\ v s .  (( s with<| TLBEntry59 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry58_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry58";
+  read_from := (\ s .  s.TLBEntry58);
+  write_to := (\ v s .  (( s with<| TLBEntry58 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry57_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry57";
+  read_from := (\ s .  s.TLBEntry57);
+  write_to := (\ v s .  (( s with<| TLBEntry57 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry56_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry56";
+  read_from := (\ s .  s.TLBEntry56);
+  write_to := (\ v s .  (( s with<| TLBEntry56 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry55_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry55";
+  read_from := (\ s .  s.TLBEntry55);
+  write_to := (\ v s .  (( s with<| TLBEntry55 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry54_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry54";
+  read_from := (\ s .  s.TLBEntry54);
+  write_to := (\ v s .  (( s with<| TLBEntry54 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry53_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry53";
+  read_from := (\ s .  s.TLBEntry53);
+  write_to := (\ v s .  (( s with<| TLBEntry53 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry52_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry52";
+  read_from := (\ s .  s.TLBEntry52);
+  write_to := (\ v s .  (( s with<| TLBEntry52 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry51_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry51";
+  read_from := (\ s .  s.TLBEntry51);
+  write_to := (\ v s .  (( s with<| TLBEntry51 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry50_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry50";
+  read_from := (\ s .  s.TLBEntry50);
+  write_to := (\ v s .  (( s with<| TLBEntry50 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry49_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry49";
+  read_from := (\ s .  s.TLBEntry49);
+  write_to := (\ v s .  (( s with<| TLBEntry49 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry48_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry48";
+  read_from := (\ s .  s.TLBEntry48);
+  write_to := (\ v s .  (( s with<| TLBEntry48 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry47_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry47";
+  read_from := (\ s .  s.TLBEntry47);
+  write_to := (\ v s .  (( s with<| TLBEntry47 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry46_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry46";
+  read_from := (\ s .  s.TLBEntry46);
+  write_to := (\ v s .  (( s with<| TLBEntry46 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry45_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry45";
+  read_from := (\ s .  s.TLBEntry45);
+  write_to := (\ v s .  (( s with<| TLBEntry45 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry44_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry44";
+  read_from := (\ s .  s.TLBEntry44);
+  write_to := (\ v s .  (( s with<| TLBEntry44 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry43_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry43";
+  read_from := (\ s .  s.TLBEntry43);
+  write_to := (\ v s .  (( s with<| TLBEntry43 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry42_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry42";
+  read_from := (\ s .  s.TLBEntry42);
+  write_to := (\ v s .  (( s with<| TLBEntry42 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry41_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry41";
+  read_from := (\ s .  s.TLBEntry41);
+  write_to := (\ v s .  (( s with<| TLBEntry41 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry40_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry40";
+  read_from := (\ s .  s.TLBEntry40);
+  write_to := (\ v s .  (( s with<| TLBEntry40 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry39_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry39";
+  read_from := (\ s .  s.TLBEntry39);
+  write_to := (\ v s .  (( s with<| TLBEntry39 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry38_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry38";
+  read_from := (\ s .  s.TLBEntry38);
+  write_to := (\ v s .  (( s with<| TLBEntry38 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry37_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry37";
+  read_from := (\ s .  s.TLBEntry37);
+  write_to := (\ v s .  (( s with<| TLBEntry37 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry36_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry36";
+  read_from := (\ s .  s.TLBEntry36);
+  write_to := (\ v s .  (( s with<| TLBEntry36 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry35_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry35";
+  read_from := (\ s .  s.TLBEntry35);
+  write_to := (\ v s .  (( s with<| TLBEntry35 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry34_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry34";
+  read_from := (\ s .  s.TLBEntry34);
+  write_to := (\ v s .  (( s with<| TLBEntry34 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry33_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry33";
+  read_from := (\ s .  s.TLBEntry33);
+  write_to := (\ v s .  (( s with<| TLBEntry33 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry32_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry32";
+  read_from := (\ s .  s.TLBEntry32);
+  write_to := (\ v s .  (( s with<| TLBEntry32 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry31_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry31";
+  read_from := (\ s .  s.TLBEntry31);
+  write_to := (\ v s .  (( s with<| TLBEntry31 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry30_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry30";
+  read_from := (\ s .  s.TLBEntry30);
+  write_to := (\ v s .  (( s with<| TLBEntry30 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry29_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry29";
+  read_from := (\ s .  s.TLBEntry29);
+  write_to := (\ v s .  (( s with<| TLBEntry29 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry28_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry28";
+  read_from := (\ s .  s.TLBEntry28);
+  write_to := (\ v s .  (( s with<| TLBEntry28 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry27_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry27";
+  read_from := (\ s .  s.TLBEntry27);
+  write_to := (\ v s .  (( s with<| TLBEntry27 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry26_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry26";
+  read_from := (\ s .  s.TLBEntry26);
+  write_to := (\ v s .  (( s with<| TLBEntry26 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry25_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry25";
+  read_from := (\ s .  s.TLBEntry25);
+  write_to := (\ v s .  (( s with<| TLBEntry25 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry24_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry24";
+  read_from := (\ s .  s.TLBEntry24);
+  write_to := (\ v s .  (( s with<| TLBEntry24 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry23_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry23";
+  read_from := (\ s .  s.TLBEntry23);
+  write_to := (\ v s .  (( s with<| TLBEntry23 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry22_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry22";
+  read_from := (\ s .  s.TLBEntry22);
+  write_to := (\ v s .  (( s with<| TLBEntry22 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry21_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry21";
+  read_from := (\ s .  s.TLBEntry21);
+  write_to := (\ v s .  (( s with<| TLBEntry21 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry20_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry20";
+  read_from := (\ s .  s.TLBEntry20);
+  write_to := (\ v s .  (( s with<| TLBEntry20 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry19_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry19";
+  read_from := (\ s .  s.TLBEntry19);
+  write_to := (\ v s .  (( s with<| TLBEntry19 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry18_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry18";
+  read_from := (\ s .  s.TLBEntry18);
+  write_to := (\ v s .  (( s with<| TLBEntry18 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry17_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry17";
+  read_from := (\ s .  s.TLBEntry17);
+  write_to := (\ v s .  (( s with<| TLBEntry17 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry16_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry16";
+  read_from := (\ s .  s.TLBEntry16);
+  write_to := (\ v s .  (( s with<| TLBEntry16 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry15_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry15";
+  read_from := (\ s .  s.TLBEntry15);
+  write_to := (\ v s .  (( s with<| TLBEntry15 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry14_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry14";
+  read_from := (\ s .  s.TLBEntry14);
+  write_to := (\ v s .  (( s with<| TLBEntry14 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry13_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry13";
+  read_from := (\ s .  s.TLBEntry13);
+  write_to := (\ v s .  (( s with<| TLBEntry13 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry12_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry12";
+  read_from := (\ s .  s.TLBEntry12);
+  write_to := (\ v s .  (( s with<| TLBEntry12 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry11_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry11";
+  read_from := (\ s .  s.TLBEntry11);
+  write_to := (\ v s .  (( s with<| TLBEntry11 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry10_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry10";
+  read_from := (\ s .  s.TLBEntry10);
+  write_to := (\ v s .  (( s with<| TLBEntry10 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry09_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry09";
+  read_from := (\ s .  s.TLBEntry09);
+  write_to := (\ v s .  (( s with<| TLBEntry09 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry08_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry08";
+  read_from := (\ s .  s.TLBEntry08);
+  write_to := (\ v s .  (( s with<| TLBEntry08 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry07_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry07";
+  read_from := (\ s .  s.TLBEntry07);
+  write_to := (\ v s .  (( s with<| TLBEntry07 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry06_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry06";
+  read_from := (\ s .  s.TLBEntry06);
+  write_to := (\ v s .  (( s with<| TLBEntry06 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry05_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry05";
+  read_from := (\ s .  s.TLBEntry05);
+  write_to := (\ v s .  (( s with<| TLBEntry05 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry04_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry04";
+  read_from := (\ s .  s.TLBEntry04);
+  write_to := (\ v s .  (( s with<| TLBEntry04 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry03_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry03";
+  read_from := (\ s .  s.TLBEntry03);
+  write_to := (\ v s .  (( s with<| TLBEntry03 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry02_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry02";
+  read_from := (\ s .  s.TLBEntry02);
+  write_to := (\ v s .  (( s with<| TLBEntry02 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry01_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry01";
+  read_from := (\ s .  s.TLBEntry01);
+  write_to := (\ v s .  (( s with<| TLBEntry01 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry00_ref:((regstate),(register_value),(TLBEntry))register_ref)=  (<|
+  name := "TLBEntry00";
+  read_from := (\ s .  s.TLBEntry00);
+  write_to := (\ v s .  (( s with<| TLBEntry00 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBXContext_ref:((regstate),(register_value),(XContextReg))register_ref)=  (<|
+  name := "TLBXContext";
+  read_from := (\ s .  s.TLBXContext);
+  write_to := (\ v s .  (( s with<| TLBXContext := v |>)));
+  of_regval := (\ v .  XContextReg_of_regval v);
+  regval_of := (\ v .  regval_of_XContextReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntryHi_ref:((regstate),(register_value),(TLBEntryHiReg))register_ref)=  (<|
+  name := "TLBEntryHi";
+  read_from := (\ s .  s.TLBEntryHi);
+  write_to := (\ v s .  (( s with<| TLBEntryHi := v |>)));
+  of_regval := (\ v .  TLBEntryHiReg_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntryHiReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBWired_ref:((regstate),(register_value),((6)words$word))register_ref)=  (<|
+  name := "TLBWired";
+  read_from := (\ s .  s.TLBWired);
+  write_to := (\ v s .  (( s with<| TLBWired := v |>)));
+  of_regval := (\ v .  vector_6_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_6_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBPageMask_ref:((regstate),(register_value),((16)words$word))register_ref)=  (<|
+  name := "TLBPageMask";
+  read_from := (\ s .  s.TLBPageMask);
+  write_to := (\ v s .  (( s with<| TLBPageMask := v |>)));
+  of_regval := (\ v .  vector_16_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_16_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBContext_ref:((regstate),(register_value),(ContextReg))register_ref)=  (<|
+  name := "TLBContext";
+  read_from := (\ s .  s.TLBContext);
+  write_to := (\ v s .  (( s with<| TLBContext := v |>)));
+  of_regval := (\ v .  ContextReg_of_regval v);
+  regval_of := (\ v .  regval_of_ContextReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntryLo1_ref:((regstate),(register_value),(TLBEntryLoReg))register_ref)=  (<|
+  name := "TLBEntryLo1";
+  read_from := (\ s .  s.TLBEntryLo1);
+  write_to := (\ v s .  (( s with<| TLBEntryLo1 := v |>)));
+  of_regval := (\ v .  TLBEntryLoReg_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntryLoReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntryLo0_ref:((regstate),(register_value),(TLBEntryLoReg))register_ref)=  (<|
+  name := "TLBEntryLo0";
+  read_from := (\ s .  s.TLBEntryLo0);
+  write_to := (\ v s .  (( s with<| TLBEntryLo0 := v |>)));
+  of_regval := (\ v .  TLBEntryLoReg_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntryLoReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBRandom_ref:((regstate),(register_value),((6)words$word))register_ref)=  (<|
+  name := "TLBRandom";
+  read_from := (\ s .  s.TLBRandom);
+  write_to := (\ v s .  (( s with<| TLBRandom := v |>)));
+  of_regval := (\ v .  vector_6_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_6_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBIndex_ref:((regstate),(register_value),((6)words$word))register_ref)=  (<|
+  name := "TLBIndex";
+  read_from := (\ s .  s.TLBIndex);
+  write_to := (\ v s .  (( s with<| TLBIndex := v |>)));
+  of_regval := (\ v .  vector_6_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_6_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBProbe_ref:((regstate),(register_value),((1)words$word))register_ref)=  (<|
+  name := "TLBProbe";
+  read_from := (\ s .  s.TLBProbe);
+  write_to := (\ v s .  (( s with<| TLBProbe := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((nextPC_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "nextPC";
+  read_from := (\ s .  s.nextPC);
+  write_to := (\ v s .  (( s with<| nextPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "PC";
+  read_from := (\ s .  s.PC);
+  write_to := (\ v s .  (( s with<| PC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+(*val get_regval : string -> regstate -> maybe register_value*)
+val _ = Define `
+ ((get_regval:string -> regstate ->(register_value)option) reg_name s=
+   (if reg_name = "UART_RVALID" then SOME (UART_RVALID_ref.regval_of (UART_RVALID_ref.read_from s)) else
+  if reg_name = "UART_RDATA" then SOME (UART_RDATA_ref.regval_of (UART_RDATA_ref.read_from s)) else
+  if reg_name = "UART_WRITTEN" then SOME (UART_WRITTEN_ref.regval_of (UART_WRITTEN_ref.read_from s)) else
+  if reg_name = "UART_WDATA" then SOME (UART_WDATA_ref.regval_of (UART_WDATA_ref.read_from s)) else
+  if reg_name = "GPR" then SOME (GPR_ref.regval_of (GPR_ref.read_from s)) else
+  if reg_name = "LO" then SOME (LO_ref.regval_of (LO_ref.read_from s)) else
+  if reg_name = "HI" then SOME (HI_ref.regval_of (HI_ref.read_from s)) else
+  if reg_name = "delayedPC" then SOME (delayedPC_ref.regval_of (delayedPC_ref.read_from s)) else
+  if reg_name = "inBranchDelay" then SOME (inBranchDelay_ref.regval_of (inBranchDelay_ref.read_from s)) else
+  if reg_name = "branchPending" then SOME (branchPending_ref.regval_of (branchPending_ref.read_from s)) else
+  if reg_name = "CP0Status" then SOME (CP0Status_ref.regval_of (CP0Status_ref.read_from s)) else
+  if reg_name = "CP0ConfigK0" then SOME (CP0ConfigK0_ref.regval_of (CP0ConfigK0_ref.read_from s)) else
+  if reg_name = "CP0UserLocal" then SOME (CP0UserLocal_ref.regval_of (CP0UserLocal_ref.read_from s)) else
+  if reg_name = "CP0HWREna" then SOME (CP0HWREna_ref.regval_of (CP0HWREna_ref.read_from s)) else
+  if reg_name = "CP0Count" then SOME (CP0Count_ref.regval_of (CP0Count_ref.read_from s)) else
+  if reg_name = "CP0BadVAddr" then SOME (CP0BadVAddr_ref.regval_of (CP0BadVAddr_ref.read_from s)) else
+  if reg_name = "CP0LLAddr" then SOME (CP0LLAddr_ref.regval_of (CP0LLAddr_ref.read_from s)) else
+  if reg_name = "CP0LLBit" then SOME (CP0LLBit_ref.regval_of (CP0LLBit_ref.read_from s)) else
+  if reg_name = "CP0ErrorEPC" then SOME (CP0ErrorEPC_ref.regval_of (CP0ErrorEPC_ref.read_from s)) else
+  if reg_name = "CP0EPC" then SOME (CP0EPC_ref.regval_of (CP0EPC_ref.read_from s)) else
+  if reg_name = "CP0Cause" then SOME (CP0Cause_ref.regval_of (CP0Cause_ref.read_from s)) else
+  if reg_name = "CP0Compare" then SOME (CP0Compare_ref.regval_of (CP0Compare_ref.read_from s)) else
+  if reg_name = "TLBEntry63" then SOME (TLBEntry63_ref.regval_of (TLBEntry63_ref.read_from s)) else
+  if reg_name = "TLBEntry62" then SOME (TLBEntry62_ref.regval_of (TLBEntry62_ref.read_from s)) else
+  if reg_name = "TLBEntry61" then SOME (TLBEntry61_ref.regval_of (TLBEntry61_ref.read_from s)) else
+  if reg_name = "TLBEntry60" then SOME (TLBEntry60_ref.regval_of (TLBEntry60_ref.read_from s)) else
+  if reg_name = "TLBEntry59" then SOME (TLBEntry59_ref.regval_of (TLBEntry59_ref.read_from s)) else
+  if reg_name = "TLBEntry58" then SOME (TLBEntry58_ref.regval_of (TLBEntry58_ref.read_from s)) else
+  if reg_name = "TLBEntry57" then SOME (TLBEntry57_ref.regval_of (TLBEntry57_ref.read_from s)) else
+  if reg_name = "TLBEntry56" then SOME (TLBEntry56_ref.regval_of (TLBEntry56_ref.read_from s)) else
+  if reg_name = "TLBEntry55" then SOME (TLBEntry55_ref.regval_of (TLBEntry55_ref.read_from s)) else
+  if reg_name = "TLBEntry54" then SOME (TLBEntry54_ref.regval_of (TLBEntry54_ref.read_from s)) else
+  if reg_name = "TLBEntry53" then SOME (TLBEntry53_ref.regval_of (TLBEntry53_ref.read_from s)) else
+  if reg_name = "TLBEntry52" then SOME (TLBEntry52_ref.regval_of (TLBEntry52_ref.read_from s)) else
+  if reg_name = "TLBEntry51" then SOME (TLBEntry51_ref.regval_of (TLBEntry51_ref.read_from s)) else
+  if reg_name = "TLBEntry50" then SOME (TLBEntry50_ref.regval_of (TLBEntry50_ref.read_from s)) else
+  if reg_name = "TLBEntry49" then SOME (TLBEntry49_ref.regval_of (TLBEntry49_ref.read_from s)) else
+  if reg_name = "TLBEntry48" then SOME (TLBEntry48_ref.regval_of (TLBEntry48_ref.read_from s)) else
+  if reg_name = "TLBEntry47" then SOME (TLBEntry47_ref.regval_of (TLBEntry47_ref.read_from s)) else
+  if reg_name = "TLBEntry46" then SOME (TLBEntry46_ref.regval_of (TLBEntry46_ref.read_from s)) else
+  if reg_name = "TLBEntry45" then SOME (TLBEntry45_ref.regval_of (TLBEntry45_ref.read_from s)) else
+  if reg_name = "TLBEntry44" then SOME (TLBEntry44_ref.regval_of (TLBEntry44_ref.read_from s)) else
+  if reg_name = "TLBEntry43" then SOME (TLBEntry43_ref.regval_of (TLBEntry43_ref.read_from s)) else
+  if reg_name = "TLBEntry42" then SOME (TLBEntry42_ref.regval_of (TLBEntry42_ref.read_from s)) else
+  if reg_name = "TLBEntry41" then SOME (TLBEntry41_ref.regval_of (TLBEntry41_ref.read_from s)) else
+  if reg_name = "TLBEntry40" then SOME (TLBEntry40_ref.regval_of (TLBEntry40_ref.read_from s)) else
+  if reg_name = "TLBEntry39" then SOME (TLBEntry39_ref.regval_of (TLBEntry39_ref.read_from s)) else
+  if reg_name = "TLBEntry38" then SOME (TLBEntry38_ref.regval_of (TLBEntry38_ref.read_from s)) else
+  if reg_name = "TLBEntry37" then SOME (TLBEntry37_ref.regval_of (TLBEntry37_ref.read_from s)) else
+  if reg_name = "TLBEntry36" then SOME (TLBEntry36_ref.regval_of (TLBEntry36_ref.read_from s)) else
+  if reg_name = "TLBEntry35" then SOME (TLBEntry35_ref.regval_of (TLBEntry35_ref.read_from s)) else
+  if reg_name = "TLBEntry34" then SOME (TLBEntry34_ref.regval_of (TLBEntry34_ref.read_from s)) else
+  if reg_name = "TLBEntry33" then SOME (TLBEntry33_ref.regval_of (TLBEntry33_ref.read_from s)) else
+  if reg_name = "TLBEntry32" then SOME (TLBEntry32_ref.regval_of (TLBEntry32_ref.read_from s)) else
+  if reg_name = "TLBEntry31" then SOME (TLBEntry31_ref.regval_of (TLBEntry31_ref.read_from s)) else
+  if reg_name = "TLBEntry30" then SOME (TLBEntry30_ref.regval_of (TLBEntry30_ref.read_from s)) else
+  if reg_name = "TLBEntry29" then SOME (TLBEntry29_ref.regval_of (TLBEntry29_ref.read_from s)) else
+  if reg_name = "TLBEntry28" then SOME (TLBEntry28_ref.regval_of (TLBEntry28_ref.read_from s)) else
+  if reg_name = "TLBEntry27" then SOME (TLBEntry27_ref.regval_of (TLBEntry27_ref.read_from s)) else
+  if reg_name = "TLBEntry26" then SOME (TLBEntry26_ref.regval_of (TLBEntry26_ref.read_from s)) else
+  if reg_name = "TLBEntry25" then SOME (TLBEntry25_ref.regval_of (TLBEntry25_ref.read_from s)) else
+  if reg_name = "TLBEntry24" then SOME (TLBEntry24_ref.regval_of (TLBEntry24_ref.read_from s)) else
+  if reg_name = "TLBEntry23" then SOME (TLBEntry23_ref.regval_of (TLBEntry23_ref.read_from s)) else
+  if reg_name = "TLBEntry22" then SOME (TLBEntry22_ref.regval_of (TLBEntry22_ref.read_from s)) else
+  if reg_name = "TLBEntry21" then SOME (TLBEntry21_ref.regval_of (TLBEntry21_ref.read_from s)) else
+  if reg_name = "TLBEntry20" then SOME (TLBEntry20_ref.regval_of (TLBEntry20_ref.read_from s)) else
+  if reg_name = "TLBEntry19" then SOME (TLBEntry19_ref.regval_of (TLBEntry19_ref.read_from s)) else
+  if reg_name = "TLBEntry18" then SOME (TLBEntry18_ref.regval_of (TLBEntry18_ref.read_from s)) else
+  if reg_name = "TLBEntry17" then SOME (TLBEntry17_ref.regval_of (TLBEntry17_ref.read_from s)) else
+  if reg_name = "TLBEntry16" then SOME (TLBEntry16_ref.regval_of (TLBEntry16_ref.read_from s)) else
+  if reg_name = "TLBEntry15" then SOME (TLBEntry15_ref.regval_of (TLBEntry15_ref.read_from s)) else
+  if reg_name = "TLBEntry14" then SOME (TLBEntry14_ref.regval_of (TLBEntry14_ref.read_from s)) else
+  if reg_name = "TLBEntry13" then SOME (TLBEntry13_ref.regval_of (TLBEntry13_ref.read_from s)) else
+  if reg_name = "TLBEntry12" then SOME (TLBEntry12_ref.regval_of (TLBEntry12_ref.read_from s)) else
+  if reg_name = "TLBEntry11" then SOME (TLBEntry11_ref.regval_of (TLBEntry11_ref.read_from s)) else
+  if reg_name = "TLBEntry10" then SOME (TLBEntry10_ref.regval_of (TLBEntry10_ref.read_from s)) else
+  if reg_name = "TLBEntry09" then SOME (TLBEntry09_ref.regval_of (TLBEntry09_ref.read_from s)) else
+  if reg_name = "TLBEntry08" then SOME (TLBEntry08_ref.regval_of (TLBEntry08_ref.read_from s)) else
+  if reg_name = "TLBEntry07" then SOME (TLBEntry07_ref.regval_of (TLBEntry07_ref.read_from s)) else
+  if reg_name = "TLBEntry06" then SOME (TLBEntry06_ref.regval_of (TLBEntry06_ref.read_from s)) else
+  if reg_name = "TLBEntry05" then SOME (TLBEntry05_ref.regval_of (TLBEntry05_ref.read_from s)) else
+  if reg_name = "TLBEntry04" then SOME (TLBEntry04_ref.regval_of (TLBEntry04_ref.read_from s)) else
+  if reg_name = "TLBEntry03" then SOME (TLBEntry03_ref.regval_of (TLBEntry03_ref.read_from s)) else
+  if reg_name = "TLBEntry02" then SOME (TLBEntry02_ref.regval_of (TLBEntry02_ref.read_from s)) else
+  if reg_name = "TLBEntry01" then SOME (TLBEntry01_ref.regval_of (TLBEntry01_ref.read_from s)) else
+  if reg_name = "TLBEntry00" then SOME (TLBEntry00_ref.regval_of (TLBEntry00_ref.read_from s)) else
+  if reg_name = "TLBXContext" then SOME (TLBXContext_ref.regval_of (TLBXContext_ref.read_from s)) else
+  if reg_name = "TLBEntryHi" then SOME (TLBEntryHi_ref.regval_of (TLBEntryHi_ref.read_from s)) else
+  if reg_name = "TLBWired" then SOME (TLBWired_ref.regval_of (TLBWired_ref.read_from s)) else
+  if reg_name = "TLBPageMask" then SOME (TLBPageMask_ref.regval_of (TLBPageMask_ref.read_from s)) else
+  if reg_name = "TLBContext" then SOME (TLBContext_ref.regval_of (TLBContext_ref.read_from s)) else
+  if reg_name = "TLBEntryLo1" then SOME (TLBEntryLo1_ref.regval_of (TLBEntryLo1_ref.read_from s)) else
+  if reg_name = "TLBEntryLo0" then SOME (TLBEntryLo0_ref.regval_of (TLBEntryLo0_ref.read_from s)) else
+  if reg_name = "TLBRandom" then SOME (TLBRandom_ref.regval_of (TLBRandom_ref.read_from s)) else
+  if reg_name = "TLBIndex" then SOME (TLBIndex_ref.regval_of (TLBIndex_ref.read_from s)) else
+  if reg_name = "TLBProbe" then SOME (TLBProbe_ref.regval_of (TLBProbe_ref.read_from s)) else
+  if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else
+  if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
+  NONE))`;
+
+
+(*val set_regval : string -> register_value -> regstate -> maybe regstate*)
+val _ = Define `
+ ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=
+   (if reg_name = "UART_RVALID" then OPTION_MAP (\ v .  UART_RVALID_ref.write_to v s) (UART_RVALID_ref.of_regval v) else
+  if reg_name = "UART_RDATA" then OPTION_MAP (\ v .  UART_RDATA_ref.write_to v s) (UART_RDATA_ref.of_regval v) else
+  if reg_name = "UART_WRITTEN" then OPTION_MAP (\ v .  UART_WRITTEN_ref.write_to v s) (UART_WRITTEN_ref.of_regval v) else
+  if reg_name = "UART_WDATA" then OPTION_MAP (\ v .  UART_WDATA_ref.write_to v s) (UART_WDATA_ref.of_regval v) else
+  if reg_name = "GPR" then OPTION_MAP (\ v .  GPR_ref.write_to v s) (GPR_ref.of_regval v) else
+  if reg_name = "LO" then OPTION_MAP (\ v .  LO_ref.write_to v s) (LO_ref.of_regval v) else
+  if reg_name = "HI" then OPTION_MAP (\ v .  HI_ref.write_to v s) (HI_ref.of_regval v) else
+  if reg_name = "delayedPC" then OPTION_MAP (\ v .  delayedPC_ref.write_to v s) (delayedPC_ref.of_regval v) else
+  if reg_name = "inBranchDelay" then OPTION_MAP (\ v .  inBranchDelay_ref.write_to v s) (inBranchDelay_ref.of_regval v) else
+  if reg_name = "branchPending" then OPTION_MAP (\ v .  branchPending_ref.write_to v s) (branchPending_ref.of_regval v) else
+  if reg_name = "CP0Status" then OPTION_MAP (\ v .  CP0Status_ref.write_to v s) (CP0Status_ref.of_regval v) else
+  if reg_name = "CP0ConfigK0" then OPTION_MAP (\ v .  CP0ConfigK0_ref.write_to v s) (CP0ConfigK0_ref.of_regval v) else
+  if reg_name = "CP0UserLocal" then OPTION_MAP (\ v .  CP0UserLocal_ref.write_to v s) (CP0UserLocal_ref.of_regval v) else
+  if reg_name = "CP0HWREna" then OPTION_MAP (\ v .  CP0HWREna_ref.write_to v s) (CP0HWREna_ref.of_regval v) else
+  if reg_name = "CP0Count" then OPTION_MAP (\ v .  CP0Count_ref.write_to v s) (CP0Count_ref.of_regval v) else
+  if reg_name = "CP0BadVAddr" then OPTION_MAP (\ v .  CP0BadVAddr_ref.write_to v s) (CP0BadVAddr_ref.of_regval v) else
+  if reg_name = "CP0LLAddr" then OPTION_MAP (\ v .  CP0LLAddr_ref.write_to v s) (CP0LLAddr_ref.of_regval v) else
+  if reg_name = "CP0LLBit" then OPTION_MAP (\ v .  CP0LLBit_ref.write_to v s) (CP0LLBit_ref.of_regval v) else
+  if reg_name = "CP0ErrorEPC" then OPTION_MAP (\ v .  CP0ErrorEPC_ref.write_to v s) (CP0ErrorEPC_ref.of_regval v) else
+  if reg_name = "CP0EPC" then OPTION_MAP (\ v .  CP0EPC_ref.write_to v s) (CP0EPC_ref.of_regval v) else
+  if reg_name = "CP0Cause" then OPTION_MAP (\ v .  CP0Cause_ref.write_to v s) (CP0Cause_ref.of_regval v) else
+  if reg_name = "CP0Compare" then OPTION_MAP (\ v .  CP0Compare_ref.write_to v s) (CP0Compare_ref.of_regval v) else
+  if reg_name = "TLBEntry63" then OPTION_MAP (\ v .  TLBEntry63_ref.write_to v s) (TLBEntry63_ref.of_regval v) else
+  if reg_name = "TLBEntry62" then OPTION_MAP (\ v .  TLBEntry62_ref.write_to v s) (TLBEntry62_ref.of_regval v) else
+  if reg_name = "TLBEntry61" then OPTION_MAP (\ v .  TLBEntry61_ref.write_to v s) (TLBEntry61_ref.of_regval v) else
+  if reg_name = "TLBEntry60" then OPTION_MAP (\ v .  TLBEntry60_ref.write_to v s) (TLBEntry60_ref.of_regval v) else
+  if reg_name = "TLBEntry59" then OPTION_MAP (\ v .  TLBEntry59_ref.write_to v s) (TLBEntry59_ref.of_regval v) else
+  if reg_name = "TLBEntry58" then OPTION_MAP (\ v .  TLBEntry58_ref.write_to v s) (TLBEntry58_ref.of_regval v) else
+  if reg_name = "TLBEntry57" then OPTION_MAP (\ v .  TLBEntry57_ref.write_to v s) (TLBEntry57_ref.of_regval v) else
+  if reg_name = "TLBEntry56" then OPTION_MAP (\ v .  TLBEntry56_ref.write_to v s) (TLBEntry56_ref.of_regval v) else
+  if reg_name = "TLBEntry55" then OPTION_MAP (\ v .  TLBEntry55_ref.write_to v s) (TLBEntry55_ref.of_regval v) else
+  if reg_name = "TLBEntry54" then OPTION_MAP (\ v .  TLBEntry54_ref.write_to v s) (TLBEntry54_ref.of_regval v) else
+  if reg_name = "TLBEntry53" then OPTION_MAP (\ v .  TLBEntry53_ref.write_to v s) (TLBEntry53_ref.of_regval v) else
+  if reg_name = "TLBEntry52" then OPTION_MAP (\ v .  TLBEntry52_ref.write_to v s) (TLBEntry52_ref.of_regval v) else
+  if reg_name = "TLBEntry51" then OPTION_MAP (\ v .  TLBEntry51_ref.write_to v s) (TLBEntry51_ref.of_regval v) else
+  if reg_name = "TLBEntry50" then OPTION_MAP (\ v .  TLBEntry50_ref.write_to v s) (TLBEntry50_ref.of_regval v) else
+  if reg_name = "TLBEntry49" then OPTION_MAP (\ v .  TLBEntry49_ref.write_to v s) (TLBEntry49_ref.of_regval v) else
+  if reg_name = "TLBEntry48" then OPTION_MAP (\ v .  TLBEntry48_ref.write_to v s) (TLBEntry48_ref.of_regval v) else
+  if reg_name = "TLBEntry47" then OPTION_MAP (\ v .  TLBEntry47_ref.write_to v s) (TLBEntry47_ref.of_regval v) else
+  if reg_name = "TLBEntry46" then OPTION_MAP (\ v .  TLBEntry46_ref.write_to v s) (TLBEntry46_ref.of_regval v) else
+  if reg_name = "TLBEntry45" then OPTION_MAP (\ v .  TLBEntry45_ref.write_to v s) (TLBEntry45_ref.of_regval v) else
+  if reg_name = "TLBEntry44" then OPTION_MAP (\ v .  TLBEntry44_ref.write_to v s) (TLBEntry44_ref.of_regval v) else
+  if reg_name = "TLBEntry43" then OPTION_MAP (\ v .  TLBEntry43_ref.write_to v s) (TLBEntry43_ref.of_regval v) else
+  if reg_name = "TLBEntry42" then OPTION_MAP (\ v .  TLBEntry42_ref.write_to v s) (TLBEntry42_ref.of_regval v) else
+  if reg_name = "TLBEntry41" then OPTION_MAP (\ v .  TLBEntry41_ref.write_to v s) (TLBEntry41_ref.of_regval v) else
+  if reg_name = "TLBEntry40" then OPTION_MAP (\ v .  TLBEntry40_ref.write_to v s) (TLBEntry40_ref.of_regval v) else
+  if reg_name = "TLBEntry39" then OPTION_MAP (\ v .  TLBEntry39_ref.write_to v s) (TLBEntry39_ref.of_regval v) else
+  if reg_name = "TLBEntry38" then OPTION_MAP (\ v .  TLBEntry38_ref.write_to v s) (TLBEntry38_ref.of_regval v) else
+  if reg_name = "TLBEntry37" then OPTION_MAP (\ v .  TLBEntry37_ref.write_to v s) (TLBEntry37_ref.of_regval v) else
+  if reg_name = "TLBEntry36" then OPTION_MAP (\ v .  TLBEntry36_ref.write_to v s) (TLBEntry36_ref.of_regval v) else
+  if reg_name = "TLBEntry35" then OPTION_MAP (\ v .  TLBEntry35_ref.write_to v s) (TLBEntry35_ref.of_regval v) else
+  if reg_name = "TLBEntry34" then OPTION_MAP (\ v .  TLBEntry34_ref.write_to v s) (TLBEntry34_ref.of_regval v) else
+  if reg_name = "TLBEntry33" then OPTION_MAP (\ v .  TLBEntry33_ref.write_to v s) (TLBEntry33_ref.of_regval v) else
+  if reg_name = "TLBEntry32" then OPTION_MAP (\ v .  TLBEntry32_ref.write_to v s) (TLBEntry32_ref.of_regval v) else
+  if reg_name = "TLBEntry31" then OPTION_MAP (\ v .  TLBEntry31_ref.write_to v s) (TLBEntry31_ref.of_regval v) else
+  if reg_name = "TLBEntry30" then OPTION_MAP (\ v .  TLBEntry30_ref.write_to v s) (TLBEntry30_ref.of_regval v) else
+  if reg_name = "TLBEntry29" then OPTION_MAP (\ v .  TLBEntry29_ref.write_to v s) (TLBEntry29_ref.of_regval v) else
+  if reg_name = "TLBEntry28" then OPTION_MAP (\ v .  TLBEntry28_ref.write_to v s) (TLBEntry28_ref.of_regval v) else
+  if reg_name = "TLBEntry27" then OPTION_MAP (\ v .  TLBEntry27_ref.write_to v s) (TLBEntry27_ref.of_regval v) else
+  if reg_name = "TLBEntry26" then OPTION_MAP (\ v .  TLBEntry26_ref.write_to v s) (TLBEntry26_ref.of_regval v) else
+  if reg_name = "TLBEntry25" then OPTION_MAP (\ v .  TLBEntry25_ref.write_to v s) (TLBEntry25_ref.of_regval v) else
+  if reg_name = "TLBEntry24" then OPTION_MAP (\ v .  TLBEntry24_ref.write_to v s) (TLBEntry24_ref.of_regval v) else
+  if reg_name = "TLBEntry23" then OPTION_MAP (\ v .  TLBEntry23_ref.write_to v s) (TLBEntry23_ref.of_regval v) else
+  if reg_name = "TLBEntry22" then OPTION_MAP (\ v .  TLBEntry22_ref.write_to v s) (TLBEntry22_ref.of_regval v) else
+  if reg_name = "TLBEntry21" then OPTION_MAP (\ v .  TLBEntry21_ref.write_to v s) (TLBEntry21_ref.of_regval v) else
+  if reg_name = "TLBEntry20" then OPTION_MAP (\ v .  TLBEntry20_ref.write_to v s) (TLBEntry20_ref.of_regval v) else
+  if reg_name = "TLBEntry19" then OPTION_MAP (\ v .  TLBEntry19_ref.write_to v s) (TLBEntry19_ref.of_regval v) else
+  if reg_name = "TLBEntry18" then OPTION_MAP (\ v .  TLBEntry18_ref.write_to v s) (TLBEntry18_ref.of_regval v) else
+  if reg_name = "TLBEntry17" then OPTION_MAP (\ v .  TLBEntry17_ref.write_to v s) (TLBEntry17_ref.of_regval v) else
+  if reg_name = "TLBEntry16" then OPTION_MAP (\ v .  TLBEntry16_ref.write_to v s) (TLBEntry16_ref.of_regval v) else
+  if reg_name = "TLBEntry15" then OPTION_MAP (\ v .  TLBEntry15_ref.write_to v s) (TLBEntry15_ref.of_regval v) else
+  if reg_name = "TLBEntry14" then OPTION_MAP (\ v .  TLBEntry14_ref.write_to v s) (TLBEntry14_ref.of_regval v) else
+  if reg_name = "TLBEntry13" then OPTION_MAP (\ v .  TLBEntry13_ref.write_to v s) (TLBEntry13_ref.of_regval v) else
+  if reg_name = "TLBEntry12" then OPTION_MAP (\ v .  TLBEntry12_ref.write_to v s) (TLBEntry12_ref.of_regval v) else
+  if reg_name = "TLBEntry11" then OPTION_MAP (\ v .  TLBEntry11_ref.write_to v s) (TLBEntry11_ref.of_regval v) else
+  if reg_name = "TLBEntry10" then OPTION_MAP (\ v .  TLBEntry10_ref.write_to v s) (TLBEntry10_ref.of_regval v) else
+  if reg_name = "TLBEntry09" then OPTION_MAP (\ v .  TLBEntry09_ref.write_to v s) (TLBEntry09_ref.of_regval v) else
+  if reg_name = "TLBEntry08" then OPTION_MAP (\ v .  TLBEntry08_ref.write_to v s) (TLBEntry08_ref.of_regval v) else
+  if reg_name = "TLBEntry07" then OPTION_MAP (\ v .  TLBEntry07_ref.write_to v s) (TLBEntry07_ref.of_regval v) else
+  if reg_name = "TLBEntry06" then OPTION_MAP (\ v .  TLBEntry06_ref.write_to v s) (TLBEntry06_ref.of_regval v) else
+  if reg_name = "TLBEntry05" then OPTION_MAP (\ v .  TLBEntry05_ref.write_to v s) (TLBEntry05_ref.of_regval v) else
+  if reg_name = "TLBEntry04" then OPTION_MAP (\ v .  TLBEntry04_ref.write_to v s) (TLBEntry04_ref.of_regval v) else
+  if reg_name = "TLBEntry03" then OPTION_MAP (\ v .  TLBEntry03_ref.write_to v s) (TLBEntry03_ref.of_regval v) else
+  if reg_name = "TLBEntry02" then OPTION_MAP (\ v .  TLBEntry02_ref.write_to v s) (TLBEntry02_ref.of_regval v) else
+  if reg_name = "TLBEntry01" then OPTION_MAP (\ v .  TLBEntry01_ref.write_to v s) (TLBEntry01_ref.of_regval v) else
+  if reg_name = "TLBEntry00" then OPTION_MAP (\ v .  TLBEntry00_ref.write_to v s) (TLBEntry00_ref.of_regval v) else
+  if reg_name = "TLBXContext" then OPTION_MAP (\ v .  TLBXContext_ref.write_to v s) (TLBXContext_ref.of_regval v) else
+  if reg_name = "TLBEntryHi" then OPTION_MAP (\ v .  TLBEntryHi_ref.write_to v s) (TLBEntryHi_ref.of_regval v) else
+  if reg_name = "TLBWired" then OPTION_MAP (\ v .  TLBWired_ref.write_to v s) (TLBWired_ref.of_regval v) else
+  if reg_name = "TLBPageMask" then OPTION_MAP (\ v .  TLBPageMask_ref.write_to v s) (TLBPageMask_ref.of_regval v) else
+  if reg_name = "TLBContext" then OPTION_MAP (\ v .  TLBContext_ref.write_to v s) (TLBContext_ref.of_regval v) else
+  if reg_name = "TLBEntryLo1" then OPTION_MAP (\ v .  TLBEntryLo1_ref.write_to v s) (TLBEntryLo1_ref.of_regval v) else
+  if reg_name = "TLBEntryLo0" then OPTION_MAP (\ v .  TLBEntryLo0_ref.write_to v s) (TLBEntryLo0_ref.of_regval v) else
+  if reg_name = "TLBRandom" then OPTION_MAP (\ v .  TLBRandom_ref.write_to v s) (TLBRandom_ref.of_regval v) else
+  if reg_name = "TLBIndex" then OPTION_MAP (\ v .  TLBIndex_ref.write_to v s) (TLBIndex_ref.of_regval v) else
+  if reg_name = "TLBProbe" then OPTION_MAP (\ v .  TLBProbe_ref.write_to v s) (TLBProbe_ref.of_regval v) else
+  if reg_name = "nextPC" then OPTION_MAP (\ v .  nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else
+  if reg_name = "PC" then OPTION_MAP (\ v .  PC_ref.write_to v s) (PC_ref.of_regval v) else
+  NONE))`;
+
+
+val _ = Define `
+ ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))=  (get_regval, set_regval))`;
+
+
+
+val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``:  (regstate, 'a, 'r, exception)monadR``);
+val _ = type_abbrev((*  'a *) "M" , ``:  (regstate, 'a, exception)monad``);
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml b/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml
index 160f550f..bd1d98af 100644
--- a/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml
+++ b/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from riscv.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory riscv_typesTheory riscv_extrasTheory riscvTheory;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory riscvTheory;
 
 val _ = numLib.prefer_num();
 
diff --git a/snapshots/hol4/sail/riscv/riscvScript.sml b/snapshots/hol4/sail/riscv/riscvScript.sml
index e8514af3..bd56ca74 100644
--- a/snapshots/hol4/sail/riscv/riscvScript.sml
+++ b/snapshots/hol4/sail/riscv/riscvScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from riscv.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory riscv_typesTheory riscv_extrasTheory;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory;
 
 val _ = numLib.prefer_num();
 
@@ -10,14 +10,51 @@ val _ = new_theory "riscv"
 
 (*Generated by Sail from riscv.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 (*open import Riscv_types*)
 (*open import Riscv_extras*)
 
+(*val spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((spc_forwards:unit -> string) () =  " ")`;
+
+
+(*val spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((spc_backwards:string -> unit) s=  () )`;
+
+
+(*val opt_spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((opt_spc_forwards:unit -> string) () =  "")`;
+
+
+(*val opt_spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((opt_spc_backwards:string -> unit) s=  () )`;
+
+
+(*val def_spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((def_spc_forwards:unit -> string) () =  " ")`;
+
+
+(*val def_spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((def_spc_backwards:string -> unit) s=  () )`;
+
+
 
 
 
@@ -39,7 +76,7 @@ val _ = new_theory "riscv"
 (*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*)
 
 val _ = Define `
- ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1=  ((get_slice_int0 n m o1  :  'n words$word)))`;
+ ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1=  ((get_slice_int n m o1  :  'n words$word)))`;
 
 
 (*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*)
@@ -60,28 +97,73 @@ val _ = Define `
 (*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*)
 
 val _ = Define `
- ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (state_monad$seqS
+ ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (sail2_state_monad$seqS
    (write_ram (( 64 : int):ii) width
      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
        :  64 words$word) addr data)
-   (state_monad$returnS T)))`;
+   (sail2_state_monad$returnS T)))`;
 
 
 (*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*)
 
-(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*)
+(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (maybe (mword 'int8_times_n))*)
 
 val _ = Define `
- ((RISCV_read:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=  (state_monad$bindS
-   (read_ram (( 64 : int):ii) width
-      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-        :  64 words$word) addr
-     : ( 'int8_times_n words$word) M) (\ (w__0 :  'int8_times_n words$word) . 
-   state_monad$returnS (SOME w__0))))`;
+ ((RISCV_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl res=
+    ((case (aq, rl, res) of
+     (F, F, F) => sail2_state_monad$bindS
+      (MEMr (( 64 : int):ii) width
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word) addr
+        : ( 'int8_times_n words$word) M) (\ (w__0 :  'int8_times_n words$word) . 
+      sail2_state_monad$returnS (SOME w__0))
+   | (T, F, F) => sail2_state_monad$bindS
+      (MEMr_acquire (( 64 : int):ii) width
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word) addr
+        : ( 'int8_times_n words$word) M) (\ (w__1 :  'int8_times_n words$word) . 
+      sail2_state_monad$returnS (SOME w__1))
+   | (T, T, F) => sail2_state_monad$bindS
+      (MEMr_strong_acquire (( 64 : int):ii) width
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word) addr
+        : ( 'int8_times_n words$word) M) (\ (w__2 :  'int8_times_n words$word) . 
+      sail2_state_monad$returnS (SOME w__2))
+   | (F, F, T) => sail2_state_monad$bindS
+      (MEMr_reserved (( 64 : int):ii) width
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word) addr
+        : ( 'int8_times_n words$word) M) (\ (w__3 :  'int8_times_n words$word) . 
+      sail2_state_monad$returnS (SOME w__3))
+   | (T, F, T) => sail2_state_monad$bindS
+      (MEMr_reserved_acquire (( 64 : int):ii) width
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word) addr
+        : ( 'int8_times_n words$word) M) (\ (w__4 :  'int8_times_n words$word) . 
+      sail2_state_monad$returnS (SOME w__4))
+   | (T, T, T) => sail2_state_monad$bindS
+      (MEMr_reserved_strong_acquire (( 64 : int):ii) width
+         (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+           :  64 words$word) addr
+        : ( 'int8_times_n words$word) M) (\ (w__5 :  'int8_times_n words$word) . 
+      sail2_state_monad$returnS (SOME w__5))
+   | (F, T, F) => sail2_state_monad$returnS NONE
+   | (F, T, T) => sail2_state_monad$returnS NONE
+   )))`;
 
 
 (*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*)
@@ -101,7 +183,7 @@ val _ = Define `
 (*val coerce_int_nat : ii -> M ii*)
 
 val _ = Define `
- ((coerce_int_nat:int ->(regstate)state_monad$sequential_state ->(((int),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) x=  (state_monad$seqS (state_monad$assert_expS T "") (state_monad$returnS x)))`;
+ ((coerce_int_nat:int ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x=  (sail2_state_monad$seqS (sail2_state_monad$assert_expS T "") (sail2_state_monad$returnS x)))`;
 
 
 (*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
@@ -161,13 +243,13 @@ val _ = Define `
 (*val vector64 : ii -> mword ty64*)
 
 val _ = Define `
- ((vector64:int ->(64)words$word) n=  ((get_slice_int0 (( 64 : int):ii) n (( 0 : int):ii)  :  64 words$word)))`;
+ ((vector64:int ->(64)words$word) n=  ((get_slice_int (( 64 : int):ii) n (( 0 : int):ii)  :  64 words$word)))`;
 
 
 (*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*)
 
 val _ = Define `
- ((to_bits:int -> int -> 'l words$word) l n=  ((get_slice_int0 l n (( 0 : int):ii)  :  'l words$word)))`;
+ ((to_bits:int -> int -> 'l words$word) l n=  ((get_slice_int l n (( 0 : int):ii)  :  'l words$word)))`;
 
 
 (*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*)
@@ -231,29 +313,89 @@ val _ = Define `
 (*val rX : integer -> M (mword ty64)*)
 
 val _ = Define `
- ((rX:int ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) l__81=
-    (if (((l__81 = (( 0 : int):ii)))) then
-     state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ ((rX:int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r=
+    (let p0_ = r in
+   if (((p0_ = (( 0 : int):ii)))) then
+     sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
               :  64 words$word)
-   else state_monad$bindS
-     (state_monad$read_regS Xs_ref) (\ (w__0 : xlenbits list) . 
-     state_monad$returnS ((access_list_dec w__0 l__81  :  64 words$word)))))`;
+   else if (((p0_ = (( 1 : int):ii)))) then (sail2_state_monad$read_regS x1_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 2 : int):ii)))) then (sail2_state_monad$read_regS x2_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 3 : int):ii)))) then (sail2_state_monad$read_regS x3_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 4 : int):ii)))) then (sail2_state_monad$read_regS x4_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 5 : int):ii)))) then (sail2_state_monad$read_regS x5_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 6 : int):ii)))) then (sail2_state_monad$read_regS x6_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 7 : int):ii)))) then (sail2_state_monad$read_regS x7_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 8 : int):ii)))) then (sail2_state_monad$read_regS x8_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 9 : int):ii)))) then (sail2_state_monad$read_regS x9_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 10 : int):ii)))) then (sail2_state_monad$read_regS x10_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 11 : int):ii)))) then (sail2_state_monad$read_regS x11_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 12 : int):ii)))) then (sail2_state_monad$read_regS x12_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 13 : int):ii)))) then (sail2_state_monad$read_regS x13_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 14 : int):ii)))) then (sail2_state_monad$read_regS x14_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 15 : int):ii)))) then (sail2_state_monad$read_regS x15_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 16 : int):ii)))) then (sail2_state_monad$read_regS x16_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 17 : int):ii)))) then (sail2_state_monad$read_regS x17_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 18 : int):ii)))) then (sail2_state_monad$read_regS x18_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 19 : int):ii)))) then (sail2_state_monad$read_regS x19_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 20 : int):ii)))) then (sail2_state_monad$read_regS x20_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 21 : int):ii)))) then (sail2_state_monad$read_regS x21_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 22 : int):ii)))) then (sail2_state_monad$read_regS x22_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 23 : int):ii)))) then (sail2_state_monad$read_regS x23_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 24 : int):ii)))) then (sail2_state_monad$read_regS x24_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 25 : int):ii)))) then (sail2_state_monad$read_regS x25_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 26 : int):ii)))) then (sail2_state_monad$read_regS x26_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 27 : int):ii)))) then (sail2_state_monad$read_regS x27_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 28 : int):ii)))) then (sail2_state_monad$read_regS x28_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 29 : int):ii)))) then (sail2_state_monad$read_regS x29_ref  : ( 64 words$word) M)
+   else if (((p0_ = (( 30 : int):ii)))) then (sail2_state_monad$read_regS x30_ref  : ( 64 words$word) M)
+   else (sail2_state_monad$read_regS x31_ref  : ( 64 words$word) M)))`;
 
 
 (*val wX : integer -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((wX:int ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r v=
-    (if (((r <> (( 0 : int):ii)))) then state_monad$bindS
-     (state_monad$read_regS Xs_ref) (\ (w__0 : ( 64 words$word) list) .  state_monad$seqS
-     (state_monad$write_regS Xs_ref ((update_list_dec w__0 r v  : ( 64 words$word) list)))
-     (state_monad$returnS ((prerr_endline
-                ((STRCAT "x"
-                    ((STRCAT ((stringFromInteger r))
-                        ((STRCAT " <- " ((string_of_vec v))))))))))))
-   else state_monad$returnS () ))`;
+ ((wX:int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r v=
+    (let p0_ = r in sail2_state_monad$seqS
+   (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS () 
+    else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$write_regS x1_ref v
+    else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$write_regS x2_ref v
+    else if (((p0_ = (( 3 : int):ii)))) then sail2_state_monad$write_regS x3_ref v
+    else if (((p0_ = (( 4 : int):ii)))) then sail2_state_monad$write_regS x4_ref v
+    else if (((p0_ = (( 5 : int):ii)))) then sail2_state_monad$write_regS x5_ref v
+    else if (((p0_ = (( 6 : int):ii)))) then sail2_state_monad$write_regS x6_ref v
+    else if (((p0_ = (( 7 : int):ii)))) then sail2_state_monad$write_regS x7_ref v
+    else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$write_regS x8_ref v
+    else if (((p0_ = (( 9 : int):ii)))) then sail2_state_monad$write_regS x9_ref v
+    else if (((p0_ = (( 10 : int):ii)))) then sail2_state_monad$write_regS x10_ref v
+    else if (((p0_ = (( 11 : int):ii)))) then sail2_state_monad$write_regS x11_ref v
+    else if (((p0_ = (( 12 : int):ii)))) then sail2_state_monad$write_regS x12_ref v
+    else if (((p0_ = (( 13 : int):ii)))) then sail2_state_monad$write_regS x13_ref v
+    else if (((p0_ = (( 14 : int):ii)))) then sail2_state_monad$write_regS x14_ref v
+    else if (((p0_ = (( 15 : int):ii)))) then sail2_state_monad$write_regS x15_ref v
+    else if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$write_regS x16_ref v
+    else if (((p0_ = (( 17 : int):ii)))) then sail2_state_monad$write_regS x17_ref v
+    else if (((p0_ = (( 18 : int):ii)))) then sail2_state_monad$write_regS x18_ref v
+    else if (((p0_ = (( 19 : int):ii)))) then sail2_state_monad$write_regS x19_ref v
+    else if (((p0_ = (( 20 : int):ii)))) then sail2_state_monad$write_regS x20_ref v
+    else if (((p0_ = (( 21 : int):ii)))) then sail2_state_monad$write_regS x21_ref v
+    else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$write_regS x22_ref v
+    else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$write_regS x23_ref v
+    else if (((p0_ = (( 24 : int):ii)))) then sail2_state_monad$write_regS x24_ref v
+    else if (((p0_ = (( 25 : int):ii)))) then sail2_state_monad$write_regS x25_ref v
+    else if (((p0_ = (( 26 : int):ii)))) then sail2_state_monad$write_regS x26_ref v
+    else if (((p0_ = (( 27 : int):ii)))) then sail2_state_monad$write_regS x27_ref v
+    else if (((p0_ = (( 28 : int):ii)))) then sail2_state_monad$write_regS x28_ref v
+    else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$write_regS x29_ref v
+    else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$write_regS x30_ref v
+    else sail2_state_monad$write_regS x31_ref v)
+   (sail2_state_monad$returnS (if (((r <> (( 0 : int):ii)))) then
+             print_endline
+               ((STRCAT "x"
+                   ((STRCAT ((stringFromInteger r))
+                       ((STRCAT " <- " ((string_of_bits v))))))))
+           else () ))))`;
 
 
 (*val reg_name_abi : mword ty5 -> string*)
@@ -330,9 +472,9 @@ val _ = Define `
 
 val _ = Define `
  ((Architecture_of_num:int -> Architecture) arg_=
-    (let l__79 = arg_ in
-   if (((l__79 = (( 0 : int):ii)))) then RV32
-   else if (((l__79 = (( 1 : int):ii)))) then RV64
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RV32
+   else if (((p0_ = (( 1 : int):ii)))) then RV64
    else RV128))`;
 
 
@@ -369,9 +511,9 @@ val _ = Define `
 
 val _ = Define `
  ((Privilege_of_num:int -> Privilege) arg_=
-    (let l__77 = arg_ in
-   if (((l__77 = (( 0 : int):ii)))) then User
-   else if (((l__77 = (( 1 : int):ii)))) then Supervisor
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then User
+   else if (((p0_ = (( 1 : int):ii)))) then Supervisor
    else Machine))`;
 
 
@@ -413,10 +555,10 @@ val _ = Define `
 
 val _ = Define `
  ((AccessType_of_num:int -> AccessType) arg_=
-    (let l__74 = arg_ in
-   if (((l__74 = (( 0 : int):ii)))) then Read
-   else if (((l__74 = (( 1 : int):ii)))) then Write
-   else if (((l__74 = (( 2 : int):ii)))) then ReadWrite
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Read
+   else if (((p0_ = (( 1 : int):ii)))) then Write
+   else if (((p0_ = (( 2 : int):ii)))) then ReadWrite
    else Execute))`;
 
 
@@ -427,12 +569,19 @@ val _ = Define `
     ((case arg_ of   Read => (( 0 : int):ii) | Write => (( 1 : int):ii) | ReadWrite => (( 2 : int):ii) | Execute => (( 3 : int):ii) )))`;
 
 
+(*val accessType_to_str : AccessType -> string*)
+
+val _ = Define `
+ ((accessType_to_str:AccessType -> string) a=
+    ((case a of   Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" )))`;
+
+
 (*val ReadType_of_num : integer -> ReadType*)
 
 val _ = Define `
  ((ReadType_of_num:int -> ReadType) arg_=
-    (let l__73 = arg_ in
-   if (((l__73 = (( 0 : int):ii)))) then Instruction
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Instruction
    else Data))`;
 
 
@@ -442,26 +591,32 @@ val _ = Define `
  ((num_of_ReadType:ReadType -> int) arg_=  ((case arg_ of   Instruction => (( 0 : int):ii) | Data => (( 1 : int):ii) )))`;
 
 
+(*val readType_to_str : ReadType -> string*)
+
+val _ = Define `
+ ((readType_to_str:ReadType -> string) r=  ((case r of   Instruction => "I" | Data => "D" )))`;
+
+
 (*val ExceptionType_of_num : integer -> ExceptionType*)
 
 val _ = Define `
  ((ExceptionType_of_num:int -> ExceptionType) arg_=
-    (let l__58 = arg_ in
-   if (((l__58 = (( 0 : int):ii)))) then E_Fetch_Addr_Align
-   else if (((l__58 = (( 1 : int):ii)))) then E_Fetch_Access_Fault
-   else if (((l__58 = (( 2 : int):ii)))) then E_Illegal_Instr
-   else if (((l__58 = (( 3 : int):ii)))) then E_Breakpoint
-   else if (((l__58 = (( 4 : int):ii)))) then E_Load_Addr_Align
-   else if (((l__58 = (( 5 : int):ii)))) then E_Load_Access_Fault
-   else if (((l__58 = (( 6 : int):ii)))) then E_SAMO_Addr_Align
-   else if (((l__58 = (( 7 : int):ii)))) then E_SAMO_Access_Fault
-   else if (((l__58 = (( 8 : int):ii)))) then E_U_EnvCall
-   else if (((l__58 = (( 9 : int):ii)))) then E_S_EnvCall
-   else if (((l__58 = (( 10 : int):ii)))) then E_Reserved_10
-   else if (((l__58 = (( 11 : int):ii)))) then E_M_EnvCall
-   else if (((l__58 = (( 12 : int):ii)))) then E_Fetch_Page_Fault
-   else if (((l__58 = (( 13 : int):ii)))) then E_Load_Page_Fault
-   else if (((l__58 = (( 14 : int):ii)))) then E_Reserved_14
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then E_Fetch_Addr_Align
+   else if (((p0_ = (( 1 : int):ii)))) then E_Fetch_Access_Fault
+   else if (((p0_ = (( 2 : int):ii)))) then E_Illegal_Instr
+   else if (((p0_ = (( 3 : int):ii)))) then E_Breakpoint
+   else if (((p0_ = (( 4 : int):ii)))) then E_Load_Addr_Align
+   else if (((p0_ = (( 5 : int):ii)))) then E_Load_Access_Fault
+   else if (((p0_ = (( 6 : int):ii)))) then E_SAMO_Addr_Align
+   else if (((p0_ = (( 7 : int):ii)))) then E_SAMO_Access_Fault
+   else if (((p0_ = (( 8 : int):ii)))) then E_U_EnvCall
+   else if (((p0_ = (( 9 : int):ii)))) then E_S_EnvCall
+   else if (((p0_ = (( 10 : int):ii)))) then E_Reserved_10
+   else if (((p0_ = (( 11 : int):ii)))) then E_M_EnvCall
+   else if (((p0_ = (( 12 : int):ii)))) then E_Fetch_Page_Fault
+   else if (((p0_ = (( 13 : int):ii)))) then E_Load_Page_Fault
+   else if (((p0_ = (( 14 : int):ii)))) then E_Reserved_14
    else E_SAMO_Page_Fault))`;
 
 
@@ -518,7 +673,7 @@ val _ = Define `
 val _ = Define `
  ((exceptionType_to_str:ExceptionType -> string) e=
     ((case e of
-     E_Fetch_Addr_Align => "fisaligned-fetch"
+     E_Fetch_Addr_Align => "misaligned-fetch"
    | E_Fetch_Access_Fault => "fetch-access-fault"
    | E_Illegal_Instr => "illegal-instruction"
    | E_Breakpoint => "breakpoint"
@@ -541,15 +696,15 @@ val _ = Define `
 
 val _ = Define `
  ((InterruptType_of_num:int -> InterruptType) arg_=
-    (let l__50 = arg_ in
-   if (((l__50 = (( 0 : int):ii)))) then I_U_Software
-   else if (((l__50 = (( 1 : int):ii)))) then I_S_Software
-   else if (((l__50 = (( 2 : int):ii)))) then I_M_Software
-   else if (((l__50 = (( 3 : int):ii)))) then I_U_Timer
-   else if (((l__50 = (( 4 : int):ii)))) then I_S_Timer
-   else if (((l__50 = (( 5 : int):ii)))) then I_M_Timer
-   else if (((l__50 = (( 6 : int):ii)))) then I_U_External
-   else if (((l__50 = (( 7 : int):ii)))) then I_S_External
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then I_U_Software
+   else if (((p0_ = (( 1 : int):ii)))) then I_S_Software
+   else if (((p0_ = (( 2 : int):ii)))) then I_M_Software
+   else if (((p0_ = (( 3 : int):ii)))) then I_U_Timer
+   else if (((p0_ = (( 4 : int):ii)))) then I_S_Timer
+   else if (((p0_ = (( 5 : int):ii)))) then I_M_Timer
+   else if (((p0_ = (( 6 : int):ii)))) then I_U_External
+   else if (((p0_ = (( 7 : int):ii)))) then I_S_External
    else I_M_External))`;
 
 
@@ -591,9 +746,9 @@ val _ = Define `
 
 val _ = Define `
  ((TrapVectorMode_of_num:int -> TrapVectorMode) arg_=
-    (let l__48 = arg_ in
-   if (((l__48 = (( 0 : int):ii)))) then TV_Direct
-   else if (((l__48 = (( 1 : int):ii)))) then TV_Vector
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then TV_Direct
+   else if (((p0_ = (( 1 : int):ii)))) then TV_Vector
    else TV_Reserved))`;
 
 
@@ -617,23 +772,23 @@ val _ = Define `
 (*val not_implemented : forall 'a. string -> M 'a*)
 
 val _ = Define `
- ((not_implemented:string ->(regstate)state_monad$sequential_state ->(('a,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) message=  (state_monad$throwS (Error_not_implemented message)))`;
+ ((not_implemented:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) message=  (sail2_state_monad$throwS (Error_not_implemented message)))`;
 
 
 (*val internal_error : forall 'a. string -> M 'a*)
 
 val _ = Define `
- ((internal_error:string ->(regstate)state_monad$sequential_state ->(('a,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) s=  (state_monad$seqS (state_monad$assert_expS F s) (state_monad$throwS (Error_internal_error () ))))`;
+ ((internal_error:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=  (sail2_state_monad$seqS (sail2_state_monad$assert_expS F s) (sail2_state_monad$throwS (Error_internal_error () ))))`;
 
 
 (*val ExtStatus_of_num : integer -> ExtStatus*)
 
 val _ = Define `
  ((ExtStatus_of_num:int -> ExtStatus) arg_=
-    (let l__45 = arg_ in
-   if (((l__45 = (( 0 : int):ii)))) then Off
-   else if (((l__45 = (( 1 : int):ii)))) then Initial
-   else if (((l__45 = (( 2 : int):ii)))) then Clean
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Off
+   else if (((p0_ = (( 1 : int):ii)))) then Initial
+   else if (((p0_ = (( 2 : int):ii)))) then Clean
    else Dirty))`;
 
 
@@ -671,9 +826,9 @@ val _ = Define `
 
 val _ = Define `
  ((SATPMode_of_num:int -> SATPMode) arg_=
-    (let l__43 = arg_ in
-   if (((l__43 = (( 0 : int):ii)))) then Sbare
-   else if (((l__43 = (( 1 : int):ii)))) then Sv32
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Sbare
+   else if (((p0_ = (( 1 : int):ii)))) then Sv32
    else Sv39))`;
 
 
@@ -687,15 +842,28 @@ val _ = Define `
 
 val _ = Define `
  ((satpMode_of_bits:Architecture ->(4)words$word ->(SATPMode)option) (a : Architecture) (m : satp_mode)= 
-  ((case (a, m) of   (g__113, b__0) => SOME Sbare )))`;
+  ((case (a, m) of
+         (g__33, b__0) =>
+   if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then SOME Sbare
+   else
+     (case (g__33, b__0) of
+           (RV32, b__1) =>
+     if (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then
+       SOME Sv32 else (case (RV32, b__1) of   (g__34, g__35) => NONE )
+       | (RV64, b__2) =>
+     if (((b__2 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then
+       SOME Sv39 else (case (RV64, b__2) of   (g__34, g__35) => NONE )
+       | (g__34, g__35) => NONE
+     )
+   )))`;
 
 
 (*val uop_of_num : integer -> uop*)
 
 val _ = Define `
  ((uop_of_num:int -> uop) arg_=
-    (let l__42 = arg_ in
-   if (((l__42 = (( 0 : int):ii)))) then RISCV_LUI
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RISCV_LUI
    else RISCV_AUIPC))`;
 
 
@@ -709,12 +877,12 @@ val _ = Define `
 
 val _ = Define `
  ((bop_of_num:int -> bop) arg_=
-    (let l__37 = arg_ in
-   if (((l__37 = (( 0 : int):ii)))) then RISCV_BEQ
-   else if (((l__37 = (( 1 : int):ii)))) then RISCV_BNE
-   else if (((l__37 = (( 2 : int):ii)))) then RISCV_BLT
-   else if (((l__37 = (( 3 : int):ii)))) then RISCV_BGE
-   else if (((l__37 = (( 4 : int):ii)))) then RISCV_BLTU
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RISCV_BEQ
+   else if (((p0_ = (( 1 : int):ii)))) then RISCV_BNE
+   else if (((p0_ = (( 2 : int):ii)))) then RISCV_BLT
+   else if (((p0_ = (( 3 : int):ii)))) then RISCV_BGE
+   else if (((p0_ = (( 4 : int):ii)))) then RISCV_BLTU
    else RISCV_BGEU))`;
 
 
@@ -736,12 +904,12 @@ val _ = Define `
 
 val _ = Define `
  ((iop_of_num:int -> iop) arg_=
-    (let l__32 = arg_ in
-   if (((l__32 = (( 0 : int):ii)))) then RISCV_ADDI
-   else if (((l__32 = (( 1 : int):ii)))) then RISCV_SLTI
-   else if (((l__32 = (( 2 : int):ii)))) then RISCV_SLTIU
-   else if (((l__32 = (( 3 : int):ii)))) then RISCV_XORI
-   else if (((l__32 = (( 4 : int):ii)))) then RISCV_ORI
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDI
+   else if (((p0_ = (( 1 : int):ii)))) then RISCV_SLTI
+   else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLTIU
+   else if (((p0_ = (( 3 : int):ii)))) then RISCV_XORI
+   else if (((p0_ = (( 4 : int):ii)))) then RISCV_ORI
    else RISCV_ANDI))`;
 
 
@@ -763,9 +931,9 @@ val _ = Define `
 
 val _ = Define `
  ((sop_of_num:int -> sop) arg_=
-    (let l__30 = arg_ in
-   if (((l__30 = (( 0 : int):ii)))) then RISCV_SLLI
-   else if (((l__30 = (( 1 : int):ii)))) then RISCV_SRLI
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RISCV_SLLI
+   else if (((p0_ = (( 1 : int):ii)))) then RISCV_SRLI
    else RISCV_SRAI))`;
 
 
@@ -780,16 +948,16 @@ val _ = Define `
 
 val _ = Define `
  ((rop_of_num:int -> rop) arg_=
-    (let l__21 = arg_ in
-   if (((l__21 = (( 0 : int):ii)))) then RISCV_ADD
-   else if (((l__21 = (( 1 : int):ii)))) then RISCV_SUB
-   else if (((l__21 = (( 2 : int):ii)))) then RISCV_SLL
-   else if (((l__21 = (( 3 : int):ii)))) then RISCV_SLT
-   else if (((l__21 = (( 4 : int):ii)))) then RISCV_SLTU
-   else if (((l__21 = (( 5 : int):ii)))) then RISCV_XOR
-   else if (((l__21 = (( 6 : int):ii)))) then RISCV_SRL
-   else if (((l__21 = (( 7 : int):ii)))) then RISCV_SRA
-   else if (((l__21 = (( 8 : int):ii)))) then RISCV_OR
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RISCV_ADD
+   else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUB
+   else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLL
+   else if (((p0_ = (( 3 : int):ii)))) then RISCV_SLT
+   else if (((p0_ = (( 4 : int):ii)))) then RISCV_SLTU
+   else if (((p0_ = (( 5 : int):ii)))) then RISCV_XOR
+   else if (((p0_ = (( 6 : int):ii)))) then RISCV_SRL
+   else if (((p0_ = (( 7 : int):ii)))) then RISCV_SRA
+   else if (((p0_ = (( 8 : int):ii)))) then RISCV_OR
    else RISCV_AND))`;
 
 
@@ -815,11 +983,11 @@ val _ = Define `
 
 val _ = Define `
  ((ropw_of_num:int -> ropw) arg_=
-    (let l__17 = arg_ in
-   if (((l__17 = (( 0 : int):ii)))) then RISCV_ADDW
-   else if (((l__17 = (( 1 : int):ii)))) then RISCV_SUBW
-   else if (((l__17 = (( 2 : int):ii)))) then RISCV_SLLW
-   else if (((l__17 = (( 3 : int):ii)))) then RISCV_SRLW
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDW
+   else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUBW
+   else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLLW
+   else if (((p0_ = (( 3 : int):ii)))) then RISCV_SRLW
    else RISCV_SRAW))`;
 
 
@@ -840,15 +1008,15 @@ val _ = Define `
 
 val _ = Define `
  ((amoop_of_num:int -> amoop) arg_=
-    (let l__9 = arg_ in
-   if (((l__9 = (( 0 : int):ii)))) then AMOSWAP
-   else if (((l__9 = (( 1 : int):ii)))) then AMOADD
-   else if (((l__9 = (( 2 : int):ii)))) then AMOXOR
-   else if (((l__9 = (( 3 : int):ii)))) then AMOAND
-   else if (((l__9 = (( 4 : int):ii)))) then AMOOR
-   else if (((l__9 = (( 5 : int):ii)))) then AMOMIN
-   else if (((l__9 = (( 6 : int):ii)))) then AMOMAX
-   else if (((l__9 = (( 7 : int):ii)))) then AMOMINU
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then AMOSWAP
+   else if (((p0_ = (( 1 : int):ii)))) then AMOADD
+   else if (((p0_ = (( 2 : int):ii)))) then AMOXOR
+   else if (((p0_ = (( 3 : int):ii)))) then AMOAND
+   else if (((p0_ = (( 4 : int):ii)))) then AMOOR
+   else if (((p0_ = (( 5 : int):ii)))) then AMOMIN
+   else if (((p0_ = (( 6 : int):ii)))) then AMOMAX
+   else if (((p0_ = (( 7 : int):ii)))) then AMOMINU
    else AMOMAXU))`;
 
 
@@ -873,9 +1041,9 @@ val _ = Define `
 
 val _ = Define `
  ((csrop_of_num:int -> csrop) arg_=
-    (let l__7 = arg_ in
-   if (((l__7 = (( 0 : int):ii)))) then CSRRW
-   else if (((l__7 = (( 1 : int):ii)))) then CSRRS
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then CSRRW
+   else if (((p0_ = (( 1 : int):ii)))) then CSRRS
    else CSRRC))`;
 
 
@@ -889,10 +1057,10 @@ val _ = Define `
 
 val _ = Define `
  ((word_width_of_num:int -> word_width) arg_=
-    (let l__4 = arg_ in
-   if (((l__4 = (( 0 : int):ii)))) then BYTE
-   else if (((l__4 = (( 1 : int):ii)))) then HALF
-   else if (((l__4 = (( 2 : int):ii)))) then WORD
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then BYTE
+   else if (((p0_ = (( 1 : int):ii)))) then HALF
+   else if (((p0_ = (( 2 : int):ii)))) then WORD
    else DOUBLE))`;
 
 
@@ -903,282 +1071,1001 @@ val _ = Define `
     ((case arg_ of   BYTE => (( 0 : int):ii) | HALF => (( 1 : int):ii) | WORD => (( 2 : int):ii) | DOUBLE => (( 3 : int):ii) )))`;
 
 
-(*val is_aligned_addr : mword ty64 -> integer -> bool*)
+(*val reg_name_forwards : mword ty5 -> string*)
 
 val _ = Define `
- ((is_aligned_addr:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
-    (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):ii)))`;
+ ((reg_name_forwards:(5)words$word -> string) arg_=
+    (let p0_ = arg_ in
+   if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))
+   then
+     "zero"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) then
+     "ra"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) then
+     "sp"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) then
+     "gp"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) then
+     "tp"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))))) then
+     "t0"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))))) then
+     "t1"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))))) then
+     "t2"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) then
+     "fp"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))))) then
+     "s1"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))))) then
+     "a0"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))))) then
+     "a1"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) then
+     "a2"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))))) then
+     "a3"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))))) then
+     "a4"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))))) then
+     "a5"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) then
+     "a6"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))))) then
+     "a7"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)))))) then
+     "s2"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)))))) then
+     "s3"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) then
+     "s4"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1]  :  5 words$word)))))) then
+     "s5"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0]  :  5 words$word)))))) then
+     "s6"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1]  :  5 words$word)))))) then
+     "s7"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) then
+     "s8"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1]  :  5 words$word)))))) then
+     "s9"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))))) then
+     "s10"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))))) then
+     "s11"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) then
+     "t3"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))))) then
+     "t4"
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))))) then
+     "t5"
+   else "t6"))`;
 
 
-(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val reg_name_backwards : string -> mword ty5*)
 
 val _ = Define `
- ((checked_mem_read:ReadType ->(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int)=  (state_monad$bindS
-   (RISCV_read addr width  : ( ( 'int8_times_n words$word)option) M) (\ (w__0 :
-      ( 'int8_times_n words$word)option) . 
-   state_monad$returnS ((case (t, w__0) of
-     (Instruction, NONE) => MemException E_Fetch_Access_Fault
-   | (Data, NONE) => MemException E_Load_Access_Fault
-   | (_, SOME (v)) => MemValue v
-   )))))`;
+ ((reg_name_backwards:string ->(5)words$word) arg_=
+    ((case arg_ of
+     "zero" => (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+   | "ra" => (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)
+   | "sp" => (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)
+   | "gp" => (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)
+   | "tp" => (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)
+   | "t0" => (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)
+   | "t1" => (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)
+   | "t2" => (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)
+   | "fp" => (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)
+   | "s1" => (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)
+   | "a0" => (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)
+   | "a1" => (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)
+   | "a2" => (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)
+   | "a3" => (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)
+   | "a4" => (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)
+   | "a5" => (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)
+   | "a6" => (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)
+   | "a7" => (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)
+   | "s2" => (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)
+   | "s3" => (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)
+   | "s4" => (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)
+   | "s5" => (vec_of_bits [B1;B0;B1;B0;B1]  :  5 words$word)
+   | "s6" => (vec_of_bits [B1;B0;B1;B1;B0]  :  5 words$word)
+   | "s7" => (vec_of_bits [B1;B0;B1;B1;B1]  :  5 words$word)
+   | "s8" => (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)
+   | "s9" => (vec_of_bits [B1;B1;B0;B0;B1]  :  5 words$word)
+   | "s10" => (vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)
+   | "s11" => (vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)
+   | "t3" => (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)
+   | "t4" => (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)
+   | "t5" => (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)
+   | "t6" => (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)
+   )))`;
 
 
-(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val reg_name_forwards_matches : mword ty5 -> bool*)
 
-(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+val _ = Define `
+ ((reg_name_forwards_matches:(5)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))
+   then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))))) then
+     T
+   else F))`;
+
+
+(*val reg_name_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((reg_name_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "zero" => T
+   | "ra" => T
+   | "sp" => T
+   | "gp" => T
+   | "tp" => T
+   | "t0" => T
+   | "t1" => T
+   | "t2" => T
+   | "fp" => T
+   | "s1" => T
+   | "a0" => T
+   | "a1" => T
+   | "a2" => T
+   | "a3" => T
+   | "a4" => T
+   | "a5" => T
+   | "a6" => T
+   | "a7" => T
+   | "s2" => T
+   | "s3" => T
+   | "s4" => T
+   | "s5" => T
+   | "s6" => T
+   | "s7" => T
+   | "s8" => T
+   | "s9" => T
+   | "s10" => T
+   | "s11" => T
+   | "t3" => T
+   | "t4" => T
+   | "t5" => T
+   | "t6" => T
+   | _ => F
+   )))`;
 
-(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))*)
+
+val _ = Define `
+ ((reg_name_matches_prefix:string ->((5)words$word#int)option) arg_=
+    (let stringappend_1814_0 = arg_ in
+   if (((((string_startswith stringappend_1814_0 "zero")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "zero")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "zero")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "ra")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "ra")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "ra")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "sp")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "sp")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "sp")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "gp")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "gp")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "gp")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "tp")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "tp")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "tp")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t0")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t0")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t0")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t1")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t1")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t1")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t2")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t2")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t2")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "fp")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "fp")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "fp")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s1")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s1")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s1")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a0")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a0")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a0")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a1")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a1")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a1")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a2")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a2")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a2")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a3")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a3")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a3")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a4")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a4")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a4")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a5")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a5")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a5")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a6")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a6")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a6")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "a7")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "a7")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "a7")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s2")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s2")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s2")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s3")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s3")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s3")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s4")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s4")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s4")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s5")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s5")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s5")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s6")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s6")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s6")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s7")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s7")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s7")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s8")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s8")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s8")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s9")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s9")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s9")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s10")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s10")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s10")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "s11")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "s11")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "s11")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t3")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t3")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t3")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t4")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t4")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t4")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t5")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t5")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t5")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1814_0 "t6")) /\ (
+  (case ((string_drop stringappend_1814_0 ((string_length "t6")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1814_0 ((string_length "t6")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
-(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val sep_forwards : unit -> string*)
 
 val _ = Define `
- ((MEMr:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=  ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+ ((sep_forwards:unit -> string) arg_=
+    ((case arg_ of
+     ()  =>
+      string_append ((opt_spc_forwards () ))
+        ((string_append "," ((string_append ((def_spc_forwards () )) ""))))
+   )))`;
+
+
+(*val sep_backwards : string -> unit*)
+
+val _ = Define `
+ ((sep_backwards:string -> unit) arg_=
+    (let stringappend_1807_0 = arg_ in  
+  (case
+  (case ((opt_spc_matches_prefix stringappend_1807_0)) of
+        SOME (stringappend_1808_0,stringappend_1809_0) => (stringappend_1808_0, stringappend_1809_0)
+  ) of
+      (() , stringappend_1809_0) =>
+  let stringappend_1810_0 = (string_drop stringappend_1807_0
+                               stringappend_1809_0) in
+  let stringappend_1811_0 = (string_drop stringappend_1810_0
+                               ((string_length ","))) in
+  (case
+  (case ((opt_spc_matches_prefix stringappend_1811_0)) of
+        SOME (stringappend_1812_0,stringappend_1813_0) => (stringappend_1812_0, stringappend_1813_0)
+  ) of
+      (() , stringappend_1813_0) =>
+  (case ((string_drop stringappend_1811_0 stringappend_1813_0)) of
+        "" => () 
+  )
+  )
+  )))`;
+
+
+(*val sep_forwards_matches : unit -> bool*)
+
+val _ = Define `
+ ((sep_forwards_matches:unit -> bool) arg_= 
+  ((case arg_ of   ()  => T )))`;
+
+
+(*val sep_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((sep_backwards_matches:string -> bool) arg_=
+    (let stringappend_1800_0 = arg_ in
+   if ((case ((opt_spc_matches_prefix stringappend_1800_0)) of
+       SOME (stringappend_1801_0,stringappend_1802_0) =>
+        let stringappend_1803_0 = (string_drop stringappend_1800_0 stringappend_1802_0) in
+        if (((((string_startswith stringappend_1803_0 ",")) /\ (let stringappend_1804_0 = (string_drop stringappend_1803_0 ((string_length ","))) in
+               if ((case ((opt_spc_matches_prefix stringappend_1804_0)) of
+                   SOME (stringappend_1805_0,stringappend_1806_0) =>
+                    (case ((string_drop stringappend_1804_0 stringappend_1806_0)) of
+                      "" => T
+                    | _ => F
+                    )
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+          T
+        else F
+     | NONE => F
+     )) then  (case
+ (case ((opt_spc_matches_prefix stringappend_1800_0)) of
+       SOME (stringappend_1801_0,stringappend_1802_0) =>
+ (stringappend_1801_0, stringappend_1802_0)
+ ) of
+     (() , stringappend_1802_0) =>
+ let stringappend_1803_0 = (string_drop stringappend_1800_0
+                              stringappend_1802_0) in
+ let stringappend_1804_0 = (string_drop stringappend_1803_0
+                              ((string_length ","))) in
+ (case
+ (case ((opt_spc_matches_prefix stringappend_1804_0)) of
+       SOME (stringappend_1805_0,stringappend_1806_0) =>
+ (stringappend_1805_0, stringappend_1806_0)
+ ) of
+     (() , stringappend_1806_0) =>
+ (case ((string_drop stringappend_1804_0 stringappend_1806_0)) of   "" => T )
+ )
+ )
+   else F))`;
+
+
+(*val sep_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((sep_matches_prefix:string ->(unit#int)option) arg_=
+    (let stringappend_1793_0 = arg_ in
+   if ((case ((opt_spc_matches_prefix stringappend_1793_0)) of
+       SOME (stringappend_1794_0,stringappend_1795_0) =>
+        let stringappend_1796_0 = (string_drop stringappend_1793_0 stringappend_1795_0) in
+        if (((((string_startswith stringappend_1796_0 ",")) /\ (let stringappend_1797_0 = (string_drop stringappend_1796_0 ((string_length ","))) in
+               if ((case ((opt_spc_matches_prefix stringappend_1797_0)) of
+                   SOME (stringappend_1798_0,stringappend_1799_0) => 
+  (case ((string_drop stringappend_1797_0 stringappend_1799_0)) of   s_ => T )
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+          T
+        else F
+     | NONE => F
+     )) then  (case
+ (case ((opt_spc_matches_prefix stringappend_1793_0)) of
+       SOME (stringappend_1794_0,stringappend_1795_0) =>
+ (stringappend_1794_0, stringappend_1795_0)
+ ) of
+     (() , stringappend_1795_0) =>
+ let stringappend_1796_0 = (string_drop stringappend_1793_0
+                              stringappend_1795_0) in
+ let stringappend_1797_0 = (string_drop stringappend_1796_0
+                              ((string_length ","))) in
+ (case
+ (case ((opt_spc_matches_prefix stringappend_1797_0)) of
+       SOME (stringappend_1798_0,stringappend_1799_0) =>
+ (stringappend_1798_0, stringappend_1799_0)
+ ) of
+     (() , stringappend_1799_0) =>
+ (case ((string_drop stringappend_1797_0 stringappend_1799_0)) of
+       s_ => SOME (() , ((string_length arg_)) - ((string_length s_)))
+ )
+ )
+ )
+   else NONE))`;
 
 
+(*val bool_bits_forwards : bool -> mword ty1*)
+
 val _ = Define `
- ((MEMr_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=
-    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+ ((bool_bits_forwards:bool ->(1)words$word) arg_=
+    ((case arg_ of
+     T => (vec_of_bits [B1]  :  1 words$word)
+   | F => (vec_of_bits [B0]  :  1 words$word)
+   )))`;
 
 
+(*val bool_bits_backwards : mword ty1 -> bool*)
+
 val _ = Define `
- ((MEMr_strong_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=
-    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+ ((bool_bits_backwards:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else F))`;
+
 
+(*val bool_bits_forwards_matches : bool -> bool*)
 
 val _ = Define `
- ((MEMr_reserved:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=
-    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+ ((bool_bits_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   T => T | F => T )))`;
+
 
+(*val bool_bits_backwards_matches : mword ty1 -> bool*)
 
 val _ = Define `
- ((MEMr_reserved_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=
-    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+ ((bool_bits_backwards_matches:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else F))`;
 
 
+(*val bool_not_bits_forwards : bool -> mword ty1*)
+
 val _ = Define `
- ((MEMr_reserved_strong_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width=
-    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+ ((bool_not_bits_forwards:bool ->(1)words$word) arg_=
+    ((case arg_ of
+     T => (vec_of_bits [B0]  :  1 words$word)
+   | F => (vec_of_bits [B1]  :  1 words$word)
+   )))`;
 
 
-(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val bool_not_bits_backwards : mword ty1 -> bool*)
 
 val _ = Define `
- ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width aq rl res=
-    (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then
-     state_monad$returnS (MemException E_Load_Addr_Align)
-   else
-     (case (aq, rl, res) of
-       (F, F, F) => (MEMr addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
-     | (T, F, F) => (MEMr_acquire addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
-     | (F, F, T) =>
-        (MEMr_reserved addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
-     | (T, F, T) =>
-        (MEMr_reserved_acquire addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
-     | (F, T, F) => state_monad$throwS (Error_not_implemented "load.rl")
-     | (T, T, F) =>
-        (MEMr_strong_acquire addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
-     | (F, T, T) => state_monad$throwS (Error_not_implemented "lr.rl")
-     | (T, T, T) =>
-        (MEMr_reserved_strong_acquire addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
-     )))`;
+ ((bool_not_bits_backwards:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else F))`;
 
 
-(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+(*val bool_not_bits_forwards_matches : bool -> bool*)
 
 val _ = Define `
- ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width aq rl con=
-    (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
-     state_monad$returnS (MemException E_SAMO_Addr_Align)
-   else
-     (case (aq, rl, con) of
-       (F, F, F) => state_monad$seqS (MEMea addr width) (state_monad$returnS (MemValue () ))
-     | (F, T, F) => state_monad$seqS (MEMea_release addr width) (state_monad$returnS (MemValue () ))
-     | (F, F, T) => state_monad$seqS (MEMea_conditional addr width) (state_monad$returnS (MemValue () ))
-     | (F, T, T) => state_monad$seqS (MEMea_conditional_release addr width) (state_monad$returnS (MemValue () ))
-     | (T, F, F) => state_monad$throwS (Error_not_implemented "store.aq")
-     | (T, T, F) => state_monad$seqS (MEMea_strong_release addr width) (state_monad$returnS (MemValue () ))
-     | (T, F, T) => state_monad$throwS (Error_not_implemented "sc.aq")
-     | (T, T, T) => state_monad$seqS (MEMea_conditional_strong_release addr width) (state_monad$returnS (MemValue () ))
-     )))`;
+ ((bool_not_bits_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   T => T | F => T )))`;
 
 
-(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+(*val bool_not_bits_backwards_matches : mword ty1 -> bool*)
 
 val _ = Define `
- ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)=  (state_monad$bindS
-   (RISCV_write addr width data) (\ (w__0 : bool) . 
-   state_monad$returnS (if w__0 then MemValue () 
-           else MemException E_SAMO_Access_Fault))))`;
+ ((bool_not_bits_backwards_matches:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else F))`;
+
 
+(*val size_bits_forwards : word_width -> mword ty2*)
 
-(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+val _ = Define `
+ ((size_bits_forwards:word_width ->(2)words$word) arg_=
+    ((case arg_ of
+     BYTE => (vec_of_bits [B0;B0]  :  2 words$word)
+   | HALF => (vec_of_bits [B0;B1]  :  2 words$word)
+   | WORD => (vec_of_bits [B1;B0]  :  2 words$word)
+   | DOUBLE => (vec_of_bits [B1;B1]  :  2 words$word)
+   )))`;
 
-(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+(*val size_bits_backwards : mword ty2 -> word_width*)
 
-(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+val _ = Define `
+ ((size_bits_backwards:(2)words$word -> word_width) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0]  :  2 words$word)))) then BYTE
+   else if (((p0_ = (vec_of_bits [B0;B1]  :  2 words$word)))) then HALF
+   else if (((p0_ = (vec_of_bits [B1;B0]  :  2 words$word)))) then WORD
+   else DOUBLE))`;
 
-(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+(*val size_bits_forwards_matches : word_width -> bool*)
 
 val _ = Define `
- ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+ ((size_bits_forwards_matches:word_width -> bool) arg_= 
+  ((case arg_ of   BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`;
+
 
+(*val size_bits_backwards_matches : mword ty2 -> bool*)
 
 val _ = Define `
- ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+ ((size_bits_backwards_matches:(2)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0]  :  2 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B1]  :  2 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0]  :  2 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B1]  :  2 words$word)))) then T
+   else F))`;
+
 
+(*val size_mnemonic_forwards : word_width -> string*)
 
 val _ = Define `
- ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+ ((size_mnemonic_forwards:word_width -> string) arg_=
+    ((case arg_ of   BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" )))`;
 
 
+(*val size_mnemonic_backwards : string -> word_width*)
+
 val _ = Define `
- ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+ ((size_mnemonic_backwards:string -> word_width) arg_=
+    ((case arg_ of   "b" => BYTE | "h" => HALF | "w" => WORD | "d" => DOUBLE )))`;
+
 
+(*val size_mnemonic_forwards_matches : word_width -> bool*)
 
 val _ = Define `
- ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+ ((size_mnemonic_forwards_matches:word_width -> bool) arg_= 
+  ((case arg_ of   BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`;
 
 
+(*val size_mnemonic_backwards_matches : string -> bool*)
+
 val _ = Define `
- ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+ ((size_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of   "b" => T | "h" => T | "w" => T | "d" => T | _ => F )))`;
 
 
-(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+(*val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))*)
 
 val _ = Define `
- ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width value aq rl con=
-    (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
-     state_monad$returnS (MemException E_SAMO_Addr_Align)
-   else
-     (case (aq, rl, con) of
-       (F, F, F) => MEMval addr width value
-     | (F, T, F) => MEMval_release addr width value
-     | (F, F, T) => MEMval_conditional addr width value
-     | (F, T, T) => MEMval_conditional_release addr width value
-     | (T, F, F) => state_monad$throwS (Error_not_implemented "store.aq")
-     | (T, T, F) => MEMval_strong_release addr width value
-     | (T, F, T) => state_monad$throwS (Error_not_implemented "sc.aq")
-     | (T, T, T) => MEMval_conditional_strong_release addr width value
-     )))`;
+ ((size_mnemonic_matches_prefix:string ->(word_width#int)option) arg_=
+    (let stringappend_1789_0 = arg_ in
+   if (((((string_startswith stringappend_1789_0 "b")) /\ (
+  (case ((string_drop stringappend_1789_0 ((string_length "b")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1789_0 ((string_length "b")))) of
+       s_ => SOME (BYTE, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1789_0 "h")) /\ (
+  (case ((string_drop stringappend_1789_0 ((string_length "h")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1789_0 ((string_length "h")))) of
+       s_ => SOME (HALF, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1789_0 "w")) /\ (
+  (case ((string_drop stringappend_1789_0 ((string_length "w")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1789_0 ((string_length "w")))) of
+       s_ => SOME (WORD, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1789_0 "d")) /\ (
+  (case ((string_drop stringappend_1789_0 ((string_length "d")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1789_0 ((string_length "d")))) of
+       s_ => SOME (DOUBLE, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val Mk_Misa : mword ty64 -> Misa*)
+
+val _ = Define `
+ ((Mk_Misa:(64)words$word -> Misa) v=  (<| Misa_Misa_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Misa_bits : Misa -> mword ty64*)
+
+val _ = Define `
+ ((get_Misa_bits:Misa ->(64)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _get_Misa : Misa -> mword ty64*)
+(*val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Misa:Misa ->(64)words$word) (Mk_Misa (v))=  v)`;
+ ((set_Misa_bits:((regstate),(register_value),(Misa))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*)
+(*val _update_Misa_bits : Misa -> mword ty64 -> Misa*)
 
 val _ = Define `
- ((set_Misa:((regstate),(register_value),(Misa))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Misa v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Misa_bits:Misa ->(64)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
 
+(*val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE*)
 
-(*val _get_SV39_PTE : SV39_PTE -> mword ty64*)
+(*val _get_SV39_PTE_bits : SV39_PTE -> mword ty64*)
 
-(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*)
+(*val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*)
 
 (*val _get_Misa_MXL : Misa -> mword ty2*)
 
 val _ = Define `
- ((get_Misa_MXL:Misa ->(2)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))`;
+ ((get_Misa_MXL:Misa ->(2)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 62 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*)
 
 val _ = Define `
- ((update_Misa_MXL:Misa ->(2)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_MXL:Misa ->(2)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_Z : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_Z:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_Z:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 25 : int):ii) (( 25 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_Z : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_Z:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 25 : int):ii) (( 25 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_Z:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_Y : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_Y:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 24 : int):ii) (( 24 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_Y:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 24 : int):ii) (( 24 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_Y : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_Y:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 24 : int):ii) (( 24 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_Y:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_X : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_X:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_X:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 23 : int):ii) (( 23 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_X : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_X:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_X:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1190,24 +2077,32 @@ val _ = Define `
 (*val _get_Misa_W : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_W:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_W:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_W : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_W:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_W:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1219,24 +2114,32 @@ val _ = Define `
 (*val _get_Misa_V : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_V:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_V:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 21 : int):ii) (( 21 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_V : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_V:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_V:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1248,24 +2151,32 @@ val _ = Define `
 (*val _get_Misa_U : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_U:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_U:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 20 : int):ii) (( 20 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_U : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_U:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_U:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1277,70 +2188,94 @@ val _ = Define `
 (*val _get_Misa_T : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_T:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_T:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_T : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_T:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_T:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_S : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_S:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_S:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_S : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_S:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_S:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_R : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_R:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_R:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 17 : int):ii) (( 17 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_R : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_R:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_R:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1352,254 +2287,342 @@ val _ = Define `
 (*val _get_Misa_Q : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_Q:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 16 : int):ii) (( 16 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_Q:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 16 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_Q : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_Q:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 16 : int):ii) (( 16 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_Q:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_P : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_P:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_P:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 15 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_P : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_P:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_P:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_O : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_O:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_O:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 14 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_O : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_O:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 14 : int):ii) (( 14 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_O:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_N : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_N:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_N:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 13 : int):ii) (( 13 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_N : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_N:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_N:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_M : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_M:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_M:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 12 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_M : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_M:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_M:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_L : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_L:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_L:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 11 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_L : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_L:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_L:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_K : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_K:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_K:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 10 : int):ii) (( 10 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_K : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_K:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_K:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_J : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_J:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_J:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_J : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_J:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_J:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_I : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_I:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_I:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_I : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_I:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_I:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_H : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_H:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_H:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_H : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_H:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_H:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_G : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_G:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_G:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_G : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_G:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_G:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1611,70 +2634,94 @@ val _ = Define `
 (*val _get_Misa_F : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_F:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_F:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_F : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_F:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_F:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_E : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_E:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_E:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_E : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_E:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_E:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_D : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_D:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_D:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_D : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_D:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_D:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1686,70 +2733,94 @@ val _ = Define `
 (*val _get_Misa_C : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_C:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_C:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_C : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_C:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_C:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_B : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_B:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_B:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_B : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_B:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_B:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Misa_A : Misa -> mword ty1*)
 
 val _ = Define `
- ((get_Misa_A:Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Misa_A:Misa ->(1)words$word) v=  ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Misa) . 
-   let r = ((get_Misa w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Misa r))))`;
+ ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Misa_A : Misa -> mword ty1 -> Misa*)
 
 val _ = Define `
- ((update_Misa_A:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x=
-    (Mk_Misa ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Misa_A:Misa ->(1)words$word -> Misa) v x=
+    ((v with<|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1758,48 +2829,85 @@ val _ = Define `
 
 (*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
 
-(*val legalize_misa : Misa -> mword ty64 -> Misa*)
+(*val legalize_misa : Misa -> mword ty64 -> M Misa*)
+
+val _ = Define `
+ ((legalize_misa:Misa ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Misa),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Misa) (v : xlenbits)=
+    (let v = (Mk_Misa v) in sail2_state_monad$bindS
+   (sail2_state$and_boolS (sail2_state_monad$returnS (((((get_Misa_C v  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
+      sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 1 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))) (\ (w__1 : bool) . 
+   sail2_state_monad$returnS (if w__1 then m
+           else update_Misa_C m ((get_Misa_C v  :  1 words$word))))))`;
+
+
+(*val Mk_Mstatus : mword ty64 -> Mstatus*)
+
+val _ = Define `
+ ((Mk_Mstatus:(64)words$word -> Mstatus) v=
+    (<| Mstatus_Mstatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Mstatus_bits : Mstatus -> mword ty64*)
 
 val _ = Define `
- ((legalize_misa:Misa ->(64)words$word -> Misa) (m : Misa) (v : xlenbits)=  m)`;
+ ((get_Mstatus_bits:Mstatus ->(64)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _get_Mstatus : Mstatus -> mword ty64*)
+(*val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Mstatus:Mstatus ->(64)words$word) (Mk_Mstatus (v))=  v)`;
+ ((set_Mstatus_bits:((regstate),(register_value),(Mstatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*)
+(*val _update_Mstatus_bits : Mstatus -> mword ty64 -> Mstatus*)
 
 val _ = Define `
- ((set_Mstatus:((regstate),(register_value),(Mstatus))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Mstatus v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Mstatus_bits:Mstatus ->(64)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_SD : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_SD:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_SD:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*)
@@ -1811,47 +2919,63 @@ val _ = Define `
 (*val _get_Mstatus_SXL : Mstatus -> mword ty2*)
 
 val _ = Define `
- ((get_Mstatus_SXL:Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 35 : int):ii) (( 34 : int):ii)  :  2 words$word)))`;
+ ((get_Mstatus_SXL:Mstatus ->(2)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 35 : int):ii) (( 34 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_SXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 35 : int):ii) (( 34 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_SXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 35 : int):ii) (( 34 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 35 : int):ii) (( 34 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 35 : int):ii) (( 34 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_UXL : Mstatus -> mword ty2*)
 
 val _ = Define `
- ((get_Mstatus_UXL:Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii)  :  2 words$word)))`;
+ ((get_Mstatus_UXL:Mstatus ->(2)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_UXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 33 : int):ii) (( 32 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_UXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*)
@@ -1863,93 +2987,125 @@ val _ = Define `
 (*val _get_Mstatus_TSR : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_TSR:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_TSR:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_TW : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_TW:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_TW:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 21 : int):ii) (( 21 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_TVM : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_TVM:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_TVM:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 20 : int):ii) (( 20 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_MXR : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_MXR:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_MXR:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*)
@@ -1961,24 +3117,32 @@ val _ = Define `
 (*val _get_Mstatus_SUM : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_SUM:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_SUM:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*)
@@ -1990,47 +3154,63 @@ val _ = Define `
 (*val _get_Mstatus_MPRV : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_MPRV:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_MPRV:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 17 : int):ii) (( 17 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_XS : Mstatus -> mword ty2*)
 
 val _ = Define `
- ((get_Mstatus_XS:Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii)  :  2 words$word)))`;
+ ((get_Mstatus_XS:Mstatus ->(2)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 15 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*)
@@ -2042,24 +3222,32 @@ val _ = Define `
 (*val _get_Mstatus_FS : Mstatus -> mword ty2*)
 
 val _ = Define `
- ((get_Mstatus_FS:Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)))`;
+ ((get_Mstatus_FS:Mstatus ->(2)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 13 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*)
@@ -2071,47 +3259,63 @@ val _ = Define `
 (*val _get_Mstatus_MPP : Mstatus -> mword ty2*)
 
 val _ = Define `
- ((get_Mstatus_MPP:Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 12 : int):ii) (( 11 : int):ii)  :  2 words$word)))`;
+ ((get_Mstatus_MPP:Mstatus ->(2)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 11 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 12 : int):ii) (( 11 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_SPP : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_SPP:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_SPP:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*)
@@ -2123,47 +3327,63 @@ val _ = Define `
 (*val _get_Mstatus_MPIE : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_MPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_MPIE:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_SPIE : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_SPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_SPIE:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2175,24 +3395,32 @@ val _ = Define `
 (*val _get_Mstatus_UPIE : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_UPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_UPIE:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2204,47 +3432,63 @@ val _ = Define `
 (*val _get_Mstatus_MIE : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_MIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_MIE:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mstatus_SIE : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_SIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_SIE:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2256,24 +3500,32 @@ val _ = Define `
 (*val _get_Mstatus_UIE : Mstatus -> mword ty1*)
 
 val _ = Define `
- ((get_Mstatus_UIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Mstatus_UIE:Mstatus ->(1)words$word) v=  ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . 
-   let r = ((get_Mstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mstatus r))))`;
+ ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*)
 
 val _ = Define `
- ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x=
-    (Mk_Mstatus ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) v x=
+    ((v with<|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2304,18 +3556,18 @@ val _ = Define `
 (*val cur_Architecture : unit -> M Architecture*)
 
 val _ = Define `
- ((cur_Architecture:unit ->(regstate)state_monad$sequential_state ->(((Architecture),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  state_monad$bindS
+ ((cur_Architecture:unit ->(regstate)sail2_state_monad$sequential_state ->(((Architecture),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$bindS
    (case w__0 of
-     Machine => state_monad$bindS
-      (state_monad$read_regS misa_ref) (\ (w__1 : Misa) .  state_monad$returnS ((get_Misa_MXL w__1  :  2 words$word)))
-   | Supervisor => state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) .  state_monad$returnS ((get_Mstatus_SXL w__2  :  2 words$word)))
-   | User => state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) .  state_monad$returnS ((get_Mstatus_UXL w__3  :  2 words$word)))
+     Machine => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) .  sail2_state_monad$returnS ((get_Misa_MXL w__1  :  2 words$word)))
+   | Supervisor => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) .  sail2_state_monad$returnS ((get_Mstatus_SXL w__2  :  2 words$word)))
+   | User => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) .  sail2_state_monad$returnS ((get_Mstatus_UXL w__3  :  2 words$word)))
    ) (\ (a : arch_xlen) . 
    (case ((architecture a)) of
-     SOME (a) => state_monad$returnS a
+     SOME (a) => sail2_state_monad$returnS a
    | NONE => internal_error "Invalid current architecture"
    )))))`;
 
@@ -2323,103 +3575,160 @@ val _ = Define `
 (*val in32BitMode : unit -> M bool*)
 
 val _ = Define `
- ((in32BitMode:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) .  state_monad$returnS (((w__0 = RV32))))))`;
+ ((in32BitMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) .  sail2_state_monad$returnS (((w__0 = RV32))))))`;
 
 
 (*val haveAtomics : unit -> M bool*)
 
 val _ = Define `
- ((haveAtomics:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
-   state_monad$returnS (((((get_Misa_A w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
+ ((haveAtomics:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
+   sail2_state_monad$returnS (((((get_Misa_A w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
 
 
 (*val haveRVC : unit -> M bool*)
 
 val _ = Define `
- ((haveRVC:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
-   state_monad$returnS (((((get_Misa_C w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
+ ((haveRVC:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
+   sail2_state_monad$returnS (((((get_Misa_C w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
 
 
 (*val haveMulDiv : unit -> M bool*)
 
 val _ = Define `
- ((haveMulDiv:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
-   state_monad$returnS (((((get_Misa_M w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
+ ((haveMulDiv:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
+   sail2_state_monad$returnS (((((get_Misa_M w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
 
 
 (*val haveFP : unit -> M bool*)
 
 val _ = Define `
- ((haveFP:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =
-    (state$or_boolS
-     ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
-      state_monad$returnS (((((get_Misa_F w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))
-     ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__1 : Misa) . 
-      state_monad$returnS (((((get_Misa_D w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))))`;
+ ((haveFP:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
+      sail2_state_monad$returnS (((((get_Misa_F w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . 
+      sail2_state_monad$returnS (((((get_Misa_D w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))))`;
+
+
+(*val pc_alignment_mask : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((pc_alignment_mask:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . 
+   sail2_state_monad$returnS ((not_vec
+              ((EXTZ (( 64 : int):ii)
+                  (if (((((get_Misa_C w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+                   then
+                     (vec_of_bits [B0;B0]  :  2 words$word)
+                   else (vec_of_bits [B1;B0]  :  2 words$word))
+                 :  64 words$word))
+             :  64 words$word)))))`;
+
+
+(*val Mk_Minterrupts : mword ty64 -> Minterrupts*)
+
+val _ = Define `
+ ((Mk_Minterrupts:(64)words$word -> Minterrupts) v=
+    (<| Minterrupts_Minterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Minterrupts_bits : Minterrupts -> mword ty64*)
+
+val _ = Define `
+ ((get_Minterrupts_bits:Minterrupts ->(64)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _get_Minterrupts : Minterrupts -> mword ty64*)
+(*val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Minterrupts:Minterrupts ->(64)words$word) (Mk_Minterrupts (v))=  v)`;
+ ((set_Minterrupts_bits:((regstate),(register_value),(Minterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*)
+(*val _update_Minterrupts_bits : Minterrupts -> mword ty64 -> Minterrupts*)
 
 val _ = Define `
- ((set_Minterrupts:((regstate),(register_value),(Minterrupts))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Minterrupts v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Minterrupts_bits:Minterrupts ->(64)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 11 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2431,24 +3740,33 @@ val _ = Define `
 (*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2460,47 +3778,65 @@ val _ = Define `
 (*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Minterrupts_STI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_STI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_STI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2512,24 +3848,33 @@ val _ = Define `
 (*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2541,47 +3886,65 @@ val _ = Define `
 (*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2593,24 +3956,33 @@ val _ = Define `
 (*val _get_Minterrupts_USI : Minterrupts -> mword ty1*)
 
 val _ = Define `
- ((get_Minterrupts_USI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Minterrupts_USI:Minterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . 
-   let r = ((get_Minterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Minterrupts r))))`;
+ ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*)
 
 val _ = Define `
- ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x=
-    (Mk_Minterrupts ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+    ((v with<|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2652,160 +4024,234 @@ val _ = Define `
    update_Minterrupts_MSI m ((bool_to_bits F  :  1 words$word))))`;
 
 
-(*val _get_Medeleg : Medeleg -> mword ty64*)
+(*val Mk_Medeleg : mword ty64 -> Medeleg*)
+
+val _ = Define `
+ ((Mk_Medeleg:(64)words$word -> Medeleg) v=
+    (<| Medeleg_Medeleg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Medeleg_bits : Medeleg -> mword ty64*)
+
+val _ = Define `
+ ((get_Medeleg_bits:Medeleg ->(64)words$word) v=  ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Medeleg:Medeleg ->(64)words$word) (Mk_Medeleg (v))=  v)`;
+ ((set_Medeleg_bits:((regstate),(register_value),(Medeleg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*)
+(*val _update_Medeleg_bits : Medeleg -> mword ty64 -> Medeleg*)
 
 val _ = Define `
- ((set_Medeleg:((regstate),(register_value),(Medeleg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Medeleg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Medeleg_bits:Medeleg ->(64)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))=
-    ((subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 15 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))=
-    ((subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 13 : int):ii) (( 13 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))=
-    ((subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 12 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 10 : int):ii) (( 10 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2817,25 +4263,33 @@ val _ = Define `
 (*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))=
-    ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2847,24 +4301,33 @@ val _ = Define `
 (*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2876,25 +4339,33 @@ val _ = Define `
 (*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))=
-    ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2906,24 +4377,33 @@ val _ = Define `
 (*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2935,24 +4415,33 @@ val _ = Define `
 (*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2964,24 +4453,33 @@ val _ = Define `
 (*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2993,25 +4491,33 @@ val _ = Define `
 (*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))=
-    ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -3023,24 +4529,33 @@ val _ = Define `
 (*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*)
 
 val _ = Define `
- ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . 
-   let r = ((get_Medeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Medeleg r))))`;
+ ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
 
 val _ = Define `
- ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x=
-    (Mk_Medeleg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+    ((v with<|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -3057,65 +4572,103 @@ val _ = Define `
    update_Medeleg_MEnvCall m ((bool_to_bits F  :  1 words$word))))`;
 
 
-(*val _get_Mtvec : Mtvec -> mword ty64*)
+(*val Mk_Mtvec : mword ty64 -> Mtvec*)
 
 val _ = Define `
- ((get_Mtvec:Mtvec ->(64)words$word) (Mk_Mtvec (v))=  v)`;
+ ((Mk_Mtvec:(64)words$word -> Mtvec) v=  (<| Mtvec_Mtvec_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
-(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*)
+(*val _get_Mtvec_bits : Mtvec -> mword ty64*)
 
 val _ = Define `
- ((set_Mtvec:((regstate),(register_value),(Mtvec))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Mtvec v) in
-   state_monad$write_regS r_ref r)))`;
+ ((get_Mtvec_bits:Mtvec ->(64)words$word) v=  ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_bits:((regstate),(register_value),(Mtvec))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mtvec_Mtvec_chunk_0 :=
+         ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_bits : Mtvec -> mword ty64 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_bits:Mtvec ->(64)words$word -> Mtvec) v x=
+    ((v with<|
+     Mtvec_Mtvec_chunk_0 :=
+       ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mtvec_Base : Mtvec -> mword ty62*)
 
 val _ = Define `
- ((get_Mtvec_Base:Mtvec ->(62)words$word) (Mk_Mtvec (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word)))`;
+ ((get_Mtvec_Base:Mtvec ->(62)words$word) v=  ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii)  :  62 words$word)))`;
 
 
 (*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*)
 
 val _ = Define `
- ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(62)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mtvec) . 
-   let r = ((get_Mtvec w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 2 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mtvec r))))`;
+ ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(62)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mtvec_Mtvec_chunk_0 :=
+         ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 61 : int):ii) (( 0 : int):ii)  :  62 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*)
 
 val _ = Define `
- ((update_Mtvec_Base:Mtvec ->(62)words$word -> Mtvec) (Mk_Mtvec (v)) x=
-    (Mk_Mtvec ((update_subrange_vec_dec v (( 63 : int):ii) (( 2 : int):ii) x  :  64 words$word))))`;
+ ((update_Mtvec_Base:Mtvec ->(62)words$word -> Mtvec) v x=
+    ((v with<|
+     Mtvec_Mtvec_chunk_0 :=
+       ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 61 : int):ii) (( 0 : int):ii)  :  62 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mtvec_Mode : Mtvec -> mword ty2*)
 
 val _ = Define `
- ((get_Mtvec_Mode:Mtvec ->(2)words$word) (Mk_Mtvec (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)))`;
+ ((get_Mtvec_Mode:Mtvec ->(2)words$word) v=  ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)))`;
 
 
 (*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*)
 
 val _ = Define `
- ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mtvec) . 
-   let r = ((get_Mtvec w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mtvec r))))`;
+ ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mtvec_Mtvec_chunk_0 :=
+         ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*)
 
 val _ = Define `
- ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) (Mk_Mtvec (v)) x=
-    (Mk_Mtvec ((update_subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) v x=
+    ((v with<|
+     Mtvec_Mtvec_chunk_0 :=
+       ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*)
@@ -3136,65 +4689,104 @@ val _ = Define `
    )))`;
 
 
-(*val _get_Mcause : Mcause -> mword ty64*)
+(*val Mk_Mcause : mword ty64 -> Mcause*)
+
+val _ = Define `
+ ((Mk_Mcause:(64)words$word -> Mcause) v=  (<| Mcause_Mcause_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Mcause_bits : Mcause -> mword ty64*)
+
+val _ = Define `
+ ((get_Mcause_bits:Mcause ->(64)words$word) v=  ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Mcause:Mcause ->(64)words$word) (Mk_Mcause (v))=  v)`;
+ ((set_Mcause_bits:((regstate),(register_value),(Mcause))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mcause_Mcause_chunk_0 :=
+         ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*)
+(*val _update_Mcause_bits : Mcause -> mword ty64 -> Mcause*)
 
 val _ = Define `
- ((set_Mcause:((regstate),(register_value),(Mcause))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Mcause v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Mcause_bits:Mcause ->(64)words$word -> Mcause) v x=
+    ((v with<|
+     Mcause_Mcause_chunk_0 :=
+       ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*)
 
 val _ = Define `
- ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) (Mk_Mcause (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+ ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) v=
+    ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
 
 
 (*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mcause) . 
-   let r = ((get_Mcause w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mcause r))))`;
+ ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mcause_Mcause_chunk_0 :=
+         ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*)
 
 val _ = Define `
- ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) (Mk_Mcause (v)) x=
-    (Mk_Mcause ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x  :  64 words$word))))`;
+ ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) v x=
+    ((v with<|
+     Mcause_Mcause_chunk_0 :=
+       ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Mcause_Cause : Mcause -> mword ty63*)
 
 val _ = Define `
- ((get_Mcause_Cause:Mcause ->(63)words$word) (Mk_Mcause (v))=  ((subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii)  :  63 words$word)))`;
+ ((get_Mcause_Cause:Mcause ->(63)words$word) v=  ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii)  :  63 words$word)))`;
 
 
 (*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*)
 
 val _ = Define `
- ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(63)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Mcause) . 
-   let r = ((get_Mcause w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Mcause r))))`;
+ ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(63)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Mcause_Mcause_chunk_0 :=
+         ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii)  :  63 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*)
 
 val _ = Define `
- ((update_Mcause_Cause:Mcause ->(63)words$word -> Mcause) (Mk_Mcause (v)) x=
-    (Mk_Mcause ((update_subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Mcause_Cause:Mcause ->(63)words$word -> Mcause) v x=
+    ((v with<|
+     Mcause_Mcause_chunk_0 :=
+       ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 62 : int):ii) (( 0 : int):ii)  :  63 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*)
@@ -3223,9 +4815,9 @@ val _ = Define `
 (*val legalize_xepc : mword ty64 -> M (mword ty64)*)
 
 val _ = Define `
- ((legalize_xepc:(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) v=  (state_monad$bindS
+ ((legalize_xepc:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) v=  (sail2_state_monad$bindS
    (haveRVC () ) (\ (w__0 : bool) . 
-   state_monad$returnS ((and_vec v
+   sail2_state_monad$returnS ((and_vec v
               ((EXTS (( 64 : int):ii)
                   (if w__0 then (vec_of_bits [B1;B1;B0]  :  3 words$word)
                    else (vec_of_bits [B1;B0;B0]  :  3 words$word))
@@ -3233,219 +4825,527 @@ val _ = Define `
              :  64 words$word)))))`;
 
 
-(*val _get_Sstatus : Sstatus -> mword ty64*)
+(*val Mk_Counteren : mword ty32 -> Counteren*)
 
 val _ = Define `
- ((get_Sstatus:Sstatus ->(64)words$word) (Mk_Sstatus (v))=  v)`;
+ ((Mk_Counteren:(32)words$word -> Counteren) v=
+    (<| Counteren_Counteren_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) |>))`;
 
 
-(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*)
+(*val _get_Counteren_bits : Counteren -> mword ty32*)
 
 val _ = Define `
- ((set_Sstatus:((regstate),(register_value),(Sstatus))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Sstatus v) in
-   state_monad$write_regS r_ref r)))`;
+ ((get_Counteren_bits:Counteren ->(32)words$word) v=
+    ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)))`;
 
 
+(*val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit*)
+
 val _ = Define `
- ((get_Sstatus_SD:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
+ ((set_Counteren_bits:((regstate),(register_value),(Counteren))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
 
+(*val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren*)
 
 val _ = Define `
- ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((update_Counteren_bits:Counteren ->(32)words$word -> Counteren) v x=
+    ((v with<|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
+          :  32 words$word))|>)))`;
 
 
+(*val _get_Counteren_HPM : Counteren -> mword ty29*)
+
 val _ = Define `
- ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x  :  64 words$word))))`;
+ ((get_Counteren_HPM:Counteren ->(29)words$word) v=
+    ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)  :  29 words$word)))`;
+
 
+(*val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit*)
 
 val _ = Define `
- ((get_Sstatus_UXL:Sstatus ->(2)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii)  :  2 words$word)))`;
+ ((set_Counteren_HPM:((regstate),(register_value),(Counteren))register_ref ->(29)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 28 : int):ii) (( 0 : int):ii)  :  29 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
+(*val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren*)
+
 val _ = Define `
- ((set_Sstatus_UXL:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 33 : int):ii) (( 32 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((update_Counteren_HPM:Counteren ->(29)words$word -> Counteren) v x=
+    ((v with<|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 28 : int):ii) (( 0 : int):ii)  :  29 words$word))
+          :  32 words$word))|>)))`;
+
 
+(*val _get_Counteren_IR : Counteren -> mword ty1*)
 
 val _ = Define `
- ((update_Sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) x  :  64 words$word))))`;
+ ((get_Counteren_IR:Counteren ->(1)words$word) v=
+    ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
 
 
+(*val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
 val _ = Define `
- ((get_Sstatus_MXR:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii)  :  1 words$word)))`;
+ ((set_Counteren_IR:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
 
+(*val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren*)
 
 val _ = Define `
- ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((update_Counteren_IR:Counteren ->(1)words$word -> Counteren) v x=
+    ((v with<|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
+(*val _get_Counteren_TM : Counteren -> mword ty1*)
+
 val _ = Define `
- ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x  :  64 words$word))))`;
+ ((get_Counteren_TM:Counteren ->(1)words$word) v=
+    ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+
 
+(*val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
 
 val _ = Define `
- ((get_Sstatus_SUM:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii)  :  1 words$word)))`;
+ ((set_Counteren_TM:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
+(*val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren*)
+
 val _ = Define `
- ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((update_Counteren_TM:Counteren ->(1)words$word -> Counteren) v x=
+    ((v with<|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
+
 
+(*val _get_Counteren_CY : Counteren -> mword ty1*)
 
 val _ = Define `
- ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x  :  64 words$word))))`;
+ ((get_Counteren_CY:Counteren ->(1)words$word) v=
+    ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
+(*val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
 val _ = Define `
- ((get_Sstatus_XS:Sstatus ->(2)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii)  :  2 words$word)))`;
+ ((set_Counteren_CY:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  32 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
 
+(*val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren*)
 
 val _ = Define `
- ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 15 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((update_Counteren_CY:Counteren ->(1)words$word -> Counteren) v x=
+    ((v with<|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  32 words$word))|>)))`;
 
 
+(*val legalize_mcounteren : Counteren -> mword ty64 -> Counteren*)
+
 val _ = Define `
- ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) x  :  64 words$word))))`;
+ ((legalize_mcounteren:Counteren ->(64)words$word -> Counteren) (c : Counteren) (v : xlenbits)=
+    (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii)))  :  1 words$word))) in
+   let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii)))  :  1 words$word))) in
+   update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii)))  :  1 words$word))))`;
+
 
+(*val legalize_scounteren : Counteren -> mword ty64 -> Counteren*)
 
 val _ = Define `
- ((get_Sstatus_FS:Sstatus ->(2)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)))`;
+ ((legalize_scounteren:Counteren ->(64)words$word -> Counteren) (c : Counteren) (v : xlenbits)=
+    (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii)))  :  1 words$word))) in
+   let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii)))  :  1 words$word))) in
+   update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii)))  :  1 words$word))))`;
 
 
+(*val retire_instruction : unit -> M unit*)
+
 val _ = Define `
- ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 13 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((retire_instruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS minstret_written_ref) (\ (w__0 : bool) . 
+   if (((((bool_to_bits w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+     sail2_state_monad$write_regS minstret_written_ref F
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS minstret_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+     sail2_state_monad$write_regS minstret_ref ((add_vec_int w__1 (( 1 : int):ii)  :  64 words$word))))))`;
+
 
+(*val Mk_Sstatus : mword ty64 -> Sstatus*)
 
 val _ = Define `
- ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) x  :  64 words$word))))`;
+ ((Mk_Sstatus:(64)words$word -> Sstatus) v=
+    (<| Sstatus_Sstatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
+(*val _get_Sstatus_bits : Sstatus -> mword ty64*)
+
 val _ = Define `
- ((get_Sstatus_SPP:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Sstatus_bits:Sstatus ->(64)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
 
+(*val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((set_Sstatus_bits:((regstate),(register_value),(Sstatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
+(*val _update_Sstatus_bits : Sstatus -> mword ty64 -> Sstatus*)
+
 val _ = Define `
- ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Sstatus_bits:Sstatus ->(64)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sstatus_SPIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Sstatus_SD:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sstatus_UPIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Sstatus_UXL:Sstatus ->(2)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii)  :  2 words$word)))`;
 
 
 val _ = Define `
- ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((set_Sstatus_UXL:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sstatus_SIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Sstatus_MXR:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sstatus_UIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Sstatus_SUM:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . 
-   let r = ((get_Sstatus w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sstatus r))))`;
+ ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x=
-    (Mk_Sstatus ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
-(*val lower_mstatus : Mstatus -> Sstatus*)
+val _ = Define `
+ ((get_Sstatus_XS:Sstatus ->(2)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)  :  2 words$word)))`;
+
 
 val _ = Define `
- ((lower_mstatus:Mstatus -> Sstatus) m=
-    (let s = (Mk_Sstatus ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in
-   let s = (update_Sstatus_SD s ((get_Mstatus_SD m  :  1 words$word))) in
-   let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m  :  2 words$word))) in
-   let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m  :  1 words$word))) in
-   let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m  :  1 words$word))) in
-   let s = (update_Sstatus_XS s ((get_Mstatus_XS m  :  2 words$word))) in
-   let s = (update_Sstatus_FS s ((get_Mstatus_FS m  :  2 words$word))) in
+ ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_FS:Sstatus ->(2)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPP:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPIE:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_UPIE:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SIE:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_UIE:Sstatus ->(1)words$word) v=  ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) v x=
+    ((v with<|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val lower_mstatus : Mstatus -> Sstatus*)
+
+val _ = Define `
+ ((lower_mstatus:Mstatus -> Sstatus) m=
+    (let s = (Mk_Sstatus ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in
+   let s = (update_Sstatus_SD s ((get_Mstatus_SD m  :  1 words$word))) in
+   let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m  :  2 words$word))) in
+   let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m  :  1 words$word))) in
+   let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m  :  1 words$word))) in
+   let s = (update_Sstatus_XS s ((get_Mstatus_XS m  :  2 words$word))) in
+   let s = (update_Sstatus_FS s ((get_Mstatus_FS m  :  2 words$word))) in
    let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m  :  1 words$word))) in
    let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m  :  1 words$word))) in
    let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m  :  1 words$word))) in
@@ -3458,7 +5358,6 @@ val _ = Define `
 val _ = Define `
  ((lift_sstatus:Mstatus -> Sstatus -> Mstatus) (m : Mstatus) (s : Sstatus)=
     (let m = (update_Mstatus_SD m ((get_Sstatus_SD s  :  1 words$word))) in
-   let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s  :  2 words$word))) in
    let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s  :  1 words$word))) in
    let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s  :  1 words$word))) in
    let m = (update_Mstatus_XS m ((get_Sstatus_XS s  :  2 words$word))) in
@@ -3473,178 +5372,279 @@ val _ = Define `
 (*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*)
 
 val _ = Define `
- ((legalize_sstatus:Mstatus ->(64)words$word -> Mstatus) (m : Mstatus) (v : xlenbits)=  (lift_sstatus m (Mk_Sstatus v)))`;
+ ((legalize_sstatus:Mstatus ->(64)words$word -> Mstatus) (m : Mstatus) (v : xlenbits)=  (lift_sstatus m ((Mk_Sstatus v))))`;
+
+
+(*val Mk_Sedeleg : mword ty64 -> Sedeleg*)
+
+val _ = Define `
+ ((Mk_Sedeleg:(64)words$word -> Sedeleg) v=
+    (<| Sedeleg_Sedeleg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Sedeleg_bits : Sedeleg -> mword ty64*)
+
+val _ = Define `
+ ((get_Sedeleg_bits:Sedeleg ->(64)words$word) v=  ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _get_Sedeleg : Sedeleg -> mword ty64*)
+(*val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Sedeleg:Sedeleg ->(64)words$word) (Mk_Sedeleg (v))=  v)`;
+ ((set_Sedeleg_bits:((regstate),(register_value),(Sedeleg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*)
+(*val _update_Sedeleg_bits : Sedeleg -> mword ty64 -> Sedeleg*)
 
 val _ = Define `
- ((set_Sedeleg:((regstate),(register_value),(Sedeleg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Sedeleg v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Sedeleg_bits:Sedeleg ->(64)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=
-    ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=
-    ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=
-    ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) v=
+    ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . 
-   let r = ((get_Sedeleg w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sedeleg r))))`;
+ ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x=
-    (Mk_Sedeleg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+    ((v with<|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*)
@@ -3654,121 +5654,199 @@ val _ = Define `
     (Mk_Sedeleg ((EXTZ (( 64 : int):ii) ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii)  :  9 words$word))  :  64 words$word))))`;
 
 
-(*val _get_Sinterrupts : Sinterrupts -> mword ty64*)
+(*val Mk_Sinterrupts : mword ty64 -> Sinterrupts*)
+
+val _ = Define `
+ ((Mk_Sinterrupts:(64)words$word -> Sinterrupts) v=
+    (<| Sinterrupts_Sinterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Sinterrupts_bits : Sinterrupts -> mword ty64*)
+
+val _ = Define `
+ ((get_Sinterrupts_bits:Sinterrupts ->(64)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+(*val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Sinterrupts:Sinterrupts ->(64)words$word) (Mk_Sinterrupts (v))=  v)`;
+ ((set_Sinterrupts_bits:((regstate),(register_value),(Sinterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*)
+(*val _update_Sinterrupts_bits : Sinterrupts -> mword ty64 -> Sinterrupts*)
 
 val _ = Define `
- ((set_Sinterrupts:((regstate),(register_value),(Sinterrupts))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Sinterrupts v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Sinterrupts_bits:Sinterrupts ->(64)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
+ ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . 
-   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sinterrupts r))))`;
+ ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x=
-    (Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x  :  64 words$word))))`;
+ ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
+ ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . 
-   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sinterrupts r))))`;
+ ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x=
-    (Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . 
-   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sinterrupts r))))`;
+ ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x=
-    (Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  64 words$word))))`;
+ ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . 
-   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sinterrupts r))))`;
+ ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x=
-    (Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  64 words$word))))`;
+ ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . 
-   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sinterrupts r))))`;
+ ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x=
-    (Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  64 words$word))))`;
+ ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) v=
+    ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
 
 
 val _ = Define `
- ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . 
-   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Sinterrupts r))))`;
+ ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x=
-    (Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+    ((v with<|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*)
@@ -3855,7 +5933,7 @@ val _ = Define `
 
 val _ = Define `
  ((legalize_sip:Minterrupts -> Minterrupts ->(64)words$word -> Minterrupts) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)=
-    (lift_sip m d (Mk_Sinterrupts v)))`;
+    (lift_sip m d ((Mk_Sinterrupts v))))`;
 
 
 (*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*)
@@ -3892,85 +5970,131 @@ val _ = Define `
 
 val _ = Define `
  ((legalize_sie:Minterrupts -> Minterrupts ->(64)words$word -> Minterrupts) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)=
-    (lift_sie m d (Mk_Sinterrupts v)))`;
+    (lift_sie m d ((Mk_Sinterrupts v))))`;
+
+
+(*val Mk_Satp64 : mword ty64 -> Satp64*)
+
+val _ = Define `
+ ((Mk_Satp64:(64)words$word -> Satp64) v=  (<| Satp64_Satp64_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+(*val _get_Satp64_bits : Satp64 -> mword ty64*)
+
+val _ = Define `
+ ((get_Satp64_bits:Satp64 ->(64)words$word) v=  ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
 
 
-(*val _get_Satp64 : Satp64 -> mword ty64*)
+(*val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((get_Satp64:Satp64 ->(64)words$word) (Mk_Satp64 (v))=  v)`;
+ ((set_Satp64_bits:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
-(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*)
+(*val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64*)
 
 val _ = Define `
- ((set_Satp64:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_Satp64 v) in
-   state_monad$write_regS r_ref r)))`;
+ ((update_Satp64_bits:Satp64 ->(64)words$word -> Satp64) v x=
+    ((v with<|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
 
 
 val _ = Define `
- ((get_Satp64_Mode:Satp64 ->(4)words$word) (Mk_Satp64 (v))=  ((subrange_vec_dec v (( 63 : int):ii) (( 60 : int):ii)  :  4 words$word)))`;
+ ((get_Satp64_Mode:Satp64 ->(4)words$word) v=  ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)  :  4 words$word)))`;
 
 
 val _ = Define `
- ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . 
-   let r = ((get_Satp64 w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 60 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Satp64 r))))`;
+ ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)
+             ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 val _ = Define `
- ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) (Mk_Satp64 (v)) x=
-    (Mk_Satp64 ((update_subrange_vec_dec v (( 63 : int):ii) (( 60 : int):ii) x  :  64 words$word))))`;
+ ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) v x=
+    ((v with<|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)
+           ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii)  :  4 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Satp64_Asid : Satp64 -> mword ty16*)
 
 val _ = Define `
- ((get_Satp64_Asid:Satp64 ->(16)words$word) (Mk_Satp64 (v))=  ((subrange_vec_dec v (( 59 : int):ii) (( 44 : int):ii)  :  16 words$word)))`;
+ ((get_Satp64_Asid:Satp64 ->(16)words$word) v=  ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)  :  16 words$word)))`;
 
 
 (*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*)
 
 val _ = Define `
- ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . 
-   let r = ((get_Satp64 w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 59 : int):ii) (( 44 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Satp64 r))))`;
+ ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)
+             ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*)
 
 val _ = Define `
- ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) (Mk_Satp64 (v)) x=
-    (Mk_Satp64 ((update_subrange_vec_dec v (( 59 : int):ii) (( 44 : int):ii) x  :  64 words$word))))`;
+ ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) v x=
+    ((v with<|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)
+           ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val _get_Satp64_PPN : Satp64 -> mword ty44*)
 
 val _ = Define `
- ((get_Satp64_PPN:Satp64 ->(44)words$word) (Mk_Satp64 (v))=  ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word)))`;
+ ((get_Satp64_PPN:Satp64 ->(44)words$word) v=  ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word)))`;
 
 
 (*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*)
 
 val _ = Define `
- ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . 
-   let r = ((get_Satp64 w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 43 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_Satp64 r))))`;
+ ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
 (*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*)
 
 val _ = Define `
- ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) (Mk_Satp64 (v)) x=
-    (Mk_Satp64 ((update_subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) v x=
+    ((v with<|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word))
+          :  64 words$word))|>)))`;
 
 
 (*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*)
@@ -3981,7 +6105,7 @@ val _ = Define `
    (case ((satpMode_of_bits a ((get_Satp64_Mode s  :  4 words$word)))) of
      NONE => o1
    | SOME (Sv32) => o1
-   | SOME (_) => (get_Satp64 s  :  64 words$word)
+   | SOME (_) => (get_Satp64_bits s  :  64 words$word)
    )))`;
 
 
@@ -4070,6 +6194,10 @@ val _ = Define `
      "mtval"
    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
      "mip"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "pmpcfg0"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)))) then
+     "pmpaddr0"
    else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
      "mcycle"
    else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
@@ -4083,6 +6211,1139 @@ val _ = Define `
    else "UNKNOWN"))`;
 
 
+(*val csr_name_map_forwards : mword ty12 -> string*)
+
+val _ = Define `
+ ((csr_name_map_forwards:(12)words$word -> string) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "ustatus"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "uie"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     "utvec"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "uscratch"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "uepc"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "ucause"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "utval"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "uip"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "fflags"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "frm"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "fcsr"
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "cycle"
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "time"
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "instret"
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "cycleh"
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "timeh"
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "instreth"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "sstatus"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "sedeleg"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "sideleg"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "sie"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     "stvec"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     "scounteren"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "sscratch"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "sepc"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "scause"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "stval"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "sip"
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "satp"
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     "mvendorid"
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     "marchid"
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     "mimpid"
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     "mhartid"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mstatus"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "misa"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "medeleg"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "mideleg"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "mie"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     "mtvec"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     "mcounteren"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mscratch"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "mepc"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "mcause"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "mtval"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "mip"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "pmpcfg0"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "pmpcfg1"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "pmpcfg2"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "pmpcfg3"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)))) then
+     "pmpaddr0"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     "pmpaddr1"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     "pmpaddr2"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     "pmpaddr3"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     "pmpaddr4"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1]  :  12 words$word)))) then
+     "pmpaddr5"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0]  :  12 words$word)))) then
+     "pmpaddr6"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1]  :  12 words$word)))) then
+     "pmpaddr7"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0]  :  12 words$word)))) then
+     "pmpaddr8"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1]  :  12 words$word)))) then
+     "pmpaddr9"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0]  :  12 words$word)))) then
+     "pmpaddr10"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1]  :  12 words$word)))) then
+     "pmpaddr11"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0]  :  12 words$word)))) then
+     "pmpaddr12"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1]  :  12 words$word)))) then
+     "pmpaddr13"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0]  :  12 words$word)))) then
+     "pmpaddr14"
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1]  :  12 words$word)))) then
+     "pmpaddr15"
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mcycle"
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "minstret"
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mcycleh"
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "minstreth"
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "tselect"
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "tdata1"
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "tdata2"
+   else "tdata3"))`;
+
+
+(*val csr_name_map_backwards : string -> mword ty12*)
+
+val _ = Define `
+ ((csr_name_map_backwards:string ->(12)words$word) arg_=
+    ((case arg_ of
+     "ustatus" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "uie" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)
+   | "utvec" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)
+   | "uscratch" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "uepc" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "ucause" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "utval" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "uip" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)
+   | "fflags" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "frm" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "fcsr" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "cycle" => (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "time" => (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "instret" => (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "cycleh" => (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "timeh" => (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "instreth" => (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "sstatus" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "sedeleg" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "sideleg" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "sie" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)
+   | "stvec" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)
+   | "scounteren" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)
+   | "sscratch" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "sepc" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "scause" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "stval" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "sip" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)
+   | "satp" => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "mvendorid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)
+   | "marchid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)
+   | "mimpid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)
+   | "mhartid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)
+   | "mstatus" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "misa" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "medeleg" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "mideleg" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "mie" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)
+   | "mtvec" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)
+   | "mcounteren" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)
+   | "mscratch" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "mepc" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "mcause" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "mtval" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "mip" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)
+   | "pmpcfg0" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "pmpcfg1" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "pmpcfg2" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "pmpcfg3" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word)
+   | "pmpaddr0" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)
+   | "pmpaddr1" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1]  :  12 words$word)
+   | "pmpaddr2" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0]  :  12 words$word)
+   | "pmpaddr3" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1]  :  12 words$word)
+   | "pmpaddr4" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0]  :  12 words$word)
+   | "pmpaddr5" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1]  :  12 words$word)
+   | "pmpaddr6" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0]  :  12 words$word)
+   | "pmpaddr7" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1]  :  12 words$word)
+   | "pmpaddr8" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0]  :  12 words$word)
+   | "pmpaddr9" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1]  :  12 words$word)
+   | "pmpaddr10" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0]  :  12 words$word)
+   | "pmpaddr11" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1]  :  12 words$word)
+   | "pmpaddr12" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0]  :  12 words$word)
+   | "pmpaddr13" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1]  :  12 words$word)
+   | "pmpaddr14" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0]  :  12 words$word)
+   | "pmpaddr15" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1]  :  12 words$word)
+   | "mcycle" => (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "minstret" => (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "mcycleh" => (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "minstreth" => (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "tselect" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)
+   | "tdata1" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word)
+   | "tdata2" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word)
+   | "tdata3" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word)
+   )))`;
+
+
+(*val csr_name_map_forwards_matches : mword ty12 -> bool*)
+
+val _ = Define `
+ ((csr_name_map_forwards_matches:(12)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     T
+   else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     T
+   else F))`;
+
+
+(*val csr_name_map_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((csr_name_map_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "ustatus" => T
+   | "uie" => T
+   | "utvec" => T
+   | "uscratch" => T
+   | "uepc" => T
+   | "ucause" => T
+   | "utval" => T
+   | "uip" => T
+   | "fflags" => T
+   | "frm" => T
+   | "fcsr" => T
+   | "cycle" => T
+   | "time" => T
+   | "instret" => T
+   | "cycleh" => T
+   | "timeh" => T
+   | "instreth" => T
+   | "sstatus" => T
+   | "sedeleg" => T
+   | "sideleg" => T
+   | "sie" => T
+   | "stvec" => T
+   | "scounteren" => T
+   | "sscratch" => T
+   | "sepc" => T
+   | "scause" => T
+   | "stval" => T
+   | "sip" => T
+   | "satp" => T
+   | "mvendorid" => T
+   | "marchid" => T
+   | "mimpid" => T
+   | "mhartid" => T
+   | "mstatus" => T
+   | "misa" => T
+   | "medeleg" => T
+   | "mideleg" => T
+   | "mie" => T
+   | "mtvec" => T
+   | "mcounteren" => T
+   | "mscratch" => T
+   | "mepc" => T
+   | "mcause" => T
+   | "mtval" => T
+   | "mip" => T
+   | "pmpcfg0" => T
+   | "pmpcfg1" => T
+   | "pmpcfg2" => T
+   | "pmpcfg3" => T
+   | "pmpaddr0" => T
+   | "pmpaddr1" => T
+   | "pmpaddr2" => T
+   | "pmpaddr3" => T
+   | "pmpaddr4" => T
+   | "pmpaddr5" => T
+   | "pmpaddr6" => T
+   | "pmpaddr7" => T
+   | "pmpaddr8" => T
+   | "pmpaddr9" => T
+   | "pmpaddr10" => T
+   | "pmpaddr11" => T
+   | "pmpaddr12" => T
+   | "pmpaddr13" => T
+   | "pmpaddr14" => T
+   | "pmpaddr15" => T
+   | "mcycle" => T
+   | "minstret" => T
+   | "mcycleh" => T
+   | "minstreth" => T
+   | "tselect" => T
+   | "tdata1" => T
+   | "tdata2" => T
+   | "tdata3" => T
+   | _ => F
+   )))`;
+
+
+(*val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))*)
+
+val _ = Define `
+ ((csr_name_map_matches_prefix:string ->((12)words$word#int)option) arg_=
+    (let stringappend_1716_0 = arg_ in
+   if (((((string_startswith stringappend_1716_0 "ustatus")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "ustatus")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "ustatus")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "uie")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "uie")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "uie")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "utvec")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "utvec")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "utvec")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "uscratch")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "uscratch")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "uscratch")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "uepc")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "uepc")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "uepc")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "ucause")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "ucause")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "ucause")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "utval")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "utval")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "utval")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "uip")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "uip")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "uip")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "fflags")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "fflags")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "fflags")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "frm")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "frm")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "frm")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "fcsr")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "fcsr")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "fcsr")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "cycle")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "cycle")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "cycle")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "time")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "time")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "time")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "instret")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "instret")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "instret")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "cycleh")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "cycleh")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "cycleh")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "timeh")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "timeh")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "timeh")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "instreth")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "instreth")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "instreth")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sstatus")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sstatus")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sstatus")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sedeleg")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sedeleg")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sedeleg")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sideleg")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sideleg")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sideleg")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sie")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sie")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sie")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "stvec")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "stvec")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "stvec")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "scounteren")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "scounteren")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "scounteren")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sscratch")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sscratch")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sscratch")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sepc")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sepc")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sepc")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "scause")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "scause")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "scause")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "stval")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "stval")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "stval")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "sip")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "sip")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "sip")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "satp")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "satp")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "satp")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mvendorid")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mvendorid")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mvendorid")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "marchid")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "marchid")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "marchid")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mimpid")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mimpid")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mimpid")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mhartid")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mhartid")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mhartid")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mstatus")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mstatus")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mstatus")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "misa")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "misa")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "misa")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "medeleg")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "medeleg")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "medeleg")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mideleg")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mideleg")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mideleg")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mie")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mie")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mie")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mtvec")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mtvec")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mtvec")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mcounteren")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mcounteren")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mcounteren")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mscratch")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mscratch")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mscratch")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mepc")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mepc")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mepc")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mcause")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mcause")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mcause")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mtval")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mtval")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mtval")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mip")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mip")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mip")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpcfg0")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg0")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg0")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpcfg1")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg1")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg1")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpcfg2")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg2")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg2")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpcfg3")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg3")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg3")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr0")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr0")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr0")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr1")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr1")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr1")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr2")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr2")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr2")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr3")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr3")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr3")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr4")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr4")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr4")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr5")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr5")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr5")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr6")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr6")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr6")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr7")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr7")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr7")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr8")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr8")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr8")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr9")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr9")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr9")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr10")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr10")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr10")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr11")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr11")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr11")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr12")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr12")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr12")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr13")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr13")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr13")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr14")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr14")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr14")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "pmpaddr15")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr15")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr15")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mcycle")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mcycle")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mcycle")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "minstret")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "minstret")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "minstret")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "mcycleh")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "mcycleh")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "mcycleh")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "minstreth")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "minstreth")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "minstreth")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "tselect")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "tselect")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "tselect")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "tdata1")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "tdata1")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "tdata1")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "tdata2")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "tdata2")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "tdata2")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1716_0 "tdata3")) /\ (
+  (case ((string_drop stringappend_1716_0 ((string_length "tdata3")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1716_0 ((string_length "tdata3")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]  :  12 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
 (*val csrAccess : mword ty12 -> mword ty2*)
 
 val _ = Define `
@@ -4132,6 +7393,10 @@ val _ = Define `
      (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
      (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)))) then
+     F
    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
      ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
@@ -4171,42 +7436,94 @@ val _ = Define `
 (*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*)
 
 val _ = Define `
- ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=  (state_monad$bindS
-   (state$and_boolS
-     (state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))))
-     (state$and_boolS
-        (state_monad$returnS (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
-        ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . 
-         state_monad$returnS (((((get_Mstatus_TVM w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))) (\ (w__2 :
+ ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=  (sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     (sail2_state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))))
+     (sail2_state$and_boolS
+        (sail2_state_monad$returnS (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . 
+         sail2_state_monad$returnS (((((get_Mstatus_TVM w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))) (\ (w__2 :
      bool) . 
-   state_monad$returnS ((~ w__2)))))`;
+   sail2_state_monad$returnS ((~ w__2)))))`;
+
+
+(*val check_Counteren : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((check_Counteren:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=
+    ((case (csr, p) of
+     (b__0, Supervisor) =>
+      if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS mcounteren_ref) (\ (w__0 : Counteren) . 
+        sail2_state_monad$returnS (((((get_Counteren_CY w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+      else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS mcounteren_ref) (\ (w__1 : Counteren) . 
+        sail2_state_monad$returnS (((((get_Counteren_TM w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+      else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS mcounteren_ref) (\ (w__2 : Counteren) . 
+        sail2_state_monad$returnS (((((get_Counteren_IR w__2  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+      else
+        sail2_state_monad$returnS ((case (b__0, Supervisor) of
+          (g__31, g__32) =>
+           if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+                      csr)) /\ ((zopz0zIzJ_u csr
+                      (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  :  12 words$word)))))) then
+             F
+           else T
+        ))
+   | (b__3, User) =>
+      if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS scounteren_ref) (\ (w__6 : Counteren) . 
+        sail2_state_monad$returnS (((((get_Counteren_CY w__6  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+      else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS scounteren_ref) (\ (w__7 : Counteren) . 
+        sail2_state_monad$returnS (((((get_Counteren_TM w__7  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+      else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS scounteren_ref) (\ (w__8 : Counteren) . 
+        sail2_state_monad$returnS (((((get_Counteren_IR w__8  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+      else
+        sail2_state_monad$returnS ((case (b__3, User) of
+          (g__31, g__32) =>
+           if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+                      csr)) /\ ((zopz0zIzJ_u csr
+                      (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  :  12 words$word)))))) then
+             F
+           else T
+        ))
+   | (g__31, g__32) =>
+      sail2_state_monad$returnS (if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)
+                         csr)) /\ ((zopz0zIzJ_u csr
+                         (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  :  12 words$word)))))) then
+                F
+              else T)
+   )))`;
 
 
 (*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*)
 
 val _ = Define `
- ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)=
-    (state$and_boolS (state_monad$returnS ((is_CSR_defined csr p)))
-     (state$and_boolS
-        (state_monad$returnS ((check_CSR_access ((csrAccess csr  :  2 words$word)) ((csrPriv csr  :  2 words$word)) p
-                    isWrite))) ((check_TVM_SATP csr p)))))`;
+ ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)=
+    (sail2_state$and_boolS (sail2_state_monad$returnS ((is_CSR_defined csr p)))
+     (sail2_state$and_boolS
+        (sail2_state_monad$returnS ((check_CSR_access ((csrAccess csr  :  2 words$word)) ((csrPriv csr  :  2 words$word)) p
+                    isWrite))) (sail2_state$and_boolS ((check_TVM_SATP csr p)) ((check_Counteren csr p))))))`;
 
 
 (*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*)
 
 val _ = Define `
- ((exception_delegatee:ExceptionType -> Privilege ->(regstate)state_monad$sequential_state ->(((Privilege),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)=
-    (let idx = (num_of_ExceptionType e) in state_monad$bindS
-   (state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) . 
-   let super = (access_vec_dec ((get_Medeleg w__0  :  64 words$word)) idx) in state_monad$bindS
-   (state_monad$read_regS sedeleg_ref) (\ (w__1 : Sedeleg) . 
-   let user = (access_vec_dec ((get_Sedeleg w__1  :  64 words$word)) idx) in state_monad$bindS
-   (state$and_boolS
-     ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__2 : Misa) . 
-      state_monad$returnS (((((get_Misa_S w__2  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))
-     (state_monad$returnS ((bit_to_bool super)))) (\ (w__3 : bool) . 
+ ((exception_delegatee:ExceptionType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)=
+    (let idx = (num_of_ExceptionType e) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) . 
+   let super = (access_vec_dec ((get_Medeleg_bits w__0  :  64 words$word)) idx) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS sedeleg_ref) (\ (w__1 : Sedeleg) . 
+   let user = (access_vec_dec ((get_Sedeleg_bits w__1  :  64 words$word)) idx) in sail2_state_monad$bindS
+   (sail2_state$and_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__2 : Misa) . 
+      sail2_state_monad$returnS (((((get_Misa_S w__2  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))
+     (sail2_state_monad$returnS ((bit_to_bool super)))) (\ (w__3 : bool) . 
    let deleg = (if w__3 then Supervisor else Machine) in
-   state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg  :  2 words$word))
+   sail2_state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg  :  2 words$word))
                   ((privLevel_to_bits p  :  2 words$word)))) then
              p
            else deleg))))))`;
@@ -4246,51 +7563,98 @@ val _ = Define `
    else NONE))`;
 
 
-(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*)
+(*val curInterrupt : Privilege -> Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*)
 
 val _ = Define `
- ((curInterrupt:Minterrupts -> Minterrupts -> Minterrupts ->(regstate)state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts)=
+ ((curInterrupt:Privilege -> Minterrupts -> Minterrupts -> Minterrupts ->(regstate)sail2_state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (priv : Privilege) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts)=
     (let (en_mip : xlenbits) =
-     ((and_vec ((get_Minterrupts pend  :  64 words$word)) ((get_Minterrupts enbl  :  64 words$word))
+     ((and_vec ((get_Minterrupts_bits pend  :  64 words$word))
+        ((get_Minterrupts_bits enbl  :  64 words$word))
        :  64 words$word)) in
    if (((en_mip = ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))) then
-     state_monad$returnS NONE
-   else
+     sail2_state_monad$returnS NONE
+   else sail2_state_monad$bindS
+     (sail2_state$or_boolS
+       (sail2_state_monad$returnS (((((privLevel_to_bits priv  :  2 words$word)) <> ((privLevel_to_bits Machine  :  2 words$word))))))
+       (sail2_state$and_boolS
+          (sail2_state_monad$returnS (((((privLevel_to_bits priv  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . 
+           sail2_state_monad$returnS (((((get_Mstatus_MIE w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))) (\ eff_mie .  sail2_state_monad$bindS
+     (sail2_state$or_boolS
+       (sail2_state_monad$returnS (((((privLevel_to_bits priv  :  2 words$word)) = ((privLevel_to_bits User  :  2 words$word))))))
+       (sail2_state$and_boolS
+          (sail2_state_monad$returnS (((((privLevel_to_bits priv  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+          ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . 
+           sail2_state_monad$returnS (((((get_Mstatus_SIE w__2  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))) (\ eff_sie . 
      let eff_mip =
-       ((and_vec en_mip ((not_vec ((get_Minterrupts delg  :  64 words$word))  :  64 words$word))
+       ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg  :  64 words$word))  :  64 words$word))
          :  64 words$word)) in
-     let eff_sip = ((and_vec en_mip ((get_Minterrupts delg  :  64 words$word))  :  64 words$word)) in state_monad$bindS
-     (state$and_boolS
-       ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . 
-        state_monad$returnS (((((get_Mstatus_MIE w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))
-       (state_monad$returnS (((eff_mip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))))) (\ (w__1 :
-       bool) . 
-     if w__1 then
-       state_monad$returnS ((case ((findPendingInterrupt eff_mip)) of
+     let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg  :  64 words$word))  :  64 words$word)) in
+     if (((eff_mie /\ (((eff_mip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))))))) then
+       (case ((findPendingInterrupt eff_mip)) of
          SOME (i) =>
           let r = (i, Machine) in
-          SOME r
-       | NONE => NONE
-       ))
-     else state_monad$bindS
-       (state$and_boolS
-         ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . 
-          state_monad$returnS (((((get_Mstatus_SIE w__2  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))
-         (state$and_boolS
-            (state_monad$returnS (((eff_sip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))))
-            (state$or_boolS
-               ( state_monad$bindS(state_monad$read_regS cur_privilege_ref) (\ (w__3 : Privilege) . 
-                state_monad$returnS (((((privLevel_to_bits w__3  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word)))))))
-               ( state_monad$bindS(state_monad$read_regS cur_privilege_ref) (\ (w__4 : Privilege) . 
-                state_monad$returnS (((((privLevel_to_bits w__4  :  2 words$word)) = ((privLevel_to_bits User  :  2 words$word)))))))))) (\ (w__7 : bool) . 
-       state_monad$returnS (if w__7 then
-                 (case ((findPendingInterrupt eff_sip)) of
-                   SOME (i) =>
-                    let r = (i, Supervisor) in
-                    SOME r
-                 | NONE => NONE
-                 )
-               else NONE)))))`;
+          sail2_state_monad$returnS (SOME r)
+       | NONE =>
+          internal_error
+            ((STRCAT "non-zero eff_mip="
+                ((STRCAT ((string_of_bits eff_mip)) ", but nothing pending"))))
+       )
+     else if (((eff_sie /\ (((eff_sip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))))))
+     then
+       (case ((findPendingInterrupt eff_sip)) of
+         SOME (i) =>
+          let r = (i, Supervisor) in
+          sail2_state_monad$returnS (SOME r)
+       | NONE =>
+          internal_error
+            ((STRCAT "non-zero eff_sip="
+                ((STRCAT ((string_of_bits eff_sip)) ", but nothing pending"))))
+       )
+     else
+       let p =
+         (if (((((get_Minterrupts_MTI pend  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+         then
+           "1"
+         else "0") in
+       let e =
+         (if (((((get_Minterrupts_MTI enbl  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+         then
+           "1"
+         else "0") in
+       let d =
+         (if (((((get_Minterrupts_MTI delg  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+         then
+           "1"
+         else "0") in
+       let (_ : unit) =
+         (print_endline
+           ((STRCAT " MTI: pend="
+               ((STRCAT p
+                   ((STRCAT " enbl=" ((STRCAT e ((STRCAT " delg=" d))))))))))) in
+       let eff_mip =
+         ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg  :  64 words$word))  :  64 words$word))
+           :  64 words$word)) in
+       let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg  :  64 words$word))  :  64 words$word)) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS mstatus_ref) (\ (w__8 : Mstatus) .  sail2_state_monad$bindS
+       (sail2_state_monad$read_regS mstatus_ref) (\ (w__9 : Mstatus) .  sail2_state_monad$bindS
+       (sail2_state_monad$read_regS mstatus_ref) (\ (w__10 : Mstatus) . 
+       let (_ : unit) =
+         (print_endline
+           ((STRCAT "mstatus="
+               ((STRCAT ((string_of_bits ((get_Mstatus_bits w__8  :  64 words$word))))
+                   ((STRCAT " mie,sie="
+                       ((STRCAT ((string_of_bits ((get_Mstatus_MIE w__9  :  1 words$word))))
+                           ((STRCAT ","
+                               ((STRCAT
+                                   ((string_of_bits ((get_Mstatus_SIE w__10  :  1 words$word))))
+                                   ((STRCAT " en_mip="
+                                       ((STRCAT ((string_of_bits en_mip))
+                                           ((STRCAT " eff_mip="
+                                               ((STRCAT ((string_of_bits eff_mip))
+                                                   ((STRCAT " eff_sip="
+                                                       ((string_of_bits eff_sip))))))))))))))))))))))))) in
+       sail2_state_monad$returnS NONE)))))))`;
 
 
 (*val tval : maybe (mword ty64) -> mword ty64*)
@@ -4306,57 +7670,76 @@ val _ = Define `
 (*val handle_trap : Privilege -> bool -> mword ty4 -> mword ty64 -> maybe (mword ty64) -> M (mword ty64)*)
 
 val _ = Define `
- ((handle_trap:Privilege -> bool ->(4)words$word ->(64)words$word ->(xlenbits)option ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info :
+ ((handle_trap:Privilege -> bool ->(4)words$word ->(64)words$word ->(xlenbits)option ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info :
    xlenbits option)=
     (let (_ : unit) =
-     (prerr_endline
+     (print_endline
        ((STRCAT "handling "
            ((STRCAT (if intr then "int#" else "exc#")
-               ((STRCAT ((string_of_vec c))
+               ((STRCAT ((string_of_bits c))
                    ((STRCAT " at priv "
                        ((STRCAT ((privLevel_to_str del_priv))
                            ((STRCAT " with tval "
-                               ((string_of_vec ((tval info  :  64 words$word))))))))))))))))) in
+                               ((string_of_bits ((tval info  :  64 words$word))))))))))))))))) in
    (case del_priv of
-     Machine => state_monad$bindS (state_monad$seqS (state_monad$seqS
+     Machine => sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
       (set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr  :  1 words$word)))
       (set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):ii) c  :  63 words$word))))
-      (state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
       (set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0  :  1 words$word)))
       (set_Mstatus_MIE mstatus_ref ((bool_to_bits F  :  1 words$word))))
-      (state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) .  state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS
+      (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
       (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1  :  2 words$word)))
-      (state_monad$write_regS mtval_ref ((tval info  :  64 words$word))))
-      (state_monad$write_regS mepc_ref pc))
-      (state_monad$write_regS cur_privilege_ref del_priv))
-      (state_monad$read_regS mtvec_ref)) (\ (w__2 : Mtvec) .  state_monad$bindS
-      (state_monad$read_regS mcause_ref) (\ (w__3 : Mcause) . 
-      (case ((tvec_addr w__2 w__3  :  ( 64 words$word)option)) of
-        SOME (epc) => state_monad$returnS epc
+      (sail2_state_monad$write_regS mtval_ref ((tval info  :  64 words$word))))
+      (sail2_state_monad$write_regS mepc_ref pc))
+      (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . 
+      let (_ : unit) =
+        (print_endline
+          ((STRCAT "CSR mstatus <- "
+              ((STRCAT ((string_of_bits ((get_Mstatus_bits w__2  :  64 words$word))))
+                  ((STRCAT " (input: "
+                      ((STRCAT ((string_of_bits ((get_Mstatus_bits w__3  :  64 words$word)))) ")"))))))))) in
+      let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mtvec_ref) (\ (w__4 : Mtvec) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mcause_ref) (\ (w__5 : Mcause) . 
+      (case ((tvec_addr w__4 w__5  :  ( 64 words$word)option)) of
+        SOME (epc) => sail2_state_monad$returnS epc
       | NONE => (internal_error "Invalid mtvec mode"  : ( 64 words$word) M)
-      )))))
-   | Supervisor => state_monad$bindS (state_monad$seqS (state_monad$seqS
+      )))))))
+   | Supervisor => sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
       (set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr  :  1 words$word)))
       (set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):ii) c  :  63 words$word))))
-      (state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
-      (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6  :  1 words$word)))
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__8 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__8  :  1 words$word)))
       (set_Mstatus_SIE mstatus_ref ((bool_to_bits F  :  1 words$word))))
-      (state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) .  state_monad$bindS
-      (case w__7 of
-        User => state_monad$returnS ((bool_to_bits F  :  1 words$word))
-      | Supervisor => state_monad$returnS ((bool_to_bits T  :  1 words$word))
+      (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__9 : Privilege) .  sail2_state_monad$bindS
+      (case w__9 of
+        User => sail2_state_monad$returnS ((bool_to_bits F  :  1 words$word))
+      | Supervisor => sail2_state_monad$returnS ((bool_to_bits T  :  1 words$word))
       | Machine => (internal_error "invalid privilege for s-mode trap"  : ( 1 words$word) M)
-      ) (\ (w__9 :  1 words$word) .  state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS
-      (set_Mstatus_SPP mstatus_ref w__9)
-      (state_monad$write_regS stval_ref ((tval info  :  64 words$word))))
-      (state_monad$write_regS sepc_ref pc))
-      (state_monad$write_regS cur_privilege_ref del_priv))
-      (state_monad$read_regS stvec_ref)) (\ (w__10 : Mtvec) .  state_monad$bindS
-      (state_monad$read_regS scause_ref) (\ (w__11 : Mcause) . 
-      (case ((tvec_addr w__10 w__11  :  ( 64 words$word)option)) of
-        SOME (epc) => state_monad$returnS epc
+      ) (\ (w__11 :  1 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (set_Mstatus_SPP mstatus_ref w__11)
+      (sail2_state_monad$write_regS stval_ref ((tval info  :  64 words$word))))
+      (sail2_state_monad$write_regS sepc_ref pc))
+      (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__12 : Mstatus) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__13 : Mstatus) . 
+      let (_ : unit) =
+        (print_endline
+          ((STRCAT "CSR mstatus <- "
+              ((STRCAT ((string_of_bits ((get_Mstatus_bits w__12  :  64 words$word))))
+                  ((STRCAT " (input: "
+                      ((STRCAT ((string_of_bits ((get_Mstatus_bits w__13  :  64 words$word))))
+                          ")"))))))))) in
+      let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS stvec_ref) (\ (w__14 : Mtvec) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS scause_ref) (\ (w__15 : Mcause) . 
+      (case ((tvec_addr w__14 w__15  :  ( 64 words$word)option)) of
+        SOME (epc) => sail2_state_monad$returnS epc
       | NONE => (internal_error "Invalid stvec mode"  : ( 64 words$word) M)
-      ))))))
+      ))))))))
    | User => (internal_error "the N extension is currently unsupported"  : ( 64 words$word) M)
    )))`;
 
@@ -4364,12 +7747,12 @@ val _ = Define `
 (*val handle_exception : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)*)
 
 val _ = Define `
- ((handle_exception:Privilege -> ctl_result ->(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)=
+ ((handle_exception:Privilege -> ctl_result ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)=
     ((case (cur_priv, ctl) of
-     (_, CTL_TRAP (e)) => state_monad$bindS
+     (_, CTL_TRAP (e)) => sail2_state_monad$bindS
       (exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv . 
       let (_ : unit) =
-        (prerr_endline
+        (print_endline
           ((STRCAT "trapping from "
               ((STRCAT ((privLevel_to_str cur_priv))
                   ((STRCAT " to "
@@ -4379,1789 +7762,4146 @@ val _ = Define `
       (handle_trap del_priv F ((exceptionType_to_bits e.sync_exception_trap  :  4 words$word)) pc
          e.sync_exception_excinfo
         : ( 64 words$word) M))
-   | (_, CTL_MRET (_)) => state_monad$bindS
-      (state_monad$read_regS cur_privilege_ref) (\ prev_priv .  state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
+   | (_, CTL_MRET (_)) => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
       (set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1  :  1 words$word)))
       (set_Mstatus_MPIE mstatus_ref ((bool_to_bits T  :  1 words$word))))
-      (state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
-      (state_monad$write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2  :  2 words$word)))))
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2  :  2 words$word)))))
       (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User  :  2 words$word))))
-      (state_monad$read_regS cur_privilege_ref)) (\ (w__3 : Privilege) . 
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__3 : Mstatus) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) . 
+      let (_ : unit) =
+        (print_endline
+          ((STRCAT "CSR mstatus <- "
+              ((STRCAT ((string_of_bits ((get_Mstatus_bits w__3  :  64 words$word))))
+                  ((STRCAT " (input: "
+                      ((STRCAT ((string_of_bits ((get_Mstatus_bits w__4  :  64 words$word)))) ")"))))))))) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) . 
       let (_ : unit) =
-        (prerr_endline
+        (print_endline
           ((STRCAT "ret-ing from "
               ((STRCAT ((privLevel_to_str prev_priv))
-                  ((STRCAT " to " ((privLevel_to_str w__3))))))))) in
-      (state_monad$read_regS mepc_ref  : ( 64 words$word) M)))))
-   | (_, CTL_SRET (_)) => state_monad$bindS
-      (state_monad$read_regS cur_privilege_ref) (\ prev_priv .  state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
-      (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5  :  1 words$word)))
+                  ((STRCAT " to " ((privLevel_to_str w__5))))))))) in
+      let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mepc_ref  : ( 64 words$word) M) (\ (w__6 :  64 words$word) .  sail2_state_monad$bindS
+      (pc_alignment_mask ()   : ( 64 words$word) M) (\ (w__7 :  64 words$word) . 
+      sail2_state_monad$returnS ((and_vec w__6 w__7  :  64 words$word))))))))))
+   | (_, CTL_SRET (_)) => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__8 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__8  :  1 words$word)))
       (set_Mstatus_SPIE mstatus_ref ((bool_to_bits T  :  1 words$word))))
-      (state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) .  state_monad$bindS (state_monad$seqS (state_monad$seqS
-      (state_monad$write_regS
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__9 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS
         cur_privilege_ref
-        (if (((((get_Mstatus_SPP w__6  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+        (if (((((get_Mstatus_SPP w__9  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
          then
            Supervisor
          else User))
       (set_Mstatus_SPP mstatus_ref ((bool_to_bits F  :  1 words$word))))
-      (state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . 
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__10 : Mstatus) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__11 : Mstatus) . 
       let (_ : unit) =
-        (prerr_endline
+        (print_endline
+          ((STRCAT "CSR mstatus <- "
+              ((STRCAT ((string_of_bits ((get_Mstatus_bits w__10  :  64 words$word))))
+                  ((STRCAT " (input: "
+                      ((STRCAT ((string_of_bits ((get_Mstatus_bits w__11  :  64 words$word))))
+                          ")"))))))))) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__12 : Privilege) . 
+      let (_ : unit) =
+        (print_endline
           ((STRCAT "ret-ing from "
               ((STRCAT ((privLevel_to_str prev_priv))
-                  ((STRCAT " to " ((privLevel_to_str w__7))))))))) in
-      (state_monad$read_regS sepc_ref  : ( 64 words$word) M)))))
+                  ((STRCAT " to " ((privLevel_to_str w__12))))))))) in
+      let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS sepc_ref  : ( 64 words$word) M) (\ (w__13 :  64 words$word) .  sail2_state_monad$bindS
+      (pc_alignment_mask ()   : ( 64 words$word) M) (\ (w__14 :  64 words$word) . 
+      sail2_state_monad$returnS ((and_vec w__13 w__14  :  64 words$word))))))))))
    )))`;
 
 
 (*val handle_mem_exception : mword ty64 -> ExceptionType -> M unit*)
 
 val _ = Define `
- ((handle_mem_exception:(64)words$word -> ExceptionType ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)=
-    (let (t : sync_exception) = (<| sync_exception_trap := e;  sync_exception_excinfo := (SOME addr) |>) in state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  state_monad$bindS
+ ((handle_mem_exception:(64)words$word -> ExceptionType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)=
+    (let (t : sync_exception) = (<| sync_exception_trap := e;  sync_exception_excinfo := (SOME addr) |>) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
    (handle_exception w__0 (CTL_TRAP t) w__1  : ( 64 words$word) M) (\ (w__2 : xlenbits) . 
-   state_monad$write_regS nextPC_ref w__2)))))`;
+   sail2_state_monad$write_regS nextPC_ref w__2)))))`;
 
 
 (*val handle_decode_exception : mword ty64 -> M unit*)
 
 val _ = Define `
- ((handle_decode_exception:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) instbits=
+ ((handle_decode_exception:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) instbits=
     (let (t : sync_exception) =
      (<| sync_exception_trap := E_Illegal_Instr; 
-        sync_exception_excinfo := (SOME instbits) |>) in state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  state_monad$bindS
+        sync_exception_excinfo := (SOME instbits) |>) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
    (handle_exception w__0 (CTL_TRAP t) w__1  : ( 64 words$word) M) (\ (w__2 : xlenbits) . 
-   state_monad$write_regS nextPC_ref w__2)))))`;
+   sail2_state_monad$write_regS nextPC_ref w__2)))))`;
 
 
 (*val handle_interrupt : InterruptType -> Privilege -> M unit*)
 
 val _ = Define `
- ((handle_interrupt:InterruptType -> Privilege ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS
+ ((handle_interrupt:InterruptType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS
    (handle_trap del_priv T ((interruptType_to_bits i  :  4 words$word)) w__0 NONE
      : ( 64 words$word) M) (\ (w__1 : xlenbits) . 
-   state_monad$write_regS nextPC_ref w__1))))`;
+   sail2_state_monad$write_regS nextPC_ref w__1))))`;
 
 
 (*val handle_illegal : unit -> M unit*)
 
 val _ = Define `
- ((handle_illegal:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =
+ ((handle_illegal:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
     (let (t : sync_exception) =
      (<| sync_exception_trap := E_Illegal_Instr; 
-        sync_exception_excinfo := NONE |>) in state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  state_monad$bindS
+        sync_exception_excinfo := NONE |>) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) .  sail2_state_monad$bindS
    (handle_exception w__0 (CTL_TRAP t) w__1  : ( 64 words$word) M) (\ (w__2 : xlenbits) . 
-   state_monad$write_regS nextPC_ref w__2)))))`;
+   sail2_state_monad$write_regS nextPC_ref w__2)))))`;
 
 
 (*val init_sys : unit -> M unit*)
 
 val _ = Define `
- ((init_sys:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS
-   (state_monad$write_regS cur_privilege_ref Machine)
+ ((init_sys:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS cur_privilege_ref Machine)
+   (sail2_state_monad$write_regS mhartid_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
    (set_Misa_MXL misa_ref ((arch_to_bits RV64  :  2 words$word))))
+   (set_Misa_A misa_ref ((bool_to_bits T  :  1 words$word))))
    (set_Misa_C misa_ref ((bool_to_bits T  :  1 words$word))))
+   (set_Misa_I misa_ref ((bool_to_bits T  :  1 words$word))))
+   (set_Misa_M misa_ref ((bool_to_bits T  :  1 words$word))))
    (set_Misa_U misa_ref ((bool_to_bits T  :  1 words$word))))
    (set_Misa_S misa_ref ((bool_to_bits T  :  1 words$word))))
-   (state_monad$read_regS misa_ref)) (\ (w__0 : Misa) .  state_monad$bindS (state_monad$seqS
+   (sail2_state_monad$read_regS misa_ref)) (\ (w__0 : Misa) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0  :  2 words$word)))
-   (state_monad$read_regS misa_ref)) (\ (w__1 : Misa) .  state_monad$seqS (state_monad$seqS
+   (sail2_state_monad$read_regS misa_ref)) (\ (w__1 : Misa) .  sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
    (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1  :  2 words$word)))
    (set_Mstatus_SD mstatus_ref ((bool_to_bits F  :  1 words$word))))
-   (state_monad$write_regS mhartid_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))))))`;
+   (set_Minterrupts_bits mip_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (set_Minterrupts_bits mie_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (set_Minterrupts_bits mideleg_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (set_Medeleg_bits medeleg_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (set_Mtvec_bits mtvec_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (set_Mcause_bits mcause_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (sail2_state_monad$write_regS mepc_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (sail2_state_monad$write_regS mtval_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (sail2_state_monad$write_regS mscratch_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (sail2_state_monad$write_regS mcycle_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (sail2_state_monad$write_regS mtime_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (set_Counteren_bits mcounteren_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  32 words$word))))
+   (sail2_state_monad$write_regS minstret_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+   (sail2_state_monad$write_regS minstret_written_ref F))
+   (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . 
+   sail2_state_monad$returnS ((print_endline
+              ((STRCAT "CSR mstatus <- "
+                  ((STRCAT ((string_of_bits ((get_Mstatus_bits w__2  :  64 words$word))))
+                      ((STRCAT " (input: "
+                          ((STRCAT
+                              ((string_of_bits
+                                  ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))
+                              ")")))))))))))))))`;
+
+
+(*val phys_mem_segments : unit -> list ((mword ty64 * mword ty64))*)
+
+val _ = Define `
+ ((phys_mem_segments:unit ->((64)words$word#(64)words$word)list) () =
+    (((plat_rom_base ()   :  64 words$word), (plat_rom_size ()   :  64 words$word)) ::
+     (((plat_ram_base ()   :  64 words$word), (plat_ram_size ()   :  64 words$word)) :: [])))`;
+
+
+(*val within_phys_mem : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_phys_mem:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (if (((((zopz0zIzJ_u ((plat_ram_base ()   :  64 words$word)) addr)) /\ ((zopz0zIzJ_u ((add_vec_int addr width  :  64 words$word))
+              ((add_vec ((plat_ram_base ()   :  64 words$word)) ((plat_ram_size ()   :  64 words$word))
+                 :  64 words$word))))))) then
+     T
+   else if (((((zopz0zIzJ_u ((plat_rom_base ()   :  64 words$word)) addr)) /\ ((zopz0zIzJ_u ((add_vec_int addr width  :  64 words$word))
+                   ((add_vec ((plat_rom_base ()   :  64 words$word)) ((plat_rom_size ()   :  64 words$word))
+                      :  64 words$word))))))) then
+     T
+   else F))`;
 
 
-(*val tick_clock : unit -> M unit*)
+(*val within_clint : mword ty64 -> integer -> bool*)
 
 val _ = Define `
- ((tick_clock:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS mcycle_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii)  :  64 words$word)))))`;
+ ((within_clint:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (((zopz0zIzJ_u ((plat_clint_base ()   :  64 words$word)) addr)) /\ ((zopz0zIzJ_u ((add_vec_int addr width  :  64 words$word))
+         ((add_vec ((plat_clint_base ()   :  64 words$word)) ((plat_clint_size ()   :  64 words$word))
+            :  64 words$word))))))`;
+
 
+(*val within_htif_writable : mword ty64 -> integer -> bool*)
 
 val _ = Define `
- ((PAGESIZE_BITS:int)=  ((( 12 : int):ii)))`;
+ ((within_htif_writable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (((plat_htif_tohost ()   :  64 words$word)) = addr))`;
 
 
-(*val _get_PTE_Bits : PTE_Bits -> mword ty8*)
+(*val within_htif_readable : mword ty64 -> integer -> bool*)
 
 val _ = Define `
- ((get_PTE_Bits:PTE_Bits ->(8)words$word) (Mk_PTE_Bits (v))=  v)`;
-
+ ((within_htif_readable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (((plat_htif_tohost ()   :  64 words$word)) = addr))`;
 
-(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((set_PTE_Bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_PTE_Bits v) in
-   state_monad$write_regS r_ref r)))`;
+((MSIP_BASE:(64)words$word)=
+   ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                B0;B0;B0;B0;B0;B0;B0;B0]
+    :  64 words$word)))`;
 
 
 val _ = Define `
- ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+((MTIMECMP_BASE:(64)words$word)=
+   ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;
+                B0;B0;B0;B0;B0;B0;B0;B0]
+    :  64 words$word)))`;
 
 
 val _ = Define `
- ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+((MTIME_BASE:(64)words$word)=
+   ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;
+                B1;B1;B1;B1;B1;B0;B0;B0]
+    :  64 words$word)))`;
 
 
+(*val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
 val _ = Define `
- ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x  :  8 words$word))))`;
+ ((clint_load:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    (let addr = ((sub_vec addr ((plat_clint_base ()   :  64 words$word))  :  64 words$word)) in
+   if ((((((addr = MSIP_BASE))) /\ ((((((width = (( 8 : int):ii)))) \/ (((width = (( 4 : int):ii))))))))))
+   then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) . 
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint["
+             ((STRCAT ((string_of_bits addr))
+                 ((STRCAT "] -> "
+                     ((string_of_bits ((get_Minterrupts_MSI w__0  :  1 words$word))))))))))) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mip_ref) (\ (w__1 : Minterrupts) . 
+     sail2_state_monad$returnS (MemValue ((zero_extend ((get_Minterrupts_MSI w__1  :  1 words$word))
+                          (((( 8 : int):ii) * width))
+                         :  'int8_times_n words$word)))))
+   else if ((((((addr = MTIMECMP_BASE))) /\ (((width = (( 8 : int):ii))))))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mtimecmp_ref  : ( 64 words$word) M) (\ (w__2 : xlenbits) . 
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint["
+             ((STRCAT ((string_of_bits addr)) ((STRCAT "] -> " ((string_of_bits w__2))))))))) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mtimecmp_ref  : ( 64 words$word) M) (\ (w__3 : xlenbits) . 
+     sail2_state_monad$returnS (MemValue ((zero_extend w__3 (( 64 : int):ii)  :  'int8_times_n words$word)))))
+   else if ((((((addr = MTIME_BASE))) /\ (((width = (( 8 : int):ii))))))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M) (\ (w__4 : xlenbits) . 
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint["
+             ((STRCAT ((string_of_bits addr)) ((STRCAT "] -> " ((string_of_bits w__4))))))))) in sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M) (\ (w__5 : xlenbits) . 
+     sail2_state_monad$returnS (MemValue ((zero_extend w__5 (( 64 : int):ii)  :  'int8_times_n words$word)))))
+   else
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint[" ((STRCAT ((string_of_bits addr)) "] -> <not-mapped>"))))) in
+     sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
 
 
+(*val clint_dispatch : unit -> M unit*)
+
 val _ = Define `
- ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+ ((clint_dispatch:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
+   let (_ : unit) = (print_endline ((STRCAT "clint::tick mtime <- " ((string_of_bits w__0))))) in sail2_state_monad$bindS (sail2_state_monad$seqS
+   (set_Minterrupts_MTI mip_ref ((bool_to_bits F  :  1 words$word)))
+   (sail2_state_monad$read_regS mtimecmp_ref  : ( 64 words$word) M)) (\ (w__1 : xlenbits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) . 
+   if ((zopz0zIzJ_u w__1 w__2)) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M) (\ (w__3 : xlenbits) . 
+     let (_ : unit) =
+       (print_endline ((STRCAT " clint timer pending at mtime " ((string_of_bits w__3))))) in
+     set_Minterrupts_MTI mip_ref ((bool_to_bits T  :  1 words$word)))
+   else sail2_state_monad$returnS () )))))`;
+
 
+(*val clint_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
 val _ = Define `
- ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((clint_store:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+    (let addr = ((sub_vec addr ((plat_clint_base ()   :  64 words$word))  :  64 words$word)) in
+   if ((((((addr = MSIP_BASE))) /\ ((((((width = (( 8 : int):ii)))) \/ (((width = (( 4 : int):ii))))))))))
+   then
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint["
+             ((STRCAT ((string_of_bits addr))
+                 ((STRCAT "] <- "
+                     ((STRCAT ((string_of_bits data))
+                         ((STRCAT " (mip.MSI <- "
+                             ((STRCAT
+                                 ((string_of_bits
+                                     ((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii)))  :  1 words$word))))
+                                 ")"))))))))))))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (set_Minterrupts_MSI mip_ref
+       ((bool_to_bits
+           (((((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii)))  :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word))))
+          :  1 words$word)))
+     (clint_dispatch () )) (sail2_state_monad$returnS (MemValue () ))
+   else if ((((((addr = MTIMECMP_BASE))) /\ (((width = (( 8 : int):ii))))))) then
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint["
+             ((STRCAT ((string_of_bits addr))
+                 ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))) in sail2_state_monad$seqS (sail2_state_monad$seqS
+     (sail2_state_monad$write_regS mtimecmp_ref ((zero_extend data (( 64 : int):ii)  :  64 words$word)))
+     (clint_dispatch () )) (sail2_state_monad$returnS (MemValue () ))
+   else
+     let (_ : unit) =
+       (print_endline
+         ((STRCAT "clint["
+             ((STRCAT ((string_of_bits addr))
+                 ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (<unmapped>)"))))))))) in
+     sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
 
+(*val tick_clock : unit -> M unit*)
 
 val _ = Define `
- ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x  :  8 words$word))))`;
+ ((tick_clock:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mcycle_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii)  :  64 words$word)))
+   (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS mtime_ref ((add_vec_int w__1 (( 1 : int):ii)  :  64 words$word))) (clint_dispatch () )))))`;
+
 
+(*val Mk_htif_cmd : mword ty64 -> htif_cmd*)
 
 val _ = Define `
- ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+ ((Mk_htif_cmd:(64)words$word -> htif_cmd) v=
+    (<| htif_cmd_htif_cmd_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
 
 
+(*val _get_htif_cmd_bits : htif_cmd -> mword ty64*)
+
 val _ = Define `
- ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((get_htif_cmd_bits:htif_cmd ->(64)words$word) v=
+    ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
 
+(*val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x  :  8 words$word))))`;
+ ((set_htif_cmd_bits:((regstate),(register_value),(htif_cmd))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
+(*val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd*)
+
 val _ = Define `
- ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+ ((update_htif_cmd_bits:htif_cmd ->(64)words$word -> htif_cmd) v x=
+    ((v with<|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
 
+(*val _get_htif_cmd_device : htif_cmd -> mword ty8*)
 
 val _ = Define `
- ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((get_htif_cmd_device:htif_cmd ->(8)words$word) v=
+    ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)  :  8 words$word)))`;
 
 
+(*val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
+
 val _ = Define `
- ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x  :  8 words$word))))`;
+ ((set_htif_cmd_device:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
 
+(*val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd*)
 
 val _ = Define `
- ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+ ((update_htif_cmd_device:htif_cmd ->(8)words$word -> htif_cmd) v x=
+    ((v with<|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  64 words$word))|>)))`;
 
 
+(*val _get_htif_cmd_cmd : htif_cmd -> mword ty8*)
+
 val _ = Define `
- ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((get_htif_cmd_cmd:htif_cmd ->(8)words$word) v=
+    ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)  :  8 words$word)))`;
+
 
+(*val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
 
 val _ = Define `
- ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x  :  8 words$word))))`;
+ ((set_htif_cmd_cmd:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
 
 
+(*val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd*)
+
 val _ = Define `
- ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+ ((update_htif_cmd_cmd:htif_cmd ->(8)words$word -> htif_cmd) v x=
+    ((v with<|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  64 words$word))|>)))`;
+
 
+(*val _get_htif_cmd_payload : htif_cmd -> mword ty48*)
 
 val _ = Define `
- ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((get_htif_cmd_payload:htif_cmd ->(48)words$word) v=
+    ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)  :  48 words$word)))`;
 
 
+(*val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit*)
+
 val _ = Define `
- ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x  :  8 words$word))))`;
+ ((set_htif_cmd_payload:((regstate),(register_value),(htif_cmd))register_ref ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii)  :  48 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
 
+(*val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd*)
 
 val _ = Define `
- ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+ ((update_htif_cmd_payload:htif_cmd ->(48)words$word -> htif_cmd) v x=
+    ((v with<|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 47 : int):ii) (( 0 : int):ii)  :  48 words$word))
+          :  64 words$word))|>)))`;
 
 
+(*val htif_load : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
 val _ = Define `
- ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((htif_load:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS htif_tohost_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
+   let (_ : unit) =
+     (print_endline
+       ((STRCAT "htif["
+           ((STRCAT ((string_of_bits addr)) ((STRCAT "] -> " ((string_of_bits w__0))))))))) in
+   if (((width = (( 8 : int):ii)))) then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS htif_tohost_ref  : ( 64 words$word) M) (\ (w__1 : xlenbits) . 
+     sail2_state_monad$returnS (MemValue ((zero_extend w__1 (( 64 : int):ii)  :  'int8_times_n words$word))))
+   else sail2_state_monad$returnS (MemException E_Load_Access_Fault))))`;
+
 
+(*val htif_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
 val _ = Define `
- ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x  :  8 words$word))))`;
+ ((htif_store:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+    (let (_ : unit) =
+     (print_endline
+       ((STRCAT "htif["
+           ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))) in
+   let (cbits : xlenbits) = ((EXTZ (( 64 : int):ii) data  :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS htif_tohost_ref cbits)
+   (let cmd = (Mk_htif_cmd cbits) in
+   let b__0 = ((get_htif_cmd_device cmd  :  8 words$word)) in sail2_state_monad$seqS
+   (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)))) then
+      let (_ : unit) =
+        (print_endline
+          ((STRCAT "htif-syscall-proxy cmd: "
+              ((string_of_bits ((get_htif_cmd_payload cmd  :  48 words$word))))))) in
+      if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd  :  48 words$word)) (( 0 : int):ii)))
+                :  1 words$word)) = (vec_of_bits [B1]  :  1 words$word)))) then sail2_state_monad$seqS
+        (sail2_state_monad$write_regS htif_done_ref T)
+        (sail2_state_monad$write_regS
+          htif_exit_code_ref
+          ((shift_bits_right
+              ((zero_extend ((get_htif_cmd_payload cmd  :  48 words$word)) xlen  :  64 words$word))
+              (vec_of_bits [B0;B1]  :  2 words$word)
+             :  64 words$word)))
+      else sail2_state_monad$returnS () 
+    else
+      sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  :  8 words$word)))) then
+                let (_ : unit) =
+                  (print_endline
+                    ((STRCAT "htif-term cmd: "
+                        ((string_of_bits ((get_htif_cmd_payload cmd  :  48 words$word))))))) in
+                let b__2 = ((get_htif_cmd_cmd cmd  :  8 words$word)) in
+                if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)))) then () 
+                else if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  :  8 words$word)))) then
+                  plat_term_write
+                    ((subrange_vec_dec ((get_htif_cmd_payload cmd  :  48 words$word)) (( 7 : int):ii) (( 0 : int):ii)
+                       :  8 words$word))
+                else print_endline ((STRCAT "Unknown term cmd: " ((string_of_bits b__2))))
+              else print_endline ((STRCAT "htif-???? cmd: " ((string_of_bits data))))))
+   (sail2_state_monad$returnS (MemValue () )))))`;
 
 
+(*val htif_tick : unit -> M unit*)
+
 val _ = Define `
- ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+ ((htif_tick:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS htif_tohost_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
+   let (_ : unit) = (print_endline ((STRCAT "htif::tick " ((string_of_bits w__0))))) in
+   sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))))`;
+
 
+(*val within_mmio_readable : mword ty64 -> integer -> bool*)
 
 val _ = Define `
- ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . 
-   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v  :  8 words$word)) in
-   state_monad$write_regS r_ref (Mk_PTE_Bits r))))`;
+ ((within_mmio_readable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (((within_clint addr width)) \/ (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= width)))))))`;
 
 
+(*val within_mmio_writable : mword ty64 -> integer -> bool*)
+
 val _ = Define `
- ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x=
-    (Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x  :  8 words$word))))`;
+ ((within_mmio_writable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (((within_clint addr width)) \/ (((((within_htif_writable addr width)) /\ ((width <= (( 8 : int):ii))))))))`;
 
 
-(*val isPTEPtr : mword ty8 -> bool*)
+(*val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
 val _ = Define `
- ((isPTEPtr:(8)words$word -> bool) p=
-    (let a = (Mk_PTE_Bits p) in
-   ((((((get_PTE_Bits_R a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ ((((((((get_PTE_Bits_W a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ (((((get_PTE_Bits_X a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))))))))`;
+ ((mmio_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int)=
+    (if ((within_clint addr width)) then
+     (clint_load addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+   else if (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= width))))) then
+     (htif_load addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+   else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
 
 
-(*val isInvalidPTE : mword ty8 -> bool*)
+(*val mmio_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
 val _ = Define `
- ((isInvalidPTE:(8)words$word -> bool) p=
-    (let a = (Mk_PTE_Bits p) in
-   ((((((get_PTE_Bits_V a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ ((((((((get_PTE_Bits_W a  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_R a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))))))))`;
+ ((mmio_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)=
+    (if ((within_clint addr width)) then clint_store addr width data
+   else if (((((within_htif_writable addr width)) /\ ((width <= (( 8 : int):ii)))))) then
+     htif_store addr width data
+   else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
 
 
-(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*)
+(*val init_platform : unit -> M unit*)
 
 val _ = Define `
- ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p :
-  PTE_Bits)=
-    ((case (ac, priv) of
-     (Read, User) =>
-      state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr)))))))))
-   | (Write, User) =>
-      state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
-   | (ReadWrite, User) =>
-      state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr))))))))))))
-   | (Execute, User) =>
-      state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
-   | (Read, Supervisor) =>
-      state_monad$returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr)))))))))
-   | (Write, Supervisor) =>
-      state_monad$returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
-   | (ReadWrite, Supervisor) =>
-      state_monad$returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr))))))))))))
-   | (Execute, Supervisor) =>
-      state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ (((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
-   | (_, Machine) => internal_error "m-mode mem perm check"
-   )))`;
+ ((init_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$seqS (sail2_state_monad$seqS
+   (sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))
+   (sail2_state_monad$write_regS htif_done_ref F))
+   (sail2_state_monad$write_regS htif_exit_code_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))))`;
 
 
-(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*)
+(*val tick_platform : unit -> M unit*)
 
 val _ = Define `
- ((update_PTE_Bits:PTE_Bits -> AccessType ->(PTE_Bits)option) (p : PTE_Bits) (a : AccessType)=
-    (let update_d =
-     (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))) in
-   let update_a = (((get_PTE_Bits_A p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))) in
-   if (((update_d \/ update_a))) then
-     let np = (update_PTE_Bits_A p ((bool_to_bits T  :  1 words$word))) in
-     let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits T  :  1 words$word)) else np) in
-     SOME np
-   else NONE))`;
+ ((tick_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (let (_ : unit) = (cancel_reservation () ) in
+   htif_tick () ))`;
 
 
-(*val PTW_Error_of_num : integer -> PTW_Error*)
+(*val is_aligned_addr : mword ty64 -> integer -> bool*)
 
 val _ = Define `
- ((PTW_Error_of_num:int -> PTW_Error) arg_=
-    (let l__0 = arg_ in
-   if (((l__0 = (( 0 : int):ii)))) then PTW_Access
-   else if (((l__0 = (( 1 : int):ii)))) then PTW_Invalid_PTE
-   else if (((l__0 = (( 2 : int):ii)))) then PTW_No_Permission
-   else if (((l__0 = (( 3 : int):ii)))) then PTW_Misaligned
-   else PTW_PTE_Update))`;
+ ((is_aligned_addr:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+    (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):ii)))`;
 
 
-(*val num_of_PTW_Error : PTW_Error -> integer*)
+(*val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
 
 val _ = Define `
- ((num_of_PTW_Error:PTW_Error -> int) arg_=
-    ((case arg_ of
-     PTW_Access => (( 0 : int):ii)
-   | PTW_Invalid_PTE => (( 1 : int):ii)
+ ((phys_mem_read:ReadType ->(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+  bool)=  (sail2_state_monad$bindS
+   (RISCV_read addr width aq rl res  : ( ( 'int8_times_n words$word)option) M) (\ (w__0 :
+      ( 'int8_times_n words$word)option) . 
+   sail2_state_monad$returnS ((case (t, w__0) of
+     (Instruction, NONE) => MemException E_Fetch_Access_Fault
+   | (Data, NONE) => MemException E_Load_Access_Fault
+   | (_, SOME (v)) =>
+      let (_ : unit) =
+        (print_endline
+          ((STRCAT "mem["
+              ((STRCAT ((readType_to_str t))
+                  ((STRCAT ","
+                      ((STRCAT ((string_of_bits addr))
+                          ((STRCAT "] -> " ((string_of_bits v))))))))))))) in
+      MemValue v
+   )))))`;
+
+
+(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((checked_mem_read:ReadType ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int)=
+    (if ((((((((readType_to_str t)) = ((readType_to_str Data))))) /\ ((within_mmio_readable addr width))))) then
+     (mmio_read addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+   else if ((within_phys_mem addr width)) then
+     (phys_mem_read t addr width F F F  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+   else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val MEMr : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+(*val MEMr_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+(*val MEMr_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+(*val MEMr_reserved : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+(*val MEMr_reserved_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+(*val MEMr_reserved_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((MEMr0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=  ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+
+
+val _ = Define `
+ ((MEMr_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+
+
+val _ = Define `
+ ((MEMr_strong_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+
+
+val _ = Define `
+ ((MEMr_reserved0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+
+
+val _ = Define `
+ ((MEMr_reserved_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+
+
+val _ = Define `
+ ((MEMr_reserved_strong_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+    ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`;
+
+
+(*val mem_read : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl res=
+    (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then
+     sail2_state_monad$returnS (MemException E_Load_Addr_Align)
+   else
+     (case (aq, rl, res) of
+       (F, F, F) =>
+        (checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+     | (T, F, F) => (MEMr_acquire0 addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+     | (F, F, T) =>
+        (MEMr_reserved0 addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+     | (T, F, T) =>
+        (MEMr_reserved_acquire0 addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+     | (F, T, F) => sail2_state_monad$throwS (Error_not_implemented "load.rl")
+     | (T, T, F) =>
+        (MEMr_strong_acquire0 addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+     | (F, T, T) => sail2_state_monad$throwS (Error_not_implemented "lr.rl")
+     | (T, T, T) =>
+        (MEMr_reserved_strong_acquire0 addr width  : ( ( 'int8_times_n words$word)MemoryOpResult) M)
+     )))`;
+
+
+(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl con=
+    (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+     sail2_state_monad$returnS (MemException E_SAMO_Addr_Align)
+   else
+     (case (aq, rl, con) of
+       (F, F, F) => sail2_state_monad$seqS (MEMea addr width) (sail2_state_monad$returnS (MemValue () ))
+     | (F, T, F) => sail2_state_monad$seqS (MEMea_release addr width) (sail2_state_monad$returnS (MemValue () ))
+     | (F, F, T) => sail2_state_monad$seqS (MEMea_conditional addr width) (sail2_state_monad$returnS (MemValue () ))
+     | (F, T, T) => sail2_state_monad$seqS (MEMea_conditional_release addr width) (sail2_state_monad$returnS (MemValue () ))
+     | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq")
+     | (T, T, F) => sail2_state_monad$seqS (MEMea_strong_release addr width) (sail2_state_monad$returnS (MemValue () ))
+     | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq")
+     | (T, T, T) => sail2_state_monad$seqS (MEMea_conditional_strong_release addr width) (sail2_state_monad$returnS (MemValue () ))
+     )))`;
+
+
+(*val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((phys_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)=
+    (let (_ : unit) =
+     (print_endline
+       ((STRCAT "mem["
+           ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))) in sail2_state_monad$bindS
+   (RISCV_write addr width data) (\ (w__0 : bool) . 
+   sail2_state_monad$returnS (if w__0 then MemValue () 
+           else MemException E_SAMO_Access_Fault))))`;
+
+
+(*val checked_mem_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)=
+    (if ((within_mmio_writable addr width)) then mmio_write addr width data
+   else if ((within_phys_mem addr width)) then phys_mem_write addr width data
+   else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val MEMval : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+(*val MEMval_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+(*val MEMval_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+(*val MEMval_conditional : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+(*val MEMval_conditional_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+(*val MEMval_conditional_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+(*val mem_write_value : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width value aq rl con=
+    (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+     sail2_state_monad$returnS (MemException E_SAMO_Addr_Align)
+   else
+     (case (aq, rl, con) of
+       (F, F, F) => checked_mem_write addr width value
+     | (F, T, F) => MEMval_release addr width value
+     | (F, F, T) => MEMval_conditional addr width value
+     | (F, T, T) => MEMval_conditional_release addr width value
+     | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq")
+     | (T, T, F) => MEMval_strong_release addr width value
+     | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq")
+     | (T, T, T) => MEMval_conditional_strong_release addr width value
+     )))`;
+
+
+val _ = Define `
+ ((PAGESIZE_BITS:int)=  ((( 12 : int):ii)))`;
+
+
+(*val Mk_PTE_Bits : mword ty8 -> PTE_Bits*)
+
+val _ = Define `
+ ((Mk_PTE_Bits:(8)words$word -> PTE_Bits) v=
+    (<| PTE_Bits_PTE_Bits_chunk_0 := ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)) |>))`;
+
+
+(*val _get_PTE_Bits_bits : PTE_Bits -> mword ty8*)
+
+val _ = Define `
+ ((get_PTE_Bits_bits:PTE_Bits ->(8)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+
+
+(*val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_PTE_Bits_bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits_bits:PTE_Bits ->(8)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) v=  ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+            :  8 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+    ((v with<|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word))
+          :  8 words$word))|>)))`;
+
+
+(*val isPTEPtr : mword ty8 -> bool*)
+
+val _ = Define `
+ ((isPTEPtr:(8)words$word -> bool) p=
+    (let a = (Mk_PTE_Bits p) in
+   ((((((get_PTE_Bits_R a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ ((((((((get_PTE_Bits_W a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ (((((get_PTE_Bits_X a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))))))))`;
+
+
+(*val isInvalidPTE : mword ty8 -> bool*)
+
+val _ = Define `
+ ((isInvalidPTE:(8)words$word -> bool) p=
+    (let a = (Mk_PTE_Bits p) in
+   ((((((get_PTE_Bits_V a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ ((((((((get_PTE_Bits_W a  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_R a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))))))))`;
+
+
+(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*)
+
+val _ = Define `
+ ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p :
+  PTE_Bits)=
+    ((case (ac, priv) of
+     (Read, User) =>
+      sail2_state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr)))))))))
+   | (Write, User) =>
+      sail2_state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (ReadWrite, User) =>
+      sail2_state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr))))))))))))
+   | (Execute, User) =>
+      sail2_state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (Read, Supervisor) =>
+      sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr)))))))))
+   | (Write, Supervisor) =>
+      sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (ReadWrite, Supervisor) =>
+      sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr))))))))))))
+   | (Execute, Supervisor) =>
+      sail2_state_monad$returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ (((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (_, Machine) => internal_error "m-mode mem perm check"
+   )))`;
+
+
+(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits:PTE_Bits -> AccessType ->(PTE_Bits)option) (p : PTE_Bits) (a : AccessType)=
+    (let update_d =
+     (((((((((accessType_to_str a)) = ((accessType_to_str Write))))) \/ (((((accessType_to_str a)) = ((accessType_to_str ReadWrite)))))))) /\ (((((get_PTE_Bits_D p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))) in
+   let update_a = (((get_PTE_Bits_A p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))) in
+   if (((update_d \/ update_a))) then
+     let np = (update_PTE_Bits_A p ((bool_to_bits T  :  1 words$word))) in
+     let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits T  :  1 words$word)) else np) in
+     SOME np
+   else NONE))`;
+
+
+(*val PTW_Error_of_num : integer -> PTW_Error*)
+
+val _ = Define `
+ ((PTW_Error_of_num:int -> PTW_Error) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then PTW_Access
+   else if (((p0_ = (( 1 : int):ii)))) then PTW_Invalid_PTE
+   else if (((p0_ = (( 2 : int):ii)))) then PTW_No_Permission
+   else if (((p0_ = (( 3 : int):ii)))) then PTW_Misaligned
+   else PTW_PTE_Update))`;
+
+
+(*val num_of_PTW_Error : PTW_Error -> integer*)
+
+val _ = Define `
+ ((num_of_PTW_Error:PTW_Error -> int) arg_=
+    ((case arg_ of
+     PTW_Access => (( 0 : int):ii)
+   | PTW_Invalid_PTE => (( 1 : int):ii)
    | PTW_No_Permission => (( 2 : int):ii)
    | PTW_Misaligned => (( 3 : int):ii)
    | PTW_PTE_Update => (( 4 : int):ii)
    )))`;
 
 
-(*val translationException : AccessType -> PTW_Error -> ExceptionType*)
+(*val ptw_error_to_str : PTW_Error -> string*)
+
+val _ = Define `
+ ((ptw_error_to_str:PTW_Error -> string) e=
+    ((case e of
+     PTW_Access => "mem-access-error"
+   | PTW_Invalid_PTE => "invalid-pte"
+   | PTW_No_Permission => "no-permission"
+   | PTW_Misaligned => "misaligned-superpage"
+   | PTW_PTE_Update => "pte-update-needed"
+   )))`;
+
+
+(*val translationException : AccessType -> PTW_Error -> ExceptionType*)
+
+val _ = Define `
+ ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)=
+    (let (e : ExceptionType) =
+     ((case (a, f) of
+       (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+     | (ReadWrite, _) => E_SAMO_Page_Fault
+     | (Read, PTW_Access) => E_Load_Access_Fault
+     | (Read, _) => E_Load_Page_Fault
+     | (Write, PTW_Access) => E_SAMO_Access_Fault
+     | (Write, _) => E_SAMO_Page_Fault
+     | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+     | (Fetch, _) => E_Fetch_Page_Fault
+     )) in
+   let (_ : unit) =
+     (print_endline
+       ((STRCAT "translationException("
+           ((STRCAT ((accessType_to_str a))
+               ((STRCAT ", "
+                   ((STRCAT ((ptw_error_to_str f))
+                       ((STRCAT ") -> " ((exceptionType_to_str e))))))))))))) in
+   e))`;
+
+
+val _ = Define `
+ ((SV39_LEVEL_BITS:int)=  ((( 9 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV39_LEVELS:int)=  ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE39_LOG_SIZE:int)=  ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE39_SIZE:int)=  ((( 8 : int):ii)))`;
+
+
+(*val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV39_Vaddr:(39)words$word -> SV39_Vaddr) v=
+    (<| SV39_Vaddr_SV39_Vaddr_chunk_0 := ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii)  :  39 words$word)) |>))`;
+
+
+(*val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word) v=
+    ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)  :  39 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_bits:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii)  :  39 words$word))
+            :  39 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word -> SV39_Vaddr) v x=
+    ((v with<|
+     SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 38 : int):ii) (( 0 : int):ii)  :  39 words$word))
+          :  39 words$word))|>)))`;
+
+
+(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) v=
+    ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)  :  27 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+             ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+            :  39 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) v x=
+    ((v with<|
+     SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+           ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii)  :  27 words$word))
+          :  39 words$word))|>)))`;
+
+
+(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) v=
+    ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word))
+            :  39 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) v x=
+    ((v with<|
+     SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word))
+          :  39 words$word))|>)))`;
+
+
+(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*)
+
+(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*)
+
+(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*)
+
+(*val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr*)
+
+val _ = Define `
+ ((Mk_SV39_Paddr:(56)words$word -> SV39_Paddr) v=
+    (<| SV39_Paddr_SV39_Paddr_chunk_0 := ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word)) |>))`;
+
+
+(*val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56*)
+
+val _ = Define `
+ ((get_SV39_Paddr_bits:SV39_Paddr ->(56)words$word) v=
+    ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word)))`;
+
+
+(*val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_bits:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_Paddr_SV39_Paddr_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word))
+            :  56 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_bits:SV39_Paddr ->(56)words$word -> SV39_Paddr) v x=
+    ((v with<|
+     SV39_Paddr_SV39_Paddr_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 55 : int):ii) (( 0 : int):ii)  :  56 words$word))
+          :  56 words$word))|>)))`;
+
+
+(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) v=
+    ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)  :  44 words$word)))`;
+
+
+(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_Paddr_SV39_Paddr_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+             ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word))
+            :  56 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) v x=
+    ((v with<|
+     SV39_Paddr_SV39_Paddr_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+           ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word))
+          :  56 words$word))|>)))`;
+
+
+(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*)
+
+(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*)
+
+(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) v=
+    ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_Paddr_SV39_Paddr_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word))
+            :  56 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) v x=
+    ((v with<|
+     SV39_Paddr_SV39_Paddr_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word))
+          :  56 words$word))|>)))`;
+
+
+(*val Mk_SV39_PTE : mword ty64 -> SV39_PTE*)
+
+val _ = Define `
+ ((Mk_SV39_PTE:(64)words$word -> SV39_PTE) v=
+    (<| SV39_PTE_SV39_PTE_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) |>))`;
+
+
+val _ = Define `
+ ((get_SV39_PTE_bits:SV39_PTE ->(64)words$word) v=
+    ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV39_PTE_bits:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV39_PTE_bits:SV39_PTE ->(64)words$word -> SV39_PTE) v x=
+    ((v with<|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word))
+          :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) v=
+    ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)  :  44 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+             ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) v x=
+    ((v with<|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+           ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii)  :  44 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*)
+
+val _ = Define `
+ ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) v=  ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)  :  2 words$word)))`;
+
+
+(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+             ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) v x=
+    ((v with<|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+           ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*)
+
+val _ = Define `
+ ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) v=  ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+
+
+(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS r_ref) (\ r . 
+   let r =
+     ((r with<|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+             ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+            :  64 words$word))|>)) in
+   sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) v x=
+    ((v with<|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+           ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
+          :  64 words$word))|>)))`;
+
+
+(*val curAsid64 : unit -> M (mword ty16)*)
+
+val _ = Define `
+ ((curAsid64:unit ->(regstate)sail2_state_monad$sequential_state ->((((16)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let satp64 = (Mk_Satp64 w__0) in
+   sail2_state_monad$returnS ((get_Satp64_Asid satp64  :  16 words$word)))))`;
+
+
+(*val curPTB39 : unit -> M (mword ty56)*)
+
+val _ = Define `
+ ((curPTB39:unit ->(regstate)sail2_state_monad$sequential_state ->((((56)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let satp64 = (Mk_Satp64 w__0) in
+   sail2_state_monad$returnS ((EXTZ (( 56 : int):ii)
+              ((shiftl ((get_Satp64_PPN satp64  :  44 words$word)) PAGESIZE_BITS  :  44 words$word))
+             :  56 words$word)))))`;
+
+
+(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*)
+
+ val walk39_defn = Hol_defn "walk39" `
+ ((walk39:(39)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((PTW_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global=
+    (let va = (Mk_SV39_Vaddr vaddr) in
+   let (pt_ofs : paddr39) =
+     ((shiftl
+        ((EXTZ (( 56 : int):ii)
+            ((subrange_vec_dec
+                ((shiftr ((get_SV39_Vaddr_VPNi va  :  27 words$word))
+                    ((level * SV39_LEVEL_BITS))
+                   :  27 words$word)) ((SV39_LEVEL_BITS - (( 1 : int):ii))) (( 0 : int):ii)
+               :  9 words$word))
+           :  56 words$word)) PTE39_LOG_SIZE
+       :  56 words$word)) in
+   let pte_addr = ((add_vec ptb pt_ofs  :  56 words$word)) in sail2_state_monad$bindS
+   (phys_mem_read Data ((EXTZ (( 64 : int):ii) pte_addr  :  64 words$word)) (( 8 : int):ii) F F F
+     : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) . 
+   (case w__0 of
+     MemException (_) =>
+      let (_ : unit) =
+        (print_endline
+          ((STRCAT "walk39(vaddr="
+              ((STRCAT ((string_of_bits vaddr))
+                  ((STRCAT " level="
+                      ((STRCAT ((stringFromInteger level))
+                          ((STRCAT " pt_base="
+                              ((STRCAT ((string_of_bits ptb))
+                                  ((STRCAT " pt_ofs="
+                                      ((STRCAT ((string_of_bits pt_ofs))
+                                          ((STRCAT " pte_addr="
+                                              ((STRCAT ((string_of_bits pte_addr))
+                                                  ": invalid pte address"))))))))))))))))))))) in
+      sail2_state_monad$returnS (PTW_Failure PTW_Access)
+   | MemValue (v) =>
+      let pte = (Mk_SV39_PTE v) in
+      let pbits = ((get_SV39_PTE_BITS pte  :  8 words$word)) in
+      let pattr = (Mk_PTE_Bits pbits) in
+      let is_global =
+        (global \/ (((((get_PTE_Bits_G pattr  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))) in
+      if ((isInvalidPTE pbits)) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+      else if ((isPTEPtr pbits)) then
+        if (((level = (( 0 : int):ii)))) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+        else
+          walk39 vaddr ac priv mxr do_sum
+            ((EXTZ (( 56 : int):ii)
+                ((shiftl ((get_SV39_PTE_PPNi pte  :  44 words$word)) PAGESIZE_BITS  :  44 words$word))
+               :  56 words$word)) ((level - (( 1 : int):ii))) is_global
+      else sail2_state_monad$bindS
+        (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) . 
+        sail2_state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission
+                else if ((level > (( 0 : int):ii))) then
+                  let mask =
+                    ((sub_vec_int
+                       ((shiftl
+                           ((xor_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                               ((xor_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                                   ((EXTZ (( 44 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  44 words$word))
+                                  :  44 words$word))
+                              :  44 words$word)) ((level * SV39_LEVEL_BITS))
+                          :  44 words$word)) (( 1 : int):ii)
+                      :  44 words$word)) in
+                  if (((((and_vec ((get_SV39_PTE_PPNi pte  :  44 words$word)) mask  :  44 words$word)) <> ((EXTZ (( 44 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  44 words$word))))) then
+                    PTW_Failure PTW_Misaligned
+                  else
+                    let ppn =
+                      ((or_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                         ((and_vec
+                             ((EXTZ (( 44 : int):ii) ((get_SV39_Vaddr_VPNi va  :  27 words$word))  :  44 words$word))
+                             mask
+                            :  44 words$word))
+                        :  44 words$word)) in
+                    PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va  :  12 words$word))
+                                   :  56 words$word),pte,pte_addr,level,is_global)
+                else
+                  PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                                  ((get_SV39_Vaddr_PgOfs va  :  12 words$word))
+                                 :  56 words$word),pte,pte_addr,level,is_global)))
+   ))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn;
+
+(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*)
+
+val _ = Define `
+ ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> SV39_PTE -> int ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((TLB39_Entry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr=
+    (let (shift : ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in
+   let (vAddrMask : vaddr39) =
+     ((sub_vec_int
+        ((shiftl
+            ((xor_vec vAddr
+                ((xor_vec vAddr ((EXTZ (( 39 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  39 words$word))
+                   :  39 words$word))
+               :  39 words$word)) shift
+           :  39 words$word)) (( 1 : int):ii)
+       :  39 words$word)) in
+   let (vMatchMask : vaddr39) = ((not_vec vAddrMask  :  39 words$word)) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mcycle_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
+   sail2_state_monad$returnS (<| TLB39_Entry_asid := asid; 
+              TLB39_Entry_global := global; 
+              TLB39_Entry_pte := pte; 
+              TLB39_Entry_pteAddr := pteAddr; 
+              TLB39_Entry_vAddrMask := vAddrMask; 
+              TLB39_Entry_vMatchMask := vMatchMask; 
+              TLB39_Entry_vAddr := ((and_vec vAddr vMatchMask  :  39 words$word)); 
+              TLB39_Entry_pAddr :=
+                ((shiftl ((shiftr pAddr shift  :  56 words$word)) shift  :  56 words$word)); 
+              TLB39_Entry_age := w__0 |>))))`;
+
+
+val _ = Define `
+ ((TLBEntries:int)=  ((( 32 : int):ii)))`;
+
+
+(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*)
+
+val _ = Define `
+ ((lookupTLB39:(16)words$word ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->((((int#TLB39_Entry)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vaddr=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS tlb39_ref) (\ (w__0 :  TLB39_Entry option) . 
+   sail2_state_monad$returnS ((case w__0 of
+     NONE => NONE
+   | SOME (e) =>
+      if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr  :  39 words$word))))))))
+      then
+        SOME ((( 0 : int):ii), e)
+      else NONE
+   )))))`;
+
+
+(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> SV39_PTE ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global=  (sail2_state_monad$bindS
+   (make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . 
+   sail2_state_monad$write_regS tlb39_ref (SOME ent))))`;
+
+
+(*val writeTLB39 : ii -> TLB39_Entry -> M unit*)
+
+val _ = Define `
+ ((writeTLB39:int -> TLB39_Entry ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (idx : ii) (ent : TLB39_Entry)=  (sail2_state_monad$write_regS tlb39_ref (SOME ent)))`;
+
+
+(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*)
+
+val _ = Define `
+ ((flushTLB:((16)words$word)option ->((39)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid addr=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS tlb39_ref) (\ (w__0 :  TLB39_Entry option) . 
+   let (ent :  TLB39_Entry option) =
+     ((case (w__0, asid, addr) of
+       (NONE, _, _) => NONE
+     | (SOME (e), NONE, NONE) => NONE
+     | (SOME (e), NONE, SOME (a)) =>
+        if (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask a  :  39 words$word))))) then
+          NONE
+        else SOME e
+     | (SOME (e), SOME (i), NONE) =>
+        if ((((((e.TLB39_Entry_asid = i))) /\ ((~ e.TLB39_Entry_global))))) then NONE
+        else SOME e
+     | (SOME (e), SOME (i), SOME (a)) =>
+        if ((((((e.TLB39_Entry_asid = i))) /\ ((((((e.TLB39_Entry_vAddr = ((and_vec a e.TLB39_Entry_vMatchMask  :  39 words$word))))) /\ ((~ e.TLB39_Entry_global)))))))) then
+          NONE
+        else SOME e
+     )) in
+   sail2_state_monad$write_regS tlb39_ref ent)))`;
+
+
+(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*)
+
+val _ = Define `
+ ((translate39:(39)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((TR39_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr ac priv mxr do_sum level=  (sail2_state_monad$bindS
+   (curAsid64 ()   : ( 16 words$word) M) (\ asid .  sail2_state_monad$bindS
+   (lookupTLB39 asid vAddr) (\ (w__0 :  ((ii # TLB39_Entry))option) . 
+   (case w__0 of
+     SOME (idx,ent) =>
+      let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte  :  8 words$word))) in sail2_state_monad$bindS
+      (checkPTEPermission ac priv mxr do_sum pteBits) (\ (w__1 : bool) . 
+      if ((~ w__1)) then sail2_state_monad$returnS (TR39_Failure PTW_No_Permission)
+      else
+        (case ((update_PTE_Bits pteBits ac)) of
+          NONE =>
+           sail2_state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr
+                                    ((EXTZ (( 56 : int):ii)
+                                        ((and_vec vAddr ent.TLB39_Entry_vAddrMask  :  39 words$word))
+                                       :  56 words$word))
+                                   :  56 words$word)))
+        | SOME (pbits) =>
+           if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR39_Failure PTW_PTE_Update)
+           else
+             let (n_ent : TLB39_Entry) = ent in
+             let n_ent =
+               ((n_ent with<|
+                 TLB39_Entry_pte :=
+                   ((update_SV39_PTE_BITS ent.TLB39_Entry_pte
+                       ((get_PTE_Bits_bits pbits  :  8 words$word))))|>)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+             (writeTLB39 idx n_ent)
+             (checked_mem_write ((EXTZ (( 64 : int):ii) ent.TLB39_Entry_pteAddr  :  64 words$word)) (( 8 : int):ii)
+               ((get_SV39_PTE_bits ent.TLB39_Entry_pte  :  64 words$word)))) (\ (w__2 : unit
+               MemoryOpResult) .  sail2_state_monad$seqS
+             (case w__2 of
+               MemValue (_) => sail2_state_monad$returnS () 
+             | MemException (e) => internal_error "invalid physical address in TLB"
+             )
+             (sail2_state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr
+                                      ((EXTZ (( 56 : int):ii)
+                                          ((and_vec vAddr ent.TLB39_Entry_vAddrMask  :  39 words$word))
+                                         :  56 words$word))
+                                     :  56 words$word)))))
+        ))
+   | NONE => sail2_state_monad$bindS
+      (curPTB39 ()   : ( 56 words$word) M) (\ (w__6 :  56 words$word) .  sail2_state_monad$bindS
+      (walk39 vAddr ac priv mxr do_sum w__6 level F) (\ (w__7 : PTW_Result) . 
+      (case w__7 of
+        PTW_Failure (f) => sail2_state_monad$returnS (TR39_Failure f)
+      | PTW_Success (pAddr,pte,pteAddr,level,global) =>
+         (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV39_PTE_BITS pte  :  8 words$word)))) ac)) of
+           NONE => sail2_state_monad$seqS
+            (addToTLB39 asid vAddr pAddr pte pteAddr level global) (sail2_state_monad$returnS (TR39_Address pAddr))
+         | SOME (pbits) =>
+            if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR39_Failure PTW_PTE_Update)
+            else
+              let (w_pte : SV39_PTE) =
+                (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits  :  8 words$word))) in sail2_state_monad$bindS
+              (checked_mem_write ((EXTZ (( 64 : int):ii) pteAddr  :  64 words$word)) (( 8 : int):ii)
+                ((get_SV39_PTE_bits w_pte  :  64 words$word))) (\ (w__8 : unit MemoryOpResult) . 
+              (case w__8 of
+                MemValue (_) => sail2_state_monad$seqS
+                 (addToTLB39 asid vAddr pAddr w_pte pteAddr level global)
+                 (sail2_state_monad$returnS (TR39_Address pAddr))
+              | MemException (e) => sail2_state_monad$returnS (TR39_Failure PTW_Access)
+              ))
+         )
+      )))
+   )))))`;
+
+
+(*val translationMode : Privilege -> M SATPMode*)
+
+val _ = Define `
+ ((translationMode:Privilege ->(regstate)sail2_state_monad$sequential_state ->(((SATPMode),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv=
+    (if (((((privLevel_to_bits priv  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))))
+   then
+     sail2_state_monad$returnS Sbare
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . 
+     let arch = (architecture ((get_Mstatus_SXL w__0  :  2 words$word))) in
+     (case arch of
+       SOME (RV64) => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+        let (mbits : satp_mode) = ((get_Satp64_Mode ((Mk_Satp64 w__1))  :  4 words$word)) in
+        (case ((satpMode_of_bits RV64 mbits)) of
+          SOME (m) => sail2_state_monad$returnS m
+        | NONE => internal_error "invalid RV64 translation mode in satp"
+        ))
+     | _ => internal_error "unsupported address translation arch"
+     ))))`;
+
+
+(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*)
+
+val _ = Define `
+ ((translateAddr:(64)words$word -> AccessType -> ReadType ->(regstate)sail2_state_monad$sequential_state ->(((TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr ac rt=  (sail2_state_monad$bindS
+   (case rt of
+     Instruction => sail2_state_monad$read_regS cur_privilege_ref
+   | Data => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . 
+      if (((((get_Mstatus_MPRV w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then sail2_state_monad$bindS
+        (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . 
+        sail2_state_monad$returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2  :  2 words$word)))))
+      else sail2_state_monad$read_regS cur_privilege_ref)
+   ) (\ (effPriv : Privilege) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . 
+   let (mxr : bool) =
+     (((get_Mstatus_MXR w__5  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) . 
+   let (do_sum : bool) =
+     (((get_Mstatus_SUM w__6  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))) in sail2_state_monad$bindS
+   (translationMode effPriv) (\ (mode : SATPMode) .  
+  (case mode of
+        Sbare => sail2_state_monad$returnS (TR_Address vAddr)
+    | SV39 => sail2_state_monad$bindS
+                (translate39
+                   ((subrange_vec_dec vAddr (( 38 : int): ii)
+                       (( 0 : int): ii) : 39 words$word)) ac effPriv 
+                 mxr do_sum ((SV39_LEVELS - (( 1 : int): ii))))
+                (\ (w__7 : TR39_Result) . 
+                 sail2_state_monad$returnS
+                   ((case w__7 of
+                          TR39_Address (pa) => TR_Address
+                                                 ((EXTZ (( 64 : int): ii) pa : 64 words$word))
+                      | TR39_Failure (f) => TR_Failure
+                                              ((translationException ac f))
+                    )))
+  )))))))`;
+
+
+(*val decode : mword ty32 -> maybe ast*)
+
+(*val decodeCompressed : mword ty16 -> maybe ast*)
+
+(*val execute : ast -> M bool*)
+
+(*val print_insn : ast -> string*)
+
+(*val encdec_uop_forwards : uop -> mword ty7*)
+
+val _ = Define `
+ ((encdec_uop_forwards:uop ->(7)words$word) arg_=
+    ((case arg_ of
+     RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1]  :  7 words$word)
+   | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1]  :  7 words$word)
+   )))`;
+
+
+(*val encdec_uop_backwards : mword ty7 -> uop*)
+
+val _ = Define `
+ ((encdec_uop_backwards:(7)words$word -> uop) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1]  :  7 words$word)))) then RISCV_LUI
+   else RISCV_AUIPC))`;
+
+
+(*val encdec_uop_forwards_matches : uop -> bool*)
+
+val _ = Define `
+ ((encdec_uop_forwards_matches:uop -> bool) arg_= 
+  ((case arg_ of   RISCV_LUI => T | RISCV_AUIPC => T )))`;
+
+
+(*val encdec_uop_backwards_matches : mword ty7 -> bool*)
+
+val _ = Define `
+ ((encdec_uop_backwards_matches:(7)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1]  :  7 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1]  :  7 words$word)))) then T
+   else F))`;
+
+
+(*val utype_mnemonic_forwards : uop -> string*)
+
+val _ = Define `
+ ((utype_mnemonic_forwards:uop -> string) arg_=  ((case arg_ of   RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" )))`;
+
+
+(*val utype_mnemonic_backwards : string -> uop*)
+
+val _ = Define `
+ ((utype_mnemonic_backwards:string -> uop) arg_=
+    ((case arg_ of   "lui" => RISCV_LUI | "auipc" => RISCV_AUIPC )))`;
+
+
+(*val utype_mnemonic_forwards_matches : uop -> bool*)
+
+val _ = Define `
+ ((utype_mnemonic_forwards_matches:uop -> bool) arg_= 
+  ((case arg_ of   RISCV_LUI => T | RISCV_AUIPC => T )))`;
+
+
+(*val utype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((utype_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of   "lui" => T | "auipc" => T | _ => F )))`;
+
+
+(*val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))*)
+
+val _ = Define `
+ ((utype_mnemonic_matches_prefix:string ->(uop#int)option) arg_=
+    (let stringappend_1714_0 = arg_ in
+   if (((((string_startswith stringappend_1714_0 "lui")) /\ (
+  (case ((string_drop stringappend_1714_0 ((string_length "lui")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1714_0 ((string_length "lui")))) of
+       s_ => SOME (RISCV_LUI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1714_0 "auipc")) /\ (
+  (case ((string_drop stringappend_1714_0 ((string_length "auipc")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1714_0 ((string_length "auipc")))) of
+       s_ => SOME (RISCV_AUIPC, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val encdec_bop_forwards : bop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_bop_forwards:bop ->(3)words$word) arg_=
+    ((case arg_ of
+     RISCV_BEQ => (vec_of_bits [B0;B0;B0]  :  3 words$word)
+   | RISCV_BNE => (vec_of_bits [B0;B0;B1]  :  3 words$word)
+   | RISCV_BLT => (vec_of_bits [B1;B0;B0]  :  3 words$word)
+   | RISCV_BGE => (vec_of_bits [B1;B0;B1]  :  3 words$word)
+   | RISCV_BLTU => (vec_of_bits [B1;B1;B0]  :  3 words$word)
+   | RISCV_BGEU => (vec_of_bits [B1;B1;B1]  :  3 words$word)
+   )))`;
+
+
+(*val encdec_bop_backwards : mword ty3 -> bop*)
+
+val _ = Define `
+ ((encdec_bop_backwards:(3)words$word -> bop) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then RISCV_BEQ
+   else if (((p0_ = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then RISCV_BNE
+   else if (((p0_ = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then RISCV_BLT
+   else if (((p0_ = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then RISCV_BGE
+   else if (((p0_ = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then RISCV_BLTU
+   else RISCV_BGEU))`;
+
+
+(*val encdec_bop_forwards_matches : bop -> bool*)
+
+val _ = Define `
+ ((encdec_bop_forwards_matches:bop -> bool) arg_= 
+  ((case arg_ of
+         RISCV_BEQ => T
+     | RISCV_BNE => T
+     | RISCV_BLT => T
+     | RISCV_BGE => T
+     | RISCV_BLTU => T
+     | RISCV_BGEU => T
+   )))`;
+
+
+(*val encdec_bop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_bop_backwards_matches:(3)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) then T
+   else F))`;
+
+
+(*val btype_mnemonic_forwards : bop -> string*)
+
+val _ = Define `
+ ((btype_mnemonic_forwards:bop -> string) arg_=
+    ((case arg_ of
+     RISCV_BEQ => "beq"
+   | RISCV_BNE => "bne"
+   | RISCV_BLT => "blt"
+   | RISCV_BGE => "bge"
+   | RISCV_BLTU => "bltu"
+   | RISCV_BGEU => "bgeu"
+   )))`;
+
+
+(*val btype_mnemonic_backwards : string -> bop*)
+
+val _ = Define `
+ ((btype_mnemonic_backwards:string -> bop) arg_=
+    ((case arg_ of
+     "beq" => RISCV_BEQ
+   | "bne" => RISCV_BNE
+   | "blt" => RISCV_BLT
+   | "bge" => RISCV_BGE
+   | "bltu" => RISCV_BLTU
+   | "bgeu" => RISCV_BGEU
+   )))`;
+
+
+(*val btype_mnemonic_forwards_matches : bop -> bool*)
+
+val _ = Define `
+ ((btype_mnemonic_forwards_matches:bop -> bool) arg_= 
+  ((case arg_ of
+         RISCV_BEQ => T
+     | RISCV_BNE => T
+     | RISCV_BLT => T
+     | RISCV_BGE => T
+     | RISCV_BLTU => T
+     | RISCV_BGEU => T
+   )))`;
+
+
+(*val btype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((btype_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "beq" => T
+   | "bne" => T
+   | "blt" => T
+   | "bge" => T
+   | "bltu" => T
+   | "bgeu" => T
+   | _ => F
+   )))`;
+
+
+(*val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))*)
+
+val _ = Define `
+ ((btype_mnemonic_matches_prefix:string ->(bop#int)option) arg_=
+    (let stringappend_1708_0 = arg_ in
+   if (((((string_startswith stringappend_1708_0 "beq")) /\ (
+  (case ((string_drop stringappend_1708_0 ((string_length "beq")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1708_0 ((string_length "beq")))) of
+       s_ => SOME (RISCV_BEQ, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1708_0 "bne")) /\ (
+  (case ((string_drop stringappend_1708_0 ((string_length "bne")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1708_0 ((string_length "bne")))) of
+       s_ => SOME (RISCV_BNE, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1708_0 "blt")) /\ (
+  (case ((string_drop stringappend_1708_0 ((string_length "blt")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1708_0 ((string_length "blt")))) of
+       s_ => SOME (RISCV_BLT, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1708_0 "bge")) /\ (
+  (case ((string_drop stringappend_1708_0 ((string_length "bge")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1708_0 ((string_length "bge")))) of
+       s_ => SOME (RISCV_BGE, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1708_0 "bltu")) /\ (
+  (case ((string_drop stringappend_1708_0 ((string_length "bltu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1708_0 ((string_length "bltu")))) of
+       s_ => SOME (RISCV_BLTU, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1708_0 "bgeu")) /\ (
+  (case ((string_drop stringappend_1708_0 ((string_length "bgeu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1708_0 ((string_length "bgeu")))) of
+       s_ => SOME (RISCV_BGEU, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val encdec_iop_forwards : iop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_iop_forwards:iop ->(3)words$word) arg_=
+    ((case arg_ of
+     RISCV_ADDI => (vec_of_bits [B0;B0;B0]  :  3 words$word)
+   | RISCV_SLTI => (vec_of_bits [B0;B1;B0]  :  3 words$word)
+   | RISCV_SLTIU => (vec_of_bits [B0;B1;B1]  :  3 words$word)
+   | RISCV_XORI => (vec_of_bits [B1;B0;B0]  :  3 words$word)
+   | RISCV_ORI => (vec_of_bits [B1;B1;B0]  :  3 words$word)
+   | RISCV_ANDI => (vec_of_bits [B1;B1;B1]  :  3 words$word)
+   )))`;
+
+
+(*val encdec_iop_backwards : mword ty3 -> iop*)
+
+val _ = Define `
+ ((encdec_iop_backwards:(3)words$word -> iop) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then RISCV_ADDI
+   else if (((p0_ = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then RISCV_SLTI
+   else if (((p0_ = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then RISCV_SLTIU
+   else if (((p0_ = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then RISCV_XORI
+   else if (((p0_ = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then RISCV_ORI
+   else RISCV_ANDI))`;
+
+
+(*val encdec_iop_forwards_matches : iop -> bool*)
+
+val _ = Define `
+ ((encdec_iop_forwards_matches:iop -> bool) arg_= 
+  ((case arg_ of
+         RISCV_ADDI => T
+     | RISCV_SLTI => T
+     | RISCV_SLTIU => T
+     | RISCV_XORI => T
+     | RISCV_ORI => T
+     | RISCV_ANDI => T
+   )))`;
+
+
+(*val encdec_iop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_iop_backwards_matches:(3)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) then T
+   else F))`;
+
+
+(*val itype_mnemonic_forwards : iop -> string*)
+
+val _ = Define `
+ ((itype_mnemonic_forwards:iop -> string) arg_=
+    ((case arg_ of
+     RISCV_ADDI => "addi"
+   | RISCV_SLTI => "slti"
+   | RISCV_SLTIU => "sltiu"
+   | RISCV_XORI => "xori"
+   | RISCV_ORI => "ori"
+   | RISCV_ANDI => "andi"
+   )))`;
+
+
+(*val itype_mnemonic_backwards : string -> iop*)
+
+val _ = Define `
+ ((itype_mnemonic_backwards:string -> iop) arg_=
+    ((case arg_ of
+     "addi" => RISCV_ADDI
+   | "slti" => RISCV_SLTI
+   | "sltiu" => RISCV_SLTIU
+   | "xori" => RISCV_XORI
+   | "ori" => RISCV_ORI
+   | "andi" => RISCV_ANDI
+   )))`;
+
+
+(*val itype_mnemonic_forwards_matches : iop -> bool*)
+
+val _ = Define `
+ ((itype_mnemonic_forwards_matches:iop -> bool) arg_= 
+  ((case arg_ of
+         RISCV_ADDI => T
+     | RISCV_SLTI => T
+     | RISCV_SLTIU => T
+     | RISCV_XORI => T
+     | RISCV_ORI => T
+     | RISCV_ANDI => T
+   )))`;
+
+
+(*val itype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((itype_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "addi" => T
+   | "slti" => T
+   | "sltiu" => T
+   | "xori" => T
+   | "ori" => T
+   | "andi" => T
+   | _ => F
+   )))`;
+
+
+(*val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))*)
+
+val _ = Define `
+ ((itype_mnemonic_matches_prefix:string ->(iop#int)option) arg_=
+    (let stringappend_1702_0 = arg_ in
+   if (((((string_startswith stringappend_1702_0 "addi")) /\ (
+  (case ((string_drop stringappend_1702_0 ((string_length "addi")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1702_0 ((string_length "addi")))) of
+       s_ => SOME (RISCV_ADDI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1702_0 "slti")) /\ (
+  (case ((string_drop stringappend_1702_0 ((string_length "slti")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1702_0 ((string_length "slti")))) of
+       s_ => SOME (RISCV_SLTI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1702_0 "sltiu")) /\ (
+  (case ((string_drop stringappend_1702_0 ((string_length "sltiu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1702_0 ((string_length "sltiu")))) of
+       s_ => SOME (RISCV_SLTIU, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1702_0 "xori")) /\ (
+  (case ((string_drop stringappend_1702_0 ((string_length "xori")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1702_0 ((string_length "xori")))) of
+       s_ => SOME (RISCV_XORI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1702_0 "ori")) /\ (
+  (case ((string_drop stringappend_1702_0 ((string_length "ori")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1702_0 ((string_length "ori")))) of
+       s_ => SOME (RISCV_ORI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1702_0 "andi")) /\ (
+  (case ((string_drop stringappend_1702_0 ((string_length "andi")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1702_0 ((string_length "andi")))) of
+       s_ => SOME (RISCV_ANDI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val encdec_sop_forwards : sop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_sop_forwards:sop ->(3)words$word) arg_=
+    ((case arg_ of
+     RISCV_SLLI => (vec_of_bits [B0;B0;B1]  :  3 words$word)
+   | RISCV_SRLI => (vec_of_bits [B1;B0;B1]  :  3 words$word)
+   | RISCV_SRAI => (vec_of_bits [B1;B0;B1]  :  3 words$word)
+   )))`;
+
+
+(*val encdec_sop_backwards : mword ty3 -> sop*)
+
+val _ = Define `
+ ((encdec_sop_backwards:(3)words$word -> sop) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then RISCV_SLLI
+   else if (((p0_ = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then RISCV_SRLI
+   else RISCV_SRAI))`;
+
+
+(*val encdec_sop_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((encdec_sop_forwards_matches:sop -> bool) arg_= 
+  ((case arg_ of   RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val encdec_sop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_sop_backwards_matches:(3)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then T
+   else F))`;
+
+
+(*val shiftiop_mnemonic_forwards : sop -> string*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_forwards:sop -> string) arg_=
+    ((case arg_ of   RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`;
+
+
+(*val shiftiop_mnemonic_backwards : string -> sop*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_backwards:string -> sop) arg_=
+    ((case arg_ of   "slli" => RISCV_SLLI | "srli" => RISCV_SRLI | "srai" => RISCV_SRAI )))`;
+
+
+(*val shiftiop_mnemonic_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_forwards_matches:sop -> bool) arg_= 
+  ((case arg_ of   RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val shiftiop_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of   "slli" => T | "srli" => T | "srai" => T | _ => F )))`;
+
+
+(*val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_matches_prefix:string ->(sop#int)option) arg_=
+    (let stringappend_1699_0 = arg_ in
+   if (((((string_startswith stringappend_1699_0 "slli")) /\ (
+  (case ((string_drop stringappend_1699_0 ((string_length "slli")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1699_0 ((string_length "slli")))) of
+       s_ => SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1699_0 "srli")) /\ (
+  (case ((string_drop stringappend_1699_0 ((string_length "srli")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1699_0 ((string_length "srli")))) of
+       s_ => SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1699_0 "srai")) /\ (
+  (case ((string_drop stringappend_1699_0 ((string_length "srai")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1699_0 ((string_length "srai")))) of
+       s_ => SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val rtype_mnemonic_forwards : rop -> string*)
+
+val _ = Define `
+ ((rtype_mnemonic_forwards:rop -> string) arg_=
+    ((case arg_ of
+     RISCV_ADD => "add"
+   | RISCV_SUB => "sub"
+   | RISCV_SLL => "sll"
+   | RISCV_SLT => "slt"
+   | RISCV_SLTU => "sltu"
+   | RISCV_XOR => "xor"
+   | RISCV_SRL => "srl"
+   | RISCV_SRA => "sra"
+   | RISCV_OR => "or"
+   | RISCV_AND => "and"
+   )))`;
+
+
+(*val rtype_mnemonic_backwards : string -> rop*)
+
+val _ = Define `
+ ((rtype_mnemonic_backwards:string -> rop) arg_=
+    ((case arg_ of
+     "add" => RISCV_ADD
+   | "sub" => RISCV_SUB
+   | "sll" => RISCV_SLL
+   | "slt" => RISCV_SLT
+   | "sltu" => RISCV_SLTU
+   | "xor" => RISCV_XOR
+   | "srl" => RISCV_SRL
+   | "sra" => RISCV_SRA
+   | "or" => RISCV_OR
+   | "and" => RISCV_AND
+   )))`;
+
+
+(*val rtype_mnemonic_forwards_matches : rop -> bool*)
+
+val _ = Define `
+ ((rtype_mnemonic_forwards_matches:rop -> bool) arg_= 
+  ((case arg_ of
+         RISCV_ADD => T
+     | RISCV_SUB => T
+     | RISCV_SLL => T
+     | RISCV_SLT => T
+     | RISCV_SLTU => T
+     | RISCV_XOR => T
+     | RISCV_SRL => T
+     | RISCV_SRA => T
+     | RISCV_OR => T
+     | RISCV_AND => T
+   )))`;
+
+
+(*val rtype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((rtype_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "add" => T
+   | "sub" => T
+   | "sll" => T
+   | "slt" => T
+   | "sltu" => T
+   | "xor" => T
+   | "srl" => T
+   | "sra" => T
+   | "or" => T
+   | "and" => T
+   | _ => F
+   )))`;
+
+
+(*val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))*)
+
+val _ = Define `
+ ((rtype_mnemonic_matches_prefix:string ->(rop#int)option) arg_=
+    (let stringappend_1689_0 = arg_ in
+   if (((((string_startswith stringappend_1689_0 "add")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "add")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "add")))) of
+       s_ => SOME (RISCV_ADD, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "sub")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "sub")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "sub")))) of
+       s_ => SOME (RISCV_SUB, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "sll")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "sll")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "sll")))) of
+       s_ => SOME (RISCV_SLL, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "slt")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "slt")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "slt")))) of
+       s_ => SOME (RISCV_SLT, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "sltu")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "sltu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "sltu")))) of
+       s_ => SOME (RISCV_SLTU, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "xor")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "xor")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "xor")))) of
+       s_ => SOME (RISCV_XOR, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "srl")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "srl")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "srl")))) of
+       s_ => SOME (RISCV_SRL, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "sra")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "sra")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "sra")))) of
+       s_ => SOME (RISCV_SRA, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "or")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "or")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "or")))) of
+       s_ => SOME (RISCV_OR, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1689_0 "and")) /\ (
+  (case ((string_drop stringappend_1689_0 ((string_length "and")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1689_0 ((string_length "and")))) of
+       s_ => SOME (RISCV_AND, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*)
+
+val _ = Define `
+ ((extend_value:bool ->('int8_times_n words$word)MemoryOpResult ->((64)words$word)MemoryOpResult) is_unsigned value=
+    ((case value of
+     MemValue (v) =>
+      MemValue (if is_unsigned then (EXTZ (( 64 : int):ii) v  :  64 words$word)
+                else (EXTS (( 64 : int):ii) v  :  64 words$word))
+   | MemException (e) => MemException e
+   )))`;
+
+
+(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*)
+
+val _ = Define `
+ ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned=
+    ((case ((extend_value is_unsigned value  : ( 64 words$word) MemoryOpResult)) of
+     MemValue (result) => sail2_state_monad$seqS (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)
+   | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+   )))`;
+
+
+(*val check_misaligned : mword ty64 -> word_width -> bool*)
+
+val _ = Define `
+ ((check_misaligned:(64)words$word -> word_width -> bool) (vaddr : xlenbits) (width : word_width)=
+    (if ((plat_enable_misaligned_access () )) then F
+   else
+     (case width of
+       BYTE => F
+     | HALF =>
+        (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))
+     | WORD =>
+        ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ (((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))
+     | DOUBLE =>
+        ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ (((((cast_unit_vec0 ((access_vec_dec vaddr (( 2 : int):ii)))  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))))))
+     )))`;
+
+
+(*val maybe_aq_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_aq_forwards:bool -> string) arg_=  ((case arg_ of   T => ".aq" | F => "" )))`;
+
+
+(*val maybe_aq_backwards : string -> bool*)
+
+val _ = Define `
+ ((maybe_aq_backwards:string -> bool) arg_=  ((case arg_ of   ".aq" => T | "" => F )))`;
+
+
+(*val maybe_aq_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_aq_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   T => T | F => T )))`;
+
+
+(*val maybe_aq_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_aq_backwards_matches:string -> bool) arg_=  ((case arg_ of   ".aq" => T | "" => T | _ => F )))`;
+
+
+(*val maybe_aq_matches_prefix : string -> maybe ((bool * ii))*)
+
+val _ = Define `
+ ((maybe_aq_matches_prefix:string ->(bool#int)option) arg_=
+    (let stringappend_1687_0 = arg_ in
+   if (((((string_startswith stringappend_1687_0 ".aq")) /\ (
+  (case ((string_drop stringappend_1687_0 ((string_length ".aq")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1687_0 ((string_length ".aq")))) of
+       s_ => SOME (T, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1687_0 "")) /\ (
+  (case ((string_drop stringappend_1687_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1687_0 ((string_length "")))) of
+       s_ => SOME (F, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val maybe_rl_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_rl_forwards:bool -> string) arg_=  ((case arg_ of   T => ".rl" | F => "" )))`;
+
+
+(*val maybe_rl_backwards : string -> bool*)
+
+val _ = Define `
+ ((maybe_rl_backwards:string -> bool) arg_=  ((case arg_ of   ".rl" => T | "" => F )))`;
+
+
+(*val maybe_rl_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_rl_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   T => T | F => T )))`;
+
+
+(*val maybe_rl_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_rl_backwards_matches:string -> bool) arg_=  ((case arg_ of   ".rl" => T | "" => T | _ => F )))`;
+
+
+(*val maybe_rl_matches_prefix : string -> maybe ((bool * ii))*)
+
+val _ = Define `
+ ((maybe_rl_matches_prefix:string ->(bool#int)option) arg_=
+    (let stringappend_1685_0 = arg_ in
+   if (((((string_startswith stringappend_1685_0 ".rl")) /\ (
+  (case ((string_drop stringappend_1685_0 ((string_length ".rl")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1685_0 ((string_length ".rl")))) of
+       s_ => SOME (T, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1685_0 "")) /\ (
+  (case ((string_drop stringappend_1685_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1685_0 ((string_length "")))) of
+       s_ => SOME (F, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val maybe_u_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_u_forwards:bool -> string) arg_=  ((case arg_ of   T => "u" | F => "" )))`;
+
+
+(*val maybe_u_backwards : string -> bool*)
+
+val _ = Define `
+ ((maybe_u_backwards:string -> bool) arg_=  ((case arg_ of   "u" => T | "" => F )))`;
+
+
+(*val maybe_u_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_u_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   T => T | F => T )))`;
+
+
+(*val maybe_u_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_u_backwards_matches:string -> bool) arg_=  ((case arg_ of   "u" => T | "" => T | _ => F )))`;
+
+
+(*val maybe_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+val _ = Define `
+ ((maybe_u_matches_prefix:string ->(bool#int)option) arg_=
+    (let stringappend_1683_0 = arg_ in
+   if (((((string_startswith stringappend_1683_0 "u")) /\ (
+  (case ((string_drop stringappend_1683_0 ((string_length "u")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1683_0 ((string_length "u")))) of
+       s_ => SOME (T, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1683_0 "")) /\ (
+  (case ((string_drop stringappend_1683_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1683_0 ((string_length "")))) of
+       s_ => SOME (F, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val shiftw_mnemonic_forwards : sop -> string*)
+
+val _ = Define `
+ ((shiftw_mnemonic_forwards:sop -> string) arg_=
+    ((case arg_ of   RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`;
+
+
+(*val shiftw_mnemonic_backwards : string -> sop*)
+
+val _ = Define `
+ ((shiftw_mnemonic_backwards:string -> sop) arg_=
+    ((case arg_ of   "slli" => RISCV_SLLI | "srli" => RISCV_SRLI | "srai" => RISCV_SRAI )))`;
+
+
+(*val shiftw_mnemonic_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((shiftw_mnemonic_forwards_matches:sop -> bool) arg_= 
+  ((case arg_ of   RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val shiftw_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftw_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of   "slli" => T | "srli" => T | "srai" => T | _ => F )))`;
+
+
+(*val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+val _ = Define `
+ ((shiftw_mnemonic_matches_prefix:string ->(sop#int)option) arg_=
+    (let stringappend_1680_0 = arg_ in
+   if (((((string_startswith stringappend_1680_0 "slli")) /\ (
+  (case ((string_drop stringappend_1680_0 ((string_length "slli")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1680_0 ((string_length "slli")))) of
+       s_ => SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1680_0 "srli")) /\ (
+  (case ((string_drop stringappend_1680_0 ((string_length "srli")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1680_0 ((string_length "srli")))) of
+       s_ => SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1680_0 "srai")) /\ (
+  (case ((string_drop stringappend_1680_0 ((string_length "srai")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1680_0 ((string_length "srai")))) of
+       s_ => SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val rtypew_mnemonic_forwards : ropw -> string*)
+
+val _ = Define `
+ ((rtypew_mnemonic_forwards:ropw -> string) arg_=
+    ((case arg_ of
+     RISCV_ADDW => "addw"
+   | RISCV_SUBW => "subw"
+   | RISCV_SLLW => "sllw"
+   | RISCV_SRLW => "srlw"
+   | RISCV_SRAW => "sraw"
+   )))`;
+
+
+(*val rtypew_mnemonic_backwards : string -> ropw*)
 
 val _ = Define `
- ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)= 
-  ((case (a, f) of
-         (Read, PTW_Access) => E_Load_Access_Fault
-     | (Read, _) => E_Load_Page_Fault
-     | (Write, PTW_Access) => E_SAMO_Access_Fault
-     | (Write, _) => E_SAMO_Page_Fault
-     | (Fetch, PTW_Access) => E_Fetch_Access_Fault
-     | (Fetch, _) => E_Fetch_Page_Fault
+ ((rtypew_mnemonic_backwards:string -> ropw) arg_=
+    ((case arg_ of
+     "addw" => RISCV_ADDW
+   | "subw" => RISCV_SUBW
+   | "sllw" => RISCV_SLLW
+   | "srlw" => RISCV_SRLW
+   | "sraw" => RISCV_SRAW
    )))`;
 
 
+(*val rtypew_mnemonic_forwards_matches : ropw -> bool*)
+
 val _ = Define `
- ((SV39_LEVEL_BITS:int)=  ((( 9 : int):ii)))`;
+ ((rtypew_mnemonic_forwards_matches:ropw -> bool) arg_= 
+  ((case arg_ of
+         RISCV_ADDW => T
+     | RISCV_SUBW => T
+     | RISCV_SLLW => T
+     | RISCV_SRLW => T
+     | RISCV_SRAW => T
+   )))`;
 
 
+(*val rtypew_mnemonic_backwards_matches : string -> bool*)
+
 val _ = Define `
- ((SV39_LEVELS:int)=  ((( 3 : int):ii)))`;
+ ((rtypew_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "addw" => T
+   | "subw" => T
+   | "sllw" => T
+   | "srlw" => T
+   | "sraw" => T
+   | _ => F
+   )))`;
+
+
+(*val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))*)
+
+val _ = Define `
+ ((rtypew_mnemonic_matches_prefix:string ->(ropw#int)option) arg_=
+    (let stringappend_1675_0 = arg_ in
+   if (((((string_startswith stringappend_1675_0 "addw")) /\ (
+  (case ((string_drop stringappend_1675_0 ((string_length "addw")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1675_0 ((string_length "addw")))) of
+       s_ => SOME (RISCV_ADDW, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1675_0 "subw")) /\ (
+  (case ((string_drop stringappend_1675_0 ((string_length "subw")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1675_0 ((string_length "subw")))) of
+       s_ => SOME (RISCV_SUBW, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1675_0 "sllw")) /\ (
+  (case ((string_drop stringappend_1675_0 ((string_length "sllw")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1675_0 ((string_length "sllw")))) of
+       s_ => SOME (RISCV_SLLW, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1675_0 "srlw")) /\ (
+  (case ((string_drop stringappend_1675_0 ((string_length "srlw")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1675_0 ((string_length "srlw")))) of
+       s_ => SOME (RISCV_SRLW, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1675_0 "sraw")) /\ (
+  (case ((string_drop stringappend_1675_0 ((string_length "sraw")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1675_0 ((string_length "sraw")))) of
+       s_ => SOME (RISCV_SRAW, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
 
+(*val encdec_mul_op_forwards : bool -> bool -> bool -> mword ty3*)
 
 val _ = Define `
- ((PTE39_LOG_SIZE:int)=  ((( 3 : int):ii)))`;
+ ((encdec_mul_op_forwards:bool -> bool -> bool ->(3)words$word) arg0 arg1 arg2=
+    (let arg_ = (arg0, arg1, arg2) in
+   (case arg_ of
+     (F, T, T) => (vec_of_bits [B0;B0;B0]  :  3 words$word)
+   | (T, T, T) => (vec_of_bits [B0;B0;B1]  :  3 words$word)
+   | (T, T, F) => (vec_of_bits [B0;B1;B0]  :  3 words$word)
+   | (T, F, F) => (vec_of_bits [B0;B1;B1]  :  3 words$word)
+   )))`;
 
 
+(*val encdec_mul_op_backwards : mword ty3 -> (bool * bool * bool)*)
+
 val _ = Define `
- ((PTE39_SIZE:int)=  ((( 8 : int):ii)))`;
+ ((encdec_mul_op_backwards:(3)words$word -> bool#bool#bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then (F, T, T)
+   else if (((p0_ = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then (T, T, T)
+   else if (((p0_ = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then (T, T, F)
+   else (T, F, F)))`;
 
 
-(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*)
+(*val encdec_mul_op_forwards_matches : bool -> bool -> bool -> bool*)
 
 val _ = Define `
- ((get_SV39_Vaddr:SV39_Vaddr ->(39)words$word) (Mk_SV39_Vaddr (v))=  v)`;
+ ((encdec_mul_op_forwards_matches:bool -> bool -> bool -> bool) arg0 arg1 arg2=
+    (let arg_ = (arg0, arg1, arg2) in
+   (case arg_ of
+     (F, T, T) => T
+   | (T, T, T) => T
+   | (T, T, F) => T
+   | (T, F, F) => T
+   | _ => F
+   )))`;
 
 
-(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*)
+(*val encdec_mul_op_backwards_matches : mword ty3 -> bool*)
 
 val _ = Define `
- ((set_SV39_Vaddr:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_SV39_Vaddr v) in
-   state_monad$write_regS r_ref r)))`;
+ ((encdec_mul_op_backwards_matches:(3)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then T
+   else F))`;
 
 
-(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*)
+(*val mul_mnemonic_forwards : bool -> bool -> bool -> string*)
 
 val _ = Define `
- ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) (Mk_SV39_Vaddr (v))=  ((subrange_vec_dec v (( 38 : int):ii) (( 12 : int):ii)  :  27 words$word)))`;
+ ((mul_mnemonic_forwards:bool -> bool -> bool -> string) arg0 arg1 arg2=
+    (let arg_ = (arg0, arg1, arg2) in
+   (case arg_ of
+     (F, T, T) => "mul"
+   | (T, T, T) => "mulh"
+   | (T, T, F) => "mulhsu"
+   | (T, F, F) => "mulhu"
+   )))`;
 
 
-(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*)
+(*val mul_mnemonic_backwards : string -> (bool * bool * bool)*)
 
 val _ = Define `
- ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_Vaddr) . 
-   let r = ((get_SV39_Vaddr w__0  :  39 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 38 : int):ii) (( 12 : int):ii) v  :  39 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_Vaddr r))))`;
+ ((mul_mnemonic_backwards:string -> bool#bool#bool) arg_=
+    ((case arg_ of
+     "mul" => (F, T, T)
+   | "mulh" => (T, T, T)
+   | "mulhsu" => (T, T, F)
+   | "mulhu" => (T, F, F)
+   )))`;
 
 
-(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*)
+(*val mul_mnemonic_forwards_matches : bool -> bool -> bool -> bool*)
 
 val _ = Define `
- ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) (Mk_SV39_Vaddr (v)) x=
-    (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 : int):ii) (( 12 : int):ii) x  :  39 words$word))))`;
+ ((mul_mnemonic_forwards_matches:bool -> bool -> bool -> bool) arg0 arg1 arg2=
+    (let arg_ = (arg0, arg1, arg2) in
+   (case arg_ of
+     (F, T, T) => T
+   | (T, T, T) => T
+   | (T, T, F) => T
+   | (T, F, F) => T
+   | _ => F
+   )))`;
 
 
-(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*)
+(*val mul_mnemonic_backwards_matches : string -> bool*)
 
 val _ = Define `
- ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) (Mk_SV39_Vaddr (v))=  ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word)))`;
+ ((mul_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "mul" => T
+   | "mulh" => T
+   | "mulhsu" => T
+   | "mulhu" => T
+   | _ => F
+   )))`;
 
 
-(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*)
+(*val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))*)
+
+val _ = Define `
+ ((mul_mnemonic_matches_prefix:string ->((bool#bool#bool)#int)option) arg_=
+    (let stringappend_1671_0 = arg_ in
+   if (((((string_startswith stringappend_1671_0 "mul")) /\ (
+  (case ((string_drop stringappend_1671_0 ((string_length "mul")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1671_0 ((string_length "mul")))) of
+       s_ => SOME ((F, T, T), ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1671_0 "mulh")) /\ (
+  (case ((string_drop stringappend_1671_0 ((string_length "mulh")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1671_0 ((string_length "mulh")))) of
+       s_ => SOME ((T, T, T), ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1671_0 "mulhsu")) /\ (
+  (case ((string_drop stringappend_1671_0 ((string_length "mulhsu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1671_0 ((string_length "mulhsu")))) of
+       s_ => SOME ((T, T, F), ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1671_0 "mulhu")) /\ (
+  (case ((string_drop stringappend_1671_0 ((string_length "mulhu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1671_0 ((string_length "mulhu")))) of
+       s_ => SOME ((T, F, F), ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
+
+(*val maybe_not_u_forwards : bool -> string*)
 
 val _ = Define `
- ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_Vaddr) . 
-   let r = ((get_SV39_Vaddr w__0  :  39 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 0 : int):ii) v  :  39 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_Vaddr r))))`;
+ ((maybe_not_u_forwards:bool -> string) arg_=  ((case arg_ of   F => "u" | T => "" )))`;
 
 
-(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*)
+(*val maybe_not_u_backwards : string -> bool*)
 
 val _ = Define `
- ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) (Mk_SV39_Vaddr (v)) x=
-    (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) x  :  39 words$word))))`;
+ ((maybe_not_u_backwards:string -> bool) arg_=  ((case arg_ of   "u" => F | "" => T )))`;
 
 
-(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*)
+(*val maybe_not_u_forwards_matches : bool -> bool*)
 
-(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*)
+val _ = Define `
+ ((maybe_not_u_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   F => T | T => T )))`;
 
-(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*)
 
-(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*)
+(*val maybe_not_u_backwards_matches : string -> bool*)
 
 val _ = Define `
- ((get_SV39_Paddr:SV39_Paddr ->(56)words$word) (Mk_SV39_Paddr (v))=  v)`;
+ ((maybe_not_u_backwards_matches:string -> bool) arg_=  ((case arg_ of   "u" => T | "" => T | _ => F )))`;
 
 
-(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*)
+(*val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))*)
 
 val _ = Define `
- ((set_SV39_Paddr:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_SV39_Paddr v) in
-   state_monad$write_regS r_ref r)))`;
+ ((maybe_not_u_matches_prefix:string ->(bool#int)option) arg_=
+    (let stringappend_1669_0 = arg_ in
+   if (((((string_startswith stringappend_1669_0 "u")) /\ (
+  (case ((string_drop stringappend_1669_0 ((string_length "u")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1669_0 ((string_length "u")))) of
+       s_ => SOME (F, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1669_0 "")) /\ (
+  (case ((string_drop stringappend_1669_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1669_0 ((string_length "")))) of
+       s_ => SOME (T, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
-(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*)
+(*val bit_maybe_r_forwards : mword ty1 -> string*)
 
 val _ = Define `
- ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) (Mk_SV39_Paddr (v))=  ((subrange_vec_dec v (( 55 : int):ii) (( 12 : int):ii)  :  44 words$word)))`;
+ ((bit_maybe_r_forwards:(1)words$word -> string) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then "r"
+   else ""))`;
 
 
-(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*)
+(*val bit_maybe_r_backwards : string -> mword ty1*)
 
 val _ = Define `
- ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_Paddr) . 
-   let r = ((get_SV39_Paddr w__0  :  56 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 55 : int):ii) (( 12 : int):ii) v  :  56 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_Paddr r))))`;
+ ((bit_maybe_r_backwards:string ->(1)words$word) arg_=
+    ((case arg_ of
+     "r" => (vec_of_bits [B1]  :  1 words$word)
+   | "" => (vec_of_bits [B0]  :  1 words$word)
+   )))`;
 
 
-(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*)
+(*val bit_maybe_r_forwards_matches : mword ty1 -> bool*)
 
 val _ = Define `
- ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) (Mk_SV39_Paddr (v)) x=
-    (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 : int):ii) (( 12 : int):ii) x  :  56 words$word))))`;
+ ((bit_maybe_r_forwards_matches:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else F))`;
 
 
-(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*)
+(*val bit_maybe_r_backwards_matches : string -> bool*)
 
-(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*)
+val _ = Define `
+ ((bit_maybe_r_backwards_matches:string -> bool) arg_=  ((case arg_ of   "r" => T | "" => T | _ => F )))`;
 
-(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*)
+
+(*val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))*)
 
 val _ = Define `
- ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) (Mk_SV39_Paddr (v))=  ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii)  :  12 words$word)))`;
+ ((bit_maybe_r_matches_prefix:string ->((1)words$word#int)option) arg_=
+    (let stringappend_1667_0 = arg_ in
+   if (((((string_startswith stringappend_1667_0 "r")) /\ (
+  (case ((string_drop stringappend_1667_0 ((string_length "r")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1667_0 ((string_length "r")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1667_0 "")) /\ (
+  (case ((string_drop stringappend_1667_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1667_0 ((string_length "")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
+(*val bit_maybe_w_forwards : mword ty1 -> string*)
+
 val _ = Define `
- ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_Paddr) . 
-   let r = ((get_SV39_Paddr w__0  :  56 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 0 : int):ii) v  :  56 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_Paddr r))))`;
+ ((bit_maybe_w_forwards:(1)words$word -> string) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then "w"
+   else ""))`;
+
 
+(*val bit_maybe_w_backwards : string -> mword ty1*)
 
 val _ = Define `
- ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) (Mk_SV39_Paddr (v)) x=
-    (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) x  :  56 words$word))))`;
+ ((bit_maybe_w_backwards:string ->(1)words$word) arg_=
+    ((case arg_ of
+     "w" => (vec_of_bits [B1]  :  1 words$word)
+   | "" => (vec_of_bits [B0]  :  1 words$word)
+   )))`;
 
 
+(*val bit_maybe_w_forwards_matches : mword ty1 -> bool*)
+
 val _ = Define `
- ((get_SV39_PTE:SV39_PTE ->(64)words$word) (Mk_SV39_PTE (v))=  v)`;
+ ((bit_maybe_w_forwards_matches:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else F))`;
 
 
+(*val bit_maybe_w_backwards_matches : string -> bool*)
+
 val _ = Define `
- ((set_SV39_PTE:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ r . 
-   let r = (Mk_SV39_PTE v) in
-   state_monad$write_regS r_ref r)))`;
+ ((bit_maybe_w_backwards_matches:string -> bool) arg_=  ((case arg_ of   "w" => T | "" => T | _ => F )))`;
+
 
+(*val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))*)
 
 val _ = Define `
- ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) (Mk_SV39_PTE (v))=  ((subrange_vec_dec v (( 53 : int):ii) (( 10 : int):ii)  :  44 words$word)))`;
+ ((bit_maybe_w_matches_prefix:string ->((1)words$word#int)option) arg_=
+    (let stringappend_1665_0 = arg_ in
+   if (((((string_startswith stringappend_1665_0 "w")) /\ (
+  (case ((string_drop stringappend_1665_0 ((string_length "w")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1665_0 ((string_length "w")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1665_0 "")) /\ (
+  (case ((string_drop stringappend_1665_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1665_0 ((string_length "")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
+
 
+(*val bit_maybe_i_forwards : mword ty1 -> string*)
 
 val _ = Define `
- ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . 
-   let r = ((get_SV39_PTE w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 53 : int):ii) (( 10 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_PTE r))))`;
+ ((bit_maybe_i_forwards:(1)words$word -> string) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then "i"
+   else ""))`;
 
 
+(*val bit_maybe_i_backwards : string -> mword ty1*)
+
 val _ = Define `
- ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x=
-    (Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 : int):ii) (( 10 : int):ii) x  :  64 words$word))))`;
+ ((bit_maybe_i_backwards:string ->(1)words$word) arg_=
+    ((case arg_ of
+     "i" => (vec_of_bits [B1]  :  1 words$word)
+   | "" => (vec_of_bits [B0]  :  1 words$word)
+   )))`;
 
 
-(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*)
+(*val bit_maybe_i_forwards_matches : mword ty1 -> bool*)
 
 val _ = Define `
- ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) (Mk_SV39_PTE (v))=  ((subrange_vec_dec v (( 9 : int):ii) (( 8 : int):ii)  :  2 words$word)))`;
+ ((bit_maybe_i_forwards_matches:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else F))`;
 
 
-(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*)
+(*val bit_maybe_i_backwards_matches : string -> bool*)
 
 val _ = Define `
- ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . 
-   let r = ((get_SV39_PTE w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 8 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_PTE r))))`;
+ ((bit_maybe_i_backwards_matches:string -> bool) arg_=  ((case arg_ of   "i" => T | "" => T | _ => F )))`;
 
 
-(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*)
+(*val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))*)
 
 val _ = Define `
- ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x=
-    (Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 : int):ii) (( 8 : int):ii) x  :  64 words$word))))`;
+ ((bit_maybe_i_matches_prefix:string ->((1)words$word#int)option) arg_=
+    (let stringappend_1663_0 = arg_ in
+   if (((((string_startswith stringappend_1663_0 "i")) /\ (
+  (case ((string_drop stringappend_1663_0 ((string_length "i")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1663_0 ((string_length "i")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1663_0 "")) /\ (
+  (case ((string_drop stringappend_1663_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1663_0 ((string_length "")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
-(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*)
+(*val bit_maybe_o_forwards : mword ty1 -> string*)
 
 val _ = Define `
- ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) (Mk_SV39_PTE (v))=  ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)))`;
+ ((bit_maybe_o_forwards:(1)words$word -> string) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then "o"
+   else ""))`;
 
 
-(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*)
+(*val bit_maybe_o_backwards : string -> mword ty1*)
 
 val _ = Define `
- ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v=  (state_monad$bindS
-   (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . 
-   let r = ((get_SV39_PTE w__0  :  64 words$word)) in
-   let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v  :  64 words$word)) in
-   state_monad$write_regS r_ref (Mk_SV39_PTE r))))`;
+ ((bit_maybe_o_backwards:string ->(1)words$word) arg_=
+    ((case arg_ of
+     "o" => (vec_of_bits [B1]  :  1 words$word)
+   | "" => (vec_of_bits [B0]  :  1 words$word)
+   )))`;
 
 
-(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*)
+(*val bit_maybe_o_forwards_matches : mword ty1 -> bool*)
 
 val _ = Define `
- ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x=
-    (Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x  :  64 words$word))))`;
+ ((bit_maybe_o_forwards_matches:(1)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B1]  :  1 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B0]  :  1 words$word)))) then T
+   else F))`;
 
 
-(*val curAsid64 : unit -> M (mword ty16)*)
+(*val bit_maybe_o_backwards_matches : string -> bool*)
 
 val _ = Define `
- ((curAsid64:unit ->(regstate)state_monad$sequential_state ->((((16)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let satp64 = (Mk_Satp64 w__0) in
-   state_monad$returnS ((get_Satp64_Asid satp64  :  16 words$word)))))`;
+ ((bit_maybe_o_backwards_matches:string -> bool) arg_=  ((case arg_ of   "o" => T | "" => T | _ => F )))`;
 
 
-(*val curPTB39 : unit -> M (mword ty56)*)
+(*val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))*)
 
 val _ = Define `
- ((curPTB39:unit ->(regstate)state_monad$sequential_state ->((((56)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let satp64 = (Mk_Satp64 w__0) in
-   state_monad$returnS ((EXTZ (( 56 : int):ii)
-              ((shiftl ((get_Satp64_PPN satp64  :  44 words$word)) PAGESIZE_BITS  :  44 words$word))
-             :  56 words$word)))))`;
+ ((bit_maybe_o_matches_prefix:string ->((1)words$word#int)option) arg_=
+    (let stringappend_1661_0 = arg_ in
+   if (((((string_startswith stringappend_1661_0 "o")) /\ (
+  (case ((string_drop stringappend_1661_0 ((string_length "o")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1661_0 ((string_length "o")))) of
+       s_ =>
+        SOME ((vec_of_bits [B1]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1661_0 "")) /\ (
+  (case ((string_drop stringappend_1661_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1661_0 ((string_length "")))) of
+       s_ =>
+        SOME ((vec_of_bits [B0]  :  1 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
-(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*)
+(*val fence_bits_forwards : mword ty4 -> string*)
 
- val walk39_defn = Hol_defn "walk39" `
- ((walk39:(39)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)state_monad$sequential_state ->(((PTW_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global=
-    (let va = (Mk_SV39_Vaddr vaddr) in
-   let (pt_ofs : paddr39) =
-     ((shiftl
-        ((EXTZ (( 56 : int):ii)
-            ((subrange_vec_dec
-                ((shiftr ((get_SV39_Vaddr_VPNi va  :  27 words$word))
-                    ((level * SV39_LEVEL_BITS))
-                   :  27 words$word)) ((SV39_LEVEL_BITS - (( 1 : int):ii))) (( 0 : int):ii)
-               :  9 words$word))
-           :  56 words$word)) PTE39_LOG_SIZE
-       :  56 words$word)) in
-   let pte_addr = ((add_vec ptb pt_ofs  :  56 words$word)) in state_monad$bindS
-   (checked_mem_read Data ((EXTZ (( 64 : int):ii) pte_addr  :  64 words$word)) (( 8 : int):ii)
-     : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) . 
-   (case w__0 of
-     MemException (_) => state_monad$returnS (PTW_Failure PTW_Access)
-   | MemValue (v) =>
-      let pte = (Mk_SV39_PTE v) in
-      let pbits = ((get_SV39_PTE_BITS pte  :  8 words$word)) in
-      let pattr = (Mk_PTE_Bits pbits) in
-      let is_global =
-        (global \/ (((((get_PTE_Bits_G pattr  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))) in
-      if ((isInvalidPTE pbits)) then state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
-      else if ((isPTEPtr pbits)) then
-        if (((level = (( 0 : int):ii)))) then state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
-        else
-          walk39 vaddr ac priv mxr do_sum
-            ((EXTZ (( 56 : int):ii)
-                ((shiftl ((get_SV39_PTE_PPNi pte  :  44 words$word)) PAGESIZE_BITS  :  44 words$word))
-               :  56 words$word)) ((level - (( 1 : int):ii))) is_global
-      else state_monad$bindS
-        (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) . 
-        state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission
-                else if ((level > (( 0 : int):ii))) then
-                  let mask =
-                    ((sub_vec_int
-                       ((shiftl
-                           ((xor_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
-                               ((xor_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
-                                   ((EXTZ (( 44 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  44 words$word))
-                                  :  44 words$word))
-                              :  44 words$word)) ((level * SV39_LEVEL_BITS))
-                          :  44 words$word)) (( 1 : int):ii)
-                      :  44 words$word)) in
-                  if (((((and_vec ((get_SV39_PTE_PPNi pte  :  44 words$word)) mask  :  44 words$word)) <> ((EXTZ (( 44 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  44 words$word))))) then
-                    PTW_Failure PTW_Misaligned
-                  else
-                    let ppn =
-                      ((or_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
-                         ((and_vec
-                             ((EXTZ (( 44 : int):ii) ((get_SV39_Vaddr_VPNi va  :  27 words$word))  :  44 words$word))
-                             mask
-                            :  44 words$word))
-                        :  44 words$word)) in
-                    PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va  :  12 words$word))
-                                   :  56 words$word),pte,pte_addr,level,is_global)
-                else
-                  PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
-                                  ((get_SV39_Vaddr_PgOfs va  :  12 words$word))
-                                 :  56 words$word),pte,pte_addr,level,is_global)))
-   ))))`;
+val _ = Define `
+ ((fence_bits_forwards:(4)words$word -> string) arg_=
+    ((case arg_ of
+     v__0 =>
+      let (r : 1 bits) = ((subrange_vec_dec v__0 (( 3 : int):ii) (( 3 : int):ii)  :  1 words$word)) in
+      let (w : 1 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
+      let (i : 1 bits) = ((subrange_vec_dec v__0 (( 1 : int):ii) (( 1 : int):ii)  :  1 words$word)) in
+      let (o1 : 1 bits) = ((subrange_vec_dec v__0 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in
+      string_append ((bit_maybe_r_forwards r))
+        ((string_append ((bit_maybe_w_forwards w))
+            ((string_append ((bit_maybe_i_forwards i))
+                ((string_append ((bit_maybe_o_forwards o1)) ""))))))
+   )))`;
 
-val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn;
 
-(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*)
+(*val fence_bits_backwards : string -> mword ty4*)
 
 val _ = Define `
- ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> SV39_PTE -> int ->(56)words$word ->(regstate)state_monad$sequential_state ->(((TLB39_Entry),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr=
-    (let (shift : ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in
-   let (vAddrMask : vaddr39) =
-     ((sub_vec_int
-        ((shiftl
-            ((xor_vec vAddr
-                ((xor_vec vAddr ((EXTZ (( 39 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  39 words$word))
-                   :  39 words$word))
-               :  39 words$word)) shift
-           :  39 words$word)) (( 1 : int):ii)
-       :  39 words$word)) in
-   let (vMatchMask : vaddr39) = ((not_vec vAddrMask  :  39 words$word)) in state_monad$bindS
-   (state_monad$read_regS mcycle_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
-   state_monad$returnS (<| TLB39_Entry_asid := asid; 
-              TLB39_Entry_global := global; 
-              TLB39_Entry_pte := pte; 
-              TLB39_Entry_pteAddr := pteAddr; 
-              TLB39_Entry_vAddrMask := vAddrMask; 
-              TLB39_Entry_vMatchMask := vMatchMask; 
-              TLB39_Entry_vAddr := ((and_vec vAddr vMatchMask  :  39 words$word)); 
-              TLB39_Entry_pAddr :=
-                ((shiftl ((shiftr pAddr shift  :  56 words$word)) shift  :  56 words$word)); 
-              TLB39_Entry_age := w__0 |>))))`;
+ ((fence_bits_backwards:string ->(4)words$word) arg_=
+    (let stringappend_1649_0 = arg_ in
+   let (r, stringappend_1651_0) =
+     ((case ((bit_maybe_r_matches_prefix stringappend_1649_0  :  (( 1 words$word # ii))option)) of
+       SOME (stringappend_1650_0,stringappend_1651_0) => (stringappend_1650_0, stringappend_1651_0)
+     )) in
+   let stringappend_1652_0 = (string_drop stringappend_1649_0 stringappend_1651_0) in
+   let (w, stringappend_1654_0) =
+     ((case ((bit_maybe_w_matches_prefix stringappend_1652_0  :  (( 1 words$word # ii))option)) of
+       SOME (stringappend_1653_0,stringappend_1654_0) => (stringappend_1653_0, stringappend_1654_0)
+     )) in
+   let stringappend_1655_0 = (string_drop stringappend_1652_0 stringappend_1654_0) in
+   let (i, stringappend_1657_0) =
+     ((case ((bit_maybe_i_matches_prefix stringappend_1655_0  :  (( 1 words$word # ii))option)) of
+       SOME (stringappend_1656_0,stringappend_1657_0) => (stringappend_1656_0, stringappend_1657_0)
+     )) in
+   let stringappend_1658_0 = (string_drop stringappend_1655_0 stringappend_1657_0) in
+   let (o1, stringappend_1660_0) =
+     ((case ((bit_maybe_o_matches_prefix stringappend_1658_0  :  (( 1 words$word # ii))option)) of
+       SOME (stringappend_1659_0,stringappend_1660_0) => (stringappend_1659_0, stringappend_1660_0)
+     )) in
+   (case ((string_drop stringappend_1658_0 stringappend_1660_0)) of
+     "" => (concat_vec r ((concat_vec w ((concat_vec i o1  :  2 words$word))  :  3 words$word))  :  4 words$word)
+   )))`;
+
+
+(*val fence_bits_forwards_matches : mword ty4 -> bool*)
+
+val _ = Define `
+ ((fence_bits_forwards_matches:(4)words$word -> bool) arg_= 
+  ((case arg_ of   v__1 => T )))`;
+
+
+(*val fence_bits_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((fence_bits_backwards_matches:string -> bool) arg_=
+    (let stringappend_1637_0 = arg_ in
+   if ((case ((bit_maybe_r_matches_prefix stringappend_1637_0  :  (( 1 words$word # ii))option)) of
+       SOME (stringappend_1638_0,stringappend_1639_0) =>
+        let stringappend_1640_0 = (string_drop stringappend_1637_0 stringappend_1639_0) in
+        if ((case ((bit_maybe_w_matches_prefix stringappend_1640_0  :  (( 1 words$word # ii))option)) of
+            SOME (stringappend_1641_0,stringappend_1642_0) =>
+             let stringappend_1643_0 = (string_drop stringappend_1640_0 stringappend_1642_0) in
+             if ((case ((bit_maybe_i_matches_prefix stringappend_1643_0  :  (( 1 words$word # ii))option)) of
+                 SOME (stringappend_1644_0,stringappend_1645_0) =>
+                  let stringappend_1646_0 = (string_drop stringappend_1643_0 stringappend_1645_0) in
+                  if ((case ((bit_maybe_o_matches_prefix stringappend_1646_0
+                               :  (( 1 words$word # ii))option)) of
+                      SOME (stringappend_1647_0,stringappend_1648_0) =>
+                       (case ((string_drop stringappend_1646_0 stringappend_1648_0)) of
+                         "" => T
+                       | _ => F
+                       )
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (r, stringappend_1639_0) =
+       ((case ((bit_maybe_r_matches_prefix stringappend_1637_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1638_0,stringappend_1639_0) =>
+          (stringappend_1638_0, stringappend_1639_0)
+       )) in
+     let stringappend_1640_0 = (string_drop stringappend_1637_0 stringappend_1639_0) in
+     let (w, stringappend_1642_0) =
+       ((case ((bit_maybe_w_matches_prefix stringappend_1640_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1641_0,stringappend_1642_0) =>
+          (stringappend_1641_0, stringappend_1642_0)
+       )) in
+     let stringappend_1643_0 = (string_drop stringappend_1640_0 stringappend_1642_0) in
+     let (i, stringappend_1645_0) =
+       ((case ((bit_maybe_i_matches_prefix stringappend_1643_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1644_0,stringappend_1645_0) =>
+          (stringappend_1644_0, stringappend_1645_0)
+       )) in
+     let stringappend_1646_0 = (string_drop stringappend_1643_0 stringappend_1645_0) in
+     let (o1, stringappend_1648_0) =
+       ((case ((bit_maybe_o_matches_prefix stringappend_1646_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1647_0,stringappend_1648_0) =>
+          (stringappend_1647_0, stringappend_1648_0)
+       )) in
+     (case ((string_drop stringappend_1646_0 stringappend_1648_0)) of   "" => T )
+   else F))`;
+
+
+(*val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))*)
+
+val _ = Define `
+ ((fence_bits_matches_prefix:string ->((4)words$word#int)option) arg_=
+    (let stringappend_1625_0 = arg_ in
+   if ((case ((bit_maybe_r_matches_prefix stringappend_1625_0  :  (( 1 words$word # ii))option)) of
+       SOME (stringappend_1626_0,stringappend_1627_0) =>
+        let stringappend_1628_0 = (string_drop stringappend_1625_0 stringappend_1627_0) in
+        if ((case ((bit_maybe_w_matches_prefix stringappend_1628_0  :  (( 1 words$word # ii))option)) of
+            SOME (stringappend_1629_0,stringappend_1630_0) =>
+             let stringappend_1631_0 = (string_drop stringappend_1628_0 stringappend_1630_0) in
+             if ((case ((bit_maybe_i_matches_prefix stringappend_1631_0  :  (( 1 words$word # ii))option)) of
+                 SOME (stringappend_1632_0,stringappend_1633_0) =>
+                  let stringappend_1634_0 = (string_drop stringappend_1631_0 stringappend_1633_0) in
+                  if ((case ((bit_maybe_o_matches_prefix stringappend_1634_0
+                               :  (( 1 words$word # ii))option)) of
+                      SOME (stringappend_1635_0,stringappend_1636_0) => 
+  (case ((string_drop stringappend_1634_0 stringappend_1636_0)) of   s_ => T )
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (r, stringappend_1627_0) =
+       ((case ((bit_maybe_r_matches_prefix stringappend_1625_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1626_0,stringappend_1627_0) =>
+          (stringappend_1626_0, stringappend_1627_0)
+       )) in
+     let stringappend_1628_0 = (string_drop stringappend_1625_0 stringappend_1627_0) in
+     let (w, stringappend_1630_0) =
+       ((case ((bit_maybe_w_matches_prefix stringappend_1628_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1629_0,stringappend_1630_0) =>
+          (stringappend_1629_0, stringappend_1630_0)
+       )) in
+     let stringappend_1631_0 = (string_drop stringappend_1628_0 stringappend_1630_0) in
+     let (i, stringappend_1633_0) =
+       ((case ((bit_maybe_i_matches_prefix stringappend_1631_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1632_0,stringappend_1633_0) =>
+          (stringappend_1632_0, stringappend_1633_0)
+       )) in
+     let stringappend_1634_0 = (string_drop stringappend_1631_0 stringappend_1633_0) in
+     let (o1, stringappend_1636_0) =
+       ((case ((bit_maybe_o_matches_prefix stringappend_1634_0  :  (( 1 words$word # ii))option)) of
+         SOME (stringappend_1635_0,stringappend_1636_0) =>
+          (stringappend_1635_0, stringappend_1636_0)
+       )) in
+     (case ((string_drop stringappend_1634_0 stringappend_1636_0)) of
+       s_ =>
+        SOME ((concat_vec r ((concat_vec w ((concat_vec i o1  :  2 words$word))  :  3 words$word))
+                :  4 words$word),
+              ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
+(*val aqrl_str : bool -> bool -> string*)
+
 val _ = Define `
- ((TLBEntries:int)=  ((( 32 : int):ii)))`;
+ ((aqrl_str:bool -> bool -> string) (aq : bool) (rl : bool)=
+    ((case (aq, rl) of
+     (F, F) => ""
+   | (F, T) => ".rl"
+   | (T, F) => ".aq"
+   | (T, T) => ".aqrl"
+   )))`;
+
+
+(*val lrsc_width_str : word_width -> string*)
+
+val _ = Define `
+ ((lrsc_width_str:word_width -> string) width=
+    ((case width of   BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" )))`;
+
+
+(*val process_loadres : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*)
+
+val _ = Define `
+ ((process_loadres:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned=
+    ((case ((extend_value is_unsigned value  : ( 64 words$word) MemoryOpResult)) of
+     MemValue (result) =>
+      let (_ : unit) = (load_reservation addr) in sail2_state_monad$seqS
+      (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)
+   | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+   )))`;
+
+
+(*val encdec_amoop_forwards : amoop -> mword ty5*)
+
+val _ = Define `
+ ((encdec_amoop_forwards:amoop ->(5)words$word) arg_=
+    ((case arg_ of
+     AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)
+   | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+   | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)
+   | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)
+   | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)
+   | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)
+   | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)
+   | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)
+   | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)
+   )))`;
+
+
+(*val encdec_amoop_backwards : mword ty5 -> amoop*)
+
+val _ = Define `
+ ((encdec_amoop_backwards:(5)words$word -> amoop) arg_=
+    (let p0_ = arg_ in
+   if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word))))))
+   then
+     AMOSWAP
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) then
+     AMOADD
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) then
+     AMOXOR
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) then
+     AMOAND
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) then
+     AMOOR
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) then
+     AMOMIN
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) then
+     AMOMAX
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) then
+     AMOMINU
+   else AMOMAXU))`;
+
+
+(*val encdec_amoop_forwards_matches : amoop -> bool*)
+
+val _ = Define `
+ ((encdec_amoop_forwards_matches:amoop -> bool) arg_= 
+  ((case arg_ of
+         AMOSWAP => T
+     | AMOADD => T
+     | AMOXOR => T
+     | AMOAND => T
+     | AMOOR => T
+     | AMOMIN => T
+     | AMOMAX => T
+     | AMOMINU => T
+     | AMOMAXU => T
+   )))`;
+
+
+(*val encdec_amoop_backwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((encdec_amoop_backwards_matches:(5)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word))))))
+   then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) then
+     T
+   else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) then
+     T
+   else F))`;
+
+
+(*val amo_mnemonic_forwards : amoop -> string*)
+
+val _ = Define `
+ ((amo_mnemonic_forwards:amoop -> string) arg_=
+    ((case arg_ of
+     AMOSWAP => "amoswap"
+   | AMOADD => "amoadd"
+   | AMOXOR => "amoxor"
+   | AMOAND => "amoand"
+   | AMOOR => "amoor"
+   | AMOMIN => "amomin"
+   | AMOMAX => "amomax"
+   | AMOMINU => "amominu"
+   | AMOMAXU => "amomaxu"
+   )))`;
+
+
+(*val amo_mnemonic_backwards : string -> amoop*)
+
+val _ = Define `
+ ((amo_mnemonic_backwards:string -> amoop) arg_=
+    ((case arg_ of
+     "amoswap" => AMOSWAP
+   | "amoadd" => AMOADD
+   | "amoxor" => AMOXOR
+   | "amoand" => AMOAND
+   | "amoor" => AMOOR
+   | "amomin" => AMOMIN
+   | "amomax" => AMOMAX
+   | "amominu" => AMOMINU
+   | "amomaxu" => AMOMAXU
+   )))`;
+
+
+(*val amo_mnemonic_forwards_matches : amoop -> bool*)
+
+val _ = Define `
+ ((amo_mnemonic_forwards_matches:amoop -> bool) arg_= 
+  ((case arg_ of
+         AMOSWAP => T
+     | AMOADD => T
+     | AMOXOR => T
+     | AMOAND => T
+     | AMOOR => T
+     | AMOMIN => T
+     | AMOMAX => T
+     | AMOMINU => T
+     | AMOMAXU => T
+   )))`;
+
+
+(*val amo_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((amo_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of
+     "amoswap" => T
+   | "amoadd" => T
+   | "amoxor" => T
+   | "amoand" => T
+   | "amoor" => T
+   | "amomin" => T
+   | "amomax" => T
+   | "amominu" => T
+   | "amomaxu" => T
+   | _ => F
+   )))`;
+
+
+(*val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))*)
+
+val _ = Define `
+ ((amo_mnemonic_matches_prefix:string ->(amoop#int)option) arg_=
+    (let stringappend_1616_0 = arg_ in
+   if (((((string_startswith stringappend_1616_0 "amoswap")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amoswap")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amoswap")))) of
+       s_ => SOME (AMOSWAP, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amoadd")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amoadd")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amoadd")))) of
+       s_ => SOME (AMOADD, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amoxor")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amoxor")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amoxor")))) of
+       s_ => SOME (AMOXOR, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amoand")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amoand")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amoand")))) of
+       s_ => SOME (AMOAND, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amoor")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amoor")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amoor")))) of
+       s_ => SOME (AMOOR, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amomin")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amomin")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amomin")))) of
+       s_ => SOME (AMOMIN, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amomax")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amomax")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amomax")))) of
+       s_ => SOME (AMOMAX, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amominu")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amominu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amominu")))) of
+       s_ => SOME (AMOMINU, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1616_0 "amomaxu")) /\ (
+  (case ((string_drop stringappend_1616_0 ((string_length "amomaxu")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1616_0 ((string_length "amomaxu")))) of
+       s_ => SOME (AMOMAXU, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
-(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*)
+(*val encdec_csrop_forwards : csrop -> mword ty2*)
 
 val _ = Define `
- ((lookupTLB39:(16)words$word ->(39)words$word ->(regstate)state_monad$sequential_state ->((((int#TLB39_Entry)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid vaddr=  (state_monad$bindS
-   (state_monad$read_regS tlb39_ref) (\ (w__0 :  TLB39_Entry option) . 
-   state_monad$returnS ((case w__0 of
-     NONE => NONE
-   | SOME (e) =>
-      if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr  :  39 words$word))))))))
-      then
-        SOME ((( 0 : int):ii), e)
-      else NONE
-   )))))`;
+ ((encdec_csrop_forwards:csrop ->(2)words$word) arg_=
+    ((case arg_ of
+     CSRRW => (vec_of_bits [B0;B1]  :  2 words$word)
+   | CSRRS => (vec_of_bits [B1;B0]  :  2 words$word)
+   | CSRRC => (vec_of_bits [B1;B1]  :  2 words$word)
+   )))`;
 
 
-(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*)
+(*val encdec_csrop_backwards : mword ty2 -> csrop*)
 
 val _ = Define `
- ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> SV39_PTE ->(56)words$word -> int -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global=  (state_monad$bindS
-   (make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . 
-   state_monad$write_regS tlb39_ref (SOME ent))))`;
+ ((encdec_csrop_backwards:(2)words$word -> csrop) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B1]  :  2 words$word)))) then CSRRW
+   else if (((p0_ = (vec_of_bits [B1;B0]  :  2 words$word)))) then CSRRS
+   else CSRRC))`;
 
 
-(*val writeTLB39 : ii -> TLB39_Entry -> M unit*)
+(*val encdec_csrop_forwards_matches : csrop -> bool*)
 
 val _ = Define `
- ((writeTLB39:int -> TLB39_Entry ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (idx : ii) (ent : TLB39_Entry)=  (state_monad$write_regS tlb39_ref (SOME ent)))`;
+ ((encdec_csrop_forwards_matches:csrop -> bool) arg_= 
+  ((case arg_ of   CSRRW => T | CSRRS => T | CSRRC => T )))`;
 
 
-(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*)
+(*val encdec_csrop_backwards_matches : mword ty2 -> bool*)
 
 val _ = Define `
- ((flushTLB:((16)words$word)option ->((39)words$word)option ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid addr=  (state_monad$bindS
-   (state_monad$read_regS tlb39_ref) (\ (w__0 :  TLB39_Entry option) . 
-   let (ent :  TLB39_Entry option) =
-     ((case (w__0, asid, addr) of
-       (NONE, _, _) => NONE
-     | (SOME (e), NONE, NONE) => NONE
-     | (SOME (e), NONE, SOME (a)) =>
-        if (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask a  :  39 words$word))))) then
-          NONE
-        else SOME e
-     | (SOME (e), SOME (i), NONE) =>
-        if ((((((e.TLB39_Entry_asid = i))) /\ ((~ e.TLB39_Entry_global))))) then NONE
-        else SOME e
-     | (SOME (e), SOME (i), SOME (a)) =>
-        if ((((((e.TLB39_Entry_asid = i))) /\ ((((((e.TLB39_Entry_vAddr = ((and_vec a e.TLB39_Entry_vMatchMask  :  39 words$word))))) /\ ((~ e.TLB39_Entry_global)))))))) then
-          NONE
-        else SOME e
-     )) in
-   state_monad$write_regS tlb39_ref ent)))`;
+ ((encdec_csrop_backwards_matches:(2)words$word -> bool) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (vec_of_bits [B0;B1]  :  2 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B0]  :  2 words$word)))) then T
+   else if (((p0_ = (vec_of_bits [B1;B1]  :  2 words$word)))) then T
+   else F))`;
 
 
+(*val readCSR : mword ty12 -> M (mword ty64)*)
+
 val _ = Define `
- ((enable_dirty_update:bool)=  F)`;
+ ((readCSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr=
+    (let b__0 = csr in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mvendorid_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS marchid_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mimpid_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mhartid_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) . 
+      sail2_state_monad$returnS ((get_Mstatus_bits w__4  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS misa_ref) (\ (w__5 : Misa) .  sail2_state_monad$returnS ((get_Misa_bits w__5  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) . 
+      sail2_state_monad$returnS ((get_Medeleg_bits w__6  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . 
+      sail2_state_monad$returnS ((get_Minterrupts_bits w__7  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) . 
+      sail2_state_monad$returnS ((get_Minterrupts_bits w__8  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mtvec_ref) (\ (w__9 : Mtvec) .  sail2_state_monad$returnS ((get_Mtvec_bits w__9  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mcounteren_ref) (\ (w__10 : Counteren) . 
+      sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__10  :  32 words$word))  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mscratch_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mepc_ref  : ( 64 words$word) M) (\ (w__12 :  64 words$word) .  sail2_state_monad$bindS
+      (pc_alignment_mask ()   : ( 64 words$word) M) (\ (w__13 :  64 words$word) . 
+      sail2_state_monad$returnS ((and_vec w__12 w__13  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mcause_ref) (\ (w__14 : Mcause) . 
+      sail2_state_monad$returnS ((get_Mcause_bits w__14  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mtval_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mip_ref) (\ (w__16 : Minterrupts) . 
+      sail2_state_monad$returnS ((get_Minterrupts_bits w__16  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS pmpcfg0_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS pmpaddr0_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__19 : Mstatus) . 
+      sail2_state_monad$returnS ((get_Sstatus_bits ((lower_mstatus w__19))  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS sedeleg_ref) (\ (w__20 : Sedeleg) . 
+      sail2_state_monad$returnS ((get_Sedeleg_bits w__20  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS sideleg_ref) (\ (w__21 : Sinterrupts) . 
+      sail2_state_monad$returnS ((get_Sinterrupts_bits w__21  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mie_ref) (\ (w__22 : Minterrupts) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mideleg_ref) (\ (w__23 : Minterrupts) . 
+      sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mie w__22 w__23))  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS stvec_ref) (\ (w__24 : Mtvec) .  sail2_state_monad$returnS ((get_Mtvec_bits w__24  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS scounteren_ref) (\ (w__25 : Counteren) . 
+      sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__25  :  32 words$word))  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS sscratch_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS sepc_ref  : ( 64 words$word) M) (\ (w__27 :  64 words$word) .  sail2_state_monad$bindS
+      (pc_alignment_mask ()   : ( 64 words$word) M) (\ (w__28 :  64 words$word) . 
+      sail2_state_monad$returnS ((and_vec w__27 w__28  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS scause_ref) (\ (w__29 : Mcause) . 
+      sail2_state_monad$returnS ((get_Mcause_bits w__29  :  64 words$word)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS stval_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mip_ref) (\ (w__31 : Minterrupts) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mideleg_ref) (\ (w__32 : Minterrupts) . 
+      sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mip w__31 w__32))  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS satp_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mcycle_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS mtime_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+      (sail2_state_monad$read_regS minstret_ref  : ( 64 words$word) M)
+    else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS tselect_ref  : ( 64 words$word) M) (\ (w__37 :  64 words$word) . 
+      sail2_state_monad$returnS ((not_vec w__37  :  64 words$word)))
+    else
+      let (_ : unit) = (print_bits "unhandled read to CSR " csr) in
+      sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) (\ (res : xlenbits) . 
+   let (_ : unit) =
+     (print_endline
+       ((STRCAT "CSR "
+           ((STRCAT ((csr_name csr)) ((STRCAT " -> " ((string_of_bits res))))))))) in
+   sail2_state_monad$returnS res)))`;
 
 
-(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*)
+(*val writeCSR : mword ty12 -> mword ty64 -> M unit*)
 
 val _ = Define `
- ((translate39:(39)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)state_monad$sequential_state ->(((TR39_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr ac priv mxr do_sum level=  (state_monad$bindS
-   (curAsid64 ()   : ( 16 words$word) M) (\ asid .  state_monad$bindS
-   (lookupTLB39 asid vAddr) (\ (w__0 :  ((ii # TLB39_Entry))option) . 
-   (case w__0 of
-     SOME (idx,ent) =>
-      let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte  :  8 words$word))) in state_monad$bindS
-      (checkPTEPermission ac priv mxr do_sum pteBits) (\ (w__1 : bool) . 
-      if ((~ w__1)) then state_monad$returnS (TR39_Failure PTW_No_Permission)
-      else
-        (case ((update_PTE_Bits pteBits ac)) of
-          NONE =>
-           state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr
-                                    ((EXTZ (( 56 : int):ii)
-                                        ((and_vec vAddr ent.TLB39_Entry_vAddrMask  :  39 words$word))
-                                       :  56 words$word))
-                                   :  56 words$word)))
-        | SOME (pbits) =>
-           if ((~ enable_dirty_update)) then state_monad$returnS (TR39_Failure PTW_PTE_Update)
-           else
-             let (n_ent : TLB39_Entry) = ent in
-             let n_ent =
-               ((n_ent with<|
-                 TLB39_Entry_pte :=
-                   ((update_SV39_PTE_BITS ent.TLB39_Entry_pte ((get_PTE_Bits pbits  :  8 words$word))))|>)) in state_monad$bindS (state_monad$seqS
-             (writeTLB39 idx n_ent)
-             (checked_mem_write ((EXTZ (( 64 : int):ii) ent.TLB39_Entry_pteAddr  :  64 words$word)) (( 8 : int):ii)
-               ((get_SV39_PTE ent.TLB39_Entry_pte  :  64 words$word)))) (\ (w__2 : unit
-               MemoryOpResult) .  state_monad$seqS
-             (case w__2 of
-               MemValue (_) => state_monad$returnS () 
-             | MemException (e) => internal_error "invalid physical address in TLB"
-             )
-             (state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr
-                                      ((EXTZ (( 56 : int):ii)
-                                          ((and_vec vAddr ent.TLB39_Entry_vAddrMask  :  39 words$word))
-                                         :  56 words$word))
-                                     :  56 words$word)))))
-        ))
-   | NONE => state_monad$bindS
-      (curPTB39 ()   : ( 56 words$word) M) (\ (w__6 :  56 words$word) .  state_monad$bindS
-      (walk39 vAddr ac priv mxr do_sum w__6 level F) (\ (w__7 : PTW_Result) . 
-      (case w__7 of
-        PTW_Failure (f) => state_monad$returnS (TR39_Failure f)
-      | PTW_Success (pAddr,pte,pteAddr,level,global) =>
-         (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte  :  8 words$word))) ac)) of
-           NONE => state_monad$seqS
-            (addToTLB39 asid vAddr pAddr pte pteAddr level global) (state_monad$returnS (TR39_Address pAddr))
-         | SOME (pbits) =>
-            if ((~ enable_dirty_update)) then state_monad$returnS (TR39_Failure PTW_PTE_Update)
-            else
-              let (w_pte : SV39_PTE) =
-                (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits  :  8 words$word))) in state_monad$bindS
-              (checked_mem_write ((EXTZ (( 64 : int):ii) pteAddr  :  64 words$word)) (( 8 : int):ii)
-                ((get_SV39_PTE w_pte  :  64 words$word))) (\ (w__8 : unit MemoryOpResult) . 
-              (case w__8 of
-                MemValue (_) => state_monad$seqS
-                 (addToTLB39 asid vAddr pAddr w_pte pteAddr level global)
-                 (state_monad$returnS (TR39_Address pAddr))
-              | MemException (e) => state_monad$returnS (TR39_Failure PTW_Access)
-              ))
-         )
-      )))
+ ((writeCSR:(12)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)=
+    (let b__0 = csr in sail2_state_monad$bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mstatus_ref ((legalize_mstatus w__0 value)))
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__1 : Mstatus) . 
+      sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__1  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS misa_ref) (\ (w__2 : Misa) .  sail2_state_monad$bindS
+      (legalize_misa w__2 value) (\ (w__3 : Misa) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS misa_ref w__3)
+      (sail2_state_monad$read_regS misa_ref)) (\ (w__4 : Misa) .  sail2_state_monad$returnS (SOME ((get_Misa_bits w__4  :  64 words$word))))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS medeleg_ref) (\ (w__5 : Medeleg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS medeleg_ref ((legalize_medeleg w__5 value)))
+      (sail2_state_monad$read_regS medeleg_ref)) (\ (w__6 : Medeleg) . 
+      sail2_state_monad$returnS (SOME ((get_Medeleg_bits w__6  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mideleg_ref ((legalize_mideleg w__7 value)))
+      (sail2_state_monad$read_regS mideleg_ref)) (\ (w__8 : Minterrupts) . 
+      sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__8  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mie_ref) (\ (w__9 : Minterrupts) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mie_ref ((legalize_mie w__9 value)))
+      (sail2_state_monad$read_regS mie_ref)) (\ (w__10 : Minterrupts) . 
+      sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__10  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mtvec_ref) (\ (w__11 : Mtvec) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mtvec_ref ((legalize_tvec w__11 value)))
+      (sail2_state_monad$read_regS mtvec_ref)) (\ (w__12 : Mtvec) . 
+      sail2_state_monad$returnS (SOME ((get_Mtvec_bits w__12  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mcounteren_ref) (\ (w__13 : Counteren) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mcounteren_ref ((legalize_mcounteren w__13 value)))
+      (sail2_state_monad$read_regS mcounteren_ref)) (\ (w__14 : Counteren) . 
+      sail2_state_monad$returnS (SOME ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__14  :  32 words$word))  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mscratch_ref value)
+      (sail2_state_monad$read_regS mscratch_ref  : ( 64 words$word) M)) (\ (w__15 :  64 words$word) .  sail2_state_monad$returnS (SOME w__15))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (legalize_xepc value  : ( 64 words$word) M) (\ (w__16 : xlenbits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mepc_ref w__16)
+      (sail2_state_monad$read_regS mepc_ref  : ( 64 words$word) M)) (\ (w__17 :  64 words$word) .  sail2_state_monad$returnS (SOME w__17)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (set_Mcause_bits mcause_ref value)
+      (sail2_state_monad$read_regS mcause_ref)) (\ (w__18 : Mcause) . 
+      sail2_state_monad$returnS (SOME ((get_Mcause_bits w__18  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mtval_ref value)
+      (sail2_state_monad$read_regS mtval_ref  : ( 64 words$word) M)) (\ (w__19 :  64 words$word) .  sail2_state_monad$returnS (SOME w__19))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mip_ref) (\ (w__20 : Minterrupts) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mip_ref ((legalize_mip w__20 value)))
+      (sail2_state_monad$read_regS mip_ref)) (\ (w__21 : Minterrupts) . 
+      sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__21  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS pmpcfg0_ref value)
+      (sail2_state_monad$read_regS pmpcfg0_ref  : ( 64 words$word) M)) (\ (w__22 :  64 words$word) .  sail2_state_monad$returnS (SOME w__22))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS pmpaddr0_ref value)
+      (sail2_state_monad$read_regS pmpaddr0_ref  : ( 64 words$word) M)) (\ (w__23 :  64 words$word) .  sail2_state_monad$returnS (SOME w__23))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__24 : Mstatus) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mstatus_ref ((legalize_sstatus w__24 value)))
+      (sail2_state_monad$read_regS mstatus_ref)) (\ (w__25 : Mstatus) . 
+      sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__25  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS sedeleg_ref) (\ (w__26 : Sedeleg) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__26 value)))
+      (sail2_state_monad$read_regS sedeleg_ref)) (\ (w__27 : Sedeleg) . 
+      sail2_state_monad$returnS (SOME ((get_Sedeleg_bits w__27  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (set_Sinterrupts_bits sideleg_ref value)
+      (sail2_state_monad$read_regS sideleg_ref)) (\ (w__28 : Sinterrupts) . 
+      sail2_state_monad$returnS (SOME ((get_Sinterrupts_bits w__28  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mie_ref) (\ (w__29 : Minterrupts) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mideleg_ref) (\ (w__30 : Minterrupts) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mie_ref ((legalize_sie w__29 w__30 value)))
+      (sail2_state_monad$read_regS mie_ref)) (\ (w__31 : Minterrupts) . 
+      sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__31  :  64 words$word))))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS stvec_ref) (\ (w__32 : Mtvec) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS stvec_ref ((legalize_tvec w__32 value)))
+      (sail2_state_monad$read_regS stvec_ref)) (\ (w__33 : Mtvec) . 
+      sail2_state_monad$returnS (SOME ((get_Mtvec_bits w__33  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS scounteren_ref) (\ (w__34 : Counteren) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS scounteren_ref ((legalize_scounteren w__34 value)))
+      (sail2_state_monad$read_regS scounteren_ref)) (\ (w__35 : Counteren) . 
+      sail2_state_monad$returnS (SOME ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__35  :  32 words$word))  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS sscratch_ref value)
+      (sail2_state_monad$read_regS sscratch_ref  : ( 64 words$word) M)) (\ (w__36 :  64 words$word) .  sail2_state_monad$returnS (SOME w__36))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then sail2_state_monad$bindS
+      (legalize_xepc value  : ( 64 words$word) M) (\ (w__37 : xlenbits) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS sepc_ref w__37)
+      (sail2_state_monad$read_regS sepc_ref  : ( 64 words$word) M)) (\ (w__38 :  64 words$word) .  sail2_state_monad$returnS (SOME w__38)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (set_Mcause_bits scause_ref value)
+      (sail2_state_monad$read_regS scause_ref)) (\ (w__39 : Mcause) . 
+      sail2_state_monad$returnS (SOME ((get_Mcause_bits w__39  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS stval_ref value)
+      (sail2_state_monad$read_regS stval_ref  : ( 64 words$word) M)) (\ (w__40 :  64 words$word) .  sail2_state_monad$returnS (SOME w__40))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mip_ref) (\ (w__41 : Minterrupts) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mideleg_ref) (\ (w__42 : Minterrupts) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mip_ref ((legalize_sip w__41 w__42 value)))
+      (sail2_state_monad$read_regS mip_ref)) (\ (w__43 : Minterrupts) . 
+      sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__43  :  64 words$word))))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS
+      (cur_Architecture () ) (\ (w__44 : Architecture) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__45 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS satp_ref ((legalize_satp w__44 w__45 value  :  64 words$word)))
+      (sail2_state_monad$read_regS satp_ref  : ( 64 words$word) M)) (\ (w__46 :  64 words$word) .  sail2_state_monad$returnS (SOME w__46))))
+    else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS tselect_ref value)
+      (sail2_state_monad$read_regS tselect_ref  : ( 64 words$word) M)) (\ (w__47 :  64 words$word) .  sail2_state_monad$returnS (SOME w__47))
+    else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS mcycle_ref value)
+      (sail2_state_monad$read_regS mcycle_ref  : ( 64 words$word) M)) (\ (w__48 :  64 words$word) .  sail2_state_monad$returnS (SOME w__48))
+    else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+      (sail2_state_monad$write_regS minstret_ref value)
+      (sail2_state_monad$write_regS minstret_written_ref T))
+      (sail2_state_monad$read_regS minstret_ref  : ( 64 words$word) M)) (\ (w__49 :  64 words$word) .  sail2_state_monad$returnS (SOME w__49))
+    else sail2_state_monad$returnS NONE) (\ (res :  xlenbits option) . 
+   sail2_state_monad$returnS ((case res of
+     SOME (v) =>
+      print_endline
+        ((STRCAT "CSR "
+            ((STRCAT ((csr_name csr))
+                ((STRCAT " <- "
+                    ((STRCAT ((string_of_bits v))
+                        ((STRCAT " (input: " ((STRCAT ((string_of_bits value)) ")"))))))))))))
+   | NONE => print_bits "unhandled write to CSR " csr
    )))))`;
 
 
-(*val translationMode : Privilege -> M SATPMode*)
+(*val maybe_i_forwards : bool -> string*)
 
 val _ = Define `
- ((translationMode:Privilege ->(regstate)state_monad$sequential_state ->(((SATPMode),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) priv=
-    (if (((((privLevel_to_bits priv  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))))
-   then
-     state_monad$returnS Sbare
-   else state_monad$bindS
-     (state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . 
-     let arch = (architecture ((get_Mstatus_SXL w__0  :  2 words$word))) in
-     (case arch of
-       SOME (RV64) => state_monad$bindS
-        (state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
-        let (mbits : satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1)  :  4 words$word)) in
-        (case ((satpMode_of_bits RV64 mbits)) of
-          SOME (m) => state_monad$returnS m
-        | NONE => internal_error "invalid RV64 translation mode in satp"
-        ))
-     | _ => internal_error "unsupported address translation arch"
-     ))))`;
+ ((maybe_i_forwards:bool -> string) arg_=  ((case arg_ of   T => "i" | F => "" )))`;
 
 
-(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*)
+(*val maybe_i_backwards : string -> bool*)
 
 val _ = Define `
- ((translateAddr:(64)words$word -> AccessType -> ReadType ->(regstate)state_monad$sequential_state ->(((TR_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr ac rt=  (state_monad$bindS
-   (case rt of
-     Instruction => state_monad$read_regS cur_privilege_ref
-   | Data => state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . 
-      if (((((get_Mstatus_MPRV w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then state_monad$bindS
-        (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . 
-        state_monad$returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2  :  2 words$word)))))
-      else state_monad$read_regS cur_privilege_ref)
-   ) (\ (effPriv : Privilege) .  state_monad$bindS
-   (state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . 
-   let (mxr : bool) =
-     (((get_Mstatus_MXR w__5  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))) in state_monad$bindS
-   (state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) . 
-   let (do_sum : bool) =
-     (((get_Mstatus_SUM w__6  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))) in state_monad$bindS
-   (translationMode effPriv) (\ (mode : SATPMode) .  
-  (case mode of
-        Sbare => state_monad$returnS (TR_Address vAddr)
-    | SV39 => state_monad$bindS
-                (translate39
-                   ((subrange_vec_dec vAddr (( 38 : int): ii)
-                       (( 0 : int): ii) : 39 words$word)) ac effPriv 
-                 mxr do_sum ((SV39_LEVELS - (( 1 : int): ii))))
-                (\ (w__7 : TR39_Result) . 
-                 state_monad$returnS
-                   ((case w__7 of
-                          TR39_Address (pa) => TR_Address
-                                                 ((EXTZ (( 64 : int): ii) pa : 64 words$word))
-                      | TR39_Failure (f) => TR_Failure
-                                              ((translationException ac f))
-                    )))
-  )))))))`;
+ ((maybe_i_backwards:string -> bool) arg_=  ((case arg_ of   "i" => T | "" => F )))`;
 
 
-(*val decode : mword ty32 -> maybe ast*)
+(*val maybe_i_forwards_matches : bool -> bool*)
 
-(*val decodeCompressed : mword ty16 -> maybe ast*)
+val _ = Define `
+ ((maybe_i_forwards_matches:bool -> bool) arg_= 
+  ((case arg_ of   T => T | F => T )))`;
 
-(*val execute : ast -> M unit*)
 
-(*val print_insn : ast -> string*)
+(*val maybe_i_backwards_matches : string -> bool*)
 
-(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*)
+val _ = Define `
+ ((maybe_i_backwards_matches:string -> bool) arg_=  ((case arg_ of   "i" => T | "" => T | _ => F )))`;
+
+
+(*val maybe_i_matches_prefix : string -> maybe ((bool * ii))*)
 
 val _ = Define `
- ((extend_value:bool ->('int8_times_n words$word)MemoryOpResult ->((64)words$word)MemoryOpResult) is_unsigned value=
-    ((case value of
-     MemValue (v) =>
-      MemValue (if is_unsigned then (EXTZ (( 64 : int):ii) v  :  64 words$word)
-                else (EXTS (( 64 : int):ii) v  :  64 words$word))
-   | MemException (e) => MemException e
-   )))`;
+ ((maybe_i_matches_prefix:string ->(bool#int)option) arg_=
+    (let stringappend_1614_0 = arg_ in
+   if (((((string_startswith stringappend_1614_0 "i")) /\ (
+  (case ((string_drop stringappend_1614_0 ((string_length "i")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1614_0 ((string_length "i")))) of
+       s_ => SOME (T, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1614_0 "")) /\ (
+  (case ((string_drop stringappend_1614_0 ((string_length "")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1614_0 ((string_length "")))) of
+       s_ => SOME (F, ((string_length arg_)) - ((string_length s_)))
+     )
+   else NONE))`;
 
 
-(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*)
+(*val csr_mnemonic_forwards : csrop -> string*)
 
 val _ = Define `
- ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd addr value is_unsigned=
-    ((case ((extend_value is_unsigned value  : ( 64 words$word) MemoryOpResult)) of
-     MemValue (result) => wX ((regbits_to_regno rd)) result
-   | MemException (e) => handle_mem_exception addr e
-   )))`;
+ ((csr_mnemonic_forwards:csrop -> string) arg_=
+    ((case arg_ of   CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" )))`;
 
 
-(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*)
+(*val csr_mnemonic_backwards : string -> csrop*)
 
-(*val readCSR : mword ty12 -> M (mword ty64)*)
+val _ = Define `
+ ((csr_mnemonic_backwards:string -> csrop) arg_=
+    ((case arg_ of   "csrrw" => CSRRW | "csrrs" => CSRRS | "csrrc" => CSRRC )))`;
+
+
+(*val csr_mnemonic_forwards_matches : csrop -> bool*)
 
 val _ = Define `
- ((readCSR:(12)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) csr=
-    (let b__0 = csr in
-   if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
-     (state_monad$read_regS mvendorid_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
-     (state_monad$read_regS marchid_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
-     (state_monad$read_regS mimpid_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
-     (state_monad$read_regS mhartid_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .  state_monad$returnS ((get_Mstatus w__4  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS misa_ref) (\ (w__5 : Misa) .  state_monad$returnS ((get_Misa w__5  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) .  state_monad$returnS ((get_Medeleg w__6  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . 
-     state_monad$returnS ((get_Minterrupts w__7  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) .  state_monad$returnS ((get_Minterrupts w__8  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mtvec_ref) (\ (w__9 : Mtvec) .  state_monad$returnS ((get_Mtvec w__9  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
-     (state_monad$read_regS mscratch_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
-     (state_monad$read_regS mepc_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mcause_ref) (\ (w__12 : Mcause) .  state_monad$returnS ((get_Mcause w__12  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
-     (state_monad$read_regS mtval_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mip_ref) (\ (w__14 : Minterrupts) . 
-     state_monad$returnS ((get_Minterrupts w__14  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) .  state_monad$returnS ((get_Mstatus w__15  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS sedeleg_ref) (\ (w__16 : Sedeleg) .  state_monad$returnS ((get_Sedeleg w__16  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) . 
-     state_monad$returnS ((get_Sinterrupts w__17  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mie_ref) (\ (w__18 : Minterrupts) .  state_monad$bindS
-     (state_monad$read_regS mideleg_ref) (\ (w__19 : Minterrupts) . 
-     state_monad$returnS ((get_Sinterrupts ((lower_mie w__18 w__19))  :  64 words$word))))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS stvec_ref) (\ (w__20 : Mtvec) .  state_monad$returnS ((get_Mtvec w__20  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
-     (state_monad$read_regS sscratch_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
-     (state_monad$read_regS sepc_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS scause_ref) (\ (w__23 : Mcause) .  state_monad$returnS ((get_Mcause w__23  :  64 words$word)))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
-     (state_monad$read_regS stval_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS mip_ref) (\ (w__25 : Minterrupts) .  state_monad$bindS
-     (state_monad$read_regS mideleg_ref) (\ (w__26 : Minterrupts) . 
-     state_monad$returnS ((get_Sinterrupts ((lower_mip w__25 w__26))  :  64 words$word))))
-   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
-     (state_monad$read_regS satp_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
-     (state_monad$read_regS mcycle_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
-     (state_monad$read_regS mtime_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
-     (state_monad$read_regS minstret_ref  : ( 64 words$word) M)
-   else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS
-     (state_monad$read_regS tselect_ref  : ( 64 words$word) M) (\ (w__31 :  64 words$word) . 
-     state_monad$returnS ((not_vec w__31  :  64 words$word)))
-   else
-     let (_ : unit) = (print_bits "unhandled read to CSR " csr) in
-     state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                          B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                          B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-              :  64 words$word)))`;
+ ((csr_mnemonic_forwards_matches:csrop -> bool) arg_= 
+  ((case arg_ of   CSRRW => T | CSRRS => T | CSRRC => T )))`;
 
 
-(*val writeCSR : mword ty12 -> mword ty64 -> M unit*)
+(*val csr_mnemonic_backwards_matches : string -> bool*)
 
 val _ = Define `
- ((writeCSR:(12)words$word ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)=
-    (let b__0 = csr in state_monad$bindS
-   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mstatus_ref ((legalize_mstatus w__0 value)))
-      (state_monad$read_regS mstatus_ref)) (\ (w__1 : Mstatus) . 
-      state_monad$returnS (SOME ((get_Mstatus w__1  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS medeleg_ref) (\ (w__2 : Medeleg) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS medeleg_ref ((legalize_medeleg w__2 value)))
-      (state_monad$read_regS medeleg_ref)) (\ (w__3 : Medeleg) . 
-      state_monad$returnS (SOME ((get_Medeleg w__3  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mideleg_ref) (\ (w__4 : Minterrupts) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mideleg_ref ((legalize_mideleg w__4 value)))
-      (state_monad$read_regS mideleg_ref)) (\ (w__5 : Minterrupts) . 
-      state_monad$returnS (SOME ((get_Minterrupts w__5  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mie_ref ((legalize_mie w__6 value)))
-      (state_monad$read_regS mie_ref)) (\ (w__7 : Minterrupts) . 
-      state_monad$returnS (SOME ((get_Minterrupts w__7  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mtvec_ref) (\ (w__8 : Mtvec) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mtvec_ref ((legalize_tvec w__8 value)))
-      (state_monad$read_regS mtvec_ref)) (\ (w__9 : Mtvec) .  state_monad$returnS (SOME ((get_Mtvec w__9  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mscratch_ref value)
-      (state_monad$read_regS mscratch_ref  : ( 64 words$word) M)) (\ (w__10 :  64 words$word) .  state_monad$returnS (SOME w__10))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then state_monad$bindS
-      (legalize_xepc value  : ( 64 words$word) M) (\ (w__11 : xlenbits) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mepc_ref w__11)
-      (state_monad$read_regS mepc_ref  : ( 64 words$word) M)) (\ (w__12 :  64 words$word) .  state_monad$returnS (SOME w__12)))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (set_Mcause mcause_ref value)
-      (state_monad$read_regS mcause_ref)) (\ (w__13 : Mcause) . 
-      state_monad$returnS (SOME ((get_Mcause w__13  :  64 words$word))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mtval_ref value)
-      (state_monad$read_regS mtval_ref  : ( 64 words$word) M)) (\ (w__14 :  64 words$word) .  state_monad$returnS (SOME w__14))
-    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mip_ref) (\ (w__15 : Minterrupts) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mip_ref ((legalize_mip w__15 value)))
-      (state_monad$read_regS mip_ref)) (\ (w__16 : Minterrupts) . 
-      state_monad$returnS (SOME ((get_Minterrupts w__16  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__17 : Mstatus) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mstatus_ref ((legalize_sstatus w__17 value)))
-      (state_monad$read_regS mstatus_ref)) (\ (w__18 : Mstatus) . 
-      state_monad$returnS (SOME ((get_Mstatus w__18  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS sedeleg_ref) (\ (w__19 : Sedeleg) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__19 value)))
-      (state_monad$read_regS sedeleg_ref)) (\ (w__20 : Sedeleg) . 
-      state_monad$returnS (SOME ((get_Sedeleg w__20  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (set_Sinterrupts sideleg_ref value)
-      (state_monad$read_regS sideleg_ref)) (\ (w__21 : Sinterrupts) . 
-      state_monad$returnS (SOME ((get_Sinterrupts w__21  :  64 words$word))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mie_ref) (\ (w__22 : Minterrupts) .  state_monad$bindS
-      (state_monad$read_regS mideleg_ref) (\ (w__23 : Minterrupts) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mie_ref ((legalize_sie w__22 w__23 value)))
-      (state_monad$read_regS mie_ref)) (\ (w__24 : Minterrupts) . 
-      state_monad$returnS (SOME ((get_Minterrupts w__24  :  64 words$word))))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS stvec_ref) (\ (w__25 : Mtvec) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS stvec_ref ((legalize_tvec w__25 value)))
-      (state_monad$read_regS stvec_ref)) (\ (w__26 : Mtvec) .  state_monad$returnS (SOME ((get_Mtvec w__26  :  64 words$word)))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS sscratch_ref value)
-      (state_monad$read_regS sscratch_ref  : ( 64 words$word) M)) (\ (w__27 :  64 words$word) .  state_monad$returnS (SOME w__27))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then state_monad$bindS
-      (legalize_xepc value  : ( 64 words$word) M) (\ (w__28 : xlenbits) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS sepc_ref w__28)
-      (state_monad$read_regS sepc_ref  : ( 64 words$word) M)) (\ (w__29 :  64 words$word) .  state_monad$returnS (SOME w__29)))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (set_Mcause scause_ref value)
-      (state_monad$read_regS scause_ref)) (\ (w__30 : Mcause) . 
-      state_monad$returnS (SOME ((get_Mcause w__30  :  64 words$word))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS stval_ref value)
-      (state_monad$read_regS stval_ref  : ( 64 words$word) M)) (\ (w__31 :  64 words$word) .  state_monad$returnS (SOME w__31))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (state_monad$read_regS mip_ref) (\ (w__32 : Minterrupts) .  state_monad$bindS
-      (state_monad$read_regS mideleg_ref) (\ (w__33 : Minterrupts) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS mip_ref ((legalize_sip w__32 w__33 value)))
-      (state_monad$read_regS mip_ref)) (\ (w__34 : Minterrupts) . 
-      state_monad$returnS (SOME ((get_Minterrupts w__34  :  64 words$word))))))
-    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS
-      (cur_Architecture () ) (\ (w__35 : Architecture) .  state_monad$bindS
-      (state_monad$read_regS satp_ref  : ( 64 words$word) M) (\ (w__36 :  64 words$word) .  state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS satp_ref ((legalize_satp w__35 w__36 value  :  64 words$word)))
-      (state_monad$read_regS satp_ref  : ( 64 words$word) M)) (\ (w__37 :  64 words$word) .  state_monad$returnS (SOME w__37))))
-    else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0]  :  12 words$word)))) then state_monad$bindS (state_monad$seqS
-      (state_monad$write_regS tselect_ref value)
-      (state_monad$read_regS tselect_ref  : ( 64 words$word) M)) (\ (w__38 :  64 words$word) .  state_monad$returnS (SOME w__38))
-    else state_monad$returnS NONE) (\ (res :  xlenbits option) . 
-   state_monad$returnS ((case res of
-     SOME (v) =>
-      prerr_endline
-        ((STRCAT "CSR "
-            ((STRCAT ((csr_name csr))
-                ((STRCAT " <- "
-                    ((STRCAT ((string_of_vec v))
-                        ((STRCAT " (input: " ((STRCAT ((string_of_vec value)) ")"))))))))))))
-   | NONE => print_bits "unhandled write to CSR " csr
-   )))))`;
+ ((csr_mnemonic_backwards_matches:string -> bool) arg_=
+    ((case arg_ of   "csrrw" => T | "csrrs" => T | "csrrc" => T | _ => F )))`;
+
 
+(*val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))*)
 
 val _ = Define `
- ((decode:(32)words$word ->(ast)option) v__0=
-    (if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1]  :  7 words$word)))) then
-     let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (UTYPE (imm,rd,RISCV_LUI))
-   else if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1]  :  7 words$word)))) then
-     let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (UTYPE (imm,rd,RISCV_AUIPC))
-   else if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1]  :  7 words$word)))) then
-     let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word))
-                             ((concat_vec
-                                 ((cast_unit_vec0 ((access_vec_dec imm (( 8 : int):ii)))  :  1 words$word))
-                                 ((concat_vec ((subrange_vec_dec imm (( 18 : int):ii) (( 13 : int):ii)  :  6 words$word))
-                                     ((concat_vec
-                                         ((subrange_vec_dec imm (( 12 : int):ii) (( 9 : int):ii)  :  4 words$word))
-                                         (vec_of_bits [B0]  :  1 words$word)
-                                        :  5 words$word))
-                                    :  11 words$word))
-                                :  12 words$word))
-                            :  20 words$word))
-                        :  21 words$word),rd))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RISCV_JALR (imm,rs1,rd))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii)))  :  1 words$word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word))
-                                 (vec_of_bits [B0]  :  1 words$word)
-                                :  5 words$word))
-                            :  11 words$word))
-                        :  12 words$word))
-                    :  13 words$word),rs2,rs1,RISCV_BEQ))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii)))  :  1 words$word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word))
-                                 (vec_of_bits [B0]  :  1 words$word)
-                                :  5 words$word))
-                            :  11 words$word))
-                        :  12 words$word))
-                    :  13 words$word),rs2,rs1,RISCV_BNE))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii)))  :  1 words$word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word))
-                                 (vec_of_bits [B0]  :  1 words$word)
-                                :  5 words$word))
-                            :  11 words$word))
-                        :  12 words$word))
-                    :  13 words$word),rs2,rs1,RISCV_BLT))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii)))  :  1 words$word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word))
-                                 (vec_of_bits [B0]  :  1 words$word)
-                                :  5 words$word))
-                            :  11 words$word))
-                        :  12 words$word))
-                    :  13 words$word),rs2,rs1,RISCV_BGE))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii)))  :  1 words$word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word))
-                                 (vec_of_bits [B0]  :  1 words$word)
-                                :  5 words$word))
-                            :  11 words$word))
-                        :  12 words$word))
-                    :  13 words$word),rs2,rs1,RISCV_BLTU))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii)))  :  1 words$word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii)))  :  1 words$word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii)  :  6 words$word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word))
-                                 (vec_of_bits [B0]  :  1 words$word)
-                                :  5 words$word))
-                            :  11 words$word))
-                        :  12 words$word))
-                    :  13 words$word),rs2,rs1,RISCV_BGEU))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ITYPE (imm,rs1,rd,RISCV_ADDI))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ITYPE (imm,rs1,rd,RISCV_SLTI))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ITYPE (imm,rs1,rd,RISCV_SLTIU))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ITYPE (imm,rs1,rd,RISCV_XORI))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ITYPE (imm,rs1,rd,RISCV_ORI))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ITYPE (imm,rs1,rd,RISCV_ANDI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii)  :  6 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii)  :  6 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii)  :  6 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_ADD))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_SUB))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_SLL))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_SLT))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_SLTU))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_XOR))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_SRL))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_SRA))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_OR))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPE (rs2,rs1,rd,RISCV_AND))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,F,BYTE,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,F,HALF,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,F,WORD,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,F,DOUBLE,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,T,BYTE,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,T,HALF,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOAD (imm,rs1,rd,T,WORD,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,BYTE,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,HALF,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,WORD,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,DOUBLE,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word))))))) then
-     let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (ADDIW (imm,rs1,rd))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (SHIFTW (shamt,rs1,rd,RISCV_SLLI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (SHIFTW (shamt,rs1,rd,RISCV_SRLI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (SHIFTW (shamt,rs1,rd,RISCV_SRAI))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPEW (rs2,rs1,rd,RISCV_ADDW))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPEW (rs2,rs1,rd,RISCV_SUBW))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPEW (rs2,rs1,rd,RISCV_SLLW))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPEW (rs2,rs1,rd,RISCV_SRLW))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (RTYPEW (rs2,rs1,rd,RISCV_SRAW))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (MUL (rs2,rs1,rd,F,T,T))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (MUL (rs2,rs1,rd,T,T,T))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (MUL (rs2,rs1,rd,T,T,F))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (MUL (rs2,rs1,rd,T,F,F))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (DIV0 (rs2,rs1,rd,T))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (DIV0 (rs2,rs1,rd,F))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (REM (rs2,rs1,rd,T))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (REM (rs2,rs1,rd,F))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (MULW (rs2,rs1,rd))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (DIVW (rs2,rs1,rd,T))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (DIVW (rs2,rs1,rd,F))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (REMW (rs2,rs1,rd,T))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (REMW (rs2,rs1,rd,F))
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__0 (( 19 : int):ii) (( 0 : int):ii)  :  20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
-                     :  20 words$word))))))) then
-     let (pred : 4 bits) = ((subrange_vec_dec v__0 (( 27 : int):ii) (( 24 : int):ii)  :  4 words$word)) in
-     let (succ : 4 bits) = ((subrange_vec_dec v__0 (( 23 : int):ii) (( 20 : int):ii)  :  4 words$word)) in
-     SOME (FENCE (pred,succ))
-   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;
-                             B0;B0;B0;B0;B1;B1;B1;B1]
-                 :  32 words$word)))) then
-     SOME (FENCEI () )
-   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                             B0;B1;B1;B1;B0;B0;B1;B1]
-                 :  32 words$word)))) then
-     SOME (ECALL () )
-   else if (((v__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                             B0;B1;B1;B1;B0;B0;B1;B1]
-                 :  32 words$word)))) then
-     SOME (MRET () )
-   else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                             B0;B1;B1;B1;B0;B0;B1;B1]
-                 :  32 words$word)))) then
-     SOME (SRET () )
-   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                             B0;B1;B1;B1;B0;B0;B1;B1]
-                 :  32 words$word)))) then
-     SOME (EBREAK () )
-   else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                             B0;B1;B1;B1;B0;B0;B1;B1]
-                 :  32 words$word)))) then
-     SOME (WFI () )
-   else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1]  :  7 words$word)))) /\ (((((subrange_vec_dec v__0 (( 14 : int):ii) (( 0 : int):ii)  :  15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]  :  15 words$word)))))))
-   then
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     SOME (SFENCE_VMA (rs1,rs2))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
-     let aq = (access_vec_dec v__0 (( 26 : int):ii)) in
-     let rl = (access_vec_dec v__0 (( 25 : int):ii)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (CSR (csr,rs1,rd,F,CSRRW))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (CSR (csr,rs1,rd,F,CSRRS))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (CSR (csr,rs1,rd,F,CSRRC))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (CSR (csr,rs1,rd,T,CSRRW))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (CSR (csr,rs1,rd,T,CSRRS))
-   else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
-     let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
-     let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     SOME (CSR (csr,rs1,rd,T,CSRRC))
+ ((csr_mnemonic_matches_prefix:string ->(csrop#int)option) arg_=
+    (let stringappend_1611_0 = arg_ in
+   if (((((string_startswith stringappend_1611_0 "csrrw")) /\ (
+  (case ((string_drop stringappend_1611_0 ((string_length "csrrw")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1611_0 ((string_length "csrrw")))) of
+       s_ => SOME (CSRRW, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1611_0 "csrrs")) /\ (
+  (case ((string_drop stringappend_1611_0 ((string_length "csrrs")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1611_0 ((string_length "csrrs")))) of
+       s_ => SOME (CSRRS, ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_1611_0 "csrrc")) /\ (
+  (case ((string_drop stringappend_1611_0 ((string_length "csrrc")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_1611_0 ((string_length "csrrc")))) of
+       s_ => SOME (CSRRC, ((string_length arg_)) - ((string_length s_)))
+     )
    else NONE))`;
 
 
 val _ = Define `
- ((decodeCompressed:(16)words$word ->(ast)option) v__418=
-    (if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (nzi1 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (nzi0 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+ ((decodeCompressed:(16)words$word ->(ast)option) v__2=
+    (if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzi1 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (nzi0 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      if ((((((nzi1 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) then
        SOME (NOP () )
      else NONE
-   else if (((v__418 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) then
-     SOME (ILLEGAL () )
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
-     let (nz54 : 2 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 11 : int):ii)  :  2 words$word)) in
-     let (nz96 : 4 bits) = ((subrange_vec_dec v__418 (( 10 : int):ii) (( 7 : int):ii)  :  4 words$word)) in
-     let (nz2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
-     let (nz3 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
-     let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (nz54 : 2 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 11 : int):ii)  :  2 words$word)) in
+     let (nz96 : 4 bits) = ((subrange_vec_dec v__2 (( 10 : int):ii) (( 7 : int):ii)  :  4 words$word)) in
+     let (nz2 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
+     let (nz3 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
+     let (rd : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      let nzimm =
        ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2  :  2 words$word))  :  4 words$word))
          :  8 words$word)) in
      if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)))) then NONE
      else SOME (C_ADDI4SPN (rd,nzimm))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
-     let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
-     let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (ui2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
-     let (ui6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
-     let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
+     let (rs1 : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (ui2 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
+     let (ui6 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
+     let (rd : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2  :  4 words$word))  :  5 words$word)) in
      SOME (C_LW (uimm,rs1,rd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
-     let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
-     let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
-     let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
+     let (rs1 : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let (rd : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      let uimm = ((concat_vec ui76 ui53  :  5 words$word)) in
      SOME (C_LD (uimm,rs1,rd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
-     let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
-     let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (ui2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
-     let (ui6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
+     let (rs1 : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (ui2 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
+     let (ui6 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2  :  4 words$word))  :  5 words$word)) in
      SOME (C_SW (uimm,rs1,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
-     let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
-     let (rs1 : 3 bits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
-     let (rs2 : 3 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
+     let (rs1 : 3 bits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let (rs2 : 3 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      let uimm = ((concat_vec ui76 ui53  :  5 words$word)) in
      SOME (C_SD (uimm,rs1,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (nzi5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (nzi40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (nzi5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (nzi40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      let nzi = ((concat_vec nzi5 nzi40  :  6 words$word)) in
      if ((((((nzi = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then
        NONE
      else SOME (C_ADDI (nzi,rsd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (imm5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (imm40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (imm5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (imm40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      SOME (C_ADDIW ((concat_vec imm5 imm40  :  6 words$word),rsd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (imm5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (imm40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (imm5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (imm40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE
      else SOME (C_LI ((concat_vec imm5 imm40  :  6 words$word),rd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (nzi9 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (nzi4 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
-     let (nzi6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
-     let (nzi87 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
-     let (nzi5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzi9 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (nzi4 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
+     let (nzi6 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii)  :  1 words$word)) in
+     let (nzi87 : 2 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
+     let (nzi5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
      let nzimm =
        ((concat_vec nzi9
           ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4  :  2 words$word))  :  3 words$word))
@@ -6169,65 +11909,65 @@ val _ = Define `
          :  6 words$word)) in
      if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) then NONE
      else SOME (C_ADDI16SP nzimm)
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (imm17 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (imm1612 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (imm17 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (imm1612 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then
        NONE
      else SOME (C_LUI ((concat_vec imm17 imm1612  :  6 words$word),rd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (nzui40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      let (shamt : 6 bits) = ((concat_vec nzui5 nzui40  :  6 words$word)) in
      if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) then NONE
      else SOME (C_SRLI (shamt,rsd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (nzui40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      let (shamt : 6 bits) = ((concat_vec nzui5 nzui40  :  6 words$word)) in
      if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) then NONE
      else SOME (C_SRAI (shamt,rsd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (i40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (i40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      SOME (C_ANDI ((concat_vec i5 i40  :  6 words$word),rsd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      SOME (C_SUB (rsd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      SOME (C_XOR (rsd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      SOME (C_OR (rsd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      SOME (C_AND (rsd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      SOME (C_SUBW (rsd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
-     let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      SOME (C_ADDW (rsd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (i11 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (i4 : 1 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)) in
-     let (i98 : 2 bits) = ((subrange_vec_dec v__418 (( 10 : int):ii) (( 9 : int):ii)  :  2 words$word)) in
-     let (i10 : 1 bits) = ((subrange_vec_dec v__418 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)) in
-     let (i6 : 1 bits) = ((subrange_vec_dec v__418 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
-     let (i7 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
-     let (i31 : 3 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 3 : int):ii)  :  3 words$word)) in
-     let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (i11 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (i4 : 1 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)) in
+     let (i98 : 2 bits) = ((subrange_vec_dec v__2 (( 10 : int):ii) (( 9 : int):ii)  :  2 words$word)) in
+     let (i10 : 1 bits) = ((subrange_vec_dec v__2 (( 8 : int):ii) (( 8 : int):ii)  :  1 words$word)) in
+     let (i6 : 1 bits) = ((subrange_vec_dec v__2 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
+     let (i7 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii)  :  1 words$word)) in
+     let (i31 : 3 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 3 : int):ii)  :  3 words$word)) in
+     let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
      SOME (C_J ((concat_vec i11
                    ((concat_vec i10
                        ((concat_vec i98
@@ -6239,231 +11979,263 @@ val _ = Define `
                           :  9 words$word))
                       :  10 words$word))
                   :  11 words$word)))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (i8 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (i43 : 2 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
-     let (rs : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (i76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
-     let (i21 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
-     let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (i8 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (i43 : 2 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (rs : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (i76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let (i21 : 2 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
+     let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
      SOME (C_BEQZ ((concat_vec i8
                       ((concat_vec i76
                           ((concat_vec i5 ((concat_vec i43 i21  :  4 words$word))  :  5 words$word))
                          :  7 words$word))
                      :  8 words$word),rs))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
-     let (i8 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (i43 : 2 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
-     let (rs : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (i76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
-     let (i21 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
-     let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (i8 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (i43 : 2 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii)  :  2 words$word)) in
+     let (rs : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (i76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let (i21 : 2 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 3 : int):ii)  :  2 words$word)) in
+     let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii)  :  1 words$word)) in
      SOME (C_BNEZ ((concat_vec i8
                       ((concat_vec i76
                           ((concat_vec i5 ((concat_vec i43 i21  :  4 words$word))  :  5 words$word))
                          :  7 words$word))
                      :  8 words$word),rs))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (nzui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (nzui40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      let (shamt : 6 bits) = ((concat_vec nzui5 nzui40  :  6 words$word)) in
      if ((((((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then
        NONE
      else SOME (C_SLLI (shamt,rsd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (ui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (ui42 : 3 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 4 : int):ii)  :  3 words$word)) in
-     let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 3 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (ui42 : 3 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 4 : int):ii)  :  3 words$word)) in
+     let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 3 : int):ii) (( 2 : int):ii)  :  2 words$word)) in
      let (uimm : 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42  :  4 words$word))  :  6 words$word)) in
      if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE
      else SOME (C_LWSP (uimm,rd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (ui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
-     let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (ui43 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
-     let (ui86 : 3 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (ui43 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let (ui86 : 3 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
      let (uimm : 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43  :  3 words$word))  :  6 words$word)) in
      if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE
      else SOME (C_LDSP (uimm,rd))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (ui52 : 4 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 9 : int):ii)  :  4 words$word)) in
-     let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 8 : int):ii) (( 7 : int):ii)  :  2 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui52 : 4 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 9 : int):ii)  :  4 words$word)) in
+     let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 8 : int):ii) (( 7 : int):ii)  :  2 words$word)) in
+     let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      let (uimm : 6 bits) = ((concat_vec ui76 ui52  :  6 words$word)) in
      SOME (C_SWSP (uimm,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
-     let (ui86 : 3 bits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii)  :  3 words$word)) in
+     let (ui86 : 3 bits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii)  :  3 words$word)) in
+     let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      let (uimm : 6 bits) = ((concat_vec ui86 ui53  :  6 words$word)) in
      SOME (C_SDSP (uimm,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word))))))) then
-     let (rs1 : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word))))))) then
+     let (rs1 : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
      if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE
      else SOME (C_JR rs1)
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word))))))) then
-     let (rs1 : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word))))))) then
+     let (rs1 : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
      if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE
      else SOME (C_JALR rs1)
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then
        NONE
      else SOME (C_MV (rd,rs2))
-   else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
-     let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
-     let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii)  :  5 words$word)) in
      if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then
        NONE
      else SOME (C_ADD (rsd,rs2))
+   else if (((v__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) then
+     SOME (C_ILLEGAL () )
    else NONE))`;
 
 
-(*val execute_WFI : unit -> M unit*)
+(*val execute_WFI : unit -> M bool*)
 
  val _ = Define `
- ((execute_WFI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__110=  (state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
+ ((execute_WFI:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__26=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
    (case w__0 of
-     Machine => state_monad$returnS () 
-   | Supervisor => state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . 
-      if (((((get_Mstatus_TW w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
-        handle_illegal () 
-      else state_monad$returnS () )
-   | User => handle_illegal () 
+     Machine => sail2_state_monad$returnS T
+   | Supervisor => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . 
+      if (((((get_Mstatus_TW w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then sail2_state_monad$seqS
+        (handle_illegal () ) (sail2_state_monad$returnS F)
+      else sail2_state_monad$returnS T)
+   | User => sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)
    ))))`;
 
 
-(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*)
+(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M bool*)
 
  val _ = Define `
- ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rd op=
+ ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd op=
     (let (off : xlenbits) =
      ((EXTS (( 64 : int):ii)
         ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
            :  32 words$word))
-       :  64 words$word)) in state_monad$bindS
+       :  64 words$word)) in sail2_state_monad$bindS
    (case op of
-     RISCV_LUI => state_monad$returnS off
-   | RISCV_AUIPC => state_monad$bindS
-      (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-      state_monad$returnS ((add_vec w__0 off  :  64 words$word)))
-   ) (\ (ret : xlenbits) . 
-   wX ((regbits_to_regno rd)) ret)))`;
+     RISCV_LUI => sail2_state_monad$returnS off
+   | RISCV_AUIPC => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+      sail2_state_monad$returnS ((add_vec w__0 off  :  64 words$word)))
+   ) (\ (ret : xlenbits) .  sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ret) (sail2_state_monad$returnS T))))`;
+
+
+(*val execute_THREAD_START : unit -> bool*)
+
+ val _ = Define `
+ ((execute_THREAD_START:unit -> bool) g__29=  T)`;
 
 
-(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*)
+(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) aq rl rs2 rs1 width rd=  (state_monad$bindS
-   (speculate_conditional_success () ) (\ (w__0 : bool) . 
-   let (status : 1 bits) =
-     (if w__0 then (vec_of_bits [B0]  :  1 words$word)
-     else (vec_of_bits [B1]  :  1 words$word)) in state_monad$seqS
-   (wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):ii) status  :  64 words$word)))
-   (if (((status = (vec_of_bits [B1]  :  1 words$word)))) then state_monad$returnS () 
-   else state_monad$bindS
-     (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (vaddr : xlenbits) .  state_monad$bindS
+ ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs2 rs1 width rd=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (vaddr : xlenbits) . 
+   let (aligned : bool) =
+     ((case width of
+       BYTE => T
+     | HALF =>
+        (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii)))  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))
+     | WORD =>
+        (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))
+     | DOUBLE =>
+        (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))
+     )) in
+   if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS F)
+   else sail2_state_monad$bindS
+     (speculate_conditional_success vaddr) (\ (w__0 : bool) . 
+     if (((((bool_to_bits w__0  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) then sail2_state_monad$seqS
+       (wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word)))
+       (sail2_state_monad$returnS T)
+     else sail2_state_monad$bindS
+       (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . 
+       (case w__1 of
+         TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F)
+       | TR_Address (addr) => sail2_state_monad$bindS
+          (case width of
+            WORD => mem_write_ea addr (( 4 : int):ii) aq rl T
+          | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl T
+          | _ => internal_error "STORECON expected word or double"
+          ) (\ (eares : unit MemoryOpResult) . 
+          (case eares of
+            MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+          | MemValue (_) => sail2_state_monad$bindS
+             (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val .  sail2_state_monad$bindS
+             (case width of
+               WORD =>
+                mem_write_value addr (( 4 : int):ii)
+                  ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) aq rl T
+             | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl T
+             | _ => internal_error "STORECON expected word or double"
+             ) (\ (res : unit MemoryOpResult) . 
+             (case res of
+               MemValue (_) => sail2_state_monad$seqS
+                (wX ((regbits_to_regno rd))
+                  ((EXTZ (( 64 : int):ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))
+                (let (_ : unit) = (cancel_reservation () ) in
+                sail2_state_monad$returnS T)
+             | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+             )))
+          ))
+       ))))))`;
+
+
+(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M bool*)
+
+ val _ = Define `
+ ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 width aq rl=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+   let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)) in
+   if ((check_misaligned vaddr width)) then sail2_state_monad$seqS
+     (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS F)
+   else sail2_state_monad$bindS
      (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . 
      (case w__1 of
-       TR_Failure (e) => handle_mem_exception vaddr e
-     | TR_Address (addr) => state_monad$bindS
+       TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F)
+     | TR_Address (addr) => sail2_state_monad$bindS
         (case width of
-          WORD => mem_write_ea addr (( 4 : int):ii) aq rl T
-        | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl T
-        | _ => internal_error "STORECON expected word or double"
+          BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F
+        | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F
+        | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F
+        | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F
         ) (\ (eares : unit MemoryOpResult) . 
         (case eares of
-          MemException (e) => handle_mem_exception addr e
-        | MemValue (_) => state_monad$bindS
-           (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val .  state_monad$bindS
+          MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+        | MemValue (_) => sail2_state_monad$bindS
+           (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val .  sail2_state_monad$bindS
            (case width of
-             WORD =>
+             BYTE =>
+              mem_write_value addr (( 1 : int):ii) ((subrange_vec_dec rs2_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)) aq
+                rl F
+           | HALF =>
+              mem_write_value addr (( 2 : int):ii) ((subrange_vec_dec rs2_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))
+                aq rl F
+           | WORD =>
               mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
-                aq rl T
-           | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl T
-           | _ => internal_error "STORECON expected word or double"
+                aq rl F
+           | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl F
            ) (\ (res : unit MemoryOpResult) . 
            (case res of
-             MemValue (_) => state_monad$returnS () 
-           | MemException (e) => handle_mem_exception addr e
+             MemValue (_) => sail2_state_monad$returnS T
+           | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
            )))
         ))
-     )))))))`;
+     )))))`;
 
 
-(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*)
+(*val execute_STOP_FETCHING : unit -> bool*)
 
  val _ = Define `
- ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs2 rs1 width aq rl=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)) in state_monad$bindS
-   (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . 
-   (case w__1 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) => state_monad$bindS
-      (case width of
-        BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F
-      | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F
-      | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F
-      | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F
-      ) (\ (eares : unit MemoryOpResult) . 
-      (case eares of
-        MemException (e) => handle_mem_exception addr e
-      | MemValue (_) => state_monad$bindS
-         (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val .  state_monad$bindS
-         (case width of
-           BYTE =>
-            mem_write_value addr (( 1 : int):ii) ((subrange_vec_dec rs2_val (( 7 : int):ii) (( 0 : int):ii)  :  8 words$word)) aq
-              rl F
-         | HALF =>
-            mem_write_value addr (( 2 : int):ii) ((subrange_vec_dec rs2_val (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word)) aq
-              rl F
-         | WORD =>
-            mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) aq
-              rl F
-         | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl F
-         ) (\ (res : unit MemoryOpResult) . 
-         (case res of
-           MemValue (_) => state_monad$returnS () 
-         | MemException (e) => handle_mem_exception addr e
-         )))
-      ))
-   )))))`;
+ ((execute_STOP_FETCHING:unit -> bool) g__28=  T)`;
 
 
-(*val execute_SRET : unit -> M unit*)
+(*val execute_SRET : unit -> M bool*)
 
  val _ = Define `
- ((execute_SRET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__108=  (state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
+ ((execute_SRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__24=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$seqS
    (case w__0 of
      User => handle_illegal () 
-   | Supervisor => state_monad$bindS
-      (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . 
+   | Supervisor => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . 
       if (((((get_Mstatus_TSR w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
         handle_illegal () 
-      else state_monad$bindS
-        (state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) .  state_monad$bindS
-        (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  state_monad$bindS
+      else sail2_state_monad$bindS
+        (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) .  sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__3 :  64 words$word) .  sail2_state_monad$bindS
         (handle_exception w__2 (CTL_SRET () ) w__3  : ( 64 words$word) M) (\ (w__4 : xlenbits) . 
-        state_monad$write_regS nextPC_ref w__4))))
-   | Machine => state_monad$bindS
-      (state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) .  state_monad$bindS
-      (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__6 :  64 words$word) .  state_monad$bindS
+        sail2_state_monad$write_regS nextPC_ref w__4))))
+   | Machine => sail2_state_monad$bindS
+      (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__6 :  64 words$word) .  sail2_state_monad$bindS
       (handle_exception w__5 (CTL_SRET () ) w__6  : ( 64 words$word) M) (\ (w__7 : xlenbits) . 
-      state_monad$write_regS nextPC_ref w__7)))
-   ))))`;
+      sail2_state_monad$write_regS nextPC_ref w__7)))
+   )
+   (sail2_state_monad$returnS F))))`;
 
 
-(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*)
+(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M bool*)
 
  val _ = Define `
- ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) shamt rs1 rd op=  (state_monad$bindS
+ ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
    let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in
    let (result : 32 bits) =
@@ -6471,62 +12243,66 @@ val _ = Define `
        RISCV_SLLI => (shift_bits_left rs1_val shamt  :  32 words$word)
      | RISCV_SRLI => (shift_bits_right rs1_val shamt  :  32 words$word)
      | RISCV_SRAI => (shift_right_arith32 rs1_val shamt  :  32 words$word)
-     )) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result  :  64 words$word)))))`;
+     )) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result  :  64 words$word))) (sail2_state_monad$returnS T))))`;
 
 
-(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*)
+(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M bool*)
 
  val _ = Define `
- ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) shamt rs1 rd op=  (state_monad$bindS
+ ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val . 
    let (result : xlenbits) =
      ((case op of
        RISCV_SLLI => (shift_bits_left rs1_val shamt  :  64 words$word)
      | RISCV_SRLI => (shift_bits_right rs1_val shamt  :  64 words$word)
      | RISCV_SRAI => (shift_right_arith64 rs1_val shamt  :  64 words$word)
-     )) in
-   wX ((regbits_to_regno rd)) result)))`;
+     )) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T))))`;
 
 
-(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*)
+(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs1 rs2=  (state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
+ ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs1 rs2=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
    if (((((privLevel_to_bits w__0  :  2 words$word)) = ((privLevel_to_bits User  :  2 words$word)))))
-   then
-     handle_illegal () 
-   else state_monad$bindS
-     (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) .  state_monad$bindS
-     (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . 
-     let p__104 =
+   then sail2_state_monad$seqS
+     (handle_illegal () ) (sail2_state_monad$returnS F)
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) .  sail2_state_monad$bindS
+     (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . 
+     let p__20 =
        (architecture ((get_Mstatus_SXL w__1  :  2 words$word)), (get_Mstatus_TVM w__2  :  1 words$word)) in
-     (case p__104 of
+     (case p__20 of
        (SOME (RV64), v_0) =>
-        if (((v_0 = ((bool_to_bits T  :  1 words$word))))) then handle_illegal () 
-        else state_monad$bindS
-          (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then state_monad$returnS NONE
-           else state_monad$bindS
+        if (((v_0 = ((bool_to_bits T  :  1 words$word))))) then sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)
+        else if (((v_0 = ((bool_to_bits F  :  1 words$word))))) then sail2_state_monad$bindS
+          (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE
+           else sail2_state_monad$bindS
              (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__3 :  64 words$word) . 
-             state_monad$returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):ii) (( 0 : int):ii)  :  39 words$word))))) (\ (addr :
-             vaddr39 option) .  state_monad$bindS
-          (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then state_monad$returnS NONE
-           else state_monad$bindS
+             sail2_state_monad$returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):ii) (( 0 : int):ii)  :  39 words$word))))) (\ (addr :
+             vaddr39 option) .  sail2_state_monad$bindS
+          (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE
+           else sail2_state_monad$bindS
              (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ (w__4 :  64 words$word) . 
-             state_monad$returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))))) (\ (asid :
-             asid64 option) . 
-          flushTLB asid addr))
-     | (g__102, g__103) => internal_error "unimplemented sfence architecture"
+             sail2_state_monad$returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):ii) (( 0 : int):ii)  :  16 words$word))))) (\ (asid :
+             asid64 option) .  sail2_state_monad$seqS
+          (flushTLB asid addr) (sail2_state_monad$returnS T)))
+        else
+          (case (SOME RV64, v_0) of
+            (g__18, g__19) => internal_error "unimplemented sfence architecture"
+          )
+     | (g__18, g__19) => internal_error "unimplemented sfence architecture"
      ))))))`;
 
 
-(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*)
+(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M bool*)
 
  val _ = Define `
- ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd op=  (state_monad$bindS
+ ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in
    let (result : 32 bits) =
@@ -6542,15 +12318,15 @@ val _ = Define `
      | RISCV_SRAW =>
         (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word))
           :  32 words$word)
-     )) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result  :  64 words$word))))))`;
+     )) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result  :  64 words$word))) (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*)
+(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M bool*)
 
  val _ = Define `
- ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd op=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  state_monad$bindS
+ ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val . 
    let (result : xlenbits) =
      ((case op of
@@ -6572,74 +12348,76 @@ val _ = Define `
           :  64 words$word)
      | RISCV_OR => (or_vec rs1_val rs2_val  :  64 words$word)
      | RISCV_AND => (and_vec rs1_val rs2_val  :  64 words$word)
-     )) in
-   wX ((regbits_to_regno rd)) result))))`;
+     )) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd=  (state_monad$bindS
-   (state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$bindS (state_monad$seqS
+ ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
    (wX ((regbits_to_regno rd)) w__0)
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M)) (\ (w__1 :  64 words$word) . 
-   let (newPC : xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)) in
-   state_monad$write_regS
+   let (newPC : xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS
      nextPC_ref
      ((concat_vec ((subrange_vec_dec newPC (( 63 : int):ii) (( 1 : int):ii)  :  63 words$word))
          (vec_of_bits [B0]  :  1 words$word)
-        :  64 words$word))))))`;
+        :  64 words$word)))
+   (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*)
+(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rd=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (pc : xlenbits) .  state_monad$bindS
-   (state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  state_monad$seqS
+ ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (pc : xlenbits) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$seqS
    (wX ((regbits_to_regno rd)) w__0)
-   (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm  :  64 words$word)) in
-   state_monad$write_regS nextPC_ref ((add_vec pc offset  :  64 words$word)))))))`;
+   (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm  :  64 words$word)) in sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPC_ref ((add_vec pc offset  :  64 words$word))) (sail2_state_monad$returnS T))))))`;
 
 
-(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
  val _ = Define `
- ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (state_monad$bindS
+ ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in
    let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
    let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
-   let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) r  :  32 words$word))  :  64 words$word))))))`;
+   let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) r  :  32 words$word))  :  64 words$word)))
+   (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
  val _ = Define `
- ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  state_monad$bindS
+ ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val . 
    let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
    let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
-   let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
-   wX ((regbits_to_regno rd)) ((to_bits xlen r  :  64 words$word))))))`;
+   let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ((to_bits xlen r  :  64 words$word))) (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_NOP : unit -> unit*)
+(*val execute_NOP : unit -> bool*)
 
  val _ = Define `
- ((execute_NOP:unit -> unit) g__111=  () )`;
+ ((execute_NOP:unit -> bool) g__27=  T)`;
 
 
-(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd=  (state_monad$bindS
+ ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in
    let (rs1_int : ii) = (integer_word$w2i rs1_val) in
@@ -6648,97 +12426,113 @@ val _ = Define `
      ((subrange_vec_dec ((to_bits (( 64 : int):ii) ((rs1_int * rs2_int))  :  64 words$word)) (( 31 : int):ii)
         (( 0 : int):ii)
        :  32 words$word)) in
-   let (result : xlenbits) = ((EXTS (( 64 : int):ii) result32  :  64 words$word)) in
-   wX ((regbits_to_regno rd)) result))))`;
+   let (result : xlenbits) = ((EXTS (( 64 : int):ii) result32  :  64 words$word)) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*)
+(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M bool*)
 
  val _ = Define `
- ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  state_monad$bindS
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val . 
    let (rs1_int : ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
    let (rs2_int : ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
    let result128 = ((to_bits (( 128 : int):ii) ((rs1_int * rs2_int))  :  128 words$word)) in
    let result =
      (if high then (subrange_vec_dec result128 (( 127 : int):ii) (( 64 : int):ii)  :  64 words$word)
-     else (subrange_vec_dec result128 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) in
-   wX ((regbits_to_regno rd)) result))))`;
+     else (subrange_vec_dec result128 (( 63 : int):ii) (( 0 : int):ii)  :  64 words$word)) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_MRET : unit -> M unit*)
+(*val execute_MRET : unit -> M bool*)
 
  val _ = Define `
- ((execute_MRET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__107=  (state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
-   if (((((privLevel_to_bits w__0  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))))
-   then state_monad$bindS
-     (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) .  state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  state_monad$bindS
-     (handle_exception w__1 (CTL_MRET () ) w__2  : ( 64 words$word) M) (\ (w__3 : xlenbits) . 
-     state_monad$write_regS nextPC_ref w__3)))
-   else handle_illegal () )))`;
+ ((execute_MRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__23=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$seqS
+   (if (((((privLevel_to_bits w__0  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))))
+    then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) .  sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  sail2_state_monad$bindS
+      (handle_exception w__1 (CTL_MRET () ) w__2  : ( 64 words$word) M) (\ (w__3 : xlenbits) . 
+      sail2_state_monad$write_regS nextPC_ref w__3)))
+    else handle_illegal () )
+   (sail2_state_monad$returnS F))))`;
 
 
-(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*)
+(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) aq rl rs1 width rd=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (vaddr : xlenbits) .  state_monad$bindS
-   (translateAddr vaddr Read Data) (\ (w__0 : TR_Result) . 
-   (case w__0 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) =>
-      (case width of
-        WORD => state_monad$bindS
-         (mem_read addr (( 4 : int):ii) aq rl T  : ( ( 32 words$word)MemoryOpResult) M) (\ (w__1 : ( 32 words$word)
-           MemoryOpResult) . 
-         process_load rd addr w__1 F)
-      | DOUBLE => state_monad$bindS
-         (mem_read addr (( 8 : int):ii) aq rl T  : ( ( 64 words$word)MemoryOpResult) M) (\ (w__2 : ( 64 words$word)
-           MemoryOpResult) . 
-         process_load rd addr w__2 F)
-      | _ => internal_error "LOADRES expected WORD or DOUBLE"
-      )
-   )))))`;
+ ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs1 width rd=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (vaddr : xlenbits) . 
+   let (aligned : bool) =
+     ((case width of
+       BYTE => T
+     | HALF =>
+        (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii)))  :  1 words$word)) = (vec_of_bits [B0]  :  1 words$word))
+     | WORD =>
+        (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))
+     | DOUBLE =>
+        (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))
+     )) in
+   if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS F)
+   else sail2_state_monad$bindS
+     (translateAddr vaddr Read Data) (\ (w__0 : TR_Result) . 
+     (case w__0 of
+       TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F)
+     | TR_Address (addr) =>
+        (case width of
+          WORD => sail2_state_monad$bindS
+           (mem_read addr (( 4 : int):ii) aq rl T  : ( ( 32 words$word)MemoryOpResult) M) (\ (w__1 : ( 32 words$word)
+             MemoryOpResult) . 
+           process_loadres rd vaddr w__1 F)
+        | DOUBLE => sail2_state_monad$bindS
+           (mem_read addr (( 8 : int):ii) aq rl T  : ( ( 64 words$word)MemoryOpResult) M) (\ (w__3 : ( 64 words$word)
+             MemoryOpResult) . 
+           process_loadres rd vaddr w__3 F)
+        | _ => internal_error "LOADRES expected WORD or DOUBLE"
+        )
+     )))))`;
 
 
-(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*)
+(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M bool*)
 
  val _ = Define `
- ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl=  (state_monad$bindS
+ ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)) in state_monad$bindS
-   (translateAddr vaddr Read Data) (\ (w__1 : TR_Result) . 
-   (case w__1 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) =>
-      (case width of
-        BYTE => state_monad$bindS
-         (mem_read addr (( 1 : int):ii) aq rl F  : ( ( 8 words$word)MemoryOpResult) M) (\ (w__2 : ( 8 words$word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__2 is_unsigned)
-      | HALF => state_monad$bindS
-         (mem_read addr (( 2 : int):ii) aq rl F  : ( ( 16 words$word)MemoryOpResult) M) (\ (w__3 : ( 16 words$word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__3 is_unsigned)
-      | WORD => state_monad$bindS
-         (mem_read addr (( 4 : int):ii) aq rl F  : ( ( 32 words$word)MemoryOpResult) M) (\ (w__4 : ( 32 words$word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__4 is_unsigned)
-      | DOUBLE => state_monad$bindS
-         (mem_read addr (( 8 : int):ii) aq rl F  : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__5 is_unsigned)
-      )
-   )))))`;
-
-
-(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*)
+   let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)) in
+   if ((check_misaligned vaddr width)) then sail2_state_monad$seqS
+     (handle_mem_exception vaddr E_Load_Addr_Align) (sail2_state_monad$returnS F)
+   else sail2_state_monad$bindS
+     (translateAddr vaddr Read Data) (\ (w__1 : TR_Result) . 
+     (case w__1 of
+       TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F)
+     | TR_Address (addr) =>
+        (case width of
+          BYTE => sail2_state_monad$bindS
+           (mem_read addr (( 1 : int):ii) aq rl F  : ( ( 8 words$word)MemoryOpResult) M) (\ (w__2 : ( 8 words$word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__2 is_unsigned)
+        | HALF => sail2_state_monad$bindS
+           (mem_read addr (( 2 : int):ii) aq rl F  : ( ( 16 words$word)MemoryOpResult) M) (\ (w__4 : ( 16 words$word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__4 is_unsigned)
+        | WORD => sail2_state_monad$bindS
+           (mem_read addr (( 4 : int):ii) aq rl F  : ( ( 32 words$word)MemoryOpResult) M) (\ (w__6 : ( 32 words$word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__6 is_unsigned)
+        | DOUBLE => sail2_state_monad$bindS
+           (mem_read addr (( 8 : int):ii) aq rl F  : ( ( 64 words$word)MemoryOpResult) M) (\ (w__8 : ( 64 words$word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__8 is_unsigned)
+        )
+     )))))`;
+
+
+(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M bool*)
 
  val _ = Define `
- ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd op=  (state_monad$bindS
+ ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd op=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val . 
    let (immext : xlenbits) = ((EXTS (( 64 : int):ii) imm  :  64 words$word)) in
    let (result : xlenbits) =
@@ -6751,48 +12545,61 @@ val _ = Define `
      | RISCV_XORI => (xor_vec rs1_val immext  :  64 words$word)
      | RISCV_ORI => (or_vec rs1_val immext  :  64 words$word)
      | RISCV_ANDI => (and_vec rs1_val immext  :  64 words$word)
-     )) in
-   wX ((regbits_to_regno rd)) result)))`;
+     )) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T))))`;
 
 
-(*val execute_ILLEGAL : unit -> M unit*)
+(*val execute_ILLEGAL : mword ty32 -> M bool*)
 
  val _ = Define `
- ((execute_ILLEGAL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__112=  (handle_illegal () ))`;
+ ((execute_ILLEGAL:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=  (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)))`;
 
 
-(*val execute_FENCEI : unit -> M unit*)
+(*val execute_FENCEI : unit -> M bool*)
 
  val _ = Define `
- ((execute_FENCEI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__105=  (MEM_fence_i () ))`;
+ ((execute_FENCEI:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__21=  (sail2_state_monad$seqS (MEM_fence_i () ) (sail2_state_monad$returnS T)))`;
 
 
-(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*)
+(*val execute_FENCE : mword ty4 -> mword ty4 -> M bool*)
 
  val _ = Define `
- ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) pred succ= 
-  ((case (pred, succ) of
-         (b__0, b__1) =>
-   if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\
-           (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then
-     MEM_fence_rw_rw ()  else
-     if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\
-             (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then
-       MEM_fence_r_rw ()  else
-       if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\
-               (((b__1 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then
-         MEM_fence_r_r ()  else
-         if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\
-                 (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word))))))) then
-           MEM_fence_rw_w ()  else MEM_fence_w_w () 
-   )))`;
+ ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pred succ=  (sail2_state_monad$seqS
+   (case (pred, succ) of
+     (v__132, v__133) =>
+      if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))) then
+        MEM_fence_rw_rw () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))) then
+        MEM_fence_r_rw () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+        MEM_fence_r_r () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+        MEM_fence_rw_w () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+        MEM_fence_w_w () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))) then
+        MEM_fence_w_rw () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+        MEM_fence_rw_r () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+        MEM_fence_r_w () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+        MEM_fence_w_r () 
+      else
+        sail2_state_monad$returnS (if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+                  () 
+                else
+                  let (_ : unit) = (print_endline "FIXME: unsupported fence") in
+                  () )
+   )
+   (sail2_state_monad$returnS T)))`;
 
 
-(*val execute_ECALL : unit -> M unit*)
+(*val execute_ECALL : unit -> M bool*)
 
  val _ = Define `
- ((execute_ECALL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__106=  (state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
+ ((execute_ECALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__22=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . 
    let (t : sync_exception) =
      (<| sync_exception_trap :=
           ((case w__0 of
@@ -6800,27 +12607,27 @@ val _ = Define `
           | Supervisor => E_S_EnvCall
           | Machine => E_M_EnvCall
           )); 
-        sync_exception_excinfo := NONE |>) in state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) .  state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  state_monad$bindS
-   (handle_exception w__1 (CTL_TRAP t) w__2  : ( 64 words$word) M) (\ (w__3 : xlenbits) . 
-   state_monad$write_regS nextPC_ref w__3))))))`;
+        sync_exception_excinfo := NONE |>) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__2 :  64 words$word) .  sail2_state_monad$bindS
+   (handle_exception w__1 (CTL_TRAP t) w__2  : ( 64 words$word) M) (\ (w__3 : xlenbits) .  sail2_state_monad$seqS
+   (sail2_state_monad$write_regS nextPC_ref w__3) (sail2_state_monad$returnS F)))))))`;
 
 
-(*val execute_EBREAK : unit -> M unit*)
+(*val execute_EBREAK : unit -> M bool*)
 
  val _ = Define `
- ((execute_EBREAK:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__109=  (state_monad$bindS
-   (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   handle_mem_exception w__0 E_Breakpoint)))`;
+ ((execute_EBREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__25=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) .  sail2_state_monad$seqS
+   (handle_mem_exception w__0 E_Breakpoint) (sail2_state_monad$returnS F))))`;
 
 
-(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
  val _ = Define `
- ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (state_monad$bindS
+ ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in state_monad$bindS
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
    let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) in
    let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
@@ -6829,50 +12636,57 @@ val _ = Define `
    let (q' : ii) =
      (if (((s /\ ((q > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then
        (( 0 : int):ii) - ((ex_int ((pow0 (( 2 : int):ii) (( 31 : int):ii)))))
-     else q) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) q'  :  32 words$word))  :  64 words$word))))))`;
+     else q) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) q'  :  32 words$word))  :  64 words$word)))
+   (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
  val _ = Define `
- ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  state_monad$bindS
+ ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val . 
    let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
    let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
    let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in
-   let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in
-   wX ((regbits_to_regno rd)) ((to_bits xlen q'  :  64 words$word))))))`;
+   let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd)) ((to_bits xlen q'  :  64 words$word))) (sail2_state_monad$returnS T)))))`;
+
+
+(*val execute_C_ILLEGAL : unit -> M bool*)
+
+ val _ = Define `
+ ((execute_C_ILLEGAL:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__30=  (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)))`;
 
 
-(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*)
+(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rsd=
-    (let (imm : 32 bits) = ((EXTS (( 32 : int):ii) imm  :  32 words$word)) in state_monad$bindS
+ ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rsd=
+    (let (imm : 32 bits) = ((EXTS (( 32 : int):ii) imm  :  32 words$word)) in sail2_state_monad$bindS
    (rX ((regbits_to_regno rsd))  : ( 64 words$word) M) (\ rs_val . 
    let (res : 32 bits) =
-     ((add_vec ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) imm  :  32 words$word)) in
-   wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):ii) res  :  64 words$word)))))`;
+     ((add_vec ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word)) imm  :  32 words$word)) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):ii) res  :  64 words$word))) (sail2_state_monad$returnS T))))`;
 
 
-(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*)
+(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M bool*)
 
  val _ = Define `
- ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) csr rs1 rd is_imm op=  (state_monad$bindS
-   (if is_imm then state_monad$returnS ((EXTZ (( 64 : int):ii) rs1  :  64 words$word))
+ ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr rs1 rd is_imm op=  (sail2_state_monad$bindS
+   (if is_imm then sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) rs1  :  64 words$word))
     else (rX ((regbits_to_regno rs1))  : ( 64 words$word) M)) (\ (rs1_val : xlenbits) . 
    let (isWrite : bool) =
      ((case op of
        CSRRW => T
      | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii))
-     )) in state_monad$bindS
-   (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) .  state_monad$bindS
+     )) in sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) .  sail2_state_monad$bindS
    (check_CSR csr w__1 isWrite) (\ (w__2 : bool) . 
-   if ((~ w__2)) then handle_illegal () 
-   else state_monad$bindS
-     (readCSR csr  : ( 64 words$word) M) (\ csr_val .  state_monad$seqS
+   if ((~ w__2)) then sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)
+   else sail2_state_monad$bindS
+     (readCSR csr  : ( 64 words$word) M) (\ csr_val .  sail2_state_monad$seqS (sail2_state_monad$seqS
      (if isWrite then
         let (new_val : xlenbits) =
           ((case op of
@@ -6881,15 +12695,15 @@ val _ = Define `
           | CSRRC => (and_vec csr_val ((not_vec rs1_val  :  64 words$word))  :  64 words$word)
           )) in
         writeCSR csr new_val
-      else state_monad$returnS () )
-     (wX ((regbits_to_regno rd)) csr_val)))))))`;
+      else sail2_state_monad$returnS () )
+     (wX ((regbits_to_regno rd)) csr_val)) (sail2_state_monad$returnS T)))))))`;
 
 
-(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*)
+(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M bool*)
 
  val _ = Define `
- ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs2 rs1 op=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  state_monad$bindS
+ ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 op=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ rs1_val .  sail2_state_monad$bindS
    (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ rs2_val . 
    let (taken : bool) =
      ((case op of
@@ -6899,44 +12713,45 @@ val _ = Define `
      | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
      | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
      | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
-     )) in
-   if taken then state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-     state_monad$write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))
-   else state_monad$returnS () ))))`;
+     )) in sail2_state_monad$seqS
+   (if taken then sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+      sail2_state_monad$write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):ii) imm  :  64 words$word))  :  64 words$word)))
+    else sail2_state_monad$returnS () )
+   (sail2_state_monad$returnS T)))))`;
 
 
-(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*)
+(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) op aq rl rs2 rs1 width rd=  (state_monad$bindS
-   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (vaddr : xlenbits) .  state_monad$bindS
+ ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op aq rl rs2 rs1 width rd=  (sail2_state_monad$bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (vaddr : xlenbits) .  sail2_state_monad$bindS
    (translateAddr vaddr ReadWrite Data) (\ (w__0 : TR_Result) . 
    (case w__0 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) => state_monad$bindS
+     TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F)
+   | TR_Address (addr) => sail2_state_monad$bindS
       (case width of
         WORD => mem_write_ea addr (( 4 : int):ii) (((aq /\ rl))) rl T
       | DOUBLE => mem_write_ea addr (( 8 : int):ii) (((aq /\ rl))) rl T
       | _ => internal_error "AMO expected WORD or DOUBLE"
       ) (\ (eares : unit MemoryOpResult) . 
       (case eares of
-        MemException (e) => handle_mem_exception addr e
-      | MemValue (_) => state_monad$bindS
+        MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+      | MemValue (_) => sail2_state_monad$bindS
          (case width of
-           WORD => state_monad$bindS
+           WORD => sail2_state_monad$bindS
             (mem_read addr (( 4 : int):ii) aq (((aq /\ rl))) T  : ( ( 32 words$word)MemoryOpResult) M) (\ (w__4 : ( 32 words$word)
               MemoryOpResult) . 
-            state_monad$returnS ((extend_value F w__4  : ( 64 words$word) MemoryOpResult)))
-         | DOUBLE => state_monad$bindS
+            sail2_state_monad$returnS ((extend_value F w__4  : ( 64 words$word) MemoryOpResult)))
+         | DOUBLE => sail2_state_monad$bindS
             (mem_read addr (( 8 : int):ii) aq (((aq /\ rl))) T  : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word)
               MemoryOpResult) . 
-            state_monad$returnS ((extend_value F w__5  : ( 64 words$word) MemoryOpResult)))
+            sail2_state_monad$returnS ((extend_value F w__5  : ( 64 words$word) MemoryOpResult)))
          | _ => (internal_error "AMO expected WORD or DOUBLE"  : ( ( 64 words$word)MemoryOpResult) M)
          ) (\ (rval : xlenbits MemoryOpResult) . 
          (case rval of
-           MemException (e) => handle_mem_exception addr e
-         | MemValue (loaded) => state_monad$bindS
+           MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
+         | MemValue (loaded) => sail2_state_monad$bindS
             (rX ((regbits_to_regno rs2))  : ( 64 words$word) M) (\ (rs2_val : xlenbits) . 
             let (result : xlenbits) =
               ((case op of
@@ -6949,7 +12764,7 @@ val _ = Define `
               | AMOMAX => (vector64 ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded))))  :  64 words$word)
               | AMOMINU => (vector64 ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded))))  :  64 words$word)
               | AMOMAXU => (vector64 ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded))))  :  64 words$word)
-              )) in state_monad$bindS
+              )) in sail2_state_monad$bindS
             (case width of
               WORD =>
                mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))
@@ -6958,26 +12773,27 @@ val _ = Define `
             | _ => internal_error "AMO expected WORD or DOUBLE"
             ) (\ (wval : unit MemoryOpResult) . 
             (case wval of
-              MemValue (_) => wX ((regbits_to_regno rd)) loaded
-            | MemException (e) => handle_mem_exception addr e
+              MemValue (_) => sail2_state_monad$seqS (wX ((regbits_to_regno rd)) loaded) (sail2_state_monad$returnS T)
+            | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F)
             )))
          ))
       ))
    )))))`;
 
 
-(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M bool*)
 
  val _ = Define `
- ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd=  (state_monad$bindS
+ ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd=  (sail2_state_monad$bindS
    (rX ((regbits_to_regno rs1))  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
-   let (result : xlenbits) = ((add_vec ((EXTS (( 64 : int):ii) imm  :  64 words$word)) w__0  :  64 words$word)) in
-   wX ((regbits_to_regno rd))
-     ((EXTS (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word)))))`;
+   let (result : xlenbits) = ((add_vec ((EXTS (( 64 : int):ii) imm  :  64 words$word)) w__0  :  64 words$word)) in sail2_state_monad$seqS
+   (wX ((regbits_to_regno rd))
+     ((EXTS (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii)  :  32 words$word))  :  64 words$word)))
+   (sail2_state_monad$returnS T))))`;
 
 
  val execute_defn = Hol_defn "execute" `
- ((execute:ast ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) merge_var=
+ ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var=
     ((case merge_var of
      C_ADDI4SPN (rdc,nzimm) =>
       let (imm : 12 bits) =
@@ -7123,310 +12939,9894 @@ val _ = Define `
    | DIVW (rs2,rs1,rd,s) => execute_DIVW rs2 rs1 rd s
    | REMW (rs2,rs1,rd,s) => execute_REMW rs2 rs1 rd s
    | FENCE (pred,succ) => execute_FENCE pred succ
-   | FENCEI (g__105) => execute_FENCEI g__105
-   | ECALL (g__106) => execute_ECALL g__106
-   | MRET (g__107) => execute_MRET g__107
-   | SRET (g__108) => execute_SRET g__108
-   | EBREAK (g__109) => execute_EBREAK g__109
-   | WFI (g__110) => execute_WFI g__110
+   | FENCEI (g__21) => execute_FENCEI g__21
+   | ECALL (g__22) => execute_ECALL g__22
+   | MRET (g__23) => execute_MRET g__23
+   | SRET (g__24) => execute_SRET g__24
+   | EBREAK (g__25) => execute_EBREAK g__25
+   | WFI (g__26) => execute_WFI g__26
    | SFENCE_VMA (rs1,rs2) => execute_SFENCE_VMA rs1 rs2
    | LOADRES (aq,rl,rs1,width,rd) => execute_LOADRES aq rl rs1 width rd
    | STORECON (aq,rl,rs2,rs1,width,rd) => execute_STORECON aq rl rs2 rs1 width rd
    | AMO (op,aq,rl,rs2,rs1,width,rd) => execute_AMO op aq rl rs2 rs1 width rd
    | CSR (csr,rs1,rd,is_imm,op) => execute_CSR csr rs1 rd is_imm op
-   | NOP (g__111) => state_monad$returnS ((execute_NOP g__111))
-   | ILLEGAL (g__112) => execute_ILLEGAL g__112
+   | NOP (g__27) => sail2_state_monad$returnS ((execute_NOP g__27))
    | C_ADDIW (imm,rsd) => execute_C_ADDIW imm rsd
+   | STOP_FETCHING (g__28) => sail2_state_monad$returnS ((execute_STOP_FETCHING g__28))
+   | THREAD_START (g__29) => sail2_state_monad$returnS ((execute_THREAD_START g__29))
+   | ILLEGAL (s) => execute_ILLEGAL s
+   | C_ILLEGAL (g__30) => execute_C_ILLEGAL g__30
    )))`;
 
 val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn;
 
+(*val assembly_forwards : ast -> string*)
+
 val _ = Define `
- ((print_insn:ast -> string) merge_var=
-    ((case merge_var of
+ ((assembly_forwards:ast -> string) arg_=
+    ((case arg_ of
      UTYPE (imm,rd,op) =>
-      (case op of
-        RISCV_LUI =>
-         STRCAT "lui   "
-           ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
-      | RISCV_AUIPC =>
-         STRCAT "auipc "
-           ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
-      )
+      string_append ((utype_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) ""))))))))
    | RISCV_JAL (imm,rd) =>
-      STRCAT "jal   "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+      string_append "jal"
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) ""))))))))
    | RISCV_JALR (imm,rs1,rd) =>
-      STRCAT "jalr  "
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+      string_append "jalr"
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) ""))))))))))))
    | BTYPE (imm,rs2,rs1,op) =>
-      let (insn : string) =
-        ((case op of
-          RISCV_BEQ => "beq   "
-        | RISCV_BNE => "bne   "
-        | RISCV_BLT => "blt   "
-        | RISCV_BGE => "bge   "
-        | RISCV_BLTU => "bltu  "
-        | RISCV_BGEU => "bgeu  "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rs1))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs2)) ((STRCAT ", " ((string_of_vec imm))))))))))
+      string_append ((btype_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rs1))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs2))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) ""))))))))))))
    | ITYPE (imm,rs1,rd,op) =>
-      let (insn : string) =
-        ((case op of
-          RISCV_ADDI => "addi  "
-        | RISCV_SLTI => "slti  "
-        | RISCV_SLTIU => "sltiu "
-        | RISCV_XORI => "xori  "
-        | RISCV_ORI => "ori   "
-        | RISCV_ANDI => "andi  "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+      string_append ((itype_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) ""))))))))))))
    | SHIFTIOP (shamt,rs1,rd,op) =>
-      let (insn : string) =
-        ((case op of   RISCV_SLLI => "slli  " | RISCV_SRLI => "srli  " | RISCV_SRAI => "srai  " )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt))))))))))
+      string_append ((shiftiop_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((string_of_bits shamt)) ""))))))))))
    | RTYPE (rs2,rs1,rd,op) =>
-      let (insn : string) =
-        ((case op of
-          RISCV_ADD => "add   "
-        | RISCV_SUB => "sub   "
-        | RISCV_SLL => "sll   "
-        | RISCV_SLT => "slt   "
-        | RISCV_SLTU => "sltu  "
-        | RISCV_XOR => "xor   "
-        | RISCV_SRL => "srl   "
-        | RISCV_SRA => "sra   "
-        | RISCV_OR => "or    "
-        | RISCV_AND => "and   "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
-   | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) =>
-      let (insn : string) =
-        ((case (width, is_unsigned) of
-          (BYTE, F) => "lb    "
-        | (BYTE, T) => "lbu   "
-        | (HALF, F) => "lh    "
-        | (HALF, T) => "lhu   "
-        | (WORD, F) => "lw    "
-        | (WORD, T) => "lwu   "
-        | (DOUBLE, F) => "ld    "
-        | (DOUBLE, T) => "ldu   "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
-   | STORE (imm,rs2,rs1,width,aq,rl) =>
-      let (insn : string) =
-        ((case width of
-          BYTE => "sb    "
-        | HALF => "sh    "
-        | WORD => "sw    "
-        | DOUBLE => "sd    "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rs2))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+      string_append ((rtype_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) ""))))))))))))
+   | LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl) =>
+      string_append "l"
+        ((string_append ((size_mnemonic_forwards size1))
+            ((string_append ((maybe_u_forwards is_unsigned))
+                ((string_append ((maybe_aq_forwards aq))
+                    ((string_append ((maybe_rl_forwards rl))
+                        ((string_append ((spc_forwards () ))
+                            ((string_append ((reg_name_forwards rd))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs1))
+                                        ((string_append ((sep_forwards () ))
+                                            ((string_append ((string_of_bits imm)) ""))))))))))))))))))))
+   | STORE (imm,rs1,rd,size1,aq,rl) =>
+      string_append "s"
+        ((string_append ((size_mnemonic_forwards size1))
+            ((string_append ((maybe_aq_forwards aq))
+                ((string_append ((maybe_rl_forwards rl))
+                    ((string_append ((spc_forwards () ))
+                        ((string_append ((reg_name_forwards rd))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs1))
+                                    ((string_append ((sep_forwards () ))
+                                        ((string_append ((string_of_bits imm)) ""))))))))))))))))))
+   | ADDIW (imm,rs1,rd) =>
+      string_append "addiw"
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) ""))))))))))))
+   | SHIFTW (shamt,rs1,rd,op) =>
+      string_append ((shiftw_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits shamt)) ""))))))))))))
+   | RTYPEW (rs2,rs1,rd,op) =>
+      string_append ((rtypew_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) ""))))))))))))
+   | MUL (rs2,rs1,rd,high,signed1,signed2) =>
+      string_append ((mul_mnemonic_forwards high signed1 signed2))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) ""))))))))))))
+   | DIV0 (rs2,rs1,rd,s) =>
+      string_append "div"
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append ((spc_forwards () ))
+                ((string_append ((reg_name_forwards rd))
+                    ((string_append ((sep_forwards () ))
+                        ((string_append ((reg_name_forwards rs1))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs2)) ""))))))))))))))
+   | REM (rs2,rs1,rd,s) =>
+      string_append "rem"
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append ((spc_forwards () ))
+                ((string_append ((reg_name_forwards rd))
+                    ((string_append ((sep_forwards () ))
+                        ((string_append ((reg_name_forwards rs1))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs2)) ""))))))))))))))
+   | MULW (rs2,rs1,rd) =>
+      string_append "mulw"
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) ""))))))))))))
+   | DIVW (rs2,rs1,rd,s) =>
+      string_append "div"
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append "w"
+                ((string_append ((spc_forwards () ))
+                    ((string_append ((reg_name_forwards rd))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs1))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs2)) ""))))))))))))))))
+   | REMW (rs2,rs1,rd,s) =>
+      string_append "rem"
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append "w"
+                ((string_append ((spc_forwards () ))
+                    ((string_append ((reg_name_forwards rd))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs1))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs2)) ""))))))))))))))))
+   | FENCE (pred,succ) =>
+      string_append "fence"
+        ((string_append ((spc_forwards () ))
+            ((string_append ((fence_bits_forwards pred))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((fence_bits_forwards succ)) ""))))))))
+   | FENCEI (() ) => "fence.i"
+   | ECALL (() ) => "ecall"
+   | MRET (() ) => "mret"
+   | SRET (() ) => "sret"
+   | EBREAK (() ) => "ebreak"
+   | WFI (() ) => "wfi"
+   | SFENCE_VMA (rs1,rs2) =>
+      string_append "sfence.vma"
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rs1))
+                ((string_append ((sep_forwards () )) ((string_append ((reg_name_forwards rs2)) ""))))))))
+   | LOADRES (aq,rl,rs1,size1,rd) =>
+      string_append "lr."
+        ((string_append ((maybe_aq_forwards aq))
+            ((string_append ((maybe_rl_forwards rl))
+                ((string_append ((size_mnemonic_forwards size1))
+                    ((string_append ((spc_forwards () ))
+                        ((string_append ((reg_name_forwards rd))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs1)) ""))))))))))))))
+   | STORECON (aq,rl,rs2,rs1,size1,rd) =>
+      string_append "sc."
+        ((string_append ((maybe_aq_forwards aq))
+            ((string_append ((maybe_rl_forwards rl))
+                ((string_append ((size_mnemonic_forwards size1))
+                    ((string_append ((spc_forwards () ))
+                        ((string_append ((reg_name_forwards rd))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs1))
+                                    ((string_append ((sep_forwards () ))
+                                        ((string_append ((reg_name_forwards rs2)) ""))))))))))))))))))
+   | AMO (op,aq,rl,rs2,rs1,width,rd) =>
+      string_append ((amo_mnemonic_forwards op))
+        ((string_append "."
+            ((string_append ((size_mnemonic_forwards width))
+                ((string_append ((maybe_aq_forwards aq))
+                    ((string_append ((maybe_rl_forwards rl))
+                        ((string_append ((spc_forwards () ))
+                            ((string_append ((reg_name_forwards rd))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs1))
+                                        ((string_append ((sep_forwards () ))
+                                            ((string_append ((reg_name_forwards rs2)) ""))))))))))))))))))))
+   | CSR (csr,rs1,rd,T,op) =>
+      string_append ((csr_mnemonic_forwards op))
+        ((string_append "i"
+            ((string_append ((spc_forwards () ))
+                ((string_append ((reg_name_forwards rd))
+                    ((string_append ((sep_forwards () ))
+                        ((string_append ((string_of_bits rs1))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((csr_name_map_forwards csr)) ""))))))))))))))
+   | CSR (csr,rs1,rd,F,op) =>
+      string_append ((csr_mnemonic_forwards op))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((csr_name_map_forwards csr)) ""))))))))))))
+   | ILLEGAL (s) =>
+      string_append "illegal"
+        ((string_append ((spc_forwards () )) ((string_append ((string_of_bits s)) ""))))
+   )))`;
+
+
+(*val assembly_backwards : string -> ast*)
+
+val _ = Define `
+ ((assembly_backwards:string -> ast) arg_=
+    (let stringappend_1076_0 = arg_ in
+   if ((case ((utype_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1077_0,stringappend_1078_0) =>
+        let stringappend_1079_0 = (string_drop stringappend_1076_0 stringappend_1078_0) in
+        if ((case ((spc_matches_prefix stringappend_1079_0)) of
+            SOME (stringappend_1080_0,stringappend_1081_0) =>
+             let stringappend_1082_0 = (string_drop stringappend_1079_0 stringappend_1081_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1082_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1083_0,stringappend_1084_0) =>
+                  let stringappend_1085_0 = (string_drop stringappend_1082_0 stringappend_1084_0) in
+                  if ((case ((sep_matches_prefix stringappend_1085_0)) of
+                      SOME (stringappend_1086_0,stringappend_1087_0) =>
+                       let stringappend_1088_0 = (string_drop stringappend_1085_0 stringappend_1087_0) in
+                       if ((case ((hex_bits_20_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1088_0
+                                    :  (( 20 words$word # ii))option)) of
+                           SOME (stringappend_1089_0,stringappend_1090_0) =>
+                            (case ((string_drop stringappend_1088_0 stringappend_1090_0)) of
+                              "" => T
+                            | _ => F
+                            )
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1078_0) =
+       ((case ((utype_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1077_0,stringappend_1078_0) =>
+          (stringappend_1077_0, stringappend_1078_0)
+       )) in
+     let stringappend_1079_0 = (string_drop stringappend_1076_0 stringappend_1078_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1079_0)) of
+        SOME (stringappend_1080_0,stringappend_1081_0) =>
+  (stringappend_1080_0, stringappend_1081_0)
+  ) of
+      (() , stringappend_1081_0) =>
+  let stringappend_1082_0 = (string_drop stringappend_1079_0
+                               stringappend_1081_0) in
+  let (rd, stringappend_1084_0) =
+      ((case ((reg_name_matches_prefix stringappend_1082_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1083_0,stringappend_1084_0) =>
+       (stringappend_1083_0, stringappend_1084_0)
+       )) in
+  let stringappend_1085_0 = (string_drop stringappend_1082_0
+                               stringappend_1084_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1085_0)) of
+        SOME (stringappend_1086_0,stringappend_1087_0) =>
+  (stringappend_1086_0, stringappend_1087_0)
+  ) of
+      (() , stringappend_1087_0) =>
+  let stringappend_1088_0 = (string_drop stringappend_1085_0
+                               stringappend_1087_0) in
+  let (imm, stringappend_1090_0) =
+      ((case ((hex_bits_20_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1088_0 : (( 20 words$word # ii)) option)) of
+             SOME (stringappend_1089_0,stringappend_1090_0) =>
+       (stringappend_1089_0, stringappend_1090_0)
+       )) in
+  (case ((string_drop stringappend_1088_0 stringappend_1090_0)) of
+        "" => UTYPE (imm,rd,op)
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "jal")) /\ (let stringappend_1092_0 = (string_drop stringappend_1076_0 ((string_length "jal"))) in
+               if ((case ((spc_matches_prefix stringappend_1092_0)) of
+                   SOME (stringappend_1093_0,stringappend_1094_0) =>
+                    let stringappend_1095_0 = (string_drop stringappend_1092_0 stringappend_1094_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_1095_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_1096_0,stringappend_1097_0) =>
+                         let stringappend_1098_0 =
+                           (string_drop stringappend_1095_0 stringappend_1097_0) in
+                         if ((case ((sep_matches_prefix stringappend_1098_0)) of
+                             SOME (stringappend_1099_0,stringappend_1100_0) =>
+                              let stringappend_1101_0 =
+                                (string_drop stringappend_1098_0 stringappend_1100_0) in
+                              if ((case ((hex_bits_21_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1101_0
+                                           :  (( 21 words$word # ii))option)) of
+                                  SOME (stringappend_1102_0,stringappend_1103_0) =>
+                                   (case ((string_drop stringappend_1101_0 stringappend_1103_0)) of
+                                     "" => T
+                                   | _ => F
+                                   )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1092_0 = (string_drop stringappend_1076_0 ((string_length "jal"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1092_0)) of
+        SOME (stringappend_1093_0,stringappend_1094_0) =>
+  (stringappend_1093_0, stringappend_1094_0)
+  ) of
+      (() , stringappend_1094_0) =>
+  let stringappend_1095_0 = (string_drop stringappend_1092_0
+                               stringappend_1094_0) in
+  let (rd, stringappend_1097_0) =
+      ((case ((reg_name_matches_prefix stringappend_1095_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1096_0,stringappend_1097_0) =>
+       (stringappend_1096_0, stringappend_1097_0)
+       )) in
+  let stringappend_1098_0 = (string_drop stringappend_1095_0
+                               stringappend_1097_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1098_0)) of
+        SOME (stringappend_1099_0,stringappend_1100_0) =>
+  (stringappend_1099_0, stringappend_1100_0)
+  ) of
+      (() , stringappend_1100_0) =>
+  let stringappend_1101_0 = (string_drop stringappend_1098_0
+                               stringappend_1100_0) in
+  let (imm, stringappend_1103_0) =
+      ((case ((hex_bits_21_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1101_0 : (( 21 words$word # ii)) option)) of
+             SOME (stringappend_1102_0,stringappend_1103_0) =>
+       (stringappend_1102_0, stringappend_1103_0)
+       )) in
+  (case ((string_drop stringappend_1101_0 stringappend_1103_0)) of
+        "" => RISCV_JAL (imm,rd)
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "jalr")) /\ (let stringappend_1105_0 = (string_drop stringappend_1076_0 ((string_length "jalr"))) in
+               if ((case ((spc_matches_prefix stringappend_1105_0)) of
+                   SOME (stringappend_1106_0,stringappend_1107_0) =>
+                    let stringappend_1108_0 = (string_drop stringappend_1105_0 stringappend_1107_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_1108_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_1109_0,stringappend_1110_0) =>
+                         let stringappend_1111_0 =
+                           (string_drop stringappend_1108_0 stringappend_1110_0) in
+                         if ((case ((sep_matches_prefix stringappend_1111_0)) of
+                             SOME (stringappend_1112_0,stringappend_1113_0) =>
+                              let stringappend_1114_0 =
+                                (string_drop stringappend_1111_0 stringappend_1113_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_1114_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_1115_0,stringappend_1116_0) =>
+                                   let stringappend_1117_0 =
+                                     (string_drop stringappend_1114_0 stringappend_1116_0) in
+                                   if ((case ((sep_matches_prefix stringappend_1117_0)) of
+                                       SOME (stringappend_1118_0,stringappend_1119_0) =>
+                                        let stringappend_1120_0 =
+                                          (string_drop stringappend_1117_0 stringappend_1119_0) in
+                                        if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1120_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_1121_0,stringappend_1122_0) =>
+                                             (case ((string_drop stringappend_1120_0
+                                                       stringappend_1122_0)) of
+                                               "" => T
+                                             | _ => F
+                                             )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1105_0 = (string_drop stringappend_1076_0 ((string_length "jalr"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1105_0)) of
+        SOME (stringappend_1106_0,stringappend_1107_0) =>
+  (stringappend_1106_0, stringappend_1107_0)
+  ) of
+      (() , stringappend_1107_0) =>
+  let stringappend_1108_0 = (string_drop stringappend_1105_0
+                               stringappend_1107_0) in
+  let (rd, stringappend_1110_0) =
+      ((case ((reg_name_matches_prefix stringappend_1108_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1109_0,stringappend_1110_0) =>
+       (stringappend_1109_0, stringappend_1110_0)
+       )) in
+  let stringappend_1111_0 = (string_drop stringappend_1108_0
+                               stringappend_1110_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1111_0)) of
+        SOME (stringappend_1112_0,stringappend_1113_0) =>
+  (stringappend_1112_0, stringappend_1113_0)
+  ) of
+      (() , stringappend_1113_0) =>
+  let stringappend_1114_0 = (string_drop stringappend_1111_0
+                               stringappend_1113_0) in
+  let (rs1, stringappend_1116_0) =
+      ((case ((reg_name_matches_prefix stringappend_1114_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1115_0,stringappend_1116_0) =>
+       (stringappend_1115_0, stringappend_1116_0)
+       )) in
+  let stringappend_1117_0 = (string_drop stringappend_1114_0
+                               stringappend_1116_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1117_0)) of
+        SOME (stringappend_1118_0,stringappend_1119_0) =>
+  (stringappend_1118_0, stringappend_1119_0)
+  ) of
+      (() , stringappend_1119_0) =>
+  let stringappend_1120_0 = (string_drop stringappend_1117_0
+                               stringappend_1119_0) in
+  let (imm, stringappend_1122_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1120_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1121_0,stringappend_1122_0) =>
+       (stringappend_1121_0, stringappend_1122_0)
+       )) in
+  (case ((string_drop stringappend_1120_0 stringappend_1122_0)) of
+        "" => RISCV_JALR (imm,rs1,rd)
+  )
+  )
+  )
+  )
+   else if ((case ((btype_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1124_0,stringappend_1125_0) =>
+        let stringappend_1126_0 = (string_drop stringappend_1076_0 stringappend_1125_0) in
+        if ((case ((spc_matches_prefix stringappend_1126_0)) of
+            SOME (stringappend_1127_0,stringappend_1128_0) =>
+             let stringappend_1129_0 = (string_drop stringappend_1126_0 stringappend_1128_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1129_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1130_0,stringappend_1131_0) =>
+                  let stringappend_1132_0 = (string_drop stringappend_1129_0 stringappend_1131_0) in
+                  if ((case ((sep_matches_prefix stringappend_1132_0)) of
+                      SOME (stringappend_1133_0,stringappend_1134_0) =>
+                       let stringappend_1135_0 = (string_drop stringappend_1132_0 stringappend_1134_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1135_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1136_0,stringappend_1137_0) =>
+                            let stringappend_1138_0 =
+                              (string_drop stringappend_1135_0 stringappend_1137_0) in
+                            if ((case ((sep_matches_prefix stringappend_1138_0)) of
+                                SOME (stringappend_1139_0,stringappend_1140_0) =>
+                                 let stringappend_1141_0 =
+                                   (string_drop stringappend_1138_0 stringappend_1140_0) in
+                                 if ((case ((hex_bits_13_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1141_0
+                                              :  (( 13 words$word # ii))option)) of
+                                     SOME (stringappend_1142_0,stringappend_1143_0) =>
+                                      (case ((string_drop stringappend_1141_0 stringappend_1143_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1125_0) =
+       ((case ((btype_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1124_0,stringappend_1125_0) =>
+          (stringappend_1124_0, stringappend_1125_0)
+       )) in
+     let stringappend_1126_0 = (string_drop stringappend_1076_0 stringappend_1125_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1126_0)) of
+        SOME (stringappend_1127_0,stringappend_1128_0) =>
+  (stringappend_1127_0, stringappend_1128_0)
+  ) of
+      (() , stringappend_1128_0) =>
+  let stringappend_1129_0 = (string_drop stringappend_1126_0
+                               stringappend_1128_0) in
+  let (rs1, stringappend_1131_0) =
+      ((case ((reg_name_matches_prefix stringappend_1129_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1130_0,stringappend_1131_0) =>
+       (stringappend_1130_0, stringappend_1131_0)
+       )) in
+  let stringappend_1132_0 = (string_drop stringappend_1129_0
+                               stringappend_1131_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1132_0)) of
+        SOME (stringappend_1133_0,stringappend_1134_0) =>
+  (stringappend_1133_0, stringappend_1134_0)
+  ) of
+      (() , stringappend_1134_0) =>
+  let stringappend_1135_0 = (string_drop stringappend_1132_0
+                               stringappend_1134_0) in
+  let (rs2, stringappend_1137_0) =
+      ((case ((reg_name_matches_prefix stringappend_1135_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1136_0,stringappend_1137_0) =>
+       (stringappend_1136_0, stringappend_1137_0)
+       )) in
+  let stringappend_1138_0 = (string_drop stringappend_1135_0
+                               stringappend_1137_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1138_0)) of
+        SOME (stringappend_1139_0,stringappend_1140_0) =>
+  (stringappend_1139_0, stringappend_1140_0)
+  ) of
+      (() , stringappend_1140_0) =>
+  let stringappend_1141_0 = (string_drop stringappend_1138_0
+                               stringappend_1140_0) in
+  let (imm, stringappend_1143_0) =
+      ((case ((hex_bits_13_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1141_0 : (( 13 words$word # ii)) option)) of
+             SOME (stringappend_1142_0,stringappend_1143_0) =>
+       (stringappend_1142_0, stringappend_1143_0)
+       )) in
+  (case ((string_drop stringappend_1141_0 stringappend_1143_0)) of
+        "" => BTYPE (imm,rs2,rs1,op)
+  )
+  )
+  )
+  )
+   else if ((case ((itype_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1145_0,stringappend_1146_0) =>
+        let stringappend_1147_0 = (string_drop stringappend_1076_0 stringappend_1146_0) in
+        if ((case ((spc_matches_prefix stringappend_1147_0)) of
+            SOME (stringappend_1148_0,stringappend_1149_0) =>
+             let stringappend_1150_0 = (string_drop stringappend_1147_0 stringappend_1149_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1150_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1151_0,stringappend_1152_0) =>
+                  let stringappend_1153_0 = (string_drop stringappend_1150_0 stringappend_1152_0) in
+                  if ((case ((sep_matches_prefix stringappend_1153_0)) of
+                      SOME (stringappend_1154_0,stringappend_1155_0) =>
+                       let stringappend_1156_0 = (string_drop stringappend_1153_0 stringappend_1155_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1156_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1157_0,stringappend_1158_0) =>
+                            let stringappend_1159_0 =
+                              (string_drop stringappend_1156_0 stringappend_1158_0) in
+                            if ((case ((sep_matches_prefix stringappend_1159_0)) of
+                                SOME (stringappend_1160_0,stringappend_1161_0) =>
+                                 let stringappend_1162_0 =
+                                   (string_drop stringappend_1159_0 stringappend_1161_0) in
+                                 if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1162_0
+                                              :  (( 12 words$word # ii))option)) of
+                                     SOME (stringappend_1163_0,stringappend_1164_0) =>
+                                      (case ((string_drop stringappend_1162_0 stringappend_1164_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1146_0) =
+       ((case ((itype_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1145_0,stringappend_1146_0) =>
+          (stringappend_1145_0, stringappend_1146_0)
+       )) in
+     let stringappend_1147_0 = (string_drop stringappend_1076_0 stringappend_1146_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1147_0)) of
+        SOME (stringappend_1148_0,stringappend_1149_0) =>
+  (stringappend_1148_0, stringappend_1149_0)
+  ) of
+      (() , stringappend_1149_0) =>
+  let stringappend_1150_0 = (string_drop stringappend_1147_0
+                               stringappend_1149_0) in
+  let (rd, stringappend_1152_0) =
+      ((case ((reg_name_matches_prefix stringappend_1150_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1151_0,stringappend_1152_0) =>
+       (stringappend_1151_0, stringappend_1152_0)
+       )) in
+  let stringappend_1153_0 = (string_drop stringappend_1150_0
+                               stringappend_1152_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1153_0)) of
+        SOME (stringappend_1154_0,stringappend_1155_0) =>
+  (stringappend_1154_0, stringappend_1155_0)
+  ) of
+      (() , stringappend_1155_0) =>
+  let stringappend_1156_0 = (string_drop stringappend_1153_0
+                               stringappend_1155_0) in
+  let (rs1, stringappend_1158_0) =
+      ((case ((reg_name_matches_prefix stringappend_1156_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1157_0,stringappend_1158_0) =>
+       (stringappend_1157_0, stringappend_1158_0)
+       )) in
+  let stringappend_1159_0 = (string_drop stringappend_1156_0
+                               stringappend_1158_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1159_0)) of
+        SOME (stringappend_1160_0,stringappend_1161_0) =>
+  (stringappend_1160_0, stringappend_1161_0)
+  ) of
+      (() , stringappend_1161_0) =>
+  let stringappend_1162_0 = (string_drop stringappend_1159_0
+                               stringappend_1161_0) in
+  let (imm, stringappend_1164_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1162_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1163_0,stringappend_1164_0) =>
+       (stringappend_1163_0, stringappend_1164_0)
+       )) in
+  (case ((string_drop stringappend_1162_0 stringappend_1164_0)) of
+        "" => ITYPE (imm,rs1,rd,op)
+  )
+  )
+  )
+  )
+   else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1166_0,stringappend_1167_0) =>
+        let stringappend_1168_0 = (string_drop stringappend_1076_0 stringappend_1167_0) in
+        if ((case ((spc_matches_prefix stringappend_1168_0)) of
+            SOME (stringappend_1169_0,stringappend_1170_0) =>
+             let stringappend_1171_0 = (string_drop stringappend_1168_0 stringappend_1170_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1171_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1172_0,stringappend_1173_0) =>
+                  let stringappend_1174_0 = (string_drop stringappend_1171_0 stringappend_1173_0) in
+                  if ((case ((sep_matches_prefix stringappend_1174_0)) of
+                      SOME (stringappend_1175_0,stringappend_1176_0) =>
+                       let stringappend_1177_0 = (string_drop stringappend_1174_0 stringappend_1176_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1177_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1178_0,stringappend_1179_0) =>
+                            let stringappend_1180_0 =
+                              (string_drop stringappend_1177_0 stringappend_1179_0) in
+                            if ((case ((hex_bits_6_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1180_0
+                                         :  (( 6 words$word # ii))option)) of
+                                SOME (stringappend_1181_0,stringappend_1182_0) =>
+                                 (case ((string_drop stringappend_1180_0 stringappend_1182_0)) of
+                                   "" => T
+                                 | _ => F
+                                 )
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1167_0) =
+       ((case ((shiftiop_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1166_0,stringappend_1167_0) =>
+          (stringappend_1166_0, stringappend_1167_0)
+       )) in
+     let stringappend_1168_0 = (string_drop stringappend_1076_0 stringappend_1167_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1168_0)) of
+        SOME (stringappend_1169_0,stringappend_1170_0) =>
+  (stringappend_1169_0, stringappend_1170_0)
+  ) of
+      (() , stringappend_1170_0) =>
+  let stringappend_1171_0 = (string_drop stringappend_1168_0
+                               stringappend_1170_0) in
+  let (rd, stringappend_1173_0) =
+      ((case ((reg_name_matches_prefix stringappend_1171_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1172_0,stringappend_1173_0) =>
+       (stringappend_1172_0, stringappend_1173_0)
+       )) in
+  let stringappend_1174_0 = (string_drop stringappend_1171_0
+                               stringappend_1173_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1174_0)) of
+        SOME (stringappend_1175_0,stringappend_1176_0) =>
+  (stringappend_1175_0, stringappend_1176_0)
+  ) of
+      (() , stringappend_1176_0) =>
+  let stringappend_1177_0 = (string_drop stringappend_1174_0
+                               stringappend_1176_0) in
+  let (rs1, stringappend_1179_0) =
+      ((case ((reg_name_matches_prefix stringappend_1177_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1178_0,stringappend_1179_0) =>
+       (stringappend_1178_0, stringappend_1179_0)
+       )) in
+  let stringappend_1180_0 = (string_drop stringappend_1177_0
+                               stringappend_1179_0) in
+  let (shamt, stringappend_1182_0) =
+      ((case ((hex_bits_6_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1180_0 : (( 6 words$word # ii)) option)) of
+             SOME (stringappend_1181_0,stringappend_1182_0) =>
+       (stringappend_1181_0, stringappend_1182_0)
+       )) in
+  (case ((string_drop stringappend_1180_0 stringappend_1182_0)) of
+        "" => SHIFTIOP (shamt,rs1,rd,op)
+  )
+  )
+  )
+   else if ((case ((rtype_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1184_0,stringappend_1185_0) =>
+        let stringappend_1186_0 = (string_drop stringappend_1076_0 stringappend_1185_0) in
+        if ((case ((spc_matches_prefix stringappend_1186_0)) of
+            SOME (stringappend_1187_0,stringappend_1188_0) =>
+             let stringappend_1189_0 = (string_drop stringappend_1186_0 stringappend_1188_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1189_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1190_0,stringappend_1191_0) =>
+                  let stringappend_1192_0 = (string_drop stringappend_1189_0 stringappend_1191_0) in
+                  if ((case ((sep_matches_prefix stringappend_1192_0)) of
+                      SOME (stringappend_1193_0,stringappend_1194_0) =>
+                       let stringappend_1195_0 = (string_drop stringappend_1192_0 stringappend_1194_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1195_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1196_0,stringappend_1197_0) =>
+                            let stringappend_1198_0 =
+                              (string_drop stringappend_1195_0 stringappend_1197_0) in
+                            if ((case ((sep_matches_prefix stringappend_1198_0)) of
+                                SOME (stringappend_1199_0,stringappend_1200_0) =>
+                                 let stringappend_1201_0 =
+                                   (string_drop stringappend_1198_0 stringappend_1200_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_1201_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_1202_0,stringappend_1203_0) =>
+                                      (case ((string_drop stringappend_1201_0 stringappend_1203_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1185_0) =
+       ((case ((rtype_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1184_0,stringappend_1185_0) =>
+          (stringappend_1184_0, stringappend_1185_0)
+       )) in
+     let stringappend_1186_0 = (string_drop stringappend_1076_0 stringappend_1185_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1186_0)) of
+        SOME (stringappend_1187_0,stringappend_1188_0) =>
+  (stringappend_1187_0, stringappend_1188_0)
+  ) of
+      (() , stringappend_1188_0) =>
+  let stringappend_1189_0 = (string_drop stringappend_1186_0
+                               stringappend_1188_0) in
+  let (rd, stringappend_1191_0) =
+      ((case ((reg_name_matches_prefix stringappend_1189_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1190_0,stringappend_1191_0) =>
+       (stringappend_1190_0, stringappend_1191_0)
+       )) in
+  let stringappend_1192_0 = (string_drop stringappend_1189_0
+                               stringappend_1191_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1192_0)) of
+        SOME (stringappend_1193_0,stringappend_1194_0) =>
+  (stringappend_1193_0, stringappend_1194_0)
+  ) of
+      (() , stringappend_1194_0) =>
+  let stringappend_1195_0 = (string_drop stringappend_1192_0
+                               stringappend_1194_0) in
+  let (rs1, stringappend_1197_0) =
+      ((case ((reg_name_matches_prefix stringappend_1195_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1196_0,stringappend_1197_0) =>
+       (stringappend_1196_0, stringappend_1197_0)
+       )) in
+  let stringappend_1198_0 = (string_drop stringappend_1195_0
+                               stringappend_1197_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1198_0)) of
+        SOME (stringappend_1199_0,stringappend_1200_0) =>
+  (stringappend_1199_0, stringappend_1200_0)
+  ) of
+      (() , stringappend_1200_0) =>
+  let stringappend_1201_0 = (string_drop stringappend_1198_0
+                               stringappend_1200_0) in
+  let (rs2, stringappend_1203_0) =
+      ((case ((reg_name_matches_prefix stringappend_1201_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1202_0,stringappend_1203_0) =>
+       (stringappend_1202_0, stringappend_1203_0)
+       )) in
+  (case ((string_drop stringappend_1201_0 stringappend_1203_0)) of
+        "" => RTYPE (rs2,rs1,rd,op)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "l")) /\ (let stringappend_1205_0 = (string_drop stringappend_1076_0 ((string_length "l"))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_1205_0)) of
+                   SOME (stringappend_1206_0,stringappend_1207_0) =>
+                    let stringappend_1208_0 = (string_drop stringappend_1205_0 stringappend_1207_0) in
+                    if ((case ((maybe_u_matches_prefix stringappend_1208_0)) of
+                        SOME (stringappend_1209_0,stringappend_1210_0) =>
+                         let stringappend_1211_0 =
+                           (string_drop stringappend_1208_0 stringappend_1210_0) in
+                         if ((case ((maybe_aq_matches_prefix stringappend_1211_0)) of
+                             SOME (stringappend_1212_0,stringappend_1213_0) =>
+                              let stringappend_1214_0 =
+                                (string_drop stringappend_1211_0 stringappend_1213_0) in
+                              if ((case ((maybe_rl_matches_prefix stringappend_1214_0)) of
+                                  SOME (stringappend_1215_0,stringappend_1216_0) =>
+                                   let stringappend_1217_0 =
+                                     (string_drop stringappend_1214_0 stringappend_1216_0) in
+                                   if ((case ((spc_matches_prefix stringappend_1217_0)) of
+                                       SOME (stringappend_1218_0,stringappend_1219_0) =>
+                                        let stringappend_1220_0 =
+                                          (string_drop stringappend_1217_0 stringappend_1219_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_1220_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_1221_0,stringappend_1222_0) =>
+                                             let stringappend_1223_0 =
+                                               (string_drop stringappend_1220_0 stringappend_1222_0) in
+                                             if ((case ((sep_matches_prefix stringappend_1223_0)) of
+                                                 SOME (stringappend_1224_0,stringappend_1225_0) =>
+                                                  let stringappend_1226_0 =
+                                                    (string_drop stringappend_1223_0
+                                                      stringappend_1225_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_1226_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_1227_0,stringappend_1228_0) =>
+                                                       let stringappend_1229_0 =
+                                                         (string_drop stringappend_1226_0
+                                                           stringappend_1228_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_1229_0)) of
+                                                           SOME
+                                                           (stringappend_1230_0,stringappend_1231_0) =>
+                                                            let stringappend_1232_0 =
+                                                              (string_drop stringappend_1229_0
+                                                                stringappend_1231_0) in
+                                                            if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                          stringappend_1232_0
+                                                                         :  (( 12 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_1233_0,stringappend_1234_0) =>
+                                                                 (case ((string_drop
+                                                                           stringappend_1232_0
+                                                                           stringappend_1234_0)) of
+                                                                   "" => T
+                                                                 | _ => F
+                                                                 )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1205_0 = (string_drop stringappend_1076_0 ((string_length "l"))) in
+     let (size1, stringappend_1207_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_1205_0)) of
+         SOME (stringappend_1206_0,stringappend_1207_0) =>
+          (stringappend_1206_0, stringappend_1207_0)
+       )) in
+     let stringappend_1208_0 = (string_drop stringappend_1205_0 stringappend_1207_0) in
+     let (is_unsigned, stringappend_1210_0) =
+       ((case ((maybe_u_matches_prefix stringappend_1208_0)) of
+         SOME (stringappend_1209_0,stringappend_1210_0) =>
+          (stringappend_1209_0, stringappend_1210_0)
+       )) in
+     let stringappend_1211_0 = (string_drop stringappend_1208_0 stringappend_1210_0) in
+     let (aq, stringappend_1213_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_1211_0)) of
+         SOME (stringappend_1212_0,stringappend_1213_0) =>
+          (stringappend_1212_0, stringappend_1213_0)
+       )) in
+     let stringappend_1214_0 = (string_drop stringappend_1211_0 stringappend_1213_0) in
+     let (rl, stringappend_1216_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_1214_0)) of
+         SOME (stringappend_1215_0,stringappend_1216_0) =>
+          (stringappend_1215_0, stringappend_1216_0)
+       )) in
+     let stringappend_1217_0 = (string_drop stringappend_1214_0 stringappend_1216_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1217_0)) of
+        SOME (stringappend_1218_0,stringappend_1219_0) =>
+  (stringappend_1218_0, stringappend_1219_0)
+  ) of
+      (() , stringappend_1219_0) =>
+  let stringappend_1220_0 = (string_drop stringappend_1217_0
+                               stringappend_1219_0) in
+  let (rd, stringappend_1222_0) =
+      ((case ((reg_name_matches_prefix stringappend_1220_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1221_0,stringappend_1222_0) =>
+       (stringappend_1221_0, stringappend_1222_0)
+       )) in
+  let stringappend_1223_0 = (string_drop stringappend_1220_0
+                               stringappend_1222_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1223_0)) of
+        SOME (stringappend_1224_0,stringappend_1225_0) =>
+  (stringappend_1224_0, stringappend_1225_0)
+  ) of
+      (() , stringappend_1225_0) =>
+  let stringappend_1226_0 = (string_drop stringappend_1223_0
+                               stringappend_1225_0) in
+  let (rs1, stringappend_1228_0) =
+      ((case ((reg_name_matches_prefix stringappend_1226_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1227_0,stringappend_1228_0) =>
+       (stringappend_1227_0, stringappend_1228_0)
+       )) in
+  let stringappend_1229_0 = (string_drop stringappend_1226_0
+                               stringappend_1228_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1229_0)) of
+        SOME (stringappend_1230_0,stringappend_1231_0) =>
+  (stringappend_1230_0, stringappend_1231_0)
+  ) of
+      (() , stringappend_1231_0) =>
+  let stringappend_1232_0 = (string_drop stringappend_1229_0
+                               stringappend_1231_0) in
+  let (imm, stringappend_1234_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1232_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1233_0,stringappend_1234_0) =>
+       (stringappend_1233_0, stringappend_1234_0)
+       )) in
+  (case ((string_drop stringappend_1232_0 stringappend_1234_0)) of
+        "" => LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "s")) /\ (let stringappend_1236_0 = (string_drop stringappend_1076_0 ((string_length "s"))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_1236_0)) of
+                   SOME (stringappend_1237_0,stringappend_1238_0) =>
+                    let stringappend_1239_0 = (string_drop stringappend_1236_0 stringappend_1238_0) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_1239_0)) of
+                        SOME (stringappend_1240_0,stringappend_1241_0) =>
+                         let stringappend_1242_0 =
+                           (string_drop stringappend_1239_0 stringappend_1241_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_1242_0)) of
+                             SOME (stringappend_1243_0,stringappend_1244_0) =>
+                              let stringappend_1245_0 =
+                                (string_drop stringappend_1242_0 stringappend_1244_0) in
+                              if ((case ((spc_matches_prefix stringappend_1245_0)) of
+                                  SOME (stringappend_1246_0,stringappend_1247_0) =>
+                                   let stringappend_1248_0 =
+                                     (string_drop stringappend_1245_0 stringappend_1247_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_1248_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_1249_0,stringappend_1250_0) =>
+                                        let stringappend_1251_0 =
+                                          (string_drop stringappend_1248_0 stringappend_1250_0) in
+                                        if ((case ((sep_matches_prefix stringappend_1251_0)) of
+                                            SOME (stringappend_1252_0,stringappend_1253_0) =>
+                                             let stringappend_1254_0 =
+                                               (string_drop stringappend_1251_0 stringappend_1253_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_1254_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_1255_0,stringappend_1256_0) =>
+                                                  let stringappend_1257_0 =
+                                                    (string_drop stringappend_1254_0
+                                                      stringappend_1256_0) in
+                                                  if ((case ((sep_matches_prefix stringappend_1257_0)) of
+                                                      SOME (stringappend_1258_0,stringappend_1259_0) =>
+                                                       let stringappend_1260_0 =
+                                                         (string_drop stringappend_1257_0
+                                                           stringappend_1259_0) in
+                                                       if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                     stringappend_1260_0
+                                                                    :  (( 12 words$word # ii))option)) of
+                                                           SOME
+                                                           (stringappend_1261_0,stringappend_1262_0) =>
+                                                            (case ((string_drop stringappend_1260_0
+                                                                      stringappend_1262_0)) of
+                                                              "" => T
+                                                            | _ => F
+                                                            )
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1236_0 = (string_drop stringappend_1076_0 ((string_length "s"))) in
+     let (size1, stringappend_1238_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_1236_0)) of
+         SOME (stringappend_1237_0,stringappend_1238_0) =>
+          (stringappend_1237_0, stringappend_1238_0)
+       )) in
+     let stringappend_1239_0 = (string_drop stringappend_1236_0 stringappend_1238_0) in
+     let (aq, stringappend_1241_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_1239_0)) of
+         SOME (stringappend_1240_0,stringappend_1241_0) =>
+          (stringappend_1240_0, stringappend_1241_0)
+       )) in
+     let stringappend_1242_0 = (string_drop stringappend_1239_0 stringappend_1241_0) in
+     let (rl, stringappend_1244_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_1242_0)) of
+         SOME (stringappend_1243_0,stringappend_1244_0) =>
+          (stringappend_1243_0, stringappend_1244_0)
+       )) in
+     let stringappend_1245_0 = (string_drop stringappend_1242_0 stringappend_1244_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1245_0)) of
+        SOME (stringappend_1246_0,stringappend_1247_0) =>
+  (stringappend_1246_0, stringappend_1247_0)
+  ) of
+      (() , stringappend_1247_0) =>
+  let stringappend_1248_0 = (string_drop stringappend_1245_0
+                               stringappend_1247_0) in
+  let (rd, stringappend_1250_0) =
+      ((case ((reg_name_matches_prefix stringappend_1248_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1249_0,stringappend_1250_0) =>
+       (stringappend_1249_0, stringappend_1250_0)
+       )) in
+  let stringappend_1251_0 = (string_drop stringappend_1248_0
+                               stringappend_1250_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1251_0)) of
+        SOME (stringappend_1252_0,stringappend_1253_0) =>
+  (stringappend_1252_0, stringappend_1253_0)
+  ) of
+      (() , stringappend_1253_0) =>
+  let stringappend_1254_0 = (string_drop stringappend_1251_0
+                               stringappend_1253_0) in
+  let (rs1, stringappend_1256_0) =
+      ((case ((reg_name_matches_prefix stringappend_1254_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1255_0,stringappend_1256_0) =>
+       (stringappend_1255_0, stringappend_1256_0)
+       )) in
+  let stringappend_1257_0 = (string_drop stringappend_1254_0
+                               stringappend_1256_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1257_0)) of
+        SOME (stringappend_1258_0,stringappend_1259_0) =>
+  (stringappend_1258_0, stringappend_1259_0)
+  ) of
+      (() , stringappend_1259_0) =>
+  let stringappend_1260_0 = (string_drop stringappend_1257_0
+                               stringappend_1259_0) in
+  let (imm, stringappend_1262_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1260_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1261_0,stringappend_1262_0) =>
+       (stringappend_1261_0, stringappend_1262_0)
+       )) in
+  (case ((string_drop stringappend_1260_0 stringappend_1262_0)) of
+        "" => STORE (imm,rs1,rd,size1,aq,rl)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "addiw")) /\ (let stringappend_1264_0 = (string_drop stringappend_1076_0 ((string_length "addiw"))) in
+               if ((case ((spc_matches_prefix stringappend_1264_0)) of
+                   SOME (stringappend_1265_0,stringappend_1266_0) =>
+                    let stringappend_1267_0 = (string_drop stringappend_1264_0 stringappend_1266_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_1267_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_1268_0,stringappend_1269_0) =>
+                         let stringappend_1270_0 =
+                           (string_drop stringappend_1267_0 stringappend_1269_0) in
+                         if ((case ((sep_matches_prefix stringappend_1270_0)) of
+                             SOME (stringappend_1271_0,stringappend_1272_0) =>
+                              let stringappend_1273_0 =
+                                (string_drop stringappend_1270_0 stringappend_1272_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_1273_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_1274_0,stringappend_1275_0) =>
+                                   let stringappend_1276_0 =
+                                     (string_drop stringappend_1273_0 stringappend_1275_0) in
+                                   if ((case ((sep_matches_prefix stringappend_1276_0)) of
+                                       SOME (stringappend_1277_0,stringappend_1278_0) =>
+                                        let stringappend_1279_0 =
+                                          (string_drop stringappend_1276_0 stringappend_1278_0) in
+                                        if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1279_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_1280_0,stringappend_1281_0) =>
+                                             (case ((string_drop stringappend_1279_0
+                                                       stringappend_1281_0)) of
+                                               "" => T
+                                             | _ => F
+                                             )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1264_0 = (string_drop stringappend_1076_0 ((string_length "addiw"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1264_0)) of
+        SOME (stringappend_1265_0,stringappend_1266_0) =>
+  (stringappend_1265_0, stringappend_1266_0)
+  ) of
+      (() , stringappend_1266_0) =>
+  let stringappend_1267_0 = (string_drop stringappend_1264_0
+                               stringappend_1266_0) in
+  let (rd, stringappend_1269_0) =
+      ((case ((reg_name_matches_prefix stringappend_1267_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1268_0,stringappend_1269_0) =>
+       (stringappend_1268_0, stringappend_1269_0)
+       )) in
+  let stringappend_1270_0 = (string_drop stringappend_1267_0
+                               stringappend_1269_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1270_0)) of
+        SOME (stringappend_1271_0,stringappend_1272_0) =>
+  (stringappend_1271_0, stringappend_1272_0)
+  ) of
+      (() , stringappend_1272_0) =>
+  let stringappend_1273_0 = (string_drop stringappend_1270_0
+                               stringappend_1272_0) in
+  let (rs1, stringappend_1275_0) =
+      ((case ((reg_name_matches_prefix stringappend_1273_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1274_0,stringappend_1275_0) =>
+       (stringappend_1274_0, stringappend_1275_0)
+       )) in
+  let stringappend_1276_0 = (string_drop stringappend_1273_0
+                               stringappend_1275_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1276_0)) of
+        SOME (stringappend_1277_0,stringappend_1278_0) =>
+  (stringappend_1277_0, stringappend_1278_0)
+  ) of
+      (() , stringappend_1278_0) =>
+  let stringappend_1279_0 = (string_drop stringappend_1276_0
+                               stringappend_1278_0) in
+  let (imm, stringappend_1281_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1279_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1280_0,stringappend_1281_0) =>
+       (stringappend_1280_0, stringappend_1281_0)
+       )) in
+  (case ((string_drop stringappend_1279_0 stringappend_1281_0)) of
+        "" => ADDIW (imm,rs1,rd)
+  )
+  )
+  )
+  )
+   else if ((case ((shiftw_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1283_0,stringappend_1284_0) =>
+        let stringappend_1285_0 = (string_drop stringappend_1076_0 stringappend_1284_0) in
+        if ((case ((spc_matches_prefix stringappend_1285_0)) of
+            SOME (stringappend_1286_0,stringappend_1287_0) =>
+             let stringappend_1288_0 = (string_drop stringappend_1285_0 stringappend_1287_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1288_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1289_0,stringappend_1290_0) =>
+                  let stringappend_1291_0 = (string_drop stringappend_1288_0 stringappend_1290_0) in
+                  if ((case ((sep_matches_prefix stringappend_1291_0)) of
+                      SOME (stringappend_1292_0,stringappend_1293_0) =>
+                       let stringappend_1294_0 = (string_drop stringappend_1291_0 stringappend_1293_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1294_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1295_0,stringappend_1296_0) =>
+                            let stringappend_1297_0 =
+                              (string_drop stringappend_1294_0 stringappend_1296_0) in
+                            if ((case ((sep_matches_prefix stringappend_1297_0)) of
+                                SOME (stringappend_1298_0,stringappend_1299_0) =>
+                                 let stringappend_1300_0 =
+                                   (string_drop stringappend_1297_0 stringappend_1299_0) in
+                                 if ((case ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1300_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_1301_0,stringappend_1302_0) =>
+                                      (case ((string_drop stringappend_1300_0 stringappend_1302_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1284_0) =
+       ((case ((shiftw_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1283_0,stringappend_1284_0) =>
+          (stringappend_1283_0, stringappend_1284_0)
+       )) in
+     let stringappend_1285_0 = (string_drop stringappend_1076_0 stringappend_1284_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1285_0)) of
+        SOME (stringappend_1286_0,stringappend_1287_0) =>
+  (stringappend_1286_0, stringappend_1287_0)
+  ) of
+      (() , stringappend_1287_0) =>
+  let stringappend_1288_0 = (string_drop stringappend_1285_0
+                               stringappend_1287_0) in
+  let (rd, stringappend_1290_0) =
+      ((case ((reg_name_matches_prefix stringappend_1288_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1289_0,stringappend_1290_0) =>
+       (stringappend_1289_0, stringappend_1290_0)
+       )) in
+  let stringappend_1291_0 = (string_drop stringappend_1288_0
+                               stringappend_1290_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1291_0)) of
+        SOME (stringappend_1292_0,stringappend_1293_0) =>
+  (stringappend_1292_0, stringappend_1293_0)
+  ) of
+      (() , stringappend_1293_0) =>
+  let stringappend_1294_0 = (string_drop stringappend_1291_0
+                               stringappend_1293_0) in
+  let (rs1, stringappend_1296_0) =
+      ((case ((reg_name_matches_prefix stringappend_1294_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1295_0,stringappend_1296_0) =>
+       (stringappend_1295_0, stringappend_1296_0)
+       )) in
+  let stringappend_1297_0 = (string_drop stringappend_1294_0
+                               stringappend_1296_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1297_0)) of
+        SOME (stringappend_1298_0,stringappend_1299_0) =>
+  (stringappend_1298_0, stringappend_1299_0)
+  ) of
+      (() , stringappend_1299_0) =>
+  let stringappend_1300_0 = (string_drop stringappend_1297_0
+                               stringappend_1299_0) in
+  let (shamt, stringappend_1302_0) =
+      ((case ((hex_bits_5_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1300_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1301_0,stringappend_1302_0) =>
+       (stringappend_1301_0, stringappend_1302_0)
+       )) in
+  (case ((string_drop stringappend_1300_0 stringappend_1302_0)) of
+        "" => SHIFTW (shamt,rs1,rd,op)
+  )
+  )
+  )
+  )
+   else if ((case ((rtypew_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1304_0,stringappend_1305_0) =>
+        let stringappend_1306_0 = (string_drop stringappend_1076_0 stringappend_1305_0) in
+        if ((case ((spc_matches_prefix stringappend_1306_0)) of
+            SOME (stringappend_1307_0,stringappend_1308_0) =>
+             let stringappend_1309_0 = (string_drop stringappend_1306_0 stringappend_1308_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1309_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1310_0,stringappend_1311_0) =>
+                  let stringappend_1312_0 = (string_drop stringappend_1309_0 stringappend_1311_0) in
+                  if ((case ((sep_matches_prefix stringappend_1312_0)) of
+                      SOME (stringappend_1313_0,stringappend_1314_0) =>
+                       let stringappend_1315_0 = (string_drop stringappend_1312_0 stringappend_1314_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1315_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1316_0,stringappend_1317_0) =>
+                            let stringappend_1318_0 =
+                              (string_drop stringappend_1315_0 stringappend_1317_0) in
+                            if ((case ((sep_matches_prefix stringappend_1318_0)) of
+                                SOME (stringappend_1319_0,stringappend_1320_0) =>
+                                 let stringappend_1321_0 =
+                                   (string_drop stringappend_1318_0 stringappend_1320_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_1321_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_1322_0,stringappend_1323_0) =>
+                                      (case ((string_drop stringappend_1321_0 stringappend_1323_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_1305_0) =
+       ((case ((rtypew_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1304_0,stringappend_1305_0) =>
+          (stringappend_1304_0, stringappend_1305_0)
+       )) in
+     let stringappend_1306_0 = (string_drop stringappend_1076_0 stringappend_1305_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1306_0)) of
+        SOME (stringappend_1307_0,stringappend_1308_0) =>
+  (stringappend_1307_0, stringappend_1308_0)
+  ) of
+      (() , stringappend_1308_0) =>
+  let stringappend_1309_0 = (string_drop stringappend_1306_0
+                               stringappend_1308_0) in
+  let (rd, stringappend_1311_0) =
+      ((case ((reg_name_matches_prefix stringappend_1309_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1310_0,stringappend_1311_0) =>
+       (stringappend_1310_0, stringappend_1311_0)
+       )) in
+  let stringappend_1312_0 = (string_drop stringappend_1309_0
+                               stringappend_1311_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1312_0)) of
+        SOME (stringappend_1313_0,stringappend_1314_0) =>
+  (stringappend_1313_0, stringappend_1314_0)
+  ) of
+      (() , stringappend_1314_0) =>
+  let stringappend_1315_0 = (string_drop stringappend_1312_0
+                               stringappend_1314_0) in
+  let (rs1, stringappend_1317_0) =
+      ((case ((reg_name_matches_prefix stringappend_1315_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1316_0,stringappend_1317_0) =>
+       (stringappend_1316_0, stringappend_1317_0)
+       )) in
+  let stringappend_1318_0 = (string_drop stringappend_1315_0
+                               stringappend_1317_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1318_0)) of
+        SOME (stringappend_1319_0,stringappend_1320_0) =>
+  (stringappend_1319_0, stringappend_1320_0)
+  ) of
+      (() , stringappend_1320_0) =>
+  let stringappend_1321_0 = (string_drop stringappend_1318_0
+                               stringappend_1320_0) in
+  let (rs2, stringappend_1323_0) =
+      ((case ((reg_name_matches_prefix stringappend_1321_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1322_0,stringappend_1323_0) =>
+       (stringappend_1322_0, stringappend_1323_0)
+       )) in
+  (case ((string_drop stringappend_1321_0 stringappend_1323_0)) of
+        "" => RTYPEW (rs2,rs1,rd,op)
+  )
+  )
+  )
+  )
+   else if ((case ((mul_mnemonic_matches_prefix stringappend_1076_0)) of
+       SOME (stringappend_1325_0,stringappend_1326_0) =>
+        let stringappend_1327_0 = (string_drop stringappend_1076_0 stringappend_1326_0) in
+        if ((case ((spc_matches_prefix stringappend_1327_0)) of
+            SOME (stringappend_1328_0,stringappend_1329_0) =>
+             let stringappend_1330_0 = (string_drop stringappend_1327_0 stringappend_1329_0) in
+             if ((case ((reg_name_matches_prefix stringappend_1330_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_1331_0,stringappend_1332_0) =>
+                  let stringappend_1333_0 = (string_drop stringappend_1330_0 stringappend_1332_0) in
+                  if ((case ((sep_matches_prefix stringappend_1333_0)) of
+                      SOME (stringappend_1334_0,stringappend_1335_0) =>
+                       let stringappend_1336_0 = (string_drop stringappend_1333_0 stringappend_1335_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_1336_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_1337_0,stringappend_1338_0) =>
+                            let stringappend_1339_0 =
+                              (string_drop stringappend_1336_0 stringappend_1338_0) in
+                            if ((case ((sep_matches_prefix stringappend_1339_0)) of
+                                SOME (stringappend_1340_0,stringappend_1341_0) =>
+                                 let stringappend_1342_0 =
+                                   (string_drop stringappend_1339_0 stringappend_1341_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_1342_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_1343_0,stringappend_1344_0) =>
+                                      (case ((string_drop stringappend_1342_0 stringappend_1344_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let ((high, signed1, signed2), stringappend_1326_0) =
+       ((case ((mul_mnemonic_matches_prefix stringappend_1076_0)) of
+         SOME (stringappend_1325_0,stringappend_1326_0) =>
+          (stringappend_1325_0, stringappend_1326_0)
+       )) in
+     let stringappend_1327_0 = (string_drop stringappend_1076_0 stringappend_1326_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1327_0)) of
+        SOME (stringappend_1328_0,stringappend_1329_0) =>
+  (stringappend_1328_0, stringappend_1329_0)
+  ) of
+      (() , stringappend_1329_0) =>
+  let stringappend_1330_0 = (string_drop stringappend_1327_0
+                               stringappend_1329_0) in
+  let (rd, stringappend_1332_0) =
+      ((case ((reg_name_matches_prefix stringappend_1330_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1331_0,stringappend_1332_0) =>
+       (stringappend_1331_0, stringappend_1332_0)
+       )) in
+  let stringappend_1333_0 = (string_drop stringappend_1330_0
+                               stringappend_1332_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1333_0)) of
+        SOME (stringappend_1334_0,stringappend_1335_0) =>
+  (stringappend_1334_0, stringappend_1335_0)
+  ) of
+      (() , stringappend_1335_0) =>
+  let stringappend_1336_0 = (string_drop stringappend_1333_0
+                               stringappend_1335_0) in
+  let (rs1, stringappend_1338_0) =
+      ((case ((reg_name_matches_prefix stringappend_1336_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1337_0,stringappend_1338_0) =>
+       (stringappend_1337_0, stringappend_1338_0)
+       )) in
+  let stringappend_1339_0 = (string_drop stringappend_1336_0
+                               stringappend_1338_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1339_0)) of
+        SOME (stringappend_1340_0,stringappend_1341_0) =>
+  (stringappend_1340_0, stringappend_1341_0)
+  ) of
+      (() , stringappend_1341_0) =>
+  let stringappend_1342_0 = (string_drop stringappend_1339_0
+                               stringappend_1341_0) in
+  let (rs2, stringappend_1344_0) =
+      ((case ((reg_name_matches_prefix stringappend_1342_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1343_0,stringappend_1344_0) =>
+       (stringappend_1343_0, stringappend_1344_0)
+       )) in
+  (case ((string_drop stringappend_1342_0 stringappend_1344_0)) of
+        "" => MUL (rs2,rs1,rd,high,signed1,signed2)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "div")) /\ (let stringappend_1346_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_1346_0)) of
+                   SOME (stringappend_1347_0,stringappend_1348_0) =>
+                    let stringappend_1349_0 = (string_drop stringappend_1346_0 stringappend_1348_0) in
+                    if ((case ((spc_matches_prefix stringappend_1349_0)) of
+                        SOME (stringappend_1350_0,stringappend_1351_0) =>
+                         let stringappend_1352_0 =
+                           (string_drop stringappend_1349_0 stringappend_1351_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_1352_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_1353_0,stringappend_1354_0) =>
+                              let stringappend_1355_0 =
+                                (string_drop stringappend_1352_0 stringappend_1354_0) in
+                              if ((case ((sep_matches_prefix stringappend_1355_0)) of
+                                  SOME (stringappend_1356_0,stringappend_1357_0) =>
+                                   let stringappend_1358_0 =
+                                     (string_drop stringappend_1355_0 stringappend_1357_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_1358_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_1359_0,stringappend_1360_0) =>
+                                        let stringappend_1361_0 =
+                                          (string_drop stringappend_1358_0 stringappend_1360_0) in
+                                        if ((case ((sep_matches_prefix stringappend_1361_0)) of
+                                            SOME (stringappend_1362_0,stringappend_1363_0) =>
+                                             let stringappend_1364_0 =
+                                               (string_drop stringappend_1361_0 stringappend_1363_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_1364_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_1365_0,stringappend_1366_0) =>
+                                                  (case ((string_drop stringappend_1364_0
+                                                            stringappend_1366_0)) of
+                                                    "" => T
+                                                  | _ => F
+                                                  )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1346_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in
+     let (s, stringappend_1348_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_1346_0)) of
+         SOME (stringappend_1347_0,stringappend_1348_0) =>
+          (stringappend_1347_0, stringappend_1348_0)
+       )) in
+     let stringappend_1349_0 = (string_drop stringappend_1346_0 stringappend_1348_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1349_0)) of
+        SOME (stringappend_1350_0,stringappend_1351_0) =>
+  (stringappend_1350_0, stringappend_1351_0)
+  ) of
+      (() , stringappend_1351_0) =>
+  let stringappend_1352_0 = (string_drop stringappend_1349_0
+                               stringappend_1351_0) in
+  let (rd, stringappend_1354_0) =
+      ((case ((reg_name_matches_prefix stringappend_1352_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1353_0,stringappend_1354_0) =>
+       (stringappend_1353_0, stringappend_1354_0)
+       )) in
+  let stringappend_1355_0 = (string_drop stringappend_1352_0
+                               stringappend_1354_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1355_0)) of
+        SOME (stringappend_1356_0,stringappend_1357_0) =>
+  (stringappend_1356_0, stringappend_1357_0)
+  ) of
+      (() , stringappend_1357_0) =>
+  let stringappend_1358_0 = (string_drop stringappend_1355_0
+                               stringappend_1357_0) in
+  let (rs1, stringappend_1360_0) =
+      ((case ((reg_name_matches_prefix stringappend_1358_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1359_0,stringappend_1360_0) =>
+       (stringappend_1359_0, stringappend_1360_0)
+       )) in
+  let stringappend_1361_0 = (string_drop stringappend_1358_0
+                               stringappend_1360_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1361_0)) of
+        SOME (stringappend_1362_0,stringappend_1363_0) =>
+  (stringappend_1362_0, stringappend_1363_0)
+  ) of
+      (() , stringappend_1363_0) =>
+  let stringappend_1364_0 = (string_drop stringappend_1361_0
+                               stringappend_1363_0) in
+  let (rs2, stringappend_1366_0) =
+      ((case ((reg_name_matches_prefix stringappend_1364_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1365_0,stringappend_1366_0) =>
+       (stringappend_1365_0, stringappend_1366_0)
+       )) in
+  (case ((string_drop stringappend_1364_0 stringappend_1366_0)) of
+        "" => DIV0 (rs2,rs1,rd,s)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "rem")) /\ (let stringappend_1368_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_1368_0)) of
+                   SOME (stringappend_1369_0,stringappend_1370_0) =>
+                    let stringappend_1371_0 = (string_drop stringappend_1368_0 stringappend_1370_0) in
+                    if ((case ((spc_matches_prefix stringappend_1371_0)) of
+                        SOME (stringappend_1372_0,stringappend_1373_0) =>
+                         let stringappend_1374_0 =
+                           (string_drop stringappend_1371_0 stringappend_1373_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_1374_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_1375_0,stringappend_1376_0) =>
+                              let stringappend_1377_0 =
+                                (string_drop stringappend_1374_0 stringappend_1376_0) in
+                              if ((case ((sep_matches_prefix stringappend_1377_0)) of
+                                  SOME (stringappend_1378_0,stringappend_1379_0) =>
+                                   let stringappend_1380_0 =
+                                     (string_drop stringappend_1377_0 stringappend_1379_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_1380_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_1381_0,stringappend_1382_0) =>
+                                        let stringappend_1383_0 =
+                                          (string_drop stringappend_1380_0 stringappend_1382_0) in
+                                        if ((case ((sep_matches_prefix stringappend_1383_0)) of
+                                            SOME (stringappend_1384_0,stringappend_1385_0) =>
+                                             let stringappend_1386_0 =
+                                               (string_drop stringappend_1383_0 stringappend_1385_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_1386_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_1387_0,stringappend_1388_0) =>
+                                                  (case ((string_drop stringappend_1386_0
+                                                            stringappend_1388_0)) of
+                                                    "" => T
+                                                  | _ => F
+                                                  )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1368_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in
+     let (s, stringappend_1370_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_1368_0)) of
+         SOME (stringappend_1369_0,stringappend_1370_0) =>
+          (stringappend_1369_0, stringappend_1370_0)
+       )) in
+     let stringappend_1371_0 = (string_drop stringappend_1368_0 stringappend_1370_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1371_0)) of
+        SOME (stringappend_1372_0,stringappend_1373_0) =>
+  (stringappend_1372_0, stringappend_1373_0)
+  ) of
+      (() , stringappend_1373_0) =>
+  let stringappend_1374_0 = (string_drop stringappend_1371_0
+                               stringappend_1373_0) in
+  let (rd, stringappend_1376_0) =
+      ((case ((reg_name_matches_prefix stringappend_1374_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1375_0,stringappend_1376_0) =>
+       (stringappend_1375_0, stringappend_1376_0)
+       )) in
+  let stringappend_1377_0 = (string_drop stringappend_1374_0
+                               stringappend_1376_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1377_0)) of
+        SOME (stringappend_1378_0,stringappend_1379_0) =>
+  (stringappend_1378_0, stringappend_1379_0)
+  ) of
+      (() , stringappend_1379_0) =>
+  let stringappend_1380_0 = (string_drop stringappend_1377_0
+                               stringappend_1379_0) in
+  let (rs1, stringappend_1382_0) =
+      ((case ((reg_name_matches_prefix stringappend_1380_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1381_0,stringappend_1382_0) =>
+       (stringappend_1381_0, stringappend_1382_0)
+       )) in
+  let stringappend_1383_0 = (string_drop stringappend_1380_0
+                               stringappend_1382_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1383_0)) of
+        SOME (stringappend_1384_0,stringappend_1385_0) =>
+  (stringappend_1384_0, stringappend_1385_0)
+  ) of
+      (() , stringappend_1385_0) =>
+  let stringappend_1386_0 = (string_drop stringappend_1383_0
+                               stringappend_1385_0) in
+  let (rs2, stringappend_1388_0) =
+      ((case ((reg_name_matches_prefix stringappend_1386_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1387_0,stringappend_1388_0) =>
+       (stringappend_1387_0, stringappend_1388_0)
+       )) in
+  (case ((string_drop stringappend_1386_0 stringappend_1388_0)) of
+        "" => REM (rs2,rs1,rd,s)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "mulw")) /\ (let stringappend_1390_0 = (string_drop stringappend_1076_0 ((string_length "mulw"))) in
+               if ((case ((spc_matches_prefix stringappend_1390_0)) of
+                   SOME (stringappend_1391_0,stringappend_1392_0) =>
+                    let stringappend_1393_0 = (string_drop stringappend_1390_0 stringappend_1392_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_1393_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_1394_0,stringappend_1395_0) =>
+                         let stringappend_1396_0 =
+                           (string_drop stringappend_1393_0 stringappend_1395_0) in
+                         if ((case ((sep_matches_prefix stringappend_1396_0)) of
+                             SOME (stringappend_1397_0,stringappend_1398_0) =>
+                              let stringappend_1399_0 =
+                                (string_drop stringappend_1396_0 stringappend_1398_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_1399_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_1400_0,stringappend_1401_0) =>
+                                   let stringappend_1402_0 =
+                                     (string_drop stringappend_1399_0 stringappend_1401_0) in
+                                   if ((case ((sep_matches_prefix stringappend_1402_0)) of
+                                       SOME (stringappend_1403_0,stringappend_1404_0) =>
+                                        let stringappend_1405_0 =
+                                          (string_drop stringappend_1402_0 stringappend_1404_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_1405_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_1406_0,stringappend_1407_0) =>
+                                             (case ((string_drop stringappend_1405_0
+                                                       stringappend_1407_0)) of
+                                               "" => T
+                                             | _ => F
+                                             )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1390_0 = (string_drop stringappend_1076_0 ((string_length "mulw"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1390_0)) of
+        SOME (stringappend_1391_0,stringappend_1392_0) =>
+  (stringappend_1391_0, stringappend_1392_0)
+  ) of
+      (() , stringappend_1392_0) =>
+  let stringappend_1393_0 = (string_drop stringappend_1390_0
+                               stringappend_1392_0) in
+  let (rd, stringappend_1395_0) =
+      ((case ((reg_name_matches_prefix stringappend_1393_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1394_0,stringappend_1395_0) =>
+       (stringappend_1394_0, stringappend_1395_0)
+       )) in
+  let stringappend_1396_0 = (string_drop stringappend_1393_0
+                               stringappend_1395_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1396_0)) of
+        SOME (stringappend_1397_0,stringappend_1398_0) =>
+  (stringappend_1397_0, stringappend_1398_0)
+  ) of
+      (() , stringappend_1398_0) =>
+  let stringappend_1399_0 = (string_drop stringappend_1396_0
+                               stringappend_1398_0) in
+  let (rs1, stringappend_1401_0) =
+      ((case ((reg_name_matches_prefix stringappend_1399_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1400_0,stringappend_1401_0) =>
+       (stringappend_1400_0, stringappend_1401_0)
+       )) in
+  let stringappend_1402_0 = (string_drop stringappend_1399_0
+                               stringappend_1401_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1402_0)) of
+        SOME (stringappend_1403_0,stringappend_1404_0) =>
+  (stringappend_1403_0, stringappend_1404_0)
+  ) of
+      (() , stringappend_1404_0) =>
+  let stringappend_1405_0 = (string_drop stringappend_1402_0
+                               stringappend_1404_0) in
+  let (rs2, stringappend_1407_0) =
+      ((case ((reg_name_matches_prefix stringappend_1405_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1406_0,stringappend_1407_0) =>
+       (stringappend_1406_0, stringappend_1407_0)
+       )) in
+  (case ((string_drop stringappend_1405_0 stringappend_1407_0)) of
+        "" => MULW (rs2,rs1,rd)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "div")) /\ (let stringappend_1409_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_1409_0)) of
+                   SOME (stringappend_1410_0,stringappend_1411_0) =>
+                    let stringappend_1412_0 = (string_drop stringappend_1409_0 stringappend_1411_0) in
+                    if (((((string_startswith stringappend_1412_0 "w")) /\ (let stringappend_1413_0 =
+                             (string_drop stringappend_1412_0 ((string_length "w"))) in
+                           if ((case ((spc_matches_prefix stringappend_1413_0)) of
+                               SOME (stringappend_1414_0,stringappend_1415_0) =>
+                                let stringappend_1416_0 =
+                                  (string_drop stringappend_1413_0 stringappend_1415_0) in
+                                if ((case ((reg_name_matches_prefix stringappend_1416_0
+                                             :  (( 5 words$word # ii))option)) of
+                                    SOME (stringappend_1417_0,stringappend_1418_0) =>
+                                     let stringappend_1419_0 =
+                                       (string_drop stringappend_1416_0 stringappend_1418_0) in
+                                     if ((case ((sep_matches_prefix stringappend_1419_0)) of
+                                         SOME (stringappend_1420_0,stringappend_1421_0) =>
+                                          let stringappend_1422_0 =
+                                            (string_drop stringappend_1419_0 stringappend_1421_0) in
+                                          if ((case ((reg_name_matches_prefix stringappend_1422_0
+                                                       :  (( 5 words$word # ii))option)) of
+                                              SOME (stringappend_1423_0,stringappend_1424_0) =>
+                                               let stringappend_1425_0 =
+                                                 (string_drop stringappend_1422_0 stringappend_1424_0) in
+                                               if ((case ((sep_matches_prefix stringappend_1425_0)) of
+                                                   SOME (stringappend_1426_0,stringappend_1427_0) =>
+                                                    let stringappend_1428_0 =
+                                                      (string_drop stringappend_1425_0
+                                                        stringappend_1427_0) in
+                                                    if ((case ((reg_name_matches_prefix
+                                                                  stringappend_1428_0
+                                                                 :  (( 5 words$word # ii))option)) of
+                                                        SOME
+                                                        (stringappend_1429_0,stringappend_1430_0) =>
+                                                         (case ((string_drop stringappend_1428_0
+                                                                   stringappend_1430_0)) of
+                                                           "" => T
+                                                         | _ => F
+                                                         )
+                                                      | NONE => F
+                                                      )) then
+                                                      T
+                                                    else F
+                                                 | NONE => F
+                                                 )) then
+                                                 T
+                                               else F
+                                            | NONE => F
+                                            )) then
+                                            T
+                                          else F
+                                       | NONE => F
+                                       )) then
+                                       T
+                                     else F
+                                  | NONE => F
+                                  )) then
+                                  T
+                                else F
+                             | NONE => F
+                             )) then
+                             T
+                           else F)))) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1409_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in
+     let (s, stringappend_1411_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_1409_0)) of
+         SOME (stringappend_1410_0,stringappend_1411_0) =>
+          (stringappend_1410_0, stringappend_1411_0)
+       )) in
+     let stringappend_1412_0 = (string_drop stringappend_1409_0 stringappend_1411_0) in
+     let stringappend_1413_0 = (string_drop stringappend_1412_0 ((string_length "w"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1413_0)) of
+        SOME (stringappend_1414_0,stringappend_1415_0) =>
+  (stringappend_1414_0, stringappend_1415_0)
+  ) of
+      (() , stringappend_1415_0) =>
+  let stringappend_1416_0 = (string_drop stringappend_1413_0
+                               stringappend_1415_0) in
+  let (rd, stringappend_1418_0) =
+      ((case ((reg_name_matches_prefix stringappend_1416_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1417_0,stringappend_1418_0) =>
+       (stringappend_1417_0, stringappend_1418_0)
+       )) in
+  let stringappend_1419_0 = (string_drop stringappend_1416_0
+                               stringappend_1418_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1419_0)) of
+        SOME (stringappend_1420_0,stringappend_1421_0) =>
+  (stringappend_1420_0, stringappend_1421_0)
+  ) of
+      (() , stringappend_1421_0) =>
+  let stringappend_1422_0 = (string_drop stringappend_1419_0
+                               stringappend_1421_0) in
+  let (rs1, stringappend_1424_0) =
+      ((case ((reg_name_matches_prefix stringappend_1422_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1423_0,stringappend_1424_0) =>
+       (stringappend_1423_0, stringappend_1424_0)
+       )) in
+  let stringappend_1425_0 = (string_drop stringappend_1422_0
+                               stringappend_1424_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1425_0)) of
+        SOME (stringappend_1426_0,stringappend_1427_0) =>
+  (stringappend_1426_0, stringappend_1427_0)
+  ) of
+      (() , stringappend_1427_0) =>
+  let stringappend_1428_0 = (string_drop stringappend_1425_0
+                               stringappend_1427_0) in
+  let (rs2, stringappend_1430_0) =
+      ((case ((reg_name_matches_prefix stringappend_1428_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1429_0,stringappend_1430_0) =>
+       (stringappend_1429_0, stringappend_1430_0)
+       )) in
+  (case ((string_drop stringappend_1428_0 stringappend_1430_0)) of
+        "" => DIVW (rs2,rs1,rd,s)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "rem")) /\ (let stringappend_1432_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_1432_0)) of
+                   SOME (stringappend_1433_0,stringappend_1434_0) =>
+                    let stringappend_1435_0 = (string_drop stringappend_1432_0 stringappend_1434_0) in
+                    if (((((string_startswith stringappend_1435_0 "w")) /\ (let stringappend_1436_0 =
+                             (string_drop stringappend_1435_0 ((string_length "w"))) in
+                           if ((case ((spc_matches_prefix stringappend_1436_0)) of
+                               SOME (stringappend_1437_0,stringappend_1438_0) =>
+                                let stringappend_1439_0 =
+                                  (string_drop stringappend_1436_0 stringappend_1438_0) in
+                                if ((case ((reg_name_matches_prefix stringappend_1439_0
+                                             :  (( 5 words$word # ii))option)) of
+                                    SOME (stringappend_1440_0,stringappend_1441_0) =>
+                                     let stringappend_1442_0 =
+                                       (string_drop stringappend_1439_0 stringappend_1441_0) in
+                                     if ((case ((sep_matches_prefix stringappend_1442_0)) of
+                                         SOME (stringappend_1443_0,stringappend_1444_0) =>
+                                          let stringappend_1445_0 =
+                                            (string_drop stringappend_1442_0 stringappend_1444_0) in
+                                          if ((case ((reg_name_matches_prefix stringappend_1445_0
+                                                       :  (( 5 words$word # ii))option)) of
+                                              SOME (stringappend_1446_0,stringappend_1447_0) =>
+                                               let stringappend_1448_0 =
+                                                 (string_drop stringappend_1445_0 stringappend_1447_0) in
+                                               if ((case ((sep_matches_prefix stringappend_1448_0)) of
+                                                   SOME (stringappend_1449_0,stringappend_1450_0) =>
+                                                    let stringappend_1451_0 =
+                                                      (string_drop stringappend_1448_0
+                                                        stringappend_1450_0) in
+                                                    if ((case ((reg_name_matches_prefix
+                                                                  stringappend_1451_0
+                                                                 :  (( 5 words$word # ii))option)) of
+                                                        SOME
+                                                        (stringappend_1452_0,stringappend_1453_0) =>
+                                                         (case ((string_drop stringappend_1451_0
+                                                                   stringappend_1453_0)) of
+                                                           "" => T
+                                                         | _ => F
+                                                         )
+                                                      | NONE => F
+                                                      )) then
+                                                      T
+                                                    else F
+                                                 | NONE => F
+                                                 )) then
+                                                 T
+                                               else F
+                                            | NONE => F
+                                            )) then
+                                            T
+                                          else F
+                                       | NONE => F
+                                       )) then
+                                       T
+                                     else F
+                                  | NONE => F
+                                  )) then
+                                  T
+                                else F
+                             | NONE => F
+                             )) then
+                             T
+                           else F)))) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1432_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in
+     let (s, stringappend_1434_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_1432_0)) of
+         SOME (stringappend_1433_0,stringappend_1434_0) =>
+          (stringappend_1433_0, stringappend_1434_0)
+       )) in
+     let stringappend_1435_0 = (string_drop stringappend_1432_0 stringappend_1434_0) in
+     let stringappend_1436_0 = (string_drop stringappend_1435_0 ((string_length "w"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1436_0)) of
+        SOME (stringappend_1437_0,stringappend_1438_0) =>
+  (stringappend_1437_0, stringappend_1438_0)
+  ) of
+      (() , stringappend_1438_0) =>
+  let stringappend_1439_0 = (string_drop stringappend_1436_0
+                               stringappend_1438_0) in
+  let (rd, stringappend_1441_0) =
+      ((case ((reg_name_matches_prefix stringappend_1439_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1440_0,stringappend_1441_0) =>
+       (stringappend_1440_0, stringappend_1441_0)
+       )) in
+  let stringappend_1442_0 = (string_drop stringappend_1439_0
+                               stringappend_1441_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1442_0)) of
+        SOME (stringappend_1443_0,stringappend_1444_0) =>
+  (stringappend_1443_0, stringappend_1444_0)
+  ) of
+      (() , stringappend_1444_0) =>
+  let stringappend_1445_0 = (string_drop stringappend_1442_0
+                               stringappend_1444_0) in
+  let (rs1, stringappend_1447_0) =
+      ((case ((reg_name_matches_prefix stringappend_1445_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1446_0,stringappend_1447_0) =>
+       (stringappend_1446_0, stringappend_1447_0)
+       )) in
+  let stringappend_1448_0 = (string_drop stringappend_1445_0
+                               stringappend_1447_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1448_0)) of
+        SOME (stringappend_1449_0,stringappend_1450_0) =>
+  (stringappend_1449_0, stringappend_1450_0)
+  ) of
+      (() , stringappend_1450_0) =>
+  let stringappend_1451_0 = (string_drop stringappend_1448_0
+                               stringappend_1450_0) in
+  let (rs2, stringappend_1453_0) =
+      ((case ((reg_name_matches_prefix stringappend_1451_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1452_0,stringappend_1453_0) =>
+       (stringappend_1452_0, stringappend_1453_0)
+       )) in
+  (case ((string_drop stringappend_1451_0 stringappend_1453_0)) of
+        "" => REMW (rs2,rs1,rd,s)
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_1076_0 "fence")) /\ (let stringappend_1455_0 = (string_drop stringappend_1076_0 ((string_length "fence"))) in
+               if ((case ((spc_matches_prefix stringappend_1455_0)) of
+                   SOME (stringappend_1456_0,stringappend_1457_0) =>
+                    let stringappend_1458_0 = (string_drop stringappend_1455_0 stringappend_1457_0) in
+                    if ((case ((fence_bits_matches_prefix stringappend_1458_0
+                                 :  (( 4 words$word # ii))option)) of
+                        SOME (stringappend_1459_0,stringappend_1460_0) =>
+                         let stringappend_1461_0 =
+                           (string_drop stringappend_1458_0 stringappend_1460_0) in
+                         if ((case ((sep_matches_prefix stringappend_1461_0)) of
+                             SOME (stringappend_1462_0,stringappend_1463_0) =>
+                              let stringappend_1464_0 =
+                                (string_drop stringappend_1461_0 stringappend_1463_0) in
+                              if ((case ((fence_bits_matches_prefix stringappend_1464_0
+                                           :  (( 4 words$word # ii))option)) of
+                                  SOME (stringappend_1465_0,stringappend_1466_0) =>
+                                   (case ((string_drop stringappend_1464_0 stringappend_1466_0)) of
+                                     "" => T
+                                   | _ => F
+                                   )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_1455_0 = (string_drop stringappend_1076_0 ((string_length "fence"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1455_0)) of
+        SOME (stringappend_1456_0,stringappend_1457_0) =>
+  (stringappend_1456_0, stringappend_1457_0)
+  ) of
+      (() , stringappend_1457_0) =>
+  let stringappend_1458_0 = (string_drop stringappend_1455_0
+                               stringappend_1457_0) in
+  let (pred, stringappend_1460_0) =
+      ((case ((fence_bits_matches_prefix stringappend_1458_0 : (( 4 words$word # ii)) option)) of
+             SOME (stringappend_1459_0,stringappend_1460_0) =>
+       (stringappend_1459_0, stringappend_1460_0)
+       )) in
+  let stringappend_1461_0 = (string_drop stringappend_1458_0
+                               stringappend_1460_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1461_0)) of
+        SOME (stringappend_1462_0,stringappend_1463_0) =>
+  (stringappend_1462_0, stringappend_1463_0)
+  ) of
+      (() , stringappend_1463_0) =>
+  let stringappend_1464_0 = (string_drop stringappend_1461_0
+                               stringappend_1463_0) in
+  let (succ, stringappend_1466_0) =
+      ((case ((fence_bits_matches_prefix stringappend_1464_0 : (( 4 words$word # ii)) option)) of
+             SOME (stringappend_1465_0,stringappend_1466_0) =>
+       (stringappend_1465_0, stringappend_1466_0)
+       )) in
+  (case ((string_drop stringappend_1464_0 stringappend_1466_0)) of
+        "" => FENCE (pred,succ)
+  )
+  )
+  )
+   else
+     (case stringappend_1076_0 of
+       "fence.i" => FENCEI () 
+     | "ecall" => ECALL () 
+     | "mret" => MRET () 
+     | "sret" => SRET () 
+     | "ebreak" => EBREAK () 
+     | "wfi" => WFI () 
+     | stringappend_1076_0 =>
+        if (((((string_startswith stringappend_1076_0 "sfence.vma")) /\ (let stringappend_1468_0 =
+                 (string_drop stringappend_1076_0 ((string_length "sfence.vma"))) in
+               if ((case ((spc_matches_prefix stringappend_1468_0)) of
+                   SOME (stringappend_1469_0,stringappend_1470_0) =>
+                    let stringappend_1471_0 = (string_drop stringappend_1468_0 stringappend_1470_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_1471_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_1472_0,stringappend_1473_0) =>
+                         let stringappend_1474_0 =
+                           (string_drop stringappend_1471_0 stringappend_1473_0) in
+                         if ((case ((sep_matches_prefix stringappend_1474_0)) of
+                             SOME (stringappend_1475_0,stringappend_1476_0) =>
+                              let stringappend_1477_0 =
+                                (string_drop stringappend_1474_0 stringappend_1476_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_1477_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_1478_0,stringappend_1479_0) =>
+                                   (case ((string_drop stringappend_1477_0 stringappend_1479_0)) of
+                                     "" => T
+                                   | _ => F
+                                   )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+          let stringappend_1468_0 = (string_drop stringappend_1076_0 ((string_length "sfence.vma"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1468_0)) of
+        SOME (stringappend_1469_0,stringappend_1470_0) =>
+  (stringappend_1469_0, stringappend_1470_0)
+  ) of
+      (() , stringappend_1470_0) =>
+  let stringappend_1471_0 = (string_drop stringappend_1468_0
+                               stringappend_1470_0) in
+  let (rs1, stringappend_1473_0) =
+      ((case ((reg_name_matches_prefix stringappend_1471_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1472_0,stringappend_1473_0) =>
+       (stringappend_1472_0, stringappend_1473_0)
+       )) in
+  let stringappend_1474_0 = (string_drop stringappend_1471_0
+                               stringappend_1473_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1474_0)) of
+        SOME (stringappend_1475_0,stringappend_1476_0) =>
+  (stringappend_1475_0, stringappend_1476_0)
+  ) of
+      (() , stringappend_1476_0) =>
+  let stringappend_1477_0 = (string_drop stringappend_1474_0
+                               stringappend_1476_0) in
+  let (rs2, stringappend_1479_0) =
+      ((case ((reg_name_matches_prefix stringappend_1477_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1478_0,stringappend_1479_0) =>
+       (stringappend_1478_0, stringappend_1479_0)
+       )) in
+  (case ((string_drop stringappend_1477_0 stringappend_1479_0)) of
+        "" => SFENCE_VMA (rs1,rs2)
+  )
+  )
+  )
+        else if (((((string_startswith stringappend_1076_0 "lr.")) /\ (let stringappend_1481_0 =
+                      (string_drop stringappend_1076_0 ((string_length "lr."))) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_1481_0)) of
+                        SOME (stringappend_1482_0,stringappend_1483_0) =>
+                         let stringappend_1484_0 =
+                           (string_drop stringappend_1481_0 stringappend_1483_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_1484_0)) of
+                             SOME (stringappend_1485_0,stringappend_1486_0) =>
+                              let stringappend_1487_0 =
+                                (string_drop stringappend_1484_0 stringappend_1486_0) in
+                              if ((case ((size_mnemonic_matches_prefix stringappend_1487_0)) of
+                                  SOME (stringappend_1488_0,stringappend_1489_0) =>
+                                   let stringappend_1490_0 =
+                                     (string_drop stringappend_1487_0 stringappend_1489_0) in
+                                   if ((case ((spc_matches_prefix stringappend_1490_0)) of
+                                       SOME (stringappend_1491_0,stringappend_1492_0) =>
+                                        let stringappend_1493_0 =
+                                          (string_drop stringappend_1490_0 stringappend_1492_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_1493_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_1494_0,stringappend_1495_0) =>
+                                             let stringappend_1496_0 =
+                                               (string_drop stringappend_1493_0 stringappend_1495_0) in
+                                             if ((case ((sep_matches_prefix stringappend_1496_0)) of
+                                                 SOME (stringappend_1497_0,stringappend_1498_0) =>
+                                                  let stringappend_1499_0 =
+                                                    (string_drop stringappend_1496_0
+                                                      stringappend_1498_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_1499_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_1500_0,stringappend_1501_0) =>
+                                                       (case ((string_drop stringappend_1499_0
+                                                                 stringappend_1501_0)) of
+                                                         "" => T
+                                                       | _ => F
+                                                       )
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+          let stringappend_1481_0 = (string_drop stringappend_1076_0 ((string_length "lr."))) in
+          let (aq, stringappend_1483_0) =
+            ((case ((maybe_aq_matches_prefix stringappend_1481_0)) of
+              SOME (stringappend_1482_0,stringappend_1483_0) =>
+               (stringappend_1482_0, stringappend_1483_0)
+            )) in
+          let stringappend_1484_0 = (string_drop stringappend_1481_0 stringappend_1483_0) in
+          let (rl, stringappend_1486_0) =
+            ((case ((maybe_rl_matches_prefix stringappend_1484_0)) of
+              SOME (stringappend_1485_0,stringappend_1486_0) =>
+               (stringappend_1485_0, stringappend_1486_0)
+            )) in
+          let stringappend_1487_0 = (string_drop stringappend_1484_0 stringappend_1486_0) in
+          let (size1, stringappend_1489_0) =
+            ((case ((size_mnemonic_matches_prefix stringappend_1487_0)) of
+              SOME (stringappend_1488_0,stringappend_1489_0) =>
+               (stringappend_1488_0, stringappend_1489_0)
+            )) in
+          let stringappend_1490_0 = (string_drop stringappend_1487_0 stringappend_1489_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1490_0)) of
+        SOME (stringappend_1491_0,stringappend_1492_0) =>
+  (stringappend_1491_0, stringappend_1492_0)
+  ) of
+      (() , stringappend_1492_0) =>
+  let stringappend_1493_0 = (string_drop stringappend_1490_0
+                               stringappend_1492_0) in
+  let (rd, stringappend_1495_0) =
+      ((case ((reg_name_matches_prefix stringappend_1493_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1494_0,stringappend_1495_0) =>
+       (stringappend_1494_0, stringappend_1495_0)
+       )) in
+  let stringappend_1496_0 = (string_drop stringappend_1493_0
+                               stringappend_1495_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1496_0)) of
+        SOME (stringappend_1497_0,stringappend_1498_0) =>
+  (stringappend_1497_0, stringappend_1498_0)
+  ) of
+      (() , stringappend_1498_0) =>
+  let stringappend_1499_0 = (string_drop stringappend_1496_0
+                               stringappend_1498_0) in
+  let (rs1, stringappend_1501_0) =
+      ((case ((reg_name_matches_prefix stringappend_1499_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1500_0,stringappend_1501_0) =>
+       (stringappend_1500_0, stringappend_1501_0)
+       )) in
+  (case ((string_drop stringappend_1499_0 stringappend_1501_0)) of
+        "" => LOADRES (aq,rl,rs1,size1,rd)
+  )
+  )
+  )
+        else if (((((string_startswith stringappend_1076_0 "sc.")) /\ (let stringappend_1503_0 =
+                      (string_drop stringappend_1076_0 ((string_length "sc."))) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_1503_0)) of
+                        SOME (stringappend_1504_0,stringappend_1505_0) =>
+                         let stringappend_1506_0 =
+                           (string_drop stringappend_1503_0 stringappend_1505_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_1506_0)) of
+                             SOME (stringappend_1507_0,stringappend_1508_0) =>
+                              let stringappend_1509_0 =
+                                (string_drop stringappend_1506_0 stringappend_1508_0) in
+                              if ((case ((size_mnemonic_matches_prefix stringappend_1509_0)) of
+                                  SOME (stringappend_1510_0,stringappend_1511_0) =>
+                                   let stringappend_1512_0 =
+                                     (string_drop stringappend_1509_0 stringappend_1511_0) in
+                                   if ((case ((spc_matches_prefix stringappend_1512_0)) of
+                                       SOME (stringappend_1513_0,stringappend_1514_0) =>
+                                        let stringappend_1515_0 =
+                                          (string_drop stringappend_1512_0 stringappend_1514_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_1515_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_1516_0,stringappend_1517_0) =>
+                                             let stringappend_1518_0 =
+                                               (string_drop stringappend_1515_0 stringappend_1517_0) in
+                                             if ((case ((sep_matches_prefix stringappend_1518_0)) of
+                                                 SOME (stringappend_1519_0,stringappend_1520_0) =>
+                                                  let stringappend_1521_0 =
+                                                    (string_drop stringappend_1518_0
+                                                      stringappend_1520_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_1521_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_1522_0,stringappend_1523_0) =>
+                                                       let stringappend_1524_0 =
+                                                         (string_drop stringappend_1521_0
+                                                           stringappend_1523_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_1524_0)) of
+                                                           SOME
+                                                           (stringappend_1525_0,stringappend_1526_0) =>
+                                                            let stringappend_1527_0 =
+                                                              (string_drop stringappend_1524_0
+                                                                stringappend_1526_0) in
+                                                            if ((case ((reg_name_matches_prefix
+                                                                          stringappend_1527_0
+                                                                         :  (( 5 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_1528_0,stringappend_1529_0) =>
+                                                                 (case ((string_drop
+                                                                           stringappend_1527_0
+                                                                           stringappend_1529_0)) of
+                                                                   "" => T
+                                                                 | _ => F
+                                                                 )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+          let stringappend_1503_0 = (string_drop stringappend_1076_0 ((string_length "sc."))) in
+          let (aq, stringappend_1505_0) =
+            ((case ((maybe_aq_matches_prefix stringappend_1503_0)) of
+              SOME (stringappend_1504_0,stringappend_1505_0) =>
+               (stringappend_1504_0, stringappend_1505_0)
+            )) in
+          let stringappend_1506_0 = (string_drop stringappend_1503_0 stringappend_1505_0) in
+          let (rl, stringappend_1508_0) =
+            ((case ((maybe_rl_matches_prefix stringappend_1506_0)) of
+              SOME (stringappend_1507_0,stringappend_1508_0) =>
+               (stringappend_1507_0, stringappend_1508_0)
+            )) in
+          let stringappend_1509_0 = (string_drop stringappend_1506_0 stringappend_1508_0) in
+          let (size1, stringappend_1511_0) =
+            ((case ((size_mnemonic_matches_prefix stringappend_1509_0)) of
+              SOME (stringappend_1510_0,stringappend_1511_0) =>
+               (stringappend_1510_0, stringappend_1511_0)
+            )) in
+          let stringappend_1512_0 = (string_drop stringappend_1509_0 stringappend_1511_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1512_0)) of
+        SOME (stringappend_1513_0,stringappend_1514_0) =>
+  (stringappend_1513_0, stringappend_1514_0)
+  ) of
+      (() , stringappend_1514_0) =>
+  let stringappend_1515_0 = (string_drop stringappend_1512_0
+                               stringappend_1514_0) in
+  let (rd, stringappend_1517_0) =
+      ((case ((reg_name_matches_prefix stringappend_1515_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1516_0,stringappend_1517_0) =>
+       (stringappend_1516_0, stringappend_1517_0)
+       )) in
+  let stringappend_1518_0 = (string_drop stringappend_1515_0
+                               stringappend_1517_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1518_0)) of
+        SOME (stringappend_1519_0,stringappend_1520_0) =>
+  (stringappend_1519_0, stringappend_1520_0)
+  ) of
+      (() , stringappend_1520_0) =>
+  let stringappend_1521_0 = (string_drop stringappend_1518_0
+                               stringappend_1520_0) in
+  let (rs1, stringappend_1523_0) =
+      ((case ((reg_name_matches_prefix stringappend_1521_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1522_0,stringappend_1523_0) =>
+       (stringappend_1522_0, stringappend_1523_0)
+       )) in
+  let stringappend_1524_0 = (string_drop stringappend_1521_0
+                               stringappend_1523_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1524_0)) of
+        SOME (stringappend_1525_0,stringappend_1526_0) =>
+  (stringappend_1525_0, stringappend_1526_0)
+  ) of
+      (() , stringappend_1526_0) =>
+  let stringappend_1527_0 = (string_drop stringappend_1524_0
+                               stringappend_1526_0) in
+  let (rs2, stringappend_1529_0) =
+      ((case ((reg_name_matches_prefix stringappend_1527_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1528_0,stringappend_1529_0) =>
+       (stringappend_1528_0, stringappend_1529_0)
+       )) in
+  (case ((string_drop stringappend_1527_0 stringappend_1529_0)) of
+        "" => STORECON (aq,rl,rs2,rs1,size1,rd)
+  )
+  )
+  )
+  )
+        else if ((case ((amo_mnemonic_matches_prefix stringappend_1076_0)) of
+            SOME (stringappend_1531_0,stringappend_1532_0) =>
+             let stringappend_1533_0 = (string_drop stringappend_1076_0 stringappend_1532_0) in
+             if (((((string_startswith stringappend_1533_0 ".")) /\ (let stringappend_1534_0 = (string_drop stringappend_1533_0 ((string_length "."))) in
+                    if ((case ((size_mnemonic_matches_prefix stringappend_1534_0)) of
+                        SOME (stringappend_1535_0,stringappend_1536_0) =>
+                         let stringappend_1537_0 =
+                           (string_drop stringappend_1534_0 stringappend_1536_0) in
+                         if ((case ((maybe_aq_matches_prefix stringappend_1537_0)) of
+                             SOME (stringappend_1538_0,stringappend_1539_0) =>
+                              let stringappend_1540_0 =
+                                (string_drop stringappend_1537_0 stringappend_1539_0) in
+                              if ((case ((maybe_rl_matches_prefix stringappend_1540_0)) of
+                                  SOME (stringappend_1541_0,stringappend_1542_0) =>
+                                   let stringappend_1543_0 =
+                                     (string_drop stringappend_1540_0 stringappend_1542_0) in
+                                   if ((case ((spc_matches_prefix stringappend_1543_0)) of
+                                       SOME (stringappend_1544_0,stringappend_1545_0) =>
+                                        let stringappend_1546_0 =
+                                          (string_drop stringappend_1543_0 stringappend_1545_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_1546_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_1547_0,stringappend_1548_0) =>
+                                             let stringappend_1549_0 =
+                                               (string_drop stringappend_1546_0 stringappend_1548_0) in
+                                             if ((case ((sep_matches_prefix stringappend_1549_0)) of
+                                                 SOME (stringappend_1550_0,stringappend_1551_0) =>
+                                                  let stringappend_1552_0 =
+                                                    (string_drop stringappend_1549_0
+                                                      stringappend_1551_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_1552_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_1553_0,stringappend_1554_0) =>
+                                                       let stringappend_1555_0 =
+                                                         (string_drop stringappend_1552_0
+                                                           stringappend_1554_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_1555_0)) of
+                                                           SOME
+                                                           (stringappend_1556_0,stringappend_1557_0) =>
+                                                            let stringappend_1558_0 =
+                                                              (string_drop stringappend_1555_0
+                                                                stringappend_1557_0) in
+                                                            if ((case ((reg_name_matches_prefix
+                                                                          stringappend_1558_0
+                                                                         :  (( 5 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_1559_0,stringappend_1560_0) =>
+                                                                 (case ((string_drop
+                                                                           stringappend_1558_0
+                                                                           stringappend_1560_0)) of
+                                                                   "" => T
+                                                                 | _ => F
+                                                                 )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+               T
+             else F
+          | NONE => F
+          )) then
+          let (op, stringappend_1532_0) =
+            ((case ((amo_mnemonic_matches_prefix stringappend_1076_0)) of
+              SOME (stringappend_1531_0,stringappend_1532_0) =>
+               (stringappend_1531_0, stringappend_1532_0)
+            )) in
+          let stringappend_1533_0 = (string_drop stringappend_1076_0 stringappend_1532_0) in
+          let stringappend_1534_0 = (string_drop stringappend_1533_0 ((string_length "."))) in
+          let (width, stringappend_1536_0) =
+            ((case ((size_mnemonic_matches_prefix stringappend_1534_0)) of
+              SOME (stringappend_1535_0,stringappend_1536_0) =>
+               (stringappend_1535_0, stringappend_1536_0)
+            )) in
+          let stringappend_1537_0 = (string_drop stringappend_1534_0 stringappend_1536_0) in
+          let (aq, stringappend_1539_0) =
+            ((case ((maybe_aq_matches_prefix stringappend_1537_0)) of
+              SOME (stringappend_1538_0,stringappend_1539_0) =>
+               (stringappend_1538_0, stringappend_1539_0)
+            )) in
+          let stringappend_1540_0 = (string_drop stringappend_1537_0 stringappend_1539_0) in
+          let (rl, stringappend_1542_0) =
+            ((case ((maybe_rl_matches_prefix stringappend_1540_0)) of
+              SOME (stringappend_1541_0,stringappend_1542_0) =>
+               (stringappend_1541_0, stringappend_1542_0)
+            )) in
+          let stringappend_1543_0 = (string_drop stringappend_1540_0 stringappend_1542_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1543_0)) of
+        SOME (stringappend_1544_0,stringappend_1545_0) =>
+  (stringappend_1544_0, stringappend_1545_0)
+  ) of
+      (() , stringappend_1545_0) =>
+  let stringappend_1546_0 = (string_drop stringappend_1543_0
+                               stringappend_1545_0) in
+  let (rd, stringappend_1548_0) =
+      ((case ((reg_name_matches_prefix stringappend_1546_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1547_0,stringappend_1548_0) =>
+       (stringappend_1547_0, stringappend_1548_0)
+       )) in
+  let stringappend_1549_0 = (string_drop stringappend_1546_0
+                               stringappend_1548_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1549_0)) of
+        SOME (stringappend_1550_0,stringappend_1551_0) =>
+  (stringappend_1550_0, stringappend_1551_0)
+  ) of
+      (() , stringappend_1551_0) =>
+  let stringappend_1552_0 = (string_drop stringappend_1549_0
+                               stringappend_1551_0) in
+  let (rs1, stringappend_1554_0) =
+      ((case ((reg_name_matches_prefix stringappend_1552_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1553_0,stringappend_1554_0) =>
+       (stringappend_1553_0, stringappend_1554_0)
+       )) in
+  let stringappend_1555_0 = (string_drop stringappend_1552_0
+                               stringappend_1554_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1555_0)) of
+        SOME (stringappend_1556_0,stringappend_1557_0) =>
+  (stringappend_1556_0, stringappend_1557_0)
+  ) of
+      (() , stringappend_1557_0) =>
+  let stringappend_1558_0 = (string_drop stringappend_1555_0
+                               stringappend_1557_0) in
+  let (rs2, stringappend_1560_0) =
+      ((case ((reg_name_matches_prefix stringappend_1558_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1559_0,stringappend_1560_0) =>
+       (stringappend_1559_0, stringappend_1560_0)
+       )) in
+  (case ((string_drop stringappend_1558_0 stringappend_1560_0)) of
+        "" => AMO (op,aq,rl,rs2,rs1,width,rd)
+  )
+  )
+  )
+  )
+        else if ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of
+            SOME (stringappend_1562_0,stringappend_1563_0) =>
+             let stringappend_1564_0 = (string_drop stringappend_1076_0 stringappend_1563_0) in
+             if (((((string_startswith stringappend_1564_0 "i")) /\ (let stringappend_1565_0 = (string_drop stringappend_1564_0 ((string_length "i"))) in
+                    if ((case ((spc_matches_prefix stringappend_1565_0)) of
+                        SOME (stringappend_1566_0,stringappend_1567_0) =>
+                         let stringappend_1568_0 =
+                           (string_drop stringappend_1565_0 stringappend_1567_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_1568_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_1569_0,stringappend_1570_0) =>
+                              let stringappend_1571_0 =
+                                (string_drop stringappend_1568_0 stringappend_1570_0) in
+                              if ((case ((sep_matches_prefix stringappend_1571_0)) of
+                                  SOME (stringappend_1572_0,stringappend_1573_0) =>
+                                   let stringappend_1574_0 =
+                                     (string_drop stringappend_1571_0 stringappend_1573_0) in
+                                   if ((case ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1574_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_1575_0,stringappend_1576_0) =>
+                                        let stringappend_1577_0 =
+                                          (string_drop stringappend_1574_0 stringappend_1576_0) in
+                                        if ((case ((sep_matches_prefix stringappend_1577_0)) of
+                                            SOME (stringappend_1578_0,stringappend_1579_0) =>
+                                             let stringappend_1580_0 =
+                                               (string_drop stringappend_1577_0 stringappend_1579_0) in
+                                             if ((case ((csr_name_map_matches_prefix
+                                                           stringappend_1580_0
+                                                          :  (( 12 words$word # ii))option)) of
+                                                 SOME (stringappend_1581_0,stringappend_1582_0) =>
+                                                  (case ((string_drop stringappend_1580_0
+                                                            stringappend_1582_0)) of
+                                                    "" => T
+                                                  | _ => F
+                                                  )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+               T
+             else F
+          | NONE => F
+          )) then
+          let (op, stringappend_1563_0) =
+            ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of
+              SOME (stringappend_1562_0,stringappend_1563_0) =>
+               (stringappend_1562_0, stringappend_1563_0)
+            )) in
+          let stringappend_1564_0 = (string_drop stringappend_1076_0 stringappend_1563_0) in
+          let stringappend_1565_0 = (string_drop stringappend_1564_0 ((string_length "i"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1565_0)) of
+        SOME (stringappend_1566_0,stringappend_1567_0) =>
+  (stringappend_1566_0, stringappend_1567_0)
+  ) of
+      (() , stringappend_1567_0) =>
+  let stringappend_1568_0 = (string_drop stringappend_1565_0
+                               stringappend_1567_0) in
+  let (rd, stringappend_1570_0) =
+      ((case ((reg_name_matches_prefix stringappend_1568_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1569_0,stringappend_1570_0) =>
+       (stringappend_1569_0, stringappend_1570_0)
+       )) in
+  let stringappend_1571_0 = (string_drop stringappend_1568_0
+                               stringappend_1570_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1571_0)) of
+        SOME (stringappend_1572_0,stringappend_1573_0) =>
+  (stringappend_1572_0, stringappend_1573_0)
+  ) of
+      (() , stringappend_1573_0) =>
+  let stringappend_1574_0 = (string_drop stringappend_1571_0
+                               stringappend_1573_0) in
+  let (rs1, stringappend_1576_0) =
+      ((case ((hex_bits_5_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1574_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1575_0,stringappend_1576_0) =>
+       (stringappend_1575_0, stringappend_1576_0)
+       )) in
+  let stringappend_1577_0 = (string_drop stringappend_1574_0
+                               stringappend_1576_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1577_0)) of
+        SOME (stringappend_1578_0,stringappend_1579_0) =>
+  (stringappend_1578_0, stringappend_1579_0)
+  ) of
+      (() , stringappend_1579_0) =>
+  let stringappend_1580_0 = (string_drop stringappend_1577_0
+                               stringappend_1579_0) in
+  let (csr, stringappend_1582_0) =
+      ((case ((csr_name_map_matches_prefix stringappend_1580_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1581_0,stringappend_1582_0) =>
+       (stringappend_1581_0, stringappend_1582_0)
+       )) in
+  (case ((string_drop stringappend_1580_0 stringappend_1582_0)) of
+        "" => CSR (csr,rs1,rd,T,op)
+  )
+  )
+  )
+  )
+        else if ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of
+            SOME (stringappend_1584_0,stringappend_1585_0) =>
+             let stringappend_1586_0 = (string_drop stringappend_1076_0 stringappend_1585_0) in
+             if ((case ((spc_matches_prefix stringappend_1586_0)) of
+                 SOME (stringappend_1587_0,stringappend_1588_0) =>
+                  let stringappend_1589_0 = (string_drop stringappend_1586_0 stringappend_1588_0) in
+                  if ((case ((reg_name_matches_prefix stringappend_1589_0
+                               :  (( 5 words$word # ii))option)) of
+                      SOME (stringappend_1590_0,stringappend_1591_0) =>
+                       let stringappend_1592_0 = (string_drop stringappend_1589_0 stringappend_1591_0) in
+                       if ((case ((sep_matches_prefix stringappend_1592_0)) of
+                           SOME (stringappend_1593_0,stringappend_1594_0) =>
+                            let stringappend_1595_0 =
+                              (string_drop stringappend_1592_0 stringappend_1594_0) in
+                            if ((case ((reg_name_matches_prefix stringappend_1595_0
+                                         :  (( 5 words$word # ii))option)) of
+                                SOME (stringappend_1596_0,stringappend_1597_0) =>
+                                 let stringappend_1598_0 =
+                                   (string_drop stringappend_1595_0 stringappend_1597_0) in
+                                 if ((case ((sep_matches_prefix stringappend_1598_0)) of
+                                     SOME (stringappend_1599_0,stringappend_1600_0) =>
+                                      let stringappend_1601_0 =
+                                        (string_drop stringappend_1598_0 stringappend_1600_0) in
+                                      if ((case ((csr_name_map_matches_prefix stringappend_1601_0
+                                                   :  (( 12 words$word # ii))option)) of
+                                          SOME (stringappend_1602_0,stringappend_1603_0) =>
+                                           (case ((string_drop stringappend_1601_0
+                                                     stringappend_1603_0)) of
+                                             "" => T
+                                           | _ => F
+                                           )
+                                        | NONE => F
+                                        )) then
+                                        T
+                                      else F
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          let (op, stringappend_1585_0) =
+            ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of
+              SOME (stringappend_1584_0,stringappend_1585_0) =>
+               (stringappend_1584_0, stringappend_1585_0)
+            )) in
+          let stringappend_1586_0 = (string_drop stringappend_1076_0 stringappend_1585_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1586_0)) of
+        SOME (stringappend_1587_0,stringappend_1588_0) =>
+  (stringappend_1587_0, stringappend_1588_0)
+  ) of
+      (() , stringappend_1588_0) =>
+  let stringappend_1589_0 = (string_drop stringappend_1586_0
+                               stringappend_1588_0) in
+  let (rd, stringappend_1591_0) =
+      ((case ((reg_name_matches_prefix stringappend_1589_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1590_0,stringappend_1591_0) =>
+       (stringappend_1590_0, stringappend_1591_0)
+       )) in
+  let stringappend_1592_0 = (string_drop stringappend_1589_0
+                               stringappend_1591_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1592_0)) of
+        SOME (stringappend_1593_0,stringappend_1594_0) =>
+  (stringappend_1593_0, stringappend_1594_0)
+  ) of
+      (() , stringappend_1594_0) =>
+  let stringappend_1595_0 = (string_drop stringappend_1592_0
+                               stringappend_1594_0) in
+  let (rs1, stringappend_1597_0) =
+      ((case ((reg_name_matches_prefix stringappend_1595_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1596_0,stringappend_1597_0) =>
+       (stringappend_1596_0, stringappend_1597_0)
+       )) in
+  let stringappend_1598_0 = (string_drop stringappend_1595_0
+                               stringappend_1597_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1598_0)) of
+        SOME (stringappend_1599_0,stringappend_1600_0) =>
+  (stringappend_1599_0, stringappend_1600_0)
+  ) of
+      (() , stringappend_1600_0) =>
+  let stringappend_1601_0 = (string_drop stringappend_1598_0
+                               stringappend_1600_0) in
+  let (csr, stringappend_1603_0) =
+      ((case ((csr_name_map_matches_prefix stringappend_1601_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1602_0,stringappend_1603_0) =>
+       (stringappend_1602_0, stringappend_1603_0)
+       )) in
+  (case ((string_drop stringappend_1601_0 stringappend_1603_0)) of
+        "" => CSR (csr,rs1,rd,F,op)
+  )
+  )
+  )
+  )
+        else
+          let stringappend_1605_0 = (string_drop stringappend_1076_0 ((string_length "illegal"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1605_0)) of
+        SOME (stringappend_1606_0,stringappend_1607_0) =>
+  (stringappend_1606_0, stringappend_1607_0)
+  ) of
+      (() , stringappend_1607_0) =>
+  let stringappend_1608_0 = (string_drop stringappend_1605_0
+                               stringappend_1607_0) in
+  let (s, stringappend_1610_0) =
+      ((case ((hex_bits_32_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1608_0 : (( 32 words$word # ii)) option)) of
+             SOME (stringappend_1609_0,stringappend_1610_0) =>
+       (stringappend_1609_0, stringappend_1610_0)
+       )) in
+  (case ((string_drop stringappend_1608_0 stringappend_1610_0)) of
+        "" => ILLEGAL s
+  )
+  )
+     )))`;
+
+
+(*val assembly_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((assembly_forwards_matches:ast -> bool) arg_=
+    ((case arg_ of
+     UTYPE (imm,rd,op) => T
+   | RISCV_JAL (imm,rd) => T
+   | RISCV_JALR (imm,rs1,rd) => T
+   | BTYPE (imm,rs2,rs1,op) => T
+   | ITYPE (imm,rs1,rd,op) => T
+   | SHIFTIOP (shamt,rs1,rd,op) => T
+   | RTYPE (rs2,rs1,rd,op) => T
+   | LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl) => T
+   | STORE (imm,rs1,rd,size1,aq,rl) => T
+   | ADDIW (imm,rs1,rd) => T
+   | SHIFTW (shamt,rs1,rd,op) => T
+   | RTYPEW (rs2,rs1,rd,op) => T
+   | MUL (rs2,rs1,rd,high,signed1,signed2) => T
+   | DIV0 (rs2,rs1,rd,s) => T
+   | REM (rs2,rs1,rd,s) => T
+   | MULW (rs2,rs1,rd) => T
+   | DIVW (rs2,rs1,rd,s) => T
+   | REMW (rs2,rs1,rd,s) => T
+   | FENCE (pred,succ) => T
+   | FENCEI (() ) => T
+   | ECALL (() ) => T
+   | MRET (() ) => T
+   | SRET (() ) => T
+   | EBREAK (() ) => T
+   | WFI (() ) => T
+   | SFENCE_VMA (rs1,rs2) => T
+   | LOADRES (aq,rl,rs1,size1,rd) => T
+   | STORECON (aq,rl,rs2,rs1,size1,rd) => T
+   | AMO (op,aq,rl,rs2,rs1,width,rd) => T
+   | CSR (csr,rs1,rd,T,op) => T
+   | CSR (csr,rs1,rd,F,op) => T
+   | ILLEGAL (s) => T
+   | _ => F
+   )))`;
+
+
+(*val assembly_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((assembly_backwards_matches:string -> bool) arg_=
+    (let stringappend_541_0 = arg_ in
+   if ((case ((utype_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_542_0,stringappend_543_0) =>
+        let stringappend_544_0 = (string_drop stringappend_541_0 stringappend_543_0) in
+        if ((case ((spc_matches_prefix stringappend_544_0)) of
+            SOME (stringappend_545_0,stringappend_546_0) =>
+             let stringappend_547_0 = (string_drop stringappend_544_0 stringappend_546_0) in
+             if ((case ((reg_name_matches_prefix stringappend_547_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_548_0,stringappend_549_0) =>
+                  let stringappend_550_0 = (string_drop stringappend_547_0 stringappend_549_0) in
+                  if ((case ((sep_matches_prefix stringappend_550_0)) of
+                      SOME (stringappend_551_0,stringappend_552_0) =>
+                       let stringappend_553_0 = (string_drop stringappend_550_0 stringappend_552_0) in
+                       if ((case ((hex_bits_20_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_553_0
+                                    :  (( 20 words$word # ii))option)) of
+                           SOME (stringappend_554_0,stringappend_555_0) =>
+                            (case ((string_drop stringappend_553_0 stringappend_555_0)) of
+                              "" => T
+                            | _ => F
+                            )
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_543_0) =
+       ((case ((utype_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_542_0,stringappend_543_0) => (stringappend_542_0, stringappend_543_0)
+       )) in
+     let stringappend_544_0 = (string_drop stringappend_541_0 stringappend_543_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_544_0)) of
+        SOME (stringappend_545_0,stringappend_546_0) => (stringappend_545_0, stringappend_546_0)
+  ) of
+      (() , stringappend_546_0) =>
+  let stringappend_547_0 = (string_drop stringappend_544_0 stringappend_546_0) in
+  let (rd, stringappend_549_0) =
+      ((case ((reg_name_matches_prefix stringappend_547_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_548_0,stringappend_549_0) => (stringappend_548_0, stringappend_549_0)
+       )) in
+  let stringappend_550_0 = (string_drop stringappend_547_0 stringappend_549_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_550_0)) of
+        SOME (stringappend_551_0,stringappend_552_0) => (stringappend_551_0, stringappend_552_0)
+  ) of
+      (() , stringappend_552_0) =>
+  let stringappend_553_0 = (string_drop stringappend_550_0 stringappend_552_0) in
+  let (imm, stringappend_555_0) =
+      ((case ((hex_bits_20_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_553_0 : (( 20 words$word # ii)) option)) of
+             SOME (stringappend_554_0,stringappend_555_0) => (stringappend_554_0, stringappend_555_0)
+       )) in
+  (case ((string_drop stringappend_553_0 stringappend_555_0)) of   "" => T )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "jal")) /\ (let stringappend_557_0 = (string_drop stringappend_541_0 ((string_length "jal"))) in
+               if ((case ((spc_matches_prefix stringappend_557_0)) of
+                   SOME (stringappend_558_0,stringappend_559_0) =>
+                    let stringappend_560_0 = (string_drop stringappend_557_0 stringappend_559_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_560_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_561_0,stringappend_562_0) =>
+                         let stringappend_563_0 = (string_drop stringappend_560_0 stringappend_562_0) in
+                         if ((case ((sep_matches_prefix stringappend_563_0)) of
+                             SOME (stringappend_564_0,stringappend_565_0) =>
+                              let stringappend_566_0 =
+                                (string_drop stringappend_563_0 stringappend_565_0) in
+                              if ((case ((hex_bits_21_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_566_0
+                                           :  (( 21 words$word # ii))option)) of
+                                  SOME (stringappend_567_0,stringappend_568_0) =>
+                                   (case ((string_drop stringappend_566_0 stringappend_568_0)) of
+                                     "" => T
+                                   | _ => F
+                                   )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_557_0 = (string_drop stringappend_541_0 ((string_length "jal"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_557_0)) of
+        SOME (stringappend_558_0,stringappend_559_0) => (stringappend_558_0, stringappend_559_0)
+  ) of
+      (() , stringappend_559_0) =>
+  let stringappend_560_0 = (string_drop stringappend_557_0 stringappend_559_0) in
+  let (rd, stringappend_562_0) =
+      ((case ((reg_name_matches_prefix stringappend_560_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_561_0,stringappend_562_0) => (stringappend_561_0, stringappend_562_0)
+       )) in
+  let stringappend_563_0 = (string_drop stringappend_560_0 stringappend_562_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_563_0)) of
+        SOME (stringappend_564_0,stringappend_565_0) => (stringappend_564_0, stringappend_565_0)
+  ) of
+      (() , stringappend_565_0) =>
+  let stringappend_566_0 = (string_drop stringappend_563_0 stringappend_565_0) in
+  let (imm, stringappend_568_0) =
+      ((case ((hex_bits_21_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_566_0 : (( 21 words$word # ii)) option)) of
+             SOME (stringappend_567_0,stringappend_568_0) => (stringappend_567_0, stringappend_568_0)
+       )) in
+  (case ((string_drop stringappend_566_0 stringappend_568_0)) of   "" => T )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "jalr")) /\ (let stringappend_570_0 = (string_drop stringappend_541_0 ((string_length "jalr"))) in
+               if ((case ((spc_matches_prefix stringappend_570_0)) of
+                   SOME (stringappend_571_0,stringappend_572_0) =>
+                    let stringappend_573_0 = (string_drop stringappend_570_0 stringappend_572_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_573_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_574_0,stringappend_575_0) =>
+                         let stringappend_576_0 = (string_drop stringappend_573_0 stringappend_575_0) in
+                         if ((case ((sep_matches_prefix stringappend_576_0)) of
+                             SOME (stringappend_577_0,stringappend_578_0) =>
+                              let stringappend_579_0 =
+                                (string_drop stringappend_576_0 stringappend_578_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_579_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_580_0,stringappend_581_0) =>
+                                   let stringappend_582_0 =
+                                     (string_drop stringappend_579_0 stringappend_581_0) in
+                                   if ((case ((sep_matches_prefix stringappend_582_0)) of
+                                       SOME (stringappend_583_0,stringappend_584_0) =>
+                                        let stringappend_585_0 =
+                                          (string_drop stringappend_582_0 stringappend_584_0) in
+                                        if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_585_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_586_0,stringappend_587_0) =>
+                                             (case ((string_drop stringappend_585_0
+                                                       stringappend_587_0)) of
+                                               "" => T
+                                             | _ => F
+                                             )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_570_0 = (string_drop stringappend_541_0 ((string_length "jalr"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_570_0)) of
+        SOME (stringappend_571_0,stringappend_572_0) => (stringappend_571_0, stringappend_572_0)
+  ) of
+      (() , stringappend_572_0) =>
+  let stringappend_573_0 = (string_drop stringappend_570_0 stringappend_572_0) in
+  let (rd, stringappend_575_0) =
+      ((case ((reg_name_matches_prefix stringappend_573_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_574_0,stringappend_575_0) => (stringappend_574_0, stringappend_575_0)
+       )) in
+  let stringappend_576_0 = (string_drop stringappend_573_0 stringappend_575_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_576_0)) of
+        SOME (stringappend_577_0,stringappend_578_0) => (stringappend_577_0, stringappend_578_0)
+  ) of
+      (() , stringappend_578_0) =>
+  let stringappend_579_0 = (string_drop stringappend_576_0 stringappend_578_0) in
+  let (rs1, stringappend_581_0) =
+      ((case ((reg_name_matches_prefix stringappend_579_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_580_0,stringappend_581_0) => (stringappend_580_0, stringappend_581_0)
+       )) in
+  let stringappend_582_0 = (string_drop stringappend_579_0 stringappend_581_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_582_0)) of
+        SOME (stringappend_583_0,stringappend_584_0) => (stringappend_583_0, stringappend_584_0)
+  ) of
+      (() , stringappend_584_0) =>
+  let stringappend_585_0 = (string_drop stringappend_582_0 stringappend_584_0) in
+  let (imm, stringappend_587_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_585_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_586_0,stringappend_587_0) => (stringappend_586_0, stringappend_587_0)
+       )) in
+  (case ((string_drop stringappend_585_0 stringappend_587_0)) of   "" => T )
+  )
+  )
+  )
+   else if ((case ((btype_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_589_0,stringappend_590_0) =>
+        let stringappend_591_0 = (string_drop stringappend_541_0 stringappend_590_0) in
+        if ((case ((spc_matches_prefix stringappend_591_0)) of
+            SOME (stringappend_592_0,stringappend_593_0) =>
+             let stringappend_594_0 = (string_drop stringappend_591_0 stringappend_593_0) in
+             if ((case ((reg_name_matches_prefix stringappend_594_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_595_0,stringappend_596_0) =>
+                  let stringappend_597_0 = (string_drop stringappend_594_0 stringappend_596_0) in
+                  if ((case ((sep_matches_prefix stringappend_597_0)) of
+                      SOME (stringappend_598_0,stringappend_599_0) =>
+                       let stringappend_600_0 = (string_drop stringappend_597_0 stringappend_599_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_600_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_601_0,stringappend_602_0) =>
+                            let stringappend_603_0 =
+                              (string_drop stringappend_600_0 stringappend_602_0) in
+                            if ((case ((sep_matches_prefix stringappend_603_0)) of
+                                SOME (stringappend_604_0,stringappend_605_0) =>
+                                 let stringappend_606_0 =
+                                   (string_drop stringappend_603_0 stringappend_605_0) in
+                                 if ((case ((hex_bits_13_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_606_0
+                                              :  (( 13 words$word # ii))option)) of
+                                     SOME (stringappend_607_0,stringappend_608_0) =>
+                                      (case ((string_drop stringappend_606_0 stringappend_608_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_590_0) =
+       ((case ((btype_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_589_0,stringappend_590_0) => (stringappend_589_0, stringappend_590_0)
+       )) in
+     let stringappend_591_0 = (string_drop stringappend_541_0 stringappend_590_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_591_0)) of
+        SOME (stringappend_592_0,stringappend_593_0) => (stringappend_592_0, stringappend_593_0)
+  ) of
+      (() , stringappend_593_0) =>
+  let stringappend_594_0 = (string_drop stringappend_591_0 stringappend_593_0) in
+  let (rs1, stringappend_596_0) =
+      ((case ((reg_name_matches_prefix stringappend_594_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_595_0,stringappend_596_0) => (stringappend_595_0, stringappend_596_0)
+       )) in
+  let stringappend_597_0 = (string_drop stringappend_594_0 stringappend_596_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_597_0)) of
+        SOME (stringappend_598_0,stringappend_599_0) => (stringappend_598_0, stringappend_599_0)
+  ) of
+      (() , stringappend_599_0) =>
+  let stringappend_600_0 = (string_drop stringappend_597_0 stringappend_599_0) in
+  let (rs2, stringappend_602_0) =
+      ((case ((reg_name_matches_prefix stringappend_600_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_601_0,stringappend_602_0) => (stringappend_601_0, stringappend_602_0)
+       )) in
+  let stringappend_603_0 = (string_drop stringappend_600_0 stringappend_602_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_603_0)) of
+        SOME (stringappend_604_0,stringappend_605_0) => (stringappend_604_0, stringappend_605_0)
+  ) of
+      (() , stringappend_605_0) =>
+  let stringappend_606_0 = (string_drop stringappend_603_0 stringappend_605_0) in
+  let (imm, stringappend_608_0) =
+      ((case ((hex_bits_13_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_606_0 : (( 13 words$word # ii)) option)) of
+             SOME (stringappend_607_0,stringappend_608_0) => (stringappend_607_0, stringappend_608_0)
+       )) in
+  (case ((string_drop stringappend_606_0 stringappend_608_0)) of   "" => T )
+  )
+  )
+  )
+   else if ((case ((itype_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_610_0,stringappend_611_0) =>
+        let stringappend_612_0 = (string_drop stringappend_541_0 stringappend_611_0) in
+        if ((case ((spc_matches_prefix stringappend_612_0)) of
+            SOME (stringappend_613_0,stringappend_614_0) =>
+             let stringappend_615_0 = (string_drop stringappend_612_0 stringappend_614_0) in
+             if ((case ((reg_name_matches_prefix stringappend_615_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_616_0,stringappend_617_0) =>
+                  let stringappend_618_0 = (string_drop stringappend_615_0 stringappend_617_0) in
+                  if ((case ((sep_matches_prefix stringappend_618_0)) of
+                      SOME (stringappend_619_0,stringappend_620_0) =>
+                       let stringappend_621_0 = (string_drop stringappend_618_0 stringappend_620_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_621_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_622_0,stringappend_623_0) =>
+                            let stringappend_624_0 =
+                              (string_drop stringappend_621_0 stringappend_623_0) in
+                            if ((case ((sep_matches_prefix stringappend_624_0)) of
+                                SOME (stringappend_625_0,stringappend_626_0) =>
+                                 let stringappend_627_0 =
+                                   (string_drop stringappend_624_0 stringappend_626_0) in
+                                 if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_627_0
+                                              :  (( 12 words$word # ii))option)) of
+                                     SOME (stringappend_628_0,stringappend_629_0) =>
+                                      (case ((string_drop stringappend_627_0 stringappend_629_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_611_0) =
+       ((case ((itype_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_610_0,stringappend_611_0) => (stringappend_610_0, stringappend_611_0)
+       )) in
+     let stringappend_612_0 = (string_drop stringappend_541_0 stringappend_611_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_612_0)) of
+        SOME (stringappend_613_0,stringappend_614_0) => (stringappend_613_0, stringappend_614_0)
+  ) of
+      (() , stringappend_614_0) =>
+  let stringappend_615_0 = (string_drop stringappend_612_0 stringappend_614_0) in
+  let (rd, stringappend_617_0) =
+      ((case ((reg_name_matches_prefix stringappend_615_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_616_0,stringappend_617_0) => (stringappend_616_0, stringappend_617_0)
+       )) in
+  let stringappend_618_0 = (string_drop stringappend_615_0 stringappend_617_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_618_0)) of
+        SOME (stringappend_619_0,stringappend_620_0) => (stringappend_619_0, stringappend_620_0)
+  ) of
+      (() , stringappend_620_0) =>
+  let stringappend_621_0 = (string_drop stringappend_618_0 stringappend_620_0) in
+  let (rs1, stringappend_623_0) =
+      ((case ((reg_name_matches_prefix stringappend_621_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_622_0,stringappend_623_0) => (stringappend_622_0, stringappend_623_0)
+       )) in
+  let stringappend_624_0 = (string_drop stringappend_621_0 stringappend_623_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_624_0)) of
+        SOME (stringappend_625_0,stringappend_626_0) => (stringappend_625_0, stringappend_626_0)
+  ) of
+      (() , stringappend_626_0) =>
+  let stringappend_627_0 = (string_drop stringappend_624_0 stringappend_626_0) in
+  let (imm, stringappend_629_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_627_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_628_0,stringappend_629_0) => (stringappend_628_0, stringappend_629_0)
+       )) in
+  (case ((string_drop stringappend_627_0 stringappend_629_0)) of   "" => T )
+  )
+  )
+  )
+   else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_631_0,stringappend_632_0) =>
+        let stringappend_633_0 = (string_drop stringappend_541_0 stringappend_632_0) in
+        if ((case ((spc_matches_prefix stringappend_633_0)) of
+            SOME (stringappend_634_0,stringappend_635_0) =>
+             let stringappend_636_0 = (string_drop stringappend_633_0 stringappend_635_0) in
+             if ((case ((reg_name_matches_prefix stringappend_636_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_637_0,stringappend_638_0) =>
+                  let stringappend_639_0 = (string_drop stringappend_636_0 stringappend_638_0) in
+                  if ((case ((sep_matches_prefix stringappend_639_0)) of
+                      SOME (stringappend_640_0,stringappend_641_0) =>
+                       let stringappend_642_0 = (string_drop stringappend_639_0 stringappend_641_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_642_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_643_0,stringappend_644_0) =>
+                            let stringappend_645_0 =
+                              (string_drop stringappend_642_0 stringappend_644_0) in
+                            if ((case ((hex_bits_6_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_645_0
+                                         :  (( 6 words$word # ii))option)) of
+                                SOME (stringappend_646_0,stringappend_647_0) =>
+                                 (case ((string_drop stringappend_645_0 stringappend_647_0)) of
+                                   "" => T
+                                 | _ => F
+                                 )
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_632_0) =
+       ((case ((shiftiop_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_631_0,stringappend_632_0) => (stringappend_631_0, stringappend_632_0)
+       )) in
+     let stringappend_633_0 = (string_drop stringappend_541_0 stringappend_632_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_633_0)) of
+        SOME (stringappend_634_0,stringappend_635_0) => (stringappend_634_0, stringappend_635_0)
+  ) of
+      (() , stringappend_635_0) =>
+  let stringappend_636_0 = (string_drop stringappend_633_0 stringappend_635_0) in
+  let (rd, stringappend_638_0) =
+      ((case ((reg_name_matches_prefix stringappend_636_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_637_0,stringappend_638_0) => (stringappend_637_0, stringappend_638_0)
+       )) in
+  let stringappend_639_0 = (string_drop stringappend_636_0 stringappend_638_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_639_0)) of
+        SOME (stringappend_640_0,stringappend_641_0) => (stringappend_640_0, stringappend_641_0)
+  ) of
+      (() , stringappend_641_0) =>
+  let stringappend_642_0 = (string_drop stringappend_639_0 stringappend_641_0) in
+  let (rs1, stringappend_644_0) =
+      ((case ((reg_name_matches_prefix stringappend_642_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_643_0,stringappend_644_0) => (stringappend_643_0, stringappend_644_0)
+       )) in
+  let stringappend_645_0 = (string_drop stringappend_642_0 stringappend_644_0) in
+  let (shamt, stringappend_647_0) =
+      ((case ((hex_bits_6_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_645_0 : (( 6 words$word # ii)) option)) of
+             SOME (stringappend_646_0,stringappend_647_0) => (stringappend_646_0, stringappend_647_0)
+       )) in
+  (case ((string_drop stringappend_645_0 stringappend_647_0)) of   "" => T )
+  )
+  )
+   else if ((case ((rtype_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_649_0,stringappend_650_0) =>
+        let stringappend_651_0 = (string_drop stringappend_541_0 stringappend_650_0) in
+        if ((case ((spc_matches_prefix stringappend_651_0)) of
+            SOME (stringappend_652_0,stringappend_653_0) =>
+             let stringappend_654_0 = (string_drop stringappend_651_0 stringappend_653_0) in
+             if ((case ((reg_name_matches_prefix stringappend_654_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_655_0,stringappend_656_0) =>
+                  let stringappend_657_0 = (string_drop stringappend_654_0 stringappend_656_0) in
+                  if ((case ((sep_matches_prefix stringappend_657_0)) of
+                      SOME (stringappend_658_0,stringappend_659_0) =>
+                       let stringappend_660_0 = (string_drop stringappend_657_0 stringappend_659_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_660_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_661_0,stringappend_662_0) =>
+                            let stringappend_663_0 =
+                              (string_drop stringappend_660_0 stringappend_662_0) in
+                            if ((case ((sep_matches_prefix stringappend_663_0)) of
+                                SOME (stringappend_664_0,stringappend_665_0) =>
+                                 let stringappend_666_0 =
+                                   (string_drop stringappend_663_0 stringappend_665_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_666_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_667_0,stringappend_668_0) =>
+                                      (case ((string_drop stringappend_666_0 stringappend_668_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_650_0) =
+       ((case ((rtype_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_649_0,stringappend_650_0) => (stringappend_649_0, stringappend_650_0)
+       )) in
+     let stringappend_651_0 = (string_drop stringappend_541_0 stringappend_650_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_651_0)) of
+        SOME (stringappend_652_0,stringappend_653_0) => (stringappend_652_0, stringappend_653_0)
+  ) of
+      (() , stringappend_653_0) =>
+  let stringappend_654_0 = (string_drop stringappend_651_0 stringappend_653_0) in
+  let (rd, stringappend_656_0) =
+      ((case ((reg_name_matches_prefix stringappend_654_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_655_0,stringappend_656_0) => (stringappend_655_0, stringappend_656_0)
+       )) in
+  let stringappend_657_0 = (string_drop stringappend_654_0 stringappend_656_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_657_0)) of
+        SOME (stringappend_658_0,stringappend_659_0) => (stringappend_658_0, stringappend_659_0)
+  ) of
+      (() , stringappend_659_0) =>
+  let stringappend_660_0 = (string_drop stringappend_657_0 stringappend_659_0) in
+  let (rs1, stringappend_662_0) =
+      ((case ((reg_name_matches_prefix stringappend_660_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_661_0,stringappend_662_0) => (stringappend_661_0, stringappend_662_0)
+       )) in
+  let stringappend_663_0 = (string_drop stringappend_660_0 stringappend_662_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_663_0)) of
+        SOME (stringappend_664_0,stringappend_665_0) => (stringappend_664_0, stringappend_665_0)
+  ) of
+      (() , stringappend_665_0) =>
+  let stringappend_666_0 = (string_drop stringappend_663_0 stringappend_665_0) in
+  let (rs2, stringappend_668_0) =
+      ((case ((reg_name_matches_prefix stringappend_666_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_667_0,stringappend_668_0) => (stringappend_667_0, stringappend_668_0)
+       )) in
+  (case ((string_drop stringappend_666_0 stringappend_668_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "l")) /\ (let stringappend_670_0 = (string_drop stringappend_541_0 ((string_length "l"))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_670_0)) of
+                   SOME (stringappend_671_0,stringappend_672_0) =>
+                    let stringappend_673_0 = (string_drop stringappend_670_0 stringappend_672_0) in
+                    if ((case ((maybe_u_matches_prefix stringappend_673_0)) of
+                        SOME (stringappend_674_0,stringappend_675_0) =>
+                         let stringappend_676_0 = (string_drop stringappend_673_0 stringappend_675_0) in
+                         if ((case ((maybe_aq_matches_prefix stringappend_676_0)) of
+                             SOME (stringappend_677_0,stringappend_678_0) =>
+                              let stringappend_679_0 =
+                                (string_drop stringappend_676_0 stringappend_678_0) in
+                              if ((case ((maybe_rl_matches_prefix stringappend_679_0)) of
+                                  SOME (stringappend_680_0,stringappend_681_0) =>
+                                   let stringappend_682_0 =
+                                     (string_drop stringappend_679_0 stringappend_681_0) in
+                                   if ((case ((spc_matches_prefix stringappend_682_0)) of
+                                       SOME (stringappend_683_0,stringappend_684_0) =>
+                                        let stringappend_685_0 =
+                                          (string_drop stringappend_682_0 stringappend_684_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_685_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_686_0,stringappend_687_0) =>
+                                             let stringappend_688_0 =
+                                               (string_drop stringappend_685_0 stringappend_687_0) in
+                                             if ((case ((sep_matches_prefix stringappend_688_0)) of
+                                                 SOME (stringappend_689_0,stringappend_690_0) =>
+                                                  let stringappend_691_0 =
+                                                    (string_drop stringappend_688_0
+                                                      stringappend_690_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_691_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_692_0,stringappend_693_0) =>
+                                                       let stringappend_694_0 =
+                                                         (string_drop stringappend_691_0
+                                                           stringappend_693_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_694_0)) of
+                                                           SOME
+                                                           (stringappend_695_0,stringappend_696_0) =>
+                                                            let stringappend_697_0 =
+                                                              (string_drop stringappend_694_0
+                                                                stringappend_696_0) in
+                                                            if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                          stringappend_697_0
+                                                                         :  (( 12 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_698_0,stringappend_699_0) =>
+                                                                 (case ((string_drop
+                                                                           stringappend_697_0
+                                                                           stringappend_699_0)) of
+                                                                   "" => T
+                                                                 | _ => F
+                                                                 )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_670_0 = (string_drop stringappend_541_0 ((string_length "l"))) in
+     let (size1, stringappend_672_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_670_0)) of
+         SOME (stringappend_671_0,stringappend_672_0) => (stringappend_671_0, stringappend_672_0)
+       )) in
+     let stringappend_673_0 = (string_drop stringappend_670_0 stringappend_672_0) in
+     let (is_unsigned, stringappend_675_0) =
+       ((case ((maybe_u_matches_prefix stringappend_673_0)) of
+         SOME (stringappend_674_0,stringappend_675_0) => (stringappend_674_0, stringappend_675_0)
+       )) in
+     let stringappend_676_0 = (string_drop stringappend_673_0 stringappend_675_0) in
+     let (aq, stringappend_678_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_676_0)) of
+         SOME (stringappend_677_0,stringappend_678_0) => (stringappend_677_0, stringappend_678_0)
+       )) in
+     let stringappend_679_0 = (string_drop stringappend_676_0 stringappend_678_0) in
+     let (rl, stringappend_681_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_679_0)) of
+         SOME (stringappend_680_0,stringappend_681_0) => (stringappend_680_0, stringappend_681_0)
+       )) in
+     let stringappend_682_0 = (string_drop stringappend_679_0 stringappend_681_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_682_0)) of
+        SOME (stringappend_683_0,stringappend_684_0) => (stringappend_683_0, stringappend_684_0)
+  ) of
+      (() , stringappend_684_0) =>
+  let stringappend_685_0 = (string_drop stringappend_682_0 stringappend_684_0) in
+  let (rd, stringappend_687_0) =
+      ((case ((reg_name_matches_prefix stringappend_685_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_686_0,stringappend_687_0) => (stringappend_686_0, stringappend_687_0)
+       )) in
+  let stringappend_688_0 = (string_drop stringappend_685_0 stringappend_687_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_688_0)) of
+        SOME (stringappend_689_0,stringappend_690_0) => (stringappend_689_0, stringappend_690_0)
+  ) of
+      (() , stringappend_690_0) =>
+  let stringappend_691_0 = (string_drop stringappend_688_0 stringappend_690_0) in
+  let (rs1, stringappend_693_0) =
+      ((case ((reg_name_matches_prefix stringappend_691_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_692_0,stringappend_693_0) => (stringappend_692_0, stringappend_693_0)
+       )) in
+  let stringappend_694_0 = (string_drop stringappend_691_0 stringappend_693_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_694_0)) of
+        SOME (stringappend_695_0,stringappend_696_0) => (stringappend_695_0, stringappend_696_0)
+  ) of
+      (() , stringappend_696_0) =>
+  let stringappend_697_0 = (string_drop stringappend_694_0 stringappend_696_0) in
+  let (imm, stringappend_699_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_697_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_698_0,stringappend_699_0) => (stringappend_698_0, stringappend_699_0)
+       )) in
+  (case ((string_drop stringappend_697_0 stringappend_699_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "s")) /\ (let stringappend_701_0 = (string_drop stringappend_541_0 ((string_length "s"))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_701_0)) of
+                   SOME (stringappend_702_0,stringappend_703_0) =>
+                    let stringappend_704_0 = (string_drop stringappend_701_0 stringappend_703_0) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_704_0)) of
+                        SOME (stringappend_705_0,stringappend_706_0) =>
+                         let stringappend_707_0 = (string_drop stringappend_704_0 stringappend_706_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_707_0)) of
+                             SOME (stringappend_708_0,stringappend_709_0) =>
+                              let stringappend_710_0 =
+                                (string_drop stringappend_707_0 stringappend_709_0) in
+                              if ((case ((spc_matches_prefix stringappend_710_0)) of
+                                  SOME (stringappend_711_0,stringappend_712_0) =>
+                                   let stringappend_713_0 =
+                                     (string_drop stringappend_710_0 stringappend_712_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_713_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_714_0,stringappend_715_0) =>
+                                        let stringappend_716_0 =
+                                          (string_drop stringappend_713_0 stringappend_715_0) in
+                                        if ((case ((sep_matches_prefix stringappend_716_0)) of
+                                            SOME (stringappend_717_0,stringappend_718_0) =>
+                                             let stringappend_719_0 =
+                                               (string_drop stringappend_716_0 stringappend_718_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_719_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_720_0,stringappend_721_0) =>
+                                                  let stringappend_722_0 =
+                                                    (string_drop stringappend_719_0
+                                                      stringappend_721_0) in
+                                                  if ((case ((sep_matches_prefix stringappend_722_0)) of
+                                                      SOME (stringappend_723_0,stringappend_724_0) =>
+                                                       let stringappend_725_0 =
+                                                         (string_drop stringappend_722_0
+                                                           stringappend_724_0) in
+                                                       if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                     stringappend_725_0
+                                                                    :  (( 12 words$word # ii))option)) of
+                                                           SOME
+                                                           (stringappend_726_0,stringappend_727_0) =>
+                                                            (case ((string_drop stringappend_725_0
+                                                                      stringappend_727_0)) of
+                                                              "" => T
+                                                            | _ => F
+                                                            )
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_701_0 = (string_drop stringappend_541_0 ((string_length "s"))) in
+     let (size1, stringappend_703_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_701_0)) of
+         SOME (stringappend_702_0,stringappend_703_0) => (stringappend_702_0, stringappend_703_0)
+       )) in
+     let stringappend_704_0 = (string_drop stringappend_701_0 stringappend_703_0) in
+     let (aq, stringappend_706_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_704_0)) of
+         SOME (stringappend_705_0,stringappend_706_0) => (stringappend_705_0, stringappend_706_0)
+       )) in
+     let stringappend_707_0 = (string_drop stringappend_704_0 stringappend_706_0) in
+     let (rl, stringappend_709_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_707_0)) of
+         SOME (stringappend_708_0,stringappend_709_0) => (stringappend_708_0, stringappend_709_0)
+       )) in
+     let stringappend_710_0 = (string_drop stringappend_707_0 stringappend_709_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_710_0)) of
+        SOME (stringappend_711_0,stringappend_712_0) => (stringappend_711_0, stringappend_712_0)
+  ) of
+      (() , stringappend_712_0) =>
+  let stringappend_713_0 = (string_drop stringappend_710_0 stringappend_712_0) in
+  let (rd, stringappend_715_0) =
+      ((case ((reg_name_matches_prefix stringappend_713_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_714_0,stringappend_715_0) => (stringappend_714_0, stringappend_715_0)
+       )) in
+  let stringappend_716_0 = (string_drop stringappend_713_0 stringappend_715_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_716_0)) of
+        SOME (stringappend_717_0,stringappend_718_0) => (stringappend_717_0, stringappend_718_0)
+  ) of
+      (() , stringappend_718_0) =>
+  let stringappend_719_0 = (string_drop stringappend_716_0 stringappend_718_0) in
+  let (rs1, stringappend_721_0) =
+      ((case ((reg_name_matches_prefix stringappend_719_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_720_0,stringappend_721_0) => (stringappend_720_0, stringappend_721_0)
+       )) in
+  let stringappend_722_0 = (string_drop stringappend_719_0 stringappend_721_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_722_0)) of
+        SOME (stringappend_723_0,stringappend_724_0) => (stringappend_723_0, stringappend_724_0)
+  ) of
+      (() , stringappend_724_0) =>
+  let stringappend_725_0 = (string_drop stringappend_722_0 stringappend_724_0) in
+  let (imm, stringappend_727_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_725_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_726_0,stringappend_727_0) => (stringappend_726_0, stringappend_727_0)
+       )) in
+  (case ((string_drop stringappend_725_0 stringappend_727_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "addiw")) /\ (let stringappend_729_0 = (string_drop stringappend_541_0 ((string_length "addiw"))) in
+               if ((case ((spc_matches_prefix stringappend_729_0)) of
+                   SOME (stringappend_730_0,stringappend_731_0) =>
+                    let stringappend_732_0 = (string_drop stringappend_729_0 stringappend_731_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_732_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_733_0,stringappend_734_0) =>
+                         let stringappend_735_0 = (string_drop stringappend_732_0 stringappend_734_0) in
+                         if ((case ((sep_matches_prefix stringappend_735_0)) of
+                             SOME (stringappend_736_0,stringappend_737_0) =>
+                              let stringappend_738_0 =
+                                (string_drop stringappend_735_0 stringappend_737_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_738_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_739_0,stringappend_740_0) =>
+                                   let stringappend_741_0 =
+                                     (string_drop stringappend_738_0 stringappend_740_0) in
+                                   if ((case ((sep_matches_prefix stringappend_741_0)) of
+                                       SOME (stringappend_742_0,stringappend_743_0) =>
+                                        let stringappend_744_0 =
+                                          (string_drop stringappend_741_0 stringappend_743_0) in
+                                        if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_744_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_745_0,stringappend_746_0) =>
+                                             (case ((string_drop stringappend_744_0
+                                                       stringappend_746_0)) of
+                                               "" => T
+                                             | _ => F
+                                             )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_729_0 = (string_drop stringappend_541_0 ((string_length "addiw"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_729_0)) of
+        SOME (stringappend_730_0,stringappend_731_0) => (stringappend_730_0, stringappend_731_0)
+  ) of
+      (() , stringappend_731_0) =>
+  let stringappend_732_0 = (string_drop stringappend_729_0 stringappend_731_0) in
+  let (rd, stringappend_734_0) =
+      ((case ((reg_name_matches_prefix stringappend_732_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_733_0,stringappend_734_0) => (stringappend_733_0, stringappend_734_0)
+       )) in
+  let stringappend_735_0 = (string_drop stringappend_732_0 stringappend_734_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_735_0)) of
+        SOME (stringappend_736_0,stringappend_737_0) => (stringappend_736_0, stringappend_737_0)
+  ) of
+      (() , stringappend_737_0) =>
+  let stringappend_738_0 = (string_drop stringappend_735_0 stringappend_737_0) in
+  let (rs1, stringappend_740_0) =
+      ((case ((reg_name_matches_prefix stringappend_738_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_739_0,stringappend_740_0) => (stringappend_739_0, stringappend_740_0)
+       )) in
+  let stringappend_741_0 = (string_drop stringappend_738_0 stringappend_740_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_741_0)) of
+        SOME (stringappend_742_0,stringappend_743_0) => (stringappend_742_0, stringappend_743_0)
+  ) of
+      (() , stringappend_743_0) =>
+  let stringappend_744_0 = (string_drop stringappend_741_0 stringappend_743_0) in
+  let (imm, stringappend_746_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_744_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_745_0,stringappend_746_0) => (stringappend_745_0, stringappend_746_0)
+       )) in
+  (case ((string_drop stringappend_744_0 stringappend_746_0)) of   "" => T )
+  )
+  )
+  )
+   else if ((case ((shiftw_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_748_0,stringappend_749_0) =>
+        let stringappend_750_0 = (string_drop stringappend_541_0 stringappend_749_0) in
+        if ((case ((spc_matches_prefix stringappend_750_0)) of
+            SOME (stringappend_751_0,stringappend_752_0) =>
+             let stringappend_753_0 = (string_drop stringappend_750_0 stringappend_752_0) in
+             if ((case ((reg_name_matches_prefix stringappend_753_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_754_0,stringappend_755_0) =>
+                  let stringappend_756_0 = (string_drop stringappend_753_0 stringappend_755_0) in
+                  if ((case ((sep_matches_prefix stringappend_756_0)) of
+                      SOME (stringappend_757_0,stringappend_758_0) =>
+                       let stringappend_759_0 = (string_drop stringappend_756_0 stringappend_758_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_759_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_760_0,stringappend_761_0) =>
+                            let stringappend_762_0 =
+                              (string_drop stringappend_759_0 stringappend_761_0) in
+                            if ((case ((sep_matches_prefix stringappend_762_0)) of
+                                SOME (stringappend_763_0,stringappend_764_0) =>
+                                 let stringappend_765_0 =
+                                   (string_drop stringappend_762_0 stringappend_764_0) in
+                                 if ((case ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_765_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_766_0,stringappend_767_0) =>
+                                      (case ((string_drop stringappend_765_0 stringappend_767_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_749_0) =
+       ((case ((shiftw_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_748_0,stringappend_749_0) => (stringappend_748_0, stringappend_749_0)
+       )) in
+     let stringappend_750_0 = (string_drop stringappend_541_0 stringappend_749_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_750_0)) of
+        SOME (stringappend_751_0,stringappend_752_0) => (stringappend_751_0, stringappend_752_0)
+  ) of
+      (() , stringappend_752_0) =>
+  let stringappend_753_0 = (string_drop stringappend_750_0 stringappend_752_0) in
+  let (rd, stringappend_755_0) =
+      ((case ((reg_name_matches_prefix stringappend_753_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_754_0,stringappend_755_0) => (stringappend_754_0, stringappend_755_0)
+       )) in
+  let stringappend_756_0 = (string_drop stringappend_753_0 stringappend_755_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_756_0)) of
+        SOME (stringappend_757_0,stringappend_758_0) => (stringappend_757_0, stringappend_758_0)
+  ) of
+      (() , stringappend_758_0) =>
+  let stringappend_759_0 = (string_drop stringappend_756_0 stringappend_758_0) in
+  let (rs1, stringappend_761_0) =
+      ((case ((reg_name_matches_prefix stringappend_759_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_760_0,stringappend_761_0) => (stringappend_760_0, stringappend_761_0)
+       )) in
+  let stringappend_762_0 = (string_drop stringappend_759_0 stringappend_761_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_762_0)) of
+        SOME (stringappend_763_0,stringappend_764_0) => (stringappend_763_0, stringappend_764_0)
+  ) of
+      (() , stringappend_764_0) =>
+  let stringappend_765_0 = (string_drop stringappend_762_0 stringappend_764_0) in
+  let (shamt, stringappend_767_0) =
+      ((case ((hex_bits_5_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_765_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_766_0,stringappend_767_0) => (stringappend_766_0, stringappend_767_0)
+       )) in
+  (case ((string_drop stringappend_765_0 stringappend_767_0)) of   "" => T )
+  )
+  )
+  )
+   else if ((case ((rtypew_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_769_0,stringappend_770_0) =>
+        let stringappend_771_0 = (string_drop stringappend_541_0 stringappend_770_0) in
+        if ((case ((spc_matches_prefix stringappend_771_0)) of
+            SOME (stringappend_772_0,stringappend_773_0) =>
+             let stringappend_774_0 = (string_drop stringappend_771_0 stringappend_773_0) in
+             if ((case ((reg_name_matches_prefix stringappend_774_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_775_0,stringappend_776_0) =>
+                  let stringappend_777_0 = (string_drop stringappend_774_0 stringappend_776_0) in
+                  if ((case ((sep_matches_prefix stringappend_777_0)) of
+                      SOME (stringappend_778_0,stringappend_779_0) =>
+                       let stringappend_780_0 = (string_drop stringappend_777_0 stringappend_779_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_780_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_781_0,stringappend_782_0) =>
+                            let stringappend_783_0 =
+                              (string_drop stringappend_780_0 stringappend_782_0) in
+                            if ((case ((sep_matches_prefix stringappend_783_0)) of
+                                SOME (stringappend_784_0,stringappend_785_0) =>
+                                 let stringappend_786_0 =
+                                   (string_drop stringappend_783_0 stringappend_785_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_786_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_787_0,stringappend_788_0) =>
+                                      (case ((string_drop stringappend_786_0 stringappend_788_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_770_0) =
+       ((case ((rtypew_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_769_0,stringappend_770_0) => (stringappend_769_0, stringappend_770_0)
+       )) in
+     let stringappend_771_0 = (string_drop stringappend_541_0 stringappend_770_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_771_0)) of
+        SOME (stringappend_772_0,stringappend_773_0) => (stringappend_772_0, stringappend_773_0)
+  ) of
+      (() , stringappend_773_0) =>
+  let stringappend_774_0 = (string_drop stringappend_771_0 stringappend_773_0) in
+  let (rd, stringappend_776_0) =
+      ((case ((reg_name_matches_prefix stringappend_774_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_775_0,stringappend_776_0) => (stringappend_775_0, stringappend_776_0)
+       )) in
+  let stringappend_777_0 = (string_drop stringappend_774_0 stringappend_776_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_777_0)) of
+        SOME (stringappend_778_0,stringappend_779_0) => (stringappend_778_0, stringappend_779_0)
+  ) of
+      (() , stringappend_779_0) =>
+  let stringappend_780_0 = (string_drop stringappend_777_0 stringappend_779_0) in
+  let (rs1, stringappend_782_0) =
+      ((case ((reg_name_matches_prefix stringappend_780_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_781_0,stringappend_782_0) => (stringappend_781_0, stringappend_782_0)
+       )) in
+  let stringappend_783_0 = (string_drop stringappend_780_0 stringappend_782_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_783_0)) of
+        SOME (stringappend_784_0,stringappend_785_0) => (stringappend_784_0, stringappend_785_0)
+  ) of
+      (() , stringappend_785_0) =>
+  let stringappend_786_0 = (string_drop stringappend_783_0 stringappend_785_0) in
+  let (rs2, stringappend_788_0) =
+      ((case ((reg_name_matches_prefix stringappend_786_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_787_0,stringappend_788_0) => (stringappend_787_0, stringappend_788_0)
+       )) in
+  (case ((string_drop stringappend_786_0 stringappend_788_0)) of   "" => T )
+  )
+  )
+  )
+   else if ((case ((mul_mnemonic_matches_prefix stringappend_541_0)) of
+       SOME (stringappend_790_0,stringappend_791_0) =>
+        let stringappend_792_0 = (string_drop stringappend_541_0 stringappend_791_0) in
+        if ((case ((spc_matches_prefix stringappend_792_0)) of
+            SOME (stringappend_793_0,stringappend_794_0) =>
+             let stringappend_795_0 = (string_drop stringappend_792_0 stringappend_794_0) in
+             if ((case ((reg_name_matches_prefix stringappend_795_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_796_0,stringappend_797_0) =>
+                  let stringappend_798_0 = (string_drop stringappend_795_0 stringappend_797_0) in
+                  if ((case ((sep_matches_prefix stringappend_798_0)) of
+                      SOME (stringappend_799_0,stringappend_800_0) =>
+                       let stringappend_801_0 = (string_drop stringappend_798_0 stringappend_800_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_801_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_802_0,stringappend_803_0) =>
+                            let stringappend_804_0 =
+                              (string_drop stringappend_801_0 stringappend_803_0) in
+                            if ((case ((sep_matches_prefix stringappend_804_0)) of
+                                SOME (stringappend_805_0,stringappend_806_0) =>
+                                 let stringappend_807_0 =
+                                   (string_drop stringappend_804_0 stringappend_806_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_807_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_808_0,stringappend_809_0) =>
+                                      (case ((string_drop stringappend_807_0 stringappend_809_0)) of
+                                        "" => T
+                                      | _ => F
+                                      )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let ((high, signed1, signed2), stringappend_791_0) =
+       ((case ((mul_mnemonic_matches_prefix stringappend_541_0)) of
+         SOME (stringappend_790_0,stringappend_791_0) => (stringappend_790_0, stringappend_791_0)
+       )) in
+     let stringappend_792_0 = (string_drop stringappend_541_0 stringappend_791_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_792_0)) of
+        SOME (stringappend_793_0,stringappend_794_0) => (stringappend_793_0, stringappend_794_0)
+  ) of
+      (() , stringappend_794_0) =>
+  let stringappend_795_0 = (string_drop stringappend_792_0 stringappend_794_0) in
+  let (rd, stringappend_797_0) =
+      ((case ((reg_name_matches_prefix stringappend_795_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_796_0,stringappend_797_0) => (stringappend_796_0, stringappend_797_0)
+       )) in
+  let stringappend_798_0 = (string_drop stringappend_795_0 stringappend_797_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_798_0)) of
+        SOME (stringappend_799_0,stringappend_800_0) => (stringappend_799_0, stringappend_800_0)
+  ) of
+      (() , stringappend_800_0) =>
+  let stringappend_801_0 = (string_drop stringappend_798_0 stringappend_800_0) in
+  let (rs1, stringappend_803_0) =
+      ((case ((reg_name_matches_prefix stringappend_801_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_802_0,stringappend_803_0) => (stringappend_802_0, stringappend_803_0)
+       )) in
+  let stringappend_804_0 = (string_drop stringappend_801_0 stringappend_803_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_804_0)) of
+        SOME (stringappend_805_0,stringappend_806_0) => (stringappend_805_0, stringappend_806_0)
+  ) of
+      (() , stringappend_806_0) =>
+  let stringappend_807_0 = (string_drop stringappend_804_0 stringappend_806_0) in
+  let (rs2, stringappend_809_0) =
+      ((case ((reg_name_matches_prefix stringappend_807_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_808_0,stringappend_809_0) => (stringappend_808_0, stringappend_809_0)
+       )) in
+  (case ((string_drop stringappend_807_0 stringappend_809_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "div")) /\ (let stringappend_811_0 = (string_drop stringappend_541_0 ((string_length "div"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_811_0)) of
+                   SOME (stringappend_812_0,stringappend_813_0) =>
+                    let stringappend_814_0 = (string_drop stringappend_811_0 stringappend_813_0) in
+                    if ((case ((spc_matches_prefix stringappend_814_0)) of
+                        SOME (stringappend_815_0,stringappend_816_0) =>
+                         let stringappend_817_0 = (string_drop stringappend_814_0 stringappend_816_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_817_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_818_0,stringappend_819_0) =>
+                              let stringappend_820_0 =
+                                (string_drop stringappend_817_0 stringappend_819_0) in
+                              if ((case ((sep_matches_prefix stringappend_820_0)) of
+                                  SOME (stringappend_821_0,stringappend_822_0) =>
+                                   let stringappend_823_0 =
+                                     (string_drop stringappend_820_0 stringappend_822_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_823_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_824_0,stringappend_825_0) =>
+                                        let stringappend_826_0 =
+                                          (string_drop stringappend_823_0 stringappend_825_0) in
+                                        if ((case ((sep_matches_prefix stringappend_826_0)) of
+                                            SOME (stringappend_827_0,stringappend_828_0) =>
+                                             let stringappend_829_0 =
+                                               (string_drop stringappend_826_0 stringappend_828_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_829_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_830_0,stringappend_831_0) =>
+                                                  (case ((string_drop stringappend_829_0
+                                                            stringappend_831_0)) of
+                                                    "" => T
+                                                  | _ => F
+                                                  )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_811_0 = (string_drop stringappend_541_0 ((string_length "div"))) in
+     let (s, stringappend_813_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_811_0)) of
+         SOME (stringappend_812_0,stringappend_813_0) => (stringappend_812_0, stringappend_813_0)
+       )) in
+     let stringappend_814_0 = (string_drop stringappend_811_0 stringappend_813_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_814_0)) of
+        SOME (stringappend_815_0,stringappend_816_0) => (stringappend_815_0, stringappend_816_0)
+  ) of
+      (() , stringappend_816_0) =>
+  let stringappend_817_0 = (string_drop stringappend_814_0 stringappend_816_0) in
+  let (rd, stringappend_819_0) =
+      ((case ((reg_name_matches_prefix stringappend_817_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_818_0,stringappend_819_0) => (stringappend_818_0, stringappend_819_0)
+       )) in
+  let stringappend_820_0 = (string_drop stringappend_817_0 stringappend_819_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_820_0)) of
+        SOME (stringappend_821_0,stringappend_822_0) => (stringappend_821_0, stringappend_822_0)
+  ) of
+      (() , stringappend_822_0) =>
+  let stringappend_823_0 = (string_drop stringappend_820_0 stringappend_822_0) in
+  let (rs1, stringappend_825_0) =
+      ((case ((reg_name_matches_prefix stringappend_823_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_824_0,stringappend_825_0) => (stringappend_824_0, stringappend_825_0)
+       )) in
+  let stringappend_826_0 = (string_drop stringappend_823_0 stringappend_825_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_826_0)) of
+        SOME (stringappend_827_0,stringappend_828_0) => (stringappend_827_0, stringappend_828_0)
+  ) of
+      (() , stringappend_828_0) =>
+  let stringappend_829_0 = (string_drop stringappend_826_0 stringappend_828_0) in
+  let (rs2, stringappend_831_0) =
+      ((case ((reg_name_matches_prefix stringappend_829_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_830_0,stringappend_831_0) => (stringappend_830_0, stringappend_831_0)
+       )) in
+  (case ((string_drop stringappend_829_0 stringappend_831_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "rem")) /\ (let stringappend_833_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_833_0)) of
+                   SOME (stringappend_834_0,stringappend_835_0) =>
+                    let stringappend_836_0 = (string_drop stringappend_833_0 stringappend_835_0) in
+                    if ((case ((spc_matches_prefix stringappend_836_0)) of
+                        SOME (stringappend_837_0,stringappend_838_0) =>
+                         let stringappend_839_0 = (string_drop stringappend_836_0 stringappend_838_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_839_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_840_0,stringappend_841_0) =>
+                              let stringappend_842_0 =
+                                (string_drop stringappend_839_0 stringappend_841_0) in
+                              if ((case ((sep_matches_prefix stringappend_842_0)) of
+                                  SOME (stringappend_843_0,stringappend_844_0) =>
+                                   let stringappend_845_0 =
+                                     (string_drop stringappend_842_0 stringappend_844_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_845_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_846_0,stringappend_847_0) =>
+                                        let stringappend_848_0 =
+                                          (string_drop stringappend_845_0 stringappend_847_0) in
+                                        if ((case ((sep_matches_prefix stringappend_848_0)) of
+                                            SOME (stringappend_849_0,stringappend_850_0) =>
+                                             let stringappend_851_0 =
+                                               (string_drop stringappend_848_0 stringappend_850_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_851_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_852_0,stringappend_853_0) =>
+                                                  (case ((string_drop stringappend_851_0
+                                                            stringappend_853_0)) of
+                                                    "" => T
+                                                  | _ => F
+                                                  )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_833_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in
+     let (s, stringappend_835_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_833_0)) of
+         SOME (stringappend_834_0,stringappend_835_0) => (stringappend_834_0, stringappend_835_0)
+       )) in
+     let stringappend_836_0 = (string_drop stringappend_833_0 stringappend_835_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_836_0)) of
+        SOME (stringappend_837_0,stringappend_838_0) => (stringappend_837_0, stringappend_838_0)
+  ) of
+      (() , stringappend_838_0) =>
+  let stringappend_839_0 = (string_drop stringappend_836_0 stringappend_838_0) in
+  let (rd, stringappend_841_0) =
+      ((case ((reg_name_matches_prefix stringappend_839_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_840_0,stringappend_841_0) => (stringappend_840_0, stringappend_841_0)
+       )) in
+  let stringappend_842_0 = (string_drop stringappend_839_0 stringappend_841_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_842_0)) of
+        SOME (stringappend_843_0,stringappend_844_0) => (stringappend_843_0, stringappend_844_0)
+  ) of
+      (() , stringappend_844_0) =>
+  let stringappend_845_0 = (string_drop stringappend_842_0 stringappend_844_0) in
+  let (rs1, stringappend_847_0) =
+      ((case ((reg_name_matches_prefix stringappend_845_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_846_0,stringappend_847_0) => (stringappend_846_0, stringappend_847_0)
+       )) in
+  let stringappend_848_0 = (string_drop stringappend_845_0 stringappend_847_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_848_0)) of
+        SOME (stringappend_849_0,stringappend_850_0) => (stringappend_849_0, stringappend_850_0)
+  ) of
+      (() , stringappend_850_0) =>
+  let stringappend_851_0 = (string_drop stringappend_848_0 stringappend_850_0) in
+  let (rs2, stringappend_853_0) =
+      ((case ((reg_name_matches_prefix stringappend_851_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_852_0,stringappend_853_0) => (stringappend_852_0, stringappend_853_0)
+       )) in
+  (case ((string_drop stringappend_851_0 stringappend_853_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "mulw")) /\ (let stringappend_855_0 = (string_drop stringappend_541_0 ((string_length "mulw"))) in
+               if ((case ((spc_matches_prefix stringappend_855_0)) of
+                   SOME (stringappend_856_0,stringappend_857_0) =>
+                    let stringappend_858_0 = (string_drop stringappend_855_0 stringappend_857_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_858_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_859_0,stringappend_860_0) =>
+                         let stringappend_861_0 = (string_drop stringappend_858_0 stringappend_860_0) in
+                         if ((case ((sep_matches_prefix stringappend_861_0)) of
+                             SOME (stringappend_862_0,stringappend_863_0) =>
+                              let stringappend_864_0 =
+                                (string_drop stringappend_861_0 stringappend_863_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_864_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_865_0,stringappend_866_0) =>
+                                   let stringappend_867_0 =
+                                     (string_drop stringappend_864_0 stringappend_866_0) in
+                                   if ((case ((sep_matches_prefix stringappend_867_0)) of
+                                       SOME (stringappend_868_0,stringappend_869_0) =>
+                                        let stringappend_870_0 =
+                                          (string_drop stringappend_867_0 stringappend_869_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_870_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_871_0,stringappend_872_0) =>
+                                             (case ((string_drop stringappend_870_0
+                                                       stringappend_872_0)) of
+                                               "" => T
+                                             | _ => F
+                                             )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_855_0 = (string_drop stringappend_541_0 ((string_length "mulw"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_855_0)) of
+        SOME (stringappend_856_0,stringappend_857_0) => (stringappend_856_0, stringappend_857_0)
+  ) of
+      (() , stringappend_857_0) =>
+  let stringappend_858_0 = (string_drop stringappend_855_0 stringappend_857_0) in
+  let (rd, stringappend_860_0) =
+      ((case ((reg_name_matches_prefix stringappend_858_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_859_0,stringappend_860_0) => (stringappend_859_0, stringappend_860_0)
+       )) in
+  let stringappend_861_0 = (string_drop stringappend_858_0 stringappend_860_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_861_0)) of
+        SOME (stringappend_862_0,stringappend_863_0) => (stringappend_862_0, stringappend_863_0)
+  ) of
+      (() , stringappend_863_0) =>
+  let stringappend_864_0 = (string_drop stringappend_861_0 stringappend_863_0) in
+  let (rs1, stringappend_866_0) =
+      ((case ((reg_name_matches_prefix stringappend_864_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_865_0,stringappend_866_0) => (stringappend_865_0, stringappend_866_0)
+       )) in
+  let stringappend_867_0 = (string_drop stringappend_864_0 stringappend_866_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_867_0)) of
+        SOME (stringappend_868_0,stringappend_869_0) => (stringappend_868_0, stringappend_869_0)
+  ) of
+      (() , stringappend_869_0) =>
+  let stringappend_870_0 = (string_drop stringappend_867_0 stringappend_869_0) in
+  let (rs2, stringappend_872_0) =
+      ((case ((reg_name_matches_prefix stringappend_870_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_871_0,stringappend_872_0) => (stringappend_871_0, stringappend_872_0)
+       )) in
+  (case ((string_drop stringappend_870_0 stringappend_872_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "div")) /\ (let stringappend_874_0 = (string_drop stringappend_541_0 ((string_length "div"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_874_0)) of
+                   SOME (stringappend_875_0,stringappend_876_0) =>
+                    let stringappend_877_0 = (string_drop stringappend_874_0 stringappend_876_0) in
+                    if (((((string_startswith stringappend_877_0 "w")) /\ (let stringappend_878_0 =
+                             (string_drop stringappend_877_0 ((string_length "w"))) in
+                           if ((case ((spc_matches_prefix stringappend_878_0)) of
+                               SOME (stringappend_879_0,stringappend_880_0) =>
+                                let stringappend_881_0 =
+                                  (string_drop stringappend_878_0 stringappend_880_0) in
+                                if ((case ((reg_name_matches_prefix stringappend_881_0
+                                             :  (( 5 words$word # ii))option)) of
+                                    SOME (stringappend_882_0,stringappend_883_0) =>
+                                     let stringappend_884_0 =
+                                       (string_drop stringappend_881_0 stringappend_883_0) in
+                                     if ((case ((sep_matches_prefix stringappend_884_0)) of
+                                         SOME (stringappend_885_0,stringappend_886_0) =>
+                                          let stringappend_887_0 =
+                                            (string_drop stringappend_884_0 stringappend_886_0) in
+                                          if ((case ((reg_name_matches_prefix stringappend_887_0
+                                                       :  (( 5 words$word # ii))option)) of
+                                              SOME (stringappend_888_0,stringappend_889_0) =>
+                                               let stringappend_890_0 =
+                                                 (string_drop stringappend_887_0 stringappend_889_0) in
+                                               if ((case ((sep_matches_prefix stringappend_890_0)) of
+                                                   SOME (stringappend_891_0,stringappend_892_0) =>
+                                                    let stringappend_893_0 =
+                                                      (string_drop stringappend_890_0
+                                                        stringappend_892_0) in
+                                                    if ((case ((reg_name_matches_prefix
+                                                                  stringappend_893_0
+                                                                 :  (( 5 words$word # ii))option)) of
+                                                        SOME (stringappend_894_0,stringappend_895_0) =>
+                                                         (case ((string_drop stringappend_893_0
+                                                                   stringappend_895_0)) of
+                                                           "" => T
+                                                         | _ => F
+                                                         )
+                                                      | NONE => F
+                                                      )) then
+                                                      T
+                                                    else F
+                                                 | NONE => F
+                                                 )) then
+                                                 T
+                                               else F
+                                            | NONE => F
+                                            )) then
+                                            T
+                                          else F
+                                       | NONE => F
+                                       )) then
+                                       T
+                                     else F
+                                  | NONE => F
+                                  )) then
+                                  T
+                                else F
+                             | NONE => F
+                             )) then
+                             T
+                           else F)))) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_874_0 = (string_drop stringappend_541_0 ((string_length "div"))) in
+     let (s, stringappend_876_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_874_0)) of
+         SOME (stringappend_875_0,stringappend_876_0) => (stringappend_875_0, stringappend_876_0)
+       )) in
+     let stringappend_877_0 = (string_drop stringappend_874_0 stringappend_876_0) in
+     let stringappend_878_0 = (string_drop stringappend_877_0 ((string_length "w"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_878_0)) of
+        SOME (stringappend_879_0,stringappend_880_0) => (stringappend_879_0, stringappend_880_0)
+  ) of
+      (() , stringappend_880_0) =>
+  let stringappend_881_0 = (string_drop stringappend_878_0 stringappend_880_0) in
+  let (rd, stringappend_883_0) =
+      ((case ((reg_name_matches_prefix stringappend_881_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_882_0,stringappend_883_0) => (stringappend_882_0, stringappend_883_0)
+       )) in
+  let stringappend_884_0 = (string_drop stringappend_881_0 stringappend_883_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_884_0)) of
+        SOME (stringappend_885_0,stringappend_886_0) => (stringappend_885_0, stringappend_886_0)
+  ) of
+      (() , stringappend_886_0) =>
+  let stringappend_887_0 = (string_drop stringappend_884_0 stringappend_886_0) in
+  let (rs1, stringappend_889_0) =
+      ((case ((reg_name_matches_prefix stringappend_887_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_888_0,stringappend_889_0) => (stringappend_888_0, stringappend_889_0)
+       )) in
+  let stringappend_890_0 = (string_drop stringappend_887_0 stringappend_889_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_890_0)) of
+        SOME (stringappend_891_0,stringappend_892_0) => (stringappend_891_0, stringappend_892_0)
+  ) of
+      (() , stringappend_892_0) =>
+  let stringappend_893_0 = (string_drop stringappend_890_0 stringappend_892_0) in
+  let (rs2, stringappend_895_0) =
+      ((case ((reg_name_matches_prefix stringappend_893_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_894_0,stringappend_895_0) => (stringappend_894_0, stringappend_895_0)
+       )) in
+  (case ((string_drop stringappend_893_0 stringappend_895_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "rem")) /\ (let stringappend_897_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_897_0)) of
+                   SOME (stringappend_898_0,stringappend_899_0) =>
+                    let stringappend_900_0 = (string_drop stringappend_897_0 stringappend_899_0) in
+                    if (((((string_startswith stringappend_900_0 "w")) /\ (let stringappend_901_0 =
+                             (string_drop stringappend_900_0 ((string_length "w"))) in
+                           if ((case ((spc_matches_prefix stringappend_901_0)) of
+                               SOME (stringappend_902_0,stringappend_903_0) =>
+                                let stringappend_904_0 =
+                                  (string_drop stringappend_901_0 stringappend_903_0) in
+                                if ((case ((reg_name_matches_prefix stringappend_904_0
+                                             :  (( 5 words$word # ii))option)) of
+                                    SOME (stringappend_905_0,stringappend_906_0) =>
+                                     let stringappend_907_0 =
+                                       (string_drop stringappend_904_0 stringappend_906_0) in
+                                     if ((case ((sep_matches_prefix stringappend_907_0)) of
+                                         SOME (stringappend_908_0,stringappend_909_0) =>
+                                          let stringappend_910_0 =
+                                            (string_drop stringappend_907_0 stringappend_909_0) in
+                                          if ((case ((reg_name_matches_prefix stringappend_910_0
+                                                       :  (( 5 words$word # ii))option)) of
+                                              SOME (stringappend_911_0,stringappend_912_0) =>
+                                               let stringappend_913_0 =
+                                                 (string_drop stringappend_910_0 stringappend_912_0) in
+                                               if ((case ((sep_matches_prefix stringappend_913_0)) of
+                                                   SOME (stringappend_914_0,stringappend_915_0) =>
+                                                    let stringappend_916_0 =
+                                                      (string_drop stringappend_913_0
+                                                        stringappend_915_0) in
+                                                    if ((case ((reg_name_matches_prefix
+                                                                  stringappend_916_0
+                                                                 :  (( 5 words$word # ii))option)) of
+                                                        SOME (stringappend_917_0,stringappend_918_0) =>
+                                                         (case ((string_drop stringappend_916_0
+                                                                   stringappend_918_0)) of
+                                                           "" => T
+                                                         | _ => F
+                                                         )
+                                                      | NONE => F
+                                                      )) then
+                                                      T
+                                                    else F
+                                                 | NONE => F
+                                                 )) then
+                                                 T
+                                               else F
+                                            | NONE => F
+                                            )) then
+                                            T
+                                          else F
+                                       | NONE => F
+                                       )) then
+                                       T
+                                     else F
+                                  | NONE => F
+                                  )) then
+                                  T
+                                else F
+                             | NONE => F
+                             )) then
+                             T
+                           else F)))) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_897_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in
+     let (s, stringappend_899_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_897_0)) of
+         SOME (stringappend_898_0,stringappend_899_0) => (stringappend_898_0, stringappend_899_0)
+       )) in
+     let stringappend_900_0 = (string_drop stringappend_897_0 stringappend_899_0) in
+     let stringappend_901_0 = (string_drop stringappend_900_0 ((string_length "w"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_901_0)) of
+        SOME (stringappend_902_0,stringappend_903_0) => (stringappend_902_0, stringappend_903_0)
+  ) of
+      (() , stringappend_903_0) =>
+  let stringappend_904_0 = (string_drop stringappend_901_0 stringappend_903_0) in
+  let (rd, stringappend_906_0) =
+      ((case ((reg_name_matches_prefix stringappend_904_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_905_0,stringappend_906_0) => (stringappend_905_0, stringappend_906_0)
+       )) in
+  let stringappend_907_0 = (string_drop stringappend_904_0 stringappend_906_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_907_0)) of
+        SOME (stringappend_908_0,stringappend_909_0) => (stringappend_908_0, stringappend_909_0)
+  ) of
+      (() , stringappend_909_0) =>
+  let stringappend_910_0 = (string_drop stringappend_907_0 stringappend_909_0) in
+  let (rs1, stringappend_912_0) =
+      ((case ((reg_name_matches_prefix stringappend_910_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_911_0,stringappend_912_0) => (stringappend_911_0, stringappend_912_0)
+       )) in
+  let stringappend_913_0 = (string_drop stringappend_910_0 stringappend_912_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_913_0)) of
+        SOME (stringappend_914_0,stringappend_915_0) => (stringappend_914_0, stringappend_915_0)
+  ) of
+      (() , stringappend_915_0) =>
+  let stringappend_916_0 = (string_drop stringappend_913_0 stringappend_915_0) in
+  let (rs2, stringappend_918_0) =
+      ((case ((reg_name_matches_prefix stringappend_916_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_917_0,stringappend_918_0) => (stringappend_917_0, stringappend_918_0)
+       )) in
+  (case ((string_drop stringappend_916_0 stringappend_918_0)) of   "" => T )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_541_0 "fence")) /\ (let stringappend_920_0 = (string_drop stringappend_541_0 ((string_length "fence"))) in
+               if ((case ((spc_matches_prefix stringappend_920_0)) of
+                   SOME (stringappend_921_0,stringappend_922_0) =>
+                    let stringappend_923_0 = (string_drop stringappend_920_0 stringappend_922_0) in
+                    if ((case ((fence_bits_matches_prefix stringappend_923_0
+                                 :  (( 4 words$word # ii))option)) of
+                        SOME (stringappend_924_0,stringappend_925_0) =>
+                         let stringappend_926_0 = (string_drop stringappend_923_0 stringappend_925_0) in
+                         if ((case ((sep_matches_prefix stringappend_926_0)) of
+                             SOME (stringappend_927_0,stringappend_928_0) =>
+                              let stringappend_929_0 =
+                                (string_drop stringappend_926_0 stringappend_928_0) in
+                              if ((case ((fence_bits_matches_prefix stringappend_929_0
+                                           :  (( 4 words$word # ii))option)) of
+                                  SOME (stringappend_930_0,stringappend_931_0) =>
+                                   (case ((string_drop stringappend_929_0 stringappend_931_0)) of
+                                     "" => T
+                                   | _ => F
+                                   )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_920_0 = (string_drop stringappend_541_0 ((string_length "fence"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_920_0)) of
+        SOME (stringappend_921_0,stringappend_922_0) => (stringappend_921_0, stringappend_922_0)
+  ) of
+      (() , stringappend_922_0) =>
+  let stringappend_923_0 = (string_drop stringappend_920_0 stringappend_922_0) in
+  let (pred, stringappend_925_0) =
+      ((case ((fence_bits_matches_prefix stringappend_923_0 : (( 4 words$word # ii)) option)) of
+             SOME (stringappend_924_0,stringappend_925_0) => (stringappend_924_0, stringappend_925_0)
+       )) in
+  let stringappend_926_0 = (string_drop stringappend_923_0 stringappend_925_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_926_0)) of
+        SOME (stringappend_927_0,stringappend_928_0) => (stringappend_927_0, stringappend_928_0)
+  ) of
+      (() , stringappend_928_0) =>
+  let stringappend_929_0 = (string_drop stringappend_926_0 stringappend_928_0) in
+  let (succ, stringappend_931_0) =
+      ((case ((fence_bits_matches_prefix stringappend_929_0 : (( 4 words$word # ii)) option)) of
+             SOME (stringappend_930_0,stringappend_931_0) => (stringappend_930_0, stringappend_931_0)
+       )) in
+  (case ((string_drop stringappend_929_0 stringappend_931_0)) of   "" => T )
+  )
+  )
+   else
+     (case stringappend_541_0 of
+       "fence.i" => T
+     | "ecall" => T
+     | "mret" => T
+     | "sret" => T
+     | "ebreak" => T
+     | "wfi" => T
+     | stringappend_541_0 =>
+        if (((((string_startswith stringappend_541_0 "sfence.vma")) /\ (let stringappend_933_0 =
+                 (string_drop stringappend_541_0 ((string_length "sfence.vma"))) in
+               if ((case ((spc_matches_prefix stringappend_933_0)) of
+                   SOME (stringappend_934_0,stringappend_935_0) =>
+                    let stringappend_936_0 = (string_drop stringappend_933_0 stringappend_935_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_936_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_937_0,stringappend_938_0) =>
+                         let stringappend_939_0 = (string_drop stringappend_936_0 stringappend_938_0) in
+                         if ((case ((sep_matches_prefix stringappend_939_0)) of
+                             SOME (stringappend_940_0,stringappend_941_0) =>
+                              let stringappend_942_0 =
+                                (string_drop stringappend_939_0 stringappend_941_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_942_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_943_0,stringappend_944_0) =>
+                                   (case ((string_drop stringappend_942_0 stringappend_944_0)) of
+                                     "" => T
+                                   | _ => F
+                                   )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+          let stringappend_933_0 = (string_drop stringappend_541_0 ((string_length "sfence.vma"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_933_0)) of
+        SOME (stringappend_934_0,stringappend_935_0) =>
+  (stringappend_934_0, stringappend_935_0)
+  ) of
+      (() , stringappend_935_0) =>
+  let stringappend_936_0 = (string_drop stringappend_933_0 stringappend_935_0) in
+  let (rs1, stringappend_938_0) =
+      ((case ((reg_name_matches_prefix stringappend_936_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_937_0,stringappend_938_0) =>
+       (stringappend_937_0, stringappend_938_0)
+       )) in
+  let stringappend_939_0 = (string_drop stringappend_936_0 stringappend_938_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_939_0)) of
+        SOME (stringappend_940_0,stringappend_941_0) =>
+  (stringappend_940_0, stringappend_941_0)
+  ) of
+      (() , stringappend_941_0) =>
+  let stringappend_942_0 = (string_drop stringappend_939_0 stringappend_941_0) in
+  let (rs2, stringappend_944_0) =
+      ((case ((reg_name_matches_prefix stringappend_942_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_943_0,stringappend_944_0) =>
+       (stringappend_943_0, stringappend_944_0)
+       )) in
+  (case ((string_drop stringappend_942_0 stringappend_944_0)) of   "" => T )
+  )
+  )
+        else if (((((string_startswith stringappend_541_0 "lr.")) /\ (let stringappend_946_0 = (string_drop stringappend_541_0 ((string_length "lr."))) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_946_0)) of
+                        SOME (stringappend_947_0,stringappend_948_0) =>
+                         let stringappend_949_0 = (string_drop stringappend_946_0 stringappend_948_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_949_0)) of
+                             SOME (stringappend_950_0,stringappend_951_0) =>
+                              let stringappend_952_0 =
+                                (string_drop stringappend_949_0 stringappend_951_0) in
+                              if ((case ((size_mnemonic_matches_prefix stringappend_952_0)) of
+                                  SOME (stringappend_953_0,stringappend_954_0) =>
+                                   let stringappend_955_0 =
+                                     (string_drop stringappend_952_0 stringappend_954_0) in
+                                   if ((case ((spc_matches_prefix stringappend_955_0)) of
+                                       SOME (stringappend_956_0,stringappend_957_0) =>
+                                        let stringappend_958_0 =
+                                          (string_drop stringappend_955_0 stringappend_957_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_958_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_959_0,stringappend_960_0) =>
+                                             let stringappend_961_0 =
+                                               (string_drop stringappend_958_0 stringappend_960_0) in
+                                             if ((case ((sep_matches_prefix stringappend_961_0)) of
+                                                 SOME (stringappend_962_0,stringappend_963_0) =>
+                                                  let stringappend_964_0 =
+                                                    (string_drop stringappend_961_0
+                                                      stringappend_963_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_964_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_965_0,stringappend_966_0) =>
+                                                       (case ((string_drop stringappend_964_0
+                                                                 stringappend_966_0)) of
+                                                         "" => T
+                                                       | _ => F
+                                                       )
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+          let stringappend_946_0 = (string_drop stringappend_541_0 ((string_length "lr."))) in
+          let (aq, stringappend_948_0) =
+            ((case ((maybe_aq_matches_prefix stringappend_946_0)) of
+              SOME (stringappend_947_0,stringappend_948_0) =>
+               (stringappend_947_0, stringappend_948_0)
+            )) in
+          let stringappend_949_0 = (string_drop stringappend_946_0 stringappend_948_0) in
+          let (rl, stringappend_951_0) =
+            ((case ((maybe_rl_matches_prefix stringappend_949_0)) of
+              SOME (stringappend_950_0,stringappend_951_0) =>
+               (stringappend_950_0, stringappend_951_0)
+            )) in
+          let stringappend_952_0 = (string_drop stringappend_949_0 stringappend_951_0) in
+          let (size1, stringappend_954_0) =
+            ((case ((size_mnemonic_matches_prefix stringappend_952_0)) of
+              SOME (stringappend_953_0,stringappend_954_0) =>
+               (stringappend_953_0, stringappend_954_0)
+            )) in
+          let stringappend_955_0 = (string_drop stringappend_952_0 stringappend_954_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_955_0)) of
+        SOME (stringappend_956_0,stringappend_957_0) =>
+  (stringappend_956_0, stringappend_957_0)
+  ) of
+      (() , stringappend_957_0) =>
+  let stringappend_958_0 = (string_drop stringappend_955_0 stringappend_957_0) in
+  let (rd, stringappend_960_0) =
+      ((case ((reg_name_matches_prefix stringappend_958_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_959_0,stringappend_960_0) =>
+       (stringappend_959_0, stringappend_960_0)
+       )) in
+  let stringappend_961_0 = (string_drop stringappend_958_0 stringappend_960_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_961_0)) of
+        SOME (stringappend_962_0,stringappend_963_0) =>
+  (stringappend_962_0, stringappend_963_0)
+  ) of
+      (() , stringappend_963_0) =>
+  let stringappend_964_0 = (string_drop stringappend_961_0 stringappend_963_0) in
+  let (rs1, stringappend_966_0) =
+      ((case ((reg_name_matches_prefix stringappend_964_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_965_0,stringappend_966_0) =>
+       (stringappend_965_0, stringappend_966_0)
+       )) in
+  (case ((string_drop stringappend_964_0 stringappend_966_0)) of   "" => T )
+  )
+  )
+        else if (((((string_startswith stringappend_541_0 "sc.")) /\ (let stringappend_968_0 = (string_drop stringappend_541_0 ((string_length "sc."))) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_968_0)) of
+                        SOME (stringappend_969_0,stringappend_970_0) =>
+                         let stringappend_971_0 = (string_drop stringappend_968_0 stringappend_970_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_971_0)) of
+                             SOME (stringappend_972_0,stringappend_973_0) =>
+                              let stringappend_974_0 =
+                                (string_drop stringappend_971_0 stringappend_973_0) in
+                              if ((case ((size_mnemonic_matches_prefix stringappend_974_0)) of
+                                  SOME (stringappend_975_0,stringappend_976_0) =>
+                                   let stringappend_977_0 =
+                                     (string_drop stringappend_974_0 stringappend_976_0) in
+                                   if ((case ((spc_matches_prefix stringappend_977_0)) of
+                                       SOME (stringappend_978_0,stringappend_979_0) =>
+                                        let stringappend_980_0 =
+                                          (string_drop stringappend_977_0 stringappend_979_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_980_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_981_0,stringappend_982_0) =>
+                                             let stringappend_983_0 =
+                                               (string_drop stringappend_980_0 stringappend_982_0) in
+                                             if ((case ((sep_matches_prefix stringappend_983_0)) of
+                                                 SOME (stringappend_984_0,stringappend_985_0) =>
+                                                  let stringappend_986_0 =
+                                                    (string_drop stringappend_983_0
+                                                      stringappend_985_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_986_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_987_0,stringappend_988_0) =>
+                                                       let stringappend_989_0 =
+                                                         (string_drop stringappend_986_0
+                                                           stringappend_988_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_989_0)) of
+                                                           SOME
+                                                           (stringappend_990_0,stringappend_991_0) =>
+                                                            let stringappend_992_0 =
+                                                              (string_drop stringappend_989_0
+                                                                stringappend_991_0) in
+                                                            if ((case ((reg_name_matches_prefix
+                                                                          stringappend_992_0
+                                                                         :  (( 5 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_993_0,stringappend_994_0) =>
+                                                                 (case ((string_drop
+                                                                           stringappend_992_0
+                                                                           stringappend_994_0)) of
+                                                                   "" => T
+                                                                 | _ => F
+                                                                 )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+          let stringappend_968_0 = (string_drop stringappend_541_0 ((string_length "sc."))) in
+          let (aq, stringappend_970_0) =
+            ((case ((maybe_aq_matches_prefix stringappend_968_0)) of
+              SOME (stringappend_969_0,stringappend_970_0) =>
+               (stringappend_969_0, stringappend_970_0)
+            )) in
+          let stringappend_971_0 = (string_drop stringappend_968_0 stringappend_970_0) in
+          let (rl, stringappend_973_0) =
+            ((case ((maybe_rl_matches_prefix stringappend_971_0)) of
+              SOME (stringappend_972_0,stringappend_973_0) =>
+               (stringappend_972_0, stringappend_973_0)
+            )) in
+          let stringappend_974_0 = (string_drop stringappend_971_0 stringappend_973_0) in
+          let (size1, stringappend_976_0) =
+            ((case ((size_mnemonic_matches_prefix stringappend_974_0)) of
+              SOME (stringappend_975_0,stringappend_976_0) =>
+               (stringappend_975_0, stringappend_976_0)
+            )) in
+          let stringappend_977_0 = (string_drop stringappend_974_0 stringappend_976_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_977_0)) of
+        SOME (stringappend_978_0,stringappend_979_0) =>
+  (stringappend_978_0, stringappend_979_0)
+  ) of
+      (() , stringappend_979_0) =>
+  let stringappend_980_0 = (string_drop stringappend_977_0 stringappend_979_0) in
+  let (rd, stringappend_982_0) =
+      ((case ((reg_name_matches_prefix stringappend_980_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_981_0,stringappend_982_0) =>
+       (stringappend_981_0, stringappend_982_0)
+       )) in
+  let stringappend_983_0 = (string_drop stringappend_980_0 stringappend_982_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_983_0)) of
+        SOME (stringappend_984_0,stringappend_985_0) =>
+  (stringappend_984_0, stringappend_985_0)
+  ) of
+      (() , stringappend_985_0) =>
+  let stringappend_986_0 = (string_drop stringappend_983_0 stringappend_985_0) in
+  let (rs1, stringappend_988_0) =
+      ((case ((reg_name_matches_prefix stringappend_986_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_987_0,stringappend_988_0) =>
+       (stringappend_987_0, stringappend_988_0)
+       )) in
+  let stringappend_989_0 = (string_drop stringappend_986_0 stringappend_988_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_989_0)) of
+        SOME (stringappend_990_0,stringappend_991_0) =>
+  (stringappend_990_0, stringappend_991_0)
+  ) of
+      (() , stringappend_991_0) =>
+  let stringappend_992_0 = (string_drop stringappend_989_0 stringappend_991_0) in
+  let (rs2, stringappend_994_0) =
+      ((case ((reg_name_matches_prefix stringappend_992_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_993_0,stringappend_994_0) =>
+       (stringappend_993_0, stringappend_994_0)
+       )) in
+  (case ((string_drop stringappend_992_0 stringappend_994_0)) of   "" => T )
+  )
+  )
+  )
+        else if ((case ((amo_mnemonic_matches_prefix stringappend_541_0)) of
+            SOME (stringappend_996_0,stringappend_997_0) =>
+             let stringappend_998_0 = (string_drop stringappend_541_0 stringappend_997_0) in
+             if (((((string_startswith stringappend_998_0 ".")) /\ (let stringappend_999_0 = (string_drop stringappend_998_0 ((string_length "."))) in
+                    if ((case ((size_mnemonic_matches_prefix stringappend_999_0)) of
+                        SOME (stringappend_1000_0,stringappend_1001_0) =>
+                         let stringappend_1002_0 =
+                           (string_drop stringappend_999_0 stringappend_1001_0) in
+                         if ((case ((maybe_aq_matches_prefix stringappend_1002_0)) of
+                             SOME (stringappend_1003_0,stringappend_1004_0) =>
+                              let stringappend_1005_0 =
+                                (string_drop stringappend_1002_0 stringappend_1004_0) in
+                              if ((case ((maybe_rl_matches_prefix stringappend_1005_0)) of
+                                  SOME (stringappend_1006_0,stringappend_1007_0) =>
+                                   let stringappend_1008_0 =
+                                     (string_drop stringappend_1005_0 stringappend_1007_0) in
+                                   if ((case ((spc_matches_prefix stringappend_1008_0)) of
+                                       SOME (stringappend_1009_0,stringappend_1010_0) =>
+                                        let stringappend_1011_0 =
+                                          (string_drop stringappend_1008_0 stringappend_1010_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_1011_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_1012_0,stringappend_1013_0) =>
+                                             let stringappend_1014_0 =
+                                               (string_drop stringappend_1011_0 stringappend_1013_0) in
+                                             if ((case ((sep_matches_prefix stringappend_1014_0)) of
+                                                 SOME (stringappend_1015_0,stringappend_1016_0) =>
+                                                  let stringappend_1017_0 =
+                                                    (string_drop stringappend_1014_0
+                                                      stringappend_1016_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_1017_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_1018_0,stringappend_1019_0) =>
+                                                       let stringappend_1020_0 =
+                                                         (string_drop stringappend_1017_0
+                                                           stringappend_1019_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_1020_0)) of
+                                                           SOME
+                                                           (stringappend_1021_0,stringappend_1022_0) =>
+                                                            let stringappend_1023_0 =
+                                                              (string_drop stringappend_1020_0
+                                                                stringappend_1022_0) in
+                                                            if ((case ((reg_name_matches_prefix
+                                                                          stringappend_1023_0
+                                                                         :  (( 5 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_1024_0,stringappend_1025_0) =>
+                                                                 (case ((string_drop
+                                                                           stringappend_1023_0
+                                                                           stringappend_1025_0)) of
+                                                                   "" => T
+                                                                 | _ => F
+                                                                 )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+               T
+             else F
+          | NONE => F
+          )) then
+          let (op, stringappend_997_0) =
+            ((case ((amo_mnemonic_matches_prefix stringappend_541_0)) of
+              SOME (stringappend_996_0,stringappend_997_0) =>
+               (stringappend_996_0, stringappend_997_0)
+            )) in
+          let stringappend_998_0 = (string_drop stringappend_541_0 stringappend_997_0) in
+          let stringappend_999_0 = (string_drop stringappend_998_0 ((string_length "."))) in
+          let (width, stringappend_1001_0) =
+            ((case ((size_mnemonic_matches_prefix stringappend_999_0)) of
+              SOME (stringappend_1000_0,stringappend_1001_0) =>
+               (stringappend_1000_0, stringappend_1001_0)
+            )) in
+          let stringappend_1002_0 = (string_drop stringappend_999_0 stringappend_1001_0) in
+          let (aq, stringappend_1004_0) =
+            ((case ((maybe_aq_matches_prefix stringappend_1002_0)) of
+              SOME (stringappend_1003_0,stringappend_1004_0) =>
+               (stringappend_1003_0, stringappend_1004_0)
+            )) in
+          let stringappend_1005_0 = (string_drop stringappend_1002_0 stringappend_1004_0) in
+          let (rl, stringappend_1007_0) =
+            ((case ((maybe_rl_matches_prefix stringappend_1005_0)) of
+              SOME (stringappend_1006_0,stringappend_1007_0) =>
+               (stringappend_1006_0, stringappend_1007_0)
+            )) in
+          let stringappend_1008_0 = (string_drop stringappend_1005_0 stringappend_1007_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1008_0)) of
+        SOME (stringappend_1009_0,stringappend_1010_0) =>
+  (stringappend_1009_0, stringappend_1010_0)
+  ) of
+      (() , stringappend_1010_0) =>
+  let stringappend_1011_0 = (string_drop stringappend_1008_0
+                               stringappend_1010_0) in
+  let (rd, stringappend_1013_0) =
+      ((case ((reg_name_matches_prefix stringappend_1011_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1012_0,stringappend_1013_0) =>
+       (stringappend_1012_0, stringappend_1013_0)
+       )) in
+  let stringappend_1014_0 = (string_drop stringappend_1011_0
+                               stringappend_1013_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1014_0)) of
+        SOME (stringappend_1015_0,stringappend_1016_0) =>
+  (stringappend_1015_0, stringappend_1016_0)
+  ) of
+      (() , stringappend_1016_0) =>
+  let stringappend_1017_0 = (string_drop stringappend_1014_0
+                               stringappend_1016_0) in
+  let (rs1, stringappend_1019_0) =
+      ((case ((reg_name_matches_prefix stringappend_1017_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1018_0,stringappend_1019_0) =>
+       (stringappend_1018_0, stringappend_1019_0)
+       )) in
+  let stringappend_1020_0 = (string_drop stringappend_1017_0
+                               stringappend_1019_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1020_0)) of
+        SOME (stringappend_1021_0,stringappend_1022_0) =>
+  (stringappend_1021_0, stringappend_1022_0)
+  ) of
+      (() , stringappend_1022_0) =>
+  let stringappend_1023_0 = (string_drop stringappend_1020_0
+                               stringappend_1022_0) in
+  let (rs2, stringappend_1025_0) =
+      ((case ((reg_name_matches_prefix stringappend_1023_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1024_0,stringappend_1025_0) =>
+       (stringappend_1024_0, stringappend_1025_0)
+       )) in
+  (case ((string_drop stringappend_1023_0 stringappend_1025_0)) of
+        "" => T
+  )
+  )
+  )
+  )
+        else if ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of
+            SOME (stringappend_1027_0,stringappend_1028_0) =>
+             let stringappend_1029_0 = (string_drop stringappend_541_0 stringappend_1028_0) in
+             if (((((string_startswith stringappend_1029_0 "i")) /\ (let stringappend_1030_0 = (string_drop stringappend_1029_0 ((string_length "i"))) in
+                    if ((case ((spc_matches_prefix stringappend_1030_0)) of
+                        SOME (stringappend_1031_0,stringappend_1032_0) =>
+                         let stringappend_1033_0 =
+                           (string_drop stringappend_1030_0 stringappend_1032_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_1033_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_1034_0,stringappend_1035_0) =>
+                              let stringappend_1036_0 =
+                                (string_drop stringappend_1033_0 stringappend_1035_0) in
+                              if ((case ((sep_matches_prefix stringappend_1036_0)) of
+                                  SOME (stringappend_1037_0,stringappend_1038_0) =>
+                                   let stringappend_1039_0 =
+                                     (string_drop stringappend_1036_0 stringappend_1038_0) in
+                                   if ((case ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1039_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_1040_0,stringappend_1041_0) =>
+                                        let stringappend_1042_0 =
+                                          (string_drop stringappend_1039_0 stringappend_1041_0) in
+                                        if ((case ((sep_matches_prefix stringappend_1042_0)) of
+                                            SOME (stringappend_1043_0,stringappend_1044_0) =>
+                                             let stringappend_1045_0 =
+                                               (string_drop stringappend_1042_0 stringappend_1044_0) in
+                                             if ((case ((csr_name_map_matches_prefix
+                                                           stringappend_1045_0
+                                                          :  (( 12 words$word # ii))option)) of
+                                                 SOME (stringappend_1046_0,stringappend_1047_0) =>
+                                                  (case ((string_drop stringappend_1045_0
+                                                            stringappend_1047_0)) of
+                                                    "" => T
+                                                  | _ => F
+                                                  )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+               T
+             else F
+          | NONE => F
+          )) then
+          let (op, stringappend_1028_0) =
+            ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of
+              SOME (stringappend_1027_0,stringappend_1028_0) =>
+               (stringappend_1027_0, stringappend_1028_0)
+            )) in
+          let stringappend_1029_0 = (string_drop stringappend_541_0 stringappend_1028_0) in
+          let stringappend_1030_0 = (string_drop stringappend_1029_0 ((string_length "i"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1030_0)) of
+        SOME (stringappend_1031_0,stringappend_1032_0) =>
+  (stringappend_1031_0, stringappend_1032_0)
+  ) of
+      (() , stringappend_1032_0) =>
+  let stringappend_1033_0 = (string_drop stringappend_1030_0
+                               stringappend_1032_0) in
+  let (rd, stringappend_1035_0) =
+      ((case ((reg_name_matches_prefix stringappend_1033_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1034_0,stringappend_1035_0) =>
+       (stringappend_1034_0, stringappend_1035_0)
+       )) in
+  let stringappend_1036_0 = (string_drop stringappend_1033_0
+                               stringappend_1035_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1036_0)) of
+        SOME (stringappend_1037_0,stringappend_1038_0) =>
+  (stringappend_1037_0, stringappend_1038_0)
+  ) of
+      (() , stringappend_1038_0) =>
+  let stringappend_1039_0 = (string_drop stringappend_1036_0
+                               stringappend_1038_0) in
+  let (rs1, stringappend_1041_0) =
+      ((case ((hex_bits_5_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1039_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1040_0,stringappend_1041_0) =>
+       (stringappend_1040_0, stringappend_1041_0)
+       )) in
+  let stringappend_1042_0 = (string_drop stringappend_1039_0
+                               stringappend_1041_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1042_0)) of
+        SOME (stringappend_1043_0,stringappend_1044_0) =>
+  (stringappend_1043_0, stringappend_1044_0)
+  ) of
+      (() , stringappend_1044_0) =>
+  let stringappend_1045_0 = (string_drop stringappend_1042_0
+                               stringappend_1044_0) in
+  let (csr, stringappend_1047_0) =
+      ((case ((csr_name_map_matches_prefix stringappend_1045_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1046_0,stringappend_1047_0) =>
+       (stringappend_1046_0, stringappend_1047_0)
+       )) in
+  (case ((string_drop stringappend_1045_0 stringappend_1047_0)) of
+        "" => T
+  )
+  )
+  )
+  )
+        else if ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of
+            SOME (stringappend_1049_0,stringappend_1050_0) =>
+             let stringappend_1051_0 = (string_drop stringappend_541_0 stringappend_1050_0) in
+             if ((case ((spc_matches_prefix stringappend_1051_0)) of
+                 SOME (stringappend_1052_0,stringappend_1053_0) =>
+                  let stringappend_1054_0 = (string_drop stringappend_1051_0 stringappend_1053_0) in
+                  if ((case ((reg_name_matches_prefix stringappend_1054_0
+                               :  (( 5 words$word # ii))option)) of
+                      SOME (stringappend_1055_0,stringappend_1056_0) =>
+                       let stringappend_1057_0 = (string_drop stringappend_1054_0 stringappend_1056_0) in
+                       if ((case ((sep_matches_prefix stringappend_1057_0)) of
+                           SOME (stringappend_1058_0,stringappend_1059_0) =>
+                            let stringappend_1060_0 =
+                              (string_drop stringappend_1057_0 stringappend_1059_0) in
+                            if ((case ((reg_name_matches_prefix stringappend_1060_0
+                                         :  (( 5 words$word # ii))option)) of
+                                SOME (stringappend_1061_0,stringappend_1062_0) =>
+                                 let stringappend_1063_0 =
+                                   (string_drop stringappend_1060_0 stringappend_1062_0) in
+                                 if ((case ((sep_matches_prefix stringappend_1063_0)) of
+                                     SOME (stringappend_1064_0,stringappend_1065_0) =>
+                                      let stringappend_1066_0 =
+                                        (string_drop stringappend_1063_0 stringappend_1065_0) in
+                                      if ((case ((csr_name_map_matches_prefix stringappend_1066_0
+                                                   :  (( 12 words$word # ii))option)) of
+                                          SOME (stringappend_1067_0,stringappend_1068_0) =>
+                                           (case ((string_drop stringappend_1066_0
+                                                     stringappend_1068_0)) of
+                                             "" => T
+                                           | _ => F
+                                           )
+                                        | NONE => F
+                                        )) then
+                                        T
+                                      else F
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          let (op, stringappend_1050_0) =
+            ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of
+              SOME (stringappend_1049_0,stringappend_1050_0) =>
+               (stringappend_1049_0, stringappend_1050_0)
+            )) in
+          let stringappend_1051_0 = (string_drop stringappend_541_0 stringappend_1050_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1051_0)) of
+        SOME (stringappend_1052_0,stringappend_1053_0) =>
+  (stringappend_1052_0, stringappend_1053_0)
+  ) of
+      (() , stringappend_1053_0) =>
+  let stringappend_1054_0 = (string_drop stringappend_1051_0
+                               stringappend_1053_0) in
+  let (rd, stringappend_1056_0) =
+      ((case ((reg_name_matches_prefix stringappend_1054_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1055_0,stringappend_1056_0) =>
+       (stringappend_1055_0, stringappend_1056_0)
+       )) in
+  let stringappend_1057_0 = (string_drop stringappend_1054_0
+                               stringappend_1056_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1057_0)) of
+        SOME (stringappend_1058_0,stringappend_1059_0) =>
+  (stringappend_1058_0, stringappend_1059_0)
+  ) of
+      (() , stringappend_1059_0) =>
+  let stringappend_1060_0 = (string_drop stringappend_1057_0
+                               stringappend_1059_0) in
+  let (rs1, stringappend_1062_0) =
+      ((case ((reg_name_matches_prefix stringappend_1060_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_1061_0,stringappend_1062_0) =>
+       (stringappend_1061_0, stringappend_1062_0)
+       )) in
+  let stringappend_1063_0 = (string_drop stringappend_1060_0
+                               stringappend_1062_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_1063_0)) of
+        SOME (stringappend_1064_0,stringappend_1065_0) =>
+  (stringappend_1064_0, stringappend_1065_0)
+  ) of
+      (() , stringappend_1065_0) =>
+  let stringappend_1066_0 = (string_drop stringappend_1063_0
+                               stringappend_1065_0) in
+  let (csr, stringappend_1068_0) =
+      ((case ((csr_name_map_matches_prefix stringappend_1066_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_1067_0,stringappend_1068_0) =>
+       (stringappend_1067_0, stringappend_1068_0)
+       )) in
+  (case ((string_drop stringappend_1066_0 stringappend_1068_0)) of
+        "" => T
+  )
+  )
+  )
+  )
+        else if (((((string_startswith stringappend_541_0 "illegal")) /\ (let stringappend_1070_0 =
+                      (string_drop stringappend_541_0 ((string_length "illegal"))) in
+                    if ((case ((spc_matches_prefix stringappend_1070_0)) of
+                        SOME (stringappend_1071_0,stringappend_1072_0) =>
+                         let stringappend_1073_0 =
+                           (string_drop stringappend_1070_0 stringappend_1072_0) in
+                         if ((case ((hex_bits_32_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1073_0
+                                      :  (( 32 words$word # ii))option)) of
+                             SOME (stringappend_1074_0,stringappend_1075_0) =>
+                              (case ((string_drop stringappend_1073_0 stringappend_1075_0)) of
+                                "" => T
+                              | _ => F
+                              )
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F)))) then
+          let stringappend_1070_0 = (string_drop stringappend_541_0 ((string_length "illegal"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_1070_0)) of
+        SOME (stringappend_1071_0,stringappend_1072_0) =>
+  (stringappend_1071_0, stringappend_1072_0)
+  ) of
+      (() , stringappend_1072_0) =>
+  let stringappend_1073_0 = (string_drop stringappend_1070_0
+                               stringappend_1072_0) in
+  let (s, stringappend_1075_0) =
+      ((case ((hex_bits_32_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_1073_0 : (( 32 words$word # ii)) option)) of
+             SOME (stringappend_1074_0,stringappend_1075_0) =>
+       (stringappend_1074_0, stringappend_1075_0)
+       )) in
+  (case ((string_drop stringappend_1073_0 stringappend_1075_0)) of
+        "" => T
+  )
+  )
+        else F
+     )))`;
+
+
+(*val assembly_matches_prefix : string -> maybe ((ast * ii))*)
+
+val _ = Define `
+ ((assembly_matches_prefix:string ->(ast#int)option) arg_=
+    (let stringappend_0_0 = arg_ in
+   if ((case ((utype_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_1_0,stringappend_2_0) =>
+        let stringappend_3_0 = (string_drop stringappend_0_0 stringappend_2_0) in
+        if ((case ((spc_matches_prefix stringappend_3_0)) of
+            SOME (stringappend_4_0,stringappend_5_0) =>
+             let stringappend_6_0 = (string_drop stringappend_3_0 stringappend_5_0) in
+             if ((case ((reg_name_matches_prefix stringappend_6_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_7_0,stringappend_8_0) =>
+                  let stringappend_9_0 = (string_drop stringappend_6_0 stringappend_8_0) in
+                  if ((case ((sep_matches_prefix stringappend_9_0)) of
+                      SOME (stringappend_10_0,stringappend_11_0) =>
+                       let stringappend_12_0 = (string_drop stringappend_9_0 stringappend_11_0) in
+                       if ((case ((hex_bits_20_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_12_0
+                                    :  (( 20 words$word # ii))option)) of
+                           SOME (stringappend_13_0,stringappend_14_0) => 
+  (case ((string_drop stringappend_12_0 stringappend_14_0)) of   s_ => T )
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_2_0) =
+       ((case ((utype_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_1_0,stringappend_2_0) => (stringappend_1_0, stringappend_2_0)
+       )) in
+     let stringappend_3_0 = (string_drop stringappend_0_0 stringappend_2_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_3_0)) of
+        SOME (stringappend_4_0,stringappend_5_0) => (stringappend_4_0, stringappend_5_0)
+  ) of
+      (() , stringappend_5_0) =>
+  let stringappend_6_0 = (string_drop stringappend_3_0 stringappend_5_0) in
+  let (rd, stringappend_8_0) =
+      ((case ((reg_name_matches_prefix stringappend_6_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_7_0,stringappend_8_0) => (stringappend_7_0, stringappend_8_0)
+       )) in
+  let stringappend_9_0 = (string_drop stringappend_6_0 stringappend_8_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_9_0)) of
+        SOME (stringappend_10_0,stringappend_11_0) => (stringappend_10_0, stringappend_11_0)
+  ) of
+      (() , stringappend_11_0) =>
+  let stringappend_12_0 = (string_drop stringappend_9_0 stringappend_11_0) in
+  let (imm, stringappend_14_0) =
+      ((case ((hex_bits_20_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_12_0 : (( 20 words$word # ii)) option)) of
+             SOME (stringappend_13_0,stringappend_14_0) => (stringappend_13_0, stringappend_14_0)
+       )) in
+  (case ((string_drop stringappend_12_0 stringappend_14_0)) of
+        s_ => SOME
+                (UTYPE (imm,rd,op), ((string_length arg_)) -
+                                      ((string_length s_)))
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "jal")) /\ (let stringappend_16_0 = (string_drop stringappend_0_0 ((string_length "jal"))) in
+               if ((case ((spc_matches_prefix stringappend_16_0)) of
+                   SOME (stringappend_17_0,stringappend_18_0) =>
+                    let stringappend_19_0 = (string_drop stringappend_16_0 stringappend_18_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_19_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_20_0,stringappend_21_0) =>
+                         let stringappend_22_0 = (string_drop stringappend_19_0 stringappend_21_0) in
+                         if ((case ((sep_matches_prefix stringappend_22_0)) of
+                             SOME (stringappend_23_0,stringappend_24_0) =>
+                              let stringappend_25_0 =
+                                (string_drop stringappend_22_0 stringappend_24_0) in
+                              if ((case ((hex_bits_21_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_25_0
+                                           :  (( 21 words$word # ii))option)) of
+                                  SOME (stringappend_26_0,stringappend_27_0) => 
+  (case ((string_drop stringappend_25_0 stringappend_27_0)) of   s_ => T )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_16_0 = (string_drop stringappend_0_0 ((string_length "jal"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_16_0)) of
+        SOME (stringappend_17_0,stringappend_18_0) => (stringappend_17_0, stringappend_18_0)
+  ) of
+      (() , stringappend_18_0) =>
+  let stringappend_19_0 = (string_drop stringappend_16_0 stringappend_18_0) in
+  let (rd, stringappend_21_0) =
+      ((case ((reg_name_matches_prefix stringappend_19_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_20_0,stringappend_21_0) => (stringappend_20_0, stringappend_21_0)
+       )) in
+  let stringappend_22_0 = (string_drop stringappend_19_0 stringappend_21_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_22_0)) of
+        SOME (stringappend_23_0,stringappend_24_0) => (stringappend_23_0, stringappend_24_0)
+  ) of
+      (() , stringappend_24_0) =>
+  let stringappend_25_0 = (string_drop stringappend_22_0 stringappend_24_0) in
+  let (imm, stringappend_27_0) =
+      ((case ((hex_bits_21_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_25_0 : (( 21 words$word # ii)) option)) of
+             SOME (stringappend_26_0,stringappend_27_0) => (stringappend_26_0, stringappend_27_0)
+       )) in
+  (case ((string_drop stringappend_25_0 stringappend_27_0)) of
+        s_ => SOME
+                (RISCV_JAL (imm,rd), ((string_length arg_)) -
+                                       ((string_length s_)))
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "jalr")) /\ (let stringappend_29_0 = (string_drop stringappend_0_0 ((string_length "jalr"))) in
+               if ((case ((spc_matches_prefix stringappend_29_0)) of
+                   SOME (stringappend_30_0,stringappend_31_0) =>
+                    let stringappend_32_0 = (string_drop stringappend_29_0 stringappend_31_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_32_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_33_0,stringappend_34_0) =>
+                         let stringappend_35_0 = (string_drop stringappend_32_0 stringappend_34_0) in
+                         if ((case ((sep_matches_prefix stringappend_35_0)) of
+                             SOME (stringappend_36_0,stringappend_37_0) =>
+                              let stringappend_38_0 =
+                                (string_drop stringappend_35_0 stringappend_37_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_38_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_39_0,stringappend_40_0) =>
+                                   let stringappend_41_0 =
+                                     (string_drop stringappend_38_0 stringappend_40_0) in
+                                   if ((case ((sep_matches_prefix stringappend_41_0)) of
+                                       SOME (stringappend_42_0,stringappend_43_0) =>
+                                        let stringappend_44_0 =
+                                          (string_drop stringappend_41_0 stringappend_43_0) in
+                                        if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_44_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_45_0,stringappend_46_0) => 
+  (case ((string_drop stringappend_44_0 stringappend_46_0)) of   s_ => T )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_29_0 = (string_drop stringappend_0_0 ((string_length "jalr"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_29_0)) of
+        SOME (stringappend_30_0,stringappend_31_0) => (stringappend_30_0, stringappend_31_0)
+  ) of
+      (() , stringappend_31_0) =>
+  let stringappend_32_0 = (string_drop stringappend_29_0 stringappend_31_0) in
+  let (rd, stringappend_34_0) =
+      ((case ((reg_name_matches_prefix stringappend_32_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_33_0,stringappend_34_0) => (stringappend_33_0, stringappend_34_0)
+       )) in
+  let stringappend_35_0 = (string_drop stringappend_32_0 stringappend_34_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_35_0)) of
+        SOME (stringappend_36_0,stringappend_37_0) => (stringappend_36_0, stringappend_37_0)
+  ) of
+      (() , stringappend_37_0) =>
+  let stringappend_38_0 = (string_drop stringappend_35_0 stringappend_37_0) in
+  let (rs1, stringappend_40_0) =
+      ((case ((reg_name_matches_prefix stringappend_38_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_39_0,stringappend_40_0) => (stringappend_39_0, stringappend_40_0)
+       )) in
+  let stringappend_41_0 = (string_drop stringappend_38_0 stringappend_40_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_41_0)) of
+        SOME (stringappend_42_0,stringappend_43_0) => (stringappend_42_0, stringappend_43_0)
+  ) of
+      (() , stringappend_43_0) =>
+  let stringappend_44_0 = (string_drop stringappend_41_0 stringappend_43_0) in
+  let (imm, stringappend_46_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_44_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_45_0,stringappend_46_0) => (stringappend_45_0, stringappend_46_0)
+       )) in
+  (case ((string_drop stringappend_44_0 stringappend_46_0)) of
+        s_ =>
+  SOME
+    (RISCV_JALR (imm,rs1,rd), ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((btype_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_48_0,stringappend_49_0) =>
+        let stringappend_50_0 = (string_drop stringappend_0_0 stringappend_49_0) in
+        if ((case ((spc_matches_prefix stringappend_50_0)) of
+            SOME (stringappend_51_0,stringappend_52_0) =>
+             let stringappend_53_0 = (string_drop stringappend_50_0 stringappend_52_0) in
+             if ((case ((reg_name_matches_prefix stringappend_53_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_54_0,stringappend_55_0) =>
+                  let stringappend_56_0 = (string_drop stringappend_53_0 stringappend_55_0) in
+                  if ((case ((sep_matches_prefix stringappend_56_0)) of
+                      SOME (stringappend_57_0,stringappend_58_0) =>
+                       let stringappend_59_0 = (string_drop stringappend_56_0 stringappend_58_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_59_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_60_0,stringappend_61_0) =>
+                            let stringappend_62_0 = (string_drop stringappend_59_0 stringappend_61_0) in
+                            if ((case ((sep_matches_prefix stringappend_62_0)) of
+                                SOME (stringappend_63_0,stringappend_64_0) =>
+                                 let stringappend_65_0 =
+                                   (string_drop stringappend_62_0 stringappend_64_0) in
+                                 if ((case ((hex_bits_13_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_65_0
+                                              :  (( 13 words$word # ii))option)) of
+                                     SOME (stringappend_66_0,stringappend_67_0) => 
+  (case ((string_drop stringappend_65_0 stringappend_67_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_49_0) =
+       ((case ((btype_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_48_0,stringappend_49_0) => (stringappend_48_0, stringappend_49_0)
+       )) in
+     let stringappend_50_0 = (string_drop stringappend_0_0 stringappend_49_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_50_0)) of
+        SOME (stringappend_51_0,stringappend_52_0) => (stringappend_51_0, stringappend_52_0)
+  ) of
+      (() , stringappend_52_0) =>
+  let stringappend_53_0 = (string_drop stringappend_50_0 stringappend_52_0) in
+  let (rs1, stringappend_55_0) =
+      ((case ((reg_name_matches_prefix stringappend_53_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_54_0,stringappend_55_0) => (stringappend_54_0, stringappend_55_0)
+       )) in
+  let stringappend_56_0 = (string_drop stringappend_53_0 stringappend_55_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_56_0)) of
+        SOME (stringappend_57_0,stringappend_58_0) => (stringappend_57_0, stringappend_58_0)
+  ) of
+      (() , stringappend_58_0) =>
+  let stringappend_59_0 = (string_drop stringappend_56_0 stringappend_58_0) in
+  let (rs2, stringappend_61_0) =
+      ((case ((reg_name_matches_prefix stringappend_59_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_60_0,stringappend_61_0) => (stringappend_60_0, stringappend_61_0)
+       )) in
+  let stringappend_62_0 = (string_drop stringappend_59_0 stringappend_61_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_62_0)) of
+        SOME (stringappend_63_0,stringappend_64_0) => (stringappend_63_0, stringappend_64_0)
+  ) of
+      (() , stringappend_64_0) =>
+  let stringappend_65_0 = (string_drop stringappend_62_0 stringappend_64_0) in
+  let (imm, stringappend_67_0) =
+      ((case ((hex_bits_13_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_65_0 : (( 13 words$word # ii)) option)) of
+             SOME (stringappend_66_0,stringappend_67_0) => (stringappend_66_0, stringappend_67_0)
+       )) in
+  (case ((string_drop stringappend_65_0 stringappend_67_0)) of
+        s_ => SOME
+                (BTYPE (imm,rs2,rs1,op), ((string_length arg_)) -
+                                           ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((itype_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_69_0,stringappend_70_0) =>
+        let stringappend_71_0 = (string_drop stringappend_0_0 stringappend_70_0) in
+        if ((case ((spc_matches_prefix stringappend_71_0)) of
+            SOME (stringappend_72_0,stringappend_73_0) =>
+             let stringappend_74_0 = (string_drop stringappend_71_0 stringappend_73_0) in
+             if ((case ((reg_name_matches_prefix stringappend_74_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_75_0,stringappend_76_0) =>
+                  let stringappend_77_0 = (string_drop stringappend_74_0 stringappend_76_0) in
+                  if ((case ((sep_matches_prefix stringappend_77_0)) of
+                      SOME (stringappend_78_0,stringappend_79_0) =>
+                       let stringappend_80_0 = (string_drop stringappend_77_0 stringappend_79_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_80_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_81_0,stringappend_82_0) =>
+                            let stringappend_83_0 = (string_drop stringappend_80_0 stringappend_82_0) in
+                            if ((case ((sep_matches_prefix stringappend_83_0)) of
+                                SOME (stringappend_84_0,stringappend_85_0) =>
+                                 let stringappend_86_0 =
+                                   (string_drop stringappend_83_0 stringappend_85_0) in
+                                 if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_86_0
+                                              :  (( 12 words$word # ii))option)) of
+                                     SOME (stringappend_87_0,stringappend_88_0) => 
+  (case ((string_drop stringappend_86_0 stringappend_88_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_70_0) =
+       ((case ((itype_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_69_0,stringappend_70_0) => (stringappend_69_0, stringappend_70_0)
+       )) in
+     let stringappend_71_0 = (string_drop stringappend_0_0 stringappend_70_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_71_0)) of
+        SOME (stringappend_72_0,stringappend_73_0) => (stringappend_72_0, stringappend_73_0)
+  ) of
+      (() , stringappend_73_0) =>
+  let stringappend_74_0 = (string_drop stringappend_71_0 stringappend_73_0) in
+  let (rd, stringappend_76_0) =
+      ((case ((reg_name_matches_prefix stringappend_74_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_75_0,stringappend_76_0) => (stringappend_75_0, stringappend_76_0)
+       )) in
+  let stringappend_77_0 = (string_drop stringappend_74_0 stringappend_76_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_77_0)) of
+        SOME (stringappend_78_0,stringappend_79_0) => (stringappend_78_0, stringappend_79_0)
+  ) of
+      (() , stringappend_79_0) =>
+  let stringappend_80_0 = (string_drop stringappend_77_0 stringappend_79_0) in
+  let (rs1, stringappend_82_0) =
+      ((case ((reg_name_matches_prefix stringappend_80_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_81_0,stringappend_82_0) => (stringappend_81_0, stringappend_82_0)
+       )) in
+  let stringappend_83_0 = (string_drop stringappend_80_0 stringappend_82_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_83_0)) of
+        SOME (stringappend_84_0,stringappend_85_0) => (stringappend_84_0, stringappend_85_0)
+  ) of
+      (() , stringappend_85_0) =>
+  let stringappend_86_0 = (string_drop stringappend_83_0 stringappend_85_0) in
+  let (imm, stringappend_88_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_86_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_87_0,stringappend_88_0) => (stringappend_87_0, stringappend_88_0)
+       )) in
+  (case ((string_drop stringappend_86_0 stringappend_88_0)) of
+        s_ => SOME
+                (ITYPE (imm,rs1,rd,op), ((string_length arg_)) -
+                                          ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_90_0,stringappend_91_0) =>
+        let stringappend_92_0 = (string_drop stringappend_0_0 stringappend_91_0) in
+        if ((case ((spc_matches_prefix stringappend_92_0)) of
+            SOME (stringappend_93_0,stringappend_94_0) =>
+             let stringappend_95_0 = (string_drop stringappend_92_0 stringappend_94_0) in
+             if ((case ((reg_name_matches_prefix stringappend_95_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_96_0,stringappend_97_0) =>
+                  let stringappend_98_0 = (string_drop stringappend_95_0 stringappend_97_0) in
+                  if ((case ((sep_matches_prefix stringappend_98_0)) of
+                      SOME (stringappend_99_0,stringappend_100_0) =>
+                       let stringappend_101_0 = (string_drop stringappend_98_0 stringappend_100_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_101_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_102_0,stringappend_103_0) =>
+                            let stringappend_104_0 =
+                              (string_drop stringappend_101_0 stringappend_103_0) in
+                            if ((case ((hex_bits_6_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_104_0
+                                         :  (( 6 words$word # ii))option)) of
+                                SOME (stringappend_105_0,stringappend_106_0) => 
+  (case ((string_drop stringappend_104_0 stringappend_106_0)) of   s_ => T )
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_91_0) =
+       ((case ((shiftiop_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_90_0,stringappend_91_0) => (stringappend_90_0, stringappend_91_0)
+       )) in
+     let stringappend_92_0 = (string_drop stringappend_0_0 stringappend_91_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_92_0)) of
+        SOME (stringappend_93_0,stringappend_94_0) => (stringappend_93_0, stringappend_94_0)
+  ) of
+      (() , stringappend_94_0) =>
+  let stringappend_95_0 = (string_drop stringappend_92_0 stringappend_94_0) in
+  let (rd, stringappend_97_0) =
+      ((case ((reg_name_matches_prefix stringappend_95_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_96_0,stringappend_97_0) => (stringappend_96_0, stringappend_97_0)
+       )) in
+  let stringappend_98_0 = (string_drop stringappend_95_0 stringappend_97_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_98_0)) of
+        SOME (stringappend_99_0,stringappend_100_0) => (stringappend_99_0, stringappend_100_0)
+  ) of
+      (() , stringappend_100_0) =>
+  let stringappend_101_0 = (string_drop stringappend_98_0 stringappend_100_0) in
+  let (rs1, stringappend_103_0) =
+      ((case ((reg_name_matches_prefix stringappend_101_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_102_0,stringappend_103_0) => (stringappend_102_0, stringappend_103_0)
+       )) in
+  let stringappend_104_0 = (string_drop stringappend_101_0 stringappend_103_0) in
+  let (shamt, stringappend_106_0) =
+      ((case ((hex_bits_6_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_104_0 : (( 6 words$word # ii)) option)) of
+             SOME (stringappend_105_0,stringappend_106_0) => (stringappend_105_0, stringappend_106_0)
+       )) in
+  (case ((string_drop stringappend_104_0 stringappend_106_0)) of
+        s_ =>
+  SOME
+    (SHIFTIOP (shamt,rs1,rd,op), ((string_length arg_)) -
+                                   ((string_length s_)))
+  )
+  )
+  )
+   else if ((case ((rtype_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_108_0,stringappend_109_0) =>
+        let stringappend_110_0 = (string_drop stringappend_0_0 stringappend_109_0) in
+        if ((case ((spc_matches_prefix stringappend_110_0)) of
+            SOME (stringappend_111_0,stringappend_112_0) =>
+             let stringappend_113_0 = (string_drop stringappend_110_0 stringappend_112_0) in
+             if ((case ((reg_name_matches_prefix stringappend_113_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_114_0,stringappend_115_0) =>
+                  let stringappend_116_0 = (string_drop stringappend_113_0 stringappend_115_0) in
+                  if ((case ((sep_matches_prefix stringappend_116_0)) of
+                      SOME (stringappend_117_0,stringappend_118_0) =>
+                       let stringappend_119_0 = (string_drop stringappend_116_0 stringappend_118_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_119_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_120_0,stringappend_121_0) =>
+                            let stringappend_122_0 =
+                              (string_drop stringappend_119_0 stringappend_121_0) in
+                            if ((case ((sep_matches_prefix stringappend_122_0)) of
+                                SOME (stringappend_123_0,stringappend_124_0) =>
+                                 let stringappend_125_0 =
+                                   (string_drop stringappend_122_0 stringappend_124_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_125_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_126_0,stringappend_127_0) => 
+  (case ((string_drop stringappend_125_0 stringappend_127_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_109_0) =
+       ((case ((rtype_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_108_0,stringappend_109_0) => (stringappend_108_0, stringappend_109_0)
+       )) in
+     let stringappend_110_0 = (string_drop stringappend_0_0 stringappend_109_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_110_0)) of
+        SOME (stringappend_111_0,stringappend_112_0) => (stringappend_111_0, stringappend_112_0)
+  ) of
+      (() , stringappend_112_0) =>
+  let stringappend_113_0 = (string_drop stringappend_110_0 stringappend_112_0) in
+  let (rd, stringappend_115_0) =
+      ((case ((reg_name_matches_prefix stringappend_113_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_114_0,stringappend_115_0) => (stringappend_114_0, stringappend_115_0)
+       )) in
+  let stringappend_116_0 = (string_drop stringappend_113_0 stringappend_115_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_116_0)) of
+        SOME (stringappend_117_0,stringappend_118_0) => (stringappend_117_0, stringappend_118_0)
+  ) of
+      (() , stringappend_118_0) =>
+  let stringappend_119_0 = (string_drop stringappend_116_0 stringappend_118_0) in
+  let (rs1, stringappend_121_0) =
+      ((case ((reg_name_matches_prefix stringappend_119_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_120_0,stringappend_121_0) => (stringappend_120_0, stringappend_121_0)
+       )) in
+  let stringappend_122_0 = (string_drop stringappend_119_0 stringappend_121_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_122_0)) of
+        SOME (stringappend_123_0,stringappend_124_0) => (stringappend_123_0, stringappend_124_0)
+  ) of
+      (() , stringappend_124_0) =>
+  let stringappend_125_0 = (string_drop stringappend_122_0 stringappend_124_0) in
+  let (rs2, stringappend_127_0) =
+      ((case ((reg_name_matches_prefix stringappend_125_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_126_0,stringappend_127_0) => (stringappend_126_0, stringappend_127_0)
+       )) in
+  (case ((string_drop stringappend_125_0 stringappend_127_0)) of
+        s_ => SOME
+                (RTYPE (rs2,rs1,rd,op), ((string_length arg_)) -
+                                          ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "l")) /\ (let stringappend_129_0 = (string_drop stringappend_0_0 ((string_length "l"))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_129_0)) of
+                   SOME (stringappend_130_0,stringappend_131_0) =>
+                    let stringappend_132_0 = (string_drop stringappend_129_0 stringappend_131_0) in
+                    if ((case ((maybe_u_matches_prefix stringappend_132_0)) of
+                        SOME (stringappend_133_0,stringappend_134_0) =>
+                         let stringappend_135_0 = (string_drop stringappend_132_0 stringappend_134_0) in
+                         if ((case ((maybe_aq_matches_prefix stringappend_135_0)) of
+                             SOME (stringappend_136_0,stringappend_137_0) =>
+                              let stringappend_138_0 =
+                                (string_drop stringappend_135_0 stringappend_137_0) in
+                              if ((case ((maybe_rl_matches_prefix stringappend_138_0)) of
+                                  SOME (stringappend_139_0,stringappend_140_0) =>
+                                   let stringappend_141_0 =
+                                     (string_drop stringappend_138_0 stringappend_140_0) in
+                                   if ((case ((spc_matches_prefix stringappend_141_0)) of
+                                       SOME (stringappend_142_0,stringappend_143_0) =>
+                                        let stringappend_144_0 =
+                                          (string_drop stringappend_141_0 stringappend_143_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_144_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_145_0,stringappend_146_0) =>
+                                             let stringappend_147_0 =
+                                               (string_drop stringappend_144_0 stringappend_146_0) in
+                                             if ((case ((sep_matches_prefix stringappend_147_0)) of
+                                                 SOME (stringappend_148_0,stringappend_149_0) =>
+                                                  let stringappend_150_0 =
+                                                    (string_drop stringappend_147_0
+                                                      stringappend_149_0) in
+                                                  if ((case ((reg_name_matches_prefix
+                                                                stringappend_150_0
+                                                               :  (( 5 words$word # ii))option)) of
+                                                      SOME (stringappend_151_0,stringappend_152_0) =>
+                                                       let stringappend_153_0 =
+                                                         (string_drop stringappend_150_0
+                                                           stringappend_152_0) in
+                                                       if ((case ((sep_matches_prefix
+                                                                     stringappend_153_0)) of
+                                                           SOME
+                                                           (stringappend_154_0,stringappend_155_0) =>
+                                                            let stringappend_156_0 =
+                                                              (string_drop stringappend_153_0
+                                                                stringappend_155_0) in
+                                                            if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                          stringappend_156_0
+                                                                         :  (( 12 words$word # ii))option)) of
+                                                                SOME
+                                                                (stringappend_157_0,stringappend_158_0) => 
+  (case ((string_drop stringappend_156_0 stringappend_158_0)) of   s_ => T )
+                                                              | NONE => F
+                                                              )) then
+                                                              T
+                                                            else F
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_129_0 = (string_drop stringappend_0_0 ((string_length "l"))) in
+     let (size1, stringappend_131_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_129_0)) of
+         SOME (stringappend_130_0,stringappend_131_0) => (stringappend_130_0, stringappend_131_0)
+       )) in
+     let stringappend_132_0 = (string_drop stringappend_129_0 stringappend_131_0) in
+     let (is_unsigned, stringappend_134_0) =
+       ((case ((maybe_u_matches_prefix stringappend_132_0)) of
+         SOME (stringappend_133_0,stringappend_134_0) => (stringappend_133_0, stringappend_134_0)
+       )) in
+     let stringappend_135_0 = (string_drop stringappend_132_0 stringappend_134_0) in
+     let (aq, stringappend_137_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_135_0)) of
+         SOME (stringappend_136_0,stringappend_137_0) => (stringappend_136_0, stringappend_137_0)
+       )) in
+     let stringappend_138_0 = (string_drop stringappend_135_0 stringappend_137_0) in
+     let (rl, stringappend_140_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_138_0)) of
+         SOME (stringappend_139_0,stringappend_140_0) => (stringappend_139_0, stringappend_140_0)
+       )) in
+     let stringappend_141_0 = (string_drop stringappend_138_0 stringappend_140_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_141_0)) of
+        SOME (stringappend_142_0,stringappend_143_0) => (stringappend_142_0, stringappend_143_0)
+  ) of
+      (() , stringappend_143_0) =>
+  let stringappend_144_0 = (string_drop stringappend_141_0 stringappend_143_0) in
+  let (rd, stringappend_146_0) =
+      ((case ((reg_name_matches_prefix stringappend_144_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_145_0,stringappend_146_0) => (stringappend_145_0, stringappend_146_0)
+       )) in
+  let stringappend_147_0 = (string_drop stringappend_144_0 stringappend_146_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_147_0)) of
+        SOME (stringappend_148_0,stringappend_149_0) => (stringappend_148_0, stringappend_149_0)
+  ) of
+      (() , stringappend_149_0) =>
+  let stringappend_150_0 = (string_drop stringappend_147_0 stringappend_149_0) in
+  let (rs1, stringappend_152_0) =
+      ((case ((reg_name_matches_prefix stringappend_150_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_151_0,stringappend_152_0) => (stringappend_151_0, stringappend_152_0)
+       )) in
+  let stringappend_153_0 = (string_drop stringappend_150_0 stringappend_152_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_153_0)) of
+        SOME (stringappend_154_0,stringappend_155_0) => (stringappend_154_0, stringappend_155_0)
+  ) of
+      (() , stringappend_155_0) =>
+  let stringappend_156_0 = (string_drop stringappend_153_0 stringappend_155_0) in
+  let (imm, stringappend_158_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_156_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_157_0,stringappend_158_0) => (stringappend_157_0, stringappend_158_0)
+       )) in
+  (case ((string_drop stringappend_156_0 stringappend_158_0)) of
+        s_ =>
+  SOME
+    (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl),
+    ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "s")) /\ (let stringappend_160_0 = (string_drop stringappend_0_0 ((string_length "s"))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_160_0)) of
+                   SOME (stringappend_161_0,stringappend_162_0) =>
+                    let stringappend_163_0 = (string_drop stringappend_160_0 stringappend_162_0) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_163_0)) of
+                        SOME (stringappend_164_0,stringappend_165_0) =>
+                         let stringappend_166_0 = (string_drop stringappend_163_0 stringappend_165_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_166_0)) of
+                             SOME (stringappend_167_0,stringappend_168_0) =>
+                              let stringappend_169_0 =
+                                (string_drop stringappend_166_0 stringappend_168_0) in
+                              if ((case ((spc_matches_prefix stringappend_169_0)) of
+                                  SOME (stringappend_170_0,stringappend_171_0) =>
+                                   let stringappend_172_0 =
+                                     (string_drop stringappend_169_0 stringappend_171_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_172_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_173_0,stringappend_174_0) =>
+                                        let stringappend_175_0 =
+                                          (string_drop stringappend_172_0 stringappend_174_0) in
+                                        if ((case ((sep_matches_prefix stringappend_175_0)) of
+                                            SOME (stringappend_176_0,stringappend_177_0) =>
+                                             let stringappend_178_0 =
+                                               (string_drop stringappend_175_0 stringappend_177_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_178_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_179_0,stringappend_180_0) =>
+                                                  let stringappend_181_0 =
+                                                    (string_drop stringappend_178_0
+                                                      stringappend_180_0) in
+                                                  if ((case ((sep_matches_prefix stringappend_181_0)) of
+                                                      SOME (stringappend_182_0,stringappend_183_0) =>
+                                                       let stringappend_184_0 =
+                                                         (string_drop stringappend_181_0
+                                                           stringappend_183_0) in
+                                                       if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                     stringappend_184_0
+                                                                    :  (( 12 words$word # ii))option)) of
+                                                           SOME
+                                                           (stringappend_185_0,stringappend_186_0) => 
+  (case ((string_drop stringappend_184_0 stringappend_186_0)) of   s_ => T )
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_160_0 = (string_drop stringappend_0_0 ((string_length "s"))) in
+     let (size1, stringappend_162_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_160_0)) of
+         SOME (stringappend_161_0,stringappend_162_0) => (stringappend_161_0, stringappend_162_0)
+       )) in
+     let stringappend_163_0 = (string_drop stringappend_160_0 stringappend_162_0) in
+     let (aq, stringappend_165_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_163_0)) of
+         SOME (stringappend_164_0,stringappend_165_0) => (stringappend_164_0, stringappend_165_0)
+       )) in
+     let stringappend_166_0 = (string_drop stringappend_163_0 stringappend_165_0) in
+     let (rl, stringappend_168_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_166_0)) of
+         SOME (stringappend_167_0,stringappend_168_0) => (stringappend_167_0, stringappend_168_0)
+       )) in
+     let stringappend_169_0 = (string_drop stringappend_166_0 stringappend_168_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_169_0)) of
+        SOME (stringappend_170_0,stringappend_171_0) => (stringappend_170_0, stringappend_171_0)
+  ) of
+      (() , stringappend_171_0) =>
+  let stringappend_172_0 = (string_drop stringappend_169_0 stringappend_171_0) in
+  let (rd, stringappend_174_0) =
+      ((case ((reg_name_matches_prefix stringappend_172_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_173_0,stringappend_174_0) => (stringappend_173_0, stringappend_174_0)
+       )) in
+  let stringappend_175_0 = (string_drop stringappend_172_0 stringappend_174_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_175_0)) of
+        SOME (stringappend_176_0,stringappend_177_0) => (stringappend_176_0, stringappend_177_0)
+  ) of
+      (() , stringappend_177_0) =>
+  let stringappend_178_0 = (string_drop stringappend_175_0 stringappend_177_0) in
+  let (rs1, stringappend_180_0) =
+      ((case ((reg_name_matches_prefix stringappend_178_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_179_0,stringappend_180_0) => (stringappend_179_0, stringappend_180_0)
+       )) in
+  let stringappend_181_0 = (string_drop stringappend_178_0 stringappend_180_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_181_0)) of
+        SOME (stringappend_182_0,stringappend_183_0) => (stringappend_182_0, stringappend_183_0)
+  ) of
+      (() , stringappend_183_0) =>
+  let stringappend_184_0 = (string_drop stringappend_181_0 stringappend_183_0) in
+  let (imm, stringappend_186_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_184_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_185_0,stringappend_186_0) => (stringappend_185_0, stringappend_186_0)
+       )) in
+  (case ((string_drop stringappend_184_0 stringappend_186_0)) of
+        s_ =>
+  SOME
+    (STORE (imm,rs1,rd,size1,aq,rl),
+    ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "addiw")) /\ (let stringappend_188_0 = (string_drop stringappend_0_0 ((string_length "addiw"))) in
+               if ((case ((spc_matches_prefix stringappend_188_0)) of
+                   SOME (stringappend_189_0,stringappend_190_0) =>
+                    let stringappend_191_0 = (string_drop stringappend_188_0 stringappend_190_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_191_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_192_0,stringappend_193_0) =>
+                         let stringappend_194_0 = (string_drop stringappend_191_0 stringappend_193_0) in
+                         if ((case ((sep_matches_prefix stringappend_194_0)) of
+                             SOME (stringappend_195_0,stringappend_196_0) =>
+                              let stringappend_197_0 =
+                                (string_drop stringappend_194_0 stringappend_196_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_197_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_198_0,stringappend_199_0) =>
+                                   let stringappend_200_0 =
+                                     (string_drop stringappend_197_0 stringappend_199_0) in
+                                   if ((case ((sep_matches_prefix stringappend_200_0)) of
+                                       SOME (stringappend_201_0,stringappend_202_0) =>
+                                        let stringappend_203_0 =
+                                          (string_drop stringappend_200_0 stringappend_202_0) in
+                                        if ((case ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_203_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_204_0,stringappend_205_0) => 
+  (case ((string_drop stringappend_203_0 stringappend_205_0)) of   s_ => T )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_188_0 = (string_drop stringappend_0_0 ((string_length "addiw"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_188_0)) of
+        SOME (stringappend_189_0,stringappend_190_0) => (stringappend_189_0, stringappend_190_0)
+  ) of
+      (() , stringappend_190_0) =>
+  let stringappend_191_0 = (string_drop stringappend_188_0 stringappend_190_0) in
+  let (rd, stringappend_193_0) =
+      ((case ((reg_name_matches_prefix stringappend_191_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_192_0,stringappend_193_0) => (stringappend_192_0, stringappend_193_0)
+       )) in
+  let stringappend_194_0 = (string_drop stringappend_191_0 stringappend_193_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_194_0)) of
+        SOME (stringappend_195_0,stringappend_196_0) => (stringappend_195_0, stringappend_196_0)
+  ) of
+      (() , stringappend_196_0) =>
+  let stringappend_197_0 = (string_drop stringappend_194_0 stringappend_196_0) in
+  let (rs1, stringappend_199_0) =
+      ((case ((reg_name_matches_prefix stringappend_197_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_198_0,stringappend_199_0) => (stringappend_198_0, stringappend_199_0)
+       )) in
+  let stringappend_200_0 = (string_drop stringappend_197_0 stringappend_199_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_200_0)) of
+        SOME (stringappend_201_0,stringappend_202_0) => (stringappend_201_0, stringappend_202_0)
+  ) of
+      (() , stringappend_202_0) =>
+  let stringappend_203_0 = (string_drop stringappend_200_0 stringappend_202_0) in
+  let (imm, stringappend_205_0) =
+      ((case ((hex_bits_12_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_203_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_204_0,stringappend_205_0) => (stringappend_204_0, stringappend_205_0)
+       )) in
+  (case ((string_drop stringappend_203_0 stringappend_205_0)) of
+        s_ => SOME
+                (ADDIW (imm,rs1,rd), ((string_length arg_)) -
+                                       ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((shiftw_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_207_0,stringappend_208_0) =>
+        let stringappend_209_0 = (string_drop stringappend_0_0 stringappend_208_0) in
+        if ((case ((spc_matches_prefix stringappend_209_0)) of
+            SOME (stringappend_210_0,stringappend_211_0) =>
+             let stringappend_212_0 = (string_drop stringappend_209_0 stringappend_211_0) in
+             if ((case ((reg_name_matches_prefix stringappend_212_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_213_0,stringappend_214_0) =>
+                  let stringappend_215_0 = (string_drop stringappend_212_0 stringappend_214_0) in
+                  if ((case ((sep_matches_prefix stringappend_215_0)) of
+                      SOME (stringappend_216_0,stringappend_217_0) =>
+                       let stringappend_218_0 = (string_drop stringappend_215_0 stringappend_217_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_218_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_219_0,stringappend_220_0) =>
+                            let stringappend_221_0 =
+                              (string_drop stringappend_218_0 stringappend_220_0) in
+                            if ((case ((sep_matches_prefix stringappend_221_0)) of
+                                SOME (stringappend_222_0,stringappend_223_0) =>
+                                 let stringappend_224_0 =
+                                   (string_drop stringappend_221_0 stringappend_223_0) in
+                                 if ((case ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_224_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_225_0,stringappend_226_0) => 
+  (case ((string_drop stringappend_224_0 stringappend_226_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_208_0) =
+       ((case ((shiftw_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_207_0,stringappend_208_0) => (stringappend_207_0, stringappend_208_0)
+       )) in
+     let stringappend_209_0 = (string_drop stringappend_0_0 stringappend_208_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_209_0)) of
+        SOME (stringappend_210_0,stringappend_211_0) => (stringappend_210_0, stringappend_211_0)
+  ) of
+      (() , stringappend_211_0) =>
+  let stringappend_212_0 = (string_drop stringappend_209_0 stringappend_211_0) in
+  let (rd, stringappend_214_0) =
+      ((case ((reg_name_matches_prefix stringappend_212_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_213_0,stringappend_214_0) => (stringappend_213_0, stringappend_214_0)
+       )) in
+  let stringappend_215_0 = (string_drop stringappend_212_0 stringappend_214_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_215_0)) of
+        SOME (stringappend_216_0,stringappend_217_0) => (stringappend_216_0, stringappend_217_0)
+  ) of
+      (() , stringappend_217_0) =>
+  let stringappend_218_0 = (string_drop stringappend_215_0 stringappend_217_0) in
+  let (rs1, stringappend_220_0) =
+      ((case ((reg_name_matches_prefix stringappend_218_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_219_0,stringappend_220_0) => (stringappend_219_0, stringappend_220_0)
+       )) in
+  let stringappend_221_0 = (string_drop stringappend_218_0 stringappend_220_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_221_0)) of
+        SOME (stringappend_222_0,stringappend_223_0) => (stringappend_222_0, stringappend_223_0)
+  ) of
+      (() , stringappend_223_0) =>
+  let stringappend_224_0 = (string_drop stringappend_221_0 stringappend_223_0) in
+  let (shamt, stringappend_226_0) =
+      ((case ((hex_bits_5_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_224_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_225_0,stringappend_226_0) => (stringappend_225_0, stringappend_226_0)
+       )) in
+  (case ((string_drop stringappend_224_0 stringappend_226_0)) of
+        s_ =>
+  SOME
+    (SHIFTW (shamt,rs1,rd,op), ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((rtypew_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_228_0,stringappend_229_0) =>
+        let stringappend_230_0 = (string_drop stringappend_0_0 stringappend_229_0) in
+        if ((case ((spc_matches_prefix stringappend_230_0)) of
+            SOME (stringappend_231_0,stringappend_232_0) =>
+             let stringappend_233_0 = (string_drop stringappend_230_0 stringappend_232_0) in
+             if ((case ((reg_name_matches_prefix stringappend_233_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_234_0,stringappend_235_0) =>
+                  let stringappend_236_0 = (string_drop stringappend_233_0 stringappend_235_0) in
+                  if ((case ((sep_matches_prefix stringappend_236_0)) of
+                      SOME (stringappend_237_0,stringappend_238_0) =>
+                       let stringappend_239_0 = (string_drop stringappend_236_0 stringappend_238_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_239_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_240_0,stringappend_241_0) =>
+                            let stringappend_242_0 =
+                              (string_drop stringappend_239_0 stringappend_241_0) in
+                            if ((case ((sep_matches_prefix stringappend_242_0)) of
+                                SOME (stringappend_243_0,stringappend_244_0) =>
+                                 let stringappend_245_0 =
+                                   (string_drop stringappend_242_0 stringappend_244_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_245_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_246_0,stringappend_247_0) => 
+  (case ((string_drop stringappend_245_0 stringappend_247_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_229_0) =
+       ((case ((rtypew_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_228_0,stringappend_229_0) => (stringappend_228_0, stringappend_229_0)
+       )) in
+     let stringappend_230_0 = (string_drop stringappend_0_0 stringappend_229_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_230_0)) of
+        SOME (stringappend_231_0,stringappend_232_0) => (stringappend_231_0, stringappend_232_0)
+  ) of
+      (() , stringappend_232_0) =>
+  let stringappend_233_0 = (string_drop stringappend_230_0 stringappend_232_0) in
+  let (rd, stringappend_235_0) =
+      ((case ((reg_name_matches_prefix stringappend_233_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_234_0,stringappend_235_0) => (stringappend_234_0, stringappend_235_0)
+       )) in
+  let stringappend_236_0 = (string_drop stringappend_233_0 stringappend_235_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_236_0)) of
+        SOME (stringappend_237_0,stringappend_238_0) => (stringappend_237_0, stringappend_238_0)
+  ) of
+      (() , stringappend_238_0) =>
+  let stringappend_239_0 = (string_drop stringappend_236_0 stringappend_238_0) in
+  let (rs1, stringappend_241_0) =
+      ((case ((reg_name_matches_prefix stringappend_239_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_240_0,stringappend_241_0) => (stringappend_240_0, stringappend_241_0)
+       )) in
+  let stringappend_242_0 = (string_drop stringappend_239_0 stringappend_241_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_242_0)) of
+        SOME (stringappend_243_0,stringappend_244_0) => (stringappend_243_0, stringappend_244_0)
+  ) of
+      (() , stringappend_244_0) =>
+  let stringappend_245_0 = (string_drop stringappend_242_0 stringappend_244_0) in
+  let (rs2, stringappend_247_0) =
+      ((case ((reg_name_matches_prefix stringappend_245_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_246_0,stringappend_247_0) => (stringappend_246_0, stringappend_247_0)
+       )) in
+  (case ((string_drop stringappend_245_0 stringappend_247_0)) of
+        s_ => SOME
+                (RTYPEW (rs2,rs1,rd,op), ((string_length arg_)) -
+                                           ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((mul_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_249_0,stringappend_250_0) =>
+        let stringappend_251_0 = (string_drop stringappend_0_0 stringappend_250_0) in
+        if ((case ((spc_matches_prefix stringappend_251_0)) of
+            SOME (stringappend_252_0,stringappend_253_0) =>
+             let stringappend_254_0 = (string_drop stringappend_251_0 stringappend_253_0) in
+             if ((case ((reg_name_matches_prefix stringappend_254_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_255_0,stringappend_256_0) =>
+                  let stringappend_257_0 = (string_drop stringappend_254_0 stringappend_256_0) in
+                  if ((case ((sep_matches_prefix stringappend_257_0)) of
+                      SOME (stringappend_258_0,stringappend_259_0) =>
+                       let stringappend_260_0 = (string_drop stringappend_257_0 stringappend_259_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_260_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_261_0,stringappend_262_0) =>
+                            let stringappend_263_0 =
+                              (string_drop stringappend_260_0 stringappend_262_0) in
+                            if ((case ((sep_matches_prefix stringappend_263_0)) of
+                                SOME (stringappend_264_0,stringappend_265_0) =>
+                                 let stringappend_266_0 =
+                                   (string_drop stringappend_263_0 stringappend_265_0) in
+                                 if ((case ((reg_name_matches_prefix stringappend_266_0
+                                              :  (( 5 words$word # ii))option)) of
+                                     SOME (stringappend_267_0,stringappend_268_0) => 
+  (case ((string_drop stringappend_266_0 stringappend_268_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let ((high, signed1, signed2), stringappend_250_0) =
+       ((case ((mul_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_249_0,stringappend_250_0) => (stringappend_249_0, stringappend_250_0)
+       )) in
+     let stringappend_251_0 = (string_drop stringappend_0_0 stringappend_250_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_251_0)) of
+        SOME (stringappend_252_0,stringappend_253_0) => (stringappend_252_0, stringappend_253_0)
+  ) of
+      (() , stringappend_253_0) =>
+  let stringappend_254_0 = (string_drop stringappend_251_0 stringappend_253_0) in
+  let (rd, stringappend_256_0) =
+      ((case ((reg_name_matches_prefix stringappend_254_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_255_0,stringappend_256_0) => (stringappend_255_0, stringappend_256_0)
+       )) in
+  let stringappend_257_0 = (string_drop stringappend_254_0 stringappend_256_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_257_0)) of
+        SOME (stringappend_258_0,stringappend_259_0) => (stringappend_258_0, stringappend_259_0)
+  ) of
+      (() , stringappend_259_0) =>
+  let stringappend_260_0 = (string_drop stringappend_257_0 stringappend_259_0) in
+  let (rs1, stringappend_262_0) =
+      ((case ((reg_name_matches_prefix stringappend_260_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_261_0,stringappend_262_0) => (stringappend_261_0, stringappend_262_0)
+       )) in
+  let stringappend_263_0 = (string_drop stringappend_260_0 stringappend_262_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_263_0)) of
+        SOME (stringappend_264_0,stringappend_265_0) => (stringappend_264_0, stringappend_265_0)
+  ) of
+      (() , stringappend_265_0) =>
+  let stringappend_266_0 = (string_drop stringappend_263_0 stringappend_265_0) in
+  let (rs2, stringappend_268_0) =
+      ((case ((reg_name_matches_prefix stringappend_266_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_267_0,stringappend_268_0) => (stringappend_267_0, stringappend_268_0)
+       )) in
+  (case ((string_drop stringappend_266_0 stringappend_268_0)) of
+        s_ =>
+  SOME
+    (MUL (rs2,rs1,rd,high,signed1,signed2),
+    ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "div")) /\ (let stringappend_270_0 = (string_drop stringappend_0_0 ((string_length "div"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_270_0)) of
+                   SOME (stringappend_271_0,stringappend_272_0) =>
+                    let stringappend_273_0 = (string_drop stringappend_270_0 stringappend_272_0) in
+                    if ((case ((spc_matches_prefix stringappend_273_0)) of
+                        SOME (stringappend_274_0,stringappend_275_0) =>
+                         let stringappend_276_0 = (string_drop stringappend_273_0 stringappend_275_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_276_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_277_0,stringappend_278_0) =>
+                              let stringappend_279_0 =
+                                (string_drop stringappend_276_0 stringappend_278_0) in
+                              if ((case ((sep_matches_prefix stringappend_279_0)) of
+                                  SOME (stringappend_280_0,stringappend_281_0) =>
+                                   let stringappend_282_0 =
+                                     (string_drop stringappend_279_0 stringappend_281_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_282_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_283_0,stringappend_284_0) =>
+                                        let stringappend_285_0 =
+                                          (string_drop stringappend_282_0 stringappend_284_0) in
+                                        if ((case ((sep_matches_prefix stringappend_285_0)) of
+                                            SOME (stringappend_286_0,stringappend_287_0) =>
+                                             let stringappend_288_0 =
+                                               (string_drop stringappend_285_0 stringappend_287_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_288_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_289_0,stringappend_290_0) => 
+  (case ((string_drop stringappend_288_0 stringappend_290_0)) of   s_ => T )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_270_0 = (string_drop stringappend_0_0 ((string_length "div"))) in
+     let (s, stringappend_272_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_270_0)) of
+         SOME (stringappend_271_0,stringappend_272_0) => (stringappend_271_0, stringappend_272_0)
+       )) in
+     let stringappend_273_0 = (string_drop stringappend_270_0 stringappend_272_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_273_0)) of
+        SOME (stringappend_274_0,stringappend_275_0) => (stringappend_274_0, stringappend_275_0)
+  ) of
+      (() , stringappend_275_0) =>
+  let stringappend_276_0 = (string_drop stringappend_273_0 stringappend_275_0) in
+  let (rd, stringappend_278_0) =
+      ((case ((reg_name_matches_prefix stringappend_276_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_277_0,stringappend_278_0) => (stringappend_277_0, stringappend_278_0)
+       )) in
+  let stringappend_279_0 = (string_drop stringappend_276_0 stringappend_278_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_279_0)) of
+        SOME (stringappend_280_0,stringappend_281_0) => (stringappend_280_0, stringappend_281_0)
+  ) of
+      (() , stringappend_281_0) =>
+  let stringappend_282_0 = (string_drop stringappend_279_0 stringappend_281_0) in
+  let (rs1, stringappend_284_0) =
+      ((case ((reg_name_matches_prefix stringappend_282_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_283_0,stringappend_284_0) => (stringappend_283_0, stringappend_284_0)
+       )) in
+  let stringappend_285_0 = (string_drop stringappend_282_0 stringappend_284_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_285_0)) of
+        SOME (stringappend_286_0,stringappend_287_0) => (stringappend_286_0, stringappend_287_0)
+  ) of
+      (() , stringappend_287_0) =>
+  let stringappend_288_0 = (string_drop stringappend_285_0 stringappend_287_0) in
+  let (rs2, stringappend_290_0) =
+      ((case ((reg_name_matches_prefix stringappend_288_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_289_0,stringappend_290_0) => (stringappend_289_0, stringappend_290_0)
+       )) in
+  (case ((string_drop stringappend_288_0 stringappend_290_0)) of
+        s_ => SOME
+                (DIV0 (rs2,rs1,rd,s), ((string_length arg_)) -
+                                        ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "rem")) /\ (let stringappend_292_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_292_0)) of
+                   SOME (stringappend_293_0,stringappend_294_0) =>
+                    let stringappend_295_0 = (string_drop stringappend_292_0 stringappend_294_0) in
+                    if ((case ((spc_matches_prefix stringappend_295_0)) of
+                        SOME (stringappend_296_0,stringappend_297_0) =>
+                         let stringappend_298_0 = (string_drop stringappend_295_0 stringappend_297_0) in
+                         if ((case ((reg_name_matches_prefix stringappend_298_0
+                                      :  (( 5 words$word # ii))option)) of
+                             SOME (stringappend_299_0,stringappend_300_0) =>
+                              let stringappend_301_0 =
+                                (string_drop stringappend_298_0 stringappend_300_0) in
+                              if ((case ((sep_matches_prefix stringappend_301_0)) of
+                                  SOME (stringappend_302_0,stringappend_303_0) =>
+                                   let stringappend_304_0 =
+                                     (string_drop stringappend_301_0 stringappend_303_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_304_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_305_0,stringappend_306_0) =>
+                                        let stringappend_307_0 =
+                                          (string_drop stringappend_304_0 stringappend_306_0) in
+                                        if ((case ((sep_matches_prefix stringappend_307_0)) of
+                                            SOME (stringappend_308_0,stringappend_309_0) =>
+                                             let stringappend_310_0 =
+                                               (string_drop stringappend_307_0 stringappend_309_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_310_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_311_0,stringappend_312_0) => 
+  (case ((string_drop stringappend_310_0 stringappend_312_0)) of   s_ => T )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_292_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in
+     let (s, stringappend_294_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_292_0)) of
+         SOME (stringappend_293_0,stringappend_294_0) => (stringappend_293_0, stringappend_294_0)
+       )) in
+     let stringappend_295_0 = (string_drop stringappend_292_0 stringappend_294_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_295_0)) of
+        SOME (stringappend_296_0,stringappend_297_0) => (stringappend_296_0, stringappend_297_0)
+  ) of
+      (() , stringappend_297_0) =>
+  let stringappend_298_0 = (string_drop stringappend_295_0 stringappend_297_0) in
+  let (rd, stringappend_300_0) =
+      ((case ((reg_name_matches_prefix stringappend_298_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_299_0,stringappend_300_0) => (stringappend_299_0, stringappend_300_0)
+       )) in
+  let stringappend_301_0 = (string_drop stringappend_298_0 stringappend_300_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_301_0)) of
+        SOME (stringappend_302_0,stringappend_303_0) => (stringappend_302_0, stringappend_303_0)
+  ) of
+      (() , stringappend_303_0) =>
+  let stringappend_304_0 = (string_drop stringappend_301_0 stringappend_303_0) in
+  let (rs1, stringappend_306_0) =
+      ((case ((reg_name_matches_prefix stringappend_304_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_305_0,stringappend_306_0) => (stringappend_305_0, stringappend_306_0)
+       )) in
+  let stringappend_307_0 = (string_drop stringappend_304_0 stringappend_306_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_307_0)) of
+        SOME (stringappend_308_0,stringappend_309_0) => (stringappend_308_0, stringappend_309_0)
+  ) of
+      (() , stringappend_309_0) =>
+  let stringappend_310_0 = (string_drop stringappend_307_0 stringappend_309_0) in
+  let (rs2, stringappend_312_0) =
+      ((case ((reg_name_matches_prefix stringappend_310_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_311_0,stringappend_312_0) => (stringappend_311_0, stringappend_312_0)
+       )) in
+  (case ((string_drop stringappend_310_0 stringappend_312_0)) of
+        s_ => SOME
+                (REM (rs2,rs1,rd,s), ((string_length arg_)) -
+                                       ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "mulw")) /\ (let stringappend_314_0 = (string_drop stringappend_0_0 ((string_length "mulw"))) in
+               if ((case ((spc_matches_prefix stringappend_314_0)) of
+                   SOME (stringappend_315_0,stringappend_316_0) =>
+                    let stringappend_317_0 = (string_drop stringappend_314_0 stringappend_316_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_317_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_318_0,stringappend_319_0) =>
+                         let stringappend_320_0 = (string_drop stringappend_317_0 stringappend_319_0) in
+                         if ((case ((sep_matches_prefix stringappend_320_0)) of
+                             SOME (stringappend_321_0,stringappend_322_0) =>
+                              let stringappend_323_0 =
+                                (string_drop stringappend_320_0 stringappend_322_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_323_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_324_0,stringappend_325_0) =>
+                                   let stringappend_326_0 =
+                                     (string_drop stringappend_323_0 stringappend_325_0) in
+                                   if ((case ((sep_matches_prefix stringappend_326_0)) of
+                                       SOME (stringappend_327_0,stringappend_328_0) =>
+                                        let stringappend_329_0 =
+                                          (string_drop stringappend_326_0 stringappend_328_0) in
+                                        if ((case ((reg_name_matches_prefix stringappend_329_0
+                                                     :  (( 5 words$word # ii))option)) of
+                                            SOME (stringappend_330_0,stringappend_331_0) => 
+  (case ((string_drop stringappend_329_0 stringappend_331_0)) of   s_ => T )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_314_0 = (string_drop stringappend_0_0 ((string_length "mulw"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_314_0)) of
+        SOME (stringappend_315_0,stringappend_316_0) => (stringappend_315_0, stringappend_316_0)
+  ) of
+      (() , stringappend_316_0) =>
+  let stringappend_317_0 = (string_drop stringappend_314_0 stringappend_316_0) in
+  let (rd, stringappend_319_0) =
+      ((case ((reg_name_matches_prefix stringappend_317_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_318_0,stringappend_319_0) => (stringappend_318_0, stringappend_319_0)
+       )) in
+  let stringappend_320_0 = (string_drop stringappend_317_0 stringappend_319_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_320_0)) of
+        SOME (stringappend_321_0,stringappend_322_0) => (stringappend_321_0, stringappend_322_0)
+  ) of
+      (() , stringappend_322_0) =>
+  let stringappend_323_0 = (string_drop stringappend_320_0 stringappend_322_0) in
+  let (rs1, stringappend_325_0) =
+      ((case ((reg_name_matches_prefix stringappend_323_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_324_0,stringappend_325_0) => (stringappend_324_0, stringappend_325_0)
+       )) in
+  let stringappend_326_0 = (string_drop stringappend_323_0 stringappend_325_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_326_0)) of
+        SOME (stringappend_327_0,stringappend_328_0) => (stringappend_327_0, stringappend_328_0)
+  ) of
+      (() , stringappend_328_0) =>
+  let stringappend_329_0 = (string_drop stringappend_326_0 stringappend_328_0) in
+  let (rs2, stringappend_331_0) =
+      ((case ((reg_name_matches_prefix stringappend_329_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_330_0,stringappend_331_0) => (stringappend_330_0, stringappend_331_0)
+       )) in
+  (case ((string_drop stringappend_329_0 stringappend_331_0)) of
+        s_ => SOME
+                (MULW (rs2,rs1,rd), ((string_length arg_)) -
+                                      ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "div")) /\ (let stringappend_333_0 = (string_drop stringappend_0_0 ((string_length "div"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_333_0)) of
+                   SOME (stringappend_334_0,stringappend_335_0) =>
+                    let stringappend_336_0 = (string_drop stringappend_333_0 stringappend_335_0) in
+                    if (((((string_startswith stringappend_336_0 "w")) /\ (let stringappend_337_0 =
+                             (string_drop stringappend_336_0 ((string_length "w"))) in
+                           if ((case ((spc_matches_prefix stringappend_337_0)) of
+                               SOME (stringappend_338_0,stringappend_339_0) =>
+                                let stringappend_340_0 =
+                                  (string_drop stringappend_337_0 stringappend_339_0) in
+                                if ((case ((reg_name_matches_prefix stringappend_340_0
+                                             :  (( 5 words$word # ii))option)) of
+                                    SOME (stringappend_341_0,stringappend_342_0) =>
+                                     let stringappend_343_0 =
+                                       (string_drop stringappend_340_0 stringappend_342_0) in
+                                     if ((case ((sep_matches_prefix stringappend_343_0)) of
+                                         SOME (stringappend_344_0,stringappend_345_0) =>
+                                          let stringappend_346_0 =
+                                            (string_drop stringappend_343_0 stringappend_345_0) in
+                                          if ((case ((reg_name_matches_prefix stringappend_346_0
+                                                       :  (( 5 words$word # ii))option)) of
+                                              SOME (stringappend_347_0,stringappend_348_0) =>
+                                               let stringappend_349_0 =
+                                                 (string_drop stringappend_346_0 stringappend_348_0) in
+                                               if ((case ((sep_matches_prefix stringappend_349_0)) of
+                                                   SOME (stringappend_350_0,stringappend_351_0) =>
+                                                    let stringappend_352_0 =
+                                                      (string_drop stringappend_349_0
+                                                        stringappend_351_0) in
+                                                    if ((case ((reg_name_matches_prefix
+                                                                  stringappend_352_0
+                                                                 :  (( 5 words$word # ii))option)) of
+                                                        SOME (stringappend_353_0,stringappend_354_0) => 
+  (case ((string_drop stringappend_352_0 stringappend_354_0)) of   s_ => T )
+                                                      | NONE => F
+                                                      )) then
+                                                      T
+                                                    else F
+                                                 | NONE => F
+                                                 )) then
+                                                 T
+                                               else F
+                                            | NONE => F
+                                            )) then
+                                            T
+                                          else F
+                                       | NONE => F
+                                       )) then
+                                       T
+                                     else F
+                                  | NONE => F
+                                  )) then
+                                  T
+                                else F
+                             | NONE => F
+                             )) then
+                             T
+                           else F)))) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_333_0 = (string_drop stringappend_0_0 ((string_length "div"))) in
+     let (s, stringappend_335_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_333_0)) of
+         SOME (stringappend_334_0,stringappend_335_0) => (stringappend_334_0, stringappend_335_0)
+       )) in
+     let stringappend_336_0 = (string_drop stringappend_333_0 stringappend_335_0) in
+     let stringappend_337_0 = (string_drop stringappend_336_0 ((string_length "w"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_337_0)) of
+        SOME (stringappend_338_0,stringappend_339_0) => (stringappend_338_0, stringappend_339_0)
+  ) of
+      (() , stringappend_339_0) =>
+  let stringappend_340_0 = (string_drop stringappend_337_0 stringappend_339_0) in
+  let (rd, stringappend_342_0) =
+      ((case ((reg_name_matches_prefix stringappend_340_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_341_0,stringappend_342_0) => (stringappend_341_0, stringappend_342_0)
+       )) in
+  let stringappend_343_0 = (string_drop stringappend_340_0 stringappend_342_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_343_0)) of
+        SOME (stringappend_344_0,stringappend_345_0) => (stringappend_344_0, stringappend_345_0)
+  ) of
+      (() , stringappend_345_0) =>
+  let stringappend_346_0 = (string_drop stringappend_343_0 stringappend_345_0) in
+  let (rs1, stringappend_348_0) =
+      ((case ((reg_name_matches_prefix stringappend_346_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_347_0,stringappend_348_0) => (stringappend_347_0, stringappend_348_0)
+       )) in
+  let stringappend_349_0 = (string_drop stringappend_346_0 stringappend_348_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_349_0)) of
+        SOME (stringappend_350_0,stringappend_351_0) => (stringappend_350_0, stringappend_351_0)
+  ) of
+      (() , stringappend_351_0) =>
+  let stringappend_352_0 = (string_drop stringappend_349_0 stringappend_351_0) in
+  let (rs2, stringappend_354_0) =
+      ((case ((reg_name_matches_prefix stringappend_352_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_353_0,stringappend_354_0) => (stringappend_353_0, stringappend_354_0)
+       )) in
+  (case ((string_drop stringappend_352_0 stringappend_354_0)) of
+        s_ => SOME
+                (DIVW (rs2,rs1,rd,s), ((string_length arg_)) -
+                                        ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "rem")) /\ (let stringappend_356_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in
+               if ((case ((maybe_not_u_matches_prefix stringappend_356_0)) of
+                   SOME (stringappend_357_0,stringappend_358_0) =>
+                    let stringappend_359_0 = (string_drop stringappend_356_0 stringappend_358_0) in
+                    if (((((string_startswith stringappend_359_0 "w")) /\ (let stringappend_360_0 =
+                             (string_drop stringappend_359_0 ((string_length "w"))) in
+                           if ((case ((spc_matches_prefix stringappend_360_0)) of
+                               SOME (stringappend_361_0,stringappend_362_0) =>
+                                let stringappend_363_0 =
+                                  (string_drop stringappend_360_0 stringappend_362_0) in
+                                if ((case ((reg_name_matches_prefix stringappend_363_0
+                                             :  (( 5 words$word # ii))option)) of
+                                    SOME (stringappend_364_0,stringappend_365_0) =>
+                                     let stringappend_366_0 =
+                                       (string_drop stringappend_363_0 stringappend_365_0) in
+                                     if ((case ((sep_matches_prefix stringappend_366_0)) of
+                                         SOME (stringappend_367_0,stringappend_368_0) =>
+                                          let stringappend_369_0 =
+                                            (string_drop stringappend_366_0 stringappend_368_0) in
+                                          if ((case ((reg_name_matches_prefix stringappend_369_0
+                                                       :  (( 5 words$word # ii))option)) of
+                                              SOME (stringappend_370_0,stringappend_371_0) =>
+                                               let stringappend_372_0 =
+                                                 (string_drop stringappend_369_0 stringappend_371_0) in
+                                               if ((case ((sep_matches_prefix stringappend_372_0)) of
+                                                   SOME (stringappend_373_0,stringappend_374_0) =>
+                                                    let stringappend_375_0 =
+                                                      (string_drop stringappend_372_0
+                                                        stringappend_374_0) in
+                                                    if ((case ((reg_name_matches_prefix
+                                                                  stringappend_375_0
+                                                                 :  (( 5 words$word # ii))option)) of
+                                                        SOME (stringappend_376_0,stringappend_377_0) => 
+  (case ((string_drop stringappend_375_0 stringappend_377_0)) of   s_ => T )
+                                                      | NONE => F
+                                                      )) then
+                                                      T
+                                                    else F
+                                                 | NONE => F
+                                                 )) then
+                                                 T
+                                               else F
+                                            | NONE => F
+                                            )) then
+                                            T
+                                          else F
+                                       | NONE => F
+                                       )) then
+                                       T
+                                     else F
+                                  | NONE => F
+                                  )) then
+                                  T
+                                else F
+                             | NONE => F
+                             )) then
+                             T
+                           else F)))) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_356_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in
+     let (s, stringappend_358_0) =
+       ((case ((maybe_not_u_matches_prefix stringappend_356_0)) of
+         SOME (stringappend_357_0,stringappend_358_0) => (stringappend_357_0, stringappend_358_0)
+       )) in
+     let stringappend_359_0 = (string_drop stringappend_356_0 stringappend_358_0) in
+     let stringappend_360_0 = (string_drop stringappend_359_0 ((string_length "w"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_360_0)) of
+        SOME (stringappend_361_0,stringappend_362_0) => (stringappend_361_0, stringappend_362_0)
+  ) of
+      (() , stringappend_362_0) =>
+  let stringappend_363_0 = (string_drop stringappend_360_0 stringappend_362_0) in
+  let (rd, stringappend_365_0) =
+      ((case ((reg_name_matches_prefix stringappend_363_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_364_0,stringappend_365_0) => (stringappend_364_0, stringappend_365_0)
+       )) in
+  let stringappend_366_0 = (string_drop stringappend_363_0 stringappend_365_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_366_0)) of
+        SOME (stringappend_367_0,stringappend_368_0) => (stringappend_367_0, stringappend_368_0)
+  ) of
+      (() , stringappend_368_0) =>
+  let stringappend_369_0 = (string_drop stringappend_366_0 stringappend_368_0) in
+  let (rs1, stringappend_371_0) =
+      ((case ((reg_name_matches_prefix stringappend_369_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_370_0,stringappend_371_0) => (stringappend_370_0, stringappend_371_0)
+       )) in
+  let stringappend_372_0 = (string_drop stringappend_369_0 stringappend_371_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_372_0)) of
+        SOME (stringappend_373_0,stringappend_374_0) => (stringappend_373_0, stringappend_374_0)
+  ) of
+      (() , stringappend_374_0) =>
+  let stringappend_375_0 = (string_drop stringappend_372_0 stringappend_374_0) in
+  let (rs2, stringappend_377_0) =
+      ((case ((reg_name_matches_prefix stringappend_375_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_376_0,stringappend_377_0) => (stringappend_376_0, stringappend_377_0)
+       )) in
+  (case ((string_drop stringappend_375_0 stringappend_377_0)) of
+        s_ => SOME
+                (REMW (rs2,rs1,rd,s), ((string_length arg_)) -
+                                        ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "fence")) /\ (let stringappend_379_0 = (string_drop stringappend_0_0 ((string_length "fence"))) in
+               if ((case ((spc_matches_prefix stringappend_379_0)) of
+                   SOME (stringappend_380_0,stringappend_381_0) =>
+                    let stringappend_382_0 = (string_drop stringappend_379_0 stringappend_381_0) in
+                    if ((case ((fence_bits_matches_prefix stringappend_382_0
+                                 :  (( 4 words$word # ii))option)) of
+                        SOME (stringappend_383_0,stringappend_384_0) =>
+                         let stringappend_385_0 = (string_drop stringappend_382_0 stringappend_384_0) in
+                         if ((case ((sep_matches_prefix stringappend_385_0)) of
+                             SOME (stringappend_386_0,stringappend_387_0) =>
+                              let stringappend_388_0 =
+                                (string_drop stringappend_385_0 stringappend_387_0) in
+                              if ((case ((fence_bits_matches_prefix stringappend_388_0
+                                           :  (( 4 words$word # ii))option)) of
+                                  SOME (stringappend_389_0,stringappend_390_0) => 
+  (case ((string_drop stringappend_388_0 stringappend_390_0)) of   s_ => T )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_379_0 = (string_drop stringappend_0_0 ((string_length "fence"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_379_0)) of
+        SOME (stringappend_380_0,stringappend_381_0) => (stringappend_380_0, stringappend_381_0)
+  ) of
+      (() , stringappend_381_0) =>
+  let stringappend_382_0 = (string_drop stringappend_379_0 stringappend_381_0) in
+  let (pred, stringappend_384_0) =
+      ((case ((fence_bits_matches_prefix stringappend_382_0 : (( 4 words$word # ii)) option)) of
+             SOME (stringappend_383_0,stringappend_384_0) => (stringappend_383_0, stringappend_384_0)
+       )) in
+  let stringappend_385_0 = (string_drop stringappend_382_0 stringappend_384_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_385_0)) of
+        SOME (stringappend_386_0,stringappend_387_0) => (stringappend_386_0, stringappend_387_0)
+  ) of
+      (() , stringappend_387_0) =>
+  let stringappend_388_0 = (string_drop stringappend_385_0 stringappend_387_0) in
+  let (succ, stringappend_390_0) =
+      ((case ((fence_bits_matches_prefix stringappend_388_0 : (( 4 words$word # ii)) option)) of
+             SOME (stringappend_389_0,stringappend_390_0) => (stringappend_389_0, stringappend_390_0)
+       )) in
+  (case ((string_drop stringappend_388_0 stringappend_390_0)) of
+        s_ => SOME
+                (FENCE (pred,succ), ((string_length arg_)) -
+                                      ((string_length s_)))
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "fence.i")) /\ (
+  (case ((string_drop stringappend_0_0 ((string_length "fence.i")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_0_0 ((string_length "fence.i")))) of
+       s_ => SOME (FENCEI () , ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_0_0 "ecall")) /\ (
+  (case ((string_drop stringappend_0_0 ((string_length "ecall")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_0_0 ((string_length "ecall")))) of
+       s_ => SOME (ECALL () , ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_0_0 "mret")) /\ (
+  (case ((string_drop stringappend_0_0 ((string_length "mret")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_0_0 ((string_length "mret")))) of
+       s_ => SOME (MRET () , ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_0_0 "sret")) /\ (
+  (case ((string_drop stringappend_0_0 ((string_length "sret")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_0_0 ((string_length "sret")))) of
+       s_ => SOME (SRET () , ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_0_0 "ebreak")) /\ (
+  (case ((string_drop stringappend_0_0 ((string_length "ebreak")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_0_0 ((string_length "ebreak")))) of
+       s_ => SOME (EBREAK () , ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_0_0 "wfi")) /\ (
+  (case ((string_drop stringappend_0_0 ((string_length "wfi")))) of
+        s_ => T
+  ))))) then
+     (case ((string_drop stringappend_0_0 ((string_length "wfi")))) of
+       s_ => SOME (WFI () , ((string_length arg_)) - ((string_length s_)))
+     )
+   else if (((((string_startswith stringappend_0_0 "sfence.vma")) /\ (let stringappend_398_0 = (string_drop stringappend_0_0 ((string_length "sfence.vma"))) in
+               if ((case ((spc_matches_prefix stringappend_398_0)) of
+                   SOME (stringappend_399_0,stringappend_400_0) =>
+                    let stringappend_401_0 = (string_drop stringappend_398_0 stringappend_400_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_401_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_402_0,stringappend_403_0) =>
+                         let stringappend_404_0 = (string_drop stringappend_401_0 stringappend_403_0) in
+                         if ((case ((sep_matches_prefix stringappend_404_0)) of
+                             SOME (stringappend_405_0,stringappend_406_0) =>
+                              let stringappend_407_0 =
+                                (string_drop stringappend_404_0 stringappend_406_0) in
+                              if ((case ((reg_name_matches_prefix stringappend_407_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_408_0,stringappend_409_0) => 
+  (case ((string_drop stringappend_407_0 stringappend_409_0)) of   s_ => T )
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_398_0 = (string_drop stringappend_0_0 ((string_length "sfence.vma"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_398_0)) of
+        SOME (stringappend_399_0,stringappend_400_0) => (stringappend_399_0, stringappend_400_0)
+  ) of
+      (() , stringappend_400_0) =>
+  let stringappend_401_0 = (string_drop stringappend_398_0 stringappend_400_0) in
+  let (rs1, stringappend_403_0) =
+      ((case ((reg_name_matches_prefix stringappend_401_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_402_0,stringappend_403_0) => (stringappend_402_0, stringappend_403_0)
+       )) in
+  let stringappend_404_0 = (string_drop stringappend_401_0 stringappend_403_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_404_0)) of
+        SOME (stringappend_405_0,stringappend_406_0) => (stringappend_405_0, stringappend_406_0)
+  ) of
+      (() , stringappend_406_0) =>
+  let stringappend_407_0 = (string_drop stringappend_404_0 stringappend_406_0) in
+  let (rs2, stringappend_409_0) =
+      ((case ((reg_name_matches_prefix stringappend_407_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_408_0,stringappend_409_0) => (stringappend_408_0, stringappend_409_0)
+       )) in
+  (case ((string_drop stringappend_407_0 stringappend_409_0)) of
+        s_ => SOME
+                (SFENCE_VMA (rs1,rs2), ((string_length arg_)) -
+                                         ((string_length s_)))
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "lr.")) /\ (let stringappend_411_0 = (string_drop stringappend_0_0 ((string_length "lr."))) in
+               if ((case ((maybe_aq_matches_prefix stringappend_411_0)) of
+                   SOME (stringappend_412_0,stringappend_413_0) =>
+                    let stringappend_414_0 = (string_drop stringappend_411_0 stringappend_413_0) in
+                    if ((case ((maybe_rl_matches_prefix stringappend_414_0)) of
+                        SOME (stringappend_415_0,stringappend_416_0) =>
+                         let stringappend_417_0 = (string_drop stringappend_414_0 stringappend_416_0) in
+                         if ((case ((size_mnemonic_matches_prefix stringappend_417_0)) of
+                             SOME (stringappend_418_0,stringappend_419_0) =>
+                              let stringappend_420_0 =
+                                (string_drop stringappend_417_0 stringappend_419_0) in
+                              if ((case ((spc_matches_prefix stringappend_420_0)) of
+                                  SOME (stringappend_421_0,stringappend_422_0) =>
+                                   let stringappend_423_0 =
+                                     (string_drop stringappend_420_0 stringappend_422_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_423_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_424_0,stringappend_425_0) =>
+                                        let stringappend_426_0 =
+                                          (string_drop stringappend_423_0 stringappend_425_0) in
+                                        if ((case ((sep_matches_prefix stringappend_426_0)) of
+                                            SOME (stringappend_427_0,stringappend_428_0) =>
+                                             let stringappend_429_0 =
+                                               (string_drop stringappend_426_0 stringappend_428_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_429_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_430_0,stringappend_431_0) => 
+  (case ((string_drop stringappend_429_0 stringappend_431_0)) of   s_ => T )
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_411_0 = (string_drop stringappend_0_0 ((string_length "lr."))) in
+     let (aq, stringappend_413_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_411_0)) of
+         SOME (stringappend_412_0,stringappend_413_0) => (stringappend_412_0, stringappend_413_0)
+       )) in
+     let stringappend_414_0 = (string_drop stringappend_411_0 stringappend_413_0) in
+     let (rl, stringappend_416_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_414_0)) of
+         SOME (stringappend_415_0,stringappend_416_0) => (stringappend_415_0, stringappend_416_0)
+       )) in
+     let stringappend_417_0 = (string_drop stringappend_414_0 stringappend_416_0) in
+     let (size1, stringappend_419_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_417_0)) of
+         SOME (stringappend_418_0,stringappend_419_0) => (stringappend_418_0, stringappend_419_0)
+       )) in
+     let stringappend_420_0 = (string_drop stringappend_417_0 stringappend_419_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_420_0)) of
+        SOME (stringappend_421_0,stringappend_422_0) => (stringappend_421_0, stringappend_422_0)
+  ) of
+      (() , stringappend_422_0) =>
+  let stringappend_423_0 = (string_drop stringappend_420_0 stringappend_422_0) in
+  let (rd, stringappend_425_0) =
+      ((case ((reg_name_matches_prefix stringappend_423_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_424_0,stringappend_425_0) => (stringappend_424_0, stringappend_425_0)
+       )) in
+  let stringappend_426_0 = (string_drop stringappend_423_0 stringappend_425_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_426_0)) of
+        SOME (stringappend_427_0,stringappend_428_0) => (stringappend_427_0, stringappend_428_0)
+  ) of
+      (() , stringappend_428_0) =>
+  let stringappend_429_0 = (string_drop stringappend_426_0 stringappend_428_0) in
+  let (rs1, stringappend_431_0) =
+      ((case ((reg_name_matches_prefix stringappend_429_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_430_0,stringappend_431_0) => (stringappend_430_0, stringappend_431_0)
+       )) in
+  (case ((string_drop stringappend_429_0 stringappend_431_0)) of
+        s_ =>
+  SOME
+    (LOADRES (aq,rl,rs1,size1,rd), ((string_length arg_)) -
+                                     ((string_length s_)))
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "sc.")) /\ (let stringappend_433_0 = (string_drop stringappend_0_0 ((string_length "sc."))) in
+               if ((case ((maybe_aq_matches_prefix stringappend_433_0)) of
+                   SOME (stringappend_434_0,stringappend_435_0) =>
+                    let stringappend_436_0 = (string_drop stringappend_433_0 stringappend_435_0) in
+                    if ((case ((maybe_rl_matches_prefix stringappend_436_0)) of
+                        SOME (stringappend_437_0,stringappend_438_0) =>
+                         let stringappend_439_0 = (string_drop stringappend_436_0 stringappend_438_0) in
+                         if ((case ((size_mnemonic_matches_prefix stringappend_439_0)) of
+                             SOME (stringappend_440_0,stringappend_441_0) =>
+                              let stringappend_442_0 =
+                                (string_drop stringappend_439_0 stringappend_441_0) in
+                              if ((case ((spc_matches_prefix stringappend_442_0)) of
+                                  SOME (stringappend_443_0,stringappend_444_0) =>
+                                   let stringappend_445_0 =
+                                     (string_drop stringappend_442_0 stringappend_444_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_445_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_446_0,stringappend_447_0) =>
+                                        let stringappend_448_0 =
+                                          (string_drop stringappend_445_0 stringappend_447_0) in
+                                        if ((case ((sep_matches_prefix stringappend_448_0)) of
+                                            SOME (stringappend_449_0,stringappend_450_0) =>
+                                             let stringappend_451_0 =
+                                               (string_drop stringappend_448_0 stringappend_450_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_451_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_452_0,stringappend_453_0) =>
+                                                  let stringappend_454_0 =
+                                                    (string_drop stringappend_451_0
+                                                      stringappend_453_0) in
+                                                  if ((case ((sep_matches_prefix stringappend_454_0)) of
+                                                      SOME (stringappend_455_0,stringappend_456_0) =>
+                                                       let stringappend_457_0 =
+                                                         (string_drop stringappend_454_0
+                                                           stringappend_456_0) in
+                                                       if ((case ((reg_name_matches_prefix
+                                                                     stringappend_457_0
+                                                                    :  (( 5 words$word # ii))option)) of
+                                                           SOME
+                                                           (stringappend_458_0,stringappend_459_0) => 
+  (case ((string_drop stringappend_457_0 stringappend_459_0)) of   s_ => T )
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_433_0 = (string_drop stringappend_0_0 ((string_length "sc."))) in
+     let (aq, stringappend_435_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_433_0)) of
+         SOME (stringappend_434_0,stringappend_435_0) => (stringappend_434_0, stringappend_435_0)
+       )) in
+     let stringappend_436_0 = (string_drop stringappend_433_0 stringappend_435_0) in
+     let (rl, stringappend_438_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_436_0)) of
+         SOME (stringappend_437_0,stringappend_438_0) => (stringappend_437_0, stringappend_438_0)
+       )) in
+     let stringappend_439_0 = (string_drop stringappend_436_0 stringappend_438_0) in
+     let (size1, stringappend_441_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_439_0)) of
+         SOME (stringappend_440_0,stringappend_441_0) => (stringappend_440_0, stringappend_441_0)
+       )) in
+     let stringappend_442_0 = (string_drop stringappend_439_0 stringappend_441_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_442_0)) of
+        SOME (stringappend_443_0,stringappend_444_0) => (stringappend_443_0, stringappend_444_0)
+  ) of
+      (() , stringappend_444_0) =>
+  let stringappend_445_0 = (string_drop stringappend_442_0 stringappend_444_0) in
+  let (rd, stringappend_447_0) =
+      ((case ((reg_name_matches_prefix stringappend_445_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_446_0,stringappend_447_0) => (stringappend_446_0, stringappend_447_0)
+       )) in
+  let stringappend_448_0 = (string_drop stringappend_445_0 stringappend_447_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_448_0)) of
+        SOME (stringappend_449_0,stringappend_450_0) => (stringappend_449_0, stringappend_450_0)
+  ) of
+      (() , stringappend_450_0) =>
+  let stringappend_451_0 = (string_drop stringappend_448_0 stringappend_450_0) in
+  let (rs1, stringappend_453_0) =
+      ((case ((reg_name_matches_prefix stringappend_451_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_452_0,stringappend_453_0) => (stringappend_452_0, stringappend_453_0)
+       )) in
+  let stringappend_454_0 = (string_drop stringappend_451_0 stringappend_453_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_454_0)) of
+        SOME (stringappend_455_0,stringappend_456_0) => (stringappend_455_0, stringappend_456_0)
+  ) of
+      (() , stringappend_456_0) =>
+  let stringappend_457_0 = (string_drop stringappend_454_0 stringappend_456_0) in
+  let (rs2, stringappend_459_0) =
+      ((case ((reg_name_matches_prefix stringappend_457_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_458_0,stringappend_459_0) => (stringappend_458_0, stringappend_459_0)
+       )) in
+  (case ((string_drop stringappend_457_0 stringappend_459_0)) of
+        s_ =>
+  SOME
+    (STORECON (aq,rl,rs2,rs1,size1,rd),
+    ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((amo_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_461_0,stringappend_462_0) =>
+        let stringappend_463_0 = (string_drop stringappend_0_0 stringappend_462_0) in
+        if (((((string_startswith stringappend_463_0 ".")) /\ (let stringappend_464_0 = (string_drop stringappend_463_0 ((string_length "."))) in
+               if ((case ((size_mnemonic_matches_prefix stringappend_464_0)) of
+                   SOME (stringappend_465_0,stringappend_466_0) =>
+                    let stringappend_467_0 = (string_drop stringappend_464_0 stringappend_466_0) in
+                    if ((case ((maybe_aq_matches_prefix stringappend_467_0)) of
+                        SOME (stringappend_468_0,stringappend_469_0) =>
+                         let stringappend_470_0 = (string_drop stringappend_467_0 stringappend_469_0) in
+                         if ((case ((maybe_rl_matches_prefix stringappend_470_0)) of
+                             SOME (stringappend_471_0,stringappend_472_0) =>
+                              let stringappend_473_0 =
+                                (string_drop stringappend_470_0 stringappend_472_0) in
+                              if ((case ((spc_matches_prefix stringappend_473_0)) of
+                                  SOME (stringappend_474_0,stringappend_475_0) =>
+                                   let stringappend_476_0 =
+                                     (string_drop stringappend_473_0 stringappend_475_0) in
+                                   if ((case ((reg_name_matches_prefix stringappend_476_0
+                                                :  (( 5 words$word # ii))option)) of
+                                       SOME (stringappend_477_0,stringappend_478_0) =>
+                                        let stringappend_479_0 =
+                                          (string_drop stringappend_476_0 stringappend_478_0) in
+                                        if ((case ((sep_matches_prefix stringappend_479_0)) of
+                                            SOME (stringappend_480_0,stringappend_481_0) =>
+                                             let stringappend_482_0 =
+                                               (string_drop stringappend_479_0 stringappend_481_0) in
+                                             if ((case ((reg_name_matches_prefix stringappend_482_0
+                                                          :  (( 5 words$word # ii))option)) of
+                                                 SOME (stringappend_483_0,stringappend_484_0) =>
+                                                  let stringappend_485_0 =
+                                                    (string_drop stringappend_482_0
+                                                      stringappend_484_0) in
+                                                  if ((case ((sep_matches_prefix stringappend_485_0)) of
+                                                      SOME (stringappend_486_0,stringappend_487_0) =>
+                                                       let stringappend_488_0 =
+                                                         (string_drop stringappend_485_0
+                                                           stringappend_487_0) in
+                                                       if ((case ((reg_name_matches_prefix
+                                                                     stringappend_488_0
+                                                                    :  (( 5 words$word # ii))option)) of
+                                                           SOME
+                                                           (stringappend_489_0,stringappend_490_0) => 
+  (case ((string_drop stringappend_488_0 stringappend_490_0)) of   s_ => T )
+                                                         | NONE => F
+                                                         )) then
+                                                         T
+                                                       else F
+                                                    | NONE => F
+                                                    )) then
+                                                    T
+                                                  else F
+                                               | NONE => F
+                                               )) then
+                                               T
+                                             else F
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_462_0) =
+       ((case ((amo_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_461_0,stringappend_462_0) => (stringappend_461_0, stringappend_462_0)
+       )) in
+     let stringappend_463_0 = (string_drop stringappend_0_0 stringappend_462_0) in
+     let stringappend_464_0 = (string_drop stringappend_463_0 ((string_length "."))) in
+     let (width, stringappend_466_0) =
+       ((case ((size_mnemonic_matches_prefix stringappend_464_0)) of
+         SOME (stringappend_465_0,stringappend_466_0) => (stringappend_465_0, stringappend_466_0)
+       )) in
+     let stringappend_467_0 = (string_drop stringappend_464_0 stringappend_466_0) in
+     let (aq, stringappend_469_0) =
+       ((case ((maybe_aq_matches_prefix stringappend_467_0)) of
+         SOME (stringappend_468_0,stringappend_469_0) => (stringappend_468_0, stringappend_469_0)
+       )) in
+     let stringappend_470_0 = (string_drop stringappend_467_0 stringappend_469_0) in
+     let (rl, stringappend_472_0) =
+       ((case ((maybe_rl_matches_prefix stringappend_470_0)) of
+         SOME (stringappend_471_0,stringappend_472_0) => (stringappend_471_0, stringappend_472_0)
+       )) in
+     let stringappend_473_0 = (string_drop stringappend_470_0 stringappend_472_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_473_0)) of
+        SOME (stringappend_474_0,stringappend_475_0) => (stringappend_474_0, stringappend_475_0)
+  ) of
+      (() , stringappend_475_0) =>
+  let stringappend_476_0 = (string_drop stringappend_473_0 stringappend_475_0) in
+  let (rd, stringappend_478_0) =
+      ((case ((reg_name_matches_prefix stringappend_476_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_477_0,stringappend_478_0) => (stringappend_477_0, stringappend_478_0)
+       )) in
+  let stringappend_479_0 = (string_drop stringappend_476_0 stringappend_478_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_479_0)) of
+        SOME (stringappend_480_0,stringappend_481_0) => (stringappend_480_0, stringappend_481_0)
+  ) of
+      (() , stringappend_481_0) =>
+  let stringappend_482_0 = (string_drop stringappend_479_0 stringappend_481_0) in
+  let (rs1, stringappend_484_0) =
+      ((case ((reg_name_matches_prefix stringappend_482_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_483_0,stringappend_484_0) => (stringappend_483_0, stringappend_484_0)
+       )) in
+  let stringappend_485_0 = (string_drop stringappend_482_0 stringappend_484_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_485_0)) of
+        SOME (stringappend_486_0,stringappend_487_0) => (stringappend_486_0, stringappend_487_0)
+  ) of
+      (() , stringappend_487_0) =>
+  let stringappend_488_0 = (string_drop stringappend_485_0 stringappend_487_0) in
+  let (rs2, stringappend_490_0) =
+      ((case ((reg_name_matches_prefix stringappend_488_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_489_0,stringappend_490_0) => (stringappend_489_0, stringappend_490_0)
+       )) in
+  (case ((string_drop stringappend_488_0 stringappend_490_0)) of
+        s_ =>
+  SOME
+    (AMO (op,aq,rl,rs2,rs1,width,rd),
+    ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_492_0,stringappend_493_0) =>
+        let stringappend_494_0 = (string_drop stringappend_0_0 stringappend_493_0) in
+        if (((((string_startswith stringappend_494_0 "i")) /\ (let stringappend_495_0 = (string_drop stringappend_494_0 ((string_length "i"))) in
+               if ((case ((spc_matches_prefix stringappend_495_0)) of
+                   SOME (stringappend_496_0,stringappend_497_0) =>
+                    let stringappend_498_0 = (string_drop stringappend_495_0 stringappend_497_0) in
+                    if ((case ((reg_name_matches_prefix stringappend_498_0
+                                 :  (( 5 words$word # ii))option)) of
+                        SOME (stringappend_499_0,stringappend_500_0) =>
+                         let stringappend_501_0 = (string_drop stringappend_498_0 stringappend_500_0) in
+                         if ((case ((sep_matches_prefix stringappend_501_0)) of
+                             SOME (stringappend_502_0,stringappend_503_0) =>
+                              let stringappend_504_0 =
+                                (string_drop stringappend_501_0 stringappend_503_0) in
+                              if ((case ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_504_0
+                                           :  (( 5 words$word # ii))option)) of
+                                  SOME (stringappend_505_0,stringappend_506_0) =>
+                                   let stringappend_507_0 =
+                                     (string_drop stringappend_504_0 stringappend_506_0) in
+                                   if ((case ((sep_matches_prefix stringappend_507_0)) of
+                                       SOME (stringappend_508_0,stringappend_509_0) =>
+                                        let stringappend_510_0 =
+                                          (string_drop stringappend_507_0 stringappend_509_0) in
+                                        if ((case ((csr_name_map_matches_prefix stringappend_510_0
+                                                     :  (( 12 words$word # ii))option)) of
+                                            SOME (stringappend_511_0,stringappend_512_0) => 
+  (case ((string_drop stringappend_510_0 stringappend_512_0)) of   s_ => T )
+                                          | NONE => F
+                                          )) then
+                                          T
+                                        else F
+                                     | NONE => F
+                                     )) then
+                                     T
+                                   else F
+                                | NONE => F
+                                )) then
+                                T
+                              else F
+                           | NONE => F
+                           )) then
+                           T
+                         else F
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_493_0) =
+       ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_492_0,stringappend_493_0) => (stringappend_492_0, stringappend_493_0)
+       )) in
+     let stringappend_494_0 = (string_drop stringappend_0_0 stringappend_493_0) in
+     let stringappend_495_0 = (string_drop stringappend_494_0 ((string_length "i"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_495_0)) of
+        SOME (stringappend_496_0,stringappend_497_0) => (stringappend_496_0, stringappend_497_0)
+  ) of
+      (() , stringappend_497_0) =>
+  let stringappend_498_0 = (string_drop stringappend_495_0 stringappend_497_0) in
+  let (rd, stringappend_500_0) =
+      ((case ((reg_name_matches_prefix stringappend_498_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_499_0,stringappend_500_0) => (stringappend_499_0, stringappend_500_0)
+       )) in
+  let stringappend_501_0 = (string_drop stringappend_498_0 stringappend_500_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_501_0)) of
+        SOME (stringappend_502_0,stringappend_503_0) => (stringappend_502_0, stringappend_503_0)
+  ) of
+      (() , stringappend_503_0) =>
+  let stringappend_504_0 = (string_drop stringappend_501_0 stringappend_503_0) in
+  let (rs1, stringappend_506_0) =
+      ((case ((hex_bits_5_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_504_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_505_0,stringappend_506_0) => (stringappend_505_0, stringappend_506_0)
+       )) in
+  let stringappend_507_0 = (string_drop stringappend_504_0 stringappend_506_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_507_0)) of
+        SOME (stringappend_508_0,stringappend_509_0) => (stringappend_508_0, stringappend_509_0)
+  ) of
+      (() , stringappend_509_0) =>
+  let stringappend_510_0 = (string_drop stringappend_507_0 stringappend_509_0) in
+  let (csr, stringappend_512_0) =
+      ((case ((csr_name_map_matches_prefix stringappend_510_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_511_0,stringappend_512_0) => (stringappend_511_0, stringappend_512_0)
+       )) in
+  (case ((string_drop stringappend_510_0 stringappend_512_0)) of
+        s_ =>
+  SOME (CSR (csr,rs1,rd,T,op), ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of
+       SOME (stringappend_514_0,stringappend_515_0) =>
+        let stringappend_516_0 = (string_drop stringappend_0_0 stringappend_515_0) in
+        if ((case ((spc_matches_prefix stringappend_516_0)) of
+            SOME (stringappend_517_0,stringappend_518_0) =>
+             let stringappend_519_0 = (string_drop stringappend_516_0 stringappend_518_0) in
+             if ((case ((reg_name_matches_prefix stringappend_519_0  :  (( 5 words$word # ii))option)) of
+                 SOME (stringappend_520_0,stringappend_521_0) =>
+                  let stringappend_522_0 = (string_drop stringappend_519_0 stringappend_521_0) in
+                  if ((case ((sep_matches_prefix stringappend_522_0)) of
+                      SOME (stringappend_523_0,stringappend_524_0) =>
+                       let stringappend_525_0 = (string_drop stringappend_522_0 stringappend_524_0) in
+                       if ((case ((reg_name_matches_prefix stringappend_525_0
+                                    :  (( 5 words$word # ii))option)) of
+                           SOME (stringappend_526_0,stringappend_527_0) =>
+                            let stringappend_528_0 =
+                              (string_drop stringappend_525_0 stringappend_527_0) in
+                            if ((case ((sep_matches_prefix stringappend_528_0)) of
+                                SOME (stringappend_529_0,stringappend_530_0) =>
+                                 let stringappend_531_0 =
+                                   (string_drop stringappend_528_0 stringappend_530_0) in
+                                 if ((case ((csr_name_map_matches_prefix stringappend_531_0
+                                              :  (( 12 words$word # ii))option)) of
+                                     SOME (stringappend_532_0,stringappend_533_0) => 
+  (case ((string_drop stringappend_531_0 stringappend_533_0)) of   s_ => T )
+                                   | NONE => F
+                                   )) then
+                                   T
+                                 else F
+                              | NONE => F
+                              )) then
+                              T
+                            else F
+                         | NONE => F
+                         )) then
+                         T
+                       else F
+                    | NONE => F
+                    )) then
+                    T
+                  else F
+               | NONE => F
+               )) then
+               T
+             else F
+          | NONE => F
+          )) then
+          T
+        else F
+     | NONE => F
+     )) then
+     let (op, stringappend_515_0) =
+       ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of
+         SOME (stringappend_514_0,stringappend_515_0) => (stringappend_514_0, stringappend_515_0)
+       )) in
+     let stringappend_516_0 = (string_drop stringappend_0_0 stringappend_515_0) in  
+  (case
+  (case ((spc_matches_prefix stringappend_516_0)) of
+        SOME (stringappend_517_0,stringappend_518_0) => (stringappend_517_0, stringappend_518_0)
+  ) of
+      (() , stringappend_518_0) =>
+  let stringappend_519_0 = (string_drop stringappend_516_0 stringappend_518_0) in
+  let (rd, stringappend_521_0) =
+      ((case ((reg_name_matches_prefix stringappend_519_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_520_0,stringappend_521_0) => (stringappend_520_0, stringappend_521_0)
+       )) in
+  let stringappend_522_0 = (string_drop stringappend_519_0 stringappend_521_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_522_0)) of
+        SOME (stringappend_523_0,stringappend_524_0) => (stringappend_523_0, stringappend_524_0)
+  ) of
+      (() , stringappend_524_0) =>
+  let stringappend_525_0 = (string_drop stringappend_522_0 stringappend_524_0) in
+  let (rs1, stringappend_527_0) =
+      ((case ((reg_name_matches_prefix stringappend_525_0 : (( 5 words$word # ii)) option)) of
+             SOME (stringappend_526_0,stringappend_527_0) => (stringappend_526_0, stringappend_527_0)
+       )) in
+  let stringappend_528_0 = (string_drop stringappend_525_0 stringappend_527_0) in
+  (case
+  (case ((sep_matches_prefix stringappend_528_0)) of
+        SOME (stringappend_529_0,stringappend_530_0) => (stringappend_529_0, stringappend_530_0)
+  ) of
+      (() , stringappend_530_0) =>
+  let stringappend_531_0 = (string_drop stringappend_528_0 stringappend_530_0) in
+  let (csr, stringappend_533_0) =
+      ((case ((csr_name_map_matches_prefix stringappend_531_0 : (( 12 words$word # ii)) option)) of
+             SOME (stringappend_532_0,stringappend_533_0) => (stringappend_532_0, stringappend_533_0)
+       )) in
+  (case ((string_drop stringappend_531_0 stringappend_533_0)) of
+        s_ =>
+  SOME (CSR (csr,rs1,rd,F,op), ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+  )
+  )
+   else if (((((string_startswith stringappend_0_0 "illegal")) /\ (let stringappend_535_0 = (string_drop stringappend_0_0 ((string_length "illegal"))) in
+               if ((case ((spc_matches_prefix stringappend_535_0)) of
+                   SOME (stringappend_536_0,stringappend_537_0) =>
+                    let stringappend_538_0 = (string_drop stringappend_535_0 stringappend_537_0) in
+                    if ((case ((hex_bits_32_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_538_0
+                                 :  (( 32 words$word # ii))option)) of
+                        SOME (stringappend_539_0,stringappend_540_0) => 
+  (case ((string_drop stringappend_538_0 stringappend_540_0)) of   s_ => T )
+                      | NONE => F
+                      )) then
+                      T
+                    else F
+                 | NONE => F
+                 )) then
+                 T
+               else F)))) then
+     let stringappend_535_0 = (string_drop stringappend_0_0 ((string_length "illegal"))) in  
+  (case
+  (case ((spc_matches_prefix stringappend_535_0)) of
+        SOME (stringappend_536_0,stringappend_537_0) => (stringappend_536_0, stringappend_537_0)
+  ) of
+      (() , stringappend_537_0) =>
+  let stringappend_538_0 = (string_drop stringappend_535_0 stringappend_537_0) in
+  let (s, stringappend_540_0) =
+      ((case ((hex_bits_32_matches_prefix
+                 instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                 stringappend_538_0 : (( 32 words$word # ii)) option)) of
+             SOME (stringappend_539_0,stringappend_540_0) => (stringappend_539_0, stringappend_540_0)
+       )) in
+  (case ((string_drop stringappend_538_0 stringappend_540_0)) of
+        s_ => SOME (ILLEGAL s, ((string_length arg_)) - ((string_length s_)))
+  )
+  )
+   else NONE))`;
+
+
+(*val encdec_forwards : ast -> mword ty32*)
+
+val _ = Define `
+ ((encdec_forwards:ast ->(32)words$word) arg_=
+    ((case arg_ of
+     UTYPE (imm,rd,op) =>
+      (concat_vec imm ((concat_vec rd ((encdec_uop_forwards op  :  7 words$word))  :  12 words$word))
+        :  32 words$word)
+   | RISCV_JAL (v__172,rd) =>
+      let (imm_19 : 1 bits) = ((subrange_vec_dec v__172 (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)) in
+      let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__172 (( 19 : int):ii) (( 12 : int):ii)  :  8 words$word)) in
+      let (imm_8 : 1 bits) = ((subrange_vec_dec v__172 (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)) in
+      let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__172 (( 10 : int):ii) (( 5 : int):ii)  :  6 words$word)) in
+      let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__172 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word)) in
+      (concat_vec imm_19
+         ((concat_vec imm_18_13
+             ((concat_vec imm_12_9
+                 ((concat_vec imm_8
+                     ((concat_vec imm_7_0
+                         ((concat_vec rd (vec_of_bits [B1;B1;B0;B1;B1;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  20 words$word))
+                    :  21 words$word))
+                :  25 words$word))
+            :  31 words$word))
+        :  32 words$word)
+   | RISCV_JALR (imm,rs1,rd) =>
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                 ((concat_vec rd (vec_of_bits [B1;B1;B0;B0;B1;B1;B1]  :  7 words$word)  :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | BTYPE (v__173,rs2,rs1,op) =>
+      let (imm7_6 : 1 bits) = ((subrange_vec_dec v__173 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+      let (imm5_0 : 1 bits) = ((subrange_vec_dec v__173 (( 11 : int):ii) (( 11 : int):ii)  :  1 words$word)) in
+      let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__173 (( 10 : int):ii) (( 5 : int):ii)  :  6 words$word)) in
+      let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__173 (( 4 : int):ii) (( 1 : int):ii)  :  4 words$word)) in
+      (concat_vec imm7_6
+         ((concat_vec imm7_5_0
+             ((concat_vec rs2
+                 ((concat_vec rs1
+                     ((concat_vec ((encdec_bop_forwards op  :  3 words$word))
+                         ((concat_vec imm5_4_1
+                             ((concat_vec imm5_0 (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word)
+                                :  8 words$word))
+                            :  12 words$word))
+                        :  15 words$word))
+                    :  20 words$word))
+                :  25 words$word))
+            :  31 words$word))
+        :  32 words$word)
+   | ITYPE (imm,rs1,rd,op) =>
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec ((encdec_iop_forwards op  :  3 words$word))
+                 ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  26 words$word))
+        :  32 words$word)
+   | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  26 words$word))
+        :  32 words$word)
+   | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) =>
+      (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0]  :  6 words$word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  26 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_ADD) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_SUB) =>
+      (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_SLL) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_SLT) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B1;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_SLTU) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B1;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_XOR) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_SRL) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_SRA) =>
+      (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_OR) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B1;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPE (rs2,rs1,rd,RISCV_AND) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B1;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | LOAD (imm,rs1,rd,is_unsigned,size1,F,F) =>
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec ((bool_bits_forwards is_unsigned  :  1 words$word))
+                 ((concat_vec ((size_bits_forwards size1  :  2 words$word))
+                     ((concat_vec rd (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  14 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | STORE (v__174,rs2,rs1,size1,F,F) =>
+      let (imm7 : 7 bits) = ((subrange_vec_dec v__174 (( 11 : int):ii) (( 5 : int):ii)  :  7 words$word)) in
+      let (imm5 : 5 bits) = ((subrange_vec_dec v__174 (( 4 : int):ii) (( 0 : int):ii)  :  5 words$word)) in
+      (concat_vec imm7
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                     ((concat_vec ((size_bits_forwards size1  :  2 words$word))
+                         ((concat_vec imm5 (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  14 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | ADDIW (imm,rs1,rd) =>
-      STRCAT "addiw "
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
-   | SHIFTW (shamt,rs1,rd,op) =>
-      let (insn : string) =
-        ((case op of   RISCV_SLLI => "slli  " | RISCV_SRLI => "srli  " | RISCV_SRAI => "srai  " )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt))))))))))
-   | RTYPEW (rs2,rs1,rd,op) =>
-      let (insn : string) =
-        ((case op of
-          RISCV_ADDW => "addw  "
-        | RISCV_SUBW => "subw  "
-        | RISCV_SLLW => "sllw  "
-        | RISCV_SRLW => "srlw  "
-        | RISCV_SRAW => "sraw  "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                 ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | SHIFTW (shamt,rs1,rd,RISCV_SLLI) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | SHIFTW (shamt,rs1,rd,RISCV_SRLI) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | SHIFTW (shamt,rs1,rd,RISCV_SRAI) =>
+      (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPEW (rs2,rs1,rd,RISCV_ADDW) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPEW (rs2,rs1,rd,RISCV_SUBW) =>
+      (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPEW (rs2,rs1,rd,RISCV_SLLW) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPEW (rs2,rs1,rd,RISCV_SRLW) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | RTYPEW (rs2,rs1,rd,RISCV_SRAW) =>
+      (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0;B1]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | MUL (rs2,rs1,rd,high,signed1,signed2) =>
-      let (insn : string) =
-        ((case (high, signed1, signed2) of
-          (F, T, T) => "mul   "
-        | (T, T, T) => "mulh  "
-        | (T, T, F) => "mulhsu "
-        | (T, F, F) => "mulhu"
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec ((encdec_mul_op_forwards high signed1 signed2  :  3 words$word))
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | DIV0 (rs2,rs1,rd,s) =>
-      let (insn : string) = (if s then "div   " else "divu  ") in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0]  :  2 words$word)
+                     ((concat_vec ((bool_not_bits_forwards s  :  1 words$word))
+                         ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  13 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | REM (rs2,rs1,rd,s) =>
-      let (insn : string) = (if s then "rem   " else "remu  ") in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B1]  :  2 words$word)
+                     ((concat_vec ((bool_not_bits_forwards s  :  1 words$word))
+                         ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  13 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | MULW (rs2,rs1,rd) =>
-      STRCAT "mulw  "
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | DIVW (rs2,rs1,rd,s) =>
-      let (insn : string) = (if s then "divw  " else "divuw ") in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B0]  :  2 words$word)
+                     ((concat_vec ((bool_not_bits_forwards s  :  1 words$word))
+                         ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  13 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
    | REMW (rs2,rs1,rd,s) =>
-      let (insn : string) = (if s then "remw  " else "remuw ") in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
-   | FENCE (pred,succ) => "fence"
-   | FENCEI (g__93) => "fence.i"
-   | ECALL (g__94) => "ecall"
-   | MRET (g__95) => "mret"
-   | SRET (g__96) => "sret"
-   | EBREAK (g__97) => "ebreak"
-   | WFI (g__98) => "wfi"
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1;B1]  :  2 words$word)
+                     ((concat_vec ((bool_not_bits_forwards s  :  1 words$word))
+                         ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  13 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | FENCE (pred,succ) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+         ((concat_vec pred
+             ((concat_vec succ
+                 ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                     ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                             (vec_of_bits [B0;B0;B0;B1;B1;B1;B1]  :  7 words$word)
+                            :  12 words$word))
+                        :  15 words$word))
+                    :  20 words$word))
+                :  24 words$word))
+            :  28 words$word))
+        :  32 words$word)
+   | FENCEI (() ) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+             ((concat_vec (vec_of_bits [B0;B0;B1]  :  3 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                     (vec_of_bits [B0;B0;B0;B1;B1;B1;B1]  :  7 words$word)
+                    :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | ECALL (() ) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+             ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                     (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                    :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | MRET (() ) =>
+      (concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0]  :  7 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)
+             ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                         (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                        :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | SRET (() ) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)
+             ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                         (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                        :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | EBREAK (() ) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+             ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                     (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                    :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | WFI (() ) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+             ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                     (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                    :  12 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
    | SFENCE_VMA (rs1,rs2) =>
-      STRCAT "sfence.vma "
-        ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))
-   | LOADRES (aq,rl,rs1,width,rd) =>
-      let (insn : string) =
-        ((case width of   WORD => "lr.w  " | DOUBLE => "lr.d  " | _ => "lr.bad " )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs1))))))
-   | STORECON (aq,rl,rs2,rs1,width,rd) =>
-      let (insn : string) =
-        ((case width of   WORD => "sc.w  " | DOUBLE => "sc.d  " | _ => "sc.bad " )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
-   | AMO (op,aq,rl,rs2,rs1,width,rd) =>
-      let (insn : string) =
-        ((case (op, width) of
-          (AMOSWAP, WORD) => "amoswap.w "
-        | (AMOADD, WORD) => "amoadd.w  "
-        | (AMOXOR, WORD) => "amoxor.w  "
-        | (AMOAND, WORD) => "amoand.w  "
-        | (AMOOR, WORD) => "amoor.w   "
-        | (AMOMIN, WORD) => "amomin.w  "
-        | (AMOMAX, WORD) => "amomax.w  "
-        | (AMOMINU, WORD) => "amominu.w "
-        | (AMOMAXU, WORD) => "amomaxu.w "
-        | (AMOSWAP, DOUBLE) => "amoswap.d "
-        | (AMOADD, DOUBLE) => "amoadd.d  "
-        | (AMOXOR, DOUBLE) => "amoxor.d  "
-        | (AMOAND, DOUBLE) => "amoand.d  "
-        | (AMOOR, DOUBLE) => "amoor.d   "
-        | (AMOMIN, DOUBLE) => "amomin.d  "
-        | (AMOMAX, DOUBLE) => "amomax.d  "
-        | (AMOMINU, DOUBLE) => "amominu.d "
-        | (AMOMAXU, DOUBLE) => "amomaxu.d "
-        | (_, _) => "amo.bad "
-        )) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", "
-                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+      (concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1]  :  7 words$word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                     ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                         (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)
+                        :  12 words$word))
+                    :  15 words$word))
+                :  20 words$word))
+            :  25 words$word))
+        :  32 words$word)
+   | LOADRES (aq,rl,rs1,size1,rd) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)
+         ((concat_vec ((bool_bits_forwards aq  :  1 words$word))
+             ((concat_vec ((bool_bits_forwards rl  :  1 words$word))
+                 ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                     ((concat_vec rs1
+                         ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                             ((concat_vec ((size_bits_forwards size1  :  2 words$word))
+                                 ((concat_vec rd (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)
+                                    :  12 words$word))
+                                :  14 words$word))
+                            :  15 words$word))
+                        :  20 words$word))
+                    :  25 words$word))
+                :  26 words$word))
+            :  27 words$word))
+        :  32 words$word)
+   | STORECON (aq,rl,rs2,rs1,size1,rd) =>
+      (concat_vec (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)
+         ((concat_vec ((bool_bits_forwards aq  :  1 words$word))
+             ((concat_vec ((bool_bits_forwards rl  :  1 words$word))
+                 ((concat_vec rs2
+                     ((concat_vec rs1
+                         ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                             ((concat_vec ((size_bits_forwards size1  :  2 words$word))
+                                 ((concat_vec rd (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)
+                                    :  12 words$word))
+                                :  14 words$word))
+                            :  15 words$word))
+                        :  20 words$word))
+                    :  25 words$word))
+                :  26 words$word))
+            :  27 words$word))
+        :  32 words$word)
+   | AMO (op,aq,rl,rs2,rs1,size1,rd) =>
+      (concat_vec ((encdec_amoop_forwards op  :  5 words$word))
+         ((concat_vec ((bool_bits_forwards aq  :  1 words$word))
+             ((concat_vec ((bool_bits_forwards rl  :  1 words$word))
+                 ((concat_vec rs2
+                     ((concat_vec rs1
+                         ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                             ((concat_vec ((size_bits_forwards size1  :  2 words$word))
+                                 ((concat_vec rd (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)
+                                    :  12 words$word))
+                                :  14 words$word))
+                            :  15 words$word))
+                        :  20 words$word))
+                    :  25 words$word))
+                :  26 words$word))
+            :  27 words$word))
+        :  32 words$word)
    | CSR (csr,rs1,rd,is_imm,op) =>
-      let (insn : string) =
-        ((case (op, is_imm) of
-          (CSRRW, T) => "csrrwi "
-        | (CSRRW, F) => "csrrw  "
-        | (CSRRS, T) => "csrrsi "
-        | (CSRRS, F) => "csrrs  "
-        | (CSRRC, T) => "csrrci "
-        | (CSRRC, F) => "csrrc  "
-        )) in
-      let (rs1_str : string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in
-      STRCAT insn
-        ((STRCAT ((reg_name_abi rd))
-            ((STRCAT ", " ((STRCAT rs1_str ((STRCAT ", " ((csr_name csr))))))))))
-   | NOP (g__99) => "nop"
-   | ILLEGAL (g__100) => "illegal"
+      (concat_vec csr
+         ((concat_vec rs1
+             ((concat_vec ((bool_bits_forwards is_imm  :  1 words$word))
+                 ((concat_vec ((encdec_csrop_forwards op  :  2 words$word))
+                     ((concat_vec rd (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)  :  12 words$word))
+                    :  14 words$word))
+                :  15 words$word))
+            :  20 words$word))
+        :  32 words$word)
+   | STOP_FETCHING (() ) =>
+      (concat_vec (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0]  :  16 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+             ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0]  :  2 words$word)
+                     ((concat_vec (vec_of_bits [B0;B1;B0]  :  3 words$word)
+                         (vec_of_bits [B1;B1]  :  2 words$word)
+                        :  5 words$word))
+                    :  7 words$word))
+                :  8 words$word))
+            :  16 words$word))
+        :  32 words$word)
+   | THREAD_START (() ) =>
+      (concat_vec (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0]  :  16 words$word)
+         ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+             ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                 ((concat_vec (vec_of_bits [B0;B0]  :  2 words$word)
+                     ((concat_vec (vec_of_bits [B0;B1;B0]  :  3 words$word)
+                         (vec_of_bits [B1;B1]  :  2 words$word)
+                        :  5 words$word))
+                    :  7 words$word))
+                :  8 words$word))
+            :  16 words$word))
+        :  32 words$word)
+   | ILLEGAL (s) => s
+   )))`;
+
+
+(*val encdec_backwards : mword ty32 -> ast*)
+
+val _ = Define `
+ ((encdec_backwards:(32)words$word -> ast) arg_=
+    (let v__175 = arg_ in
+   if (let mappingpatterns_23_0 = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     encdec_uop_backwards_matches mappingpatterns_23_0) then
+     let (imm :  20 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 12 : int):ii)  :  20 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_23_0 = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     let op = (encdec_uop_backwards mappingpatterns_23_0) in
+     UTYPE (imm,rd,op)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (p0_ = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1]  :  7 words$word))) then
+     let (imm_19 : 1 bits) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) in
+     let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__175 (( 30 : int):ii) (( 25 : int):ii)  :  6 words$word)) in
+     let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 21 : int):ii)  :  4 words$word)) in
+     let (imm_8 : 1 bits) = ((subrange_vec_dec v__175 (( 20 : int):ii) (( 20 : int):ii)  :  1 words$word)) in
+     let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 12 : int):ii)  :  8 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RISCV_JAL ((concat_vec imm_19
+                   ((concat_vec imm_7_0
+                       ((concat_vec imm_8
+                           ((concat_vec imm_18_13
+                               ((concat_vec imm_12_9 (vec_of_bits [B0]  :  1 words$word)  :  5 words$word))
+                              :  11 words$word))
+                          :  12 words$word))
+                      :  20 words$word))
+                  :  21 words$word),rd)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((p1_ = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1]  :  7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))))) then
+     let (imm :  12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RISCV_JALR (imm,rs1,rd)
+   else if (let mappingpatterns_24_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((encdec_bop_backwards_matches mappingpatterns_24_0)) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let (imm7_6 : 1 bits) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 31 : int):ii)  :  1 words$word)) in
+     let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__175 (( 30 : int):ii) (( 25 : int):ii)  :  6 words$word)) in
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_24_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 8 : int):ii)  :  4 words$word)) in
+     let (imm5_0 : 1 bits) = ((subrange_vec_dec v__175 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
+     let op = (encdec_bop_backwards mappingpatterns_24_0) in
+     BTYPE ((concat_vec imm7_6
+               ((concat_vec imm5_0
+                   ((concat_vec imm7_5_0
+                       ((concat_vec imm5_4_1 (vec_of_bits [B0]  :  1 words$word)  :  5 words$word))
+                      :  11 words$word))
+                  :  12 words$word))
+              :  13 words$word),rs2,rs1,op)
+   else if (let mappingpatterns_25_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((encdec_iop_backwards_matches mappingpatterns_25_0)) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let (imm :  12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_25_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let op = (encdec_iop_backwards mappingpatterns_25_0) in
+     ITYPE (imm,rs1,rd,op)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))) then
+     let (shamt :  6 words$word) = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 20 : int):ii)  :  6 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))) then
+     let (shamt :  6 words$word) = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 20 : int):ii)  :  6 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0]  :  6 words$word)))))) then
+     let (shamt :  6 words$word) = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 20 : int):ii)  :  6 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_ADD)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SUB)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SLL)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SLT)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SLTU)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_XOR)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SRL)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SRA)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_OR)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPE (rs2,rs1,rd,RISCV_AND)
+   else if (let mappingpatterns_26_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_27_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_27_0)) /\ ((bool_bits_backwards_matches mappingpatterns_26_0))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let (imm :  12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_26_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_27_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_27_0) in
+     let is_unsigned = (bool_bits_backwards mappingpatterns_26_0) in
+     LOAD (imm,rs1,rd,is_unsigned,size1,F,F)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_28_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_28_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0]  :  1 words$word)))))) then
+     let (imm7 : 7 bits) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_28_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (imm5 : 5 bits) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_28_0) in
+     STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,size1,F,F)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((p1_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))))) then
+     let (imm :  12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     ADDIW (imm,rs1,rd)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (shamt :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     SHIFTW (shamt,rs1,rd,RISCV_SLLI)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (shamt :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     SHIFTW (shamt,rs1,rd,RISCV_SRLI)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (shamt :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     SHIFTW (shamt,rs1,rd,RISCV_SRAI)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_ADDW)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SUBW)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SLLW)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SRLW)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SRAW)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let (mappingpatterns_29_0 : 3 bits) = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((encdec_mul_op_backwards_matches mappingpatterns_29_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (mappingpatterns_29_0 : 3 bits) = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_29_0) in
+     MUL (rs2,rs1,rd,high,signed1,signed2)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_30_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_30_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_30_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_30_0) in
+     DIV0 (rs2,rs1,rd,s)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_31_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_31_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_31_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_31_0) in
+     REM (rs2,rs1,rd,s)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     MULW (rs2,rs1,rd)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_32_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_32_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_32_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_32_0) in
+     DIVW (rs2,rs1,rd,s)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_33_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_33_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_33_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_33_0) in
+     REMW (rs2,rs1,rd,s)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))))) then
+     let (pred :  4 words$word) = ((subrange_vec_dec v__175 (( 27 : int):ii) (( 24 : int):ii)  :  4 words$word)) in
+     let (succ :  4 words$word) = ((subrange_vec_dec v__175 (( 23 : int):ii) (( 20 : int):ii)  :  4 words$word)) in
+     FENCE (pred,succ)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))))) then
+     FENCEI () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))))) then
+     ECALL () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p5_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0]  :  7 words$word)))))) then
+     MRET () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p5_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)))))) then
+     SRET () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))))) then
+     EBREAK () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))))) then
+     WFI () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((p3_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1]  :  7 words$word)))))) then
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     SFENCE_VMA (rs1,rs2)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_34_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_35_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_36_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((((((((((size_bits_backwards_matches mappingpatterns_36_0)) /\ ((bool_bits_backwards_matches mappingpatterns_35_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_34_0))))) /\ (((p3_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))) /\ (((p2_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))))) then
+     let mappingpatterns_34_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_35_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_36_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_36_0) in
+     let rl = (bool_bits_backwards mappingpatterns_35_0) in
+     let aq = (bool_bits_backwards mappingpatterns_34_0) in
+     LOADRES (aq,rl,rs1,size1,rd)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_37_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_38_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_39_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_39_0)) /\ ((bool_bits_backwards_matches mappingpatterns_38_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_37_0))))) /\ (((p2_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))))) then
+     let mappingpatterns_37_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_38_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_39_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_39_0) in
+     let rl = (bool_bits_backwards mappingpatterns_38_0) in
+     let aq = (bool_bits_backwards mappingpatterns_37_0) in
+     STORECON (aq,rl,rs2,rs1,size1,rd)
+   else if (let mappingpatterns_40_0 = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_41_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_42_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_43_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_43_0)) /\ ((bool_bits_backwards_matches mappingpatterns_42_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_41_0))))) /\ ((encdec_amoop_backwards_matches mappingpatterns_40_0))))) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0]  :  1 words$word)))))) then
+     let mappingpatterns_40_0 = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_41_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_42_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let (rs2 :  5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_43_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_43_0) in
+     let rl = (bool_bits_backwards mappingpatterns_42_0) in
+     let aq = (bool_bits_backwards mappingpatterns_41_0) in
+     let op = (encdec_amoop_backwards mappingpatterns_40_0) in
+     AMO (op,aq,rl,rs2,rs1,size1,rd)
+   else if (let mappingpatterns_44_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_45_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((encdec_csrop_backwards_matches mappingpatterns_45_0)) /\ ((bool_bits_backwards_matches mappingpatterns_44_0))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let (csr :  12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let (rs1 :  5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_44_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_45_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let (rd :  5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let op = (encdec_csrop_backwards mappingpatterns_45_0) in
+     let is_imm = (bool_bits_backwards mappingpatterns_44_0) in
+     CSR (csr,rs1,rd,is_imm,op)
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let p5_ = ((subrange_vec_dec v__175 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0]  :  2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0]  :  16 words$word))))))
+   then
+     STOP_FETCHING () 
+   else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word)) in
+     let p1_ = ((subrange_vec_dec v__175 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)) in
+     let p2_ = ((subrange_vec_dec v__175 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
+     let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let p4_ = ((subrange_vec_dec v__175 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let p5_ = ((subrange_vec_dec v__175 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0]  :  2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0]  :  16 words$word))))))
+   then
+     THREAD_START () 
+   else ILLEGAL v__175))`;
+
+
+(*val encdec_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((encdec_forwards_matches:ast -> bool) arg_=
+    ((case arg_ of
+     UTYPE (imm,rd,op) => T
+   | RISCV_JAL (v__224,rd) =>
+      if (let p0_ = ((subrange_vec_dec v__224 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in
+        (p0_ = (vec_of_bits [B0]  :  1 words$word))) then
+        T
+      else
+        let g__17 = (RISCV_JAL (v__224,rd)) in
+        F
+   | RISCV_JALR (imm,rs1,rd) => T
+   | BTYPE (v__225,rs2,rs1,op) =>
+      if (let p0_ = ((subrange_vec_dec v__225 (( 0 : int):ii) (( 0 : int):ii)  :  1 words$word)) in
+        (p0_ = (vec_of_bits [B0]  :  1 words$word))) then
+        T
+      else
+        let g__17 = (BTYPE (v__225,rs2,rs1,op)) in
+        F
+   | ITYPE (imm,rs1,rd,op) => T
+   | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => T
+   | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => T
+   | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => T
+   | RTYPE (rs2,rs1,rd,RISCV_ADD) => T
+   | RTYPE (rs2,rs1,rd,RISCV_SUB) => T
+   | RTYPE (rs2,rs1,rd,RISCV_SLL) => T
+   | RTYPE (rs2,rs1,rd,RISCV_SLT) => T
+   | RTYPE (rs2,rs1,rd,RISCV_SLTU) => T
+   | RTYPE (rs2,rs1,rd,RISCV_XOR) => T
+   | RTYPE (rs2,rs1,rd,RISCV_SRL) => T
+   | RTYPE (rs2,rs1,rd,RISCV_SRA) => T
+   | RTYPE (rs2,rs1,rd,RISCV_OR) => T
+   | RTYPE (rs2,rs1,rd,RISCV_AND) => T
+   | LOAD (imm,rs1,rd,is_unsigned,size1,F,F) => T
+   | STORE (v__226,rs2,rs1,size1,F,F) => T
+   | ADDIW (imm,rs1,rd) => T
+   | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => T
+   | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => T
+   | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => T
+   | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => T
+   | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => T
+   | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => T
+   | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => T
+   | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => T
+   | MUL (rs2,rs1,rd,high,signed1,signed2) => T
+   | DIV0 (rs2,rs1,rd,s) => T
+   | REM (rs2,rs1,rd,s) => T
+   | MULW (rs2,rs1,rd) => T
+   | DIVW (rs2,rs1,rd,s) => T
+   | REMW (rs2,rs1,rd,s) => T
+   | FENCE (pred,succ) => T
+   | FENCEI (() ) => T
+   | ECALL (() ) => T
+   | MRET (() ) => T
+   | SRET (() ) => T
+   | EBREAK (() ) => T
+   | WFI (() ) => T
+   | SFENCE_VMA (rs1,rs2) => T
+   | LOADRES (aq,rl,rs1,size1,rd) => T
+   | STORECON (aq,rl,rs2,rs1,size1,rd) => T
+   | AMO (op,aq,rl,rs2,rs1,size1,rd) => T
+   | CSR (csr,rs1,rd,is_imm,op) => T
+   | STOP_FETCHING (() ) => T
+   | THREAD_START (() ) => T
+   | ILLEGAL (s) => T
+   | g__17 => F
+   )))`;
+
+
+(*val encdec_backwards_matches : mword ty32 -> bool*)
+
+val _ = Define `
+ ((encdec_backwards_matches:(32)words$word -> bool) arg_=
+    (let v__227 = arg_ in
+   if (let mappingpatterns_0_0 = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     encdec_uop_backwards_matches mappingpatterns_0_0) then
+     let mappingpatterns_0_0 = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     let op = (encdec_uop_backwards mappingpatterns_0_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (p0_ = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1]  :  7 words$word))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((p1_ = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1]  :  7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))))) then
+     T
+   else if (let mappingpatterns_1_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((encdec_bop_backwards_matches mappingpatterns_1_0)) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let mappingpatterns_1_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let op = (encdec_bop_backwards mappingpatterns_1_0) in
+     T
+   else if (let mappingpatterns_2_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((encdec_iop_backwards_matches mappingpatterns_2_0)) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let mappingpatterns_2_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let op = (encdec_iop_backwards mappingpatterns_2_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 26 : int):ii)  :  6 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0]  :  6 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let mappingpatterns_3_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_4_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_4_0)) /\ ((bool_bits_backwards_matches mappingpatterns_3_0))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let mappingpatterns_3_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_4_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_4_0) in
+     let is_unsigned = (bool_bits_backwards mappingpatterns_3_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_5_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_5_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0]  :  1 words$word)))))) then
+     let mappingpatterns_5_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_5_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((p1_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0]  :  3 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let (mappingpatterns_6_0 : 3 bits) = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((encdec_mul_op_backwards_matches mappingpatterns_6_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let (mappingpatterns_6_0 : 3 bits) = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_6_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_7_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_7_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let mappingpatterns_7_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_7_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_8_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_8_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let mappingpatterns_8_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_8_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_9_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_9_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let mappingpatterns_9_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_9_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii)  :  2 words$word)) in
+     let mappingpatterns_10_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_10_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1]  :  2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))))) then
+     let mappingpatterns_10_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii)  :  1 words$word)) in
+     let s = (bool_not_bits_backwards mappingpatterns_10_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 28 : int):ii)  :  4 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p5_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p5_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii)  :  12 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii)  :  7 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii)  :  3 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii)  :  5 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((p3_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1]  :  7 words$word)))))) then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_11_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_12_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 24 : int):ii) (( 20 : int):ii)  :  5 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_13_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((((((((((((((size_bits_backwards_matches mappingpatterns_13_0)) /\ ((bool_bits_backwards_matches mappingpatterns_12_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_11_0))))) /\ (((p3_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))) /\ (((p2_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))))) then
+     let mappingpatterns_11_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_12_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_13_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_13_0) in
+     let rl = (bool_bits_backwards mappingpatterns_12_0) in
+     let aq = (bool_bits_backwards mappingpatterns_11_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_14_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_15_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_16_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_16_0)) /\ ((bool_bits_backwards_matches mappingpatterns_15_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_14_0))))) /\ (((p2_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))) /\ (((p1_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))))) then
+     let mappingpatterns_14_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_15_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_16_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_16_0) in
+     let rl = (bool_bits_backwards mappingpatterns_15_0) in
+     let aq = (bool_bits_backwards mappingpatterns_14_0) in
+     T
+   else if (let mappingpatterns_17_0 = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_18_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_19_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_20_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_20_0)) /\ ((bool_bits_backwards_matches mappingpatterns_19_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_18_0))))) /\ ((encdec_amoop_backwards_matches mappingpatterns_17_0))))) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0]  :  1 words$word)))))) then
+     let mappingpatterns_17_0 = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii)  :  5 words$word)) in
+     let mappingpatterns_18_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_19_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_20_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let size1 = (size_bits_backwards mappingpatterns_20_0) in
+     let rl = (bool_bits_backwards mappingpatterns_19_0) in
+     let aq = (bool_bits_backwards mappingpatterns_18_0) in
+     let op = (encdec_amoop_backwards mappingpatterns_17_0) in
+     T
+   else if (let mappingpatterns_21_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_22_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii)  :  7 words$word)) in
+     ((((((encdec_csrop_backwards_matches mappingpatterns_22_0)) /\ ((bool_bits_backwards_matches mappingpatterns_21_0))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))) then
+     let mappingpatterns_21_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii)  :  1 words$word)) in
+     let mappingpatterns_22_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii)  :  2 words$word)) in
+     let op = (encdec_csrop_backwards mappingpatterns_22_0) in
+     let is_imm = (bool_bits_backwards mappingpatterns_21_0) in
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let p5_ = ((subrange_vec_dec v__227 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0]  :  2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0]  :  16 words$word))))))
+   then
+     T
+   else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 16 : int):ii)  :  16 words$word)) in
+     let p1_ = ((subrange_vec_dec v__227 (( 15 : int):ii) (( 8 : int):ii)  :  8 words$word)) in
+     let p2_ = ((subrange_vec_dec v__227 (( 7 : int):ii) (( 7 : int):ii)  :  1 words$word)) in
+     let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 5 : int):ii)  :  2 words$word)) in
+     let p4_ = ((subrange_vec_dec v__227 (( 4 : int):ii) (( 2 : int):ii)  :  3 words$word)) in
+     let p5_ = ((subrange_vec_dec v__227 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) in
+     ((((((((((((((((p5_ = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0]  :  2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0]  :  1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0]  :  16 words$word))))))
+   then
+     T
+   else T))`;
+
+
+val _ = Define `
+ ((print_insn:ast -> string) merge_var=
+    ((case merge_var of
+     NOP (g__13) => "nop"
    | C_ADDI4SPN (rdc,nzimm) =>
       STRCAT "c.addi4spn "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rdc  :  5 words$word))))
-            ((STRCAT ", " ((string_of_vec nzimm))))))
+            ((STRCAT ", " ((string_of_bits nzimm))))))
    | C_LW (uimm,rsc,rdc) =>
       STRCAT "c.lw   "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rdc  :  5 words$word))))
             ((STRCAT ", "
                 ((STRCAT ((reg_name_abi ((creg2reg_bits rsc  :  5 words$word))))
-                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+                    ((STRCAT ", " ((string_of_bits uimm))))))))))
    | C_LD (uimm,rsc,rdc) =>
       STRCAT "c.ld   "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rdc  :  5 words$word))))
             ((STRCAT ", "
                 ((STRCAT ((reg_name_abi ((creg2reg_bits rsc  :  5 words$word))))
-                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+                    ((STRCAT ", " ((string_of_bits uimm))))))))))
    | C_SW (uimm,rsc1,rsc2) =>
       STRCAT "c.sw   "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1  :  5 words$word))))
             ((STRCAT ", "
                 ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2  :  5 words$word))))
-                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+                    ((STRCAT ", " ((string_of_bits uimm))))))))))
    | C_SD (uimm,rsc1,rsc2) =>
       STRCAT "c.sd   "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1  :  5 words$word))))
             ((STRCAT ", "
                 ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2  :  5 words$word))))
-                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+                    ((STRCAT ", " ((string_of_bits uimm))))))))))
    | C_ADDI (nzi,rsd) =>
       STRCAT "c.addi   "
-        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec nzi))))))
-   | C_JAL (imm) => STRCAT "c.jal   " ((string_of_vec imm))
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_bits nzi))))))
+   | C_JAL (imm) => STRCAT "c.jal   " ((string_of_bits imm))
    | C_ADDIW (imm,rsd) =>
       STRCAT "c.addiw "
-        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec imm))))))
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_bits imm))))))
    | C_LI (imm,rd) =>
       STRCAT "c.li  "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
-   | C_ADDI16SP (imm) => STRCAT "c.addi16sp  " ((string_of_vec imm))
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits imm))))))
+   | C_ADDI16SP (imm) => STRCAT "c.addi16sp  " ((string_of_bits imm))
    | C_LUI (imm,rd) =>
       STRCAT "c.lui  "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits imm))))))
    | C_SRLI (shamt,rsd) =>
       STRCAT "c.srli  "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
-            ((STRCAT ", " ((string_of_vec shamt))))))
+            ((STRCAT ", " ((string_of_bits shamt))))))
    | C_SRAI (shamt,rsd) =>
       STRCAT "c.srai  "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
-            ((STRCAT ", " ((string_of_vec shamt))))))
+            ((STRCAT ", " ((string_of_bits shamt))))))
    | C_ANDI (imm,rsd) =>
       STRCAT "c.andi  "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
-            ((STRCAT ", " ((string_of_vec imm))))))
+            ((STRCAT ", " ((string_of_bits imm))))))
    | C_SUB (rsd,rs2) =>
       STRCAT "c.sub  "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
@@ -7451,30 +22851,30 @@ val _ = Define `
       STRCAT "c.addw "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
             ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
-   | C_J (imm) => STRCAT "c.j    " ((string_of_vec imm))
+   | C_J (imm) => STRCAT "c.j    " ((string_of_bits imm))
    | C_BEQZ (imm,rs) =>
       STRCAT "c.beqz "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rs  :  5 words$word))))
-            ((STRCAT ", " ((string_of_vec imm))))))
+            ((STRCAT ", " ((string_of_bits imm))))))
    | C_BNEZ (imm,rs) =>
       STRCAT "c.bnez "
         ((STRCAT ((reg_name_abi ((creg2reg_bits rs  :  5 words$word))))
-            ((STRCAT ", " ((string_of_vec imm))))))
+            ((STRCAT ", " ((string_of_bits imm))))))
    | C_SLLI (shamt,rsd) =>
       STRCAT "c.slli "
-        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec shamt))))))
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_bits shamt))))))
    | C_LWSP (uimm,rd) =>
       STRCAT "c.lwsp "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm))))))
    | C_LDSP (uimm,rd) =>
       STRCAT "c.ldsp "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm))))))
    | C_SWSP (uimm,rd) =>
       STRCAT "c.swsp "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm))))))
    | C_SDSP (uimm,rd) =>
       STRCAT "c.sdsp "
-        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm))))))
    | C_JR (rs1) => STRCAT "c.jr  " ((reg_name_abi rs1))
    | C_JALR (rs1) => STRCAT "c.jalr  " ((reg_name_abi rs1))
    | C_MV (rd,rs2) =>
@@ -7483,9 +22883,18 @@ val _ = Define `
    | C_ADD (rsd,rs2) =>
       STRCAT "c.add  "
         ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((reg_name_abi rs2))))))
+   | STOP_FETCHING (g__14) => "stop_fetching"
+   | THREAD_START (g__15) => "thread_start"
+   | ILLEGAL (s) => STRCAT "illegal " ((string_of_bits s))
+   | C_ILLEGAL (g__16) => "c.illegal"
+   | insn => assembly_forwards insn
    )))`;
 
 
+val _ = Define `
+ ((decode:(32)words$word ->(ast)option) bv=  (SOME ((encdec_backwards bv))))`;
+
+
 (*val isRVC : mword ty16 -> bool*)
 
 val _ = Define `
@@ -7496,42 +22905,42 @@ val _ = Define `
 (*val fetch : unit -> M FetchResult*)
 
 val _ = Define `
- ((fetch:unit ->(regstate)state_monad$sequential_state ->(((FetchResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state$or_boolS
-     ( state_monad$bindS(state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
-      state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):ii)))  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word))))))
-     (state$and_boolS
-        ( state_monad$bindS(state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 : xlenbits) . 
-         state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):ii)))  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word))))))
-        ( state_monad$bindS(haveRVC () ) (\ (w__2 : bool) .  state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . 
-   if w__4 then state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__5 :  64 words$word) . 
-     state_monad$returnS (F_Error (E_Fetch_Addr_Align,w__5)))
-   else state_monad$bindS
-     (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__6 :  64 words$word) .  state_monad$bindS
+ ((fetch:unit ->(regstate)sail2_state_monad$sequential_state ->(((FetchResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =  (sail2_state_monad$bindS
+   (sail2_state$or_boolS
+     ( sail2_state_monad$bindS(sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 : xlenbits) . 
+      sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):ii)))  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word))))))
+     (sail2_state$and_boolS
+        ( sail2_state_monad$bindS(sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 : xlenbits) . 
+         sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):ii)))  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word))))))
+        ( sail2_state_monad$bindS(haveRVC () ) (\ (w__2 : bool) .  sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . 
+   if w__4 then sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__5 :  64 words$word) . 
+     sail2_state_monad$returnS (F_Error (E_Fetch_Addr_Align,w__5)))
+   else sail2_state_monad$bindS
+     (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__6 :  64 words$word) .  sail2_state_monad$bindS
      (translateAddr w__6 Execute Instruction) (\ (w__7 : TR_Result) . 
      (case w__7 of
-       TR_Failure (e) => state_monad$bindS
-        (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__8 :  64 words$word) .  state_monad$returnS (F_Error (e,w__8)))
-     | TR_Address (ppclo) => state_monad$bindS
+       TR_Failure (e) => sail2_state_monad$bindS
+        (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__8 :  64 words$word) .  sail2_state_monad$returnS (F_Error (e,w__8)))
+     | TR_Address (ppclo) => sail2_state_monad$bindS
         (checked_mem_read Instruction ppclo (( 2 : int):ii)  : ( ( 16 words$word)MemoryOpResult) M) (\ (w__9 : ( 16 words$word)
           MemoryOpResult) . 
         (case w__9 of
-          MemException (e) => state_monad$bindS
-           (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__10 :  64 words$word) . 
-           state_monad$returnS (F_Error (E_Fetch_Access_Fault,w__10)))
+          MemException (e) => sail2_state_monad$bindS
+           (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__10 :  64 words$word) . 
+           sail2_state_monad$returnS (F_Error (E_Fetch_Access_Fault,w__10)))
         | MemValue (ilo) =>
-           if ((isRVC ilo)) then state_monad$returnS (F_RVC ilo)
-           else state_monad$bindS
-             (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__11 :  64 words$word) . 
-             let (PChi : xlenbits) = ((add_vec_int w__11 (( 2 : int):ii)  :  64 words$word)) in state_monad$bindS
+           if ((isRVC ilo)) then sail2_state_monad$returnS (F_RVC ilo)
+           else sail2_state_monad$bindS
+             (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__11 :  64 words$word) . 
+             let (PChi : xlenbits) = ((add_vec_int w__11 (( 2 : int):ii)  :  64 words$word)) in sail2_state_monad$bindS
              (translateAddr PChi Execute Instruction) (\ (w__12 : TR_Result) . 
              (case w__12 of
-               TR_Failure (e) => state_monad$returnS (F_Error (e,PChi))
-             | TR_Address (ppchi) => state_monad$bindS
+               TR_Failure (e) => sail2_state_monad$returnS (F_Error (e,PChi))
+             | TR_Address (ppchi) => sail2_state_monad$bindS
                 (checked_mem_read Instruction ppchi (( 2 : int):ii)  : ( ( 16 words$word)MemoryOpResult) M) (\ (w__13 : ( 16 words$word)
                   MemoryOpResult) . 
-                state_monad$returnS ((case w__13 of
+                sail2_state_monad$returnS ((case w__13 of
                   MemException (e) => F_Error (E_Fetch_Access_Fault,PChi)
                 | MemValue (ihi) => F_Base ((concat_vec ihi ilo  :  32 words$word))
                 )))
@@ -7540,77 +22949,566 @@ val _ = Define `
      ))))))`;
 
 
-(*val step : unit -> M bool*)
+(*val step : ii -> M (bool * bool)*)
 
 val _ = Define `
- ((step:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () =  (state_monad$bindS
-   (state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) .  state_monad$bindS
-   (state_monad$read_regS mie_ref) (\ (w__1 : Minterrupts) .  state_monad$bindS
-   (state_monad$read_regS mideleg_ref) (\ (w__2 : Minterrupts) .  state_monad$bindS
-   (curInterrupt w__0 w__1 w__2) (\ (w__3 :  ((InterruptType # Privilege))option) . 
-   (case w__3 of
+ ((step:int ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) step_no=  (sail2_state_monad$bindS
+   (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mip_ref) (\ (w__1 : Minterrupts) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mie_ref) (\ (w__2 : Minterrupts) .  sail2_state_monad$bindS
+   (sail2_state_monad$read_regS mideleg_ref) (\ (w__3 : Minterrupts) .  sail2_state_monad$bindS
+   (curInterrupt w__0 w__1 w__2 w__3) (\ (w__4 :  ((InterruptType # Privilege))option) . 
+   (case w__4 of
      SOME (intr,priv) =>
-      let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr  :  4 words$word))) in state_monad$seqS
-      (handle_interrupt intr priv) (state_monad$returnS F)
-   | NONE => state_monad$bindS
-      (fetch () ) (\ (w__4 : FetchResult) . 
-      (case w__4 of
-        F_Error (e,addr) => state_monad$seqS (handle_mem_exception addr e) (state_monad$returnS F)
+      let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr  :  4 words$word))) in sail2_state_monad$seqS
+      (handle_interrupt intr priv) (sail2_state_monad$returnS (F, F))
+   | NONE => sail2_state_monad$bindS
+      (fetch () ) (\ (w__5 : FetchResult) . 
+      (case w__5 of
+        F_Error (e,addr) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS (F, F))
       | F_RVC (h) =>
          (case ((decodeCompressed h)) of
-           NONE => state_monad$bindS
-            (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__5 : xlenbits) . 
+           NONE => sail2_state_monad$bindS
+            (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__6 : Privilege) .  sail2_state_monad$bindS
+            (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__7 : xlenbits) . 
             let (_ : unit) =
-              (prerr_endline
-                ((STRCAT "PC: "
-                    ((STRCAT ((string_of_vec w__5))
-                        ((STRCAT " instr: "
-                            ((STRCAT ((string_of_vec h)) " :  <no-decode>"))))))))) in state_monad$seqS
-            (handle_decode_exception ((EXTZ (( 64 : int):ii) h  :  64 words$word))) (state_monad$returnS F))
-         | SOME (ast) => state_monad$bindS
-            (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__6 : xlenbits) . 
+              (print_endline
+                ((STRCAT "["
+                    ((STRCAT ((stringFromInteger step_no))
+                        ((STRCAT "] ["
+                            ((STRCAT ((privLevel_to_str w__6))
+                                ((STRCAT "]: "
+                                    ((STRCAT ((string_of_bits w__7))
+                                        ((STRCAT " ("
+                                            ((STRCAT ((string_of_bits h)) ") <no-decode>"))))))))))))))))) in sail2_state_monad$seqS
+            (handle_decode_exception ((EXTZ (( 64 : int):ii) h  :  64 words$word))) (sail2_state_monad$returnS (F, T))))
+         | SOME (ast) => sail2_state_monad$bindS
+            (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__8 : Privilege) .  sail2_state_monad$bindS
+            (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__9 : xlenbits) . 
             let (_ : unit) =
-              (prerr_endline
-                ((STRCAT "PC: "
-                    ((STRCAT ((string_of_vec w__6))
-                        ((STRCAT " instr: "
-                            ((STRCAT ((string_of_vec h))
-                                ((STRCAT " :  " ((print_insn ast))))))))))))) in state_monad$bindS
-            (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__7 :  64 words$word) .  state_monad$seqS (state_monad$seqS
-            (state_monad$write_regS nextPC_ref ((add_vec_int w__7 (( 2 : int):ii)  :  64 words$word)))
-            (execute ast)) (state_monad$returnS T)))
+              (print_endline
+                ((STRCAT "["
+                    ((STRCAT ((stringFromInteger step_no))
+                        ((STRCAT "] ["
+                            ((STRCAT ((privLevel_to_str w__8))
+                                ((STRCAT "]: "
+                                    ((STRCAT ((string_of_bits w__9))
+                                        ((STRCAT " ("
+                                            ((STRCAT ((string_of_bits h))
+                                                ((STRCAT ") " ((print_insn ast))))))))))))))))))))) in sail2_state_monad$bindS
+            (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__10 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__10 (( 2 : int):ii)  :  64 words$word)))
+            (execute ast)) (\ (w__11 : bool) .  sail2_state_monad$returnS (w__11, T)))))
          )
       | F_Base (w) =>
          (case ((decode w)) of
-           NONE => state_monad$bindS
-            (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__9 : xlenbits) . 
+           NONE => sail2_state_monad$bindS
+            (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__13 : Privilege) .  sail2_state_monad$bindS
+            (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__14 : xlenbits) . 
             let (_ : unit) =
-              (prerr_endline
-                ((STRCAT "PC: "
-                    ((STRCAT ((string_of_vec w__9))
-                        ((STRCAT " instr: "
-                            ((STRCAT ((string_of_vec w)) " :  <no-decode>"))))))))) in state_monad$seqS
-            (handle_decode_exception ((EXTZ (( 64 : int):ii) w  :  64 words$word))) (state_monad$returnS F))
-         | SOME (ast) => state_monad$bindS
-            (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__10 : xlenbits) . 
+              (print_endline
+                ((STRCAT "["
+                    ((STRCAT ((stringFromInteger step_no))
+                        ((STRCAT "] ["
+                            ((STRCAT ((privLevel_to_str w__13))
+                                ((STRCAT "]: "
+                                    ((STRCAT ((string_of_bits w__14))
+                                        ((STRCAT " ("
+                                            ((STRCAT ((string_of_bits w)) ") <no-decode>"))))))))))))))))) in sail2_state_monad$seqS
+            (handle_decode_exception ((EXTZ (( 64 : int):ii) w  :  64 words$word))) (sail2_state_monad$returnS (F, T))))
+         | SOME (ast) => sail2_state_monad$bindS
+            (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__15 : Privilege) .  sail2_state_monad$bindS
+            (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__16 : xlenbits) . 
             let (_ : unit) =
-              (prerr_endline
-                ((STRCAT "PC: "
-                    ((STRCAT ((string_of_vec w__10))
-                        ((STRCAT " instr: "
-                            ((STRCAT ((string_of_vec w))
-                                ((STRCAT " :  " ((print_insn ast))))))))))))) in state_monad$bindS
-            (state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__11 :  64 words$word) .  state_monad$seqS (state_monad$seqS
-            (state_monad$write_regS nextPC_ref ((add_vec_int w__11 (( 4 : int):ii)  :  64 words$word)))
-            (execute ast)) (state_monad$returnS T)))
+              (print_endline
+                ((STRCAT "["
+                    ((STRCAT ((stringFromInteger step_no))
+                        ((STRCAT "] ["
+                            ((STRCAT ((privLevel_to_str w__15))
+                                ((STRCAT "]: "
+                                    ((STRCAT ((string_of_bits w__16))
+                                        ((STRCAT " ("
+                                            ((STRCAT ((string_of_bits w))
+                                                ((STRCAT ") " ((print_insn ast))))))))))))))))))))) in sail2_state_monad$bindS
+            (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__17 :  64 words$word) .  sail2_state_monad$bindS (sail2_state_monad$seqS
+            (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__17 (( 4 : int):ii)  :  64 words$word)))
+            (execute ast)) (\ (w__18 : bool) .  sail2_state_monad$returnS (w__18, T)))))
          )
       ))
-   )))))))`;
+   ))))))))`;
+
+
+(*val loop : unit -> M unit*)
+
+val _ = Define `
+ ((loop:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+    (let insns_per_tick = (plat_insns_per_tick () ) in
+   let (i : ii) = ((( 0 : int):ii)) in
+   let (step_no : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+   (sail2_state$whileS (i, step_no)
+     (\ varstup .  let (i, step_no) = varstup in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS htif_done_ref) (\ (w__0 : bool) .  sail2_state_monad$returnS ((~ w__0))))
+     (\ varstup .  let (i, step_no) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS
+       (sail2_state_monad$write_regS minstret_written_ref F)
+       (step step_no)) (\ varstup .  let (retired, stepped) = varstup in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS nextPC_ref  : ( 64 words$word) M) (\ (w__1 : xlenbits) .  sail2_state_monad$seqS (sail2_state_monad$seqS
+       (sail2_state_monad$write_regS PC_ref w__1)
+       (if retired then retire_instruction () 
+        else sail2_state_monad$returnS () ))
+       (let (step_no : ii) = (if stepped then ((ex_int step_no)) + (( 1 : int):ii) else step_no) in sail2_state_monad$bindS
+       (sail2_state_monad$read_regS htif_done_ref) (\ (w__2 : bool) .  sail2_state_monad$bindS
+       (if w__2 then sail2_state_monad$bindS
+          (sail2_state_monad$read_regS htif_exit_code_ref  : ( 64 words$word) M) (\ (w__3 : xlenbits) . 
+          let exit_val = (lem$w2ui w__3) in
+          sail2_state_monad$returnS (let _ =
+            (if (((exit_val = (( 0 : int):ii)))) then print_endline "SUCCESS"
+            else print_int "FAILURE: " exit_val) in
+          i))
+        else
+          let i = (((ex_int i)) + (( 1 : int):ii)) in
+          if (((((ex_int i)) = insns_per_tick))) then sail2_state_monad$seqS (sail2_state_monad$seqS
+            (tick_clock () ) (tick_platform () )) (sail2_state_monad$returnS (( 0 : int):ii))
+          else sail2_state_monad$returnS i) (\ (i : ii) . 
+       sail2_state_monad$returnS (i, step_no)))))))) (\ varstup .  let ((i : ii), (step_no : ii)) = varstup in
+   sail2_state_monad$returnS () )))`;
+
+
+(*val read_kind_of_num : integer -> read_kind*)
+
+val _ = Define `
+ ((read_kind_of_num:int -> read_kind) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Read_plain
+   else if (((p0_ = (( 1 : int):ii)))) then Read_reserve
+   else if (((p0_ = (( 2 : int):ii)))) then Read_acquire
+   else if (((p0_ = (( 3 : int):ii)))) then Read_exclusive
+   else if (((p0_ = (( 4 : int):ii)))) then Read_exclusive_acquire
+   else if (((p0_ = (( 5 : int):ii)))) then Read_stream
+   else if (((p0_ = (( 6 : int):ii)))) then Read_RISCV_acquire
+   else if (((p0_ = (( 7 : int):ii)))) then Read_RISCV_strong_acquire
+   else if (((p0_ = (( 8 : int):ii)))) then Read_RISCV_reserved
+   else if (((p0_ = (( 9 : int):ii)))) then Read_RISCV_reserved_acquire
+   else if (((p0_ = (( 10 : int):ii)))) then Read_RISCV_reserved_strong_acquire
+   else Read_X86_locked))`;
+
+
+(*val num_of_read_kind : read_kind -> integer*)
+
+val _ = Define `
+ ((num_of_read_kind:read_kind -> int) arg_=
+    ((case arg_ of
+     Read_plain => (( 0 : int):ii)
+   | Read_reserve => (( 1 : int):ii)
+   | Read_acquire => (( 2 : int):ii)
+   | Read_exclusive => (( 3 : int):ii)
+   | Read_exclusive_acquire => (( 4 : int):ii)
+   | Read_stream => (( 5 : int):ii)
+   | Read_RISCV_acquire => (( 6 : int):ii)
+   | Read_RISCV_strong_acquire => (( 7 : int):ii)
+   | Read_RISCV_reserved => (( 8 : int):ii)
+   | Read_RISCV_reserved_acquire => (( 9 : int):ii)
+   | Read_RISCV_reserved_strong_acquire => (( 10 : int):ii)
+   | Read_X86_locked => (( 11 : int):ii)
+   )))`;
+
+
+(*val write_kind_of_num : integer -> write_kind*)
+
+val _ = Define `
+ ((write_kind_of_num:int -> write_kind) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Write_plain
+   else if (((p0_ = (( 1 : int):ii)))) then Write_conditional
+   else if (((p0_ = (( 2 : int):ii)))) then Write_release
+   else if (((p0_ = (( 3 : int):ii)))) then Write_exclusive
+   else if (((p0_ = (( 4 : int):ii)))) then Write_exclusive_release
+   else if (((p0_ = (( 5 : int):ii)))) then Write_RISCV_release
+   else if (((p0_ = (( 6 : int):ii)))) then Write_RISCV_strong_release
+   else if (((p0_ = (( 7 : int):ii)))) then Write_RISCV_conditional
+   else if (((p0_ = (( 8 : int):ii)))) then Write_RISCV_conditional_release
+   else if (((p0_ = (( 9 : int):ii)))) then Write_RISCV_conditional_strong_release
+   else Write_X86_locked))`;
+
+
+(*val num_of_write_kind : write_kind -> integer*)
+
+val _ = Define `
+ ((num_of_write_kind:write_kind -> int) arg_=
+    ((case arg_ of
+     Write_plain => (( 0 : int):ii)
+   | Write_conditional => (( 1 : int):ii)
+   | Write_release => (( 2 : int):ii)
+   | Write_exclusive => (( 3 : int):ii)
+   | Write_exclusive_release => (( 4 : int):ii)
+   | Write_RISCV_release => (( 5 : int):ii)
+   | Write_RISCV_strong_release => (( 6 : int):ii)
+   | Write_RISCV_conditional => (( 7 : int):ii)
+   | Write_RISCV_conditional_release => (( 8 : int):ii)
+   | Write_RISCV_conditional_strong_release => (( 9 : int):ii)
+   | Write_X86_locked => (( 10 : int):ii)
+   )))`;
+
+
+(*val barrier_kind_of_num : integer -> barrier_kind*)
+
+val _ = Define `
+ ((barrier_kind_of_num:int -> barrier_kind) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Barrier_Sync
+   else if (((p0_ = (( 1 : int):ii)))) then Barrier_LwSync
+   else if (((p0_ = (( 2 : int):ii)))) then Barrier_Eieio
+   else if (((p0_ = (( 3 : int):ii)))) then Barrier_Isync
+   else if (((p0_ = (( 4 : int):ii)))) then Barrier_DMB
+   else if (((p0_ = (( 5 : int):ii)))) then Barrier_DMB_ST
+   else if (((p0_ = (( 6 : int):ii)))) then Barrier_DMB_LD
+   else if (((p0_ = (( 7 : int):ii)))) then Barrier_DSB
+   else if (((p0_ = (( 8 : int):ii)))) then Barrier_DSB_ST
+   else if (((p0_ = (( 9 : int):ii)))) then Barrier_DSB_LD
+   else if (((p0_ = (( 10 : int):ii)))) then Barrier_ISB
+   else if (((p0_ = (( 11 : int):ii)))) then Barrier_MIPS_SYNC
+   else if (((p0_ = (( 12 : int):ii)))) then Barrier_RISCV_rw_rw
+   else if (((p0_ = (( 13 : int):ii)))) then Barrier_RISCV_r_rw
+   else if (((p0_ = (( 14 : int):ii)))) then Barrier_RISCV_r_r
+   else if (((p0_ = (( 15 : int):ii)))) then Barrier_RISCV_rw_w
+   else if (((p0_ = (( 16 : int):ii)))) then Barrier_RISCV_w_w
+   else if (((p0_ = (( 17 : int):ii)))) then Barrier_RISCV_w_rw
+   else if (((p0_ = (( 18 : int):ii)))) then Barrier_RISCV_rw_r
+   else if (((p0_ = (( 19 : int):ii)))) then Barrier_RISCV_r_w
+   else if (((p0_ = (( 20 : int):ii)))) then Barrier_RISCV_w_r
+   else if (((p0_ = (( 21 : int):ii)))) then Barrier_RISCV_i
+   else Barrier_x86_MFENCE))`;
+
+
+(*val num_of_barrier_kind : barrier_kind -> integer*)
+
+val _ = Define `
+ ((num_of_barrier_kind:barrier_kind -> int) arg_=
+    ((case arg_ of
+     Barrier_Sync => (( 0 : int):ii)
+   | Barrier_LwSync => (( 1 : int):ii)
+   | Barrier_Eieio => (( 2 : int):ii)
+   | Barrier_Isync => (( 3 : int):ii)
+   | Barrier_DMB => (( 4 : int):ii)
+   | Barrier_DMB_ST => (( 5 : int):ii)
+   | Barrier_DMB_LD => (( 6 : int):ii)
+   | Barrier_DSB => (( 7 : int):ii)
+   | Barrier_DSB_ST => (( 8 : int):ii)
+   | Barrier_DSB_LD => (( 9 : int):ii)
+   | Barrier_ISB => (( 10 : int):ii)
+   | Barrier_MIPS_SYNC => (( 11 : int):ii)
+   | Barrier_RISCV_rw_rw => (( 12 : int):ii)
+   | Barrier_RISCV_r_rw => (( 13 : int):ii)
+   | Barrier_RISCV_r_r => (( 14 : int):ii)
+   | Barrier_RISCV_rw_w => (( 15 : int):ii)
+   | Barrier_RISCV_w_w => (( 16 : int):ii)
+   | Barrier_RISCV_w_rw => (( 17 : int):ii)
+   | Barrier_RISCV_rw_r => (( 18 : int):ii)
+   | Barrier_RISCV_r_w => (( 19 : int):ii)
+   | Barrier_RISCV_w_r => (( 20 : int):ii)
+   | Barrier_RISCV_i => (( 21 : int):ii)
+   | Barrier_x86_MFENCE => (( 22 : int):ii)
+   )))`;
+
+
+(*val trans_kind_of_num : integer -> trans_kind*)
+
+val _ = Define `
+ ((trans_kind_of_num:int -> trans_kind) arg_=
+    (let p0_ = arg_ in
+   if (((p0_ = (( 0 : int):ii)))) then Transaction_start
+   else if (((p0_ = (( 1 : int):ii)))) then Transaction_commit
+   else Transaction_abort))`;
+
+
+(*val num_of_trans_kind : trans_kind -> integer*)
+
+val _ = Define `
+ ((num_of_trans_kind:trans_kind -> int) arg_=
+    ((case arg_ of
+     Transaction_start => (( 0 : int):ii)
+   | Transaction_commit => (( 1 : int):ii)
+   | Transaction_abort => (( 2 : int):ii)
+   )))`;
+
+
+val _ = Define `
+((GPRstr:(string)list)=
+   (["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16";
+   "x15";"x14";"x13";"x12";"x21";"x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"]))`;
+
+
+val _ = Define `
+ ((CIA_fp:regfp)=  (RFull "CIA"))`;
+
+
+val _ = Define `
+ ((NIA_fp:regfp)=  (RFull "NIA"))`;
+
+
+(*val initial_analysis : ast -> M (list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)*)
+
+val _ = Define `
+ ((initial_analysis:ast ->(regstate)sail2_state_monad$sequential_state ->((((regfp)list#(regfp)list#(regfp)list#(niafp)list#diafp#instruction_kind),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) instr=
+    (let iR = ([]) in
+   let oR = ([]) in
+   let aR = ([]) in
+   let ik = (IK_simple () ) in
+   let Nias = ([NIAFP_successor () ]) in
+   let Dia = (DIAFP_none () ) in sail2_state_monad$bindS
+   (case instr of
+     EBREAK (_) => sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | UTYPE (imm,rd,op) =>
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | RISCV_JAL (imm,rd) =>
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm  :  64 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__0 :  64 words$word) . 
+      let (Nias : niafps) = ([NIAFP_concrete_address ((add_vec w__0 offset  :  64 words$word))]) in
+      let (ik : instruction_kind) = (IK_branch () ) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | RISCV_JALR (imm,rs,rd) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm  :  64 words$word)) in
+      let (Nias : niafps) = ([NIAFP_indirect_address () ]) in
+      let (ik : instruction_kind) = (IK_branch () ) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | BTYPE (imm,rs2,rs1,op) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let ik = (IK_branch () ) in
+      let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm  :  64 words$word)) in sail2_state_monad$bindS
+      (sail2_state_monad$read_regS PC_ref  : ( 64 words$word) M) (\ (w__1 :  64 words$word) . 
+      let (Nias : niafps) =
+        ([NIAFP_concrete_address ((add_vec w__1 offset  :  64 words$word));NIAFP_successor () ]) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | ITYPE (imm,rs,rd,op) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | SHIFTIOP (imm,rs,rd,op) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | RTYPE (rs2,rs1,rd,op) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | CSR (csr,rs1,rd,is_imm,op) =>
+      let (isWrite : bool) =
+        ((case op of
+          CSRRW => T
+        | _ => if is_imm then (((lem$w2ui rs1)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii))
+        )) in
+      let (iR : regfps) = ((RFull ((csr_name csr))) :: iR) in
+      let (iR : regfps) =
+        (if ((~ is_imm)) then (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR
+        else iR) in
+      let (oR : regfps) = (if isWrite then (RFull ((csr_name csr))) :: oR else oR) in
+      let (oR : regfps) = ((RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | LOAD (imm,rs,rd,unsign,width,aq,rl) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      let aR = iR in sail2_state_monad$bindS
+      (case (aq, rl) of
+        (F, F) => sail2_state_monad$returnS (IK_mem_read Read_plain)
+      | (T, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_acquire)
+      | (T, T) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_strong_acquire)
+      | _ => internal_error "LOAD type not implemented in initial_analysis"
+      ) (\ (w__3 : instruction_kind) . 
+      let (ik : instruction_kind) = w__3 in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | STORE (imm,rs2,rs1,width,aq,rl) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let (aR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then aR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: aR) in sail2_state_monad$bindS
+      (case (aq, rl) of
+        (F, F) => sail2_state_monad$returnS (IK_mem_write Write_plain)
+      | (F, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_release)
+      | (T, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_strong_release)
+      | _ => internal_error "STORE type not implemented in initial_analysis"
+      ) (\ (w__5 : instruction_kind) . 
+      let (ik : instruction_kind) = w__5 in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | ADDIW (imm,rs,rd) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | SHIFTW (imm,rs,rd,op) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | RTYPEW (rs2,rs1,rd,op) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | FENCE (pred,succ) => sail2_state_monad$bindS
+      (case (pred, succ) of
+        (v__276, v__277) =>
+         if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_rw)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_rw)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_r)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_w)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_w)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_rw)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_r)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_w)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_r)
+         else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+           sail2_state_monad$returnS (IK_simple () )
+         else internal_error "barrier type not implemented in initial_analysis"
+      ) (\ (w__17 : instruction_kind) . 
+      let (ik : instruction_kind) = w__17 in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | FENCEI (_) =>
+      let (ik : instruction_kind) = (IK_barrier Barrier_RISCV_i) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | LOADRES (aq,rl,rs1,width,rd) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      let aR = iR in sail2_state_monad$bindS
+      (case (aq, rl) of
+        (F, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved)
+      | (T, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved_acquire)
+      | (T, T) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved_strong_acquire)
+      | (F, T) => internal_error "LOADRES type not implemented in initial_analysis"
+      ) (\ (w__19 : instruction_kind) . 
+      let (ik : instruction_kind) = w__19 in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | STORECON (aq,rl,rs2,rs1,width,rd) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let (aR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then aR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: aR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in sail2_state_monad$bindS
+      (case (aq, rl) of
+        (F, F) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional)
+      | (F, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional_release)
+      | (T, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional_strong_release)
+      | (T, F) => internal_error "STORECON type not implemented in initial_analysis"
+      ) (\ (w__21 : instruction_kind) . 
+      let (ik : instruction_kind) = w__21 in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+   | AMO (op,aq,rl,rs2,rs1,width,rd) =>
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in
+      let (iR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in
+      let (aR : regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then aR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: aR) in
+      let (oR : regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in
+      let (ik : instruction_kind) =
+        ((case (aq, rl) of
+          (F, F) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional)
+        | (F, T) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional_release)
+        | (T, F) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional)
+        | (T, T) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional_release)
+        )) in
+      sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   | _ => sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+   ) (\ varstup .  let ((Nias : niafps), (aR : regfps), (iR : regfps), (ik : instruction_kind), (oR :
+     regfps)) = varstup in
+   sail2_state_monad$returnS (iR, oR, aR, Nias, Dia, ik))))`;
 
 
 val _ = Define `
 ((initial_regstate:regstate)=
    (<| tlb39 := NONE; 
+     htif_exit_code :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     htif_done := F; 
+     htif_tohost :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     mtimecmp :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
      tselect :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -7622,10 +23520,11 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
      scause :=
-       (Mk_Mcause (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                    :  64 words$word)); 
+       (<| Mcause_Mcause_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      sepc :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -7637,26 +23536,28 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
      stvec :=
-       (Mk_Mtvec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                   :  64 words$word)); 
+       (<| Mtvec_Mtvec_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      satp :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
      sideleg :=
-       (Mk_Sinterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0]
-                         :  64 words$word)); 
+       (<| Sinterrupts_Sinterrupts_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      sedeleg :=
-       (Mk_Sedeleg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                     :  64 words$word)); 
+       (<| Sedeleg_Sedeleg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      pmpcfg0 :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -7687,6 +23588,7 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
+     minstret_written := F; 
      minstret :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -7702,6 +23604,16 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
+     scounteren :=
+       (<| Counteren_Counteren_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0]
+               :  32 words$word)) |>); 
+     mcounteren :=
+       (<| Counteren_Counteren_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0]
+               :  32 words$word)) |>); 
      mscratch :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
@@ -7718,54 +23630,214 @@ val _ = Define `
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
      mcause :=
-       (Mk_Mcause (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                    :  64 words$word)); 
+       (<| Mcause_Mcause_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      mtvec :=
-       (Mk_Mtvec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                   :  64 words$word)); 
+       (<| Mtvec_Mtvec_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      medeleg :=
-       (Mk_Medeleg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                     :  64 words$word)); 
+       (<| Medeleg_Medeleg_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      mideleg :=
-       (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0]
-                         :  64 words$word)); 
+       (<| Minterrupts_Minterrupts_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      mie :=
-       (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0]
-                         :  64 words$word)); 
+       (<| Minterrupts_Minterrupts_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      mip :=
-       (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                     B0]
-                         :  64 words$word)); 
+       (<| Minterrupts_Minterrupts_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      mstatus :=
-       (Mk_Mstatus (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                     :  64 words$word)); 
+       (<| Mstatus_Mstatus_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      misa :=
-       (Mk_Misa (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
-                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
-                  :  64 words$word)); 
+       (<| Misa_Misa_chunk_0 :=
+             ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+               :  64 words$word)) |>); 
      cur_inst :=
        ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
          :  64 words$word)); 
      cur_privilege := User; 
+     x31 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x30 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x29 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x28 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x27 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x26 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x25 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x24 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x23 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x22 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x21 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x20 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x19 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x18 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x17 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x16 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x15 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x14 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x13 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x12 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x11 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x10 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x9 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x8 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x7 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x6 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x5 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x4 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x3 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x2 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
+     x1 :=
+       ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+         :  64 words$word)); 
      Xs :=
        ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
diff --git a/snapshots/hol4/sail/riscv/riscv_extrasScript.sml b/snapshots/hol4/sail/riscv/riscv_extrasScript.sml
index 41ae5deb..32ef1ebd 100644
--- a/snapshots/hol4/sail/riscv/riscv_extrasScript.sml
+++ b/snapshots/hol4/sail/riscv/riscv_extrasScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from riscv_extras.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory;
 
 val _ = numLib.prefer_num();
 
@@ -10,31 +10,43 @@ val _ = new_theory "riscv_extras"
 
 (*open import Pervasives*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 
 val _ = type_abbrev((*  'a *) "bitvector" , ``:  'a words$word``);
 
 val _ = Define `
- ((MEM_fence_rw_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (barrier Barrier_RISCV_rw_rw))`;
+ ((MEM_fence_rw_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () =  (barrier Barrier_RISCV_rw_rw))`;
 
 val _ = Define `
- ((MEM_fence_r_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)  () =  (barrier Barrier_RISCV_r_rw))`;
+ ((MEM_fence_r_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)  () =  (barrier Barrier_RISCV_r_rw))`;
 
 val _ = Define `
- ((MEM_fence_r_r:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)   () =  (barrier Barrier_RISCV_r_r))`;
+ ((MEM_fence_r_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   () =  (barrier Barrier_RISCV_r_r))`;
 
 val _ = Define `
- ((MEM_fence_rw_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)  () =  (barrier Barrier_RISCV_rw_w))`;
+ ((MEM_fence_rw_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)  () =  (barrier Barrier_RISCV_rw_w))`;
 
 val _ = Define `
- ((MEM_fence_w_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)   () =  (barrier Barrier_RISCV_w_w))`;
+ ((MEM_fence_w_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   () =  (barrier Barrier_RISCV_w_w))`;
 
 val _ = Define `
- ((MEM_fence_i:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)     () =  (barrier Barrier_RISCV_i))`;
+ ((MEM_fence_w_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)  () =  (barrier Barrier_RISCV_w_rw))`;
+
+val _ = Define `
+ ((MEM_fence_rw_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)  () =  (barrier Barrier_RISCV_rw_r))`;
+
+val _ = Define `
+ ((MEM_fence_r_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   () =  (barrier Barrier_RISCV_r_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)   () =  (barrier Barrier_RISCV_w_r))`;
+
+val _ = Define `
+ ((MEM_fence_i:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)     () =  (barrier Barrier_RISCV_i))`;
 
 
 (*val MEMea                            : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
@@ -45,60 +57,150 @@ val _ = Define `
 (*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
 
 val _ = Define `
- ((MEMea:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=                       (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`;
+ ((MEMea:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=                       (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=               (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=        (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=           (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=   (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= 
+                                          (sail2_state_monad$write_mem_eaS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`;
+
+
+(*val MEMr                         : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_acquire                 : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_strong_acquire          : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved                : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_acquire        : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+
+val _ = Define `
+ ((MEMr:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr=                          (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addr size1))`;
 
 val _ = Define `
- ((MEMea_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=               (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`;
+ ((MEMr_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr=                  (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addr size1))`;
 
 val _ = Define `
- ((MEMea_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=        (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`;
+ ((MEMr_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr=           (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addr size1))`;
 
 val _ = Define `
- ((MEMea_conditional:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=           (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`;
+ ((MEMr_reserved:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr=                 (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addr size1))`;
 
 val _ = Define `
- ((MEMea_conditional_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=   (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`;
+ ((MEMr_reserved_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr=         (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addr size1))`;
 
 val _ = Define `
- ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= 
-                                          (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`;
+ ((MEMr_reserved_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr=  (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addr size1))`;
 
 
 (*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*)
 val _ = Define `
- ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address value=  (state_monad$bindS (state_monad$seqS
-  (state_monad$write_mem_eaS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1))
-  (state_monad$write_mem_valS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict value)) (\b .  (case (b ) of ( _ ) => state_monad$returnS ()  ))))`;
+ ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address value=  (sail2_state_monad$bindS
+  (sail2_state_monad$write_mem_valS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict value) (\b .  (case (b ) of ( _ ) => sail2_state_monad$returnS ()  ))))`;
 
 
 (*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
 val _ = Define `
- ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address=
-   (state_monad$read_memS 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`;
+ ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address=
+   (sail2_state_monad$read_memS 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`;
+
+
+(*val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit*)
+val _ = Define `
+ ((load_reservation:'a words$word -> unit) addr=  () )`;
+
+
+val _ = Define `
+ ((speculate_conditional_success:'c -> 'a sail2_state_monad$sequential_state ->(((bool),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) _=  (sail2_state_monad$excl_resultS () ))`;
+
+
+val _ = Define `
+ ((cancel_reservation:unit -> unit) () =  () )`;
+
+
+(*val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_ram_base:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
 
 
+(*val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a*)
 val _ = Define `
- ((speculate_conditional_success:unit -> 'a state_monad$sequential_state ->(((bool),'b)state_monad$result#'a state_monad$sequential_state)set) () =  (state_monad$excl_resultS () ))`;
+ ((plat_ram_size:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
 
 
-(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*)
+(*val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a*)
 val _ = Define `
- ((get_slice_int0:int -> int -> int -> 'a words$word) len n lo=
-   (
-  (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in
-  let bits = (bits_of_int (hi +( 1 : int)) n) in
-  of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list F bits hi lo)))`;
+ ((plat_rom_base:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_rom_size:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_clint_base:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_clint_size:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_enable_dirty_update : unit -> bool*)
+val _ = Define `
+ ((plat_enable_dirty_update:unit -> bool) () =  F)`;
+
+
+(*val plat_enable_misaligned_access : unit -> bool*)
+val _ = Define `
+ ((plat_enable_misaligned_access:unit -> bool) () =  F)`;
+
+
+(*val plat_insns_per_tick : unit -> integer*)
+val _ = Define `
+ ((plat_insns_per_tick:unit -> int) () = (( 1 : int)))`;
+
+
+(*val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_htif_tohost:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit*)
+val _ = Define `
+ ((plat_term_write:'a words$word -> unit) _=  () )`;
+
+
+(*val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_term_read:unit -> 'a words$word) () =  (integer_word$i2w(( 0 : int))))`;
 
 
 (*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
@@ -112,12 +214,22 @@ val _ = Define `
 
 (*val print_string : string -> string -> unit*)
 val _ = Define `
- ((print_string:string -> string -> unit) msg s=  (prerr_endline ( STRCAT msg s)))`;
+ ((print_string:string -> string -> unit) msg s=  () )`;
+ (* print_endline (msg ^ s) *)
 
+(*val prerr_string : string -> string -> unit*)
+val _ = Define `
+ ((prerr_string:string -> string -> unit) msg s=  (prerr_endline ( STRCAT msg s)))`;
 
-(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+
+(*val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
 val _ = Define `
- ((print_bits:string -> 'a words$word -> unit) msg bs=  (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`;
+ ((prerr_bits:string -> 'a words$word -> unit) msg bs=  (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`;
+
 
+(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+val _ = Define `
+ ((print_bits:string -> 'a words$word -> unit) msg bs=  () )`;
+ (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
 val _ = export_theory()
 
diff --git a/snapshots/hol4/sail/riscv/riscv_typesScript.sml b/snapshots/hol4/sail/riscv/riscv_typesScript.sml
index 4637d1df..d478b614 100644
--- a/snapshots/hol4/sail/riscv/riscv_typesScript.sml
+++ b/snapshots/hol4/sail/riscv/riscv_typesScript.sml
@@ -1,6 +1,6 @@
 (*Generated by Lem from riscv_types.lem.*)
 open HolKernel Parse boolLib bossLib;
-open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory;
 
 val _ = numLib.prefer_num();
 
@@ -10,11 +10,12 @@ val _ = new_theory "riscv_types"
 
 (*Generated by Sail from riscv.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 val _ = type_abbrev((*  'n *) "bits" , ``:  'n words$word``);
 
 
@@ -205,80 +206,67 @@ val _ = Hol_datatype `
 
 
 val _ = Hol_datatype `
- MemoryOpResult =   MemValue of ('a) | MemException of (ExceptionType)`;
-
+ Misa  = <| Misa_Misa_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Misa  =   Mk_Misa of ( 64 words$word)`;
-
+ SV39_PTE  = <| SV39_PTE_SV39_PTE_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- SV39_PTE  =   Mk_SV39_PTE of ( 64 words$word)`;
-
+ PTE_Bits  = <| PTE_Bits_PTE_Bits_chunk_0 :  8 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- PTE_Bits  =   Mk_PTE_Bits of ( 8 words$word)`;
-
+ Mstatus  = <| Mstatus_Mstatus_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Mstatus  =   Mk_Mstatus of ( 64 words$word)`;
-
+ Sstatus  = <| Sstatus_Sstatus_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Sstatus  =   Mk_Sstatus of ( 64 words$word)`;
-
+ Minterrupts  = <| Minterrupts_Minterrupts_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Minterrupts  =   Mk_Minterrupts of ( 64 words$word)`;
-
+ Sinterrupts  = <| Sinterrupts_Sinterrupts_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Sinterrupts  =   Mk_Sinterrupts of ( 64 words$word)`;
-
+ Medeleg  = <| Medeleg_Medeleg_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Medeleg  =   Mk_Medeleg of ( 64 words$word)`;
-
+ Sedeleg  = <| Sedeleg_Sedeleg_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Sedeleg  =   Mk_Sedeleg of ( 64 words$word)`;
-
+ Mtvec  = <| Mtvec_Mtvec_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Mtvec  =   Mk_Mtvec of ( 64 words$word)`;
-
+ Satp64  = <| Satp64_Satp64_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Satp64  =   Mk_Satp64 of ( 64 words$word)`;
-
+ Mcause  = <| Mcause_Mcause_chunk_0 :  64 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- Mcause  =   Mk_Mcause of ( 64 words$word)`;
-
+ Counteren  = <| Counteren_Counteren_chunk_0 :  32 words$word  |>`;
 
 
 
@@ -294,6 +282,17 @@ val _ = Hol_datatype `
 
 
 
+val _ = Hol_datatype `
+ MemoryOpResult =   MemValue of ('a) | MemException of (ExceptionType)`;
+
+
+
+
+val _ = Hol_datatype `
+ htif_cmd  = <| htif_cmd_htif_cmd_chunk_0 :  64 words$word  |>`;
+
+
+
 val _ = type_abbrev( "pteAttribs"  , ``: 8 bits``);
 
 val _ = Hol_datatype `
@@ -309,14 +308,12 @@ val _ = type_abbrev( "paddr39"  , ``: 56 bits``);
 val _ = type_abbrev( "pte39"  , ``: xlenbits``);
 
 val _ = Hol_datatype `
- SV39_Vaddr  =   Mk_SV39_Vaddr of ( 39 words$word)`;
-
+ SV39_Vaddr  = <| SV39_Vaddr_SV39_Vaddr_chunk_0 :  39 words$word  |>`;
 
 
 
 val _ = Hol_datatype `
- SV39_Paddr  =   Mk_SV39_Paddr of ( 56 words$word)`;
-
+ SV39_Paddr  = <| SV39_Paddr_SV39_Paddr_chunk_0 :  56 words$word  |>`;
 
 
 
@@ -388,7 +385,6 @@ val _ = Hol_datatype `
   | AMO of ((amoop # bool # bool # regbits # regbits # word_width # regbits))
   | CSR of (( 12 bits # regbits # regbits # bool # csrop))
   | NOP of (unit)
-  | ILLEGAL of (unit)
   | C_ADDI4SPN of ((cregbits # 8 bits))
   | C_LW of (( 5 bits # cregbits # cregbits))
   | C_LD of (( 5 bits # cregbits # cregbits))
@@ -420,7 +416,11 @@ val _ = Hol_datatype `
   | C_JR of (regbits)
   | C_JALR of (regbits)
   | C_MV of ((regbits # regbits))
-  | C_ADD of ((regbits # regbits))`;
+  | C_ADD of ((regbits # regbits))
+  | STOP_FETCHING of (unit)
+  | THREAD_START of (unit)
+  | ILLEGAL of (word)
+  | C_ILLEGAL of (unit)`;
 
 
 
@@ -431,11 +431,51 @@ val _ = Hol_datatype `
 
 
 
+val _ = Hol_datatype `
+ regfp  =
+    RFull of (string)
+  | RSlice of ((string # ii # ii))
+  | RSliceBit of ((string # ii))
+  | RField of ((string # string))`;
+
+
+
+
+val _ = type_abbrev( "regfps"  , ``: regfp list``);
+
+val _ = Hol_datatype `
+ niafp  =
+    NIAFP_successor of (unit)
+  | NIAFP_concrete_address of ( 64 bits)
+  | NIAFP_indirect_address of (unit)`;
+
+
+
+
+val _ = type_abbrev( "niafps"  , ``: niafp list``);
+
+val _ = Hol_datatype `
+ diafp  =   DIAFP_none of (unit) | DIAFP_concrete of ( 64 bits) | DIAFP_reg of (regfp)`;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 val _ = Hol_datatype `
  register_value  =
     Regval_vector of ((ii # bool # register_value list))
   | Regval_list of ( register_value list)
   | Regval_option of ( register_value option)
+  | Regval_Counteren of (Counteren)
   | Regval_Mcause of (Mcause)
   | Regval_Medeleg of (Medeleg)
   | Regval_Minterrupts of (Minterrupts)
@@ -446,6 +486,7 @@ val _ = Hol_datatype `
   | Regval_Sedeleg of (Sedeleg)
   | Regval_Sinterrupts of (Sinterrupts)
   | Regval_TLB39_Entry of (TLB39_Entry)
+  | Regval_bool of (bool)
   | Regval_vector_64_dec_bit of ( 64 words$word)`;
 
 
@@ -454,6 +495,10 @@ val _ = Hol_datatype `
 val _ = Hol_datatype `
  regstate  =
   <| tlb39 :  TLB39_Entry option;
+     htif_exit_code :  64 words$word;
+     htif_done : bool;
+     htif_tohost :  64 words$word;
+     mtimecmp :  64 words$word;
      tselect :  64 words$word;
      stval :  64 words$word;
      scause : Mcause;
@@ -469,9 +514,12 @@ val _ = Hol_datatype `
      marchid :  64 words$word;
      mimpid :  64 words$word;
      mvendorid :  64 words$word;
+     minstret_written : bool;
      minstret :  64 words$word;
      mtime :  64 words$word;
      mcycle :  64 words$word;
+     scounteren : Counteren;
+     mcounteren : Counteren;
      mscratch :  64 words$word;
      mtval :  64 words$word;
      mepc :  64 words$word;
@@ -485,6 +533,37 @@ val _ = Hol_datatype `
      misa : Misa;
      cur_inst :  64 words$word;
      cur_privilege : Privilege;
+     x31 :  64 words$word;
+     x30 :  64 words$word;
+     x29 :  64 words$word;
+     x28 :  64 words$word;
+     x27 :  64 words$word;
+     x26 :  64 words$word;
+     x25 :  64 words$word;
+     x24 :  64 words$word;
+     x23 :  64 words$word;
+     x22 :  64 words$word;
+     x21 :  64 words$word;
+     x20 :  64 words$word;
+     x19 :  64 words$word;
+     x18 :  64 words$word;
+     x17 :  64 words$word;
+     x16 :  64 words$word;
+     x15 :  64 words$word;
+     x14 :  64 words$word;
+     x13 :  64 words$word;
+     x12 :  64 words$word;
+     x11 :  64 words$word;
+     x10 :  64 words$word;
+     x9 :  64 words$word;
+     x8 :  64 words$word;
+     x7 :  64 words$word;
+     x6 :  64 words$word;
+     x5 :  64 words$word;
+     x4 :  64 words$word;
+     x3 :  64 words$word;
+     x2 :  64 words$word;
+     x1 :  64 words$word;
      Xs : ( 64 words$word) list;
      nextPC :  64 words$word;
      PC :  64 words$word  |>`;
@@ -493,11 +572,24 @@ val _ = Hol_datatype `
 
 
 
+(*val Counteren_of_regval : register_value -> maybe Counteren*)
+
+val _ = Define `
+ ((Counteren_of_regval:register_value ->(Counteren)option) merge_var=
+    ((case merge_var of   Regval_Counteren (v) => SOME v | g__12 => NONE )))`;
+
+
+(*val regval_of_Counteren : Counteren -> register_value*)
+
+val _ = Define `
+ ((regval_of_Counteren:Counteren -> register_value) v=  (Regval_Counteren v))`;
+
+
 (*val Mcause_of_regval : register_value -> maybe Mcause*)
 
 val _ = Define `
  ((Mcause_of_regval:register_value ->(Mcause)option) merge_var=
-    ((case merge_var of   Regval_Mcause (v) => SOME v | g__92 => NONE )))`;
+    ((case merge_var of   Regval_Mcause (v) => SOME v | g__11 => NONE )))`;
 
 
 (*val regval_of_Mcause : Mcause -> register_value*)
@@ -510,7 +602,7 @@ val _ = Define `
 
 val _ = Define `
  ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var=
-    ((case merge_var of   Regval_Medeleg (v) => SOME v | g__91 => NONE )))`;
+    ((case merge_var of   Regval_Medeleg (v) => SOME v | g__10 => NONE )))`;
 
 
 (*val regval_of_Medeleg : Medeleg -> register_value*)
@@ -523,7 +615,7 @@ val _ = Define `
 
 val _ = Define `
  ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var=
-    ((case merge_var of   Regval_Minterrupts (v) => SOME v | g__90 => NONE )))`;
+    ((case merge_var of   Regval_Minterrupts (v) => SOME v | g__9 => NONE )))`;
 
 
 (*val regval_of_Minterrupts : Minterrupts -> register_value*)
@@ -536,7 +628,7 @@ val _ = Define `
 
 val _ = Define `
  ((Misa_of_regval:register_value ->(Misa)option) merge_var=
-    ((case merge_var of   Regval_Misa (v) => SOME v | g__89 => NONE )))`;
+    ((case merge_var of   Regval_Misa (v) => SOME v | g__8 => NONE )))`;
 
 
 (*val regval_of_Misa : Misa -> register_value*)
@@ -549,7 +641,7 @@ val _ = Define `
 
 val _ = Define `
  ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var=
-    ((case merge_var of   Regval_Mstatus (v) => SOME v | g__88 => NONE )))`;
+    ((case merge_var of   Regval_Mstatus (v) => SOME v | g__7 => NONE )))`;
 
 
 (*val regval_of_Mstatus : Mstatus -> register_value*)
@@ -562,7 +654,7 @@ val _ = Define `
 
 val _ = Define `
  ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var=
-    ((case merge_var of   Regval_Mtvec (v) => SOME v | g__87 => NONE )))`;
+    ((case merge_var of   Regval_Mtvec (v) => SOME v | g__6 => NONE )))`;
 
 
 (*val regval_of_Mtvec : Mtvec -> register_value*)
@@ -575,7 +667,7 @@ val _ = Define `
 
 val _ = Define `
  ((Privilege_of_regval:register_value ->(Privilege)option) merge_var=
-    ((case merge_var of   Regval_Privilege (v) => SOME v | g__86 => NONE )))`;
+    ((case merge_var of   Regval_Privilege (v) => SOME v | g__5 => NONE )))`;
 
 
 (*val regval_of_Privilege : Privilege -> register_value*)
@@ -588,7 +680,7 @@ val _ = Define `
 
 val _ = Define `
  ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var=
-    ((case merge_var of   Regval_Sedeleg (v) => SOME v | g__85 => NONE )))`;
+    ((case merge_var of   Regval_Sedeleg (v) => SOME v | g__4 => NONE )))`;
 
 
 (*val regval_of_Sedeleg : Sedeleg -> register_value*)
@@ -601,7 +693,7 @@ val _ = Define `
 
 val _ = Define `
  ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var=
-    ((case merge_var of   Regval_Sinterrupts (v) => SOME v | g__84 => NONE )))`;
+    ((case merge_var of   Regval_Sinterrupts (v) => SOME v | g__3 => NONE )))`;
 
 
 (*val regval_of_Sinterrupts : Sinterrupts -> register_value*)
@@ -614,7 +706,7 @@ val _ = Define `
 
 val _ = Define `
  ((TLB39_Entry_of_regval:register_value ->(TLB39_Entry)option) merge_var=
-    ((case merge_var of   Regval_TLB39_Entry (v) => SOME v | g__83 => NONE )))`;
+    ((case merge_var of   Regval_TLB39_Entry (v) => SOME v | g__2 => NONE )))`;
 
 
 (*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*)
@@ -623,11 +715,24 @@ val _ = Define `
  ((regval_of_TLB39_Entry:TLB39_Entry -> register_value) v=  (Regval_TLB39_Entry v))`;
 
 
+(*val bool_of_regval : register_value -> maybe bool*)
+
+val _ = Define `
+ ((bool_of_regval:register_value ->(bool)option) merge_var=
+    ((case merge_var of   Regval_bool (v) => SOME v | g__1 => NONE )))`;
+
+
+(*val regval_of_bool : bool -> register_value*)
+
+val _ = Define `
+ ((regval_of_bool:bool -> register_value) v=  (Regval_bool v))`;
+
+
 (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
 
 val _ = Define `
  ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=
-    ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__82 => NONE )))`;
+    ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__0 => NONE )))`;
 
 
 (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
@@ -640,44 +745,44 @@ val _ = Define `
 
 (*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
 val _ = Define `
- ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
   (\x .  (case x of
-               Regval_vector (_, _, v) => just_list (MAP of_regval v)
+               Regval_vector (_, _, v) => just_list (MAP of_regval1 v)
            | _ => NONE
          )))`;
 
 
 (*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
 val _ = Define `
- ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of xs)))`;
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`;
 
 
 (*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
 val _ = Define `
- ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= 
   (\x .  (case x of
-               Regval_list v => just_list (MAP of_regval v)
+               Regval_list v => just_list (MAP of_regval1 v)
            | _ => NONE
          )))`;
 
 
 (*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
 val _ = Define `
- ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs=  (Regval_list (MAP regval_of xs)))`;
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs=  (Regval_list (MAP regval_of1 xs)))`;
 
 
 (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
 val _ = Define `
- ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= 
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= 
   (\x .  (case x of
-               Regval_option v => SOME (OPTION_BIND v of_regval)
+               Regval_option v => SOME (OPTION_BIND v of_regval1)
            | _ => NONE
          )))`;
 
 
 (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
 val _ = Define `
- ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v=  (Regval_option (OPTION_MAP regval_of v)))`;
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v=  (Regval_option (OPTION_MAP regval_of1 v)))`;
 
 
 
@@ -690,6 +795,42 @@ val _ = Define `
   regval_of := (\ v .  regval_of_option (\ v .  regval_of_TLB39_Entry v) v) |>))`;
 
 
+val _ = Define `
+ ((htif_exit_code_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "htif_exit_code";
+  read_from := (\ s .  s.htif_exit_code);
+  write_to := (\ v s .  (( s with<| htif_exit_code := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((htif_done_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "htif_done";
+  read_from := (\ s .  s.htif_done);
+  write_to := (\ v s .  (( s with<| htif_done := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((htif_tohost_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "htif_tohost";
+  read_from := (\ s .  s.htif_tohost);
+  write_to := (\ v s .  (( s with<| htif_tohost := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtimecmp_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "mtimecmp";
+  read_from := (\ s .  s.mtimecmp);
+  write_to := (\ v s .  (( s with<| mtimecmp := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
 val _ = Define `
  ((tselect_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
   name := "tselect";
@@ -825,6 +966,15 @@ val _ = Define `
   regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
 
 
+val _ = Define `
+ ((minstret_written_ref:((regstate),(register_value),(bool))register_ref)=  (<|
+  name := "minstret_written";
+  read_from := (\ s .  s.minstret_written);
+  write_to := (\ v s .  (( s with<| minstret_written := v |>)));
+  of_regval := (\ v .  bool_of_regval v);
+  regval_of := (\ v .  regval_of_bool v) |>))`;
+
+
 val _ = Define `
  ((minstret_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
   name := "minstret";
@@ -852,6 +1002,24 @@ val _ = Define `
   regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
 
 
+val _ = Define `
+ ((scounteren_ref:((regstate),(register_value),(Counteren))register_ref)=  (<|
+  name := "scounteren";
+  read_from := (\ s .  s.scounteren);
+  write_to := (\ v s .  (( s with<| scounteren := v |>)));
+  of_regval := (\ v .  Counteren_of_regval v);
+  regval_of := (\ v .  regval_of_Counteren v) |>))`;
+
+
+val _ = Define `
+ ((mcounteren_ref:((regstate),(register_value),(Counteren))register_ref)=  (<|
+  name := "mcounteren";
+  read_from := (\ s .  s.mcounteren);
+  write_to := (\ v s .  (( s with<| mcounteren := v |>)));
+  of_regval := (\ v .  Counteren_of_regval v);
+  regval_of := (\ v .  regval_of_Counteren v) |>))`;
+
+
 val _ = Define `
  ((mscratch_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
   name := "mscratch";
@@ -969,6 +1137,285 @@ val _ = Define `
   regval_of := (\ v .  regval_of_Privilege v) |>))`;
 
 
+val _ = Define `
+ ((x31_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x31";
+  read_from := (\ s .  s.x31);
+  write_to := (\ v s .  (( s with<| x31 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x30_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x30";
+  read_from := (\ s .  s.x30);
+  write_to := (\ v s .  (( s with<| x30 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x29_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x29";
+  read_from := (\ s .  s.x29);
+  write_to := (\ v s .  (( s with<| x29 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x28_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x28";
+  read_from := (\ s .  s.x28);
+  write_to := (\ v s .  (( s with<| x28 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x27_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x27";
+  read_from := (\ s .  s.x27);
+  write_to := (\ v s .  (( s with<| x27 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x26_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x26";
+  read_from := (\ s .  s.x26);
+  write_to := (\ v s .  (( s with<| x26 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x25_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x25";
+  read_from := (\ s .  s.x25);
+  write_to := (\ v s .  (( s with<| x25 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x24_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x24";
+  read_from := (\ s .  s.x24);
+  write_to := (\ v s .  (( s with<| x24 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x23_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x23";
+  read_from := (\ s .  s.x23);
+  write_to := (\ v s .  (( s with<| x23 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x22_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x22";
+  read_from := (\ s .  s.x22);
+  write_to := (\ v s .  (( s with<| x22 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x21_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x21";
+  read_from := (\ s .  s.x21);
+  write_to := (\ v s .  (( s with<| x21 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x20_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x20";
+  read_from := (\ s .  s.x20);
+  write_to := (\ v s .  (( s with<| x20 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x19_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x19";
+  read_from := (\ s .  s.x19);
+  write_to := (\ v s .  (( s with<| x19 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x18_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x18";
+  read_from := (\ s .  s.x18);
+  write_to := (\ v s .  (( s with<| x18 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x17_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x17";
+  read_from := (\ s .  s.x17);
+  write_to := (\ v s .  (( s with<| x17 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x16_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x16";
+  read_from := (\ s .  s.x16);
+  write_to := (\ v s .  (( s with<| x16 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x15_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x15";
+  read_from := (\ s .  s.x15);
+  write_to := (\ v s .  (( s with<| x15 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x14_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x14";
+  read_from := (\ s .  s.x14);
+  write_to := (\ v s .  (( s with<| x14 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x13_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x13";
+  read_from := (\ s .  s.x13);
+  write_to := (\ v s .  (( s with<| x13 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x12_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x12";
+  read_from := (\ s .  s.x12);
+  write_to := (\ v s .  (( s with<| x12 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x11_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x11";
+  read_from := (\ s .  s.x11);
+  write_to := (\ v s .  (( s with<| x11 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x10_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x10";
+  read_from := (\ s .  s.x10);
+  write_to := (\ v s .  (( s with<| x10 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x9_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x9";
+  read_from := (\ s .  s.x9);
+  write_to := (\ v s .  (( s with<| x9 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x8_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x8";
+  read_from := (\ s .  s.x8);
+  write_to := (\ v s .  (( s with<| x8 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x7_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x7";
+  read_from := (\ s .  s.x7);
+  write_to := (\ v s .  (( s with<| x7 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x6_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x6";
+  read_from := (\ s .  s.x6);
+  write_to := (\ v s .  (( s with<| x6 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x5_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x5";
+  read_from := (\ s .  s.x5);
+  write_to := (\ v s .  (( s with<| x5 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x4_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x4";
+  read_from := (\ s .  s.x4);
+  write_to := (\ v s .  (( s with<| x4 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x3_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x3";
+  read_from := (\ s .  s.x3);
+  write_to := (\ v s .  (( s with<| x3 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x2_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x2";
+  read_from := (\ s .  s.x2);
+  write_to := (\ v s .  (( s with<| x2 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x1_ref:((regstate),(register_value),((64)words$word))register_ref)=  (<|
+  name := "x1";
+  read_from := (\ s .  s.x1);
+  write_to := (\ v s .  (( s with<| x1 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
 val _ = Define `
  ((Xs_ref:((regstate),(register_value),(((64)words$word)list))register_ref)=  (<|
   name := "Xs";
@@ -1000,6 +1447,10 @@ val _ = Define `
 val _ = Define `
  ((get_regval:string -> regstate ->(register_value)option) reg_name s=
    (if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else
+  if reg_name = "htif_exit_code" then SOME (htif_exit_code_ref.regval_of (htif_exit_code_ref.read_from s)) else
+  if reg_name = "htif_done" then SOME (htif_done_ref.regval_of (htif_done_ref.read_from s)) else
+  if reg_name = "htif_tohost" then SOME (htif_tohost_ref.regval_of (htif_tohost_ref.read_from s)) else
+  if reg_name = "mtimecmp" then SOME (mtimecmp_ref.regval_of (mtimecmp_ref.read_from s)) else
   if reg_name = "tselect" then SOME (tselect_ref.regval_of (tselect_ref.read_from s)) else
   if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else
   if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else
@@ -1015,9 +1466,12 @@ val _ = Define `
   if reg_name = "marchid" then SOME (marchid_ref.regval_of (marchid_ref.read_from s)) else
   if reg_name = "mimpid" then SOME (mimpid_ref.regval_of (mimpid_ref.read_from s)) else
   if reg_name = "mvendorid" then SOME (mvendorid_ref.regval_of (mvendorid_ref.read_from s)) else
+  if reg_name = "minstret_written" then SOME (minstret_written_ref.regval_of (minstret_written_ref.read_from s)) else
   if reg_name = "minstret" then SOME (minstret_ref.regval_of (minstret_ref.read_from s)) else
   if reg_name = "mtime" then SOME (mtime_ref.regval_of (mtime_ref.read_from s)) else
   if reg_name = "mcycle" then SOME (mcycle_ref.regval_of (mcycle_ref.read_from s)) else
+  if reg_name = "scounteren" then SOME (scounteren_ref.regval_of (scounteren_ref.read_from s)) else
+  if reg_name = "mcounteren" then SOME (mcounteren_ref.regval_of (mcounteren_ref.read_from s)) else
   if reg_name = "mscratch" then SOME (mscratch_ref.regval_of (mscratch_ref.read_from s)) else
   if reg_name = "mtval" then SOME (mtval_ref.regval_of (mtval_ref.read_from s)) else
   if reg_name = "mepc" then SOME (mepc_ref.regval_of (mepc_ref.read_from s)) else
@@ -1031,6 +1485,37 @@ val _ = Define `
   if reg_name = "misa" then SOME (misa_ref.regval_of (misa_ref.read_from s)) else
   if reg_name = "cur_inst" then SOME (cur_inst_ref.regval_of (cur_inst_ref.read_from s)) else
   if reg_name = "cur_privilege" then SOME (cur_privilege_ref.regval_of (cur_privilege_ref.read_from s)) else
+  if reg_name = "x31" then SOME (x31_ref.regval_of (x31_ref.read_from s)) else
+  if reg_name = "x30" then SOME (x30_ref.regval_of (x30_ref.read_from s)) else
+  if reg_name = "x29" then SOME (x29_ref.regval_of (x29_ref.read_from s)) else
+  if reg_name = "x28" then SOME (x28_ref.regval_of (x28_ref.read_from s)) else
+  if reg_name = "x27" then SOME (x27_ref.regval_of (x27_ref.read_from s)) else
+  if reg_name = "x26" then SOME (x26_ref.regval_of (x26_ref.read_from s)) else
+  if reg_name = "x25" then SOME (x25_ref.regval_of (x25_ref.read_from s)) else
+  if reg_name = "x24" then SOME (x24_ref.regval_of (x24_ref.read_from s)) else
+  if reg_name = "x23" then SOME (x23_ref.regval_of (x23_ref.read_from s)) else
+  if reg_name = "x22" then SOME (x22_ref.regval_of (x22_ref.read_from s)) else
+  if reg_name = "x21" then SOME (x21_ref.regval_of (x21_ref.read_from s)) else
+  if reg_name = "x20" then SOME (x20_ref.regval_of (x20_ref.read_from s)) else
+  if reg_name = "x19" then SOME (x19_ref.regval_of (x19_ref.read_from s)) else
+  if reg_name = "x18" then SOME (x18_ref.regval_of (x18_ref.read_from s)) else
+  if reg_name = "x17" then SOME (x17_ref.regval_of (x17_ref.read_from s)) else
+  if reg_name = "x16" then SOME (x16_ref.regval_of (x16_ref.read_from s)) else
+  if reg_name = "x15" then SOME (x15_ref.regval_of (x15_ref.read_from s)) else
+  if reg_name = "x14" then SOME (x14_ref.regval_of (x14_ref.read_from s)) else
+  if reg_name = "x13" then SOME (x13_ref.regval_of (x13_ref.read_from s)) else
+  if reg_name = "x12" then SOME (x12_ref.regval_of (x12_ref.read_from s)) else
+  if reg_name = "x11" then SOME (x11_ref.regval_of (x11_ref.read_from s)) else
+  if reg_name = "x10" then SOME (x10_ref.regval_of (x10_ref.read_from s)) else
+  if reg_name = "x9" then SOME (x9_ref.regval_of (x9_ref.read_from s)) else
+  if reg_name = "x8" then SOME (x8_ref.regval_of (x8_ref.read_from s)) else
+  if reg_name = "x7" then SOME (x7_ref.regval_of (x7_ref.read_from s)) else
+  if reg_name = "x6" then SOME (x6_ref.regval_of (x6_ref.read_from s)) else
+  if reg_name = "x5" then SOME (x5_ref.regval_of (x5_ref.read_from s)) else
+  if reg_name = "x4" then SOME (x4_ref.regval_of (x4_ref.read_from s)) else
+  if reg_name = "x3" then SOME (x3_ref.regval_of (x3_ref.read_from s)) else
+  if reg_name = "x2" then SOME (x2_ref.regval_of (x2_ref.read_from s)) else
+  if reg_name = "x1" then SOME (x1_ref.regval_of (x1_ref.read_from s)) else
   if reg_name = "Xs" then SOME (Xs_ref.regval_of (Xs_ref.read_from s)) else
   if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else
   if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
@@ -1041,6 +1526,10 @@ val _ = Define `
 val _ = Define `
  ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=
    (if reg_name = "tlb39" then OPTION_MAP (\ v .  tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else
+  if reg_name = "htif_exit_code" then OPTION_MAP (\ v .  htif_exit_code_ref.write_to v s) (htif_exit_code_ref.of_regval v) else
+  if reg_name = "htif_done" then OPTION_MAP (\ v .  htif_done_ref.write_to v s) (htif_done_ref.of_regval v) else
+  if reg_name = "htif_tohost" then OPTION_MAP (\ v .  htif_tohost_ref.write_to v s) (htif_tohost_ref.of_regval v) else
+  if reg_name = "mtimecmp" then OPTION_MAP (\ v .  mtimecmp_ref.write_to v s) (mtimecmp_ref.of_regval v) else
   if reg_name = "tselect" then OPTION_MAP (\ v .  tselect_ref.write_to v s) (tselect_ref.of_regval v) else
   if reg_name = "stval" then OPTION_MAP (\ v .  stval_ref.write_to v s) (stval_ref.of_regval v) else
   if reg_name = "scause" then OPTION_MAP (\ v .  scause_ref.write_to v s) (scause_ref.of_regval v) else
@@ -1056,9 +1545,12 @@ val _ = Define `
   if reg_name = "marchid" then OPTION_MAP (\ v .  marchid_ref.write_to v s) (marchid_ref.of_regval v) else
   if reg_name = "mimpid" then OPTION_MAP (\ v .  mimpid_ref.write_to v s) (mimpid_ref.of_regval v) else
   if reg_name = "mvendorid" then OPTION_MAP (\ v .  mvendorid_ref.write_to v s) (mvendorid_ref.of_regval v) else
+  if reg_name = "minstret_written" then OPTION_MAP (\ v .  minstret_written_ref.write_to v s) (minstret_written_ref.of_regval v) else
   if reg_name = "minstret" then OPTION_MAP (\ v .  minstret_ref.write_to v s) (minstret_ref.of_regval v) else
   if reg_name = "mtime" then OPTION_MAP (\ v .  mtime_ref.write_to v s) (mtime_ref.of_regval v) else
   if reg_name = "mcycle" then OPTION_MAP (\ v .  mcycle_ref.write_to v s) (mcycle_ref.of_regval v) else
+  if reg_name = "scounteren" then OPTION_MAP (\ v .  scounteren_ref.write_to v s) (scounteren_ref.of_regval v) else
+  if reg_name = "mcounteren" then OPTION_MAP (\ v .  mcounteren_ref.write_to v s) (mcounteren_ref.of_regval v) else
   if reg_name = "mscratch" then OPTION_MAP (\ v .  mscratch_ref.write_to v s) (mscratch_ref.of_regval v) else
   if reg_name = "mtval" then OPTION_MAP (\ v .  mtval_ref.write_to v s) (mtval_ref.of_regval v) else
   if reg_name = "mepc" then OPTION_MAP (\ v .  mepc_ref.write_to v s) (mepc_ref.of_regval v) else
@@ -1072,6 +1564,37 @@ val _ = Define `
   if reg_name = "misa" then OPTION_MAP (\ v .  misa_ref.write_to v s) (misa_ref.of_regval v) else
   if reg_name = "cur_inst" then OPTION_MAP (\ v .  cur_inst_ref.write_to v s) (cur_inst_ref.of_regval v) else
   if reg_name = "cur_privilege" then OPTION_MAP (\ v .  cur_privilege_ref.write_to v s) (cur_privilege_ref.of_regval v) else
+  if reg_name = "x31" then OPTION_MAP (\ v .  x31_ref.write_to v s) (x31_ref.of_regval v) else
+  if reg_name = "x30" then OPTION_MAP (\ v .  x30_ref.write_to v s) (x30_ref.of_regval v) else
+  if reg_name = "x29" then OPTION_MAP (\ v .  x29_ref.write_to v s) (x29_ref.of_regval v) else
+  if reg_name = "x28" then OPTION_MAP (\ v .  x28_ref.write_to v s) (x28_ref.of_regval v) else
+  if reg_name = "x27" then OPTION_MAP (\ v .  x27_ref.write_to v s) (x27_ref.of_regval v) else
+  if reg_name = "x26" then OPTION_MAP (\ v .  x26_ref.write_to v s) (x26_ref.of_regval v) else
+  if reg_name = "x25" then OPTION_MAP (\ v .  x25_ref.write_to v s) (x25_ref.of_regval v) else
+  if reg_name = "x24" then OPTION_MAP (\ v .  x24_ref.write_to v s) (x24_ref.of_regval v) else
+  if reg_name = "x23" then OPTION_MAP (\ v .  x23_ref.write_to v s) (x23_ref.of_regval v) else
+  if reg_name = "x22" then OPTION_MAP (\ v .  x22_ref.write_to v s) (x22_ref.of_regval v) else
+  if reg_name = "x21" then OPTION_MAP (\ v .  x21_ref.write_to v s) (x21_ref.of_regval v) else
+  if reg_name = "x20" then OPTION_MAP (\ v .  x20_ref.write_to v s) (x20_ref.of_regval v) else
+  if reg_name = "x19" then OPTION_MAP (\ v .  x19_ref.write_to v s) (x19_ref.of_regval v) else
+  if reg_name = "x18" then OPTION_MAP (\ v .  x18_ref.write_to v s) (x18_ref.of_regval v) else
+  if reg_name = "x17" then OPTION_MAP (\ v .  x17_ref.write_to v s) (x17_ref.of_regval v) else
+  if reg_name = "x16" then OPTION_MAP (\ v .  x16_ref.write_to v s) (x16_ref.of_regval v) else
+  if reg_name = "x15" then OPTION_MAP (\ v .  x15_ref.write_to v s) (x15_ref.of_regval v) else
+  if reg_name = "x14" then OPTION_MAP (\ v .  x14_ref.write_to v s) (x14_ref.of_regval v) else
+  if reg_name = "x13" then OPTION_MAP (\ v .  x13_ref.write_to v s) (x13_ref.of_regval v) else
+  if reg_name = "x12" then OPTION_MAP (\ v .  x12_ref.write_to v s) (x12_ref.of_regval v) else
+  if reg_name = "x11" then OPTION_MAP (\ v .  x11_ref.write_to v s) (x11_ref.of_regval v) else
+  if reg_name = "x10" then OPTION_MAP (\ v .  x10_ref.write_to v s) (x10_ref.of_regval v) else
+  if reg_name = "x9" then OPTION_MAP (\ v .  x9_ref.write_to v s) (x9_ref.of_regval v) else
+  if reg_name = "x8" then OPTION_MAP (\ v .  x8_ref.write_to v s) (x8_ref.of_regval v) else
+  if reg_name = "x7" then OPTION_MAP (\ v .  x7_ref.write_to v s) (x7_ref.of_regval v) else
+  if reg_name = "x6" then OPTION_MAP (\ v .  x6_ref.write_to v s) (x6_ref.of_regval v) else
+  if reg_name = "x5" then OPTION_MAP (\ v .  x5_ref.write_to v s) (x5_ref.of_regval v) else
+  if reg_name = "x4" then OPTION_MAP (\ v .  x4_ref.write_to v s) (x4_ref.of_regval v) else
+  if reg_name = "x3" then OPTION_MAP (\ v .  x3_ref.write_to v s) (x3_ref.of_regval v) else
+  if reg_name = "x2" then OPTION_MAP (\ v .  x2_ref.write_to v s) (x2_ref.of_regval v) else
+  if reg_name = "x1" then OPTION_MAP (\ v .  x1_ref.write_to v s) (x1_ref.of_regval v) else
   if reg_name = "Xs" then OPTION_MAP (\ v .  Xs_ref.write_to v s) (Xs_ref.of_regval v) else
   if reg_name = "nextPC" then OPTION_MAP (\ v .  nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else
   if reg_name = "PC" then OPTION_MAP (\ v .  PC_ref.write_to v s) (PC_ref.of_regval v) else
-- 
cgit v1.2.3


From 63fccf3902edbeb7816e6c419b0cbdcfea423cb9 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Tue, 10 Jul 2018 22:39:23 +0100
Subject: Update CHERI code extraction from Isabelle

Also use zero-initialised memory.  Apparently some tests access unitialised
memory, and the default behaviour of the Lem shallow embedding is to fail in
this case.
---
 mips/mips_extras.lem         |  7 +++++-
 test/isabelle/Cheri_code.thy | 51 ++++++++++++++++++++++++++++++++------------
 test/isabelle/run_cheri.ml   |  4 ++--
 3 files changed, 45 insertions(+), 17 deletions(-)

diff --git a/mips/mips_extras.lem b/mips/mips_extras.lem
index 86e78586..4edb0066 100644
--- a/mips/mips_extras.lem
+++ b/mips/mips_extras.lem
@@ -111,7 +111,12 @@ val elf_entry : unit -> integer
 let elf_entry () = 0
 declare ocaml target_rep function elf_entry = `Elf_loader.elf_entry`
 
-let print_bits msg bs = prerr_endline (msg ^ (string_of_bv bs))
+let print_bits msg bs = print_endline (msg ^ (string_of_bv bs))
+let prerr_bits msg bs = prerr_endline (msg ^ (string_of_bv bs))
+
+val prerr_string : string -> unit
+let prerr_string _ = ()
+declare ocaml target_rep function prerr_string = `Pervasives.prerr_string`
 
 val get_time_ns : unit -> integer
 let get_time_ns () = 0
diff --git a/test/isabelle/Cheri_code.thy b/test/isabelle/Cheri_code.thy
index 13884ad5..c0e8f9a7 100644
--- a/test/isabelle/Cheri_code.thy
+++ b/test/isabelle/Cheri_code.thy
@@ -5,32 +5,55 @@ begin
 declare [[code abort: failwith]]
 
 code_datatype
-  DADDIU DADDU DADDI DADD ADD ADDI ADDU ADDIU DSUBU DSUB SUB SUBU AND0 ANDI OR0 
+  DADDIU DADDU DADDI DADD ADD ADDI ADDU ADDIU DSUBU DSUB SUB SUBU AND0 ANDI OR0
   ORI NOR XOR0 XORI LUI DSLL DSLL32 DSLLV DSRA DSRA32 DSRAV DSRL DSRL32 DSRLV SLL
   SLLV SRA SRAV SRL SRLV SLT SLTI SLTU SLTIU MOVN MOVZ MFHI MFLO MTHI MTLO MUL
   MULT MULTU DMULT DMULTU MADD MADDU MSUB MSUBU DIV DIVU DDIV DDIVU J JAL JR JALR
-  BEQ BCMPZ SYSCALL_THREAD_START ImplementationDefinedStopFetching SYSCALL BREAK
-  WAIT TRAPREG TRAPIMM Load Store LWL LWR SWL SWR LDL LDR SDL SDR CACHE PREF SYNC
-  MFC0 HCF MTC0 TLBWI TLBWR TLBR TLBP RDHWR ERET CGetPerm CGetType CGetBase
-  CGetLen CGetTag CGetSealed CGetOffset CGetPCC CGetPCCSetOffset CGetCause
-  CSetCause CReadHwr CWriteHwr CAndPerm CToPtr CSub CPtrCmp CIncOffset
-  CIncOffsetImmediate CSetOffset CSetBounds CSetBoundsImmediate CSetBoundsExact
-  CClearTag CMOVX ClearRegs CFromPtr CBuildCap CCopyType CCheckPerm CCheckType
-  CTestSubset CSeal CCSeal CUnseal CCall CReturn CBX CBZ CJALR CLoad CStore CSC
-  CLC C2Dump RI CGetAddr
-
-termination whileM sorry
+  BEQ BCMPZ SYSCALL BREAK WAIT TRAPREG TRAPIMM Load Store LWL LWR SWL SWR LDL LDR
+  SDL SDR CACHE SYNC MFC0 HCF MTC0 TLBWI TLBWR TLBR TLBP RDHWR ERET CGetPerm
+  CGetType CGetBase CGetLen CGetTag CGetSealed CGetOffset CGetPCC
+  CGetPCCSetOffset CGetCause CSetCause CReadHwr CWriteHwr CAndPerm CToPtr CSub
+  CPtrCmp CIncOffset CIncOffsetImmediate CSetOffset CSetBounds
+  CSetBoundsImmediate CSetBoundsExact CClearTag CMOVX ClearRegs CFromPtr
+  CBuildCap CCopyType CCheckPerm CCheckType CTestSubset CSeal CCSeal CUnseal
+  CCall CReturn CBX CBZ CJALR CLoad CStore CSC CLC C2Dump RI CGetAddr
+
+(* Fake termination proofs of loops for code generation *)
+lemma whileM_dom: "whileM_dom (vars, cond, body)" sorry
+termination whileM using whileM_dom by auto
+lemma whileS_dom: "whileS_dom (vars, cond, body, s)" sorry
+termination whileS using whileS_dom by auto
+
+lemma liftS_whileM: "\<lbrakk>whileM vars cond body\<rbrakk>\<^sub>S = whileS vars (liftS \<circ> cond) (liftS \<circ> body)"
+  by (intro ext liftState_whileM[OF whileS_dom whileM_dom])
+
+(* Pre-lift main loop to state monad to gain some performance *)
+fun mainS :: "unit \<Rightarrow> (regstate, unit, exception) monadS" where
+  "mainS () = \<lbrakk>main ()\<rbrakk>\<^sub>S"
+
+schematic_goal liftS_main[symmetric, code]: "?m = mainS"
+  by (intro ext)
+     (simp add: main_def liftState_simp liftS_whileM comp_def del: whileM.simps whileS.simps
+           cong: bindS_cong if_cong)
+
+fun print_endline' :: "String.literal \<Rightarrow> unit" where "print_endline' _ = ()"
+lemma [code]: "print_endline s = print_endline' (String.implode s)" by auto
 
 fun prerr_endline' :: "String.literal \<Rightarrow> unit" where "prerr_endline' _ = ()"
 lemma [code]: "prerr_endline s = prerr_endline' (String.implode s)" by auto
 
+fun prerr_string' :: "String.literal \<Rightarrow> unit" where "prerr_string' _ = ()"
+lemma [code]: "prerr_string s = prerr_string' (String.implode s)" by auto
+
 fun putchar' :: "char \<Rightarrow> unit" where "putchar' _ = ()"
 lemma [code]: "putchar c = putchar' (char_of_nat (nat c))" by auto
 
 code_identifier code_module List \<rightharpoonup> (OCaml) "List0"
 code_printing constant String.implode \<rightharpoonup> (OCaml) "!(let l = _ in let res = Bytes.create (List.length l) in let rec imp i = function | [] -> res | c :: l -> Bytes.set res i c; imp (i + 1) l in imp 0 l)"
 
+code_printing constant print_endline' \<rightharpoonup> (OCaml) "Pervasives.print'_endline"
 code_printing constant prerr_endline' \<rightharpoonup> (OCaml) "Pervasives.prerr'_endline"
+code_printing constant prerr_string' \<rightharpoonup> (OCaml) "Pervasives.prerr'_string"
 code_printing constant putchar' \<rightharpoonup> (OCaml) "Pervasives.print'_char"
 
 declare insert_code[code del]
@@ -50,12 +73,12 @@ fun write_char_mem :: "int \<Rightarrow> char \<Rightarrow> (regstate, unit, exc
      bindS (write_mem_valS BC_bitU_list (bits_of_nat 8 (nat_of_char c))) (\<lambda>_.
      returnS ()))"
 
-definition "initial_state \<equiv> init_state initial_regstate"
+definition "initial_state \<equiv> init_state initial_regstate\<lparr>memstate := (\<lambda>_. Some [B0, B0, B0, B0, B0, B0, B0, B0])\<rparr>"
 
 code_printing constant elf_entry \<rightharpoonup> (OCaml) "(Arith.Int'_of'_integer (Elf'_loader.elf'_entry _))"
 code_printing constant get_time_ns \<rightharpoonup> (OCaml) "(Arith.Int'_of'_integer (Big'_int.big'_int'_of'_int (Pervasives.int'_of'_float (1e9 *. Unix.gettimeofday _))))"
 
-export_code main initial_state liftState get_regval set_regval bindS returnS iteriS iterS
+export_code mainS initial_state liftState get_regval set_regval bindS returnS iteriS iterS
   write_char_mem integer_of_int int_of_integer "op + :: int \<Rightarrow> int \<Rightarrow> int" prerr_results
   in OCaml file "cheri_export.ml"
 
diff --git a/test/isabelle/run_cheri.ml b/test/isabelle/run_cheri.ml
index 283e4283..c50d525d 100644
--- a/test/isabelle/run_cheri.ml
+++ b/test/isabelle/run_cheri.ml
@@ -64,7 +64,7 @@ let () =
   Arg.parse options (fun s -> opt_file_arguments := !opt_file_arguments @ [s]) usage_msg
 
 let (>>) = Sail2_state_monad.bindS
-let liftS = Sail2_state_lifting.liftState (Cheri_types.get_regval, Cheri_types.set_regval)
+(*let liftS = Sail2_state_lifting.liftState (Cheri_types.get_regval, Cheri_types.set_regval)*)
 
 let load_elf_segment seg =
   let open Elf_interpreted_segment in
@@ -89,4 +89,4 @@ let _ =
   (* State_monad.prerr_results *)
     (Cheri_code.initial_state |>
     (Sail2_state.iterS load_elf_segment elf_segments >> (fun _ ->
-    liftS (Cheri.main ()))));
+    (Cheri_code.mainS ()))));
-- 
cgit v1.2.3


From d559aefa947c53f84a6aeb2dc67106a21d4cfb68 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Tue, 10 Jul 2018 22:44:27 +0100
Subject: Fix some signedness bugs

add_vec_int and similar functions in the Lem library used unsigned instead of
signed conversion.
---
 lib/isabelle/Sail2_operators_mwords_lemmas.thy |  9 +++---
 src/gen_lib/sail2_operators_bitlists.lem       | 38 +++++++++-----------------
 src/gen_lib/sail2_operators_mwords.lem         | 38 +++++++++-----------------
 3 files changed, 31 insertions(+), 54 deletions(-)

diff --git a/lib/isabelle/Sail2_operators_mwords_lemmas.thy b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
index fd54c93a..47bf32b2 100644
--- a/lib/isabelle/Sail2_operators_mwords_lemmas.thy
+++ b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
@@ -153,10 +153,11 @@ declare adds_vec_def[simp]
 declare subs_vec_def[simp]
 declare mults_vec_def[simp]
 
-lemma arith_vec_int_simps[simp]:
-  "add_vec_int l r = l + (word_of_int r)"
-  "sub_vec_int l r = l - (word_of_int r)"
-  "mult_vec_int l r = (ucast l) * (word_of_int r)"
+lemma arith_vec_int_simps:
+  fixes l :: "'a::len word"
+  shows "add_vec_int l r = word_of_int (sint l + sint (word_of_int r :: 'a word))"
+    and "sub_vec_int l r = word_of_int (sint l - sint (word_of_int r :: 'a word))"
+    and "(mult_vec_int l r :: 'b::len word) = word_of_int (sint (scast l :: 'b word) * sint (word_of_int r :: 'b word))"
   unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
   by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
 
diff --git a/src/gen_lib/sail2_operators_bitlists.lem b/src/gen_lib/sail2_operators_bitlists.lem
index 0c833e90..b9a2fa86 100644
--- a/src/gen_lib/sail2_operators_bitlists.lem
+++ b/src/gen_lib/sail2_operators_bitlists.lem
@@ -145,31 +145,19 @@ let subs_vec  = arith_op_bv integerMinus true
 let mult_vec  = arith_op_double_bl integerMult false
 let mults_vec = arith_op_double_bl integerMult true
 
-val add_vec_int       : list bitU -> integer -> list bitU
-val adds_vec_int      : list bitU -> integer -> list bitU
-val sub_vec_int       : list bitU -> integer -> list bitU
-val subs_vec_int      : list bitU -> integer -> list bitU
-val mult_vec_int      : list bitU -> integer -> list bitU
-val mults_vec_int     : list bitU -> integer -> list bitU
-let add_vec_int   l r = arith_op_bv_int integerAdd false l r
-let adds_vec_int  l r = arith_op_bv_int integerAdd true l r
-let sub_vec_int   l r = arith_op_bv_int integerMinus false l r
-let subs_vec_int  l r = arith_op_bv_int integerMinus true l r
-let mult_vec_int  l r = arith_op_double_bl integerMult false l (of_int (length l) r)
-let mults_vec_int l r = arith_op_double_bl integerMult true l (of_int (length l) r)
-
-val add_int_vec       : integer -> list bitU -> list bitU
-val adds_int_vec      : integer -> list bitU -> list bitU
-val sub_int_vec       : integer -> list bitU -> list bitU
-val subs_int_vec      : integer -> list bitU -> list bitU
-val mult_int_vec      : integer -> list bitU -> list bitU
-val mults_int_vec     : integer -> list bitU -> list bitU
-let add_int_vec   l r = arith_op_int_bv integerAdd false l r
-let adds_int_vec  l r = arith_op_int_bv integerAdd true l r
-let sub_int_vec   l r = arith_op_int_bv integerMinus false l r
-let subs_int_vec  l r = arith_op_int_bv integerMinus true l r
-let mult_int_vec  l r = arith_op_double_bl integerMult false (of_int (length r) l) r
-let mults_int_vec l r = arith_op_double_bl integerMult true (of_int (length r) l) r
+val add_vec_int      : list bitU -> integer -> list bitU
+val sub_vec_int      : list bitU -> integer -> list bitU
+val mult_vec_int     : list bitU -> integer -> list bitU
+let add_vec_int  l r = arith_op_bv_int integerAdd true l r
+let sub_vec_int  l r = arith_op_bv_int integerMinus true l r
+let mult_vec_int l r = arith_op_double_bl integerMult true l (of_int (length l) r)
+
+val add_int_vec      : integer -> list bitU -> list bitU
+val sub_int_vec      : integer -> list bitU -> list bitU
+val mult_int_vec     : integer -> list bitU -> list bitU
+let add_int_vec  l r = arith_op_int_bv integerAdd true l r
+let sub_int_vec  l r = arith_op_int_bv integerMinus true l r
+let mult_int_vec l r = arith_op_double_bl integerMult true (of_int (length r) l) r
 
 val add_vec_bit      : list bitU -> bitU -> list bitU
 val adds_vec_bit     : list bitU -> bitU -> list bitU
diff --git a/src/gen_lib/sail2_operators_mwords.lem b/src/gen_lib/sail2_operators_mwords.lem
index 61048ac5..c0b7f2d1 100644
--- a/src/gen_lib/sail2_operators_mwords.lem
+++ b/src/gen_lib/sail2_operators_mwords.lem
@@ -142,31 +142,19 @@ let subs_vec  l r = arith_op_bv integerMinus true  l r
 let mult_vec  l r = arith_op_bv integerMult  false (zeroExtend l : mword 'b) (zeroExtend r : mword 'b)
 let mults_vec l r = arith_op_bv integerMult  true  (signExtend l : mword 'b) (signExtend r : mword 'b)
 
-val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
-val adds_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
-val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
-val subs_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
-val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
-val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
-let add_vec_int   l r = arith_op_bv_int integerAdd   false l r
-let adds_vec_int  l r = arith_op_bv_int integerAdd   true  l r
-let sub_vec_int   l r = arith_op_bv_int integerMinus false l r
-let subs_vec_int  l r = arith_op_bv_int integerMinus true  l r
-let mult_vec_int  l r = arith_op_bv_int integerMult  false (zeroExtend l : mword 'b) r
-let mults_vec_int l r = arith_op_bv_int integerMult  true  (signExtend l : mword 'b) r
-
-val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
-val adds_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
-val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
-val subs_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
-val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
-val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
-let add_int_vec   l r = arith_op_int_bv integerAdd   false l r
-let adds_int_vec  l r = arith_op_int_bv integerAdd   true  l r
-let sub_int_vec   l r = arith_op_int_bv integerMinus false l r
-let subs_int_vec  l r = arith_op_int_bv integerMinus true  l r
-let mult_int_vec  l r = arith_op_int_bv integerMult  false l (zeroExtend r : mword 'b)
-let mults_int_vec l r = arith_op_int_bv integerMult  true  l (signExtend r : mword 'b)
+val add_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sub_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
+let add_vec_int  l r = arith_op_bv_int integerAdd   true  l r
+let sub_vec_int  l r = arith_op_bv_int integerMinus true  l r
+let mult_vec_int l r = arith_op_bv_int integerMult  true  (signExtend l : mword 'b) r
+
+val add_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sub_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+let add_int_vec  l r = arith_op_int_bv integerAdd   true  l r
+let sub_int_vec  l r = arith_op_int_bv integerMinus true  l r
+let mult_int_vec l r = arith_op_int_bv integerMult  true  l (signExtend r : mword 'b)
 
 val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a
 val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a
-- 
cgit v1.2.3


From 443fec23008a47eceb8ecb1ad5876e1d5d5e16af Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Tue, 10 Jul 2018 22:48:16 +0100
Subject: Fix off-by-one bugs in monomorphisation rewrites involving bitvector
 subranges

CHERI test suite now passes using Isabelle-generated emulator
---
 lib/mono_rewrites.sail | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/lib/mono_rewrites.sail b/lib/mono_rewrites.sail
index c9164b6c..aa8d05cd 100644
--- a/lib/mono_rewrites.sail
+++ b/lib/mono_rewrites.sail
@@ -42,14 +42,14 @@ val is_zero_subrange : forall 'n, 'n >= 0.
   (bits('n), int, int) -> bool effect pure
 
 function is_zero_subrange (xs, i, j) = {
-  (xs & slice_mask(j, i-j)) == extzv(0b0)
+  (xs & slice_mask(j, i-j+1)) == extzv(0b0)
 }
 
 val is_ones_subrange : forall 'n, 'n >= 0.
   (bits('n), int, int) -> bool effect pure
 
 function is_ones_subrange (xs, i, j) = {
-  let m : bits('n) = slice_mask(j,j-i) in
+  let m : bits('n) = slice_mask(j,j-i+1) in
   (xs & m) == m
 }
 
@@ -76,8 +76,8 @@ val subrange_subrange_eq : forall 'n, 'n >= 0.
   (bits('n), int, int, bits('n), int, int) -> bool effect pure
 
 function subrange_subrange_eq (xs, i, j, ys, i', j') = {
-  let xs = (xs & slice_mask(j,i-j)) >> j in
-  let ys = (ys & slice_mask(j',i'-j')) >> j' in
+  let xs = (xs & slice_mask(j,i-j+1)) >> j in
+  let ys = (ys & slice_mask(j',i'-j'+1)) >> j' in
   xs == ys
 }
 
@@ -85,16 +85,16 @@ val subrange_subrange_concat : forall 'n 'o 'p 'm 'q 'r 's, 's = 'o - ('p - 1) +
   (bits('n), atom('o), atom('p), bits('m), atom('q), atom('r)) -> bits('s) effect pure
 
 function subrange_subrange_concat (xs, i, j, ys, i', j') = {
-  let xs = (xs & slice_mask(j,i-j)) >> j in
-  let ys = (ys & slice_mask(j',i'-j')) >> j' in
-  extzv(xs) << i' - (j' - 1) | extzv(ys)
+  let xs = (xs & slice_mask(j,i-j+1)) >> j in
+  let ys = (ys & slice_mask(j',i'-j'+1)) >> j' in
+  extzv(xs) << (i' - j' + 1) | extzv(ys)
 }
 
 val place_subrange : forall 'n 'm, 'n >= 0 & 'm >= 0.
   (bits('n), int, int, int) -> bits('m) effect pure
 
 function place_subrange(xs,i,j,shift) = {
-  let xs = (xs & slice_mask(j,i-j)) >> j in
+  let xs = (xs & slice_mask(j,i-j+1)) >> j in
   extzv(xs) << shift
 }
 
@@ -144,7 +144,7 @@ val unsigned_subrange : forall 'n, 'n >= 0.
   (bits('n), int, int) -> int effect pure
 
 function unsigned_subrange(xs,i,j) = {
-  let xs = (xs & slice_mask(j,i-j)) >> i in
+  let xs = (xs & slice_mask(j,i-j+1)) >> i in
   _builtin_unsigned(xs)
 }
 
-- 
cgit v1.2.3


From 9bdd053dfca7c3e3ac6717a7d2b112ef17e20895 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Wed, 11 Jul 2018 00:14:57 +0100
Subject: Update Isabelle snapshots

Except RISC-V duopod, which doesn't seem to build for me at the moment
---
 snapshots/isabelle/aarch64/Aarch64.thy             |  4084 ++--
 snapshots/isabelle/aarch64/Aarch64_lemmas.thy      |  1011 +-
 snapshots/isabelle/aarch64/Aarch64_types.thy       |    53 +-
 snapshots/isabelle/cheri/Cheri.thy                 |  6692 +++---
 snapshots/isabelle/cheri/Cheri_lemmas.thy          |  1221 +-
 snapshots/isabelle/cheri/Cheri_types.thy           |   236 +-
 snapshots/isabelle/cheri/Mips_extras.thy           |   155 +-
 snapshots/isabelle/lib/lem/Lem_basic_classes.thy   |     1 +
 snapshots/isabelle/lib/lem/Lem_machine_word.thy    |     3 +-
 snapshots/isabelle/lib/lem/Lem_num.thy             |     4 +-
 snapshots/isabelle/lib/sail/Hoare.thy              |   257 +-
 snapshots/isabelle/lib/sail/Prompt.thy             |   150 -
 snapshots/isabelle/lib/sail/Prompt_monad.thy       |   267 -
 .../isabelle/lib/sail/Prompt_monad_lemmas.thy      |   170 -
 snapshots/isabelle/lib/sail/ROOT                   |    11 +-
 snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy  |   514 +
 snapshots/isabelle/lib/sail/Sail2_operators.thy    |   326 +
 .../isabelle/lib/sail/Sail2_operators_bitlists.thy |   737 +
 .../isabelle/lib/sail/Sail2_operators_mwords.thy   |   608 +
 .../lib/sail/Sail2_operators_mwords_lemmas.thy     |   170 +
 snapshots/isabelle/lib/sail/Sail2_prompt.thy       |   162 +
 snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy |   275 +
 .../lib/sail/Sail2_prompt_monad_lemmas.thy         |   212 +
 snapshots/isabelle/lib/sail/Sail2_state.thy        |   137 +
 snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy |   387 +
 .../isabelle/lib/sail/Sail2_state_lifting.thy      |    52 +
 snapshots/isabelle/lib/sail/Sail2_state_monad.thy  |   363 +
 .../isabelle/lib/sail/Sail2_state_monad_lemmas.thy |   238 +
 snapshots/isabelle/lib/sail/Sail2_string.thy       |   215 +
 snapshots/isabelle/lib/sail/Sail2_values.thy       |  1230 +
 .../isabelle/lib/sail/Sail2_values_lemmas.thy      |   340 +
 snapshots/isabelle/lib/sail/Sail_instr_kinds.thy   |   494 -
 snapshots/isabelle/lib/sail/Sail_operators.thy     |   326 -
 .../isabelle/lib/sail/Sail_operators_bitlists.thy  |   773 -
 .../isabelle/lib/sail/Sail_operators_mwords.thy    |   638 -
 .../lib/sail/Sail_operators_mwords_lemmas.thy      |   112 -
 snapshots/isabelle/lib/sail/Sail_values.thy        |  1215 -
 snapshots/isabelle/lib/sail/Sail_values_lemmas.thy |   206 -
 snapshots/isabelle/lib/sail/State.thy              |   102 -
 snapshots/isabelle/lib/sail/State_lemmas.thy       |   202 -
 snapshots/isabelle/lib/sail/State_monad.thy        |   375 -
 snapshots/isabelle/lib/sail/State_monad_lemmas.thy |   232 -
 snapshots/isabelle/riscv/Riscv.thy                 | 23733 ++++++++++++++++---
 snapshots/isabelle/riscv/Riscv_duopod.thy          |   461 -
 snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy   |    48 -
 snapshots/isabelle/riscv/Riscv_duopod_types.thy    |   170 -
 snapshots/isabelle/riscv/Riscv_extras.thy          |   173 +-
 snapshots/isabelle/riscv/Riscv_lemmas.thy          |   613 +-
 snapshots/isabelle/riscv/Riscv_types.thy           |   667 +-
 49 files changed, 34762 insertions(+), 16059 deletions(-)
 delete mode 100644 snapshots/isabelle/lib/sail/Prompt.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Prompt_monad.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_operators.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_prompt.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_state.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_state_lifting.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_state_monad.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_string.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_values.thy
 create mode 100644 snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_instr_kinds.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_operators.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_operators_mwords.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_values.thy
 delete mode 100644 snapshots/isabelle/lib/sail/Sail_values_lemmas.thy
 delete mode 100644 snapshots/isabelle/lib/sail/State.thy
 delete mode 100644 snapshots/isabelle/lib/sail/State_lemmas.thy
 delete mode 100644 snapshots/isabelle/lib/sail/State_monad.thy
 delete mode 100644 snapshots/isabelle/lib/sail/State_monad_lemmas.thy
 delete mode 100644 snapshots/isabelle/riscv/Riscv_duopod.thy
 delete mode 100644 snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy
 delete mode 100644 snapshots/isabelle/riscv/Riscv_duopod_types.thy

diff --git a/snapshots/isabelle/aarch64/Aarch64.thy b/snapshots/isabelle/aarch64/Aarch64.thy
index a117b761..c63ed15e 100644
--- a/snapshots/isabelle/aarch64/Aarch64.thy
+++ b/snapshots/isabelle/aarch64/Aarch64.thy
@@ -5,25 +5,25 @@ theory "Aarch64"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
+	 "/tmp/sail/src/lem_interp/Sail2_instr_kinds" 
+	 "/tmp/sail/src/gen_lib/Sail2_values" 
+	 "/tmp/sail/src/gen_lib/Sail2_operators_mwords" 
+	 "/tmp/sail/src/gen_lib/Sail2_prompt_monad" 
+	 "/tmp/sail/src/gen_lib/Sail2_prompt" 
+	 "/tmp/sail/src/gen_lib/Sail2_string" 
 	 "Aarch64_types" 
-	 "Aarch64_extras" 
+	 "/tmp/sail/aarch64/mono/Aarch64_extras" 
 
 begin 
 
 (*Generated by Sail from aarch64.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 (*open import Aarch64_types*)
 (*open import Aarch64_extras*)
 
@@ -60,7 +60,7 @@ definition neq_bool  :: " bool \<Rightarrow> bool \<Rightarrow> bool "  where
 definition GetSlice_int  :: "('n::len)itself \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
      " GetSlice_int n m o1 = (
    (let n = (size_itself_int n) in
-   (get_slice_int0 n m o1  :: ( 'n::len)Word.word)))"
+   (get_slice_int n m o1  :: ( 'n::len)Word.word)))"
 
 
 (*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*)
@@ -74,19 +74,11 @@ fun cast_unit_vec0  :: " bitU \<Rightarrow>(1)Word.word "  where
 |" cast_unit_vec0 B1 = ( (vec_of_bits [B1]  ::  1 Word.word))"
 
 
-(*val DecStr : ii -> string*)
+(*val BoolStr : bool -> string*)
 
-(*val HexStr : ii -> string*)
+definition BoolStr  :: " bool \<Rightarrow> string "  where 
+     " BoolStr b = ( if b then (''true'') else (''false''))"
 
-(*val __TraceMemoryWrite : forall  'm 'p8_times_n_ . integer -> bits 'm -> bits 'p8_times_n_ -> unit*)
-
-(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*)
-
-definition InitRAM  :: " int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> unit "  where 
-     " InitRAM g__615 g__616 g__617 g__618 = ( ()  )"
-
-
-(*val __TraceMemoryRead : forall  'm 'p8_times_n_ . integer -> bits 'm -> bits 'p8_times_n_ -> unit*)
 
 (*val ex_nat : ii -> integer*)
 
@@ -118,13 +110,48 @@ definition break  :: " unit \<Rightarrow> unit "  where
 
 definition undefined_exception  :: " unit \<Rightarrow>((register_value),(exception),(exception))monad "  where 
      " undefined_exception _ = (
-   (undefined_unit ()  \<then>
-   undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . 
-   undefined_string ()  \<bind> (\<lambda> (w__1 :: string) . 
-   (undefined_unit ()  \<then>
-   undefined_unit () ) \<then>
+   undefined_string ()  \<bind> (\<lambda> (u_0 :: string) . 
+   undefined_unit ()  \<bind> (\<lambda> (u_1 :: unit) . 
    internal_pick
-     [Error_Undefined () ,Error_See w__0,Error_Implementation_Defined w__1,Error_ReservedEncoding () ,Error_ExceptionTaken () ])))"
+     [Error_Undefined u_1,Error_See u_0,Error_Implementation_Defined u_0,Error_ReservedEncoding u_1,Error_ExceptionTaken u_1])))"
+
+
+(*val __GetVerbosity : unit -> M (bits ty64)*)
+
+(*val get_cycle_count : unit -> M ii*)
+
+(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*)
+
+definition InitRAM  :: " int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> unit "  where 
+     " InitRAM g__302 g__303 g__304 g__305 = ( ()  )"
+
+
+(*val __ReadRAM : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> M (mword 'p8_times_n_)*)
+
+definition ReadRAM  :: "('m::len)itself \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>('m::len)Word.word \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad "  where 
+     " ReadRAM addr_length bytes hex_ram addr = (
+   (let addr_length = (size_itself_int addr_length) in
+   (read_ram addr_length bytes hex_ram addr  :: (( 'p8_times_n_::len)Word.word) M)))"
+
+
+(*val __TraceMemoryWrite : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*)
+
+(*val __WriteRAM : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> mword 'p8_times_n_ -> M unit*)
+
+definition WriteRAM  :: "('m::len)itself \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " WriteRAM addr_length bytes hex_ram addr data = (
+   (let addr_length = (size_itself_int addr_length) in
+   write_ram addr_length bytes hex_ram addr data))"
+
+
+definition TraceMemoryWrite  :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow> unit "  where 
+     " TraceMemoryWrite bytes addr data = ( ()  )"
+
+
+(*val __TraceMemoryRead : forall  'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*)
+
+definition TraceMemoryRead  :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow> unit "  where 
+     " TraceMemoryRead bytes addr data = ( ()  )"
 
 
 (*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
@@ -151,14 +178,17 @@ definition slice_mask  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow
 
 definition is_zero_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
      " is_zero_subrange xs i j = (
-   (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0]  ::  1 Word.word)  :: ( 'n::len)Word.word))))"
+   (((and_vec xs
+         ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+        :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0]  ::  1 Word.word)  :: ( 'n::len)Word.word))))"
 
 
 (*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
 
 definition is_ones_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
      " is_ones_subrange xs i j = (
-   (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i))  :: ( 'n::len)Word.word)) in
+   (let (m :: 'n bits) =
+     ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word)) in
    (((and_vec xs m  :: ( 'n::len)Word.word)) = m)))"
 
 
@@ -190,12 +220,15 @@ definition subrange_subrange_eq  :: "('n::len)Word.word \<Rightarrow> int \<Righ
      " subrange_subrange_eq xs i j ys i' j' = (
    (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) j
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j
        :: ( 'n::len)Word.word)) in
    (let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j'))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int (size xs))) j' ((((i' - j')) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j'
        :: ( 'n::len)Word.word)) in
    (xs = ys))))"
 
@@ -206,16 +239,18 @@ definition subrange_subrange_concat  :: " int \<Rightarrow>('n::len)Word.word \<
      " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = (
    (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) j
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j
        :: ( 'n::len)Word.word)) in
    (let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j'))  :: ( 'm::len)Word.word))  :: ( 'm::len)Word.word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int (size ys))) j' ((((i' - j')) + (( 1 :: int)::ii)))  :: ( 'm::len)Word.word))
+           :: ( 'm::len)Word.word)) j'
        :: ( 'm::len)Word.word)) in
    (or_vec
-      ((sub_vec_int ((shiftl ((extzv s__tv xs  :: ( 's::len)Word.word)) i'  :: ( 's::len)Word.word))
-          ((j' - (( 1 :: int)::ii)))
+      ((shiftl ((extzv s__tv xs  :: ( 's::len)Word.word)) ((((i' - j')) + (( 1 :: int)::ii)))
          :: ( 's::len)Word.word)) ((extzv s__tv ys  :: ( 's::len)Word.word))
      :: ( 's::len)Word.word))))"
 
@@ -226,7 +261,9 @@ definition place_subrange  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow
      " place_subrange (m__tv :: int) xs i j shift = (
    (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) j
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j
        :: ( 'n::len)Word.word)) in
    (shiftl ((extzv m__tv xs  :: ( 'm::len)Word.word)) shift  :: ( 'm::len)Word.word)))"
 
@@ -277,7 +314,9 @@ definition unsigned_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightar
      " unsigned_subrange xs i j = (
    (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) i
        :: ( 'n::len)Word.word)) in
    Word.uint xs))"
 
@@ -294,8 +333,8 @@ definition zext_ones  :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word
 
 definition boolean_of_num  :: " int \<Rightarrow> boolean "  where 
      " boolean_of_num arg0 = (
-   (let l__595 = arg0 in
-   if (((l__595 = (( 0 :: int)::ii)))) then FALSE
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FALSE
    else TRUE))"
 
 
@@ -316,8 +355,8 @@ definition undefined_boolean  :: " unit \<Rightarrow>((register_value),(boolean)
 
 definition signal_of_num  :: " int \<Rightarrow> signal "  where 
      " signal_of_num arg0 = (
-   (let l__594 = arg0 in
-   if (((l__594 = (( 0 :: int)::ii)))) then LOW
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then LOW
    else HIGH))"
 
 
@@ -338,15 +377,15 @@ definition undefined_signal  :: " unit \<Rightarrow>((register_value),(signal),(
 
 definition RetCode_of_num  :: " int \<Rightarrow> RetCode "  where 
      " RetCode_of_num arg0 = (
-   (let l__586 = arg0 in
-   if (((l__586 = (( 0 :: int)::ii)))) then RC_OK
-   else if (((l__586 = (( 1 :: int)::ii)))) then RC_UNDEFINED
-   else if (((l__586 = (( 2 :: int)::ii)))) then RC_UNPREDICTABLE
-   else if (((l__586 = (( 3 :: int)::ii)))) then RC_SEE
-   else if (((l__586 = (( 4 :: int)::ii)))) then RC_IMPLEMENTATION_DEFINED
-   else if (((l__586 = (( 5 :: int)::ii)))) then RC_SUBARCHITECTURE_DEFINED
-   else if (((l__586 = (( 6 :: int)::ii)))) then RC_EXCEPTION_TAKEN
-   else if (((l__586 = (( 7 :: int)::ii)))) then RC_ASSERT_FAILED
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RC_OK
+   else if (((p00 = (( 1 :: int)::ii)))) then RC_UNDEFINED
+   else if (((p00 = (( 2 :: int)::ii)))) then RC_UNPREDICTABLE
+   else if (((p00 = (( 3 :: int)::ii)))) then RC_SEE
+   else if (((p00 = (( 4 :: int)::ii)))) then RC_IMPLEMENTATION_DEFINED
+   else if (((p00 = (( 5 :: int)::ii)))) then RC_SUBARCHITECTURE_DEFINED
+   else if (((p00 = (( 6 :: int)::ii)))) then RC_EXCEPTION_TAKEN
+   else if (((p00 = (( 7 :: int)::ii)))) then RC_ASSERT_FAILED
    else RC_UNMATCHED_CASE))"
 
 
@@ -376,11 +415,11 @@ definition undefined___RetCode  :: " unit \<Rightarrow>((register_value),(RetCod
 
 definition FPConvOp_of_num  :: " int \<Rightarrow> FPConvOp "  where 
      " FPConvOp_of_num arg0 = (
-   (let l__582 = arg0 in
-   if (((l__582 = (( 0 :: int)::ii)))) then FPConvOp_CVT_FtoI
-   else if (((l__582 = (( 1 :: int)::ii)))) then FPConvOp_CVT_ItoF
-   else if (((l__582 = (( 2 :: int)::ii)))) then FPConvOp_MOV_FtoI
-   else if (((l__582 = (( 3 :: int)::ii)))) then FPConvOp_MOV_ItoF
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FPConvOp_CVT_FtoI
+   else if (((p00 = (( 1 :: int)::ii)))) then FPConvOp_CVT_ItoF
+   else if (((p00 = (( 2 :: int)::ii)))) then FPConvOp_MOV_FtoI
+   else if (((p00 = (( 3 :: int)::ii)))) then FPConvOp_MOV_ItoF
    else FPConvOp_CVT_FtoI_JS))"
 
 
@@ -406,35 +445,35 @@ definition undefined_FPConvOp  :: " unit \<Rightarrow>((register_value),(FPConvO
 
 definition Exception_of_num  :: " int \<Rightarrow> Exception "  where 
      " Exception_of_num arg0 = (
-   (let l__554 = arg0 in
-   if (((l__554 = (( 0 :: int)::ii)))) then Exception_Uncategorized
-   else if (((l__554 = (( 1 :: int)::ii)))) then Exception_WFxTrap
-   else if (((l__554 = (( 2 :: int)::ii)))) then Exception_CP15RTTrap
-   else if (((l__554 = (( 3 :: int)::ii)))) then Exception_CP15RRTTrap
-   else if (((l__554 = (( 4 :: int)::ii)))) then Exception_CP14RTTrap
-   else if (((l__554 = (( 5 :: int)::ii)))) then Exception_CP14DTTrap
-   else if (((l__554 = (( 6 :: int)::ii)))) then Exception_AdvSIMDFPAccessTrap
-   else if (((l__554 = (( 7 :: int)::ii)))) then Exception_FPIDTrap
-   else if (((l__554 = (( 8 :: int)::ii)))) then Exception_PACTrap
-   else if (((l__554 = (( 9 :: int)::ii)))) then Exception_CP14RRTTrap
-   else if (((l__554 = (( 10 :: int)::ii)))) then Exception_IllegalState
-   else if (((l__554 = (( 11 :: int)::ii)))) then Exception_SupervisorCall
-   else if (((l__554 = (( 12 :: int)::ii)))) then Exception_HypervisorCall
-   else if (((l__554 = (( 13 :: int)::ii)))) then Exception_MonitorCall
-   else if (((l__554 = (( 14 :: int)::ii)))) then Exception_SystemRegisterTrap
-   else if (((l__554 = (( 15 :: int)::ii)))) then Exception_ERetTrap
-   else if (((l__554 = (( 16 :: int)::ii)))) then Exception_InstructionAbort
-   else if (((l__554 = (( 17 :: int)::ii)))) then Exception_PCAlignment
-   else if (((l__554 = (( 18 :: int)::ii)))) then Exception_DataAbort
-   else if (((l__554 = (( 19 :: int)::ii)))) then Exception_SPAlignment
-   else if (((l__554 = (( 20 :: int)::ii)))) then Exception_FPTrappedException
-   else if (((l__554 = (( 21 :: int)::ii)))) then Exception_SError
-   else if (((l__554 = (( 22 :: int)::ii)))) then Exception_Breakpoint
-   else if (((l__554 = (( 23 :: int)::ii)))) then Exception_SoftwareStep
-   else if (((l__554 = (( 24 :: int)::ii)))) then Exception_Watchpoint
-   else if (((l__554 = (( 25 :: int)::ii)))) then Exception_SoftwareBreakpoint
-   else if (((l__554 = (( 26 :: int)::ii)))) then Exception_VectorCatch
-   else if (((l__554 = (( 27 :: int)::ii)))) then Exception_IRQ
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Exception_Uncategorized
+   else if (((p00 = (( 1 :: int)::ii)))) then Exception_WFxTrap
+   else if (((p00 = (( 2 :: int)::ii)))) then Exception_CP15RTTrap
+   else if (((p00 = (( 3 :: int)::ii)))) then Exception_CP15RRTTrap
+   else if (((p00 = (( 4 :: int)::ii)))) then Exception_CP14RTTrap
+   else if (((p00 = (( 5 :: int)::ii)))) then Exception_CP14DTTrap
+   else if (((p00 = (( 6 :: int)::ii)))) then Exception_AdvSIMDFPAccessTrap
+   else if (((p00 = (( 7 :: int)::ii)))) then Exception_FPIDTrap
+   else if (((p00 = (( 8 :: int)::ii)))) then Exception_PACTrap
+   else if (((p00 = (( 9 :: int)::ii)))) then Exception_CP14RRTTrap
+   else if (((p00 = (( 10 :: int)::ii)))) then Exception_IllegalState
+   else if (((p00 = (( 11 :: int)::ii)))) then Exception_SupervisorCall
+   else if (((p00 = (( 12 :: int)::ii)))) then Exception_HypervisorCall
+   else if (((p00 = (( 13 :: int)::ii)))) then Exception_MonitorCall
+   else if (((p00 = (( 14 :: int)::ii)))) then Exception_SystemRegisterTrap
+   else if (((p00 = (( 15 :: int)::ii)))) then Exception_ERetTrap
+   else if (((p00 = (( 16 :: int)::ii)))) then Exception_InstructionAbort
+   else if (((p00 = (( 17 :: int)::ii)))) then Exception_PCAlignment
+   else if (((p00 = (( 18 :: int)::ii)))) then Exception_DataAbort
+   else if (((p00 = (( 19 :: int)::ii)))) then Exception_SPAlignment
+   else if (((p00 = (( 20 :: int)::ii)))) then Exception_FPTrappedException
+   else if (((p00 = (( 21 :: int)::ii)))) then Exception_SError
+   else if (((p00 = (( 22 :: int)::ii)))) then Exception_Breakpoint
+   else if (((p00 = (( 23 :: int)::ii)))) then Exception_SoftwareStep
+   else if (((p00 = (( 24 :: int)::ii)))) then Exception_Watchpoint
+   else if (((p00 = (( 25 :: int)::ii)))) then Exception_SoftwareBreakpoint
+   else if (((p00 = (( 26 :: int)::ii)))) then Exception_VectorCatch
+   else if (((p00 = (( 27 :: int)::ii)))) then Exception_IRQ
    else Exception_FIQ))"
 
 
@@ -484,10 +523,10 @@ definition undefined_Exception  :: " unit \<Rightarrow>((register_value),(Except
 
 definition ArchVersion_of_num  :: " int \<Rightarrow> ArchVersion "  where 
      " ArchVersion_of_num arg0 = (
-   (let l__551 = arg0 in
-   if (((l__551 = (( 0 :: int)::ii)))) then ARMv8p0
-   else if (((l__551 = (( 1 :: int)::ii)))) then ARMv8p1
-   else if (((l__551 = (( 2 :: int)::ii)))) then ARMv8p2
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then ARMv8p0
+   else if (((p00 = (( 1 :: int)::ii)))) then ARMv8p1
+   else if (((p00 = (( 2 :: int)::ii)))) then ARMv8p2
    else ARMv8p3))"
 
 
@@ -510,51 +549,51 @@ definition undefined_ArchVersion  :: " unit \<Rightarrow>((register_value),(Arch
 
 definition Unpredictable_of_num  :: " int \<Rightarrow> Unpredictable "  where 
      " Unpredictable_of_num arg0 = (
-   (let l__507 = arg0 in
-   if (((l__507 = (( 0 :: int)::ii)))) then Unpredictable_WBOVERLAPLD
-   else if (((l__507 = (( 1 :: int)::ii)))) then Unpredictable_WBOVERLAPST
-   else if (((l__507 = (( 2 :: int)::ii)))) then Unpredictable_LDPOVERLAP
-   else if (((l__507 = (( 3 :: int)::ii)))) then Unpredictable_BASEOVERLAP
-   else if (((l__507 = (( 4 :: int)::ii)))) then Unpredictable_DATAOVERLAP
-   else if (((l__507 = (( 5 :: int)::ii)))) then Unpredictable_DEVPAGE2
-   else if (((l__507 = (( 6 :: int)::ii)))) then Unpredictable_INSTRDEVICE
-   else if (((l__507 = (( 7 :: int)::ii)))) then Unpredictable_RESCPACR
-   else if (((l__507 = (( 8 :: int)::ii)))) then Unpredictable_RESMAIR
-   else if (((l__507 = (( 9 :: int)::ii)))) then Unpredictable_RESTEXCB
-   else if (((l__507 = (( 10 :: int)::ii)))) then Unpredictable_RESPRRR
-   else if (((l__507 = (( 11 :: int)::ii)))) then Unpredictable_RESDACR
-   else if (((l__507 = (( 12 :: int)::ii)))) then Unpredictable_RESVTCRS
-   else if (((l__507 = (( 13 :: int)::ii)))) then Unpredictable_RESTnSZ
-   else if (((l__507 = (( 14 :: int)::ii)))) then Unpredictable_OORTnSZ
-   else if (((l__507 = (( 15 :: int)::ii)))) then Unpredictable_LARGEIPA
-   else if (((l__507 = (( 16 :: int)::ii)))) then Unpredictable_ESRCONDPASS
-   else if (((l__507 = (( 17 :: int)::ii)))) then Unpredictable_ILZEROIT
-   else if (((l__507 = (( 18 :: int)::ii)))) then Unpredictable_ILZEROT
-   else if (((l__507 = (( 19 :: int)::ii)))) then Unpredictable_BPVECTORCATCHPRI
-   else if (((l__507 = (( 20 :: int)::ii)))) then Unpredictable_VCMATCHHALF
-   else if (((l__507 = (( 21 :: int)::ii)))) then Unpredictable_VCMATCHDAPA
-   else if (((l__507 = (( 22 :: int)::ii)))) then Unpredictable_WPMASKANDBAS
-   else if (((l__507 = (( 23 :: int)::ii)))) then Unpredictable_WPBASCONTIGUOUS
-   else if (((l__507 = (( 24 :: int)::ii)))) then Unpredictable_RESWPMASK
-   else if (((l__507 = (( 25 :: int)::ii)))) then Unpredictable_WPMASKEDBITS
-   else if (((l__507 = (( 26 :: int)::ii)))) then Unpredictable_RESBPWPCTRL
-   else if (((l__507 = (( 27 :: int)::ii)))) then Unpredictable_BPNOTIMPL
-   else if (((l__507 = (( 28 :: int)::ii)))) then Unpredictable_RESBPTYPE
-   else if (((l__507 = (( 29 :: int)::ii)))) then Unpredictable_BPNOTCTXCMP
-   else if (((l__507 = (( 30 :: int)::ii)))) then Unpredictable_BPMATCHHALF
-   else if (((l__507 = (( 31 :: int)::ii)))) then Unpredictable_BPMISMATCHHALF
-   else if (((l__507 = (( 32 :: int)::ii)))) then Unpredictable_RESTARTALIGNPC
-   else if (((l__507 = (( 33 :: int)::ii)))) then Unpredictable_RESTARTZEROUPPERPC
-   else if (((l__507 = (( 34 :: int)::ii)))) then Unpredictable_ZEROUPPER
-   else if (((l__507 = (( 35 :: int)::ii)))) then Unpredictable_ERETZEROUPPERPC
-   else if (((l__507 = (( 36 :: int)::ii)))) then Unpredictable_A32FORCEALIGNPC
-   else if (((l__507 = (( 37 :: int)::ii)))) then Unpredictable_SMD
-   else if (((l__507 = (( 38 :: int)::ii)))) then Unpredictable_AFUPDATE
-   else if (((l__507 = (( 39 :: int)::ii)))) then Unpredictable_IESBinDebug
-   else if (((l__507 = (( 40 :: int)::ii)))) then Unpredictable_ZEROPMSEVFR
-   else if (((l__507 = (( 41 :: int)::ii)))) then Unpredictable_NOOPTYPES
-   else if (((l__507 = (( 42 :: int)::ii)))) then Unpredictable_ZEROMINLATENCY
-   else if (((l__507 = (( 43 :: int)::ii)))) then Unpredictable_CLEARERRITEZERO
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Unpredictable_WBOVERLAPLD
+   else if (((p00 = (( 1 :: int)::ii)))) then Unpredictable_WBOVERLAPST
+   else if (((p00 = (( 2 :: int)::ii)))) then Unpredictable_LDPOVERLAP
+   else if (((p00 = (( 3 :: int)::ii)))) then Unpredictable_BASEOVERLAP
+   else if (((p00 = (( 4 :: int)::ii)))) then Unpredictable_DATAOVERLAP
+   else if (((p00 = (( 5 :: int)::ii)))) then Unpredictable_DEVPAGE2
+   else if (((p00 = (( 6 :: int)::ii)))) then Unpredictable_INSTRDEVICE
+   else if (((p00 = (( 7 :: int)::ii)))) then Unpredictable_RESCPACR
+   else if (((p00 = (( 8 :: int)::ii)))) then Unpredictable_RESMAIR
+   else if (((p00 = (( 9 :: int)::ii)))) then Unpredictable_RESTEXCB
+   else if (((p00 = (( 10 :: int)::ii)))) then Unpredictable_RESPRRR
+   else if (((p00 = (( 11 :: int)::ii)))) then Unpredictable_RESDACR
+   else if (((p00 = (( 12 :: int)::ii)))) then Unpredictable_RESVTCRS
+   else if (((p00 = (( 13 :: int)::ii)))) then Unpredictable_RESTnSZ
+   else if (((p00 = (( 14 :: int)::ii)))) then Unpredictable_OORTnSZ
+   else if (((p00 = (( 15 :: int)::ii)))) then Unpredictable_LARGEIPA
+   else if (((p00 = (( 16 :: int)::ii)))) then Unpredictable_ESRCONDPASS
+   else if (((p00 = (( 17 :: int)::ii)))) then Unpredictable_ILZEROIT
+   else if (((p00 = (( 18 :: int)::ii)))) then Unpredictable_ILZEROT
+   else if (((p00 = (( 19 :: int)::ii)))) then Unpredictable_BPVECTORCATCHPRI
+   else if (((p00 = (( 20 :: int)::ii)))) then Unpredictable_VCMATCHHALF
+   else if (((p00 = (( 21 :: int)::ii)))) then Unpredictable_VCMATCHDAPA
+   else if (((p00 = (( 22 :: int)::ii)))) then Unpredictable_WPMASKANDBAS
+   else if (((p00 = (( 23 :: int)::ii)))) then Unpredictable_WPBASCONTIGUOUS
+   else if (((p00 = (( 24 :: int)::ii)))) then Unpredictable_RESWPMASK
+   else if (((p00 = (( 25 :: int)::ii)))) then Unpredictable_WPMASKEDBITS
+   else if (((p00 = (( 26 :: int)::ii)))) then Unpredictable_RESBPWPCTRL
+   else if (((p00 = (( 27 :: int)::ii)))) then Unpredictable_BPNOTIMPL
+   else if (((p00 = (( 28 :: int)::ii)))) then Unpredictable_RESBPTYPE
+   else if (((p00 = (( 29 :: int)::ii)))) then Unpredictable_BPNOTCTXCMP
+   else if (((p00 = (( 30 :: int)::ii)))) then Unpredictable_BPMATCHHALF
+   else if (((p00 = (( 31 :: int)::ii)))) then Unpredictable_BPMISMATCHHALF
+   else if (((p00 = (( 32 :: int)::ii)))) then Unpredictable_RESTARTALIGNPC
+   else if (((p00 = (( 33 :: int)::ii)))) then Unpredictable_RESTARTZEROUPPERPC
+   else if (((p00 = (( 34 :: int)::ii)))) then Unpredictable_ZEROUPPER
+   else if (((p00 = (( 35 :: int)::ii)))) then Unpredictable_ERETZEROUPPERPC
+   else if (((p00 = (( 36 :: int)::ii)))) then Unpredictable_A32FORCEALIGNPC
+   else if (((p00 = (( 37 :: int)::ii)))) then Unpredictable_SMD
+   else if (((p00 = (( 38 :: int)::ii)))) then Unpredictable_AFUPDATE
+   else if (((p00 = (( 39 :: int)::ii)))) then Unpredictable_IESBinDebug
+   else if (((p00 = (( 40 :: int)::ii)))) then Unpredictable_ZEROPMSEVFR
+   else if (((p00 = (( 41 :: int)::ii)))) then Unpredictable_NOOPTYPES
+   else if (((p00 = (( 42 :: int)::ii)))) then Unpredictable_ZEROMINLATENCY
+   else if (((p00 = (( 43 :: int)::ii)))) then Unpredictable_CLEARERRITEZERO
    else Unpredictable_TBD))"
 
 
@@ -620,21 +659,21 @@ definition undefined_Unpredictable  :: " unit \<Rightarrow>((register_value),(Un
 
 definition Constraint_of_num  :: " int \<Rightarrow> Constraint "  where 
      " Constraint_of_num arg0 = (
-   (let l__493 = arg0 in
-   if (((l__493 = (( 0 :: int)::ii)))) then Constraint_NONE
-   else if (((l__493 = (( 1 :: int)::ii)))) then Constraint_UNKNOWN
-   else if (((l__493 = (( 2 :: int)::ii)))) then Constraint_UNDEF
-   else if (((l__493 = (( 3 :: int)::ii)))) then Constraint_UNDEFEL0
-   else if (((l__493 = (( 4 :: int)::ii)))) then Constraint_NOP
-   else if (((l__493 = (( 5 :: int)::ii)))) then Constraint_TRUE
-   else if (((l__493 = (( 6 :: int)::ii)))) then Constraint_FALSE
-   else if (((l__493 = (( 7 :: int)::ii)))) then Constraint_DISABLED
-   else if (((l__493 = (( 8 :: int)::ii)))) then Constraint_UNCOND
-   else if (((l__493 = (( 9 :: int)::ii)))) then Constraint_COND
-   else if (((l__493 = (( 10 :: int)::ii)))) then Constraint_ADDITIONAL_DECODE
-   else if (((l__493 = (( 11 :: int)::ii)))) then Constraint_WBSUPPRESS
-   else if (((l__493 = (( 12 :: int)::ii)))) then Constraint_FAULT
-   else if (((l__493 = (( 13 :: int)::ii)))) then Constraint_FORCE
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Constraint_NONE
+   else if (((p00 = (( 1 :: int)::ii)))) then Constraint_UNKNOWN
+   else if (((p00 = (( 2 :: int)::ii)))) then Constraint_UNDEF
+   else if (((p00 = (( 3 :: int)::ii)))) then Constraint_UNDEFEL0
+   else if (((p00 = (( 4 :: int)::ii)))) then Constraint_NOP
+   else if (((p00 = (( 5 :: int)::ii)))) then Constraint_TRUE
+   else if (((p00 = (( 6 :: int)::ii)))) then Constraint_FALSE
+   else if (((p00 = (( 7 :: int)::ii)))) then Constraint_DISABLED
+   else if (((p00 = (( 8 :: int)::ii)))) then Constraint_UNCOND
+   else if (((p00 = (( 9 :: int)::ii)))) then Constraint_COND
+   else if (((p00 = (( 10 :: int)::ii)))) then Constraint_ADDITIONAL_DECODE
+   else if (((p00 = (( 11 :: int)::ii)))) then Constraint_WBSUPPRESS
+   else if (((p00 = (( 12 :: int)::ii)))) then Constraint_FAULT
+   else if (((p00 = (( 13 :: int)::ii)))) then Constraint_FORCE
    else Constraint_FORCENOSLCHECK))"
 
 
@@ -670,9 +709,9 @@ definition undefined_Constraint  :: " unit \<Rightarrow>((register_value),(Const
 
 definition InstrSet_of_num  :: " int \<Rightarrow> InstrSet "  where 
      " InstrSet_of_num arg0 = (
-   (let l__491 = arg0 in
-   if (((l__491 = (( 0 :: int)::ii)))) then InstrSet_A64
-   else if (((l__491 = (( 1 :: int)::ii)))) then InstrSet_A32
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then InstrSet_A64
+   else if (((p00 = (( 1 :: int)::ii)))) then InstrSet_A32
    else InstrSet_T32))"
 
 
@@ -744,13 +783,13 @@ definition undefined_ProcState  :: " unit \<Rightarrow>((register_value),(ProcSt
 
 definition BranchType_of_num  :: " int \<Rightarrow> BranchType "  where 
      " BranchType_of_num arg0 = (
-   (let l__485 = arg0 in
-   if (((l__485 = (( 0 :: int)::ii)))) then BranchType_CALL
-   else if (((l__485 = (( 1 :: int)::ii)))) then BranchType_ERET
-   else if (((l__485 = (( 2 :: int)::ii)))) then BranchType_DBGEXIT
-   else if (((l__485 = (( 3 :: int)::ii)))) then BranchType_RET
-   else if (((l__485 = (( 4 :: int)::ii)))) then BranchType_JMP
-   else if (((l__485 = (( 5 :: int)::ii)))) then BranchType_EXCEPTION
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then BranchType_CALL
+   else if (((p00 = (( 1 :: int)::ii)))) then BranchType_ERET
+   else if (((p00 = (( 2 :: int)::ii)))) then BranchType_DBGEXIT
+   else if (((p00 = (( 3 :: int)::ii)))) then BranchType_RET
+   else if (((p00 = (( 4 :: int)::ii)))) then BranchType_JMP
+   else if (((p00 = (( 5 :: int)::ii)))) then BranchType_EXCEPTION
    else BranchType_UNKNOWN))"
 
 
@@ -794,25 +833,25 @@ definition undefined_ExceptionRecord  :: " unit \<Rightarrow>((register_value),(
 
 definition Fault_of_num  :: " int \<Rightarrow> Fault "  where 
      " Fault_of_num arg0 = (
-   (let l__467 = arg0 in
-   if (((l__467 = (( 0 :: int)::ii)))) then Fault_None
-   else if (((l__467 = (( 1 :: int)::ii)))) then Fault_AccessFlag
-   else if (((l__467 = (( 2 :: int)::ii)))) then Fault_Alignment
-   else if (((l__467 = (( 3 :: int)::ii)))) then Fault_Background
-   else if (((l__467 = (( 4 :: int)::ii)))) then Fault_Domain
-   else if (((l__467 = (( 5 :: int)::ii)))) then Fault_Permission
-   else if (((l__467 = (( 6 :: int)::ii)))) then Fault_Translation
-   else if (((l__467 = (( 7 :: int)::ii)))) then Fault_AddressSize
-   else if (((l__467 = (( 8 :: int)::ii)))) then Fault_SyncExternal
-   else if (((l__467 = (( 9 :: int)::ii)))) then Fault_SyncExternalOnWalk
-   else if (((l__467 = (( 10 :: int)::ii)))) then Fault_SyncParity
-   else if (((l__467 = (( 11 :: int)::ii)))) then Fault_SyncParityOnWalk
-   else if (((l__467 = (( 12 :: int)::ii)))) then Fault_AsyncParity
-   else if (((l__467 = (( 13 :: int)::ii)))) then Fault_AsyncExternal
-   else if (((l__467 = (( 14 :: int)::ii)))) then Fault_Debug
-   else if (((l__467 = (( 15 :: int)::ii)))) then Fault_TLBConflict
-   else if (((l__467 = (( 16 :: int)::ii)))) then Fault_Lockdown
-   else if (((l__467 = (( 17 :: int)::ii)))) then Fault_Exclusive
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Fault_None
+   else if (((p00 = (( 1 :: int)::ii)))) then Fault_AccessFlag
+   else if (((p00 = (( 2 :: int)::ii)))) then Fault_Alignment
+   else if (((p00 = (( 3 :: int)::ii)))) then Fault_Background
+   else if (((p00 = (( 4 :: int)::ii)))) then Fault_Domain
+   else if (((p00 = (( 5 :: int)::ii)))) then Fault_Permission
+   else if (((p00 = (( 6 :: int)::ii)))) then Fault_Translation
+   else if (((p00 = (( 7 :: int)::ii)))) then Fault_AddressSize
+   else if (((p00 = (( 8 :: int)::ii)))) then Fault_SyncExternal
+   else if (((p00 = (( 9 :: int)::ii)))) then Fault_SyncExternalOnWalk
+   else if (((p00 = (( 10 :: int)::ii)))) then Fault_SyncParity
+   else if (((p00 = (( 11 :: int)::ii)))) then Fault_SyncParityOnWalk
+   else if (((p00 = (( 12 :: int)::ii)))) then Fault_AsyncParity
+   else if (((p00 = (( 13 :: int)::ii)))) then Fault_AsyncExternal
+   else if (((p00 = (( 14 :: int)::ii)))) then Fault_Debug
+   else if (((p00 = (( 15 :: int)::ii)))) then Fault_TLBConflict
+   else if (((p00 = (( 16 :: int)::ii)))) then Fault_Lockdown
+   else if (((p00 = (( 17 :: int)::ii)))) then Fault_Exclusive
    else Fault_ICacheMaint))"
 
 
@@ -852,22 +891,22 @@ definition undefined_Fault  :: " unit \<Rightarrow>((register_value),(Fault),(ex
 
 definition AccType_of_num  :: " int \<Rightarrow> AccType "  where 
      " AccType_of_num arg0 = (
-   (let l__452 = arg0 in
-   if (((l__452 = (( 0 :: int)::ii)))) then AccType_NORMAL
-   else if (((l__452 = (( 1 :: int)::ii)))) then AccType_VEC
-   else if (((l__452 = (( 2 :: int)::ii)))) then AccType_STREAM
-   else if (((l__452 = (( 3 :: int)::ii)))) then AccType_VECSTREAM
-   else if (((l__452 = (( 4 :: int)::ii)))) then AccType_ATOMIC
-   else if (((l__452 = (( 5 :: int)::ii)))) then AccType_ATOMICRW
-   else if (((l__452 = (( 6 :: int)::ii)))) then AccType_ORDERED
-   else if (((l__452 = (( 7 :: int)::ii)))) then AccType_ORDEREDRW
-   else if (((l__452 = (( 8 :: int)::ii)))) then AccType_LIMITEDORDERED
-   else if (((l__452 = (( 9 :: int)::ii)))) then AccType_UNPRIV
-   else if (((l__452 = (( 10 :: int)::ii)))) then AccType_IFETCH
-   else if (((l__452 = (( 11 :: int)::ii)))) then AccType_PTW
-   else if (((l__452 = (( 12 :: int)::ii)))) then AccType_DC
-   else if (((l__452 = (( 13 :: int)::ii)))) then AccType_IC
-   else if (((l__452 = (( 14 :: int)::ii)))) then AccType_DCZVA
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then AccType_NORMAL
+   else if (((p00 = (( 1 :: int)::ii)))) then AccType_VEC
+   else if (((p00 = (( 2 :: int)::ii)))) then AccType_STREAM
+   else if (((p00 = (( 3 :: int)::ii)))) then AccType_VECSTREAM
+   else if (((p00 = (( 4 :: int)::ii)))) then AccType_ATOMIC
+   else if (((p00 = (( 5 :: int)::ii)))) then AccType_ATOMICRW
+   else if (((p00 = (( 6 :: int)::ii)))) then AccType_ORDERED
+   else if (((p00 = (( 7 :: int)::ii)))) then AccType_ORDEREDRW
+   else if (((p00 = (( 8 :: int)::ii)))) then AccType_LIMITEDORDERED
+   else if (((p00 = (( 9 :: int)::ii)))) then AccType_UNPRIV
+   else if (((p00 = (( 10 :: int)::ii)))) then AccType_IFETCH
+   else if (((p00 = (( 11 :: int)::ii)))) then AccType_PTW
+   else if (((p00 = (( 12 :: int)::ii)))) then AccType_DC
+   else if (((p00 = (( 13 :: int)::ii)))) then AccType_IC
+   else if (((p00 = (( 14 :: int)::ii)))) then AccType_DCZVA
    else AccType_AT))"
 
 
@@ -932,10 +971,10 @@ definition undefined_FaultRecord  :: " unit \<Rightarrow>((register_value),(Faul
 
 definition MBReqDomain_of_num  :: " int \<Rightarrow> MBReqDomain "  where 
      " MBReqDomain_of_num arg0 = (
-   (let l__449 = arg0 in
-   if (((l__449 = (( 0 :: int)::ii)))) then MBReqDomain_Nonshareable
-   else if (((l__449 = (( 1 :: int)::ii)))) then MBReqDomain_InnerShareable
-   else if (((l__449 = (( 2 :: int)::ii)))) then MBReqDomain_OuterShareable
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MBReqDomain_Nonshareable
+   else if (((p00 = (( 1 :: int)::ii)))) then MBReqDomain_InnerShareable
+   else if (((p00 = (( 2 :: int)::ii)))) then MBReqDomain_OuterShareable
    else MBReqDomain_FullSystem))"
 
 
@@ -960,9 +999,9 @@ definition undefined_MBReqDomain  :: " unit \<Rightarrow>((register_value),(MBRe
 
 definition MBReqTypes_of_num  :: " int \<Rightarrow> MBReqTypes "  where 
      " MBReqTypes_of_num arg0 = (
-   (let l__447 = arg0 in
-   if (((l__447 = (( 0 :: int)::ii)))) then MBReqTypes_Reads
-   else if (((l__447 = (( 1 :: int)::ii)))) then MBReqTypes_Writes
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MBReqTypes_Reads
+   else if (((p00 = (( 1 :: int)::ii)))) then MBReqTypes_Writes
    else MBReqTypes_All))"
 
 
@@ -984,8 +1023,8 @@ definition undefined_MBReqTypes  :: " unit \<Rightarrow>((register_value),(MBReq
 
 definition MemType_of_num  :: " int \<Rightarrow> MemType "  where 
      " MemType_of_num arg0 = (
-   (let l__446 = arg0 in
-   if (((l__446 = (( 0 :: int)::ii)))) then MemType_Normal
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MemType_Normal
    else MemType_Device))"
 
 
@@ -1006,10 +1045,10 @@ definition undefined_MemType  :: " unit \<Rightarrow>((register_value),(MemType)
 
 definition DeviceType_of_num  :: " int \<Rightarrow> DeviceType "  where 
      " DeviceType_of_num arg0 = (
-   (let l__443 = arg0 in
-   if (((l__443 = (( 0 :: int)::ii)))) then DeviceType_GRE
-   else if (((l__443 = (( 1 :: int)::ii)))) then DeviceType_nGRE
-   else if (((l__443 = (( 2 :: int)::ii)))) then DeviceType_nGnRE
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then DeviceType_GRE
+   else if (((p00 = (( 1 :: int)::ii)))) then DeviceType_nGRE
+   else if (((p00 = (( 2 :: int)::ii)))) then DeviceType_nGnRE
    else DeviceType_nGnRnE))"
 
 
@@ -1099,15 +1138,15 @@ definition undefined_DescriptorUpdate  :: " unit \<Rightarrow>((register_value),
 
 definition MemAtomicOp_of_num  :: " int \<Rightarrow> MemAtomicOp "  where 
      " MemAtomicOp_of_num arg0 = (
-   (let l__435 = arg0 in
-   if (((l__435 = (( 0 :: int)::ii)))) then MemAtomicOp_ADD
-   else if (((l__435 = (( 1 :: int)::ii)))) then MemAtomicOp_BIC
-   else if (((l__435 = (( 2 :: int)::ii)))) then MemAtomicOp_EOR
-   else if (((l__435 = (( 3 :: int)::ii)))) then MemAtomicOp_ORR
-   else if (((l__435 = (( 4 :: int)::ii)))) then MemAtomicOp_SMAX
-   else if (((l__435 = (( 5 :: int)::ii)))) then MemAtomicOp_SMIN
-   else if (((l__435 = (( 6 :: int)::ii)))) then MemAtomicOp_UMAX
-   else if (((l__435 = (( 7 :: int)::ii)))) then MemAtomicOp_UMIN
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MemAtomicOp_ADD
+   else if (((p00 = (( 1 :: int)::ii)))) then MemAtomicOp_BIC
+   else if (((p00 = (( 2 :: int)::ii)))) then MemAtomicOp_EOR
+   else if (((p00 = (( 3 :: int)::ii)))) then MemAtomicOp_ORR
+   else if (((p00 = (( 4 :: int)::ii)))) then MemAtomicOp_SMAX
+   else if (((p00 = (( 5 :: int)::ii)))) then MemAtomicOp_SMIN
+   else if (((p00 = (( 6 :: int)::ii)))) then MemAtomicOp_UMAX
+   else if (((p00 = (( 7 :: int)::ii)))) then MemAtomicOp_UMIN
    else MemAtomicOp_SWP))"
 
 
@@ -1137,11 +1176,11 @@ definition undefined_MemAtomicOp  :: " unit \<Rightarrow>((register_value),(MemA
 
 definition FPType_of_num  :: " int \<Rightarrow> FPType "  where 
      " FPType_of_num arg0 = (
-   (let l__431 = arg0 in
-   if (((l__431 = (( 0 :: int)::ii)))) then FPType_Nonzero
-   else if (((l__431 = (( 1 :: int)::ii)))) then FPType_Zero
-   else if (((l__431 = (( 2 :: int)::ii)))) then FPType_Infinity
-   else if (((l__431 = (( 3 :: int)::ii)))) then FPType_QNaN
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FPType_Nonzero
+   else if (((p00 = (( 1 :: int)::ii)))) then FPType_Zero
+   else if (((p00 = (( 2 :: int)::ii)))) then FPType_Infinity
+   else if (((p00 = (( 3 :: int)::ii)))) then FPType_QNaN
    else FPType_SNaN))"
 
 
@@ -1166,12 +1205,12 @@ definition undefined_FPType  :: " unit \<Rightarrow>((register_value),(FPType),(
 
 definition FPExc_of_num  :: " int \<Rightarrow> FPExc "  where 
      " FPExc_of_num arg0 = (
-   (let l__426 = arg0 in
-   if (((l__426 = (( 0 :: int)::ii)))) then FPExc_InvalidOp
-   else if (((l__426 = (( 1 :: int)::ii)))) then FPExc_DivideByZero
-   else if (((l__426 = (( 2 :: int)::ii)))) then FPExc_Overflow
-   else if (((l__426 = (( 3 :: int)::ii)))) then FPExc_Underflow
-   else if (((l__426 = (( 4 :: int)::ii)))) then FPExc_Inexact
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FPExc_InvalidOp
+   else if (((p00 = (( 1 :: int)::ii)))) then FPExc_DivideByZero
+   else if (((p00 = (( 2 :: int)::ii)))) then FPExc_Overflow
+   else if (((p00 = (( 3 :: int)::ii)))) then FPExc_Underflow
+   else if (((p00 = (( 4 :: int)::ii)))) then FPExc_Inexact
    else FPExc_InputDenorm))"
 
 
@@ -1198,12 +1237,12 @@ definition undefined_FPExc  :: " unit \<Rightarrow>((register_value),(FPExc),(ex
 
 definition FPRounding_of_num  :: " int \<Rightarrow> FPRounding "  where 
      " FPRounding_of_num arg0 = (
-   (let l__421 = arg0 in
-   if (((l__421 = (( 0 :: int)::ii)))) then FPRounding_TIEEVEN
-   else if (((l__421 = (( 1 :: int)::ii)))) then FPRounding_POSINF
-   else if (((l__421 = (( 2 :: int)::ii)))) then FPRounding_NEGINF
-   else if (((l__421 = (( 3 :: int)::ii)))) then FPRounding_ZERO
-   else if (((l__421 = (( 4 :: int)::ii)))) then FPRounding_TIEAWAY
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FPRounding_TIEEVEN
+   else if (((p00 = (( 1 :: int)::ii)))) then FPRounding_POSINF
+   else if (((p00 = (( 2 :: int)::ii)))) then FPRounding_NEGINF
+   else if (((p00 = (( 3 :: int)::ii)))) then FPRounding_ZERO
+   else if (((p00 = (( 4 :: int)::ii)))) then FPRounding_TIEAWAY
    else FPRounding_ODD))"
 
 
@@ -1230,11 +1269,11 @@ definition undefined_FPRounding  :: " unit \<Rightarrow>((register_value),(FPRou
 
 definition SysRegAccess_of_num  :: " int \<Rightarrow> SysRegAccess "  where 
      " SysRegAccess_of_num arg0 = (
-   (let l__417 = arg0 in
-   if (((l__417 = (( 0 :: int)::ii)))) then SysRegAccess_OK
-   else if (((l__417 = (( 1 :: int)::ii)))) then SysRegAccess_UNDEFINED
-   else if (((l__417 = (( 2 :: int)::ii)))) then SysRegAccess_TrapToEL1
-   else if (((l__417 = (( 3 :: int)::ii)))) then SysRegAccess_TrapToEL2
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then SysRegAccess_OK
+   else if (((p00 = (( 1 :: int)::ii)))) then SysRegAccess_UNDEFINED
+   else if (((p00 = (( 2 :: int)::ii)))) then SysRegAccess_TrapToEL1
+   else if (((p00 = (( 3 :: int)::ii)))) then SysRegAccess_TrapToEL2
    else SysRegAccess_TrapToEL3))"
 
 
@@ -1260,11 +1299,11 @@ definition undefined_SysRegAccess  :: " unit \<Rightarrow>((register_value),(Sys
 
 definition SRType_of_num  :: " int \<Rightarrow> SRType "  where 
      " SRType_of_num arg0 = (
-   (let l__413 = arg0 in
-   if (((l__413 = (( 0 :: int)::ii)))) then SRType_LSL
-   else if (((l__413 = (( 1 :: int)::ii)))) then SRType_LSR
-   else if (((l__413 = (( 2 :: int)::ii)))) then SRType_ASR
-   else if (((l__413 = (( 3 :: int)::ii)))) then SRType_ROR
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then SRType_LSL
+   else if (((p00 = (( 1 :: int)::ii)))) then SRType_LSR
+   else if (((p00 = (( 2 :: int)::ii)))) then SRType_ASR
+   else if (((p00 = (( 3 :: int)::ii)))) then SRType_ROR
    else SRType_RRX))"
 
 
@@ -1288,10 +1327,10 @@ definition undefined_SRType  :: " unit \<Rightarrow>((register_value),(SRType),(
 
 definition ShiftType_of_num  :: " int \<Rightarrow> ShiftType "  where 
      " ShiftType_of_num arg0 = (
-   (let l__410 = arg0 in
-   if (((l__410 = (( 0 :: int)::ii)))) then ShiftType_LSL
-   else if (((l__410 = (( 1 :: int)::ii)))) then ShiftType_LSR
-   else if (((l__410 = (( 2 :: int)::ii)))) then ShiftType_ASR
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then ShiftType_LSL
+   else if (((p00 = (( 1 :: int)::ii)))) then ShiftType_LSR
+   else if (((p00 = (( 2 :: int)::ii)))) then ShiftType_ASR
    else ShiftType_ROR))"
 
 
@@ -1314,9 +1353,9 @@ definition undefined_ShiftType  :: " unit \<Rightarrow>((register_value),(ShiftT
 
 definition PrefetchHint_of_num  :: " int \<Rightarrow> PrefetchHint "  where 
      " PrefetchHint_of_num arg0 = (
-   (let l__408 = arg0 in
-   if (((l__408 = (( 0 :: int)::ii)))) then Prefetch_READ
-   else if (((l__408 = (( 1 :: int)::ii)))) then Prefetch_WRITE
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Prefetch_READ
+   else if (((p00 = (( 1 :: int)::ii)))) then Prefetch_WRITE
    else Prefetch_EXEC))"
 
 
@@ -1338,11 +1377,11 @@ definition undefined_PrefetchHint  :: " unit \<Rightarrow>((register_value),(Pre
 
 definition InterruptID_of_num  :: " int \<Rightarrow> InterruptID "  where 
      " InterruptID_of_num arg0 = (
-   (let l__404 = arg0 in
-   if (((l__404 = (( 0 :: int)::ii)))) then InterruptID_PMUIRQ
-   else if (((l__404 = (( 1 :: int)::ii)))) then InterruptID_COMMIRQ
-   else if (((l__404 = (( 2 :: int)::ii)))) then InterruptID_CTIIRQ
-   else if (((l__404 = (( 3 :: int)::ii)))) then InterruptID_COMMRX
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then InterruptID_PMUIRQ
+   else if (((p00 = (( 1 :: int)::ii)))) then InterruptID_COMMIRQ
+   else if (((p00 = (( 2 :: int)::ii)))) then InterruptID_CTIIRQ
+   else if (((p00 = (( 3 :: int)::ii)))) then InterruptID_COMMRX
    else InterruptID_COMMTX))"
 
 
@@ -1368,14 +1407,14 @@ definition undefined_InterruptID  :: " unit \<Rightarrow>((register_value),(Inte
 
 definition CrossTriggerOut_of_num  :: " int \<Rightarrow> CrossTriggerOut "  where 
      " CrossTriggerOut_of_num arg0 = (
-   (let l__397 = arg0 in
-   if (((l__397 = (( 0 :: int)::ii)))) then CrossTriggerOut_DebugRequest
-   else if (((l__397 = (( 1 :: int)::ii)))) then CrossTriggerOut_RestartRequest
-   else if (((l__397 = (( 2 :: int)::ii)))) then CrossTriggerOut_IRQ
-   else if (((l__397 = (( 3 :: int)::ii)))) then CrossTriggerOut_RSVD3
-   else if (((l__397 = (( 4 :: int)::ii)))) then CrossTriggerOut_TraceExtIn0
-   else if (((l__397 = (( 5 :: int)::ii)))) then CrossTriggerOut_TraceExtIn1
-   else if (((l__397 = (( 6 :: int)::ii)))) then CrossTriggerOut_TraceExtIn2
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CrossTriggerOut_DebugRequest
+   else if (((p00 = (( 1 :: int)::ii)))) then CrossTriggerOut_RestartRequest
+   else if (((p00 = (( 2 :: int)::ii)))) then CrossTriggerOut_IRQ
+   else if (((p00 = (( 3 :: int)::ii)))) then CrossTriggerOut_RSVD3
+   else if (((p00 = (( 4 :: int)::ii)))) then CrossTriggerOut_TraceExtIn0
+   else if (((p00 = (( 5 :: int)::ii)))) then CrossTriggerOut_TraceExtIn1
+   else if (((p00 = (( 6 :: int)::ii)))) then CrossTriggerOut_TraceExtIn2
    else CrossTriggerOut_TraceExtIn3))"
 
 
@@ -1404,14 +1443,14 @@ definition undefined_CrossTriggerOut  :: " unit \<Rightarrow>((register_value),(
 
 definition CrossTriggerIn_of_num  :: " int \<Rightarrow> CrossTriggerIn "  where 
      " CrossTriggerIn_of_num arg0 = (
-   (let l__390 = arg0 in
-   if (((l__390 = (( 0 :: int)::ii)))) then CrossTriggerIn_CrossHalt
-   else if (((l__390 = (( 1 :: int)::ii)))) then CrossTriggerIn_PMUOverflow
-   else if (((l__390 = (( 2 :: int)::ii)))) then CrossTriggerIn_RSVD2
-   else if (((l__390 = (( 3 :: int)::ii)))) then CrossTriggerIn_RSVD3
-   else if (((l__390 = (( 4 :: int)::ii)))) then CrossTriggerIn_TraceExtOut0
-   else if (((l__390 = (( 5 :: int)::ii)))) then CrossTriggerIn_TraceExtOut1
-   else if (((l__390 = (( 6 :: int)::ii)))) then CrossTriggerIn_TraceExtOut2
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CrossTriggerIn_CrossHalt
+   else if (((p00 = (( 1 :: int)::ii)))) then CrossTriggerIn_PMUOverflow
+   else if (((p00 = (( 2 :: int)::ii)))) then CrossTriggerIn_RSVD2
+   else if (((p00 = (( 3 :: int)::ii)))) then CrossTriggerIn_RSVD3
+   else if (((p00 = (( 4 :: int)::ii)))) then CrossTriggerIn_TraceExtOut0
+   else if (((p00 = (( 5 :: int)::ii)))) then CrossTriggerIn_TraceExtOut1
+   else if (((p00 = (( 6 :: int)::ii)))) then CrossTriggerIn_TraceExtOut2
    else CrossTriggerIn_TraceExtOut3))"
 
 
@@ -1440,9 +1479,9 @@ definition undefined_CrossTriggerIn  :: " unit \<Rightarrow>((register_value),(C
 
 definition MemBarrierOp_of_num  :: " int \<Rightarrow> MemBarrierOp "  where 
      " MemBarrierOp_of_num arg0 = (
-   (let l__388 = arg0 in
-   if (((l__388 = (( 0 :: int)::ii)))) then MemBarrierOp_DSB
-   else if (((l__388 = (( 1 :: int)::ii)))) then MemBarrierOp_DMB
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MemBarrierOp_DSB
+   else if (((p00 = (( 1 :: int)::ii)))) then MemBarrierOp_DMB
    else MemBarrierOp_ISB))"
 
 
@@ -1518,10 +1557,10 @@ definition undefined_TLBRecord  :: " unit \<Rightarrow>((register_value),(TLBRec
 
 definition ImmediateOp_of_num  :: " int \<Rightarrow> ImmediateOp "  where 
      " ImmediateOp_of_num arg0 = (
-   (let l__385 = arg0 in
-   if (((l__385 = (( 0 :: int)::ii)))) then ImmediateOp_MOVI
-   else if (((l__385 = (( 1 :: int)::ii)))) then ImmediateOp_MVNI
-   else if (((l__385 = (( 2 :: int)::ii)))) then ImmediateOp_ORR
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then ImmediateOp_MOVI
+   else if (((p00 = (( 1 :: int)::ii)))) then ImmediateOp_MVNI
+   else if (((p00 = (( 2 :: int)::ii)))) then ImmediateOp_ORR
    else ImmediateOp_BIC))"
 
 
@@ -1545,9 +1584,9 @@ definition undefined_ImmediateOp  :: " unit \<Rightarrow>((register_value),(Imme
 
 definition MoveWideOp_of_num  :: " int \<Rightarrow> MoveWideOp "  where 
      " MoveWideOp_of_num arg0 = (
-   (let l__383 = arg0 in
-   if (((l__383 = (( 0 :: int)::ii)))) then MoveWideOp_N
-   else if (((l__383 = (( 1 :: int)::ii)))) then MoveWideOp_Z
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MoveWideOp_N
+   else if (((p00 = (( 1 :: int)::ii)))) then MoveWideOp_Z
    else MoveWideOp_K))"
 
 
@@ -1569,9 +1608,9 @@ definition undefined_MoveWideOp  :: " unit \<Rightarrow>((register_value),(MoveW
 
 definition SystemAccessType_of_num  :: " int \<Rightarrow> SystemAccessType "  where 
      " SystemAccessType_of_num arg0 = (
-   (let l__381 = arg0 in
-   if (((l__381 = (( 0 :: int)::ii)))) then SystemAccessType_RT
-   else if (((l__381 = (( 1 :: int)::ii)))) then SystemAccessType_RRT
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then SystemAccessType_RT
+   else if (((p00 = (( 1 :: int)::ii)))) then SystemAccessType_RRT
    else SystemAccessType_DT))"
 
 
@@ -1594,10 +1633,10 @@ definition undefined_SystemAccessType  :: " unit \<Rightarrow>((register_value),
 
 definition VBitOp_of_num  :: " int \<Rightarrow> VBitOp "  where 
      " VBitOp_of_num arg0 = (
-   (let l__378 = arg0 in
-   if (((l__378 = (( 0 :: int)::ii)))) then VBitOp_VBIF
-   else if (((l__378 = (( 1 :: int)::ii)))) then VBitOp_VBIT
-   else if (((l__378 = (( 2 :: int)::ii)))) then VBitOp_VBSL
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then VBitOp_VBIF
+   else if (((p00 = (( 1 :: int)::ii)))) then VBitOp_VBIT
+   else if (((p00 = (( 2 :: int)::ii)))) then VBitOp_VBSL
    else VBitOp_VEOR))"
 
 
@@ -1620,9 +1659,9 @@ definition undefined_VBitOp  :: " unit \<Rightarrow>((register_value),(VBitOp),(
 
 definition TimeStamp_of_num  :: " int \<Rightarrow> TimeStamp "  where 
      " TimeStamp_of_num arg0 = (
-   (let l__376 = arg0 in
-   if (((l__376 = (( 0 :: int)::ii)))) then TimeStamp_None
-   else if (((l__376 = (( 1 :: int)::ii)))) then TimeStamp_Virtual
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then TimeStamp_None
+   else if (((p00 = (( 1 :: int)::ii)))) then TimeStamp_Virtual
    else TimeStamp_Physical))"
 
 
@@ -1644,10 +1683,10 @@ definition undefined_TimeStamp  :: " unit \<Rightarrow>((register_value),(TimeSt
 
 definition PrivilegeLevel_of_num  :: " int \<Rightarrow> PrivilegeLevel "  where 
      " PrivilegeLevel_of_num arg0 = (
-   (let l__373 = arg0 in
-   if (((l__373 = (( 0 :: int)::ii)))) then PL3
-   else if (((l__373 = (( 1 :: int)::ii)))) then PL2
-   else if (((l__373 = (( 2 :: int)::ii)))) then PL1
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then PL3
+   else if (((p00 = (( 1 :: int)::ii)))) then PL2
+   else if (((p00 = (( 2 :: int)::ii)))) then PL1
    else PL0))"
 
 
@@ -1680,11 +1719,11 @@ definition undefined_AArch32_SErrorSyndrome  :: " unit \<Rightarrow>((register_v
 
 definition SystemOp_of_num  :: " int \<Rightarrow> SystemOp "  where 
      " SystemOp_of_num arg0 = (
-   (let l__369 = arg0 in
-   if (((l__369 = (( 0 :: int)::ii)))) then Sys_AT
-   else if (((l__369 = (( 1 :: int)::ii)))) then Sys_DC
-   else if (((l__369 = (( 2 :: int)::ii)))) then Sys_IC
-   else if (((l__369 = (( 3 :: int)::ii)))) then Sys_TLBI
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Sys_AT
+   else if (((p00 = (( 1 :: int)::ii)))) then Sys_DC
+   else if (((p00 = (( 2 :: int)::ii)))) then Sys_IC
+   else if (((p00 = (( 3 :: int)::ii)))) then Sys_TLBI
    else Sys_SYS))"
 
 
@@ -1730,12 +1769,12 @@ definition undefined_PCSample  :: " unit \<Rightarrow>((register_value),(PCSampl
 
 definition ReduceOp_of_num  :: " int \<Rightarrow> ReduceOp "  where 
      " ReduceOp_of_num arg0 = (
-   (let l__364 = arg0 in
-   if (((l__364 = (( 0 :: int)::ii)))) then ReduceOp_FMINNUM
-   else if (((l__364 = (( 1 :: int)::ii)))) then ReduceOp_FMAXNUM
-   else if (((l__364 = (( 2 :: int)::ii)))) then ReduceOp_FMIN
-   else if (((l__364 = (( 3 :: int)::ii)))) then ReduceOp_FMAX
-   else if (((l__364 = (( 4 :: int)::ii)))) then ReduceOp_FADD
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then ReduceOp_FMINNUM
+   else if (((p00 = (( 1 :: int)::ii)))) then ReduceOp_FMAXNUM
+   else if (((p00 = (( 2 :: int)::ii)))) then ReduceOp_FMIN
+   else if (((p00 = (( 3 :: int)::ii)))) then ReduceOp_FMAX
+   else if (((p00 = (( 4 :: int)::ii)))) then ReduceOp_FADD
    else ReduceOp_ADD))"
 
 
@@ -1762,9 +1801,9 @@ definition undefined_ReduceOp  :: " unit \<Rightarrow>((register_value),(ReduceO
 
 definition LogicalOp_of_num  :: " int \<Rightarrow> LogicalOp "  where 
      " LogicalOp_of_num arg0 = (
-   (let l__362 = arg0 in
-   if (((l__362 = (( 0 :: int)::ii)))) then LogicalOp_AND
-   else if (((l__362 = (( 1 :: int)::ii)))) then LogicalOp_EOR
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then LogicalOp_AND
+   else if (((p00 = (( 1 :: int)::ii)))) then LogicalOp_EOR
    else LogicalOp_ORR))"
 
 
@@ -1786,14 +1825,14 @@ definition undefined_LogicalOp  :: " unit \<Rightarrow>((register_value),(Logica
 
 definition ExtendType_of_num  :: " int \<Rightarrow> ExtendType "  where 
      " ExtendType_of_num arg0 = (
-   (let l__355 = arg0 in
-   if (((l__355 = (( 0 :: int)::ii)))) then ExtendType_SXTB
-   else if (((l__355 = (( 1 :: int)::ii)))) then ExtendType_SXTH
-   else if (((l__355 = (( 2 :: int)::ii)))) then ExtendType_SXTW
-   else if (((l__355 = (( 3 :: int)::ii)))) then ExtendType_SXTX
-   else if (((l__355 = (( 4 :: int)::ii)))) then ExtendType_UXTB
-   else if (((l__355 = (( 5 :: int)::ii)))) then ExtendType_UXTH
-   else if (((l__355 = (( 6 :: int)::ii)))) then ExtendType_UXTW
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then ExtendType_SXTB
+   else if (((p00 = (( 1 :: int)::ii)))) then ExtendType_SXTH
+   else if (((p00 = (( 2 :: int)::ii)))) then ExtendType_SXTW
+   else if (((p00 = (( 3 :: int)::ii)))) then ExtendType_SXTX
+   else if (((p00 = (( 4 :: int)::ii)))) then ExtendType_UXTB
+   else if (((p00 = (( 5 :: int)::ii)))) then ExtendType_UXTH
+   else if (((p00 = (( 6 :: int)::ii)))) then ExtendType_UXTW
    else ExtendType_UXTX))"
 
 
@@ -1822,14 +1861,14 @@ definition undefined_ExtendType  :: " unit \<Rightarrow>((register_value),(Exten
 
 definition SystemHintOp_of_num  :: " int \<Rightarrow> SystemHintOp "  where 
      " SystemHintOp_of_num arg0 = (
-   (let l__348 = arg0 in
-   if (((l__348 = (( 0 :: int)::ii)))) then SystemHintOp_NOP
-   else if (((l__348 = (( 1 :: int)::ii)))) then SystemHintOp_YIELD
-   else if (((l__348 = (( 2 :: int)::ii)))) then SystemHintOp_WFE
-   else if (((l__348 = (( 3 :: int)::ii)))) then SystemHintOp_WFI
-   else if (((l__348 = (( 4 :: int)::ii)))) then SystemHintOp_SEV
-   else if (((l__348 = (( 5 :: int)::ii)))) then SystemHintOp_SEVL
-   else if (((l__348 = (( 6 :: int)::ii)))) then SystemHintOp_ESB
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then SystemHintOp_NOP
+   else if (((p00 = (( 1 :: int)::ii)))) then SystemHintOp_YIELD
+   else if (((p00 = (( 2 :: int)::ii)))) then SystemHintOp_WFE
+   else if (((p00 = (( 3 :: int)::ii)))) then SystemHintOp_WFI
+   else if (((p00 = (( 4 :: int)::ii)))) then SystemHintOp_SEV
+   else if (((p00 = (( 5 :: int)::ii)))) then SystemHintOp_SEVL
+   else if (((p00 = (( 6 :: int)::ii)))) then SystemHintOp_ESB
    else SystemHintOp_PSB))"
 
 
@@ -1858,9 +1897,9 @@ definition undefined_SystemHintOp  :: " unit \<Rightarrow>((register_value),(Sys
 
 definition MemOp_of_num  :: " int \<Rightarrow> MemOp "  where 
      " MemOp_of_num arg0 = (
-   (let l__346 = arg0 in
-   if (((l__346 = (( 0 :: int)::ii)))) then MemOp_LOAD
-   else if (((l__346 = (( 1 :: int)::ii)))) then MemOp_STORE
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then MemOp_LOAD
+   else if (((p00 = (( 1 :: int)::ii)))) then MemOp_STORE
    else MemOp_PREFETCH))"
 
 
@@ -1882,11 +1921,11 @@ definition undefined_MemOp  :: " unit \<Rightarrow>((register_value),(MemOp),(ex
 
 definition OpType_of_num  :: " int \<Rightarrow> OpType "  where 
      " OpType_of_num arg0 = (
-   (let l__342 = arg0 in
-   if (((l__342 = (( 0 :: int)::ii)))) then OpType_Load
-   else if (((l__342 = (( 1 :: int)::ii)))) then OpType_Store
-   else if (((l__342 = (( 2 :: int)::ii)))) then OpType_LoadAtomic
-   else if (((l__342 = (( 3 :: int)::ii)))) then OpType_Branch
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then OpType_Load
+   else if (((p00 = (( 1 :: int)::ii)))) then OpType_Store
+   else if (((p00 = (( 2 :: int)::ii)))) then OpType_LoadAtomic
+   else if (((p00 = (( 3 :: int)::ii)))) then OpType_Branch
    else OpType_Other))"
 
 
@@ -1911,10 +1950,10 @@ definition undefined_OpType  :: " unit \<Rightarrow>((register_value),(OpType),(
 
 definition FPUnaryOp_of_num  :: " int \<Rightarrow> FPUnaryOp "  where 
      " FPUnaryOp_of_num arg0 = (
-   (let l__339 = arg0 in
-   if (((l__339 = (( 0 :: int)::ii)))) then FPUnaryOp_ABS
-   else if (((l__339 = (( 1 :: int)::ii)))) then FPUnaryOp_MOV
-   else if (((l__339 = (( 2 :: int)::ii)))) then FPUnaryOp_NEG
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FPUnaryOp_ABS
+   else if (((p00 = (( 1 :: int)::ii)))) then FPUnaryOp_MOV
+   else if (((p00 = (( 2 :: int)::ii)))) then FPUnaryOp_NEG
    else FPUnaryOp_SQRT))"
 
 
@@ -1938,11 +1977,11 @@ definition undefined_FPUnaryOp  :: " unit \<Rightarrow>((register_value),(FPUnar
 
 definition CompareOp_of_num  :: " int \<Rightarrow> CompareOp "  where 
      " CompareOp_of_num arg0 = (
-   (let l__335 = arg0 in
-   if (((l__335 = (( 0 :: int)::ii)))) then CompareOp_GT
-   else if (((l__335 = (( 1 :: int)::ii)))) then CompareOp_GE
-   else if (((l__335 = (( 2 :: int)::ii)))) then CompareOp_EQ
-   else if (((l__335 = (( 3 :: int)::ii)))) then CompareOp_LE
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CompareOp_GT
+   else if (((p00 = (( 1 :: int)::ii)))) then CompareOp_GE
+   else if (((p00 = (( 2 :: int)::ii)))) then CompareOp_EQ
+   else if (((p00 = (( 3 :: int)::ii)))) then CompareOp_LE
    else CompareOp_LT))"
 
 
@@ -1967,11 +2006,11 @@ definition undefined_CompareOp  :: " unit \<Rightarrow>((register_value),(Compar
 
 definition PSTATEField_of_num  :: " int \<Rightarrow> PSTATEField "  where 
      " PSTATEField_of_num arg0 = (
-   (let l__331 = arg0 in
-   if (((l__331 = (( 0 :: int)::ii)))) then PSTATEField_DAIFSet
-   else if (((l__331 = (( 1 :: int)::ii)))) then PSTATEField_DAIFClr
-   else if (((l__331 = (( 2 :: int)::ii)))) then PSTATEField_PAN
-   else if (((l__331 = (( 3 :: int)::ii)))) then PSTATEField_UAO
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then PSTATEField_DAIFSet
+   else if (((p00 = (( 1 :: int)::ii)))) then PSTATEField_DAIFClr
+   else if (((p00 = (( 2 :: int)::ii)))) then PSTATEField_PAN
+   else if (((p00 = (( 3 :: int)::ii)))) then PSTATEField_UAO
    else PSTATEField_SP))"
 
 
@@ -1997,10 +2036,10 @@ definition undefined_PSTATEField  :: " unit \<Rightarrow>((register_value),(PSTA
 
 definition FPMaxMinOp_of_num  :: " int \<Rightarrow> FPMaxMinOp "  where 
      " FPMaxMinOp_of_num arg0 = (
-   (let l__328 = arg0 in
-   if (((l__328 = (( 0 :: int)::ii)))) then FPMaxMinOp_MAX
-   else if (((l__328 = (( 1 :: int)::ii)))) then FPMaxMinOp_MIN
-   else if (((l__328 = (( 2 :: int)::ii)))) then FPMaxMinOp_MAXNUM
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then FPMaxMinOp_MAX
+   else if (((p00 = (( 1 :: int)::ii)))) then FPMaxMinOp_MIN
+   else if (((p00 = (( 2 :: int)::ii)))) then FPMaxMinOp_MAXNUM
    else FPMaxMinOp_MINNUM))"
 
 
@@ -2024,9 +2063,9 @@ definition undefined_FPMaxMinOp  :: " unit \<Rightarrow>((register_value),(FPMax
 
 definition CountOp_of_num  :: " int \<Rightarrow> CountOp "  where 
      " CountOp_of_num arg0 = (
-   (let l__326 = arg0 in
-   if (((l__326 = (( 0 :: int)::ii)))) then CountOp_CLZ
-   else if (((l__326 = (( 1 :: int)::ii)))) then CountOp_CLS
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CountOp_CLZ
+   else if (((p00 = (( 1 :: int)::ii)))) then CountOp_CLS
    else CountOp_CNT))"
 
 
@@ -2048,9 +2087,9 @@ definition undefined_CountOp  :: " unit \<Rightarrow>((register_value),(CountOp)
 
 definition VFPNegMul_of_num  :: " int \<Rightarrow> VFPNegMul "  where 
      " VFPNegMul_of_num arg0 = (
-   (let l__324 = arg0 in
-   if (((l__324 = (( 0 :: int)::ii)))) then VFPNegMul_VNMLA
-   else if (((l__324 = (( 1 :: int)::ii)))) then VFPNegMul_VNMLS
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then VFPNegMul_VNMLA
+   else if (((p00 = (( 1 :: int)::ii)))) then VFPNegMul_VNMLS
    else VFPNegMul_VNMUL))"
 
 
@@ -2072,9 +2111,9 @@ definition undefined_VFPNegMul  :: " unit \<Rightarrow>((register_value),(VFPNeg
 
 definition VBitOps_of_num  :: " int \<Rightarrow> VBitOps "  where 
      " VBitOps_of_num arg0 = (
-   (let l__322 = arg0 in
-   if (((l__322 = (( 0 :: int)::ii)))) then VBitOps_VBIF
-   else if (((l__322 = (( 1 :: int)::ii)))) then VBitOps_VBIT
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then VBitOps_VBIF
+   else if (((p00 = (( 1 :: int)::ii)))) then VBitOps_VBIT
    else VBitOps_VBSL))"
 
 
@@ -2096,9 +2135,9 @@ definition undefined_VBitOps  :: " unit \<Rightarrow>((register_value),(VBitOps)
 
 definition VCGEtype_of_num  :: " int \<Rightarrow> VCGEtype "  where 
      " VCGEtype_of_num arg0 = (
-   (let l__320 = arg0 in
-   if (((l__320 = (( 0 :: int)::ii)))) then VCGEtype_signed
-   else if (((l__320 = (( 1 :: int)::ii)))) then VCGEtype_unsigned
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then VCGEtype_signed
+   else if (((p00 = (( 1 :: int)::ii)))) then VCGEtype_unsigned
    else VCGEtype_fp))"
 
 
@@ -2120,9 +2159,9 @@ definition undefined_VCGEtype  :: " unit \<Rightarrow>((register_value),(VCGEtyp
 
 definition VCGTtype_of_num  :: " int \<Rightarrow> VCGTtype "  where 
      " VCGTtype_of_num arg0 = (
-   (let l__318 = arg0 in
-   if (((l__318 = (( 0 :: int)::ii)))) then VCGTtype_signed
-   else if (((l__318 = (( 1 :: int)::ii)))) then VCGTtype_unsigned
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then VCGTtype_signed
+   else if (((p00 = (( 1 :: int)::ii)))) then VCGTtype_unsigned
    else VCGTtype_fp))"
 
 
@@ -2144,10 +2183,10 @@ definition undefined_VCGTtype  :: " unit \<Rightarrow>((register_value),(VCGTtyp
 
 definition InstrEnc_of_num  :: " int \<Rightarrow> InstrEnc "  where 
      " InstrEnc_of_num arg0 = (
-   (let l__315 = arg0 in
-   if (((l__315 = (( 0 :: int)::ii)))) then A64
-   else if (((l__315 = (( 1 :: int)::ii)))) then A32
-   else if (((l__315 = (( 2 :: int)::ii)))) then T16
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then A64
+   else if (((p00 = (( 1 :: int)::ii)))) then A32
+   else if (((p00 = (( 2 :: int)::ii)))) then T16
    else T32))"
 
 
@@ -2203,7 +2242,7 @@ definition UndefinedFault  :: " unit \<Rightarrow>((register_value),(unit),(exce
 definition ThisInstrAddr  :: " int \<Rightarrow> unit \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " ThisInstrAddr (N__tv :: int) _ = (
    (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
-   return ((slice0 w__0 (( 0 :: int)::ii) N__tv  :: ( 'N::len)Word.word))))"
+   return ((slice w__0 (( 0 :: int)::ii) N__tv  :: ( 'N::len)Word.word))))"
 
 
 (*val ThisInstr : unit -> M (mword ty32)*)
@@ -2266,52 +2305,52 @@ definition PACCellShuffle  :: "(64)Word.word \<Rightarrow>((register_value),((64
      " PACCellShuffle indata = (
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . 
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    return outdata))))))))))))))))))"
 
@@ -2322,52 +2361,52 @@ definition PACCellInvShuffle  :: "(64)Word.word \<Rightarrow>((register_value),(
      " PACCellInvShuffle indata = (
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . 
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    return outdata))))))))))))))))))"
 
@@ -2584,7 +2623,7 @@ definition FPDecodeRounding  :: "(2)Word.word \<Rightarrow> FPRounding "  where
 (*val FPRoundingMode : mword ty32 -> FPRounding*)
 
 definition FPRoundingMode  :: "(32)Word.word \<Rightarrow> FPRounding "  where 
-     " FPRoundingMode fpcr = ( FPDecodeRounding ((slice0 fpcr (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)))"
+     " FPRoundingMode fpcr = ( FPDecodeRounding ((slice fpcr (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)))"
 
 
 (*val __UNKNOWN_FPConvOp : unit -> FPConvOp*)
@@ -2725,21 +2764,21 @@ definition TweakCellRot  :: "(4)Word.word \<Rightarrow>((register_value),((4)Wor
      " TweakCellRot incell_name = (
    (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (outcell :: 4 bits) . 
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii)
         ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)]  ::  1 Word.word)
             (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)]  ::  1 Word.word)
            ::  1 Word.word))
        ::  4 Word.word)) in
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii)
         (vec_of_bits [access_vec_dec incell_name (( 3 :: int)::ii)]  ::  1 Word.word)
        ::  4 Word.word)) in
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii)
         (vec_of_bits [access_vec_dec incell_name (( 2 :: int)::ii)]  ::  1 Word.word)
        ::  4 Word.word)) in
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii)
         (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)]  ::  1 Word.word)
        ::  4 Word.word)) in
    return outcell))))))"
@@ -2751,53 +2790,53 @@ definition TweakShuffle  :: "(64)Word.word \<Rightarrow>((register_value),((64)W
      " TweakShuffle indata = (
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . 
    (let (outdata :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 ::
+   (TweakCellRot ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) w__0  ::  64 Word.word)) in
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) w__0  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 ::
+   (TweakCellRot ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) w__1  ::  64 Word.word)) in
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) w__1  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 ::
+   (TweakCellRot ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) w__2  ::  64 Word.word)) in
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) w__2  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 ::
+   (TweakCellRot ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__3  ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 ::
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__3  ::  64 Word.word)) in
+   (TweakCellRot ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) w__4  ::  64 Word.word)) in
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) w__4  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 ::
+   (TweakCellRot ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) w__5  ::  64 Word.word)) in
-   (TweakCellRot ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 ::
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) w__5  ::  64 Word.word)) in
+   (TweakCellRot ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 ::
       4 Word.word) . 
-   (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6  ::  64 Word.word)) in
+   (let (outdata :: 64 bits) = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6  ::  64 Word.word)) in
    return outdata)))))))))))))))))))))))))"
 
 
@@ -2807,19 +2846,19 @@ definition TweakCellInvRot  :: "(4)Word.word \<Rightarrow>((register_value),((4)
      " TweakCellInvRot incell_name = (
    (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (outcell :: 4 bits) . 
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii)
         (vec_of_bits [access_vec_dec incell_name (( 2 :: int)::ii)]  ::  1 Word.word)
        ::  4 Word.word)) in
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii)
         (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)]  ::  1 Word.word)
        ::  4 Word.word)) in
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii)
         (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)]  ::  1 Word.word)
        ::  4 Word.word)) in
    (let (outcell :: 4 bits) =
-     ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii)
+     ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii)
         ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)]  ::  1 Word.word)
             (vec_of_bits [access_vec_dec incell_name (( 3 :: int)::ii)]  ::  1 Word.word)
            ::  1 Word.word))
@@ -2832,54 +2871,54 @@ definition TweakCellInvRot  :: "(4)Word.word \<Rightarrow>((register_value),((4)
 definition TweakInvShuffle  :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
      " TweakInvShuffle indata = (
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . 
-   (TweakCellInvRot ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 ::
+   (TweakCellInvRot ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 ::
       4 Word.word) . 
-   (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) w__0  ::  64 Word.word)) in
+   (let (outdata :: 64 bits) = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) w__0  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellInvRot ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 ::
+   (TweakCellInvRot ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) w__1  ::  64 Word.word)) in
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) w__1  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellInvRot ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 ::
+   (TweakCellInvRot ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) w__2  ::  64 Word.word)) in
-   (TweakCellInvRot ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 ::
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) w__2  ::  64 Word.word)) in
+   (TweakCellInvRot ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) w__3  ::  64 Word.word)) in
-   (TweakCellInvRot ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 ::
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) w__3  ::  64 Word.word)) in
+   (TweakCellInvRot ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) w__4  ::  64 Word.word)) in
-   (TweakCellInvRot ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 ::
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) w__4  ::  64 Word.word)) in
+   (TweakCellInvRot ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 ::
       4 Word.word) . 
-   (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__5  ::  64 Word.word)) in
+   (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__5  ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
    (let outdata =
-     ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
        ::  64 Word.word)) in
-   (TweakCellInvRot ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 ::
+   (TweakCellInvRot ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 ::
       4 Word.word) . 
-   (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6  ::  64 Word.word)) in
+   (let (outdata :: 64 bits) = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6  ::  64 Word.word)) in
    return outdata)))))))))))))))))))))))))"
 
 
@@ -3197,7 +3236,7 @@ definition AArch64_SysRegWrite  :: " int \<Rightarrow> int \<Rightarrow> int \<R
 
 definition AArch64_SysRegRead  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
      " AArch64_SysRegRead arg0 arg1 arg2 arg3 arg4 = (
-   (let g__614 = (arg0, arg1, arg2, arg3, arg4) in
+   (let g__301 = (arg0, arg1, arg2, arg3, arg4) in
    assert_exp False (''Tried to read system register'') \<then>
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)))"
 
@@ -3220,13 +3259,13 @@ definition AArch64_ReportDeferredSError  :: "(25)Word.word \<Rightarrow>((regist
      " AArch64_ReportDeferredSError syndrome = (
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (target :: 64 bits) . 
    (let (target :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)) in
+     ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)) in
    (let (target :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 24 :: int)::ii)
+     ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 24 :: int)::ii)
         (vec_of_bits [access_vec_dec syndrome (( 24 :: int)::ii)]  ::  1 Word.word)
        ::  64 Word.word)) in
    (let (target :: 64 bits) =
-     ((set_slice0 (( 64 :: int)::ii) (( 24 :: int)::ii) target (( 0 :: int)::ii) ((slice0 syndrome (( 0 :: int)::ii) (( 24 :: int)::ii)  ::  24 Word.word))
+     ((set_slice (( 64 :: int)::ii) (( 24 :: int)::ii) target (( 0 :: int)::ii) ((slice syndrome (( 0 :: int)::ii) (( 24 :: int)::ii)  ::  24 Word.word))
        ::  64 Word.word)) in
    return target)))))"
 
@@ -3382,23 +3421,23 @@ definition aget_SP  :: " int \<Rightarrow> unit \<Rightarrow>((register_value),(
    read_reg PSTATE_ref) \<bind> (\<lambda> (w__0 :: ProcState) . 
    if ((((ProcState_SP   w__0) = (vec_of_bits [B0]  ::  1 Word.word)))) then
      (read_reg SP_EL0_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
-     return ((slice0 w__1 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
+     return ((slice w__1 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
    else
      read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
-     (let p__613 = ((ProcState_EL   w__2)) in
-     (let pat0 = p__613 in
+     (let p__300 = ((ProcState_EL   w__2)) in
+     (let pat0 = p__300 in
      if (((pat0 = EL0))) then
        (read_reg SP_EL0_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
-       return ((slice0 w__3 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
+       return ((slice w__3 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
      else if (((pat0 = EL1))) then
        (read_reg SP_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 bits) . 
-       return ((slice0 w__4 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
+       return ((slice w__4 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
      else if (((pat0 = EL2))) then
        (read_reg SP_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
-       return ((slice0 w__5 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
+       return ((slice w__5 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
      else
        (read_reg SP_EL3_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 bits) . 
-       return ((slice0 w__6 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word))))))))"
+       return ((slice w__6 (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word))))))))"
 
 
 (*val __IMPDEF_integer : string -> ii*)
@@ -3473,7 +3512,7 @@ definition RoundTowardsZero  :: " real \<Rightarrow> int "  where
 definition Restarting  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " Restarting _ = (
    (read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
-   return (((((slice0 w__0 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1]  ::  6 Word.word))))))"
+   return (((((slice w__0 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1]  ::  6 Word.word))))))"
 
 
 (*val PtrHasUpperAndLowerAddRanges : unit -> M bool*)
@@ -3770,12 +3809,12 @@ definition aget_Vpart  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow
    (if (((part = (( 0 :: int)::ii)))) then
      (assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \<or> ((((((width__tv = (( 16 :: int)::ii)))) \<or> ((((((width__tv = (( 32 :: int)::ii)))) \<or> (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'') \<then>
      read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 bits) list) . 
-     return ((slice0 ((access_list_dec w__0 n  ::  128 Word.word)) (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
+     return ((slice ((access_list_dec w__0 n  ::  128 Word.word)) (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
    else
      (assert_exp (((width__tv = (( 64 :: int)::ii)))) (''(width == 64)'') \<then>
      read_reg V_ref) \<bind> (\<lambda> (w__1 :: ( 128 bits) list) . 
      return ((Word.ucast
-                ((slice0 ((access_list_dec w__1 n  ::  128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii)  :: ( 'width::len)Word.word))
+                ((slice ((access_list_dec w__1 n  ::  128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii)  :: ( 'width::len)Word.word))
                :: ( 'width::len)Word.word)))))"
 
 
@@ -3786,7 +3825,7 @@ definition aget_V  :: " int \<Rightarrow> int \<Rightarrow>((register_value),(('
    ((assert_exp (((((n \<ge> (( 0 :: int)::ii))) \<and> ((n \<le> (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \<then>
    assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \<or> ((((((width__tv = (( 16 :: int)::ii)))) \<or> ((((((width__tv = (( 32 :: int)::ii)))) \<or> ((((((width__tv = (( 64 :: int)::ii)))) \<or> (((width__tv = (( 128 :: int)::ii)))))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))'')) \<then>
    read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 bits) list) . 
-   return ((slice0 ((access_list_dec w__0 n  ::  128 Word.word)) (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word))))"
+   return ((slice ((access_list_dec w__0 n  ::  128 Word.word)) (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word))))"
 
 
 (*val LookUpRIndex : ii -> mword ty5 -> M ii*)
@@ -3795,19 +3834,18 @@ definition LookUpRIndex  :: " int \<Rightarrow>(5)Word.word \<Rightarrow>((regis
      " LookUpRIndex n mode = (
    (assert_exp (((((n \<ge> (( 0 :: int)::ii))) \<and> ((n \<le> (( 14 :: int)::ii)))))) (''((n >= 0) && (n <= 14))'') \<then>
    undefined_int () ) \<bind> (\<lambda> (result :: ii) . 
-   (let l__308 = n in
-   if (((l__308 = (( 8 :: int)::ii)))) then RBankSelect mode (( 8 :: int)::ii) (( 24 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii)
-   else if (((l__308 = (( 9 :: int)::ii)))) then
-     RBankSelect mode (( 9 :: int)::ii) (( 25 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii)
-   else if (((l__308 = (( 10 :: int)::ii)))) then
+   (let p00 = n in
+   if (((p00 = (( 8 :: int)::ii)))) then RBankSelect mode (( 8 :: int)::ii) (( 24 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii)
+   else if (((p00 = (( 9 :: int)::ii)))) then RBankSelect mode (( 9 :: int)::ii) (( 25 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii)
+   else if (((p00 = (( 10 :: int)::ii)))) then
      RBankSelect mode (( 10 :: int)::ii) (( 26 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii)
-   else if (((l__308 = (( 11 :: int)::ii)))) then
+   else if (((p00 = (( 11 :: int)::ii)))) then
      RBankSelect mode (( 11 :: int)::ii) (( 27 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii)
-   else if (((l__308 = (( 12 :: int)::ii)))) then
+   else if (((p00 = (( 12 :: int)::ii)))) then
      RBankSelect mode (( 12 :: int)::ii) (( 28 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii)
-   else if (((l__308 = (( 13 :: int)::ii)))) then
+   else if (((p00 = (( 13 :: int)::ii)))) then
      RBankSelect mode (( 13 :: int)::ii) (( 29 :: int)::ii) (( 17 :: int)::ii) (( 19 :: int)::ii) (( 21 :: int)::ii) (( 23 :: int)::ii) (( 15 :: int)::ii)
-   else if (((l__308 = (( 14 :: int)::ii)))) then
+   else if (((p00 = (( 14 :: int)::ii)))) then
      RBankSelect mode (( 14 :: int)::ii) (( 30 :: int)::ii) (( 16 :: int)::ii) (( 18 :: int)::ii) (( 20 :: int)::ii) (( 22 :: int)::ii) (( 14 :: int)::ii)
    else return n)))"
 
@@ -3851,7 +3889,7 @@ definition BitReverse  :: "('N::len)Word.word \<Rightarrow>((register_value),(('
    (let (result :: 'N bits) =
      (foreach (index_list (( 0 :: int)::ii) ((((int (size data))) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
        (\<lambda> i result . 
-         (set_slice0 ((int (size data))) (( 1 :: int)::ii) result
+         (set_slice ((int (size data))) (( 1 :: int)::ii) result
             ((((((int (size data))) - i)) - (( 1 :: int)::ii)))
             (vec_of_bits [access_vec_dec data i]  ::  1 Word.word)
            :: ( 'N::len)Word.word))) in
@@ -3864,7 +3902,7 @@ definition NextInstrAddr  :: " int \<Rightarrow> unit \<Rightarrow>((register_va
      " NextInstrAddr (N__tv :: int) _ = (
    (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    ThisInstrLength ()  \<bind> (\<lambda> (w__1 :: ii) . 
-   return ((slice0 ((add_vec_int w__0 ((((ex_int w__1)) div (( 8 :: int)::ii)))  ::  64 Word.word)) (( 0 :: int)::ii)
+   return ((slice ((add_vec_int w__0 ((((ex_int w__1)) div (( 8 :: int)::ii)))  ::  64 Word.word)) (( 0 :: int)::ii)
               N__tv
              :: ( 'N::len)Word.word)))))"
 
@@ -3950,12 +3988,12 @@ definition RotCell  :: "(4)Word.word \<Rightarrow> int \<Rightarrow>((register_v
    (undefined_bitvector (( 8 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (tmp :: 8 bits) . 
    (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (outcell :: 4 bits) . 
    (let (tmp :: 8 bits) =
-     ((set_slice0 (( 8 :: int)::ii) (( 8 :: int)::ii) tmp (( 0 :: int)::ii)
-        ((concat_vec ((slice0 incell_name (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
-            ((slice0 incell_name (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     ((set_slice (( 8 :: int)::ii) (( 8 :: int)::ii) tmp (( 0 :: int)::ii)
+        ((concat_vec ((slice incell_name (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+            ((slice incell_name (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
            ::  8 Word.word))
        ::  8 Word.word)) in
-   (let (outcell :: 4 bits) = ((slice0 tmp (((( 4 :: int)::ii) - amount)) (( 4 :: int)::ii)  ::  4 Word.word)) in
+   (let (outcell :: 4 bits) = ((slice tmp (((( 4 :: int)::ii) - amount)) (( 4 :: int)::ii)  ::  4 Word.word)) in
    return outcell)))))"
 
 
@@ -3963,8 +4001,8 @@ definition RotCell  :: "(4)Word.word \<Rightarrow> int \<Rightarrow>((register_v
 
 definition FPNeg  :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPNeg op1 = (
-   (let l__305 = (int (size op1)) in
-   if (((l__305 = (( 16 :: int)::ii)))) then
+   (let p00 = (int (size op1)) in
+   if (((p00 = (( 16 :: int)::ii)))) then
      (let (op1 ::  16 Word.word) = ((Word.ucast op1  ::  16 Word.word)) in
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      return ((Word.ucast
@@ -3973,10 +4011,10 @@ definition FPNeg  :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le
                         (vec_of_bits [access_vec_dec op1 (((( 16 :: int)::ii) - (( 1 :: int)::ii)))]
                           ::  1 Word.word)
                        ::  1 Word.word))
-                    ((slice0 op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii)))  ::  15 Word.word))
+                    ((slice op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii)))  ::  15 Word.word))
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))
-   else if (((l__305 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      (let (op1 ::  32 Word.word) = ((Word.ucast op1  ::  32 Word.word)) in
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      return ((Word.ucast
@@ -3985,10 +4023,10 @@ definition FPNeg  :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le
                         (vec_of_bits [access_vec_dec op1 (((( 32 :: int)::ii) - (( 1 :: int)::ii)))]
                           ::  1 Word.word)
                        ::  1 Word.word))
-                    ((slice0 op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii)))  ::  31 Word.word))
+                    ((slice op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii)))  ::  31 Word.word))
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))
-   else if (((l__305 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      (let (op1 ::  64 Word.word) = ((Word.ucast op1  ::  64 Word.word)) in
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      return ((Word.ucast
@@ -3997,7 +4035,7 @@ definition FPNeg  :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le
                         (vec_of_bits [access_vec_dec op1 (((( 64 :: int)::ii) - (( 1 :: int)::ii)))]
                           ::  1 Word.word)
                        ::  1 Word.word))
-                    ((slice0 op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii)))  ::  63 Word.word))
+                    ((slice op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii)))  ::  63 Word.word))
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))
    else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))"
@@ -4007,29 +4045,29 @@ definition FPNeg  :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le
 
 definition FPAbs  :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPAbs op1 = (
-   (let l__302 = (int (size op1)) in
-   if (((l__302 = (( 16 :: int)::ii)))) then
+   (let p00 = (int (size op1)) in
+   if (((p00 = (( 16 :: int)::ii)))) then
      (let (op1 ::  16 Word.word) = ((Word.ucast op1  ::  16 Word.word)) in
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      return ((Word.ucast
                 ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
-                    ((slice0 op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii)))  ::  15 Word.word))
+                    ((slice op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii)))  ::  15 Word.word))
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))
-   else if (((l__302 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      (let (op1 ::  32 Word.word) = ((Word.ucast op1  ::  32 Word.word)) in
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      return ((Word.ucast
                 ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
-                    ((slice0 op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii)))  ::  31 Word.word))
+                    ((slice op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii)))  ::  31 Word.word))
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))
-   else if (((l__302 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      (let (op1 ::  64 Word.word) = ((Word.ucast op1  ::  64 Word.word)) in
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      return ((Word.ucast
                 ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
-                    ((slice0 op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii)))  ::  63 Word.word))
+                    ((slice op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii)))  ::  63 Word.word))
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))
    else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))"
@@ -4114,23 +4152,6 @@ definition EncodeLDFSC  :: " Fault \<Rightarrow> int \<Rightarrow>((register_val
    )))"
 
 
-(*val BigEndianReverse : forall 'width . Size 'width => mword 'width -> M (mword 'width)*)
-
-definition BigEndianReverse  :: "('width::len)Word.word \<Rightarrow>((register_value),(('width::len)Word.word),(exception))monad "  where 
-     " BigEndianReverse value_name = (
-   assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 64 :: int)::ii)))) \<or> (((((int (size value_name))) = (( 128 :: int)::ii)))))))))))))))) ('''') \<then>
-   ((let (result :: 'width bits) =
-     ((replicate_bits (vec_of_bits [B0]  ::  1 Word.word) ((int (size value_name)))  :: ( 'width::len)Word.word)) in
-   (let (result :: 'width bits) =
-     (foreach (index_list (( 0 :: int)::ii) ((((int (size result))) - (( 1 :: int)::ii))) (( 8 :: int)::ii)) result
-       (\<lambda> i result . 
-         (update_subrange_vec_dec result ((i + (( 7 :: int)::ii))) i
-            ((subrange_vec_dec value_name
-                ((((((int (size result))) - i)) - (( 1 :: int)::ii)))
-                ((((((int (size result))) - i)) - (( 8 :: int)::ii)))
-               ::  8 Word.word))
-           :: ( 'width::len)Word.word))) in
-   return result))))"
 
 
 (*val AArch32_ReportHypEntry : ExceptionRecord -> M unit*)
@@ -4156,25 +4177,25 @@ definition AArch32_ReportHypEntry  :: " ExceptionRecord \<Rightarrow>((register_
             ::  7 Word.word)) iss
         ::  32 Word.word)) \<then>
    (if ((((((typ1 = Exception_InstructionAbort))) \<or> (((typ1 = Exception_PCAlignment)))))) then
-      (write_reg HIFAR_ref ((slice0(ExceptionRecord_vaddress   exception) (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
+      (write_reg HIFAR_ref ((slice(ExceptionRecord_vaddress   exception) (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
       (undefined_bitvector (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__0 :: 32 bits) . 
       write_reg HDFAR_ref w__0)
     else if (((typ1 = Exception_DataAbort))) then
       (undefined_bitvector (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
       write_reg HIFAR_ref w__1 \<then>
-      write_reg HDFAR_ref ((slice0(ExceptionRecord_vaddress   exception) (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)))
+      write_reg HDFAR_ref ((slice(ExceptionRecord_vaddress   exception) (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)))
     else return () )) \<then>
    (if(ExceptionRecord_ipavalid   exception) then
      (read_reg HPFAR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
      write_reg
        HPFAR_ref
-       ((set_slice0 (( 32 :: int)::ii) (( 28 :: int)::ii) w__2 (( 4 :: int)::ii)
-           ((slice0(ExceptionRecord_ipaddress   exception) (( 12 :: int)::ii) (( 28 :: int)::ii)  ::  28 Word.word))
+       ((set_slice (( 32 :: int)::ii) (( 28 :: int)::ii) w__2 (( 4 :: int)::ii)
+           ((slice(ExceptionRecord_ipaddress   exception) (( 12 :: int)::ii) (( 28 :: int)::ii)  ::  28 Word.word))
           ::  32 Word.word)))
    else
      (read_reg HPFAR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
      (undefined_bitvector (( 28 :: int)::ii)  :: ( 28 Word.word) M) \<bind> (\<lambda> (w__4 ::  28 Word.word) . 
-     write_reg HPFAR_ref ((set_slice0 (( 32 :: int)::ii) (( 28 :: int)::ii) w__3 (( 4 :: int)::ii) w__4  ::  32 Word.word)))))))))))))))"
+     write_reg HPFAR_ref ((set_slice (( 32 :: int)::ii) (( 28 :: int)::ii) w__3 (( 4 :: int)::ii) w__4  ::  32 Word.word)))))))))))))))"
 
 
 (*val aset_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> mword 'size -> M (mword 'N)*)
@@ -4187,7 +4208,7 @@ definition aset_Elem__0  :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>(
    (let vector_name = vector_name__arg in
    assert_exp (((((e \<ge> (( 0 :: int)::ii))) \<and> ((((((e + (( 1 :: int)::ii))) * size1)) \<le> ((int (size vector_name)))))))) (''((e >= 0) && (((e + 1) * size) <= N))'') \<then>
    ((let (vector_name :: ( 'N::len)Word.word) =
-     ((set_slice0 ((int (size vector_name))) size1 vector_name ((e * size1)) value_name
+     ((set_slice ((int (size vector_name))) size1 vector_name ((e * size1)) value_name
        :: ( 'N::len)Word.word)) in
    return vector_name)))))"
 
@@ -4207,7 +4228,7 @@ definition aget_Elem__0  :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>(
      " aget_Elem__0 vector_name e size1 = (
    (let size1 = (size_itself_int size1) in
    assert_exp (((((e \<ge> (( 0 :: int)::ii))) \<and> ((((((e + (( 1 :: int)::ii))) * size1)) \<le> ((int (size vector_name)))))))) (''((e >= 0) && (((e + 1) * size) <= N))'') \<then>
-   return ((slice0 vector_name ((e * size1)) size1  :: ( 'size::len)Word.word))))"
+   return ((slice vector_name ((e * size1)) size1  :: ( 'size::len)Word.word))))"
 
 
 definition aget_Elem__1  :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('size::len)Word.word),(exception))monad "  where 
@@ -4286,7 +4307,8 @@ definition SatQ  :: " int \<Rightarrow>('N::len)itself \<Rightarrow> bool \<Righ
 definition Replicate  :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " Replicate (N__tv :: int) x = (
    assert_exp (((((N__tv mod ((int (size x))))) = (( 0 :: int)::ii)))) (''((N MOD M) == 0)'') \<then>
-   return ((replicate_bits x ((N__tv div ((int (size x)))))  :: ( 'N::len)Word.word)))"
+   ((let O1 = (N__tv div ((int (size x)))) in
+   assert_exp True ('''') \<then> return ((replicate_bits x ((N__tv div ((int (size x)))))  :: ( 'N::len)Word.word)))))"
 
 
 (*val Zeros__0 : forall 'N . Size 'N => itself 'N -> mword 'N*)
@@ -4382,8 +4404,8 @@ definition aset_SP  :: "('width::len)Word.word \<Rightarrow>((register_value),(u
      write_reg SP_EL0_ref w__1)
    else
      read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
-     (let p__612 = ((ProcState_EL   w__2)) in
-     (let pat0 = p__612 in
+     (let p__299 = ((ProcState_EL   w__2)) in
+     (let pat0 = p__299 in
      if (((pat0 = EL0))) then
        (ZeroExtend__1 (( 64 :: int)::ii) value_name  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
        write_reg SP_EL0_ref w__3)
@@ -4439,7 +4461,7 @@ definition Poly32Mod2  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right
            (or_vec data ((sub_vec_int ((shiftl poly' i  :: ( 'N::len)Word.word)) (( 32 :: int)::ii)  :: ( 'N::len)Word.word))
              :: ( 'N::len)Word.word)
          else data)) in
-   return ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)))))))"
+   return ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)))))))"
 
 
 (*val LSL_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*)
@@ -4474,7 +4496,7 @@ definition LSL  :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register
 definition AArch32_ITAdvance  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " AArch32_ITAdvance _ = (
    read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . 
-   if (((((slice0(ProcState_IT   w__0) (( 0 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then
+   if (((((slice(ProcState_IT   w__0) (( 0 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then
      read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . 
      write_reg
        PSTATE_ref
@@ -4483,9 +4505,9 @@ definition AArch32_ITAdvance  :: " unit \<Rightarrow>((register_value),(unit),(e
      read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
      (let (tmp_2760 :: 8 bits) = ((ProcState_IT   w__2)) in
      read_reg PSTATE_ref \<bind> (\<lambda> (w__3 :: ProcState) . 
-     (LSL ((slice0(ProcState_IT   w__3) (( 0 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word)) (( 1 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__4 ::
+     (LSL ((slice(ProcState_IT   w__3) (( 0 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word)) (( 1 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__4 ::
         5 Word.word) . 
-     (let tmp_2760 = ((set_slice0 (( 8 :: int)::ii) (( 5 :: int)::ii) tmp_2760 (( 0 :: int)::ii) w__4  ::  8 Word.word)) in
+     (let tmp_2760 = ((set_slice (( 8 :: int)::ii) (( 5 :: int)::ii) tmp_2760 (( 0 :: int)::ii) w__4  ::  8 Word.word)) in
      read_reg PSTATE_ref \<bind> (\<lambda> (w__5 :: ProcState) . 
      write_reg PSTATE_ref (w__5 (| ProcState_IT := tmp_2760 |))))))))))"
 
@@ -4608,22 +4630,22 @@ definition GetPSRFromPSTATE  :: " unit \<Rightarrow>((register_value),((32)Word.
 
 definition FPZero  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPZero (N__tv :: int) sign = (
-   (let l__299 = N__tv in
-   if (((l__299 = (( 16 :: int)::ii)))) then
+   (let p00 = N__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 5 bits) = ((Zeros__0 ((make_the_value (( 5 :: int)::ii)  ::  5 itself))  ::  5 Word.word)) in
      (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F  ::  10 itself))  ::  10 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  6 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word))))))
-   else if (((l__299 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 8 bits) = ((Zeros__0 ((make_the_value (( 8 :: int)::ii)  ::  8 itself))  ::  8 Word.word)) in
      (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F  ::  23 itself))  ::  23 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  9 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word))))))
-   else if (((l__299 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 11 bits) = ((Zeros__0 ((make_the_value (( 11 :: int)::ii)  ::  11 itself))  ::  11 Word.word)) in
@@ -4698,8 +4720,8 @@ definition AArch32_PhysicalSErrorSyndrome  :: " unit \<Rightarrow>((register_val
 
 definition VFPExpandImm  :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " VFPExpandImm (N__tv :: int) imm8 = (
-   (let l__296 = N__tv in
-   if (((l__296 = (( 16 :: int)::ii)))) then
+   (let p00 = N__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)]  ::  1 Word.word)) in
@@ -4718,7 +4740,7 @@ definition VFPExpandImm  :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis
          ::  10 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  6 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))))))
-   else if (((l__296 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)]  ::  1 Word.word)) in
@@ -4737,7 +4759,7 @@ definition VFPExpandImm  :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis
          ::  23 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  9 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))))))
-   else if (((l__296 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)]  ::  1 Word.word)) in
@@ -4842,8 +4864,8 @@ definition IsOnes  :: "('N::len)Word.word \<Rightarrow> bool "  where
 
 definition FPMaxNormal  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPMaxNormal (N__tv :: int) sign = (
-   (let l__293 = N__tv in
-   if (((l__293 = (( 16 :: int)::ii)))) then
+   (let p00 = N__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 5 bits) =
@@ -4854,7 +4876,7 @@ definition FPMaxNormal  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist
      (let (frac :: 10 bits) = ((Ones__0 ((make_the_value F  ::  10 itself))  ::  10 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  6 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word))))))
-   else if (((l__293 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 8 bits) =
@@ -4865,7 +4887,7 @@ definition FPMaxNormal  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist
      (let (frac :: 23 bits) = ((Ones__0 ((make_the_value F  ::  23 itself))  ::  23 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  9 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word))))))
-   else if (((l__293 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 11 bits) =
@@ -4883,22 +4905,22 @@ definition FPMaxNormal  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist
 
 definition FPInfinity  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPInfinity (N__tv :: int) sign = (
-   (let l__290 = N__tv in
-   if (((l__290 = (( 16 :: int)::ii)))) then
+   (let p00 = N__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii)  ::  5 itself))  ::  5 Word.word)) in
      (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F  ::  10 itself))  ::  10 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  6 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word))))))
-   else if (((l__290 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii)  ::  8 itself))  ::  8 Word.word)) in
      (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F  ::  23 itself))  ::  23 Word.word)) in
      return ((Word.ucast ((concat_vec ((concat_vec sign exp  ::  9 Word.word)) frac  :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word))))))
-   else if (((l__290 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (exp :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii)  ::  11 itself))  ::  11 Word.word)) in
@@ -4912,8 +4934,8 @@ definition FPInfinity  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((registe
 
 definition FPDefaultNaN  :: " int \<Rightarrow> unit \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPDefaultNaN (N__tv :: int) _ = (
-   (let l__287 = N__tv in
-   if (((l__287 = (( 16 :: int)::ii)))) then
+   (let p00 = N__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (sign :: 1 bits) = ((vec_of_bits [B0]  ::  1 Word.word)) in
@@ -4926,7 +4948,7 @@ definition FPDefaultNaN  :: " int \<Rightarrow> unit \<Rightarrow>((register_val
                 ((concat_vec ((concat_vec (vec_of_bits [B0]  ::  1 Word.word) exp  ::  6 Word.word)) frac
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))))))
-   else if (((l__287 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (sign :: 1 bits) = ((vec_of_bits [B0]  ::  1 Word.word)) in
@@ -4939,7 +4961,7 @@ definition FPDefaultNaN  :: " int \<Rightarrow> unit \<Rightarrow>((register_val
                 ((concat_vec ((concat_vec (vec_of_bits [B0]  ::  1 Word.word) exp  ::  9 Word.word)) frac
                    :: ( 'N::len)Word.word))
                :: ( 'N::len)Word.word)))))))
-   else if (((l__287 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
      ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in
      (let (sign :: 1 bits) = ((vec_of_bits [B0]  ::  1 Word.word)) in
@@ -4965,40 +4987,40 @@ definition FPConvertNaN  :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>(
    (undefined_bitvector (( 51 :: int)::ii)  :: ( 51 Word.word) M) \<bind> (\<lambda> (frac :: 51 bits) . 
    (let (sign :: 1 bits) =
      ((vec_of_bits [access_vec_dec op1 ((((int (size op1))) - (( 1 :: int)::ii)))]  ::  1 Word.word)) in
-   (let l__281 = (int (size op1)) in
+   (let p00 = (int (size op1)) in
    (let (frac :: 51 bits) =
-     (if (((l__281 = (( 64 :: int)::ii)))) then
+     (if (((p00 = (( 64 :: int)::ii)))) then
        (let (op1 ::  64 Word.word) = ((Word.ucast op1  ::  64 Word.word)) in
-       (slice0 op1 (( 0 :: int)::ii) (( 51 :: int)::ii)  ::  51 Word.word))
-     else if (((l__281 = (( 32 :: int)::ii)))) then
+       (slice op1 (( 0 :: int)::ii) (( 51 :: int)::ii)  ::  51 Word.word))
+     else if (((p00 = (( 32 :: int)::ii)))) then
        (let (op1 ::  32 Word.word) = ((Word.ucast op1  ::  32 Word.word)) in
-       (concat_vec ((slice0 op1 (( 0 :: int)::ii) (( 22 :: int)::ii)  ::  22 Word.word))
+       (concat_vec ((slice op1 (( 0 :: int)::ii) (( 22 :: int)::ii)  ::  22 Word.word))
           ((Zeros__0 ((make_the_value (( 29 :: int)::ii)  ::  29 itself))  ::  29 Word.word))
          ::  51 Word.word))
      else
        (let (op1 ::  16 Word.word) = ((Word.ucast op1  ::  16 Word.word)) in
-       (concat_vec ((slice0 op1 (( 0 :: int)::ii) (( 9 :: int)::ii)  ::  9 Word.word))
+       (concat_vec ((slice op1 (( 0 :: int)::ii) (( 9 :: int)::ii)  ::  9 Word.word))
           ((Zeros__0 ((make_the_value (( 42 :: int)::ii)  ::  42 itself))  ::  42 Word.word))
          ::  51 Word.word))) in
-   (let l__284 = (int (size result)) in
+   (let p00 = (int (size result)) in
    (let (result :: 'M bits) =
-     (if (((l__284 = (( 64 :: int)::ii)))) then
+     (if (((p00 = (( 64 :: int)::ii)))) then
        (concat_vec
           ((concat_vec sign
               ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 52 :: int)::ii))) ))  ::  12 Word.word))
              ::  13 Word.word)) frac
          :: ( 'M::len)Word.word)
-     else if (((l__284 = (( 32 :: int)::ii)))) then
+     else if (((p00 = (( 32 :: int)::ii)))) then
        (concat_vec
           ((concat_vec sign
               ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 23 :: int)::ii))) ))  ::  9 Word.word))
-             ::  10 Word.word)) ((slice0 frac (( 29 :: int)::ii) (( 22 :: int)::ii)  ::  22 Word.word))
+             ::  10 Word.word)) ((slice frac (( 29 :: int)::ii) (( 22 :: int)::ii)  ::  22 Word.word))
          :: ( 'M::len)Word.word)
      else
        (concat_vec
           ((concat_vec sign
-              ((Ones__0 ((make_the_value ((l__284 - (( 10 :: int)::ii))) ))  ::  6 Word.word))
-             ::  7 Word.word)) ((slice0 frac (( 42 :: int)::ii) (( 9 :: int)::ii)  ::  9 Word.word))
+              ((Ones__0 ((make_the_value ((p00 - (( 10 :: int)::ii))) ))  ::  6 Word.word))
+             ::  7 Word.word)) ((slice frac (( 42 :: int)::ii) (( 9 :: int)::ii)  ::  9 Word.word))
          :: ( 'M::len)Word.word)) in
    return result))))))))"
 
@@ -5014,7 +5036,7 @@ definition ExcVectorBase  :: " unit \<Rightarrow>((register_value),((32)Word.wor
                ::  32 Word.word))
    else
      (read_reg VBAR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
-     return ((concat_vec ((slice0 w__1 (( 5 :: int)::ii) (( 27 :: int)::ii)  ::  27 Word.word))
+     return ((concat_vec ((slice w__1 (( 5 :: int)::ii) (( 27 :: int)::ii)  ::  27 Word.word))
                 ((Zeros__0 ((make_the_value (( 5 :: int)::ii)  ::  5 itself))  ::  5 Word.word))
                ::  32 Word.word)))))"
 
@@ -5027,69 +5049,69 @@ definition PACSub  :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.wo
    (let (Toutput :: 64 bits) =
      (foreach (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) Toutput
        (\<lambda> i Toutput . 
-         (let b__0 = ((slice0 Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) in
+         (let b__0 = ((slice Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) in
          if (((b__0 = (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B1,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B1,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B1,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B1,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)))) in
    return Toutput)))"
@@ -5104,78 +5126,80 @@ definition PACMult  :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.w
    (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (t2 :: 4 bits) . 
    (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (t3 :: 4 bits) . 
    (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (Soutput :: 64 bits) . 
-   (foreachM (index_list (( 0 :: int)::ii) (( 3 :: int)::ii) (( 1 :: int)::ii)) Soutput
-     (\<lambda> i Soutput . 
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+   (foreachM (index_list (( 0 :: int)::ii) (( 3 :: int)::ii) (( 1 :: int)::ii)) (Soutput, t0, t1, t2, t3)
+     (\<lambda> i varstup .  (let (Soutput, t0, t1, t2, t3) = varstup in
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 ::  4 Word.word) . 
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 2 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 ::  4 Word.word) . 
-       (let t0 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) ((xor_vec w__0 w__1  ::  4 Word.word))  ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) (( 1 :: int)::ii)
+       (let t0 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) ((xor_vec w__0 w__1  ::  4 Word.word))  ::  4 Word.word)) in
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 ::  4 Word.word) . 
        (let t0 =
-         ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii)
-            ((xor_vec ((slice0 t0 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__2  ::  4 Word.word))
+         ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii)
+            ((xor_vec ((slice t0 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__2  ::  4 Word.word))
            ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 ::  4 Word.word) . 
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 ::  4 Word.word) . 
-       (let t1 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) ((xor_vec w__3 w__4  ::  4 Word.word))  ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) (( 2 :: int)::ii)
+       (let t1 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) ((xor_vec w__3 w__4  ::  4 Word.word))  ::  4 Word.word)) in
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) (( 2 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 ::  4 Word.word) . 
        (let t1 =
-         ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii)
-            ((xor_vec ((slice0 t1 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__5  ::  4 Word.word))
+         ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii)
+            ((xor_vec ((slice t1 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__5  ::  4 Word.word))
            ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 2 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 ::  4 Word.word) . 
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__7 ::  4 Word.word) . 
-       (let t2 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) ((xor_vec w__6 w__7  ::  4 Word.word))  ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) (( 1 :: int)::ii)
+       (let t2 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) ((xor_vec w__6 w__7  ::  4 Word.word))  ::  4 Word.word)) in
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__8 ::  4 Word.word) . 
        (let t2 =
-         ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii)
-            ((xor_vec ((slice0 t2 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__8  ::  4 Word.word))
+         ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii)
+            ((xor_vec ((slice t2 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__8  ::  4 Word.word))
            ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__9 ::  4 Word.word) . 
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 2 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__10 ::  4 Word.word) . 
-       (let t3 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) ((xor_vec w__9 w__10  ::  4 Word.word))  ::  4 Word.word)) in
-       (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
+       (let t3 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) ((xor_vec w__9 w__10  ::  4 Word.word))  ::  4 Word.word)) in
+       (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii)  ::  4 Word.word))
           (( 1 :: int)::ii)
          :: ( 4 Word.word) M) \<bind> (\<lambda> (w__11 ::  4 Word.word) . 
        (let (t3 :: 4 bits) =
-         ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii)
-            ((xor_vec ((slice0 t3 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__11  ::  4 Word.word))
+         ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii)
+            ((xor_vec ((slice t3 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) w__11  ::  4 Word.word))
            ::  4 Word.word)) in
        (let (Soutput :: 64 bits) =
-         ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * i))
-            ((slice0 t3 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+         ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * i))
+            ((slice t3 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
            ::  64 Word.word)) in
        (let (Soutput :: 64 bits) =
-         ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii)))))
-            ((slice0 t2 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+         ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii)))))
+            ((slice t2 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
            ::  64 Word.word)) in
        (let (Soutput :: 64 bits) =
-         ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii)))))
-            ((slice0 t1 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+         ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii)))))
+            ((slice t1 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
            ::  64 Word.word)) in
        (let (Soutput :: 64 bits) =
-         ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii)))))
-            ((slice0 t0 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+         ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii)))))
+            ((slice t0 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
            ::  64 Word.word)) in
-       return Soutput))))))))))))))))))))))))))))))))"
+       return (Soutput, t0, t1, t2, t3)))))))))))))))))))))))))))) \<bind> (\<lambda> varstup .  (let ((Soutput :: 64 bits), (t0 :: 4
+     bits), (t1 :: 4 bits), (t2 :: 4 bits), (t3 :: 4 bits)) = varstup in
+   return Soutput))))))))"
 
 
 (*val PACInvSub : mword ty64 -> M (mword ty64)*)
@@ -5186,69 +5210,69 @@ definition PACInvSub  :: "(64)Word.word \<Rightarrow>((register_value),((64)Word
    (let (Toutput :: 64 bits) =
      (foreach (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) Toutput
        (\<lambda> i Toutput . 
-         (let b__0 = ((slice0 Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) in
+         (let b__0 = ((slice Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii)  ::  4 Word.word)) in
          if (((b__0 = (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B0,B1,B1,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B1,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B0,B1,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B1,B0,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B1,B0,B1]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B1,B1,B0,B0]  ::  4 Word.word)
              ::  64 Word.word)
          else if (((b__0 = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) then
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B1,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)
          else
-           (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
+           (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i))
               (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)
              ::  64 Word.word)))) in
    return Toutput)))"
@@ -5281,7 +5305,7 @@ definition ComputePAC  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow
    ((let modk0 =
      ((concat_vec
         ((concat_vec (vec_of_bits [access_vec_dec key0 (( 0 :: int)::ii)]  ::  1 Word.word)
-            ((slice0 key0 (( 2 :: int)::ii) (( 62 :: int)::ii)  ::  62 Word.word))
+            ((slice key0 (( 2 :: int)::ii) (( 62 :: int)::ii)  ::  62 Word.word))
            ::  63 Word.word))
         ((xor_vec (vec_of_bits [access_vec_dec key0 (( 63 :: int)::ii)]  ::  1 Word.word)
             (vec_of_bits [access_vec_dec key0 (( 1 :: int)::ii)]  ::  1 Word.word)
@@ -5302,7 +5326,7 @@ definition ComputePAC  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow
         else return workingval) \<bind> (\<lambda> (workingval :: 64 bits) . 
        (PACSub workingval  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . 
        (let workingval = w__13 in
-       (TweakShuffle ((slice0 runningmod (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64
+       (TweakShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64
          bits) . 
        (let (runningmod :: 64 bits) = w__14 in
        return (roundkey, runningmod, workingval))))))))))))) \<bind> (\<lambda> varstup .  (let ((roundkey :: 64 bits), (runningmod :: 64
@@ -5330,8 +5354,8 @@ definition ComputePAC  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow
    (let workingval = w__23 in
    (let workingval = ((xor_vec workingval key0  ::  64 Word.word)) in
    (let workingval = ((xor_vec workingval runningmod  ::  64 Word.word)) in
-   (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) workingval
-     (\<lambda> i workingval . 
+   (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) (roundkey, runningmod, workingval)
+     (\<lambda> i varstup .  (let (roundkey, runningmod, workingval) = varstup in
        (PACInvSub workingval  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 bits) . 
        (let workingval = w__24 in
        (if ((i < (( 4 :: int)::ii))) then
@@ -5339,7 +5363,7 @@ definition ComputePAC  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow
           (let workingval = w__25 in
           (PACCellInvShuffle workingval  :: ( 64 Word.word) M)))
         else return workingval) \<bind> (\<lambda> (workingval :: 64 bits) . 
-       (TweakInvShuffle ((slice0 runningmod (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64
+       (TweakInvShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64
          bits) . 
        (let runningmod = w__27 in
        (let roundkey = ((xor_vec key1 runningmod  ::  64 Word.word)) in
@@ -5349,9 +5373,10 @@ definition ComputePAC  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow
            ::  64 Word.word)) in
        (let (workingval :: 64 bits) = ((xor_vec workingval roundkey  ::  64 Word.word)) in
        (let (workingval :: 64 bits) = ((xor_vec workingval Alpha  ::  64 Word.word)) in
-       return workingval)))))))))))) \<bind> (\<lambda> (workingval :: 64 bits) . 
+       return (roundkey, runningmod, workingval)))))))))))))) \<bind> (\<lambda> varstup .  (let ((roundkey :: 64 bits), (runningmod :: 64
+     bits), (workingval :: 64 bits)) = varstup in
    (let (workingval :: 64 bits) = ((xor_vec workingval modk0  ::  64 Word.word)) in
-   return workingval)))))))))))))))))))))))))))))))))))))))))))))))"
+   return workingval))))))))))))))))))))))))))))))))))))))))))))))))"
 
 
 (*val Align__0 : ii -> ii -> ii*)
@@ -5378,12 +5403,12 @@ definition aset__Mem  :: " AddressDescriptor \<Rightarrow> int \<Rightarrow> Acc
    (hex_slice (''0x13000000'') (( 52 :: int)::ii) (( 0 :: int)::ii)  :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 ::  52 Word.word) . 
    if (((address = w__0))) then
      if (((((Word.uint value_name)) = (( 4 :: int)::ii)))) then
-       (let (_ :: unit) = (prerr_endline ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (char_of_nat 10)])) in
+       (let (_ :: unit) = (prerr ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (char_of_nat 10)])) in
        exit0 () )
-     else return ((putchar ((Word.uint ((slice0 value_name (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))))))
+     else return ((putchar ((Word.uint ((slice value_name (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))))))
    else
      (read_reg Memory_ref  :: ( 52 Word.word) M) \<bind> (\<lambda> (w__1 ::  52 Word.word) . 
-     write_ram (( 52 :: int)::ii) size1 w__1 address value_name)))))"
+     WriteRAM ((make_the_value (( 52 :: int)::ii)  ::  52 itself)) size1 w__1 address value_name)))))"
 
 
 (*val aget__Mem : forall   'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> M (mword 'p8_times_size_)*)
@@ -5394,7 +5419,8 @@ definition aget__Mem  :: " AddressDescriptor \<Rightarrow> int \<Rightarrow> Acc
    ((let (address :: 52 bits) = ((FullAddress_physicaladdress  (AddressDescriptor_paddress   desc))) in
    (assert_exp (((address = ((Align__1 address size1  ::  52 Word.word))))) (''(address == Align(address, size))'') \<then>
    (read_reg Memory_ref  :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 ::  52 Word.word) . 
-   (read_ram (( 52 :: int)::ii) size1 w__0 address  :: (( 'p8_times_size_::len)Word.word) M)))))"
+   (ReadRAM ((make_the_value (( 52 :: int)::ii)  ::  52 itself)) size1 w__0 address
+     :: (( 'p8_times_size_::len)Word.word) M)))))"
 
 
 (*val aset_X : forall 'width . Size 'width => ii -> mword 'width -> M unit*)
@@ -5418,7 +5444,7 @@ definition aarch64_integer_arithmetic_address_pcrel  :: " int \<Rightarrow>(64)W
    (aget_PC ()   :: ( 64 Word.word) M) \<bind> (\<lambda> (base :: 64 bits) . 
    (let (base :: 64 bits) =
      (if page then
-       (set_slice0 (( 64 :: int)::ii) (( 12 :: int)::ii) base (( 0 :: int)::ii)
+       (set_slice (( 64 :: int)::ii) (( 12 :: int)::ii) base (( 0 :: int)::ii)
           ((Zeros__0 ((make_the_value (( 12 :: int)::ii)  ::  12 itself))  ::  12 Word.word))
          ::  64 Word.word)
      else base) in
@@ -5484,7 +5510,7 @@ definition aget_X  :: " int \<Rightarrow> int \<Rightarrow>((register_value),(('
    assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \<or> ((((((width__tv = (( 16 :: int)::ii)))) \<or> ((((((width__tv = (( 32 :: int)::ii)))) \<or> (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'')) \<then>
    (if (((n \<noteq> (( 31 :: int)::ii)))) then
      read_reg R_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . 
-     return ((slice0 ((access_list_dec w__0 n  ::  64 Word.word)) (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
+     return ((slice ((access_list_dec w__0 n  ::  64 Word.word)) (( 0 :: int)::ii) width__tv  :: ( 'width::len)Word.word)))
    else return ((Zeros__0 ((make_the_value width__tv  :: ( 'width::len)itself))  :: ( 'width::len)Word.word))))"
 
 
@@ -5517,8 +5543,8 @@ definition aarch64_system_register_system  :: " bool \<Rightarrow> int \<Rightar
 (*val aarch64_integer_insext_insert_movewide : ii -> ii -> mword ty16 -> MoveWideOp -> ii -> M unit*)
 
 definition aarch64_integer_insext_insert_movewide  :: " int \<Rightarrow> int \<Rightarrow>(16)Word.word \<Rightarrow> MoveWideOp \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_insext_insert_movewide d l__276 imm opcode pos = (
-   if (((l__276 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_insext_insert_movewide d l__267 imm opcode pos = (
+   if (((l__267 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5527,12 +5553,12 @@ definition aarch64_integer_insext_insert_movewide  :: " int \<Rightarrow> int \<
       else
         (let (result :: 8 bits) = ((Zeros__1 (( 8 :: int)::ii) ()   ::  8 Word.word)) in
         return result)) \<bind> (\<lambda> (result :: 8 bits) . 
-     (let result = ((set_slice0 (( 8 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  8 Word.word)) in
+     (let result = ((set_slice (( 8 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  8 Word.word)) in
      (let (result :: 8 bits) =
        (if (((opcode = MoveWideOp_N))) then (not_vec result  ::  8 Word.word)
        else result) in
      aset_X d result)))))
-   else if (((l__276 = (( 16 :: int)::ii)))) then
+   else if (((l__267 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5541,12 +5567,12 @@ definition aarch64_integer_insext_insert_movewide  :: " int \<Rightarrow> int \<
       else
         (let (result :: 16 bits) = ((Zeros__1 (( 16 :: int)::ii) ()   ::  16 Word.word)) in
         return result)) \<bind> (\<lambda> (result :: 16 bits) . 
-     (let result = ((set_slice0 (( 16 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  16 Word.word)) in
+     (let result = ((set_slice (( 16 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  16 Word.word)) in
      (let (result :: 16 bits) =
        (if (((opcode = MoveWideOp_N))) then (not_vec result  ::  16 Word.word)
        else result) in
      aset_X d result)))))
-   else if (((l__276 = (( 32 :: int)::ii)))) then
+   else if (((l__267 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5555,12 +5581,12 @@ definition aarch64_integer_insext_insert_movewide  :: " int \<Rightarrow> int \<
       else
         (let (result :: 32 bits) = ((Zeros__1 (( 32 :: int)::ii) ()   ::  32 Word.word)) in
         return result)) \<bind> (\<lambda> (result :: 32 bits) . 
-     (let result = ((set_slice0 (( 32 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  32 Word.word)) in
+     (let result = ((set_slice (( 32 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  32 Word.word)) in
      (let (result :: 32 bits) =
        (if (((opcode = MoveWideOp_N))) then (not_vec result  ::  32 Word.word)
        else result) in
      aset_X d result)))))
-   else if (((l__276 = (( 64 :: int)::ii)))) then
+   else if (((l__267 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5569,12 +5595,12 @@ definition aarch64_integer_insext_insert_movewide  :: " int \<Rightarrow> int \<
       else
         (let (result :: 64 bits) = ((Zeros__1 (( 64 :: int)::ii) ()   ::  64 Word.word)) in
         return result)) \<bind> (\<lambda> (result :: 64 bits) . 
-     (let result = ((set_slice0 (( 64 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  64 Word.word)) in
+     (let result = ((set_slice (( 64 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  64 Word.word)) in
      (let (result :: 64 bits) =
        (if (((opcode = MoveWideOp_N))) then (not_vec result  ::  64 Word.word)
        else result) in
      aset_X d result)))))
-   else if (((l__276 = (( 128 :: int)::ii)))) then
+   else if (((l__267 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5583,21 +5609,21 @@ definition aarch64_integer_insext_insert_movewide  :: " int \<Rightarrow> int \<
       else
         (let (result :: 128 bits) = ((Zeros__1 (( 128 :: int)::ii) ()   ::  128 Word.word)) in
         return result)) \<bind> (\<lambda> (result :: 128 bits) . 
-     (let result = ((set_slice0 (( 128 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  128 Word.word)) in
+     (let result = ((set_slice (( 128 :: int)::ii) (( 16 :: int)::ii) result pos imm  ::  128 Word.word)) in
      (let (result :: 128 bits) =
        (if (((opcode = MoveWideOp_N))) then (not_vec result  ::  128 Word.word)
        else result) in
      aset_X d result)))))
    else
-     (let dbytes = (ex_int ((l__276 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__267 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
 (*val aarch64_integer_insext_extract_immediate : ii -> ii -> ii -> ii -> ii -> M unit*)
 
 definition aarch64_integer_insext_extract_immediate  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_insext_extract_immediate d l__271 lsb1 m n = (
-   if (((l__271 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_insext_extract_immediate d l__262 lsb1 m n = (
+   if (((l__262 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5605,9 +5631,9 @@ definition aarch64_integer_insext_extract_immediate  :: " int \<Rightarrow> int
      (aget_X (( 8 :: int)::ii) n  :: ( 8 Word.word) M) \<bind> (\<lambda> (operand1 :: 8 bits) . 
      (aget_X (( 8 :: int)::ii) m  :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . 
      (let (concat1 :: 16 bits) = ((concat_vec operand1 operand2  ::  16 Word.word)) in
-     (let result = ((slice0 concat1 lsb1 (( 8 :: int)::ii)  ::  8 Word.word)) in
+     (let result = ((slice concat1 lsb1 (( 8 :: int)::ii)  ::  8 Word.word)) in
      aset_X d result))))))
-   else if (((l__271 = (( 16 :: int)::ii)))) then
+   else if (((l__262 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5615,9 +5641,9 @@ definition aarch64_integer_insext_extract_immediate  :: " int \<Rightarrow> int
      (aget_X (( 16 :: int)::ii) n  :: ( 16 Word.word) M) \<bind> (\<lambda> (operand1 :: 16 bits) . 
      (aget_X (( 16 :: int)::ii) m  :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . 
      (let (concat1 :: 32 bits) = ((concat_vec operand1 operand2  ::  32 Word.word)) in
-     (let result = ((slice0 concat1 lsb1 (( 16 :: int)::ii)  ::  16 Word.word)) in
+     (let result = ((slice concat1 lsb1 (( 16 :: int)::ii)  ::  16 Word.word)) in
      aset_X d result))))))
-   else if (((l__271 = (( 32 :: int)::ii)))) then
+   else if (((l__262 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5625,9 +5651,9 @@ definition aarch64_integer_insext_extract_immediate  :: " int \<Rightarrow> int
      (aget_X (( 32 :: int)::ii) n  :: ( 32 Word.word) M) \<bind> (\<lambda> (operand1 :: 32 bits) . 
      (aget_X (( 32 :: int)::ii) m  :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . 
      (let (concat1 :: 64 bits) = ((concat_vec operand1 operand2  ::  64 Word.word)) in
-     (let result = ((slice0 concat1 lsb1 (( 32 :: int)::ii)  ::  32 Word.word)) in
+     (let result = ((slice concat1 lsb1 (( 32 :: int)::ii)  ::  32 Word.word)) in
      aset_X d result))))))
-   else if (((l__271 = (( 64 :: int)::ii)))) then
+   else if (((l__262 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5635,9 +5661,9 @@ definition aarch64_integer_insext_extract_immediate  :: " int \<Rightarrow> int
      (aget_X (( 64 :: int)::ii) n  :: ( 64 Word.word) M) \<bind> (\<lambda> (operand1 :: 64 bits) . 
      (aget_X (( 64 :: int)::ii) m  :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . 
      (let (concat1 :: 128 bits) = ((concat_vec operand1 operand2  ::  128 Word.word)) in
-     (let result = ((slice0 concat1 lsb1 (( 64 :: int)::ii)  ::  64 Word.word)) in
+     (let result = ((slice concat1 lsb1 (( 64 :: int)::ii)  ::  64 Word.word)) in
      aset_X d result))))))
-   else if (((l__271 = (( 128 :: int)::ii)))) then
+   else if (((l__262 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5645,18 +5671,18 @@ definition aarch64_integer_insext_extract_immediate  :: " int \<Rightarrow> int
      (aget_X (( 128 :: int)::ii) n  :: ( 128 Word.word) M) \<bind> (\<lambda> (operand1 :: 128 bits) . 
      (aget_X (( 128 :: int)::ii) m  :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . 
      (let (concat1 :: 256 bits) = ((concat_vec operand1 operand2  ::  256 Word.word)) in
-     (let result = ((slice0 concat1 lsb1 (( 128 :: int)::ii)  ::  128 Word.word)) in
+     (let result = ((slice concat1 lsb1 (( 128 :: int)::ii)  ::  128 Word.word)) in
      aset_X d result))))))
    else
-     (let dbytes = (ex_int ((l__271 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__262 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
 (*val aarch64_integer_arithmetic_rev : ii -> ii -> ii -> ii -> M unit*)
 
 definition aarch64_integer_arithmetic_rev  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_rev container_size d l__266 n = (
-   if (((l__266 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_rev container_size d l__257 n = (
+   if (((l__257 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5666,23 +5692,29 @@ definition aarch64_integer_arithmetic_rev  :: " int \<Rightarrow> int \<Rightarr
      (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in
      (let (index1 :: ii) = ((( 0 :: int)::ii)) in
      undefined_int ()  \<bind> (\<lambda> (rev_index :: ii) . 
-     (let (result :: 8 bits) =
-       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-         (\<lambda> c result . 
+     (let ((index1 :: ii), (result :: 8 bits), (rev_index :: ii)) =
+       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                          result,
+                                                                                          rev_index)
+         (\<lambda> c varstup .  (let (index1, result, rev_index) = varstup in
            (let (rev_index :: ii) =
              (((ex_int index1)) +
                ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in
-           (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-             (\<lambda> e result . 
-               (let (result :: 8 bits) =
-                 ((set_slice0 (( 8 :: int)::ii) (( 8 :: int)::ii) result rev_index
-                    ((slice0 operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
-                   ::  8 Word.word)) in
-               (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
-               (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
-               result)))))))) in
+           (let ((index1 :: ii), (result :: 8 bits), (rev_index :: ii)) =
+             (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\<lambda> e varstup .  (let (index1, result, rev_index) = varstup in
+                 (let (result :: 8 bits) =
+                   ((set_slice (( 8 :: int)::ii) (( 8 :: int)::ii) result rev_index
+                      ((slice operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
+                     ::  8 Word.word)) in
+                 (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
+                 (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
+                 (index1, result, rev_index))))))) in
+           (index1, result, rev_index)))))) in
      aset_X d result))))))))
-   else if (((l__266 = (( 16 :: int)::ii)))) then
+   else if (((l__257 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5692,23 +5724,29 @@ definition aarch64_integer_arithmetic_rev  :: " int \<Rightarrow> int \<Rightarr
      (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in
      (let (index1 :: ii) = ((( 0 :: int)::ii)) in
      undefined_int ()  \<bind> (\<lambda> (rev_index :: ii) . 
-     (let (result :: 16 bits) =
-       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-         (\<lambda> c result . 
+     (let ((index1 :: ii), (result :: 16 bits), (rev_index :: ii)) =
+       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                          result,
+                                                                                          rev_index)
+         (\<lambda> c varstup .  (let (index1, result, rev_index) = varstup in
            (let (rev_index :: ii) =
              (((ex_int index1)) +
                ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in
-           (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-             (\<lambda> e result . 
-               (let (result :: 16 bits) =
-                 ((set_slice0 (( 16 :: int)::ii) (( 8 :: int)::ii) result rev_index
-                    ((slice0 operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
-                   ::  16 Word.word)) in
-               (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
-               (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
-               result)))))))) in
+           (let ((index1 :: ii), (result :: 16 bits), (rev_index :: ii)) =
+             (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\<lambda> e varstup .  (let (index1, result, rev_index) = varstup in
+                 (let (result :: 16 bits) =
+                   ((set_slice (( 16 :: int)::ii) (( 8 :: int)::ii) result rev_index
+                      ((slice operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
+                     ::  16 Word.word)) in
+                 (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
+                 (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
+                 (index1, result, rev_index))))))) in
+           (index1, result, rev_index)))))) in
      aset_X d result))))))))
-   else if (((l__266 = (( 32 :: int)::ii)))) then
+   else if (((l__257 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5718,23 +5756,29 @@ definition aarch64_integer_arithmetic_rev  :: " int \<Rightarrow> int \<Rightarr
      (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in
      (let (index1 :: ii) = ((( 0 :: int)::ii)) in
      undefined_int ()  \<bind> (\<lambda> (rev_index :: ii) . 
-     (let (result :: 32 bits) =
-       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-         (\<lambda> c result . 
+     (let ((index1 :: ii), (result :: 32 bits), (rev_index :: ii)) =
+       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                          result,
+                                                                                          rev_index)
+         (\<lambda> c varstup .  (let (index1, result, rev_index) = varstup in
            (let (rev_index :: ii) =
              (((ex_int index1)) +
                ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in
-           (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-             (\<lambda> e result . 
-               (let (result :: 32 bits) =
-                 ((set_slice0 (( 32 :: int)::ii) (( 8 :: int)::ii) result rev_index
-                    ((slice0 operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
-                   ::  32 Word.word)) in
-               (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
-               (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
-               result)))))))) in
+           (let ((index1 :: ii), (result :: 32 bits), (rev_index :: ii)) =
+             (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\<lambda> e varstup .  (let (index1, result, rev_index) = varstup in
+                 (let (result :: 32 bits) =
+                   ((set_slice (( 32 :: int)::ii) (( 8 :: int)::ii) result rev_index
+                      ((slice operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
+                     ::  32 Word.word)) in
+                 (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
+                 (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
+                 (index1, result, rev_index))))))) in
+           (index1, result, rev_index)))))) in
      aset_X d result))))))))
-   else if (((l__266 = (( 64 :: int)::ii)))) then
+   else if (((l__257 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5744,23 +5788,29 @@ definition aarch64_integer_arithmetic_rev  :: " int \<Rightarrow> int \<Rightarr
      (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in
      (let (index1 :: ii) = ((( 0 :: int)::ii)) in
      undefined_int ()  \<bind> (\<lambda> (rev_index :: ii) . 
-     (let (result :: 64 bits) =
-       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-         (\<lambda> c result . 
+     (let ((index1 :: ii), (result :: 64 bits), (rev_index :: ii)) =
+       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                          result,
+                                                                                          rev_index)
+         (\<lambda> c varstup .  (let (index1, result, rev_index) = varstup in
            (let (rev_index :: ii) =
              (((ex_int index1)) +
                ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in
-           (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-             (\<lambda> e result . 
-               (let (result :: 64 bits) =
-                 ((set_slice0 (( 64 :: int)::ii) (( 8 :: int)::ii) result rev_index
-                    ((slice0 operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
-                   ::  64 Word.word)) in
-               (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
-               (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
-               result)))))))) in
+           (let ((index1 :: ii), (result :: 64 bits), (rev_index :: ii)) =
+             (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\<lambda> e varstup .  (let (index1, result, rev_index) = varstup in
+                 (let (result :: 64 bits) =
+                   ((set_slice (( 64 :: int)::ii) (( 8 :: int)::ii) result rev_index
+                      ((slice operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
+                     ::  64 Word.word)) in
+                 (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
+                 (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
+                 (index1, result, rev_index))))))) in
+           (index1, result, rev_index)))))) in
      aset_X d result))))))))
-   else if (((l__266 = (( 128 :: int)::ii)))) then
+   else if (((l__257 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5770,32 +5820,38 @@ definition aarch64_integer_arithmetic_rev  :: " int \<Rightarrow> int \<Rightarr
      (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in
      (let (index1 :: ii) = ((( 0 :: int)::ii)) in
      undefined_int ()  \<bind> (\<lambda> (rev_index :: ii) . 
-     (let (result :: 128 bits) =
-       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-         (\<lambda> c result . 
+     (let ((index1 :: ii), (result :: 128 bits), (rev_index :: ii)) =
+       (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                          result,
+                                                                                          rev_index)
+         (\<lambda> c varstup .  (let (index1, result, rev_index) = varstup in
            (let (rev_index :: ii) =
              (((ex_int index1)) +
                ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in
-           (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
-             (\<lambda> e result . 
-               (let (result :: 128 bits) =
-                 ((set_slice0 (( 128 :: int)::ii) (( 8 :: int)::ii) result rev_index
-                    ((slice0 operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
-                   ::  128 Word.word)) in
-               (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
-               (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
-               result)))))))) in
+           (let ((index1 :: ii), (result :: 128 bits), (rev_index :: ii)) =
+             (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1,
+                                                                                                            result,
+                                                                                                            rev_index)
+               (\<lambda> e varstup .  (let (index1, result, rev_index) = varstup in
+                 (let (result :: 128 bits) =
+                   ((set_slice (( 128 :: int)::ii) (( 8 :: int)::ii) result rev_index
+                      ((slice operand index1 (( 8 :: int)::ii)  ::  8 Word.word))
+                     ::  128 Word.word)) in
+                 (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in
+                 (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in
+                 (index1, result, rev_index))))))) in
+           (index1, result, rev_index)))))) in
      aset_X d result))))))))
    else
-     (let dbytes = (ex_int ((l__266 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__257 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
 (*val aarch64_integer_arithmetic_rbit : ii -> ii -> ii -> M unit*)
 
 definition aarch64_integer_arithmetic_rbit  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_rbit d l__261 n = (
-   if (((l__261 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_rbit d l__252 n = (
+   if (((l__252 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5804,11 +5860,11 @@ definition aarch64_integer_arithmetic_rbit  :: " int \<Rightarrow> int \<Rightar
      (let (result :: 8 bits) =
        (foreach (index_list (( 0 :: int)::ii) (((( 8 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
          (\<lambda> i result . 
-           (set_slice0 (( 8 :: int)::ii) (( 1 :: int)::ii) result (((((( 8 :: int)::ii) - (( 1 :: int)::ii))) - i))
+           (set_slice (( 8 :: int)::ii) (( 1 :: int)::ii) result (((((( 8 :: int)::ii) - (( 1 :: int)::ii))) - i))
               (vec_of_bits [access_vec_dec operand i]  ::  1 Word.word)
              ::  8 Word.word))) in
      aset_X d result))))
-   else if (((l__261 = (( 16 :: int)::ii)))) then
+   else if (((l__252 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5817,11 +5873,11 @@ definition aarch64_integer_arithmetic_rbit  :: " int \<Rightarrow> int \<Rightar
      (let (result :: 16 bits) =
        (foreach (index_list (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
          (\<lambda> i result . 
-           (set_slice0 (( 16 :: int)::ii) (( 1 :: int)::ii) result (((((( 16 :: int)::ii) - (( 1 :: int)::ii))) - i))
+           (set_slice (( 16 :: int)::ii) (( 1 :: int)::ii) result (((((( 16 :: int)::ii) - (( 1 :: int)::ii))) - i))
               (vec_of_bits [access_vec_dec operand i]  ::  1 Word.word)
              ::  16 Word.word))) in
      aset_X d result))))
-   else if (((l__261 = (( 32 :: int)::ii)))) then
+   else if (((l__252 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5830,11 +5886,11 @@ definition aarch64_integer_arithmetic_rbit  :: " int \<Rightarrow> int \<Rightar
      (let (result :: 32 bits) =
        (foreach (index_list (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
          (\<lambda> i result . 
-           (set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) result (((((( 32 :: int)::ii) - (( 1 :: int)::ii))) - i))
+           (set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) result (((((( 32 :: int)::ii) - (( 1 :: int)::ii))) - i))
               (vec_of_bits [access_vec_dec operand i]  ::  1 Word.word)
              ::  32 Word.word))) in
      aset_X d result))))
-   else if (((l__261 = (( 64 :: int)::ii)))) then
+   else if (((l__252 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5843,11 +5899,11 @@ definition aarch64_integer_arithmetic_rbit  :: " int \<Rightarrow> int \<Rightar
      (let (result :: 64 bits) =
        (foreach (index_list (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
          (\<lambda> i result . 
-           (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) result (((((( 64 :: int)::ii) - (( 1 :: int)::ii))) - i))
+           (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) result (((((( 64 :: int)::ii) - (( 1 :: int)::ii))) - i))
               (vec_of_bits [access_vec_dec operand i]  ::  1 Word.word)
              ::  64 Word.word))) in
      aset_X d result))))
-   else if (((l__261 = (( 128 :: int)::ii)))) then
+   else if (((l__252 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5856,12 +5912,12 @@ definition aarch64_integer_arithmetic_rbit  :: " int \<Rightarrow> int \<Rightar
      (let (result :: 128 bits) =
        (foreach (index_list (( 0 :: int)::ii) (((( 128 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result
          (\<lambda> i result . 
-           (set_slice0 (( 128 :: int)::ii) (( 1 :: int)::ii) result (((((( 128 :: int)::ii) - (( 1 :: int)::ii))) - i))
+           (set_slice (( 128 :: int)::ii) (( 1 :: int)::ii) result (((((( 128 :: int)::ii) - (( 1 :: int)::ii))) - i))
               (vec_of_bits [access_vec_dec operand i]  ::  1 Word.word)
              ::  128 Word.word))) in
      aset_X d result))))
    else
-     (let dbytes = (ex_int ((l__261 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__252 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -5881,8 +5937,8 @@ definition integer_arithmetic_rbit_decode  :: "(1)Word.word \<Rightarrow>(1)Word
 (*val aarch64_integer_arithmetic_mul_widening_64128hi : ii -> ii -> ii -> ii -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_mul_widening_64128hi  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_mul_widening_64128hi d l__256 m n unsigned = (
-   if (((l__256 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_mul_widening_64128hi d l__247 m n unsigned = (
+   if (((l__247 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5892,7 +5948,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi  :: " int \<Rightarro
        (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 64 :: int)::ii)  ::  64 Word.word))))))
-   else if (((l__256 = (( 16 :: int)::ii)))) then
+   else if (((l__247 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5902,7 +5958,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi  :: " int \<Rightarro
        (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 64 :: int)::ii)  ::  64 Word.word))))))
-   else if (((l__256 = (( 32 :: int)::ii)))) then
+   else if (((l__247 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5912,7 +5968,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi  :: " int \<Rightarro
        (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 64 :: int)::ii)  ::  64 Word.word))))))
-   else if (((l__256 = (( 64 :: int)::ii)))) then
+   else if (((l__247 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5922,7 +5978,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi  :: " int \<Rightarro
        (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 64 :: int)::ii)  ::  64 Word.word))))))
-   else if (((l__256 = (( 128 :: int)::ii)))) then
+   else if (((l__247 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -5933,7 +5989,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi  :: " int \<Rightarro
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 64 :: int)::ii)  ::  64 Word.word))))))
    else
-     (let dbytes = (ex_int ((l__256 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__247 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -5955,8 +6011,8 @@ definition integer_arithmetic_mul_widening_64128hi_decode  :: "(1)Word.word \<Ri
 (*val aarch64_integer_arithmetic_mul_widening_3264 : ii -> ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_mul_widening_3264 a d l__229 l__230 m n sub_op unsigned = (
-   if ((((((l__229 = (( 8 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then
+     " aarch64_integer_arithmetic_mul_widening_3264 a d l__220 l__221 m n sub_op unsigned = (
+   if ((((((l__220 = (( 8 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -5976,7 +6032,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if ((((((l__229 = (( 8 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__220 = (( 8 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -5996,8 +6052,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__229 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__229 = (( 16 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then
+   else if (((l__220 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__220 = (( 16 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6017,7 +6073,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if ((((((l__229 = (( 16 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__220 = (( 16 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6037,8 +6093,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__229 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__229 = (( 32 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then
+   else if (((l__220 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__220 = (( 32 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6058,7 +6114,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if ((((((l__229 = (( 32 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__220 = (( 32 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6078,8 +6134,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__229 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__229 = (( 64 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then
+   else if (((l__220 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__220 = (( 64 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6099,7 +6155,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if ((((((l__229 = (( 64 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__220 = (( 64 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6119,8 +6175,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__229 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__229 = (( 128 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then
+   else if (((l__220 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__220 = (( 128 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6140,7 +6196,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if ((((((l__229 = (( 128 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__220 = (( 128 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6160,14 +6216,14 @@ definition aarch64_integer_arithmetic_mul_widening_3264  :: " int \<Rightarrow>
                ((ex_int ((asl_Int operand2 unsigned))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__229 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if (((l__230 = (( 32 :: int)::ii)))) then
+   else if (((l__220 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if (((l__221 = (( 32 :: int)::ii)))) then
      assert_exp True (''destsize constraint'') \<then>
-     ((let dbytes = (ex_int ((l__229 div (( 8 :: int)::ii)))) in
+     ((let dbytes = (ex_int ((l__220 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))
-   else if (((l__230 = (( 64 :: int)::ii)))) then
+   else if (((l__221 = (( 64 :: int)::ii)))) then
      assert_exp True (''destsize constraint'') \<then>
-     ((let dbytes = (ex_int ((l__229 div (( 8 :: int)::ii)))) in
+     ((let dbytes = (ex_int ((l__220 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))
    else assert_exp True (''destsize constraint''))"
 
@@ -6191,8 +6247,8 @@ definition integer_arithmetic_mul_widening_3264_decode  :: "(1)Word.word \<Right
 (*val aarch64_integer_arithmetic_mul_uniform_addsub : ii -> ii -> ii -> ii -> ii -> ii -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_mul_uniform_addsub a d l__202 l__203 m n sub_op = (
-   if ((((((l__202 = (( 8 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then
+     " aarch64_integer_arithmetic_mul_uniform_addsub a d l__193 l__194 m n sub_op = (
+   if ((((((l__193 = (( 8 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6207,7 +6263,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word)))))))))
-   else if ((((((l__202 = (( 8 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__193 = (( 8 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6222,8 +6278,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__202 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__202 = (( 16 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then
+   else if (((l__193 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__193 = (( 16 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6238,7 +6294,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word)))))))))
-   else if ((((((l__202 = (( 16 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__193 = (( 16 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6253,8 +6309,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__202 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__202 = (( 32 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then
+   else if (((l__193 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__193 = (( 32 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6269,7 +6325,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word)))))))))
-   else if ((((((l__202 = (( 32 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__193 = (( 32 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6284,8 +6340,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__202 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__202 = (( 64 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then
+   else if (((l__193 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__193 = (( 64 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6300,7 +6356,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word)))))))))
-   else if ((((((l__202 = (( 64 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__193 = (( 64 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6315,8 +6371,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__202 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if ((((((l__202 = (( 128 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then
+   else if (((l__193 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if ((((((l__193 = (( 128 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6331,7 +6387,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word)))))))))
-   else if ((((((l__202 = (( 128 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then
+   else if ((((((l__193 = (( 128 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then
      assert_exp True (''destsize constraint'') \<then>
      ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
@@ -6346,14 +6402,14 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub  :: " int \<Rightarrow>
        else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))))
-   else if (((l__202 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'')
-   else if (((l__203 = (( 32 :: int)::ii)))) then
+   else if (((l__193 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'')
+   else if (((l__194 = (( 32 :: int)::ii)))) then
      assert_exp True (''destsize constraint'') \<then>
-     ((let dbytes = (ex_int ((l__202 div (( 8 :: int)::ii)))) in
+     ((let dbytes = (ex_int ((l__193 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))
-   else if (((l__203 = (( 64 :: int)::ii)))) then
+   else if (((l__194 = (( 64 :: int)::ii)))) then
      assert_exp True (''destsize constraint'') \<then>
-     ((let dbytes = (ex_int ((l__202 div (( 8 :: int)::ii)))) in
+     ((let dbytes = (ex_int ((l__193 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))
    else assert_exp True (''destsize constraint''))"
 
@@ -6378,8 +6434,8 @@ definition integer_arithmetic_mul_uniform_addsub_decode  :: "(1)Word.word \<Righ
 (*val aarch64_integer_arithmetic_div : ii -> ii -> ii -> ii -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_div  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_div d l__197 m n unsigned = (
-   if (((l__197 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_div d l__188 m n unsigned = (
+   if (((l__188 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6393,7 +6449,7 @@ definition aarch64_integer_arithmetic_div  :: " int \<Rightarrow> int \<Rightarr
            (((((real_of_int ((asl_Int operand1 unsigned))))) div
                (((real_of_int ((asl_Int operand2 unsigned)))))))) in
      aset_X d ((GetSlice_int ((make_the_value (( 8 :: int)::ii)  ::  8 itself)) result (( 0 :: int)::ii)  ::  8 Word.word)))))))
-   else if (((l__197 = (( 16 :: int)::ii)))) then
+   else if (((l__188 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6408,7 +6464,7 @@ definition aarch64_integer_arithmetic_div  :: " int \<Rightarrow> int \<Rightarr
                (((real_of_int ((asl_Int operand2 unsigned)))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 16 :: int)::ii)  ::  16 itself)) result (( 0 :: int)::ii)  ::  16 Word.word)))))))
-   else if (((l__197 = (( 32 :: int)::ii)))) then
+   else if (((l__188 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6423,7 +6479,7 @@ definition aarch64_integer_arithmetic_div  :: " int \<Rightarrow> int \<Rightarr
                (((real_of_int ((asl_Int operand2 unsigned)))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word)))))))
-   else if (((l__197 = (( 64 :: int)::ii)))) then
+   else if (((l__188 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6438,7 +6494,7 @@ definition aarch64_integer_arithmetic_div  :: " int \<Rightarrow> int \<Rightarr
                (((real_of_int ((asl_Int operand2 unsigned)))))))) in
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word)))))))
-   else if (((l__197 = (( 128 :: int)::ii)))) then
+   else if (((l__188 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6454,7 +6510,7 @@ definition aarch64_integer_arithmetic_div  :: " int \<Rightarrow> int \<Rightarr
      aset_X d
        ((GetSlice_int ((make_the_value (( 128 :: int)::ii)  ::  128 itself)) result (( 0 :: int)::ii)  ::  128 Word.word)))))))
    else
-     (let dbytes = (ex_int ((l__197 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__188 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -6476,8 +6532,8 @@ definition integer_arithmetic_div_decode  :: "(1)Word.word \<Rightarrow>(1)Word.
 (*val aarch64_integer_arithmetic_cnt : ii -> ii -> ii -> CountOp -> M unit*)
 
 definition aarch64_integer_arithmetic_cnt  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> CountOp \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_cnt d l__192 n opcode = (
-   if (((l__192 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_cnt d l__183 n opcode = (
+   if (((l__183 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6486,7 +6542,7 @@ definition aarch64_integer_arithmetic_cnt  :: " int \<Rightarrow> int \<Rightarr
      (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1
       else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . 
      aset_X d ((GetSlice_int ((make_the_value (( 8 :: int)::ii)  ::  8 itself)) result (( 0 :: int)::ii)  ::  8 Word.word))))))
-   else if (((l__192 = (( 16 :: int)::ii)))) then
+   else if (((l__183 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6496,7 +6552,7 @@ definition aarch64_integer_arithmetic_cnt  :: " int \<Rightarrow> int \<Rightarr
       else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . 
      aset_X d
        ((GetSlice_int ((make_the_value (( 16 :: int)::ii)  ::  16 itself)) result (( 0 :: int)::ii)  ::  16 Word.word))))))
-   else if (((l__192 = (( 32 :: int)::ii)))) then
+   else if (((l__183 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6506,7 +6562,7 @@ definition aarch64_integer_arithmetic_cnt  :: " int \<Rightarrow> int \<Rightarr
       else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . 
      aset_X d
        ((GetSlice_int ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) result (( 0 :: int)::ii)  ::  32 Word.word))))))
-   else if (((l__192 = (( 64 :: int)::ii)))) then
+   else if (((l__183 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6516,7 +6572,7 @@ definition aarch64_integer_arithmetic_cnt  :: " int \<Rightarrow> int \<Rightarr
       else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . 
      aset_X d
        ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) result (( 0 :: int)::ii)  ::  64 Word.word))))))
-   else if (((l__192 = (( 128 :: int)::ii)))) then
+   else if (((l__183 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6527,7 +6583,7 @@ definition aarch64_integer_arithmetic_cnt  :: " int \<Rightarrow> int \<Rightarr
      aset_X d
        ((GetSlice_int ((make_the_value (( 128 :: int)::ii)  ::  128 itself)) result (( 0 :: int)::ii)  ::  128 Word.word))))))
    else
-     (let dbytes = (ex_int ((l__192 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__183 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -6550,8 +6606,8 @@ definition integer_arithmetic_cnt_decode  :: "(1)Word.word \<Rightarrow>(1)Word.
 (*val aarch64_integer_arithmetic_addsub_carry : ii -> ii -> ii -> ii -> bool -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_addsub_carry  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_addsub_carry d l__187 m n setflags sub_op = (
-   if (((l__187 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_addsub_carry d l__178 m n setflags sub_op = (
+   if (((l__178 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6581,7 +6637,7 @@ definition aarch64_integer_arithmetic_addsub_carry  :: " int \<Rightarrow> int \
         write_reg PSTATE_ref (w__4 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__187 = (( 16 :: int)::ii)))) then
+   else if (((l__178 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6611,7 +6667,7 @@ definition aarch64_integer_arithmetic_addsub_carry  :: " int \<Rightarrow> int \
         write_reg PSTATE_ref (w__9 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__187 = (( 32 :: int)::ii)))) then
+   else if (((l__178 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6641,7 +6697,7 @@ definition aarch64_integer_arithmetic_addsub_carry  :: " int \<Rightarrow> int \
         write_reg PSTATE_ref (w__14 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__187 = (( 64 :: int)::ii)))) then
+   else if (((l__178 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6671,7 +6727,7 @@ definition aarch64_integer_arithmetic_addsub_carry  :: " int \<Rightarrow> int \
         write_reg PSTATE_ref (w__19 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__187 = (( 128 :: int)::ii)))) then
+   else if (((l__178 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6702,7 +6758,7 @@ definition aarch64_integer_arithmetic_addsub_carry  :: " int \<Rightarrow> int \
       else return () ) \<then>
      aset_X d result))))))))))
    else
-     (let dbytes = (ex_int ((l__187 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__178 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -6859,8 +6915,8 @@ definition ShiftReg  :: " int \<Rightarrow> int \<Rightarrow> ShiftType \<Righta
 (*val aarch64_integer_shift_variable : ii -> ii -> ii -> ii -> ShiftType -> M unit*)
 
 definition aarch64_integer_shift_variable  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_shift_variable d l__182 m n shift_type = (
-   if (((l__182 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_shift_variable d l__173 m n shift_type = (
+   if (((l__173 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6870,7 +6926,7 @@ definition aarch64_integer_shift_variable  :: " int \<Rightarrow> int \<Rightarr
        bits) . 
      (let result = w__0 in
      aset_X d result)))))
-   else if (((l__182 = (( 16 :: int)::ii)))) then
+   else if (((l__173 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6880,7 +6936,7 @@ definition aarch64_integer_shift_variable  :: " int \<Rightarrow> int \<Rightarr
        bits) . 
      (let result = w__1 in
      aset_X d result)))))
-   else if (((l__182 = (( 32 :: int)::ii)))) then
+   else if (((l__173 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6890,7 +6946,7 @@ definition aarch64_integer_shift_variable  :: " int \<Rightarrow> int \<Rightarr
        bits) . 
      (let result = w__2 in
      aset_X d result)))))
-   else if (((l__182 = (( 64 :: int)::ii)))) then
+   else if (((l__173 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6900,7 +6956,7 @@ definition aarch64_integer_shift_variable  :: " int \<Rightarrow> int \<Rightarr
        bits) . 
      (let result = w__3 in
      aset_X d result)))))
-   else if (((l__182 = (( 128 :: int)::ii)))) then
+   else if (((l__173 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6911,7 +6967,7 @@ definition aarch64_integer_shift_variable  :: " int \<Rightarrow> int \<Rightarr
      (let result = w__4 in
      aset_X d result)))))
    else
-     (let dbytes = (ex_int ((l__182 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__173 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -6933,8 +6989,8 @@ definition integer_shift_variable_decode  :: "(1)Word.word \<Rightarrow>(1)Word.
 (*val aarch64_integer_logical_shiftedreg : ii -> ii -> bool -> ii -> ii -> LogicalOp -> bool -> ii -> ShiftType -> M unit*)
 
 definition aarch64_integer_logical_shiftedreg  :: " int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> int \<Rightarrow> LogicalOp \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_logical_shiftedreg d l__177 invert m n op1 setflags shift_amount shift_type = (
-   if (((l__177 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_logical_shiftedreg d l__168 invert m n op1 setflags shift_amount shift_type = (
+   if (((l__168 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -6971,7 +7027,7 @@ definition aarch64_integer_logical_shiftedreg  :: " int \<Rightarrow> int \<Righ
         write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |))))))))
       else return () ) \<then>
      aset_X d result))))))
-   else if (((l__177 = (( 16 :: int)::ii)))) then
+   else if (((l__168 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7008,7 +7064,7 @@ definition aarch64_integer_logical_shiftedreg  :: " int \<Rightarrow> int \<Righ
         write_reg PSTATE_ref (w__7 (| ProcState_V := tup__3 |))))))))
       else return () ) \<then>
      aset_X d result))))))
-   else if (((l__177 = (( 32 :: int)::ii)))) then
+   else if (((l__168 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7045,7 +7101,7 @@ definition aarch64_integer_logical_shiftedreg  :: " int \<Rightarrow> int \<Righ
         write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |))))))))
       else return () ) \<then>
      aset_X d result))))))
-   else if (((l__177 = (( 64 :: int)::ii)))) then
+   else if (((l__168 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7082,7 +7138,7 @@ definition aarch64_integer_logical_shiftedreg  :: " int \<Rightarrow> int \<Righ
         write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |))))))))
       else return () ) \<then>
      aset_X d result))))))
-   else if (((l__177 = (( 128 :: int)::ii)))) then
+   else if (((l__168 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7120,15 +7176,15 @@ definition aarch64_integer_logical_shiftedreg  :: " int \<Rightarrow> int \<Righ
       else return () ) \<then>
      aset_X d result))))))
    else
-     (let dbytes = (ex_int ((l__177 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__168 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
 (*val aarch64_integer_arithmetic_addsub_shiftedreg : ii -> ii -> ii -> ii -> bool -> ii -> ShiftType -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_addsub_shiftedreg  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_addsub_shiftedreg d l__172 m n setflags shift_amount shift_type sub_op = (
-   if (((l__172 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_addsub_shiftedreg d l__163 m n setflags shift_amount shift_type sub_op = (
+   if (((l__163 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7164,7 +7220,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg  :: " int \<Rightarrow>
         write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__172 = (( 16 :: int)::ii)))) then
+   else if (((l__163 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7200,7 +7256,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg  :: " int \<Rightarrow>
         write_reg PSTATE_ref (w__7 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__172 = (( 32 :: int)::ii)))) then
+   else if (((l__163 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7236,7 +7292,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg  :: " int \<Rightarrow>
         write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__172 = (( 64 :: int)::ii)))) then
+   else if (((l__163 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7272,7 +7328,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg  :: " int \<Rightarrow>
         write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |)))))))
       else return () ) \<then>
      aset_X d result))))))))))
-   else if (((l__172 = (( 128 :: int)::ii)))) then
+   else if (((l__163 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7309,7 +7365,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg  :: " int \<Rightarrow>
       else return () ) \<then>
      aset_X d result))))))))))
    else
-     (let dbytes = (ex_int ((l__172 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__163 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -7320,13 +7376,13 @@ definition Prefetch  :: "(64)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((
    undefined_PrefetchHint ()  \<bind> (\<lambda> (hint :: PrefetchHint) . 
    undefined_int ()  \<bind> (\<lambda> (target :: ii) . 
    undefined_bool ()  \<bind> (\<lambda> (stream :: bool) . 
-   (let b__0 = ((slice0 prfop (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+   (let b__0 = ((slice prfop (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
    (let (hint :: PrefetchHint) =
      (if (((b__0 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then Prefetch_READ
      else if (((b__0 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then Prefetch_EXEC
      else if (((b__0 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then Prefetch_WRITE
      else hint) in
-   (let (target :: ii) = (Word.uint ((slice0 prfop (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
+   (let (target :: ii) = (Word.uint ((slice prfop (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
    (let (stream :: bool) =
      ((vec_of_bits [access_vec_dec prfop (( 0 :: int)::ii)]  ::  1 Word.word) \<noteq> (vec_of_bits [B0]  ::  1 Word.word)) in
    (let (_ :: unit) = (Hint_Prefetch address hint target stream) in
@@ -7555,8 +7611,8 @@ definition aarch64_integer_arithmetic_addsub_immediate  :: " int \<Rightarrow>('
 (*val aarch64_integer_arithmetic_addsub_extendedreg : ii -> ii -> ExtendType -> ii -> ii -> bool -> ii -> bool -> M unit*)
 
 definition aarch64_integer_arithmetic_addsub_extendedreg  :: " int \<Rightarrow> int \<Rightarrow> ExtendType \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " aarch64_integer_arithmetic_addsub_extendedreg d l__167 extend_type m n setflags shift sub_op = (
-   if (((l__167 = (( 8 :: int)::ii)))) then
+     " aarch64_integer_arithmetic_addsub_extendedreg d l__158 extend_type m n setflags shift sub_op = (
+   if (((l__158 = (( 8 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7594,7 +7650,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg  :: " int \<Rightarrow>
       else return () ) \<then>
      (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result
      else aset_X d result)))))))))))
-   else if (((l__167 = (( 16 :: int)::ii)))) then
+   else if (((l__158 = (( 16 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7632,7 +7688,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg  :: " int \<Rightarrow>
       else return () ) \<then>
      (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result
      else aset_X d result)))))))))))
-   else if (((l__167 = (( 32 :: int)::ii)))) then
+   else if (((l__158 = (( 32 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7670,7 +7726,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg  :: " int \<Rightarrow>
       else return () ) \<then>
      (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result
      else aset_X d result)))))))))))
-   else if (((l__167 = (( 64 :: int)::ii)))) then
+   else if (((l__158 = (( 64 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7708,7 +7764,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg  :: " int \<Rightarrow>
       else return () ) \<then>
      (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result
      else aset_X d result)))))))))))
-   else if (((l__167 = (( 128 :: int)::ii)))) then
+   else if (((l__158 = (( 128 :: int)::ii)))) then
      (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in
      ((assert_exp True (''datasize constraint'') \<then>
      assert_exp True (''dbytes constraint'')) \<then>
@@ -7747,7 +7803,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg  :: " int \<Rightarrow>
      (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result
      else aset_X d result)))))))))))
    else
-     (let dbytes = (ex_int ((l__167 div (( 8 :: int)::ii)))) in
+     (let dbytes = (ex_int ((l__158 div (( 8 :: int)::ii)))) in
      assert_exp True (''datasize constraint'')))"
 
 
@@ -7882,52 +7938,52 @@ definition CalculateBottomPACBit  :: "(64)Word.word \<Rightarrow>(1)Word.word \<
       if w__1 then
         (if (((top_bit = (vec_of_bits [B1]  ::  1 Word.word)))) then
            (read_reg TCR_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
-           return ((Word.uint ((slice0 w__2 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))
+           return ((Word.uint ((slice w__2 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))
          else
            (read_reg TCR_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
-           return ((Word.uint ((slice0 w__3 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))) \<bind> (\<lambda> (w__4 :: ii) . 
+           return ((Word.uint ((slice w__3 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))) \<bind> (\<lambda> (w__4 :: ii) . 
         (let tsz_field = w__4 in
         (if (((top_bit = (vec_of_bits [B1]  ::  1 Word.word)))) then
            (read_reg TCR_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
-           return (((((slice0 w__5 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))
+           return (((((slice w__5 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))
          else
            (read_reg TCR_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 bits) . 
-           return (((((slice0 w__6 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) \<bind> (\<lambda> (w__7 :: bool) . 
+           return (((((slice w__6 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) \<bind> (\<lambda> (w__7 :: bool) . 
         (let (using64k :: bool) = w__7 in
         return (tsz_field, using64k)))))
       else
         (assert_exp ((HaveEL EL2)) (''HaveEL(EL2)'') \<then>
         (if (((top_bit = (vec_of_bits [B1]  ::  1 Word.word)))) then
            (read_reg TCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 bits) . 
-           return ((Word.uint ((slice0 w__8 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))
+           return ((Word.uint ((slice w__8 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))
          else
            (read_reg TCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 bits) . 
-           return ((Word.uint ((slice0 w__9 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))))) \<bind> (\<lambda> (w__10 :: ii) . 
+           return ((Word.uint ((slice w__9 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))))) \<bind> (\<lambda> (w__10 :: ii) . 
         (let tsz_field = w__10 in
         (if (((top_bit = (vec_of_bits [B1]  ::  1 Word.word)))) then
            (read_reg TCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
-           return (((((slice0 w__11 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))
+           return (((((slice w__11 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))
          else
            (read_reg TCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 bits) . 
-           return (((((slice0 w__12 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) \<bind> (\<lambda> (w__13 :: bool) . 
+           return (((((slice w__12 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) \<bind> (\<lambda> (w__13 :: bool) . 
         (let (using64k :: bool) = w__13 in
         return (tsz_field, using64k))))))
     else
       read_reg PSTATE_ref \<bind> (\<lambda> (w__14 :: ProcState) . 
       (if ((((ProcState_EL   w__14) = EL2))) then
          (read_reg TCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 bits) . 
-         return ((Word.uint ((slice0 w__15 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))
+         return ((Word.uint ((slice w__15 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))
        else
          (read_reg TCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . 
-         return ((Word.uint ((slice0 w__16 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))) \<bind> (\<lambda> (w__17 :: ii) . 
+         return ((Word.uint ((slice w__16 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)))))) \<bind> (\<lambda> (w__17 :: ii) . 
       (let tsz_field = w__17 in
       read_reg PSTATE_ref \<bind> (\<lambda> (w__18 :: ProcState) . 
       (if ((((ProcState_EL   w__18) = EL2))) then
          (read_reg TCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . 
-         return (((((slice0 w__19 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))
+         return (((((slice w__19 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))
        else
          (read_reg TCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
-         return (((((slice0 w__20 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+         return (((((slice w__20 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
       (let (using64k :: bool) = w__21 in
       return (tsz_field, using64k)))))))) \<bind> (\<lambda> varstup .  (let ((tsz_field :: ii), (using64k :: bool)) = varstup in
    (let (max_limit_tsz_field :: ii) = ((( 39 :: int)::ii)) in
@@ -8071,8 +8127,8 @@ definition aset_SPSR  :: "(32)Word.word \<Rightarrow>((register_value),(unit),(e
    UsingAArch32 ()  \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then
      read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . 
-     (let p__611 = ((ProcState_M   w__1)) in
-     (let pat0 = p__611 in
+     (let p__298 = ((ProcState_M   w__1)) in
+     (let pat0 = p__298 in
      if (((pat0 = M32_FIQ))) then write_reg SPSR_fiq_ref value_name
      else if (((pat0 = M32_IRQ))) then write_reg SPSR_irq_ref value_name
      else if (((pat0 = M32_Svc))) then write_reg SPSR_svc_ref value_name
@@ -8083,8 +8139,8 @@ definition aset_SPSR  :: "(32)Word.word \<Rightarrow>((register_value),(unit),(e
      else Unreachable () )))
    else
      read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
-     (let p__610 = ((ProcState_EL   w__2)) in
-     (let pat0 = p__610 in
+     (let p__297 = ((ProcState_EL   w__2)) in
+     (let pat0 = p__297 in
      if (((pat0 = EL1))) then write_reg SPSR_EL1_ref value_name
      else if (((pat0 = EL2))) then write_reg SPSR_EL2_ref value_name
      else if (((pat0 = EL3))) then write_reg SPSR_EL3_ref value_name
@@ -8099,8 +8155,8 @@ definition aget_SPSR  :: " unit \<Rightarrow>((register_value),((32)Word.word),(
    UsingAArch32 ()  \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then
      read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . 
-     (let p__609 = ((ProcState_M   w__1)) in
-     (let pat0 = p__609 in
+     (let p__296 = ((ProcState_M   w__1)) in
+     (let pat0 = p__296 in
      if (((pat0 = M32_FIQ))) then (read_reg SPSR_fiq_ref  :: ( 32 Word.word) M)
      else if (((pat0 = M32_IRQ))) then (read_reg SPSR_irq_ref  :: ( 32 Word.word) M)
      else if (((pat0 = M32_Svc))) then (read_reg SPSR_svc_ref  :: ( 32 Word.word) M)
@@ -8111,8 +8167,8 @@ definition aget_SPSR  :: " unit \<Rightarrow>((register_value),((32)Word.word),(
      else Unreachable ()  \<then> return result)))
    else
      read_reg PSTATE_ref \<bind> (\<lambda> (w__9 :: ProcState) . 
-     (let p__608 = ((ProcState_EL   w__9)) in
-     (let pat0 = p__608 in
+     (let p__295 = ((ProcState_EL   w__9)) in
+     (let pat0 = p__295 in
      if (((pat0 = EL1))) then (read_reg SPSR_EL1_ref  :: ( 32 Word.word) M)
      else if (((pat0 = EL2))) then (read_reg SPSR_EL2_ref  :: ( 32 Word.word) M)
      else if (((pat0 = EL3))) then (read_reg SPSR_EL3_ref  :: ( 32 Word.word) M)
@@ -8160,20 +8216,20 @@ definition FPProcessException  :: " FPExc \<Rightarrow>(32)Word.word \<Rightarro
        (read_reg FPSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
        write_reg
          FPSCR_ref
-         ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 cumul (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
+         ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 cumul (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
      else
        (read_reg FPSR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
        write_reg
          FPSR_ref
-         ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 cumul (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word))))))))"
+         ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 cumul (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word))))))))"
 
 
 (*val FPRoundBase : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*)
 
 definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPRoundBase (N__tv :: int) op1 fpcr rounding = (
-   (let l__164 = N__tv in
-   if (((l__164 = (( 16 :: int)::ii)))) then
+   (let p00 = N__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      (((assert_exp True ('''') \<then>
      assert_exp (((op1 \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \<then>
      assert_exp (((rounding \<noteq> FPRounding_TIEAWAY))) ('''')) \<then>
@@ -8217,12 +8273,12 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
           (read_reg FPSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
           write_reg
             FPSCR_ref
-            ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
+            ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
         else
           (read_reg FPSR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
           write_reg
             FPSR_ref
-            ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))) \<then>
+            ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))) \<then>
        (FPZero (( 16 :: int)::ii) sign  :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__3 :: ( 'N::len)Word.word) . 
        return ((Word.ucast w__3  :: ( 'N::len)Word.word))))
      else
@@ -8288,7 +8344,7 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
          else (biased_exp, int_mant)) in
        (let (int_mant :: ii) =
          (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> (((rounding = FPRounding_ODD)))))) then
-           set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+           set_slice_int (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
          else int_mant) in
        (if (((False \<or> ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word))))))) then
           if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 5 :: int)::ii))) - (( 1 :: int)::ii))))) then
@@ -8336,7 +8392,7 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
        (if (((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr
         else return () ) \<then>
        return ((Word.ucast result  :: ( 'N::len)Word.word))))))))))))))))))))))))))
-   else if (((l__164 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      (((assert_exp True ('''') \<then>
      assert_exp (((op1 \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \<then>
      assert_exp (((rounding \<noteq> FPRounding_TIEAWAY))) ('''')) \<then>
@@ -8380,12 +8436,12 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
           (read_reg FPSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 ::  32 Word.word) . 
           write_reg
             FPSCR_ref
-            ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__9 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
+            ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__9 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
         else
           (read_reg FPSR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 ::  32 Word.word) . 
           write_reg
             FPSR_ref
-            ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__10 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))) \<then>
+            ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__10 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))) \<then>
        (FPZero (( 32 :: int)::ii) sign  :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__11 :: ( 'N::len)Word.word) . 
        return ((Word.ucast w__11  :: ( 'N::len)Word.word))))
      else
@@ -8451,38 +8507,15 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
          else (biased_exp, int_mant)) in
        (let (int_mant :: ii) =
          (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> (((rounding = FPRounding_ODD)))))) then
-           set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+           set_slice_int (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
          else int_mant) in
-       (if (((True \<or> ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word))))))) then
-          if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 8 :: int)::ii))) - (( 1 :: int)::ii))))) then
-            (if overflow_to_inf then (FPInfinity (( 32 :: int)::ii) sign  :: ( 32 Word.word) M)
-             else (FPMaxNormal (( 32 :: int)::ii) sign  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 ::  32 Word.word) . 
-            (let result = w__14 in
-            FPProcessException FPExc_Overflow fpcr \<then>
-            ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in
-            return (error, result)))))
-          else
-            (let (result :: 32 bits) =
-              ((concat_vec
-                 ((concat_vec sign
-                     ((GetSlice_int
-                         ((make_the_value (((((( 32 :: int)::ii) - (( 23 :: int)::ii))) - (( 1 :: int)::ii)))
-                            ::  8 itself)) biased_exp (( 0 :: int)::ii)
-                        ::  8 Word.word))
-                    ::  9 Word.word))
-                 ((GetSlice_int ((make_the_value (( 23 :: int)::ii)  ::  23 itself)) int_mant (( 0 :: int)::ii)
-                    ::  23 Word.word))
-                ::  32 Word.word)) in
-            return (error, result))
-        else if ((((ex_int biased_exp)) \<ge> ((pow2 (( 8 :: int)::ii))))) then
-          (let result =
-            ((concat_vec sign
-               ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 1 :: int)::ii)))  ::  31 itself))
-                  ::  31 Word.word))
-              ::  32 Word.word)) in
-          FPProcessException FPExc_InvalidOp fpcr \<then>
-          ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in
-          return (error, result))))
+       (if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 8 :: int)::ii))) - (( 1 :: int)::ii))))) then
+          (if overflow_to_inf then (FPInfinity (( 32 :: int)::ii) sign  :: ( 32 Word.word) M)
+           else (FPMaxNormal (( 32 :: int)::ii) sign  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 ::  32 Word.word) . 
+          (let result = w__14 in
+          FPProcessException FPExc_Overflow fpcr \<then>
+          ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in
+          return (error, result)))))
         else
           (let (result :: 32 bits) =
             ((concat_vec
@@ -8499,7 +8532,7 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
        (if (((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr
         else return () ) \<then>
        return ((Word.ucast result  :: ( 'N::len)Word.word))))))))))))))))))))))))))
-   else if (((l__164 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      (((assert_exp True ('''') \<then>
      assert_exp (((op1 \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \<then>
      assert_exp (((rounding \<noteq> FPRounding_TIEAWAY))) ('''')) \<then>
@@ -8543,12 +8576,12 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
           (read_reg FPSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 ::  32 Word.word) . 
           write_reg
             FPSCR_ref
-            ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__17 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
+            ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__17 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))
         else
           (read_reg FPSR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 ::  32 Word.word) . 
           write_reg
             FPSR_ref
-            ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))) \<then>
+            ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 3 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)))) \<then>
        (FPZero (( 64 :: int)::ii) sign  :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'N::len)Word.word) . 
        return ((Word.ucast w__19  :: ( 'N::len)Word.word))))
      else
@@ -8614,38 +8647,15 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
          else (biased_exp, int_mant)) in
        (let (int_mant :: ii) =
          (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> (((rounding = FPRounding_ODD)))))) then
-           set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+           set_slice_int (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
          else int_mant) in
-       (if (((True \<or> ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word))))))) then
-          if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 11 :: int)::ii))) - (( 1 :: int)::ii))))) then
-            (if overflow_to_inf then (FPInfinity (( 64 :: int)::ii) sign  :: ( 64 Word.word) M)
-             else (FPMaxNormal (( 64 :: int)::ii) sign  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__22 ::  64 Word.word) . 
-            (let result = w__22 in
-            FPProcessException FPExc_Overflow fpcr \<then>
-            ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in
-            return (error, result)))))
-          else
-            (let (result :: 64 bits) =
-              ((concat_vec
-                 ((concat_vec sign
-                     ((GetSlice_int
-                         ((make_the_value (((((( 64 :: int)::ii) - (( 52 :: int)::ii))) - (( 1 :: int)::ii)))
-                            ::  11 itself)) biased_exp (( 0 :: int)::ii)
-                        ::  11 Word.word))
-                    ::  12 Word.word))
-                 ((GetSlice_int ((make_the_value (( 52 :: int)::ii)  ::  52 itself)) int_mant (( 0 :: int)::ii)
-                    ::  52 Word.word))
-                ::  64 Word.word)) in
-            return (error, result))
-        else if ((((ex_int biased_exp)) \<ge> ((pow2 (( 11 :: int)::ii))))) then
-          (let result =
-            ((concat_vec sign
-               ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 1 :: int)::ii)))  ::  63 itself))
-                  ::  63 Word.word))
-              ::  64 Word.word)) in
-          FPProcessException FPExc_InvalidOp fpcr \<then>
-          ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in
-          return (error, result))))
+       (if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 11 :: int)::ii))) - (( 1 :: int)::ii))))) then
+          (if overflow_to_inf then (FPInfinity (( 64 :: int)::ii) sign  :: ( 64 Word.word) M)
+           else (FPMaxNormal (( 64 :: int)::ii) sign  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__22 ::  64 Word.word) . 
+          (let result = w__22 in
+          FPProcessException FPExc_Overflow fpcr \<then>
+          ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in
+          return (error, result)))))
         else
           (let (result :: 64 bits) =
             ((concat_vec
@@ -8670,7 +8680,7 @@ definition FPRoundBase  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \
 definition FPRoundCV  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPRoundCV (N__tv :: int) op1 fpcr__arg rounding = (
    (let fpcr = fpcr__arg in
-   (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
+   (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
    (FPRoundBase N__tv op1 fpcr rounding  :: (( 'N::len)Word.word) M))))"
 
 
@@ -8681,7 +8691,7 @@ definition FPRoundCV  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<R
 definition FPRound__0  :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad "  where 
      " FPRound__0 (N__tv :: int) op1 fpcr__arg rounding = (
    (let fpcr = fpcr__arg in
-   (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
+   (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
    (FPRoundBase N__tv op1 fpcr rounding  :: (( 'N::len)Word.word) M))))"
 
 
@@ -8714,12 +8724,12 @@ definition FPProcessNaN  :: " FPType \<Rightarrow>('N::len)Word.word \<Rightarro
    ((assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \<then>
    assert_exp ((((((typ1 = FPType_QNaN))) \<or> (((typ1 = FPType_SNaN)))))) (''((type == FPType_QNaN) || (type == FPType_SNaN))'')) \<then>
    undefined_int () ) \<bind> (\<lambda> (topfrac :: ii) . 
-   (let l__161 = (int (size op1)) in
+   (let p00 = (int (size op1)) in
    (let (topfrac :: ii) =
-     (if (((l__161 = (( 16 :: int)::ii)))) then
+     (if (((p00 = (( 16 :: int)::ii)))) then
        (let (op1 ::  16 Word.word) = ((Word.ucast op1  ::  16 Word.word)) in
        (( 9 :: int)::ii))
-     else if (((l__161 = (( 32 :: int)::ii)))) then
+     else if (((p00 = (( 32 :: int)::ii)))) then
        (let (op1 ::  32 Word.word) = ((Word.ucast op1  ::  32 Word.word)) in
        (( 22 :: int)::ii))
      else
@@ -8728,7 +8738,7 @@ definition FPProcessNaN  :: " FPType \<Rightarrow>('N::len)Word.word \<Rightarro
    (let (result :: 'N bits) = op1 in
    (if (((typ1 = FPType_SNaN))) then
       (let result =
-        ((set_slice0 ((int (size op1))) (( 1 :: int)::ii) result topfrac (vec_of_bits [B1]  ::  1 Word.word)  :: ( 'N::len)Word.word)) in
+        ((set_slice ((int (size op1))) (( 1 :: int)::ii) result topfrac (vec_of_bits [B1]  ::  1 Word.word)  :: ( 'N::len)Word.word)) in
       FPProcessException FPExc_InvalidOp fpcr \<then> return result)
     else return result) \<bind> (\<lambda> (result :: 'N bits) . 
    if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
@@ -8835,13 +8845,13 @@ definition AArch32_ExecutingLSMInstr  :: " unit \<Rightarrow>((register_value),(
    CurrentInstrSet ()  \<bind> (\<lambda> (instr_set :: InstrSet) . 
    assert_exp ((((((instr_set = InstrSet_A32))) \<or> (((instr_set = InstrSet_T32)))))) (''((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))'') \<then>
    (if (((instr_set = InstrSet_A32))) then
-     return ((((((((slice0 instr (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)))) \<and> (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))))))
+     return ((((((((slice instr (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)))) \<and> (((((slice instr (( 25 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))))))
    else
      ThisInstrLength ()  \<bind> (\<lambda> (w__0 :: ii) . 
      return (if (((((ex_int w__0)) = (( 16 :: int)::ii)))) then
-               (((slice0 instr (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B0,B0]  ::  4 Word.word))
+               (((slice instr (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B0,B0]  ::  4 Word.word))
              else
-               ((((((slice0 instr (( 25 :: int)::ii) (( 7 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0]  ::  7 Word.word)))) \<and> ((((vec_of_bits [access_vec_dec instr (( 22 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))))))"
+               ((((((slice instr (( 25 :: int)::ii) (( 7 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0]  ::  7 Word.word)))) \<and> ((((vec_of_bits [access_vec_dec instr (( 22 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))))))"
 
 
 (*val AArch32_ExecutingCP10or11Instr : unit -> M bool*)
@@ -8852,13 +8862,13 @@ definition AArch32_ExecutingCP10or11Instr  :: " unit \<Rightarrow>((register_val
    CurrentInstrSet ()  \<bind> (\<lambda> (instr_set :: InstrSet) . 
    assert_exp ((((((instr_set = InstrSet_A32))) \<or> (((instr_set = InstrSet_T32)))))) (''((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))'') \<then>
    return (if (((instr_set = InstrSet_A32))) then
-             (((((((((slice0 instr (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) \<or> (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word))))))) \<and> (((((and_vec ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+             (((((((((slice instr (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) \<or> (((((slice instr (( 25 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word))))))) \<and> (((((and_vec ((slice instr (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                        (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
                       ::  4 Word.word)) = (vec_of_bits [B1,B0,B1,B0]  ::  4 Word.word)))))
            else
-             (((((((((and_vec ((slice0 instr (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+             (((((((((and_vec ((slice instr (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                            (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
-                          ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) \<and> ((((((((slice0 instr (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) \<or> (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))))))))) \<and> (((((and_vec ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+                          ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) \<and> ((((((((slice instr (( 24 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)))) \<or> (((((slice instr (( 25 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))))))))) \<and> (((((and_vec ((slice instr (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                        (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
                       ::  4 Word.word)) = (vec_of_bits [B1,B0,B1,B0]  ::  4 Word.word)))))))))"
 
@@ -8875,7 +8885,7 @@ definition AArch32_ReportDeferredSError  :: "(2)Word.word \<Rightarrow>(1)Word.w
      " AArch32_ReportDeferredSError AET ExT = (
    (undefined_bitvector (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (target :: 32 bits) . 
    (let (target :: 32 bits) =
-     ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)) in
+     ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  32 Word.word)) in
    (let (syndrome :: 16 bits) = ((Zeros__0 ((make_the_value (( 16 :: int)::ii)  ::  16 itself))  ::  16 Word.word)) in
    read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . 
    (if ((((ProcState_EL   w__0) = EL2))) then
@@ -8982,9 +8992,9 @@ definition Halted  :: " unit \<Rightarrow>((register_value),(bool),(exception))m
      " Halted _ = (
    or_boolM
      ((read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
-      return (((((slice0 w__0 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1]  ::  6 Word.word))))))
+      return (((((slice w__0 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1]  ::  6 Word.word))))))
      ((read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
-      return (((((slice0 w__1 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0]  ::  6 Word.word)))))) \<bind> (\<lambda> (w__2 :: bool) . 
+      return (((((slice w__1 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0]  ::  6 Word.word)))))) \<bind> (\<lambda> (w__2 :: bool) . 
    return ((\<not> w__2))))"
 
 
@@ -9004,8 +9014,8 @@ definition FPUnpackBase  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig
    (undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . 
    (if (((((int (size fpval))) = (( 16 :: int)::ii)))) then
       (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec fpval (( 15 :: int)::ii)]  ::  1 Word.word)) in
-      (let (exp16 :: 5 bits) = ((slice0 fpval (( 10 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word)) in
-      (let (frac16 :: 10 bits) = ((slice0 fpval (( 0 :: int)::ii) (( 10 :: int)::ii)  ::  10 Word.word)) in
+      (let (exp16 :: 5 bits) = ((slice fpval (( 10 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word)) in
+      (let (frac16 :: 10 bits) = ((slice fpval (( 0 :: int)::ii) (( 10 :: int)::ii)  ::  10 Word.word)) in
       (let ((typ1 :: FPType), (value_name :: real)) =
         (if ((IsZero exp16)) then
           (let ((typ1 :: FPType), (value_name :: real)) =
@@ -9050,8 +9060,8 @@ definition FPUnpackBase  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig
       return (sign, typ1, value_name)))))
     else if (((((int (size fpval))) = (( 32 :: int)::ii)))) then
       (let sign = ((vec_of_bits [access_vec_dec fpval (( 31 :: int)::ii)]  ::  1 Word.word)) in
-      (let exp32 = ((slice0 fpval (( 23 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word)) in
-      (let frac32 = ((slice0 fpval (( 0 :: int)::ii) (( 23 :: int)::ii)  ::  23 Word.word)) in
+      (let exp32 = ((slice fpval (( 23 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word)) in
+      (let frac32 = ((slice fpval (( 0 :: int)::ii) (( 23 :: int)::ii)  ::  23 Word.word)) in
       (if ((IsZero exp32)) then
          if (((((IsZero frac32)) \<or> ((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word))))))) then
            (let typ1 = FPType_Zero in
@@ -9095,8 +9105,8 @@ definition FPUnpackBase  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig
       return (sign, typ1, value_name))))))
     else
       (let sign = ((vec_of_bits [access_vec_dec fpval (( 63 :: int)::ii)]  ::  1 Word.word)) in
-      (let exp64 = ((slice0 fpval (( 52 :: int)::ii) (( 11 :: int)::ii)  ::  11 Word.word)) in
-      (let frac64 = ((slice0 fpval (( 0 :: int)::ii) (( 52 :: int)::ii)  ::  52 Word.word)) in
+      (let exp64 = ((slice fpval (( 52 :: int)::ii) (( 11 :: int)::ii)  ::  11 Word.word)) in
+      (let frac64 = ((slice fpval (( 0 :: int)::ii) (( 52 :: int)::ii)  ::  52 Word.word)) in
       (if ((IsZero exp64)) then
          if (((((IsZero frac64)) \<or> ((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word))))))) then
            (let typ1 = FPType_Zero in
@@ -9150,7 +9160,7 @@ definition FPUnpackBase  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig
 definition FPUnpackCV  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(FPType*(1)Word.word*real),(exception))monad "  where 
      " FPUnpackCV fpval fpcr__arg = (
    (let fpcr = fpcr__arg in
-   (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
+   (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
    undefined_real ()  \<bind> (\<lambda> (value_name :: real) . 
    (undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . 
    undefined_FPType ()  \<bind> (\<lambda> (fp_type :: FPType) . 
@@ -9167,8 +9177,8 @@ definition FPUnpackCV  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right
 
 definition FPConvert__0  :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('M::len)Word.word),(exception))monad "  where 
      " FPConvert__0 (M__tv :: int) op1 fpcr rounding = (
-   (let l__158 = M__tv in
-   if (((l__158 = (( 16 :: int)::ii)))) then
+   (let p00 = M__tv in
+   if (((p00 = (( 16 :: int)::ii)))) then
      ((assert_exp True ('''') \<then>
      assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then>
      (undefined_bitvector (( 16 :: int)::ii)  :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . 
@@ -9202,7 +9212,7 @@ definition FPConvert__0  :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>(
       else (FPRoundCV (( 16 :: int)::ii) value_name fpcr rounding  :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16
        bits) . 
      return ((Word.ucast result  :: ( 'M::len)Word.word)))))))))))))
-   else if (((l__158 = (( 32 :: int)::ii)))) then
+   else if (((p00 = (( 32 :: int)::ii)))) then
      ((assert_exp True ('''') \<then>
      assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then>
      (undefined_bitvector (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . 
@@ -9236,7 +9246,7 @@ definition FPConvert__0  :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>(
       else (FPRoundCV (( 32 :: int)::ii) value_name fpcr rounding  :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32
        bits) . 
      return ((Word.ucast result  :: ( 'M::len)Word.word)))))))))))))
-   else if (((l__158 = (( 64 :: int)::ii)))) then
+   else if (((p00 = (( 64 :: int)::ii)))) then
      ((assert_exp True ('''') \<then>
      assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then>
      (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (result :: 64 bits) . 
@@ -9283,7 +9293,7 @@ definition FPConvert__1  :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>(
 definition FPUnpack  :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(FPType*(1)Word.word*real),(exception))monad "  where 
      " FPUnpack fpval fpcr__arg = (
    (let fpcr = fpcr__arg in
-   (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
+   (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)) in
    undefined_real ()  \<bind> (\<lambda> (value_name :: real) . 
    (undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . 
    undefined_FPType ()  \<bind> (\<lambda> (fp_type :: FPType) . 
@@ -9369,7 +9379,7 @@ definition FPToFixedJS  :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>(3
       (read_reg FPSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 ::  32 Word.word) . 
       write_reg
         FPSCR_ref
-        ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 28 :: int)::ii)
+        ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 28 :: int)::ii)
             ((concat_vec ((concat_vec (vec_of_bits [B0]  ::  1 Word.word) Z  ::  2 Word.word))
                 (vec_of_bits [B0,B0]  ::  2 Word.word)
                ::  4 Word.word))
@@ -10008,11 +10018,11 @@ definition ExternalDebugInterruptsDisabled  :: "(2)Word.word \<Rightarrow>((regi
    if (((pat0 = EL3))) then
      and_boolM
        ((read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
-        return (((((slice0 w__0 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) ((ExternalSecureInvasiveDebugEnabled () ))
+        return (((((slice w__0 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))))) ((ExternalSecureInvasiveDebugEnabled () ))
    else if (((pat0 = EL2))) then
      and_boolM
        ((read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 bits) . 
-        return (((((and_vec ((slice0 w__3 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+        return (((((and_vec ((slice w__3 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                        (vec_of_bits [B1,B0]  ::  2 Word.word)
                       ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))
        ((ExternalInvasiveDebugEnabled () ))
@@ -10021,14 +10031,14 @@ definition ExternalDebugInterruptsDisabled  :: "(2)Word.word \<Rightarrow>((regi
      if w__6 then
        and_boolM
          ((read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
-          return (((((and_vec ((slice0 w__7 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+          return (((((and_vec ((slice w__7 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                          (vec_of_bits [B1,B0]  ::  2 Word.word)
                         ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))
          ((ExternalSecureInvasiveDebugEnabled () ))
      else
        and_boolM
          ((read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . 
-          return (((((slice0 w__10 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) \<noteq> (vec_of_bits [B0,B0]  ::  2 Word.word)))))) ((ExternalInvasiveDebugEnabled () ))))))"
+          return (((((slice w__10 (( 22 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) \<noteq> (vec_of_bits [B0,B0]  ::  2 Word.word)))))) ((ExternalInvasiveDebugEnabled () ))))))"
 
 
 (*val ELStateUsingAArch32K : mword ty2 -> bool -> M (bool * bool)*)
@@ -10115,44 +10125,44 @@ definition UpdateEDSCRFields  :: " unit \<Rightarrow>((register_value),(unit),(e
      (read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
      (write_reg
        EDSCR_ref
-       ((set_slice0 (( 32 :: int)::ii) (( 2 :: int)::ii) w__1 (( 8 :: int)::ii) (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  32 Word.word)) \<then>
+       ((set_slice (( 32 :: int)::ii) (( 2 :: int)::ii) w__1 (( 8 :: int)::ii) (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  32 Word.word)) \<then>
      (read_reg EDSCR_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
      (undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 ::  1 Word.word) . 
-     (write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 18 :: int)::ii) w__3  ::  32 Word.word)) \<then>
+     (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 18 :: int)::ii) w__3  ::  32 Word.word)) \<then>
      (read_reg EDSCR_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__4 ::  32 Word.word) . 
      write_reg
        EDSCR_ref
-       ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 10 :: int)::ii) (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)
+       ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 10 :: int)::ii) (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)
           ::  32 Word.word))))))
    else
      (read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 ::  32 Word.word) . 
      read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . 
-     (write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 2 :: int)::ii) w__5 (( 8 :: int)::ii)(ProcState_EL   w__6)  ::  32 Word.word)) \<then>
+     (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 2 :: int)::ii) w__5 (( 8 :: int)::ii)(ProcState_EL   w__6)  ::  32 Word.word)) \<then>
      (read_reg EDSCR_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 ::  32 Word.word) . 
      IsSecure ()  \<bind> (\<lambda> (w__8 :: bool) . 
      (write_reg
        EDSCR_ref
-       ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__7 (( 18 :: int)::ii)
+       ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__7 (( 18 :: int)::ii)
            (if w__8 then (vec_of_bits [B0]  ::  1 Word.word)
             else (vec_of_bits [B1]  ::  1 Word.word))
           ::  32 Word.word)) \<then>
      (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M)) \<bind> (\<lambda> (RW :: 4 bits) . 
      ELUsingAArch32 EL1 \<bind> (\<lambda> (w__9 :: bool) . 
      (let (RW :: 4 bits) =
-       ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 1 :: int)::ii)
+       ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 1 :: int)::ii)
           (if w__9 then (vec_of_bits [B0]  ::  1 Word.word)
            else (vec_of_bits [B1]  ::  1 Word.word))
          ::  4 Word.word)) in
      read_reg PSTATE_ref \<bind> (\<lambda> (w__10 :: ProcState) . 
      (if ((((ProcState_EL   w__10) \<noteq> EL0))) then
         (let (RW :: 4 bits) =
-          ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)]  ::  1 Word.word)
+          ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)]  ::  1 Word.word)
             ::  4 Word.word)) in
         return RW)
       else
         UsingAArch32 ()  \<bind> (\<lambda> (w__11 :: bool) . 
         (let (RW :: 4 bits) =
-          ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii)
+          ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii)
              (if w__11 then (vec_of_bits [B0]  ::  1 Word.word)
               else (vec_of_bits [B1]  ::  1 Word.word))
             ::  4 Word.word)) in
@@ -10163,45 +10173,45 @@ definition UpdateEDSCRFields  :: " unit \<Rightarrow>((register_value),(unit),(e
            return ((((vec_of_bits [access_vec_dec w__12 (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word))))))) \<bind> (\<lambda> (w__14 :: bool) . 
      (if w__14 then
         (let (RW :: 4 bits) =
-          ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)]  ::  1 Word.word)
+          ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)]  ::  1 Word.word)
             ::  4 Word.word)) in
         return RW)
       else
         ELUsingAArch32 EL2 \<bind> (\<lambda> (w__15 :: bool) . 
         (let (RW :: 4 bits) =
-          ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii)
+          ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii)
              (if w__15 then (vec_of_bits [B0]  ::  1 Word.word)
               else (vec_of_bits [B1]  ::  1 Word.word))
             ::  4 Word.word)) in
         return RW))) \<bind> (\<lambda> (RW :: 4 bits) . 
      (if ((\<not> ((HaveEL EL3)))) then
         (let (RW :: 4 bits) =
-          ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)]  ::  1 Word.word)
+          ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)]  ::  1 Word.word)
             ::  4 Word.word)) in
         return RW)
       else
         ELUsingAArch32 EL3 \<bind> (\<lambda> (w__16 :: bool) . 
         (let (RW :: 4 bits) =
-          ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii)
+          ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii)
              (if w__16 then (vec_of_bits [B0]  ::  1 Word.word)
               else (vec_of_bits [B1]  ::  1 Word.word))
             ::  4 Word.word)) in
         return RW))) \<bind> (\<lambda> (RW :: 4 bits) . 
      (if ((((vec_of_bits [access_vec_dec RW (( 3 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
         (undefined_bitvector (( 3 :: int)::ii)  :: ( 3 Word.word) M) \<bind> (\<lambda> (w__17 ::  3 Word.word) . 
-        (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 3 :: int)::ii) RW (( 0 :: int)::ii) w__17  ::  4 Word.word)) in
+        (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 3 :: int)::ii) RW (( 0 :: int)::ii) w__17  ::  4 Word.word)) in
         return RW))
       else if ((((vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
         (undefined_bitvector (( 2 :: int)::ii)  :: ( 2 Word.word) M) \<bind> (\<lambda> (w__18 ::  2 Word.word) . 
-        (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 2 :: int)::ii) RW (( 0 :: int)::ii) w__18  ::  4 Word.word)) in
+        (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 2 :: int)::ii) RW (( 0 :: int)::ii) w__18  ::  4 Word.word)) in
         return RW))
       else if ((((vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
         (undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M) \<bind> (\<lambda> (w__19 ::  1 Word.word) . 
-        (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) w__19  ::  4 Word.word)) in
+        (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) w__19  ::  4 Word.word)) in
         return RW))
       else return RW) \<bind> (\<lambda> (RW :: 4 bits) . 
      (read_reg EDSCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 ::  32 Word.word) . 
-     write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__20 (( 10 :: int)::ii) RW  ::  32 Word.word))))))))))))))))))"
+     write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__20 (( 10 :: int)::ii) RW  ::  32 Word.word))))))))))))))))))"
 
 
 (*val Halt : mword ty6 -> M unit*)
@@ -10370,9 +10380,9 @@ definition S2ConvertAttrsHints  :: "(2)Word.word \<Rightarrow> AccType \<Rightar
 definition S2AttrDecode  :: "(2)Word.word \<Rightarrow>(4)Word.word \<Rightarrow> AccType \<Rightarrow>((register_value),(MemoryAttributes),(exception))monad "  where 
      " S2AttrDecode SH attr acctype = (
    undefined_MemoryAttributes ()  \<bind> (\<lambda> (memattrs :: MemoryAttributes) . 
-   (if (((((slice0 attr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
+   (if (((((slice attr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
       (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_typ := MemType_Device |))) in
-      (let b__0 = ((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+      (let b__0 = ((slice attr (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
       (let (memattrs :: MemoryAttributes) =
         (if (((b__0 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
           (memattrs (| MemoryAttributes_device := DeviceType_nGnRnE |))
@@ -10382,13 +10392,13 @@ definition S2AttrDecode  :: "(2)Word.word \<Rightarrow>(4)Word.word \<Rightarrow
           (memattrs (| MemoryAttributes_device := DeviceType_nGRE |))
         else (memattrs (| MemoryAttributes_device := DeviceType_GRE |))) in
       return memattrs)))
-    else if (((((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) \<noteq> (vec_of_bits [B0,B0]  ::  2 Word.word))))
+    else if (((((slice attr (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) \<noteq> (vec_of_bits [B0,B0]  ::  2 Word.word))))
     then
       (let memattrs = ((memattrs (| MemoryAttributes_typ := MemType_Normal |))) in
-      S2ConvertAttrsHints ((slice0 attr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) acctype \<bind> (\<lambda> (w__0 ::
+      S2ConvertAttrsHints ((slice attr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) acctype \<bind> (\<lambda> (w__0 ::
         MemAttrHints) . 
       (let memattrs = ((memattrs (| MemoryAttributes_outer := w__0 |))) in
-      S2ConvertAttrsHints ((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) acctype \<bind> (\<lambda> (w__1 ::
+      S2ConvertAttrsHints ((slice attr (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) acctype \<bind> (\<lambda> (w__1 ::
         MemAttrHints) . 
       (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_inner := w__1 |))) in
       (let (memattrs :: MemoryAttributes) =
@@ -10661,25 +10671,25 @@ definition LongConvertAttrsHints  :: "(4)Word.word \<Rightarrow> AccType \<Right
      (if w__0 then
        (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in
        (result (| MemAttrHints_hints := MemHint_No |)))
-     else if (((((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
+     else if (((((slice attrfield (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
        (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WT |))) in
        (let (result :: MemAttrHints) =
-         ((result (| MemAttrHints_hints := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
+         ((result (| MemAttrHints_hints := ((slice attrfield (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
        (result (| MemAttrHints_transient := True |))))
-     else if (((((slice0 attrfield (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B0,B1,B0,B0]  ::  4 Word.word)))) then
+     else if (((((slice attrfield (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B0,B1,B0,B0]  ::  4 Word.word)))) then
        (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in
        (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := MemHint_No |))) in
        (result (| MemAttrHints_transient := False |))))
-     else if (((((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then
+     else if (((((slice attrfield (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then
        (let (result :: MemAttrHints) =
-         ((result (| MemAttrHints_attrs := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
+         ((result (| MemAttrHints_attrs := ((slice attrfield (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
        (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := MemAttr_WB |))) in
        (result (| MemAttrHints_transient := True |))))
      else
        (let (result :: MemAttrHints) =
-         ((result (| MemAttrHints_attrs := ((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
+         ((result (| MemAttrHints_attrs := ((slice attrfield (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
        (let (result :: MemAttrHints) =
-         ((result (| MemAttrHints_hints := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
+         ((result (| MemAttrHints_hints := ((slice attrfield (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|))) in
        (result (| MemAttrHints_transient := False |))))) in
    return result))))"
 
@@ -10804,11 +10814,11 @@ definition AArch64_CheckAndUpdateDescriptor_SecondStage  :: " DescriptorUpdate \
       (let desc = w__1 in
       (let (desc :: 64 bits) =
         (if hw_update_AF then
-          (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)
+          (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)
         else desc) in
       (let (desc :: 64 bits) =
         (if hw_update_AP then
-          (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)
+          (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)
         else desc) in
       aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc)))))))
     else return () ) \<then>
@@ -10902,10 +10912,10 @@ definition ZeroExtend_slice_append  :: " int \<Rightarrow>('n::len)Word.word \<R
      " ZeroExtend_slice_append (o__tv :: int) xs i l ys = (
    assert_exp True ('''') \<then>
    ((let xs = ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) in
-   (ZeroExtend__1 o__tv ((shiftr xs i  :: ( 'n::len)Word.word))  :: (( 'o::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'o::len)Word.word) . 
-   (let (xs :: 'o bits) = ((shiftl w__0 ((int (size ys)))  :: ( 'o::len)Word.word)) in
-   (ZeroExtend__1 ((int (size xs))) ys  :: (( 'o::len)Word.word) M) \<bind> (\<lambda> (ys :: 'o bits) . 
-   return ((or_vec xs ys  :: ( 'o::len)Word.word))))))))"
+   (let (xs :: 'o bits) =
+     ((shiftl ((extzv o__tv ((shiftr xs i  :: ( 'n::len)Word.word))  :: ( 'o::len)Word.word)) ((int (size ys)))  :: ( 'o::len)Word.word)) in
+   (let (ys :: 'o bits) = ((extzv ((int (size xs))) ys  :: ( 'o::len)Word.word)) in
+   return ((or_vec xs ys  :: ( 'o::len)Word.word)))))))"
 
 
 definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightarrow>(64)Word.word \<Rightarrow> AccType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),(TLBRecord),(exception))monad "  where 
@@ -10951,13 +10961,13 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
       liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 bits) . 
       (let inputaddr = w__6 in
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 bits) . 
-      (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__7 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+      (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__7 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__8 :: 32 bits) . 
       (let largegrain =
-        (((slice0 w__8 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+        (((slice w__8 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__9 :: 32 bits) . 
       (let midgrain =
-        (((slice0 w__9 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
+        (((slice w__9 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
       (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in
       (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then
          (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in
@@ -10973,7 +10983,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
          return inputsize)))
        else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . 
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__10 :: 32 bits) . 
-      (let ps = ((slice0 w__10 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+      (let ps = ((slice w__10 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
       and_boolM
         (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max))))))))
         (liftR ((IsZero_slice inputaddr inputsize
@@ -10986,9 +10996,9 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 bits) . 
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__15 :: 32 bits) . 
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 bits) . 
-      liftR (WalkAttrDecode ((slice0 w__14 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-               ((slice0 w__15 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-               ((slice0 w__16 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) True) \<bind> (\<lambda> (w__17 :: MemoryAttributes) . 
+      liftR (WalkAttrDecode ((slice w__14 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+               ((slice w__15 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+               ((slice w__16 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) True) \<bind> (\<lambda> (w__17 :: MemoryAttributes) . 
       (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__17 |))) in
       liftR ((read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__18 :: 32 bits) . 
       (let reversedescriptors =
@@ -11004,7 +11014,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
          return ((((vec_of_bits [access_vec_dec w__21 (( 22 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__22 :: bool) . 
       (let update_AP = w__22 in
       liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__23 :: 32 bits) . 
-      (let startlevel = (Word.uint ((slice0 w__23 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
+      (let startlevel = (Word.uint ((slice w__23 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
       (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) =
         (if largegrain then
           (let (grainsize :: ii) = ((( 16 :: int)::ii)) in
@@ -11117,7 +11127,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
              (let z = (if ((baselowerbound < (( 6 :: int)::ii))) then (( 6 :: int)::ii) else baselowerbound) in
              liftR (assert_exp True ('''')) \<then>
              ((let (baseaddress :: 52 bits) =
-               ((concat_vec ((slice0 baseregister (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+               ((concat_vec ((slice baseregister (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                   ((slice_zeros_concat ((((((- z)) + (( 48 :: int)::ii))) + z))
                       baseregister z ((((- z)) + (( 48 :: int)::ii))) z
                      ::  48 Word.word))
@@ -11148,10 +11158,39 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
           liftR (undefined_bool () ) \<bind> (\<lambda> (hwupdatewalk :: bool) . 
           liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . 
           liftR (undefined_int () ) \<bind> (\<lambda> (addrselectbottom :: ii) . 
-          (untilM (addrselectbottom, desc, descaddr, level, result)
-            (\<lambda> varstup .  (let (addrselectbottom, desc, descaddr, level, result) = varstup in
+          (untilM (accdesc,
+                   addrselectbottom,
+                   addrselecttop,
+                   baseaddress,
+                   blocktranslate,
+                   desc,
+                   descaddr,
+                   descaddr2,
+                   level,
+                   result)
+            (\<lambda> varstup . 
+            (let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
+                 baseaddress,
+                 blocktranslate,
+                 desc,
+                 descaddr,
+                 descaddr2,
+                 level,
+                 result) = varstup in
               return blocktranslate))
-            (\<lambda> varstup .  (let (addrselectbottom, desc, descaddr, level, result) = varstup in
+            (\<lambda> varstup . 
+            (let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
+                 baseaddress,
+                 blocktranslate,
+                 desc,
+                 descaddr,
+                 descaddr2,
+                 level,
+                 result) = varstup in
               (let addrselectbottom =
                 ((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride))))
                   +
@@ -11180,21 +11219,22 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
               (let desc = w__36 in
               (if reversedescriptors then liftR ((BigEndianReverse desc  :: ( 64 Word.word) M))
                else return desc) \<bind> (\<lambda> (desc :: 64 bits) . 
-              (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) \<or> ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii))))))))))
+              (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) \<or> ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii))))))))))
                then
                  (let (tmp_240 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
                  liftR (AArch64_TranslationFault ipaddress level acctype iswrite True s2fs1walk) \<bind> (\<lambda> (w__38 ::
                    FaultRecord) . 
                  (let tmp_240 = ((tmp_240 (| AddressDescriptor_fault := w__38 |))) in
                  (let result = ((result (| TLBRecord_addrdesc := tmp_240 |))) in
-                 (early_return result :: (unit, TLBRecord) MR) \<then> return (level, result)))))
-               else if ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii)))))))
+                 (early_return result :: (unit, TLBRecord) MR) \<then>
+                 return (addrselecttop, baseaddress, blocktranslate, level, result)))))
+               else if ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii)))))))
                then
                  (let (blocktranslate :: bool) = True in
-                 return (level, result))
+                 return (addrselecttop, baseaddress, blocktranslate, level, result))
                else
                  or_boolM
-                   (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
+                   (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
                    (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii))))
                       (liftR (IsZero_slice desc outputsize
                                 ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__39 ::
@@ -11206,32 +11246,41 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
                      FaultRecord) . 
                    (let tmp_250 = ((tmp_250 (| AddressDescriptor_fault := w__42 |))) in
                    (let result = ((result (| TLBRecord_addrdesc := tmp_250 |))) in
-                   (early_return result :: (unit, TLBRecord) MR) \<then> return (level, result)))))
+                   (early_return result :: (unit, TLBRecord) MR) \<then>
+                   return (addrselecttop, baseaddress, blocktranslate, level, result)))))
                  else
                    (let gsz = grainsize in
                    liftR (assert_exp True ('''')) \<then>
-                   ((let (_ :: unit) =
+                   ((let (baseaddress :: 52 bits) =
                      (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then
-                       (let (baseaddress :: 52 bits) =
-                         ((concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
-                            ((slice_zeros_concat
-                                ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc
-                                gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz
-                               ::  48 Word.word))
-                           ::  52 Word.word)) in
-                       () )
+                       (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+                          ((slice_zeros_concat
+                              ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc
+                              gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz
+                             ::  48 Word.word))
+                         ::  52 Word.word)
                      else
-                       (let (baseaddress :: 52 bits) =
-                         ((place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii)))
-                            gsz
-                           ::  52 Word.word)) in
-                       () )) in
+                       (place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii)))
+                          gsz
+                         ::  52 Word.word)) in
                    (let (level :: ii) = (((ex_int level)) + (( 1 :: int)::ii)) in
                    (let (addrselecttop :: ii) = (((ex_int addrselectbottom)) - (( 1 :: int)::ii)) in
                    (let (blocktranslate :: bool) = False in
-                   return (level, result))))))))) \<bind> (\<lambda> varstup .  (let ((level :: ii), (result :: TLBRecord)) = varstup in
-              return (addrselectbottom, desc, descaddr, level, result)))))))))))))))))))))) \<bind> (\<lambda> varstup .  (let ((addrselectbottom ::
-            ii), (desc :: 64 bits), (descaddr :: AddressDescriptor), (level :: ii), (result ::
+                   return (addrselecttop, baseaddress, blocktranslate, level, result))))))))) \<bind> (\<lambda> varstup .  (let ((addrselecttop ::
+                ii), (baseaddress :: 52 bits), (blocktranslate :: bool), (level :: ii), (result ::
+                TLBRecord)) = varstup in
+              return (accdesc,
+                      addrselectbottom,
+                      addrselecttop,
+                      baseaddress,
+                      blocktranslate,
+                      desc,
+                      descaddr,
+                      descaddr2,
+                      level,
+                      result)))))))))))))))))))))) \<bind> (\<lambda> varstup .  (let ((accdesc :: AccessDescriptor), (addrselectbottom ::
+            ii), (addrselecttop :: ii), (baseaddress :: 52 bits), (blocktranslate :: bool), (desc :: 64
+            bits), (descaddr :: AddressDescriptor), (descaddr2 :: AddressDescriptor), (level :: ii), (result ::
             TLBRecord)) = varstup in
           if ((((ex_int level)) < ((ex_int firstblocklevel)))) then
             (let (tmp_260 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
@@ -11260,7 +11309,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
                else return result)
              else return result) \<bind> (\<lambda> (result :: TLBRecord) . 
             or_boolM
-              (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
+              (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
               (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii))))
                  (liftR (IsZero_slice desc outputsize
                            ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__46 ::
@@ -11280,7 +11329,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
               liftR (assert_exp True ('''')) \<then>
               ((let (outputaddress :: 52 bits) =
                 (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then
-                  (concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+                  (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                      ((slice_slice_concat (( 48 :: int)::ii) desc asb
                          ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb
                         ::  48 Word.word))
@@ -11308,7 +11357,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
                   (let ((desc :: 64 bits), (result :: TLBRecord)) =
                     (if ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
                       (let (desc :: 64 bits) =
-                        ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+                        ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                           ::  64 Word.word)) in
                       (let (tmp_320 :: DescriptorUpdate) = ((TLBRecord_descupdate   result)) in
                       (let (tmp_320 :: DescriptorUpdate) =
@@ -11334,7 +11383,7 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
               (let (contiguousbit :: 1 bits) =
                 ((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)]  ::  1 Word.word)) in
               (let (nG :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 :: int)::ii)]  ::  1 Word.word)) in
-              (let (sh :: 2 bits) = ((slice0 desc (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+              (let (sh :: 2 bits) = ((slice desc (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
               liftR ((undefined_bitvector (( 3 :: int)::ii)  :: ( 3 Word.word) M)) \<bind> (\<lambda> (ap :: 3 bits) . 
               (let (ap :: 3 bits) =
                 (if apply_nvnv1_effect then
@@ -11342,10 +11391,10 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
                      (vec_of_bits [B0,B1]  ::  2 Word.word)
                     ::  3 Word.word)
                 else
-                  (concat_vec ((slice0 desc (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                  (concat_vec ((slice desc (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                      (vec_of_bits [B1]  ::  1 Word.word)
                     ::  3 Word.word)) in
-              (let (memattr :: 4 bits) = ((slice0 desc (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+              (let (memattr :: 4 bits) = ((slice desc (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
               liftR ((undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__51 :: 4 bits) . 
               (let result = ((result (| TLBRecord_domain := w__51 |))) in
               (let result = ((result (| TLBRecord_level := level |))) in
@@ -11358,14 +11407,14 @@ definition AArch64_TranslationTableWalk_SecondStage  :: "(52)Word.word \<Rightar
                             ((ex_int grainsize))))))|))) in
               (let (tmp_480 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
               (let tmp_480 =
-                ((set_slice0 (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice0 ap (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                ((set_slice (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice ap (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                   ::  3 Word.word)) in
               (let (tmp_490 :: Permissions) = ((TLBRecord_perms   result)) in
               (let tmp_490 = ((tmp_490 (| Permissions_ap := tmp_480 |))) in
               (let result = ((result (| TLBRecord_perms := tmp_490 |))) in
               (let (tmp_500 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
               (let tmp_500 =
-                ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+                ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                   ::  3 Word.word)) in
               (let (tmp_510 :: Permissions) = ((TLBRecord_perms   result)) in
               (let tmp_510 = ((tmp_510 (| Permissions_ap := tmp_500 |))) in
@@ -11429,7 +11478,7 @@ definition AArch64_SecondStageTranslate  :: " AddressDescriptor \<Rightarrow>(64
    (undefined_bitvector (( 52 :: int)::ii)  :: ( 52 Word.word) M) \<bind> (\<lambda> (ipaddress :: 52 bits) . 
    if s2_enabled then
      (let ipaddress =
-       ((slice0(FullAddress_physicaladdress  (AddressDescriptor_paddress   S1)) (( 0 :: int)::ii) (( 52 :: int)::ii)  ::  52 Word.word)) in
+       ((slice(FullAddress_physicaladdress  (AddressDescriptor_paddress   S1)) (( 0 :: int)::ii) (( 52 :: int)::ii)  ::  52 Word.word)) in
      AArch64_TranslationTableWalk_SecondStage ipaddress vaddress acctype iswrite s2fs1walk size1 \<bind> (\<lambda> (w__3 ::
        TLBRecord) . 
      (let S2 = w__3 in
@@ -11603,7 +11652,7 @@ definition SSAdvance  :: " unit \<Rightarrow>((register_value),(unit),(exception
 definition ConditionHolds  :: "(4)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " ConditionHolds cond = (
    undefined_bool ()  \<bind> (\<lambda> (result :: bool) . 
-   (let b__0 = ((slice0 cond (( 1 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+   (let b__0 = ((slice cond (( 1 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
    (if (((b__0 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then
       read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . 
       (let (result :: bool) = ((ProcState_Z   w__0) = (vec_of_bits [B1]  ::  1 Word.word)) in
@@ -12037,31 +12086,31 @@ definition ConditionSyndrome  :: " unit \<Rightarrow>((register_value),((5)Word.
      read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
      if ((((ProcState_T   w__2) = (vec_of_bits [B0]  ::  1 Word.word)))) then
        (let syndrome =
-         ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  5 Word.word)) in
+         ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  5 Word.word)) in
        and_boolM ((ConditionHolds cond)) ((ConstrainUnpredictableBool Unpredictable_ESRCONDPASS)) \<bind> (\<lambda> (w__5 ::
          bool) . 
        (let (syndrome :: 5 bits) =
          (if w__5 then
-           (set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
+           (set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
              ::  5 Word.word)
-         else (set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond  ::  5 Word.word)) in
+         else (set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond  ::  5 Word.word)) in
        return syndrome)))
      else if ((IMPDEF_boolean (''Condition valid for trapped T32''))) then
        (let (syndrome :: 5 bits) =
-         ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  5 Word.word)) in
-       (let (syndrome :: 5 bits) = ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond  ::  5 Word.word)) in
+         ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  5 Word.word)) in
+       (let (syndrome :: 5 bits) = ((set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond  ::  5 Word.word)) in
        return syndrome))
      else
        (let syndrome =
-         ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  5 Word.word)) in
+         ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  5 Word.word)) in
        (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 ::  4 Word.word) . 
-       (let (syndrome :: 5 bits) = ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) w__6  ::  5 Word.word)) in
+       (let (syndrome :: 5 bits) = ((set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) w__6  ::  5 Word.word)) in
        return syndrome))))))
    else
      (let (syndrome :: 5 bits) =
-       ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  5 Word.word)) in
+       ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  5 Word.word)) in
      (let (syndrome :: 5 bits) =
-       ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
+       ((set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0]  ::  4 Word.word)
          ::  5 Word.word)) in
      return syndrome))))))"
 
@@ -12081,7 +12130,7 @@ definition BranchToAddr  :: "('N::len)Word.word \<Rightarrow> BranchType \<Right
      and_boolM (return (((((int (size target))) = (( 64 :: int)::ii)))))
        (UsingAArch32 ()  \<bind> (\<lambda> (w__2 :: bool) .  return ((\<not> w__2)))) \<bind> (\<lambda> (w__3 :: bool) . 
      assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \<then>
-     write_reg PC_ref ((slice0 target (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))))))"
+     write_reg PC_ref ((slice target (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))))))"
 
 
 (*val BadMode : mword ty5 -> M bool*)
@@ -12231,7 +12280,7 @@ definition ELFromSPSR  :: "(32)Word.word \<Rightarrow>((register_value),(bool*(2
    undefined_bool ()  \<bind> (\<lambda> (valid_name :: bool) . 
    (undefined_bitvector (( 2 :: int)::ii)  :: ( 2 Word.word) M) \<bind> (\<lambda> (el :: 2 bits) . 
    (if ((((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
-      (let el = ((slice0 spsr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+      (let el = ((slice spsr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
       (if ((HighestELUsingAArch32 () )) then return False
        else if ((\<not> ((HaveEL el)))) then return False
        else if ((((vec_of_bits [access_vec_dec spsr (( 1 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
@@ -12249,7 +12298,7 @@ definition ELFromSPSR  :: "(32)Word.word \<Rightarrow>((register_value),(bool*(2
       (let (valid_name :: bool) = False in
       return (el, valid_name))
     else
-      (ELFromM32 ((slice0 spsr (( 0 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word))  :: ((bool *  2 Word.word)) M) \<bind> (\<lambda> varstup .  (let (tup__0, tup__1) = varstup in
+      (ELFromM32 ((slice spsr (( 0 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word))  :: ((bool *  2 Word.word)) M) \<bind> (\<lambda> varstup .  (let (tup__0, tup__1) = varstup in
       (let (valid_name :: bool) = tup__0 in
       (let (el :: 2 bits) = tup__1 in
       return (el, valid_name)))))) \<bind> (\<lambda> varstup .  (let ((el :: 2 bits), (valid_name :: bool)) = varstup in
@@ -12580,21 +12629,21 @@ definition AArch64_vESBOperation  :: " unit \<Rightarrow>((register_value),(unit
      ((if w__12 then
         (read_reg VDFSR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
         (read_reg VDFSR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . 
-        (AArch32_ReportDeferredSError ((slice0 w__13 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+        (AArch32_ReportDeferredSError ((slice w__13 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
            (vec_of_bits [access_vec_dec w__14 (( 12 :: int)::ii)]  ::  1 Word.word)
           :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
         (let (VDISR :: 32 bits) = w__15 in
         return () ))))
       else
         (read_reg VSESR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . 
-        (AArch64_ReportDeferredSError ((slice0 w__16 (( 0 :: int)::ii) (( 25 :: int)::ii)  ::  25 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64
+        (AArch64_ReportDeferredSError ((slice w__16 (( 0 :: int)::ii) (( 25 :: int)::ii)  ::  25 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64
           bits) . 
         (let (VDISR_EL2 :: 64 bits) = w__17 in
         return () )))) \<then>
      (read_reg HCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__18 ::  64 Word.word) . 
      write_reg
        HCR_EL2_ref
-       ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) w__18 (( 8 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))))
+       ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) w__18 (( 8 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))))
    else return () ))))))))"
 
 
@@ -12732,6 +12781,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
       liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr :: AddressDescriptor) . 
       liftR ((undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (baseregister :: 64 bits) . 
       liftR ((undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (inputaddr :: 64 bits) . 
+      (let (tmp_170 :: FaultRecord) = ((AddressDescriptor_fault   descaddr)) in
+      (let tmp_170 = ((tmp_170 (| FaultRecord_typ := Fault_None |))) in
+      (let descaddr = ((descaddr (| AddressDescriptor_fault := tmp_170 |))) in
       (let (tmp_180 :: MemoryAttributes) = ((AddressDescriptor_memattrs   descaddr)) in
       (let tmp_180 = ((tmp_180 (| MemoryAttributes_typ := MemType_Normal |))) in
       (let descaddr = ((descaddr (| AddressDescriptor_memattrs := tmp_180 |))) in
@@ -12769,12 +12821,12 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
          (if ((((ProcState_EL   w__11) = EL3))) then
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__12 :: 32 bits) . 
             (let largegrain =
-              (((slice0 w__12 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+              (((slice w__12 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__13 :: 32 bits) . 
             (let midgrain =
-              (((slice0 w__13 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
+              (((slice w__13 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 bits) . 
-            (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__14 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+            (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__14 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
             (let inputsize_max =
               (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
               else (( 48 :: int)::ii)) in
@@ -12792,7 +12844,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                return inputsize)))
              else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . 
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__15 :: 32 bits) . 
-            (let ps = ((slice0 w__15 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+            (let ps = ((slice w__15 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
             and_boolM
               (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max))))))))
               (liftR ((IsZero_slice inputaddr inputsize
@@ -12805,9 +12857,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__19 :: 32 bits) . 
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__20 :: 32 bits) . 
             liftR ((read_reg TCR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__21 :: 32 bits) . 
-            liftR (WalkAttrDecode ((slice0 w__19 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                     ((slice0 w__20 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                     ((slice0 w__21 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__22 ::
+            liftR (WalkAttrDecode ((slice w__19 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                     ((slice w__20 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                     ((slice w__21 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__22 ::
               MemoryAttributes) . 
             (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__22 |))) in
             liftR ((read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__23 :: 32 bits) . 
@@ -12847,13 +12899,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
               (if ((((vec_of_bits [access_vec_dec inputaddr top1]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 bits) . 
                  (let largegrain =
-                   (((slice0 w__31 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+                   (((slice w__31 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__32 :: 64 bits) . 
                  (let midgrain =
-                   (((slice0 w__32 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
+                   (((slice w__32 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__33 :: 64 bits) . 
                  (let inputsize =
-                   ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__33 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+                   ((( 64 :: int)::ii) - ((Word.uint ((slice w__33 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
                  (let inputsize_max =
                    (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
                    else (( 48 :: int)::ii)) in
@@ -12889,9 +12941,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 :: 64 bits) . 
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__39 :: 64 bits) . 
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__40 :: 64 bits) . 
-                 liftR (WalkAttrDecode ((slice0 w__38 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                          ((slice0 w__39 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                          ((slice0 w__40 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__41 ::
+                 liftR (WalkAttrDecode ((slice w__38 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                          ((slice w__39 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                          ((slice w__40 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__41 ::
                    MemoryAttributes) . 
                  (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__41 |))) in
                  and_boolM (return ((AArch64_HaveHPDExt () )))
@@ -12909,13 +12961,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                else
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__44 :: 64 bits) . 
                  (let inputsize =
-                   ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__44 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+                   ((( 64 :: int)::ii) - ((Word.uint ((slice w__44 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__45 :: 64 bits) . 
                  (let largegrain =
-                   (((slice0 w__45 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)) in
+                   (((slice w__45 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)) in
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__46 :: 64 bits) . 
                  (let midgrain =
-                   (((slice0 w__46 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+                   (((slice w__46 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
                  (let inputsize_max =
                    (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
                    else (( 48 :: int)::ii)) in
@@ -12951,9 +13003,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__51 :: 64 bits) . 
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__52 :: 64 bits) . 
                  liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__53 :: 64 bits) . 
-                 liftR (WalkAttrDecode ((slice0 w__51 (( 28 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                          ((slice0 w__52 (( 26 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                          ((slice0 w__53 (( 24 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__54 ::
+                 liftR (WalkAttrDecode ((slice w__51 (( 28 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                          ((slice w__52 (( 26 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                          ((slice w__53 (( 24 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__54 ::
                    MemoryAttributes) . 
                  (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__54 |))) in
                  and_boolM (return ((AArch64_HaveHPDExt () )))
@@ -12971,7 +13023,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                 bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled ::
                 bool), (inputsize :: ii), (largegrain :: bool), (midgrain :: bool)) = varstup in
               liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__57 :: 64 bits) . 
-              (let ps = ((slice0 w__57 (( 32 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+              (let ps = ((slice w__57 (( 32 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
               liftR ((read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__58 :: 32 bits) . 
               (let reversedescriptors =
                 ((vec_of_bits [access_vec_dec w__58 (( 25 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)) in
@@ -13004,13 +13056,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
               if ((((ProcState_EL   w__63) = EL2))) then
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__64 :: 64 bits) . 
                 (let inputsize =
-                  ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__64 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+                  ((( 64 :: int)::ii) - ((Word.uint ((slice w__64 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__65 :: 64 bits) . 
                 (let largegrain =
-                  (((slice0 w__65 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+                  (((slice w__65 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__66 :: 64 bits) . 
                 (let midgrain =
-                  (((slice0 w__66 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
+                  (((slice w__66 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
                 (let inputsize_max =
                   (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
                   else (( 48 :: int)::ii)) in
@@ -13033,7 +13085,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                    return inputsize)))
                  else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . 
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__67 :: 64 bits) . 
-                (let ps = ((slice0 w__67 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+                (let ps = ((slice w__67 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
                 and_boolM
                   (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max))))))))
                   (liftR ((IsZero_slice inputaddr inputsize
@@ -13046,9 +13098,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__71 :: 64 bits) . 
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__72 :: 64 bits) . 
                 liftR ((read_reg TCR_EL2_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__73 :: 64 bits) . 
-                liftR (WalkAttrDecode ((slice0 w__71 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                         ((slice0 w__72 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                         ((slice0 w__73 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__74 ::
+                liftR (WalkAttrDecode ((slice w__71 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                         ((slice w__72 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                         ((slice w__73 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__74 ::
                   MemoryAttributes) . 
                 (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__74 |))) in
                 liftR ((read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__75 :: 32 bits) . 
@@ -13086,13 +13138,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                 (if ((((vec_of_bits [access_vec_dec inputaddr top1]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . 
                    (let inputsize =
-                     ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__82 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+                     ((( 64 :: int)::ii) - ((Word.uint ((slice w__82 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__83 :: 64 bits) . 
                    (let largegrain =
-                     (((slice0 w__83 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+                     (((slice w__83 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__84 :: 64 bits) . 
                    (let midgrain =
-                     (((slice0 w__84 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
+                     (((slice w__84 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
                    (let inputsize_max =
                      (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
                      else (( 48 :: int)::ii)) in
@@ -13128,9 +13180,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . 
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . 
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . 
-                   liftR (WalkAttrDecode ((slice0 w__89 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                            ((slice0 w__90 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                            ((slice0 w__91 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__92 ::
+                   liftR (WalkAttrDecode ((slice w__89 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                            ((slice w__90 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                            ((slice w__91 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__92 ::
                      MemoryAttributes) . 
                    (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__92 |))) in
                    and_boolM (return ((AArch64_HaveHPDExt () )))
@@ -13148,13 +13200,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  else
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__95 :: 64 bits) . 
                    (let inputsize =
-                     ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__95 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+                     ((( 64 :: int)::ii) - ((Word.uint ((slice w__95 (( 16 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__96 :: 64 bits) . 
                    (let largegrain =
-                     (((slice0 w__96 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)) in
+                     (((slice w__96 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)) in
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__97 :: 64 bits) . 
                    (let midgrain =
-                     (((slice0 w__97 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+                     (((slice w__97 (( 30 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
                    (let inputsize_max =
                      (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
                      else (( 48 :: int)::ii)) in
@@ -13190,9 +13242,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__102 :: 64 bits) . 
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__103 :: 64 bits) . 
                    liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__104 :: 64 bits) . 
-                   liftR (WalkAttrDecode ((slice0 w__102 (( 28 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                            ((slice0 w__103 (( 26 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                            ((slice0 w__104 (( 24 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__105 ::
+                   liftR (WalkAttrDecode ((slice w__102 (( 28 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                            ((slice w__103 (( 26 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                            ((slice w__104 (( 24 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__105 ::
                      MemoryAttributes) . 
                    (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__105 |))) in
                    and_boolM (return ((AArch64_HaveHPDExt () )))
@@ -13210,7 +13262,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                   bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled ::
                   bool), (inputsize :: ii), (largegrain :: bool), (midgrain :: bool)) = varstup in
                 liftR ((read_reg TCR_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__108 :: 64 bits) . 
-                (let ps = ((slice0 w__108 (( 32 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+                (let ps = ((slice w__108 (( 32 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
                 liftR ((read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__109 :: 32 bits) . 
                 (let reversedescriptors =
                   ((vec_of_bits [access_vec_dec w__109 (( 25 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)) in
@@ -13289,13 +13341,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
          liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__115 :: 64 bits) . 
          (let inputaddr = w__115 in
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__116 :: 32 bits) . 
-         (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__116 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
+         (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__116 (( 0 :: int)::ii) (( 6 :: int)::ii)  ::  6 Word.word))))) in
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__117 :: 32 bits) . 
          (let largegrain =
-           (((slice0 w__117 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+           (((slice w__117 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__118 :: 32 bits) . 
          (let midgrain =
-           (((slice0 w__118 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
+           (((slice w__118 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)) in
          (let inputsize_max =
            (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii)
            else (( 48 :: int)::ii)) in
@@ -13313,7 +13365,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
             return inputsize)))
           else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . 
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__119 :: 32 bits) . 
-         (let ps = ((slice0 w__119 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+         (let ps = ((slice w__119 (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
          and_boolM
            (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max))))))))
            (liftR ((IsZero_slice inputaddr inputsize
@@ -13326,9 +13378,9 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__123 :: 32 bits) . 
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__124 :: 32 bits) . 
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__125 :: 32 bits) . 
-         liftR (WalkAttrDecode ((slice0 w__123 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                  ((slice0 w__124 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
-                  ((slice0 w__125 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__126 ::
+         liftR (WalkAttrDecode ((slice w__123 (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                  ((slice w__124 (( 10 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                  ((slice w__125 (( 12 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) secondstage) \<bind> (\<lambda> (w__126 ::
            MemoryAttributes) . 
          (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__126 |))) in
          liftR ((read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__127 :: 32 bits) . 
@@ -13345,7 +13397,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
             return ((((vec_of_bits [access_vec_dec w__130 (( 22 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__131 :: bool) . 
          (let update_AP = w__131 in
          liftR ((read_reg VTCR_EL2_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__132 :: 32 bits) . 
-         (let startlevel = (Word.uint ((slice0 w__132 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
+         (let startlevel = (Word.uint ((slice w__132 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
          (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) =
            (if largegrain then
              (let (grainsize :: ii) = ((( 16 :: int)::ii)) in
@@ -13479,7 +13531,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
              (let z = (if ((baselowerbound < (( 6 :: int)::ii))) then (( 6 :: int)::ii) else baselowerbound) in
              liftR (assert_exp True ('''')) \<then>
              ((let (baseaddress :: 52 bits) =
-               ((concat_vec ((slice0 baseregister (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+               ((concat_vec ((slice baseregister (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                   ((slice_zeros_concat ((((((- z)) + (( 48 :: int)::ii))) + z))
                       baseregister z ((((- z)) + (( 48 :: int)::ii))) z
                      ::  48 Word.word))
@@ -13510,20 +13562,32 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
           liftR (undefined_bool () ) \<bind> (\<lambda> (hwupdatewalk :: bool) . 
           liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . 
           liftR (undefined_int () ) \<bind> (\<lambda> (addrselectbottom :: ii) . 
-          (untilM (addrselectbottom,
+          (untilM (accdesc,
+                   addrselectbottom,
+                   addrselecttop,
                    ap_table,
+                   baseaddress,
+                   blocktranslate,
                    desc,
                    descaddr,
+                   descaddr2,
+                   hwupdatewalk,
                    level,
                    ns_table,
                    pxn_table,
                    result,
                    xn_table)
             (\<lambda> varstup . 
-            (let (addrselectbottom,
+            (let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
                  ap_table,
+                 baseaddress,
+                 blocktranslate,
                  desc,
                  descaddr,
+                 descaddr2,
+                 hwupdatewalk,
                  level,
                  ns_table,
                  pxn_table,
@@ -13531,10 +13595,16 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  xn_table) = varstup in
               return blocktranslate))
             (\<lambda> varstup . 
-            (let (addrselectbottom,
+            (let (accdesc,
+                 addrselectbottom,
+                 addrselecttop,
                  ap_table,
+                 baseaddress,
+                 blocktranslate,
                  desc,
                  descaddr,
+                 descaddr2,
+                 hwupdatewalk,
                  level,
                  ns_table,
                  pxn_table,
@@ -13562,7 +13632,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                 bool) . 
               (if w__144 then
                  (let (descaddr2 :: AddressDescriptor) = descaddr in
-                 return (descaddr2, result))
+                 return (descaddr2, hwupdatewalk, result))
                else
                  (let hwupdatewalk = False in
                  liftR (AArch64_SecondStageWalk descaddr vaddress acctype iswrite (( 8 :: int)::ii)
@@ -13575,8 +13645,8 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                     (let result = ((result (| TLBRecord_addrdesc := tmp_230 |))) in
                     (early_return result :: (unit, TLBRecord) MR) \<then> return result)))
                   else return result) \<bind> (\<lambda> (result :: TLBRecord) . 
-                 return (descaddr2, result)))))) \<bind> (\<lambda> varstup .  (let ((descaddr2 :: AddressDescriptor), (result ::
-                TLBRecord)) = varstup in
+                 return (descaddr2, hwupdatewalk, result)))))) \<bind> (\<lambda> varstup .  (let ((descaddr2 ::
+                AddressDescriptor), (hwupdatewalk :: bool), (result :: TLBRecord)) = varstup in
               liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__146 :: 64 bits) . 
               (let descaddr2 = ((descaddr2 (| AddressDescriptor_vaddress := w__146 |))) in
               liftR (CreateAccessDescriptorPTW acctype secondstage s2fs1walk level) \<bind> (\<lambda> (w__147 ::
@@ -13587,7 +13657,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
               (let desc = w__148 in
               (if reversedescriptors then liftR ((BigEndianReverse desc  :: ( 64 Word.word) M))
                else return desc) \<bind> (\<lambda> (desc :: 64 bits) . 
-              (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) \<or> ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii))))))))))
+              (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) \<or> ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii))))))))))
                then
                  (let (tmp_240 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
                  liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage
@@ -13595,14 +13665,30 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  (let tmp_240 = ((tmp_240 (| AddressDescriptor_fault := w__150 |))) in
                  (let result = ((result (| TLBRecord_addrdesc := tmp_240 |))) in
                  (early_return result :: (unit, TLBRecord) MR) \<then>
-                 return (ap_table, level, ns_table, pxn_table, result, xn_table)))))
-               else if ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii)))))))
+                 return (addrselecttop,
+                         ap_table,
+                         baseaddress,
+                         blocktranslate,
+                         level,
+                         ns_table,
+                         pxn_table,
+                         result,
+                         xn_table)))))
+               else if ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii)))))))
                then
                  (let (blocktranslate :: bool) = True in
-                 return (ap_table, level, ns_table, pxn_table, result, xn_table))
+                 return (addrselecttop,
+                         ap_table,
+                         baseaddress,
+                         blocktranslate,
+                         level,
+                         ns_table,
+                         pxn_table,
+                         result,
+                         xn_table))
                else
                  or_boolM
-                   (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
+                   (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
                    (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii))))
                       (liftR (IsZero_slice desc outputsize
                                 ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__151 ::
@@ -13615,26 +13701,30 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                    (let tmp_250 = ((tmp_250 (| AddressDescriptor_fault := w__154 |))) in
                    (let result = ((result (| TLBRecord_addrdesc := tmp_250 |))) in
                    (early_return result :: (unit, TLBRecord) MR) \<then>
-                   return (ap_table, level, ns_table, pxn_table, result, xn_table)))))
+                   return (addrselecttop,
+                           ap_table,
+                           baseaddress,
+                           blocktranslate,
+                           level,
+                           ns_table,
+                           pxn_table,
+                           result,
+                           xn_table)))))
                  else
                    (let gsz = grainsize in
                    liftR (assert_exp True ('''')) \<then>
-                   ((let (_ :: unit) =
+                   ((let (baseaddress :: 52 bits) =
                      (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then
-                       (let (baseaddress :: 52 bits) =
-                         ((concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
-                            ((slice_zeros_concat
-                                ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc
-                                gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz
-                               ::  48 Word.word))
-                           ::  52 Word.word)) in
-                       () )
+                       (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+                          ((slice_zeros_concat
+                              ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc
+                              gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz
+                             ::  48 Word.word))
+                         ::  52 Word.word)
                      else
-                       (let (baseaddress :: 52 bits) =
-                         ((place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii)))
-                            gsz
-                           ::  52 Word.word)) in
-                       () )) in
+                       (place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii)))
+                          gsz
+                         ::  52 Word.word)) in
                    (let (ns_table :: 1 bits) =
                      (if ((\<not> secondstage)) then
                        (or_vec ns_table (vec_of_bits [access_vec_dec desc (( 63 :: int)::ii)]  ::  1 Word.word)
@@ -13643,7 +13733,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                    (let ((ap_table :: 2 bits), (pxn_table :: 1 bits), (xn_table :: 1 bits)) =
                      (if (((((\<not> secondstage)) \<and> ((\<not> hierattrsdisabled))))) then
                        (let (ap_table :: 2 bits) =
-                         ((set_slice0 (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 1 :: int)::ii)
+                         ((set_slice (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 1 :: int)::ii)
                             ((or_vec (vec_of_bits [access_vec_dec ap_table (( 1 :: int)::ii)]  ::  1 Word.word)
                                 (vec_of_bits [access_vec_dec desc (( 62 :: int)::ii)]  ::  1 Word.word)
                                ::  1 Word.word))
@@ -13670,7 +13760,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                                     (vec_of_bits [access_vec_dec desc (( 59 :: int)::ii)]  ::  1 Word.word)
                                    ::  1 Word.word)) in
                                (let (ap_table :: 2 bits) =
-                                 ((set_slice0 (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 0 :: int)::ii)
+                                 ((set_slice (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 0 :: int)::ii)
                                     ((or_vec
                                         (vec_of_bits [access_vec_dec ap_table (( 0 :: int)::ii)]  ::  1 Word.word)
                                         (vec_of_bits [access_vec_dec desc (( 61 :: int)::ii)]  ::  1 Word.word)
@@ -13685,20 +13775,36 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                    (let (level :: ii) = (((ex_int level)) + (( 1 :: int)::ii)) in
                    (let (addrselecttop :: ii) = (((ex_int addrselectbottom)) - (( 1 :: int)::ii)) in
                    (let (blocktranslate :: bool) = False in
-                   return (ap_table, level, ns_table, pxn_table, result, xn_table))))))))))) \<bind> (\<lambda> varstup .  (let ((ap_table :: 2
-                bits), (level :: ii), (ns_table :: 1 bits), (pxn_table :: 1 bits), (result ::
-                TLBRecord), (xn_table :: 1 bits)) = varstup in
-              return (addrselectbottom,
+                   return (addrselecttop,
+                           ap_table,
+                           baseaddress,
+                           blocktranslate,
+                           level,
+                           ns_table,
+                           pxn_table,
+                           result,
+                           xn_table))))))))))) \<bind> (\<lambda> varstup .  (let ((addrselecttop :: ii), (ap_table :: 2
+                bits), (baseaddress :: 52 bits), (blocktranslate :: bool), (level :: ii), (ns_table :: 1
+                bits), (pxn_table :: 1 bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in
+              return (accdesc,
+                      addrselectbottom,
+                      addrselecttop,
                       ap_table,
+                      baseaddress,
+                      blocktranslate,
                       desc,
                       descaddr,
+                      descaddr2,
+                      hwupdatewalk,
                       level,
                       ns_table,
                       pxn_table,
                       result,
-                      xn_table)))))))))))))))))))))))) \<bind> (\<lambda> varstup .  (let ((addrselectbottom :: ii), (ap_table :: 2
-            bits), (desc :: 64 bits), (descaddr :: AddressDescriptor), (level :: ii), (ns_table :: 1
-            bits), (pxn_table :: 1 bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in
+                      xn_table)))))))))))))))))))))))) \<bind> (\<lambda> varstup .  (let ((accdesc :: AccessDescriptor), (addrselectbottom ::
+            ii), (addrselecttop :: ii), (ap_table :: 2 bits), (baseaddress :: 52 bits), (blocktranslate ::
+            bool), (desc :: 64 bits), (descaddr :: AddressDescriptor), (descaddr2 ::
+            AddressDescriptor), (hwupdatewalk :: bool), (level :: ii), (ns_table :: 1 bits), (pxn_table :: 1
+            bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in
           if ((((ex_int level)) < ((ex_int firstblocklevel)))) then
             (let (tmp_260 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
             liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk) \<bind> (\<lambda> (w__155 ::
@@ -13726,7 +13832,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                else return result)
              else return result) \<bind> (\<lambda> (result :: TLBRecord) . 
             or_boolM
-              (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
+              (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))))))))
               (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii))))
                  (liftR (IsZero_slice desc outputsize
                            ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__158 ::
@@ -13747,7 +13853,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
               liftR (assert_exp True ('''')) \<then>
               ((let (outputaddress :: 52 bits) =
                 (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then
-                  (concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+                  (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
                      ((slice_slice_concat (( 48 :: int)::ii) desc asb
                          ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb
                         ::  48 Word.word))
@@ -13756,6 +13862,11 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                   (slice_slice_concat (( 52 :: int)::ii) desc asb ((((- asb)) + (( 48 :: int)::ii)))
                      inputaddr (( 0 :: int)::ii) asb
                     ::  52 Word.word)) in
+              (let (tmp_330 :: DescriptorUpdate) = ((TLBRecord_descupdate   result)) in
+              (let tmp_330 = ((tmp_330 (| DescriptorUpdate_AF := False |))) in
+              (let tmp_330 = ((tmp_330 (| DescriptorUpdate_AP := False |))) in
+              (let tmp_330 = ((tmp_330 (| DescriptorUpdate_descaddr := descaddr |))) in
+              (let result = ((result (| TLBRecord_descupdate := tmp_330 |))) in
               (if ((((vec_of_bits [access_vec_dec desc (( 10 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))) then
                  if ((\<not> update_AF)) then
                    (let (tmp_290 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
@@ -13775,7 +13886,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                   (let ((desc :: 64 bits), (result :: TLBRecord)) =
                     (if (((((\<not> secondstage)) \<and> ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word))))))) then
                       (let (desc :: 64 bits) =
-                        ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)
+                        ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)
                           ::  64 Word.word)) in
                       (let (tmp_310 :: DescriptorUpdate) = ((TLBRecord_descupdate   result)) in
                       (let (tmp_310 :: DescriptorUpdate) =
@@ -13786,7 +13897,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                       (let ((desc :: 64 bits), (result :: TLBRecord)) =
                         (if (((secondstage \<and> ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word))))))) then
                           (let (desc :: 64 bits) =
-                            ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+                            ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                               ::  64 Word.word)) in
                           (let (tmp_320 :: DescriptorUpdate) = ((TLBRecord_descupdate   result)) in
                           (let (tmp_320 :: DescriptorUpdate) =
@@ -13797,9 +13908,6 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                       (desc, result))) in
                   (desc, result))
                 else (desc, result)) in
-              (let (tmp_330 :: DescriptorUpdate) = ((TLBRecord_descupdate   result)) in
-              (let tmp_330 = ((tmp_330 (| DescriptorUpdate_descaddr := descaddr |))) in
-              (let result = ((result (| TLBRecord_descupdate := tmp_330 |))) in
               liftR ((undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (xn :: 1 bits) . 
               liftR ((undefined_bitvector (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (pxn :: 1 bits) . 
               (let ((pxn :: 1 bits), (xn :: 1 bits)) =
@@ -13814,7 +13922,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
               (let (contiguousbit :: 1 bits) =
                 ((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)]  ::  1 Word.word)) in
               (let (nG :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 :: int)::ii)]  ::  1 Word.word)) in
-              (let (sh :: 2 bits) = ((slice0 desc (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+              (let (sh :: 2 bits) = ((slice desc (( 8 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
               liftR ((undefined_bitvector (( 3 :: int)::ii)  :: ( 3 Word.word) M)) \<bind> (\<lambda> (ap :: 3 bits) . 
               (let (ap :: 3 bits) =
                 (if apply_nvnv1_effect then
@@ -13822,10 +13930,10 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                      (vec_of_bits [B0,B1]  ::  2 Word.word)
                     ::  3 Word.word)
                 else
-                  (concat_vec ((slice0 desc (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                  (concat_vec ((slice desc (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                      (vec_of_bits [B1]  ::  1 Word.word)
                     ::  3 Word.word)) in
-              (let (memattr :: 4 bits) = ((slice0 desc (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+              (let (memattr :: 4 bits) = ((slice desc (( 2 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
               liftR ((undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__163 :: 4 bits) . 
               (let result = ((result (| TLBRecord_domain := w__163 |))) in
               (let result = ((result (| TLBRecord_level := level |))) in
@@ -13843,7 +13951,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  (let result = ((result (| TLBRecord_perms := tmp_340 |))) in
                  (let (tmp_350 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
                  (let tmp_350 =
-                   ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_350 (( 2 :: int)::ii)
+                   ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_350 (( 2 :: int)::ii)
                       ((or_vec (vec_of_bits [access_vec_dec ap (( 2 :: int)::ii)]  ::  1 Word.word)
                           (vec_of_bits [access_vec_dec ap_table (( 1 :: int)::ii)]  ::  1 Word.word)
                          ::  1 Word.word))
@@ -13854,7 +13962,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                  (if ((\<not> singlepriv)) then
                     (let (tmp_370 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
                     (let tmp_370 =
-                      ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_370 (( 1 :: int)::ii)
+                      ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_370 (( 1 :: int)::ii)
                          ((and_vec (vec_of_bits [access_vec_dec ap (( 1 :: int)::ii)]  ::  1 Word.word)
                              ((not_vec (vec_of_bits [access_vec_dec ap_table (( 0 :: int)::ii)]  ::  1 Word.word)
                                 ::  1 Word.word))
@@ -13876,7 +13984,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                   else
                     (let (tmp_400 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
                     (let (tmp_400 :: 3 bits) =
-                      ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_400 (( 1 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+                      ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_400 (( 1 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                         ::  3 Word.word)) in
                     (let (tmp_410 :: Permissions) = ((TLBRecord_perms   result)) in
                     (let (tmp_410 :: Permissions) = ((tmp_410 (| Permissions_ap := tmp_400 |))) in
@@ -13890,13 +13998,13 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                     return result)))))))))) \<bind> (\<lambda> (result :: TLBRecord) . 
                  (let (tmp_430 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
                  (let tmp_430 =
-                   ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_430 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+                   ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_430 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                      ::  3 Word.word)) in
                  (let (tmp_440 :: Permissions) = ((TLBRecord_perms   result)) in
                  (let tmp_440 = ((tmp_440 (| Permissions_ap := tmp_430 |))) in
                  (let result = ((result (| TLBRecord_perms := tmp_440 |))) in
                  (let (tmp_450 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
-                 liftR (AArch64_S1AttrDecode sh ((slice0 memattr (( 0 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) acctype) \<bind> (\<lambda> (w__165 ::
+                 liftR (AArch64_S1AttrDecode sh ((slice memattr (( 0 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) acctype) \<bind> (\<lambda> (w__165 ::
                    MemoryAttributes) . 
                  (let (tmp_450 :: AddressDescriptor) =
                    ((tmp_450 (| AddressDescriptor_memattrs := w__165 |))) in
@@ -13915,14 +14023,14 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                else
                  (let (tmp_480 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
                  (let tmp_480 =
-                   ((set_slice0 (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice0 ap (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                   ((set_slice (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice ap (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                      ::  3 Word.word)) in
                  (let (tmp_490 :: Permissions) = ((TLBRecord_perms   result)) in
                  (let tmp_490 = ((tmp_490 (| Permissions_ap := tmp_480 |))) in
                  (let result = ((result (| TLBRecord_perms := tmp_490 |))) in
                  (let (tmp_500 :: 3 bits) = ((Permissions_ap  (TLBRecord_perms   result))) in
                  (let tmp_500 =
-                   ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+                   ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                      ::  3 Word.word)) in
                  (let (tmp_510 :: Permissions) = ((TLBRecord_perms   result)) in
                  (let tmp_510 = ((tmp_510 (| Permissions_ap := tmp_500 |))) in
@@ -13973,7 +14081,7 @@ definition AArch64_TranslationTableWalk  :: "(52)Word.word \<Rightarrow>(64)Word
                   (result (|
                     TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 :: int)::ii)]  ::  1 Word.word))|))
                 else result) in
-              return result))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))"
+              return result)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))"
 
 
 (*val IsZero_slice2 : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*)
@@ -14185,7 +14293,7 @@ definition AArch64_TranslateAddressS1Off  :: "(64)Word.word \<Rightarrow> AccTyp
      (let (tmp_2410 :: FullAddress) = ((AddressDescriptor_paddress  (TLBRecord_addrdesc   result))) in
      (let tmp_2410 =
        ((tmp_2410 (|
-         FullAddress_physicaladdress := ((slice0 vaddress (( 0 :: int)::ii) (( 52 :: int)::ii)  ::  52 Word.word))|))) in
+         FullAddress_physicaladdress := ((slice vaddress (( 0 :: int)::ii) (( 52 :: int)::ii)  ::  52 Word.word))|))) in
      (let (tmp_2420 :: AddressDescriptor) = ((TLBRecord_addrdesc   result)) in
      (let tmp_2420 = ((tmp_2420 (| AddressDescriptor_paddress := tmp_2410 |))) in
      (let result = ((result (| TLBRecord_addrdesc := tmp_2420 |))) in
@@ -14255,7 +14363,7 @@ definition AArch64_MaybeZeroRegisterUppers  :: " unit \<Rightarrow>((register_va
          read_reg R_ref \<bind> (\<lambda> (w__14 :: ( 64 bits) list) . 
          (let (tmp_30 :: 64 bits) = ((access_list_dec w__14 n  ::  64 Word.word)) in
          (let tmp_30 =
-           ((set_slice0 (( 64 :: int)::ii) (( 32 :: int)::ii) tmp_30 (( 32 :: int)::ii) ((Zeros__1 (( 32 :: int)::ii) ()   ::  32 Word.word))
+           ((set_slice (( 64 :: int)::ii) (( 32 :: int)::ii) tmp_30 (( 32 :: int)::ii) ((Zeros__1 (( 32 :: int)::ii) ()   ::  32 Word.word))
              ::  64 Word.word)) in
          read_reg R_ref \<bind> (\<lambda> (w__15 :: ( 64 Word.word) list) . 
          write_reg R_ref ((update_list_dec w__15 n tmp_30  :: ( 64 Word.word) list))))))
@@ -14315,7 +14423,7 @@ definition DCPSInstruction  :: "(2)Word.word \<Rightarrow>((register_value),(uni
          (read_reg SCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 ::  32 Word.word) . 
          write_reg
            SCR_ref
-           ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)))
+           ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)))
        else return () ) \<then>
       UsingAArch32 () ) \<bind> (\<lambda> (w__19 :: bool) . 
       assert_exp w__19 (''UsingAArch32()'') \<then>
@@ -14472,23 +14580,23 @@ definition AArch64_FaultSyndrome  :: " bool \<Rightarrow> FaultRecord \<Rightarr
    ((let (iss :: 25 bits) = ((Zeros__1 (( 25 :: int)::ii) ()   ::  25 Word.word)) in
    and_boolM (return ((HaveRASExt () ))) ((IsExternalSyncAbort__1 fault)) \<bind> (\<lambda> (w__1 :: bool) . 
    (let (iss :: 25 bits) =
-     (if w__1 then (set_slice0 (( 25 :: int)::ii) (( 2 :: int)::ii) iss (( 11 :: int)::ii)(FaultRecord_errortype   fault)  ::  25 Word.word)
+     (if w__1 then (set_slice (( 25 :: int)::ii) (( 2 :: int)::ii) iss (( 11 :: int)::ii)(FaultRecord_errortype   fault)  ::  25 Word.word)
      else iss) in
    (if d_side then
       and_boolM ((IsSecondStage fault)) (return ((\<not>(FaultRecord_s2fs1walk   fault)))) \<bind> (\<lambda> (w__3 ::
         bool) . 
       (if w__3 then
          (LSInstructionSyndrome ()   :: ( 11 Word.word) M) \<bind> (\<lambda> (w__4 ::  11 Word.word) . 
-         (let (iss :: 25 bits) = ((set_slice0 (( 25 :: int)::ii) (( 11 :: int)::ii) iss (( 14 :: int)::ii) w__4  ::  25 Word.word)) in
+         (let (iss :: 25 bits) = ((set_slice (( 25 :: int)::ii) (( 11 :: int)::ii) iss (( 14 :: int)::ii) w__4  ::  25 Word.word)) in
          return iss))
        else return iss) \<bind> (\<lambda> (iss :: 25 bits) . 
       (let (iss :: 25 bits) =
         (if (((((((FaultRecord_acctype   fault) = AccType_DC))) \<or> (((((((FaultRecord_acctype   fault) = AccType_IC))) \<or> ((((FaultRecord_acctype   fault) = AccType_AT))))))))) then
           (let (iss :: 25 bits) =
-            ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 8 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  25 Word.word)) in
-          (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  25 Word.word))
+            ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 8 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  25 Word.word)) in
+          (set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  25 Word.word))
         else
-          (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii)
+          (set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii)
              (if(FaultRecord_write   fault) then (vec_of_bits [B1]  ::  1 Word.word)
               else (vec_of_bits [B0]  ::  1 Word.word))
             ::  25 Word.word)) in
@@ -14496,16 +14604,16 @@ definition AArch64_FaultSyndrome  :: " bool \<Rightarrow> FaultRecord \<Rightarr
     else return iss) \<bind> (\<lambda> (iss :: 25 bits) . 
    IsExternalAbort__1 fault \<bind> (\<lambda> (w__5 :: bool) . 
    (let (iss :: 25 bits) =
-     (if w__5 then (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 9 :: int)::ii)(FaultRecord_extflag   fault)  ::  25 Word.word)
+     (if w__5 then (set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 9 :: int)::ii)(FaultRecord_extflag   fault)  ::  25 Word.word)
      else iss) in
    (let iss =
-     ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 7 :: int)::ii)
+     ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 7 :: int)::ii)
         (if(FaultRecord_s2fs1walk   fault) then (vec_of_bits [B1]  ::  1 Word.word)
          else (vec_of_bits [B0]  ::  1 Word.word))
        ::  25 Word.word)) in
    (EncodeLDFSC(FaultRecord_typ   fault)(FaultRecord_level   fault)  :: ( 6 Word.word) M) \<bind> (\<lambda> (w__6 ::
       6 Word.word) . 
-   (let (iss :: 25 bits) = ((set_slice0 (( 25 :: int)::ii) (( 6 :: int)::ii) iss (( 0 :: int)::ii) w__6  ::  25 Word.word)) in
+   (let (iss :: 25 bits) = ((set_slice (( 25 :: int)::ii) (( 6 :: int)::ii) iss (( 0 :: int)::ii) w__6  ::  25 Word.word)) in
    return iss)))))))))))"
 
 
@@ -14540,11 +14648,11 @@ definition AArch64_ExecutingATS1xPInstr  :: " unit \<Rightarrow>((register_value
      (undefined_bitvector (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (CRn :: 4 bits) . 
      (undefined_bitvector (( 3 :: int)::ii)  :: ( 3 Word.word) M) \<bind> (\<lambda> (op1 :: 3 bits) . 
      (let (w__0 :: bool) =
-       (if (((((slice0 instr (( 22 :: int)::ii) (( 10 :: int)::ii)  ::  10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0]  ::  10 Word.word)))) then
-         (let (op1 :: 3 bits) = ((slice0 instr (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
-         (let (CRn :: 4 bits) = ((slice0 instr (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
-         (let (CRm :: 4 bits) = ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
-         (let (op2 :: 3 bits) = ((slice0 instr (( 5 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+       (if (((((slice instr (( 22 :: int)::ii) (( 10 :: int)::ii)  ::  10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0]  ::  10 Word.word)))) then
+         (let (op1 :: 3 bits) = ((slice instr (( 16 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+         (let (CRn :: 4 bits) = ((slice instr (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+         (let (CRm :: 4 bits) = ((slice instr (( 8 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+         (let (op2 :: 3 bits) = ((slice instr (( 5 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
          ((((((((((op1 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((CRn = (vec_of_bits [B0,B1,B1,B1]  ::  4 Word.word))))))) \<and> (((CRm = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word))))))) \<and> ((((((op2 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<or> (((op2 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))))))))
        else False) in
      return w__0)))))))"
@@ -14692,13 +14800,13 @@ definition AArch64_ReportException  :: " ExceptionRecord \<Rightarrow>(2)Word.wo
        (read_reg HPFAR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
        write_reg
          HPFAR_EL2_ref
-         ((set_slice0 (( 64 :: int)::ii) (( 40 :: int)::ii) w__1 (( 4 :: int)::ii)
-             ((slice0(ExceptionRecord_ipaddress   exception) (( 12 :: int)::ii) (( 40 :: int)::ii)  ::  40 Word.word))
+         ((set_slice (( 64 :: int)::ii) (( 40 :: int)::ii) w__1 (( 4 :: int)::ii)
+             ((slice(ExceptionRecord_ipaddress   exception) (( 12 :: int)::ii) (( 40 :: int)::ii)  ::  40 Word.word))
             ::  64 Word.word)))
      else
        (read_reg HPFAR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
        (undefined_bitvector (( 40 :: int)::ii)  :: ( 40 Word.word) M) \<bind> (\<lambda> (w__3 ::  40 Word.word) . 
-       write_reg HPFAR_EL2_ref ((set_slice0 (( 64 :: int)::ii) (( 40 :: int)::ii) w__2 (( 4 :: int)::ii) w__3  ::  64 Word.word))))
+       write_reg HPFAR_EL2_ref ((set_slice (( 64 :: int)::ii) (( 40 :: int)::ii) w__2 (( 4 :: int)::ii) w__3  ::  64 Word.word))))
    else return () )))))))))))"
 
 
@@ -14777,59 +14885,65 @@ definition AArch64_ESBOperation  :: " unit \<Rightarrow>((register_value),(unit)
 definition AArch64_CheckAndUpdateDescriptor  :: " DescriptorUpdate \<Rightarrow> FaultRecord \<Rightarrow> bool \<Rightarrow>(64)Word.word \<Rightarrow> AccType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(FaultRecord),(exception))monad "  where 
      " AArch64_CheckAndUpdateDescriptor result fault secondstage vaddress acctype iswrite s2fs1walk hwupdatewalk__arg = (
    catch_early_return
-     ((let hwupdatewalk = hwupdatewalk__arg in
-     liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AF :: bool) . 
-     (let (hw_update_AF :: bool) =
-       (if(DescriptorUpdate_AF   result) then
-         if ((((FaultRecord_typ   fault) = Fault_None))) then True
-         else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then True
-         else False
-       else hw_update_AF) in
-     liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AP :: bool) . 
-     liftR (undefined_bool () ) \<bind> (\<lambda> (write_perm_req :: bool) . 
-     (let (hw_update_AP :: bool) =
-       (if ((((DescriptorUpdate_AP   result) \<and> ((((FaultRecord_typ   fault) = Fault_None)))))) then
-         (let (write_perm_req :: bool) =
-           ((((iswrite \<or> ((((((acctype = AccType_ATOMICRW))) \<or> (((acctype = AccType_ORDEREDRW))))))))) \<and> ((\<not> s2fs1walk))) in
-         ((((write_perm_req \<and> ((\<not> ((((((acctype = AccType_AT))) \<or> (((acctype = AccType_DC))))))))))) \<or> hwupdatewalk))
-       else False) in
-     liftR ((undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (desc :: 64 bits) . 
-     liftR (undefined_AccessDescriptor () ) \<bind> (\<lambda> (accdesc :: AccessDescriptor) . 
-     liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . 
-     (if (((hw_update_AF \<or> hw_update_AP))) then
-        or_boolM (return secondstage)
-          (liftR (HasS2Translation () ) \<bind> (\<lambda> (w__0 :: bool) .  return ((\<not> w__0)))) \<bind> (\<lambda> (w__1 ::
-          bool) . 
-        (if w__1 then
-           (let (descaddr2 :: AddressDescriptor) = ((DescriptorUpdate_descaddr   result)) in
-           return descaddr2)
-         else
-           (let hwupdatewalk = True in
-           liftR (AArch64_SecondStageWalk(DescriptorUpdate_descaddr   result) vaddress acctype iswrite
-                    (( 8 :: int)::ii) hwupdatewalk) \<bind> (\<lambda> (w__2 :: AddressDescriptor) . 
-           (let descaddr2 = w__2 in
-           (if ((IsFault descaddr2)) then
-              (early_return(AddressDescriptor_fault   descaddr2) :: (unit, FaultRecord) MR)
-            else return () ) \<then>
-           return descaddr2)))) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . 
-        liftR (CreateAccessDescriptor AccType_ATOMICRW) \<bind> (\<lambda> (w__3 :: AccessDescriptor) . 
-        (let accdesc = w__3 in
-        liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 bits) . 
-        (let desc = w__4 in
-        (let (desc :: 64 bits) =
-          (if hw_update_AF then
-            (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)
-          else desc) in
-        (let (desc :: 64 bits) =
-          (if hw_update_AP then
-            (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii)
-               (if secondstage then (vec_of_bits [B1]  ::  1 Word.word)
-                else (vec_of_bits [B0]  ::  1 Word.word))
-              ::  64 Word.word)
-          else desc) in
-        liftR (aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc)))))))))
-      else return () ) \<then>
-     return fault)))))))))))"
+     (liftR ((aget_SCTLR__1 ()   :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__0 ::  32 Word.word) . 
+      (let reversedescriptors = (((access_vec_dec w__0 (( 25 :: int)::ii))) = B1) in
+      (let hwupdatewalk = hwupdatewalk__arg in
+      liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AF :: bool) . 
+      (let (hw_update_AF :: bool) =
+        (if(DescriptorUpdate_AF   result) then
+          if ((((FaultRecord_typ   fault) = Fault_None))) then True
+          else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then True
+          else False
+        else False) in
+      liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AP :: bool) . 
+      liftR (undefined_bool () ) \<bind> (\<lambda> (write_perm_req :: bool) . 
+      (let (hw_update_AP :: bool) =
+        (if ((((DescriptorUpdate_AP   result) \<and> ((((FaultRecord_typ   fault) = Fault_None)))))) then
+          (let (write_perm_req :: bool) =
+            ((((iswrite \<or> ((((((acctype = AccType_ATOMICRW))) \<or> (((acctype = AccType_ORDEREDRW))))))))) \<and> ((\<not> s2fs1walk))) in
+          ((((write_perm_req \<and> ((\<not> ((((((acctype = AccType_AT))) \<or> (((acctype = AccType_DC))))))))))) \<or> hwupdatewalk))
+        else False) in
+      liftR ((undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (desc :: 64 bits) . 
+      liftR (undefined_AccessDescriptor () ) \<bind> (\<lambda> (accdesc :: AccessDescriptor) . 
+      liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . 
+      (if (((hw_update_AF \<or> hw_update_AP))) then
+         or_boolM (return secondstage)
+           (liftR (HasS2Translation () ) \<bind> (\<lambda> (w__1 :: bool) .  return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 ::
+           bool) . 
+         (if w__2 then
+            (let (descaddr2 :: AddressDescriptor) = ((DescriptorUpdate_descaddr   result)) in
+            return descaddr2)
+          else
+            (let hwupdatewalk = True in
+            liftR (AArch64_SecondStageWalk(DescriptorUpdate_descaddr   result) vaddress acctype iswrite
+                     (( 8 :: int)::ii) hwupdatewalk) \<bind> (\<lambda> (w__3 :: AddressDescriptor) . 
+            (let descaddr2 = w__3 in
+            (if ((IsFault descaddr2)) then
+               (early_return(AddressDescriptor_fault   descaddr2) :: (unit, FaultRecord) MR)
+             else return () ) \<then>
+            return descaddr2)))) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . 
+         liftR (CreateAccessDescriptor AccType_ATOMICRW) \<bind> (\<lambda> (w__4 :: AccessDescriptor) . 
+         (let accdesc = w__4 in
+         liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         (let desc = w__5 in
+         (if reversedescriptors then liftR ((BigEndianReverse desc  :: ( 64 Word.word) M))
+          else return desc) \<bind> (\<lambda> (desc :: 64 bits) . 
+         (let (desc :: 64 bits) =
+           (if hw_update_AF then
+             (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)
+           else desc) in
+         (let (desc :: 64 bits) =
+           (if hw_update_AP then
+             (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii)
+                (if secondstage then (vec_of_bits [B1]  ::  1 Word.word)
+                 else (vec_of_bits [B0]  ::  1 Word.word))
+               ::  64 Word.word)
+           else desc) in
+         (if reversedescriptors then liftR ((BigEndianReverse desc  :: ( 64 Word.word) M))
+          else return desc) \<bind> (\<lambda> (desc :: 64 bits) . 
+         liftR (aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc)))))))))))
+       else return () ) \<then>
+      return fault)))))))))))))"
 
 
 (*val AArch64_BreakpointValueMatch : ii -> mword ty64 -> bool -> bool*)
@@ -14876,9 +14990,9 @@ definition AArch64_StateMatch  :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ
         (let tmp_50 = tup__1 in
         (let (tmp_60 :: 5 bits) = tmp_50 in
         (let HMC = ((vec_of_bits [access_vec_dec tmp_60 (( 4 :: int)::ii)]  ::  1 Word.word)) in
-        (let (tmp_70 :: 4 bits) = ((slice0 tmp_60 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
-        (let SSC = ((slice0 tmp_70 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
-        (let PxC = ((slice0 tmp_70 (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+        (let (tmp_70 :: 4 bits) = ((slice tmp_60 (( 0 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+        (let SSC = ((slice tmp_70 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+        (let PxC = ((slice tmp_70 (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
         (liftR (assert_exp ((((((c = Constraint_DISABLED))) \<or> (((c = Constraint_UNKNOWN)))))) (''((c == Constraint_DISABLED) || (c == Constraint_UNKNOWN))'')) \<then>
         (if (((c = Constraint_DISABLED))) then (early_return False :: (unit, bool) MR)
          else return () )) \<then>
@@ -14896,9 +15010,14 @@ definition AArch64_StateMatch  :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ
      (if (((((\<not> ispriv)) \<and> ((\<not> isbreakpnt))))) then return EL0_match
       else
         liftR (read_reg PSTATE_ref) \<bind> (\<lambda> (w__1 :: ProcState) . 
-        (let (priv_match :: bool) = 
-  ((case (ProcState_EL   w__1) of   EL31 => EL3_match )) in
-        return priv_match))) \<bind> (\<lambda> (priv_match :: bool) . 
+        (let p__294 = ((ProcState_EL   w__1)) in
+        (let pat0 = p__294 in
+        (let (priv_match :: bool) =
+          (if (((pat0 = EL3))) then EL3_match
+          else if (((pat0 = EL2))) then EL2_match
+          else if (((pat0 = EL1))) then EL1_match
+          else EL0_match) in
+        return priv_match))))) \<bind> (\<lambda> (priv_match :: bool) . 
      liftR (undefined_bool () ) \<bind> (\<lambda> (security_state_match :: bool) . 
      (let b__0 = SSC in
      (if (((b__0 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then return True
@@ -14916,10 +15035,10 @@ definition AArch64_StateMatch  :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ
         liftR ((read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 bits) . 
         liftR ((read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 bits) . 
         (let first_ctx_cmp =
-          (((Word.uint ((slice0 w__4 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))) -
-            ((Word.uint ((slice0 w__5 (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))) in
+          (((Word.uint ((slice w__4 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))) -
+            ((Word.uint ((slice w__5 (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))))) in
         liftR ((read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 bits) . 
-        (let last_ctx_cmp = (Word.uint ((slice0 w__6 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))) in
+        (let last_ctx_cmp = (Word.uint ((slice w__6 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))) in
         if (((((((ex_int lbn)) < ((ex_int first_ctx_cmp)))) \<or> ((((ex_int lbn)) > ((ex_int last_ctx_cmp))))))) then
           liftR (ConstrainUnpredictableInteger first_ctx_cmp last_ctx_cmp Unpredictable_BPNOTCTXCMP) \<bind> (\<lambda> varstup .  (let (tup__0, tup__1) = varstup in
           (let c = tup__0 in
@@ -14953,7 +15072,7 @@ definition AArch64_WatchpointMatch  :: " int \<Rightarrow>(64)Word.word \<Righta
    ELUsingAArch32 w__0 \<bind> (\<lambda> (w__1 :: bool) . 
    (assert_exp ((\<not> w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \<then>
    (read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 bits) . 
-   (assert_exp ((n \<le> ((Word.uint ((slice0 w__2 (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).WRPs))'') \<then>
+   (assert_exp ((n \<le> ((Word.uint ((slice w__2 (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).WRPs))'') \<then>
    read_reg DBGWCR_EL1_ref) \<bind> (\<lambda> (w__3 :: ( 32 bits) list) . 
    (let (enabled :: bool) =
      ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n  ::  32 Word.word)) (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)) in
@@ -14965,15 +15084,15 @@ definition AArch64_WatchpointMatch  :: " int \<Rightarrow>(64)Word.word \<Righta
    read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__6 :: ( 32 bits) list) . 
    read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__7 :: ( 32 bits) list) . 
    read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__8 :: ( 32 bits) list) . 
-   AArch64_StateMatch ((slice0 ((access_list_dec w__5 n  ::  32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+   AArch64_StateMatch ((slice ((access_list_dec w__5 n  ::  32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
      (vec_of_bits [access_vec_dec ((access_list_dec w__6 n  ::  32 Word.word)) (( 13 :: int)::ii)]  ::  1 Word.word)
-     ((slice0 ((access_list_dec w__7 n  ::  32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) linked
-     ((slice0 ((access_list_dec w__8 n  ::  32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) isbreakpnt
+     ((slice ((access_list_dec w__7 n  ::  32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) linked
+     ((slice ((access_list_dec w__8 n  ::  32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) isbreakpnt
      ispriv \<bind> (\<lambda> (state_match :: bool) . 
    read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__9 :: ( 32 bits) list) . 
    (let (ls_match :: bool) =
      ((vec_of_bits [access_vec_dec
-                       ((slice0 ((access_list_dec w__9 n  ::  32 Word.word)) (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+                       ((slice ((access_list_dec w__9 n  ::  32 Word.word)) (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
                        (if iswrite then (( 1 :: int)::ii)
                         else (( 0 :: int)::ii))]
          ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)) in
@@ -14994,7 +15113,7 @@ definition AArch64_BreakpointMatch  :: " int \<Rightarrow>(64)Word.word \<Righta
    ELUsingAArch32 w__0 \<bind> (\<lambda> (w__1 :: bool) . 
    (assert_exp ((\<not> w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \<then>
    (read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 bits) . 
-   (assert_exp ((n \<le> ((Word.uint ((slice0 w__2 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).BRPs))'') \<then>
+   (assert_exp ((n \<le> ((Word.uint ((slice w__2 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).BRPs))'') \<then>
    read_reg DBGBCR_EL1_ref) \<bind> (\<lambda> (w__3 :: ( 32 bits) list) . 
    (let (enabled :: bool) =
      ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n  ::  32 Word.word)) (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)) in
@@ -15002,7 +15121,7 @@ definition AArch64_BreakpointMatch  :: " int \<Rightarrow>(64)Word.word \<Righta
    (let (ispriv :: bool) = ((ProcState_EL   w__4) \<noteq> EL0) in
    read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__5 :: ( 32 bits) list) . 
    (let (linked :: bool) =
-     (((and_vec ((slice0 ((access_list_dec w__5 n  ::  32 Word.word)) (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
+     (((and_vec ((slice ((access_list_dec w__5 n  ::  32 Word.word)) (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))
            (vec_of_bits [B1,B0,B1,B1]  ::  4 Word.word)
           ::  4 Word.word)) = (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word)) in
    (let (isbreakpnt :: bool) = True in
@@ -15011,10 +15130,10 @@ definition AArch64_BreakpointMatch  :: " int \<Rightarrow>(64)Word.word \<Righta
    read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__7 :: ( 32 bits) list) . 
    read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__8 :: ( 32 bits) list) . 
    read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__9 :: ( 32 bits) list) . 
-   AArch64_StateMatch ((slice0 ((access_list_dec w__6 n  ::  32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
+   AArch64_StateMatch ((slice ((access_list_dec w__6 n  ::  32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))
      (vec_of_bits [access_vec_dec ((access_list_dec w__7 n  ::  32 Word.word)) (( 13 :: int)::ii)]  ::  1 Word.word)
-     ((slice0 ((access_list_dec w__8 n  ::  32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) linked
-     ((slice0 ((access_list_dec w__9 n  ::  32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) isbreakpnt
+     ((slice ((access_list_dec w__8 n  ::  32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) linked
+     ((slice ((access_list_dec w__9 n  ::  32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) isbreakpnt
      ispriv \<bind> (\<lambda> (state_match :: bool) . 
    (let (value_match_name :: bool) = (AArch64_BreakpointValueMatch n vaddress linked_to) in
    undefined_bool ()  \<bind> (\<lambda> (match_i :: bool) . 
@@ -15028,7 +15147,7 @@ definition AArch64_BreakpointMatch  :: " int \<Rightarrow>(64)Word.word \<Righta
    and_boolM
      (return ((((vec_of_bits [access_vec_dec vaddress (( 1 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))))
      (read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__11 :: ( 32 bits) list) . 
-      return (((((slice0 ((access_list_dec w__11 n  ::  32 Word.word)) (( 5 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      return (((((slice ((access_list_dec w__11 n  ::  32 Word.word)) (( 5 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B1,B1,B1]  ::  4 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
    (if w__12 then
       if value_match_name then ConstrainUnpredictableBool Unpredictable_BPMATCHHALF
       else return value_match_name
@@ -15051,12 +15170,13 @@ definition AArch64_CheckBreakpoint  :: "(64)Word.word \<Rightarrow> int \<Righta
    ((let (val_match :: bool) = False in
    undefined_bool ()  \<bind> (\<lambda> (match_i :: bool) . 
    (read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
-   (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice0 w__5 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))) (( 1 :: int)::ii)) val_match
-     (\<lambda> i val_match . 
+   (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice w__5 (( 12 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))) (( 1 :: int)::ii)) (match_i,
+                                                                                             val_match)
+     (\<lambda> i varstup .  (let (match_i, val_match) = varstup in
        AArch64_BreakpointMatch i vaddress size1 \<bind> (\<lambda> (w__6 :: bool) . 
        (let (match_i :: bool) = w__6 in
        (let (val_match :: bool) = (val_match \<or> match_i) in
-       return val_match))))) \<bind> (\<lambda> (val_match :: bool) . 
+       return (match_i, val_match))))))) \<bind> (\<lambda> varstup .  (let ((match_i :: bool), (val_match :: bool)) = varstup in
    undefined_bool ()  \<bind> (\<lambda> (iswrite :: bool) . 
    undefined_AccType ()  \<bind> (\<lambda> (acctype :: AccType) . 
    (undefined_bitvector (( 6 :: int)::ii)  :: ( 6 Word.word) M) \<bind> (\<lambda> (reason :: 6 bits) . 
@@ -15074,7 +15194,7 @@ definition AArch64_CheckBreakpoint  :: "(64)Word.word \<Rightarrow> int \<Righta
        (let acctype = AccType_IFETCH in
        (let iswrite = False in
        AArch64_DebugFault acctype iswrite))
-     else AArch64_NoFault () ))))))))))))))"
+     else AArch64_NoFault () )))))))))))))))"
 
 
 (*val AArch64_BranchAddr : mword ty64 -> M (mword ty64)*)
@@ -15119,7 +15239,7 @@ definition BranchTo  :: "('N::len)Word.word \<Rightarrow> BranchType \<Rightarro
      and_boolM (return (((((int (size target))) = (( 64 :: int)::ii)))))
        (UsingAArch32 ()  \<bind> (\<lambda> (w__2 :: bool) .  return ((\<not> w__2)))) \<bind> (\<lambda> (w__3 :: bool) . 
      (assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \<then>
-     (AArch64_BranchAddr ((slice0 target (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64
+     (AArch64_BranchAddr ((slice target (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64
        bits) . 
      write_reg PC_ref w__4)))))"
 
@@ -15475,7 +15595,7 @@ definition AArch64_TakeException  :: "(2)Word.word \<Rightarrow> ExceptionRecord
     else return () ) \<then>
    (aget_VBAR__1 ()   :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__37 ::  64 Word.word) . 
    (BranchTo
-     ((concat_vec ((slice0 w__37 (( 11 :: int)::ii) (( 53 :: int)::ii)  ::  53 Word.word))
+     ((concat_vec ((slice w__37 (( 11 :: int)::ii) (( 53 :: int)::ii)  ::  53 Word.word))
          ((GetSlice_int ((make_the_value (( 11 :: int)::ii)  ::  11 itself)) vect_offset (( 0 :: int)::ii)  ::  11 Word.word))
         ::  64 Word.word)) BranchType_EXCEPTION \<then>
    undefined_bool () ) \<bind> (\<lambda> (iesb_req :: bool) . 
@@ -15522,7 +15642,7 @@ definition Strip  :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>((register_v
      ((replicate_bits (vec_of_bits [access_vec_dec A (( 55 :: int)::ii)]  ::  1 Word.word) (( 64 :: int)::ii)  ::  64 Word.word)) in
    (let (original_ptr :: 64 bits) =
      (if tbi then
-       (concat_vec ((slice0 A (( 56 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
+       (concat_vec ((slice A (( 56 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
           ((slice_slice_concat (( 56 :: int)::ii) extfield (( 0 :: int)::ii)
               ((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) A (( 0 :: int)::ii) bottom_PAC_bit
              ::  56 Word.word))
@@ -15531,45 +15651,53 @@ definition Strip  :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>((register_v
        (slice_slice_concat (( 64 :: int)::ii) extfield (( 0 :: int)::ii)
           ((((- bottom_PAC_bit)) + (( 64 :: int)::ii))) A (( 0 :: int)::ii) bottom_PAC_bit
          ::  64 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) .  
-  (case (ProcState_EL   w__1) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__2 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__4 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     and_boolM
-       (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-          (IsSecure ()  \<bind>
-             (\<lambda> (w__5 :: bool) .  return ((\<not> w__5)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__7 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__7 (( 41 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-       (\<lambda> (w__8 :: bool) . 
-        (let TrapEL2 = w__8 in
-        and_boolM (return ((HaveEL EL3)))
-          ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-             (\<lambda> (w__9 :: 32 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__9 (( 17 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__10 :: bool) . 
-           (let (TrapEL3 :: bool) = w__10 in return (TrapEL2, TrapEL3))))))
-  ) \<bind> (\<lambda> varstup .  (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . 
+   (let p__293 = ((ProcState_EL   w__1)) in
+   (let pat0 = p__293 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__5 :: bool) .  return ((\<not> w__5)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__7 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__8 :: bool) . 
+      (let TrapEL2 = w__8 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__9 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__10 :: bool) . 
+      (let (TrapEL3 :: bool) = w__10 in
+      return (TrapEL2, TrapEL3))))))
+    else if (((pat0 = EL1))) then
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__11 :: bool) .  return ((\<not> w__11)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let TrapEL2 = w__14 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__15 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__16 :: bool) . 
+      (let (TrapEL3 :: bool) = w__16 in
+      return (TrapEL2, TrapEL3)))))
+    else if (((pat0 = EL2))) then
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__17 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__18 :: bool) . 
+      (let (TrapEL3 :: bool) = w__18 in
+      return (TrapEL2, TrapEL3))))
+    else
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (TrapEL2, TrapEL3)))) \<bind> (\<lambda> varstup .  (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
    if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else return original_ptr))))))))))))))"
+   else return original_ptr))))))))))))))))"
 
 
 (*val aarch64_integer_pac_strip_dp_1src : ii -> bool -> M unit*)
@@ -15602,64 +15730,71 @@ definition AuthIB  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r
    (read_reg APIBKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APIBKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APIBKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 30 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 30 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__292 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__292 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 30 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 30 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (Auth X Y APIBKey_EL1 False (vec_of_bits [B1]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))"
+   else (Auth X Y APIBKey_EL1 False (vec_of_bits [B1]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_autib_dp_1src : ii -> ii -> bool -> M unit*)
@@ -15729,64 +15864,71 @@ definition AuthIA  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r
    (read_reg APIAKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APIAKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APIAKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 31 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 31 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__291 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__291 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 31 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 31 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (Auth X Y APIAKey_EL1 False (vec_of_bits [B0]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))"
+   else (Auth X Y APIAKey_EL1 False (vec_of_bits [B0]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_autia_dp_1src : ii -> ii -> bool -> M unit*)
@@ -15876,64 +16018,71 @@ definition AuthDB  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r
    (read_reg APDBKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APDBKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APDBKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 13 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 13 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__290 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__290 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 13 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 13 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (Auth X Y APDBKey_EL1 True (vec_of_bits [B1]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))"
+   else (Auth X Y APDBKey_EL1 True (vec_of_bits [B1]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_autdb_dp_1src : ii -> ii -> bool -> M unit*)
@@ -15960,64 +16109,71 @@ definition AuthDA  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r
    (read_reg APDAKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APDAKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APDAKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 27 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 27 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__289 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__289 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (Auth X Y APDAKey_EL1 True (vec_of_bits [B0]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))"
+   else (Auth X Y APDAKey_EL1 True (vec_of_bits [B0]  ::  1 Word.word)  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_autda_dp_1src : ii -> ii -> bool -> M unit*)
@@ -16044,64 +16200,71 @@ definition AddPACIB  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(
    (read_reg APIBKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APIBKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APIBKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 30 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 30 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__288 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__288 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 30 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 30 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (AddPAC X Y APIBKey_EL1 False  :: ( 64 Word.word) M)))))))))))"
+   else (AddPAC X Y APIBKey_EL1 False  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_pacib_dp_1src : ii -> ii -> bool -> M unit*)
@@ -16171,64 +16334,71 @@ definition AddPACIA  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(
    (read_reg APIAKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APIAKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APIAKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 31 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 31 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__287 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__287 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 31 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 31 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (AddPAC X Y APIAKey_EL1 False  :: ( 64 Word.word) M)))))))))))"
+   else (AddPAC X Y APIAKey_EL1 False  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_pacia_dp_1src : ii -> ii -> bool -> M unit*)
@@ -16297,52 +16467,61 @@ definition AddPACGA  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(
    (read_reg APGAKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APGAKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APGAKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     and_boolM
-       (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-          (IsSecure ()  \<bind>
-             (\<lambda> (w__6 :: bool) .  return ((\<not> w__6)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__8 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__8 (( 41 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-       (\<lambda> (w__9 :: bool) . 
-        (let TrapEL2 = w__9 in
-        (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-          (\<lambda> (w__10 :: 32 bits) . 
-           (let (TrapEL3 :: bool) =
-                ((vec_of_bits [access_vec_dec w__10 (( 17 :: int):: ii)] :: 1 Word.word)
-                   = (vec_of_bits [B0] :: 1 Word.word)) in
-           return (TrapEL2, TrapEL3))))))
-  ) \<bind> (\<lambda> varstup .  (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__286 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__286 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__6 :: bool) .  return ((\<not> w__6)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__8 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__9 :: bool) . 
+      (let TrapEL2 = w__9 in
+      (read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . 
+      (let (TrapEL3 :: bool) =
+        ((vec_of_bits [access_vec_dec w__10 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)) in
+      return (TrapEL2, TrapEL3))))))
+    else if (((pat0 = EL1))) then
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__11 :: bool) .  return ((\<not> w__11)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let TrapEL2 = w__14 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__15 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__16 :: bool) . 
+      (let (TrapEL3 :: bool) = w__16 in
+      return (TrapEL2, TrapEL3)))))
+    else if (((pat0 = EL2))) then
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__17 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__18 :: bool) . 
+      (let (TrapEL3 :: bool) = w__18 in
+      return (TrapEL2, TrapEL3))))
+    else
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (TrapEL2, TrapEL3)))) \<bind> (\<lambda> varstup .  (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
    if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else
-     (ComputePAC X Y ((slice0 APGAKey_EL1 (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 APGAKey_EL1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     (ComputePAC X Y ((slice APGAKey_EL1 (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice APGAKey_EL1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        :: ( 64 Word.word) M) \<bind> (\<lambda> (w__21 ::  64 Word.word) . 
-     return ((concat_vec ((slice0 w__21 (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+     return ((concat_vec ((slice w__21 (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
                 ((Zeros__0 ((make_the_value (( 32 :: int)::ii)  ::  32 itself))  ::  32 Word.word))
-               ::  64 Word.word))))))))))))"
+               ::  64 Word.word))))))))))))))"
 
 
 (*val aarch64_integer_pac_pacga_dp_2src : ii -> ii -> ii -> bool -> M unit*)
@@ -16369,64 +16548,71 @@ definition AddPACDB  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(
    (read_reg APDBKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APDBKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APDBKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 13 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 13 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__285 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__285 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 13 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 13 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (AddPAC X Y APDBKey_EL1 True  :: ( 64 Word.word) M)))))))))))"
+   else (AddPAC X Y APDBKey_EL1 True  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_pacdb_dp_1src : ii -> ii -> bool -> M unit*)
@@ -16453,64 +16639,71 @@ definition AddPACDA  :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(
    (read_reg APDAKeyHi_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (read_reg APDAKeyLo_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (let (APDAKey_EL1 :: 128 bits) =
-     ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
-        ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+     ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+        ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
        ::  128 Word.word)) in
-   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) .  
-  (case (ProcState_EL   w__2) of
-        EL01 =>
-  or_boolM
-    (or_boolM (return ((\<not> ((HaveEL EL2)))))
-       ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-          (\<lambda> (w__3 :: 64 bits) . 
-           return
-             ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word)
-                  = (vec_of_bits [B0] :: 1 Word.word)))))))
-    ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-       (\<lambda> (w__5 :: 64 bits) . 
-        return
-          ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word)
-               = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-    (\<lambda> (IsEL1Regime :: bool) . 
-     (
-     if IsEL1Regime then
-       (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__6 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__6 (( 27 :: int):: ii)] :: 1 Word.word))
-     else
-       (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind>
-         (\<lambda> (w__7 :: 32 bits) . 
-          return
-            (vec_of_bits [access_vec_dec w__7 (( 27 :: int):: ii)] :: 1 Word.word)))
-       \<bind>
-       (\<lambda> (w__8 :: 1 Word.word) . 
-        (let Enable = w__8 in
-        and_boolM
-          (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
-             (IsSecure ()  \<bind>
-                (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
-          ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind>
-             (\<lambda> (w__11 :: 64 bits) . 
-              return
-                ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word)
-                     = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-          (\<lambda> (w__12 :: bool) . 
-           (let TrapEL2 = w__12 in
-           and_boolM (return ((HaveEL EL3)))
-             ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind>
-                (\<lambda> (w__13 :: 32 bits) . 
-                 return
-                   ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word)
-                        = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind>
-             (\<lambda> (w__14 :: bool) . 
-              (let (TrapEL3 :: bool) = w__14 in
-              return (Enable, TrapEL2, TrapEL3))))))))
-  ) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in
+   read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . 
+   (let p__284 = ((ProcState_EL   w__2)) in
+   (let pat0 = p__284 in
+   (if (((pat0 = EL0))) then
+      or_boolM
+        (or_boolM (return ((\<not> ((HaveEL EL2)))))
+           ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+            return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . 
+      (if IsEL1Regime then
+         (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)]  ::  1 Word.word))
+       else
+         (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . 
+         return (vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)]  ::  1 Word.word))) \<bind> (\<lambda> (w__8 ::  1 Word.word) . 
+      (let Enable = w__8 in
+      and_boolM
+        (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime))))
+           (IsSecure ()  \<bind> (\<lambda> (w__9 :: bool) .  return ((\<not> w__9)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . 
+      (let TrapEL2 = w__12 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . 
+      (let (TrapEL3 :: bool) = w__14 in
+      return (Enable, TrapEL2, TrapEL3))))))))
+    else if (((pat0 = EL1))) then
+      (read_reg SCTLR_EL1_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 :: int)::ii)]  ::  1 Word.word)) in
+      and_boolM
+        (and_boolM (return ((HaveEL EL2)))
+           (IsSecure ()  \<bind> (\<lambda> (w__16 :: bool) .  return ((\<not> w__16)))))
+        ((read_reg HCR_EL2_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . 
+      (let TrapEL2 = w__19 in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . 
+      (let (TrapEL3 :: bool) = w__21 in
+      return (Enable, TrapEL2, TrapEL3)))))))
+    else if (((pat0 = EL2))) then
+      (read_reg SCTLR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . 
+      (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 :: int)::ii)]  ::  1 Word.word)) in
+      (let TrapEL2 = False in
+      and_boolM (return ((HaveEL EL3)))
+        ((read_reg SCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . 
+         return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B0]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . 
+      (let (TrapEL3 :: bool) = w__24 in
+      return (Enable, TrapEL2, TrapEL3))))))
+    else
+      (read_reg SCTLR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . 
+      (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 :: int)::ii)]  ::  1 Word.word)) in
+      (let (TrapEL2 :: bool) = False in
+      (let (TrapEL3 :: bool) = False in
+      return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup .  (let ((Enable :: 1 bits), (TrapEL2 ::
+     bool), (TrapEL3 :: bool)) = varstup in
    if (((Enable = (vec_of_bits [B0]  ::  1 Word.word)))) then return X
    else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
    else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii)  :: ( 64 Word.word) M)
-   else (AddPAC X Y APDAKey_EL1 True  :: ( 64 Word.word) M)))))))))))"
+   else (AddPAC X Y APDAKey_EL1 True  :: ( 64 Word.word) M)))))))))))))"
 
 
 (*val aarch64_integer_pac_pacda_dp_1src : ii -> ii -> bool -> M unit*)
@@ -16568,11 +16761,11 @@ definition AArch64_WFxTrap  :: "(2)Word.word \<Rightarrow> bool \<Rightarrow>((r
    ExceptionSyndrome Exception_WFxTrap \<bind> (\<lambda> (exception :: ExceptionRecord) . 
    (let (tmp_2720 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
    (ConditionSyndrome ()   :: ( 5 Word.word) M) \<bind> (\<lambda> (w__1 ::  5 Word.word) . 
-   (let tmp_2720 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2720 (( 20 :: int)::ii) w__1  ::  25 Word.word)) in
+   (let tmp_2720 = ((set_slice (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2720 (( 20 :: int)::ii) w__1  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2720 |))) in
    (let (tmp_2730 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
    (let tmp_2730 =
-     ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2730 (( 0 :: int)::ii)
+     ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2730 (( 0 :: int)::ii)
         (if is_wfe then (vec_of_bits [B1]  ::  1 Word.word)
          else (vec_of_bits [B0]  ::  1 Word.word))
        ::  25 Word.word)) in
@@ -16785,25 +16978,25 @@ definition AArch64_SystemRegisterTrap  :: "(2)Word.word \<Rightarrow>(2)Word.wor
    (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in
    ExceptionSyndrome Exception_SystemRegisterTrap \<bind> (\<lambda> (exception :: ExceptionRecord) . 
    (let (tmp_2800 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2800 = ((set_slice0 (( 25 :: int)::ii) (( 2 :: int)::ii) tmp_2800 (( 20 :: int)::ii) op0  ::  25 Word.word)) in
+   (let tmp_2800 = ((set_slice (( 25 :: int)::ii) (( 2 :: int)::ii) tmp_2800 (( 20 :: int)::ii) op0  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2800 |))) in
    (let (tmp_2810 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2810 = ((set_slice0 (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2810 (( 17 :: int)::ii) op2  ::  25 Word.word)) in
+   (let tmp_2810 = ((set_slice (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2810 (( 17 :: int)::ii) op2  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2810 |))) in
    (let (tmp_2820 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2820 = ((set_slice0 (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2820 (( 14 :: int)::ii) op1  ::  25 Word.word)) in
+   (let tmp_2820 = ((set_slice (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2820 (( 14 :: int)::ii) op1  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2820 |))) in
    (let (tmp_2830 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2830 = ((set_slice0 (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2830 (( 10 :: int)::ii) crn  ::  25 Word.word)) in
+   (let tmp_2830 = ((set_slice (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2830 (( 10 :: int)::ii) crn  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2830 |))) in
    (let (tmp_2840 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2840 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2840 (( 5 :: int)::ii) rt  ::  25 Word.word)) in
+   (let tmp_2840 = ((set_slice (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2840 (( 5 :: int)::ii) rt  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2840 |))) in
    (let (tmp_2850 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2850 = ((set_slice0 (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2850 (( 1 :: int)::ii) crm  ::  25 Word.word)) in
+   (let tmp_2850 = ((set_slice (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2850 (( 1 :: int)::ii) crm  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2850 |))) in
    (let (tmp_2860 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2860 = ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2860 (( 0 :: int)::ii) dir  ::  25 Word.word)) in
+   (let tmp_2860 = ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2860 (( 0 :: int)::ii) dir  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2860 |))) in
    and_boolM
      (and_boolM (return ((((((target_el = EL1))) \<and> ((HaveEL EL2))))))
@@ -16836,7 +17029,7 @@ definition AArch64_SoftwareBreakpoint  :: "(16)Word.word \<Rightarrow>((register
    (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in
    ExceptionSyndrome Exception_SoftwareBreakpoint \<bind> (\<lambda> (exception :: ExceptionRecord) . 
    (let (tmp_2710 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2710 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2710 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
+   (let tmp_2710 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2710 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2710 |))) in
    read_reg PSTATE_ref \<bind> (\<lambda> (w__9 :: ProcState) . 
    if ((((Word.uint(ProcState_EL   w__9))) > ((Word.uint EL1)))) then
@@ -17010,33 +17203,33 @@ definition AArch64_CheckForERetTrap  :: " bool \<Rightarrow> bool \<Rightarrow>(
      (let (tmp_2550 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
      (ZeroExtend__0 (vec_of_bits [B0]  ::  1 Word.word) ((make_the_value (( 23 :: int)::ii)  ::  23 itself))
        :: ( 23 Word.word) M) \<bind> (\<lambda> (w__6 ::  23 Word.word) . 
-     (let tmp_2550 = ((set_slice0 (( 25 :: int)::ii) (( 23 :: int)::ii) tmp_2550 (( 2 :: int)::ii) w__6  ::  25 Word.word)) in
+     (let tmp_2550 = ((set_slice (( 25 :: int)::ii) (( 23 :: int)::ii) tmp_2550 (( 2 :: int)::ii) w__6  ::  25 Word.word)) in
      (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2550 |))) in
      (let (exception :: ExceptionRecord) =
        (if ((\<not> eret_with_pac)) then
          (let (tmp_2560 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
          (let (tmp_2560 :: 25 bits) =
-           ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2560 (( 1 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  25 Word.word)) in
+           ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2560 (( 1 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  25 Word.word)) in
          (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_syndrome := tmp_2560 |))) in
          (let (tmp_2570 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
          (let (tmp_2570 :: 25 bits) =
-           ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2570 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  25 Word.word)) in
+           ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2570 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  25 Word.word)) in
          (exception (| ExceptionRecord_syndrome := tmp_2570 |)))))))
        else
          (let (tmp_2580 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
          (let (tmp_2580 :: 25 bits) =
-           ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2580 (( 1 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  25 Word.word)) in
+           ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2580 (( 1 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  25 Word.word)) in
          (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_syndrome := tmp_2580 |))) in
          if pac_uses_key_a then
            (let (tmp_2590 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
            (let (tmp_2590 :: 25 bits) =
-             ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2590 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)
+             ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2590 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)
                ::  25 Word.word)) in
            (exception (| ExceptionRecord_syndrome := tmp_2590 |))))
          else
            (let (tmp_2600 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
            (let (tmp_2600 :: 25 bits) =
-             ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2600 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
+             ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2600 (( 0 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)
                ::  25 Word.word)) in
            (exception (| ExceptionRecord_syndrome := tmp_2600 |)))))))) in
      AArch64_TakeException EL2 exception preferred_exception_return vect_offset))))))))))
@@ -17062,7 +17255,7 @@ definition AArch64_CallSupervisor  :: "(16)Word.word \<Rightarrow>((register_val
    (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in
    ExceptionSyndrome Exception_SupervisorCall \<bind> (\<lambda> (exception :: ExceptionRecord) . 
    (let (tmp_2770 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2770 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2770 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
+   (let tmp_2770 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2770 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2770 |))) in
    read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . 
    if ((((Word.uint(ProcState_EL   w__6))) > ((Word.uint EL1)))) then
@@ -17103,7 +17296,7 @@ definition AArch64_CallSecureMonitor  :: "(16)Word.word \<Rightarrow>((register_
    (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in
    ExceptionSyndrome Exception_MonitorCall \<bind> (\<lambda> (exception :: ExceptionRecord) . 
    (let (tmp_2930 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2930 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2930 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
+   (let tmp_2930 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2930 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2930 |))) in
    AArch64_TakeException EL3 exception preferred_exception_return vect_offset)))))))))"
 
@@ -17121,7 +17314,7 @@ definition AArch64_CallHypervisor  :: "(16)Word.word \<Rightarrow>((register_val
    (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in
    ExceptionSyndrome Exception_HypervisorCall \<bind> (\<lambda> (exception :: ExceptionRecord) . 
    (let (tmp_2890 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-   (let tmp_2890 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2890 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
+   (let tmp_2890 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2890 (( 0 :: int)::ii) immediate  ::  25 Word.word)) in
    (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2890 |))) in
    read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . 
    if ((((ProcState_EL   w__1) = EL3))) then
@@ -17214,7 +17407,7 @@ definition AArch32_EnterMode  :: "(5)Word.word \<Rightarrow>(32)Word.word \<Righ
       (read_reg SCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 ::  32 Word.word) . 
       write_reg
         SCR_ref
-        ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__4 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)))
+        ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__4 (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)))
     else return () ) \<then>
    AArch32_WriteMode target_mode) \<then>
    aset_SPSR spsr) \<then>
@@ -17270,7 +17463,7 @@ definition AArch32_EnterMode  :: "(5)Word.word \<Rightarrow>(32)Word.word \<Righ
     else return () ) \<then>
    (ExcVectorBase ()   :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__21 ::  32 Word.word) . 
    BranchTo
-     ((concat_vec ((slice0 w__21 (( 5 :: int)::ii) (( 27 :: int)::ii)  ::  27 Word.word))
+     ((concat_vec ((slice w__21 (( 5 :: int)::ii) (( 27 :: int)::ii)  ::  27 Word.word))
          ((GetSlice_int ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) vect_offset (( 0 :: int)::ii)  ::  5 Word.word))
         ::  32 Word.word)) BranchType_UNKNOWN \<then>
    EndOfInstruction () ))))))))))))))"
@@ -17297,7 +17490,7 @@ definition AArch64_AdvSIMDFPAccessTrap  :: "(2)Word.word \<Rightarrow>((register
      (let exception = w__4 in
      (let (tmp_2610 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
      (ConditionSyndrome ()   :: ( 5 Word.word) M) \<bind> (\<lambda> (w__5 ::  5 Word.word) . 
-     (let tmp_2610 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2610 (( 20 :: int)::ii) w__5  ::  25 Word.word)) in
+     (let tmp_2610 = ((set_slice (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2610 (( 20 :: int)::ii) w__5  ::  25 Word.word)) in
      (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2610 |))) in
      AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))))))"
 
@@ -17315,8 +17508,8 @@ definition AArch64_CheckFPAdvSIMDTrap  :: " unit \<Rightarrow>((register_value),
          return ((((vec_of_bits [access_vec_dec w__2 (( 34 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))))) \<bind> (\<lambda> (w__3 :: bool) . 
       if w__3 then
         (read_reg CPTR_EL2_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . 
-        (let p__607 = ((slice0 w__4 (( 20 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
-        (let v__94 = p__607 in
+        (let p__283 = ((slice w__4 (( 20 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+        (let v__94 = p__283 in
         (if (((((subrange_vec_dec v__94 (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word)) = (vec_of_bits [B0]  ::  1 Word.word)))) then
            and_boolM
              (read_reg PSTATE_ref \<bind> (\<lambda> (w__5 :: ProcState) . 
@@ -17359,8 +17552,8 @@ definition AArch64_CheckFPAdvSIMDEnabled  :: " unit \<Rightarrow>((register_valu
      bool) . 
    (if w__2 then
       (aget_CPACR ()   :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
-      (let p__606 = ((slice0 w__3 (( 20 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
-      (let v__96 = p__606 in
+      (let p__282 = ((slice w__3 (( 20 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+      (let v__96 = p__282 in
       (if (((((subrange_vec_dec v__96 (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word)) = (vec_of_bits [B0]  ::  1 Word.word)))) then
          return True
        else if (((v__96 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then
@@ -17480,7 +17673,7 @@ definition aarch64_float_convert_int  :: " int \<Rightarrow>('fltsize::len)itsel
    | FPConvOp_MOV_ItoF =>
       (aget_X intsize n  :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: 'intsize bits) . 
       (let intval = w__8 in
-      (let fltval = ((slice0 intval (( 0 :: int)::ii) fltsize  :: ( 'fltsize::len)Word.word)) in
+      (let fltval = ((slice intval (( 0 :: int)::ii) fltsize  :: ( 'fltsize::len)Word.word)) in
       aset_Vpart d part fltval)))
    | FPConvOp_CVT_FtoI_JS =>
       (aget_V fltsize n  :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: 'fltsize bits) . 
@@ -17488,7 +17681,7 @@ definition aarch64_float_convert_int  :: " int \<Rightarrow>('fltsize::len)itsel
       (read_reg FPCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 ::  32 Word.word) . 
       (FPToFixedJS intsize fltval w__10 True  :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__11 :: 'intsize bits) . 
       (let intval = w__11 in
-      (ZeroExtend__0 ((slice0 intval (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+      (ZeroExtend__0 ((slice intval (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
          ((make_the_value (( 64 :: int)::ii)  ::  64 itself))
         :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 ::  64 Word.word) . 
       aset_X d w__12))))))
@@ -18441,7 +18634,7 @@ definition AArch64_CheckWatchpoint  :: "(64)Word.word \<Rightarrow> AccType \<Ri
    ((let (val_match :: bool) = False in
    AArch64_AccessIsPrivileged acctype \<bind> (\<lambda> (ispriv :: bool) . 
    (read_reg ID_AA64DFR0_EL1_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
-   (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice0 w__2 (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))) (( 1 :: int)::ii)) val_match
+   (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice w__2 (( 20 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)))) (( 1 :: int)::ii)) val_match
      (\<lambda> i val_match . 
        or_boolM (return val_match) ((AArch64_WatchpointMatch i vaddress size1 ispriv iswrite)))) \<bind> (\<lambda> (val_match ::
      bool) . 
@@ -18509,7 +18702,7 @@ definition AArch64_CheckPermission  :: " Permissions \<Rightarrow>(64)Word.word
       (let user_r =
         ((vec_of_bits [access_vec_dec(Permissions_ap   perms) (( 1 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)) in
       (let user_w =
-        (((slice0(Permissions_ap   perms) (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
+        (((slice(Permissions_ap   perms) (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)) in
       AArch64_AccessIsPrivileged acctype \<bind> (\<lambda> (w__8 :: bool) . 
       (let ispriv = w__8 in
       (if ((HavePANExt () )) then
@@ -18774,7 +18967,7 @@ definition aset_Mem  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \
    if ((\<not> atomic)) then
      ((assert_exp ((size1 > (( 1 :: int)::ii))) (''(size > 1)'') \<then>
      AArch64_aset_MemSingle address (( 1 :: int)::ii) acctype aligned
-       ((slice0 value_name (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))) \<then>
+       ((slice value_name (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))) \<then>
      (if ((\<not> aligned)) then
         (let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in
         assert_exp ((((((c = Constraint_FAULT))) \<or> (((c = Constraint_NONE)))))) (''((c == Constraint_FAULT) || (c == Constraint_NONE))'') \<then>
@@ -18784,12 +18977,12 @@ definition aset_Mem  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \
      (foreachM (index_list (( 1 :: int)::ii) ((size1 - (( 1 :: int)::ii))) (( 1 :: int)::ii)) () 
        (\<lambda> i unit_var . 
          AArch64_aset_MemSingle ((add_vec_int address i  ::  64 Word.word)) (( 1 :: int)::ii) acctype aligned
-           ((slice0 value_name (((( 8 :: int)::ii) * i)) (( 8 :: int)::ii)  ::  8 Word.word)))))
+           ((slice value_name (((( 8 :: int)::ii) * i)) (( 8 :: int)::ii)  ::  8 Word.word)))))
    else if ((((((size1 = (( 16 :: int)::ii)))) \<and> ((((((acctype = AccType_VEC))) \<or> (((acctype = AccType_VECSTREAM))))))))) then
      AArch64_aset_MemSingle address (( 8 :: int)::ii) acctype aligned
-       ((slice0 value_name (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word)) \<then>
+       ((slice value_name (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word)) \<then>
      AArch64_aset_MemSingle ((add_vec_int address (( 8 :: int)::ii)  ::  64 Word.word)) (( 8 :: int)::ii) acctype aligned
-       ((slice0 value_name (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+       ((slice value_name (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
    else AArch64_aset_MemSingle address size1 acctype aligned value_name))))))))))"
 
 
@@ -18831,7 +19024,7 @@ definition aget_Mem  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \
       (AArch64_aget_MemSingle address (( 1 :: int)::ii) acctype aligned  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__0 ::
          8 Word.word) . 
       (let value_name =
-        ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (( 0 :: int)::ii) w__0
+        ((set_slice (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (( 0 :: int)::ii) w__0
           :: ( 'p8_times_size_::len)Word.word)) in
       (if ((\<not> aligned)) then
          (let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in
@@ -18844,19 +19037,19 @@ definition aget_Mem  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \
           (AArch64_aget_MemSingle ((add_vec_int address i  ::  64 Word.word)) (( 1 :: int)::ii) acctype aligned
             :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 ::  8 Word.word) . 
           (let value_name =
-            ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (((( 8 :: int)::ii) * i)) w__1
+            ((set_slice (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (((( 8 :: int)::ii) * i)) w__1
               :: ( 'p8_times_size_::len)Word.word)) in
           return value_name)))))))
     else if ((((((size1 = (( 16 :: int)::ii)))) \<and> ((((((acctype = AccType_VEC))) \<or> (((acctype = AccType_VECSTREAM))))))))) then
       (AArch64_aget_MemSingle address (( 8 :: int)::ii) acctype aligned  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::
          64 Word.word) . 
       (let value_name =
-        ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 64 :: int)::ii) value_name (( 0 :: int)::ii) w__2
+        ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) value_name (( 0 :: int)::ii) w__2
           :: ( 'p8_times_size_::len)Word.word)) in
       (AArch64_aget_MemSingle ((add_vec_int address (( 8 :: int)::ii)  ::  64 Word.word)) (( 8 :: int)::ii) acctype aligned
         :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 ::  64 Word.word) . 
       (let value_name =
-        ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 64 :: int)::ii) value_name (( 64 :: int)::ii) w__3
+        ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) value_name (( 64 :: int)::ii) w__3
           :: ( 'p8_times_size_::len)Word.word)) in
       return value_name))))
     else (AArch64_aget_MemSingle address size1 acctype aligned  :: (( 'p8_times_size_::len)Word.word) M)) \<bind> (\<lambda> value_name . 
@@ -18885,8 +19078,8 @@ definition aarch64_memory_vector_single_nowb  :: "('datasize::len)itself \<Right
     else (aget_X (( 64 :: int)::ii) n  :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . 
    (let offs = ((Zeros__1 (( 64 :: int)::ii) ()   ::  64 Word.word)) in
    (if replicate1 then
-      (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs
-        (\<lambda> s offs . 
+      (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (element, offs, t)
+        (\<lambda> s varstup .  (let (element, offs, t) = varstup in
           (aget_Mem ((add_vec address offs  ::  64 Word.word)) ebytes AccType_VEC  :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'esize
             bits) . 
           (let element = w__2 in
@@ -18895,10 +19088,12 @@ definition aarch64_memory_vector_single_nowb  :: "('datasize::len)itself \<Right
           aset_V t ((replicate_bits element v  :: ( 'datasize::len)Word.word))) \<then>
           ((let (offs :: 64 bits) = ((add_vec_int offs ebytes  ::  64 Word.word)) in
           (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in
-          return offs))))))))
+          return (element, offs, t)))))))))) \<bind> (\<lambda> varstup .  (let ((element :: 'esize bits), (offs :: 64
+        bits), (t :: ii)) = varstup in
+      return offs))
     else
-      (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs
-        (\<lambda> s offs . 
+      (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, t)
+        (\<lambda> s varstup .  (let (offs, rval, t) = varstup in
           (aget_V (( 128 :: int)::ii) t  :: ( 128 Word.word) M) \<bind> (\<lambda> (w__3 :: 128 bits) . 
           (let rval = w__3 in
           (if (((memop = MemOp_LOAD))) then
@@ -18907,13 +19102,16 @@ definition aarch64_memory_vector_single_nowb  :: "('datasize::len)itself \<Right
              (aset_Elem__0 rval index1 ((make_the_value esize  :: ( 'esize::len)itself)) w__4
                :: ( 128 Word.word) M) \<bind> (\<lambda> (w__5 :: 128 bits) . 
              (let rval = w__5 in
-             aset_V t rval)))
+             aset_V t rval \<then> return rval)))
            else
              (aget_Elem__0 rval index1 ((make_the_value esize  :: ( 'esize::len)itself))  :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> w__6 . 
-             aset_Mem ((add_vec address offs  ::  64 Word.word)) ebytes AccType_VEC w__6)) \<then>
-          ((let (offs :: 64 bits) = ((add_vec_int offs ebytes  ::  64 Word.word)) in
+             aset_Mem ((add_vec address offs  ::  64 Word.word)) ebytes AccType_VEC w__6 \<then> return rval)) \<bind> (\<lambda> (rval :: 128
+            bits) . 
+          (let (offs :: 64 bits) = ((add_vec_int offs ebytes  ::  64 Word.word)) in
           (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in
-          return offs)))))))) \<bind> (\<lambda> (offs :: 64 bits) . 
+          return (offs, rval, t))))))))) \<bind> (\<lambda> varstup .  (let ((offs :: 64 bits), (rval :: 128 bits), (t ::
+        ii)) = varstup in
+      return offs))) \<bind> (\<lambda> (offs :: 64 bits) . 
    if wback then
      (if (((m \<noteq> (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m  :: ( 64 Word.word) M)
       else return offs) \<bind> (\<lambda> (offs :: 64 bits) . 
@@ -18942,13 +19140,13 @@ definition aarch64_memory_vector_multiple_nowb  :: "('datasize::len)itself \<Rig
    (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment ()  \<then> (aget_SP (( 64 :: int)::ii) ()   :: ( 64 Word.word) M)
     else (aget_X (( 64 :: int)::ii) n  :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . 
    (let offs = ((Zeros__1 (( 64 :: int)::ii) ()   ::  64 Word.word)) in
-   (foreachM (index_list (( 0 :: int)::ii) ((rpt - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs
-     (\<lambda> r offs . 
-       (foreachM (index_list (( 0 :: int)::ii) ((elements - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs
-         (\<lambda> e offs . 
+   (foreachM (index_list (( 0 :: int)::ii) ((rpt - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt)
+     (\<lambda> r varstup .  (let (offs, rval, tt) = varstup in
+       (foreachM (index_list (( 0 :: int)::ii) ((elements - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt)
+         (\<lambda> e varstup .  (let (offs, rval, tt) = varstup in
            (let tt = (((t + r)) mod (( 32 :: int)::ii)) in
-           (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs
-             (\<lambda> s offs . 
+           (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt)
+             (\<lambda> s varstup .  (let (offs, rval, tt) = varstup in
                (aget_V datasize tt  :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . 
                (let rval = w__2 in
                (if (((memop = MemOp_LOAD))) then
@@ -18957,19 +19155,21 @@ definition aarch64_memory_vector_multiple_nowb  :: "('datasize::len)itself \<Rig
                   (aset_Elem__0 rval e ((make_the_value esize  :: ( 'esize::len)itself)) w__3
                     :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: 'datasize bits) . 
                   (let rval = w__4 in
-                  aset_V tt rval)))
+                  aset_V tt rval \<then> return rval)))
                 else
                   (aget_Elem__0 rval e ((make_the_value esize  :: ( 'esize::len)itself))  :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> w__5 . 
-                  aset_Mem ((add_vec address offs  ::  64 Word.word)) ebytes AccType_VEC w__5)) \<then>
-               ((let (offs :: 64 bits) = ((add_vec_int offs ebytes  ::  64 Word.word)) in
+                  aset_Mem ((add_vec address offs  ::  64 Word.word)) ebytes AccType_VEC w__5 \<then>
+                  return rval)) \<bind> (\<lambda> (rval :: 'datasize bits) . 
+               (let (offs :: 64 bits) = ((add_vec_int offs ebytes  ::  64 Word.word)) in
                (let (tt :: ii) = (((((ex_int tt)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in
-               return offs)))))))))))) \<bind> (\<lambda> (offs :: 64 bits) . 
+               return (offs, rval, tt)))))))))))))))) \<bind> (\<lambda> varstup .  (let ((offs :: 64 bits), (rval :: 'datasize
+     bits), (tt :: ii)) = varstup in
    if wback then
      (if (((m \<noteq> (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m  :: ( 64 Word.word) M)
       else return offs) \<bind> (\<lambda> (offs :: 64 bits) . 
      if (((n = (( 31 :: int)::ii)))) then aset_SP ((add_vec address offs  ::  64 Word.word))
      else aset_X n ((add_vec address offs  ::  64 Word.word)))
-   else return () ))))))))))))))"
+   else return () )))))))))))))))"
 
 
 (*val aarch64_memory_single_simdfp_register : AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> ii -> ii -> bool -> M unit*)
@@ -20339,20 +20539,20 @@ definition aarch64_memory_atomicops_cas_pair  :: " int \<Rightarrow> AccType \<R
       else return () ) \<then>
      BigEndian () ) \<bind> (\<lambda> (w__5 :: bool) . 
      if w__5 then
-       (ZeroExtend__0 ((slice0 data (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
+       (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__6 \<then>
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__7 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__7))
      else
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__8 \<then>
-       (ZeroExtend__0 ((slice0 data (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
+       (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__9)))))))))))))))))))))
@@ -20388,20 +20588,20 @@ definition aarch64_memory_atomicops_cas_pair  :: " int \<Rightarrow> AccType \<R
       else return () ) \<then>
      BigEndian () ) \<bind> (\<lambda> (w__15 :: bool) . 
      if w__15 then
-       (ZeroExtend__0 ((slice0 data (( 16 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
+       (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__16 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__16 \<then>
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__17 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__17))
      else
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__18 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__18 \<then>
-       (ZeroExtend__0 ((slice0 data (( 16 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
+       (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__19)))))))))))))))))))))
@@ -20437,20 +20637,20 @@ definition aarch64_memory_atomicops_cas_pair  :: " int \<Rightarrow> AccType \<R
       else return () ) \<then>
      BigEndian () ) \<bind> (\<lambda> (w__25 :: bool) . 
      if w__25 then
-       (ZeroExtend__0 ((slice0 data (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+       (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__26 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__26 \<then>
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__27 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__27))
      else
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__28 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__28 \<then>
-       (ZeroExtend__0 ((slice0 data (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+       (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__29)))))))))))))))))))))
@@ -20486,20 +20686,20 @@ definition aarch64_memory_atomicops_cas_pair  :: " int \<Rightarrow> AccType \<R
       else return () ) \<then>
      BigEndian () ) \<bind> (\<lambda> (w__35 :: bool) . 
      if w__35 then
-       (ZeroExtend__0 ((slice0 data (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+       (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__36 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__36 \<then>
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__37))
      else
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__38 \<then>
-       (ZeroExtend__0 ((slice0 data (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
+       (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__39 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__39)))))))))))))))))))))
@@ -20535,20 +20735,20 @@ definition aarch64_memory_atomicops_cas_pair  :: " int \<Rightarrow> AccType \<R
       else return () ) \<then>
      BigEndian () ) \<bind> (\<lambda> (w__45 :: bool) . 
      if w__45 then
-       (ZeroExtend__0 ((slice0 data (( 128 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
+       (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__46 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__46 \<then>
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__47 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__47))
      else
-       (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
+       (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__48 :: ( 'regsize::len)Word.word) . 
        (aset_X s w__48 \<then>
-       (ZeroExtend__0 ((slice0 data (( 128 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
+       (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii)  ::  128 Word.word))
           ((make_the_value regsize  :: ( 'regsize::len)itself))
          :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__49 :: ( 'regsize::len)Word.word) . 
        aset_X ((s + (( 1 :: int)::ii))) w__49)))))))))))))))))))))
@@ -20645,10 +20845,10 @@ definition AArch32_GenerateDebugExceptionsFrom  :: "(2)Word.word \<Rightarrow> b
          ELUsingAArch32 EL3 \<bind> (\<lambda> (w__9 :: bool) . 
          (if w__9 then
             (read_reg SDCR_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . 
-            return ((slice0 w__10 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)))
+            return ((slice w__10 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)))
           else
             (read_reg MDCR_EL3_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 bits) . 
-            return ((slice0 w__11 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)))) \<bind> (\<lambda> (w__12 ::  2 Word.word) . 
+            return ((slice w__11 (( 14 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)))) \<bind> (\<lambda> (w__12 ::  2 Word.word) . 
          (let spd = w__12 in
          (if ((((vec_of_bits [access_vec_dec spd (( 1 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
             (let (enabled :: bool) =
@@ -20744,12 +20944,12 @@ definition SetPSTATEFromPSR  :: "(32)Word.word \<Rightarrow>((register_value),(u
         PSTATE_ref
         (w__4 (| ProcState_IL := ((vec_of_bits [access_vec_dec spsr (( 20 :: int)::ii)]  ::  1 Word.word))|)) \<then>
       (if ((((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
-        AArch32_WriteMode ((slice0 spsr (( 0 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word))
+        AArch32_WriteMode ((slice spsr (( 0 :: int)::ii) (( 5 :: int)::ii)  ::  5 Word.word))
       else
         read_reg PSTATE_ref \<bind> (\<lambda> (w__5 :: ProcState) . 
         (write_reg PSTATE_ref (w__5 (| ProcState_nRW := ((vec_of_bits [B0]  ::  1 Word.word))|)) \<then>
         read_reg PSTATE_ref) \<bind> (\<lambda> (w__6 :: ProcState) . 
-        (write_reg PSTATE_ref (w__6 (| ProcState_EL := ((slice0 spsr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|)) \<then>
+        (write_reg PSTATE_ref (w__6 (| ProcState_EL := ((slice spsr (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))|)) \<then>
         read_reg PSTATE_ref) \<bind> (\<lambda> (w__7 :: ProcState) . 
         write_reg
           PSTATE_ref
@@ -20763,11 +20963,11 @@ definition SetPSTATEFromPSR  :: "(32)Word.word \<Rightarrow>((register_value),(u
       ConstrainUnpredictableBool Unpredictable_ILZEROT \<bind> (\<lambda> (w__11 :: bool) . 
       (let (spsr ::  32 Word.word) =
         (if w__11 then
-          (set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) spsr (( 5 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)
+          (set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) spsr (( 5 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)
         else spsr) in
       return spsr))
     else return spsr) \<bind> (\<lambda> (spsr ::  32 Word.word) . 
-   (let split_vec = ((slice0 spsr (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+   (let split_vec = ((slice spsr (( 28 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
    (let (tup__0, tup__1, tup__2, tup__3) =
      ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word),
       (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word),
@@ -20791,12 +20991,12 @@ definition SetPSTATEFromPSR  :: "(32)Word.word \<Rightarrow>((register_value),(u
       (RestoredITBits spsr  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__19 :: 8 bits) . 
       (write_reg PSTATE_ref (w__18 (| ProcState_IT := w__19 |)) \<then>
       read_reg PSTATE_ref) \<bind> (\<lambda> (w__20 :: ProcState) . 
-      (write_reg PSTATE_ref (w__20 (| ProcState_GE := ((slice0 spsr (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))|)) \<then>
+      (write_reg PSTATE_ref (w__20 (| ProcState_GE := ((slice spsr (( 16 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word))|)) \<then>
       read_reg PSTATE_ref) \<bind> (\<lambda> (w__21 :: ProcState) . 
       write_reg
         PSTATE_ref
         (w__21 (| ProcState_E := ((vec_of_bits [access_vec_dec spsr (( 9 :: int)::ii)]  ::  1 Word.word))|)) \<then>
-      ((let split_vec = ((slice0 spsr (( 6 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+      ((let split_vec = ((slice spsr (( 6 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
       (let (tup__0, tup__1, tup__2) =
         ((subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word),
          (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word),
@@ -20812,7 +21012,7 @@ definition SetPSTATEFromPSR  :: "(32)Word.word \<Rightarrow>((register_value),(u
         PSTATE_ref
         (w__25 (| ProcState_T := ((vec_of_bits [access_vec_dec spsr (( 5 :: int)::ii)]  ::  1 Word.word))|))))))))))))))
     else
-      (let split_vec = ((slice0 spsr (( 6 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
+      (let split_vec = ((slice spsr (( 6 :: int)::ii) (( 4 :: int)::ii)  ::  4 Word.word)) in
       (let (tup__0, tup__1, tup__2, tup__3) =
         ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word),
          (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word),
@@ -20965,9 +21165,9 @@ definition AArch64_ExceptionReturn  :: "(64)Word.word \<Rightarrow>(32)Word.word
    read_reg PSTATE_ref) \<bind> (\<lambda> (w__2 :: ProcState) . 
    (if ((((ProcState_IL   w__2) = (vec_of_bits [B1]  ::  1 Word.word)))) then
       (undefined_bitvector (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
-      (let new_pc = ((set_slice0 (( 64 :: int)::ii) (( 32 :: int)::ii) new_pc (( 32 :: int)::ii) w__3  ::  64 Word.word)) in
+      (let new_pc = ((set_slice (( 64 :: int)::ii) (( 32 :: int)::ii) new_pc (( 32 :: int)::ii) w__3  ::  64 Word.word)) in
       (undefined_bitvector (( 2 :: int)::ii)  :: ( 2 Word.word) M) \<bind> (\<lambda> (w__4 ::  2 Word.word) . 
-      (let (new_pc ::  64 Word.word) = ((set_slice0 (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) w__4  ::  64 Word.word)) in
+      (let (new_pc ::  64 Word.word) = ((set_slice (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) w__4  ::  64 Word.word)) in
       return new_pc))))
     else
       UsingAArch32 ()  \<bind> (\<lambda> (w__5 :: bool) . 
@@ -20975,13 +21175,13 @@ definition AArch64_ExceptionReturn  :: "(64)Word.word \<Rightarrow>(32)Word.word
         read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . 
         (let (new_pc ::  64 Word.word) =
           (if ((((ProcState_T   w__6) = (vec_of_bits [B0]  ::  1 Word.word)))) then
-            (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)
+            (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)
           else
-            (set_slice0 (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  64 Word.word)) in
+            (set_slice (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  64 Word.word)) in
         return new_pc))
       else (AArch64_BranchAddr new_pc  :: ( 64 Word.word) M))) \<bind> (\<lambda> (new_pc ::  64 Word.word) . 
    UsingAArch32 ()  \<bind> (\<lambda> (w__8 :: bool) . 
-   if w__8 then BranchTo ((slice0 new_pc (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) BranchType_UNKNOWN
+   if w__8 then BranchTo ((slice new_pc (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) BranchType_UNKNOWN
    else BranchToAddr new_pc BranchType_ERET))))))))"
 
 
@@ -21079,7 +21279,7 @@ definition AArch32_EnterHypMode  :: " ExceptionRecord \<Rightarrow>(32)Word.word
      (w__19 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word))|)) \<then>
    (read_reg HVBAR_ref  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__20 :: 32 bits) . 
    BranchTo
-     ((concat_vec ((slice0 w__20 (( 5 :: int)::ii) (( 27 :: int)::ii)  ::  27 Word.word))
+     ((concat_vec ((slice w__20 (( 5 :: int)::ii) (( 27 :: int)::ii)  ::  27 Word.word))
          ((GetSlice_int ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) vect_offset (( 0 :: int)::ii)  ::  5 Word.word))
         ::  32 Word.word)) BranchType_UNKNOWN \<then>
    EndOfInstruction () )))))))))))))))"
@@ -21124,7 +21324,7 @@ definition UnallocatedEncoding  :: " unit \<Rightarrow>((register_value),(unit),
       (read_reg FPEXC_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
       write_reg
         FPEXC_ref
-        ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__3 (( 29 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)))
+        ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__3 (( 29 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word)))
     else return () ) \<then>
    and_boolM ((UsingAArch32 () ))
      (AArch32_GeneralExceptionsToAArch64 ()  \<bind> (\<lambda> (w__5 :: bool) .  return ((\<not> w__5))))) \<bind> (\<lambda> (w__6 ::
@@ -23405,12 +23605,12 @@ definition aarch64_memory_exclusive_single  :: " AccType \<Rightarrow>('datasize
             BigEndian ()  \<bind> (\<lambda> (w__56 :: bool) . 
             if w__56 then
               aset_X t
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)) \<then>
-              aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)) \<then>
+              aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
             else
-              aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
+              aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
               aset_X t2
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)))))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)))))
           else
             ((if (((address \<noteq> ((Align__1 address dbytes  ::  64 Word.word))))) then
                (let iswrite = False in
@@ -23500,12 +23700,12 @@ definition aarch64_memory_exclusive_single  :: " AccType \<Rightarrow>('datasize
             BigEndian ()  \<bind> (\<lambda> (w__73 :: bool) . 
             if w__73 then
               aset_X t
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)) \<then>
-              aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)) \<then>
+              aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
             else
-              aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
+              aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
               aset_X t2
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)))))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)))))
           else
             ((if (((address \<noteq> ((Align__1 address dbytes  ::  64 Word.word))))) then
                (let iswrite = False in
@@ -23934,12 +24134,12 @@ definition aarch64_memory_exclusive_pair  :: " AccType \<Rightarrow>('datasize::
             BigEndian ()  \<bind> (\<lambda> (w__56 :: bool) . 
             if w__56 then
               aset_X t
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)) \<then>
-              aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)) \<then>
+              aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
             else
-              aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
+              aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
               aset_X t2
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)))))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii)))  ::  32 Word.word)))))
           else
             ((if (((address \<noteq> ((Align__1 address dbytes  ::  64 Word.word))))) then
                (let iswrite = False in
@@ -24029,12 +24229,12 @@ definition aarch64_memory_exclusive_pair  :: " AccType \<Rightarrow>('datasize::
             BigEndian ()  \<bind> (\<lambda> (w__73 :: bool) . 
             if w__73 then
               aset_X t
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)) \<then>
-              aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)) \<then>
+              aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
             else
-              aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
+              aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word)) \<then>
               aset_X t2
-                ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)))))
+                ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii)))  ::  96 Word.word)))))
           else
             ((if (((address \<noteq> ((Align__1 address dbytes  ::  64 Word.word))))) then
                (let iswrite = False in
@@ -24227,13 +24427,13 @@ definition system_barriers_decode  :: "(1)Word.word \<Rightarrow>(2)Word.word \<
     else if (((b__0 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then return MemBarrierOp_DMB
     else if (((b__0 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then return MemBarrierOp_ISB
     else UnallocatedEncoding ()  \<then> return op1) \<bind> (\<lambda> (op1 :: MemBarrierOp) . 
-   (let b__3 = ((slice0 CRm (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+   (let b__3 = ((slice CRm (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
    (let (domain1 :: MBReqDomain) =
      (if (((b__3 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then MBReqDomain_OuterShareable
      else if (((b__3 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then MBReqDomain_Nonshareable
      else if (((b__3 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then MBReqDomain_InnerShareable
      else MBReqDomain_FullSystem) in
-   (let b__7 = ((slice0 CRm (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+   (let b__7 = ((slice CRm (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
    (let ((domain1 :: MBReqDomain), (types1 :: MBReqTypes)) =
      (if (((b__7 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then
        (let (types1 :: MBReqTypes) = MBReqTypes_Reads in
@@ -27093,7 +27293,7 @@ definition memory_single_simdfp_register_aarch64_memory_single_simdfp_register__
      (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
        MemOp_LOAD
      else MemOp_STORE) in
-   (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in
+   (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in
    aarch64_memory_single_simdfp_register acctype datasize extend_type m memop n postindex shift t
      wback))))))))))))))"
 
@@ -27119,7 +27319,7 @@ definition memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_
      (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
        MemOp_LOAD
      else MemOp_STORE) in
-   (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in
+   (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in
    aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t
      wback))))))))))))"
 
@@ -27144,7 +27344,7 @@ definition memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_si
      (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
        MemOp_LOAD
      else MemOp_STORE) in
-   (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in
+   (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in
    aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t
      wback)))))))))))"
 
@@ -27169,7 +27369,7 @@ definition memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_s
      (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
        MemOp_LOAD
      else MemOp_STORE) in
-   (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in
+   (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in
    aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t
      wback)))))))))))"
 
@@ -27194,7 +27394,7 @@ definition memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_si
      (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)]  ::  1 Word.word) = (vec_of_bits [B1]  ::  1 Word.word)))) then
        MemOp_LOAD
      else MemOp_STORE) in
-   (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in
+   (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in
    aarch64_memory_single_simdfp_immediate_signed_offset_normal acctype datasize memop n offset
      postindex t wback)))))))))))"
 
@@ -30464,7 +30664,7 @@ definition memory_atomicops_st_decode  :: "(2)Word.word \<Rightarrow>(1)Word.wor
     else return () )) \<then>
    ((let (n :: ii) = (Word.uint Rn) in
    (let (s :: ii) = (Word.uint Rs) in
-   (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) ((Word.uint size1))) in
+   (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) ((Word.uint size1))) in
    (let (regsize :: ii) = (if (((((ex_int datasize)) = (( 64 :: int)::ii)))) then (( 64 :: int)::ii) else (( 32 :: int)::ii)) in
    (let (ldacctype :: AccType) = AccType_ATOMICRW in
    (let (stacctype :: AccType) =
@@ -31134,13 +31334,13 @@ definition float_convert_int_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
    (if (((b__0 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then return (( 32 :: int)::ii)
     else if (((b__0 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then return (( 64 :: int)::ii)
     else if (((b__0 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then
-      (if (((((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B0,B1]  ::  4 Word.word)))) then
+      (if (((((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B0,B1]  ::  4 Word.word)))) then
          UnallocatedEncoding () 
        else return () ) \<then>
       return (( 128 :: int)::ii)
     else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii)
     else UnallocatedEncoding ()  \<then> return fltsize) \<bind> (\<lambda> (fltsize :: ii) . 
-   (let v__98 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+   (let v__98 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
    (if (((((subrange_vec_dec v__98 (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
       (let (rounding :: FPRounding) = (FPDecodeRounding rmode) in
       (let (unsigned :: bool) =
@@ -31403,7 +31603,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () ) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__2 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__2 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__2 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31436,7 +31636,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () ) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__6 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__6 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__6 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31469,7 +31669,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () )) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__10 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__10 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__10 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31502,7 +31702,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () ) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__14 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__14 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__14 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31535,7 +31735,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () ) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__18 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__18 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__18 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31568,7 +31768,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () ) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__22 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__22 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__22 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31601,7 +31801,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () )) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__26 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__26 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__26 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31634,7 +31834,7 @@ definition float_convert_fix_decode  :: "(1)Word.word \<Rightarrow>(1)Word.word
         UnallocatedEncoding () 
       else return () ) \<then>
      ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in
-     (let b__30 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
+     (let b__30 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) rmode  ::  4 Word.word)) in
      (if (((b__30 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) then
         (let (rounding :: FPRounding) = FPRounding_ZERO in
         (let (unsigned :: bool) =
@@ -31742,7 +31942,7 @@ definition float_arithmetic_round_decode  :: "(1)Word.word \<Rightarrow>(1)Word.
    undefined_FPRounding ()  \<bind> (\<lambda> (rounding :: FPRounding) . 
    (let v__101 = rmode in
    (if (((((subrange_vec_dec v__101 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) = (vec_of_bits [B0]  ::  1 Word.word)))) then
-      (let (rounding :: FPRounding) = (FPDecodeRounding ((slice0 rmode (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
+      (let (rounding :: FPRounding) = (FPDecodeRounding ((slice rmode (( 0 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word))) in
       return (exact, rounding))
     else if (((v__101 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) then
       (let (rounding :: FPRounding) = FPRounding_TIEAWAY in
@@ -32144,7 +32344,7 @@ definition AArch64_CheckForSMCUndefOrTrap  :: "(16)Word.word \<Rightarrow>((regi
      ExceptionSyndrome Exception_MonitorCall \<bind> (\<lambda> (w__15 :: ExceptionRecord) . 
      (let exception = w__15 in
      (let (tmp_40 :: 25 bits) = ((ExceptionRecord_syndrome   exception)) in
-     (let tmp_40 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_40 (( 0 :: int)::ii) imm  ::  25 Word.word)) in
+     (let tmp_40 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_40 (( 0 :: int)::ii) imm  ::  25 Word.word)) in
      (let exception = ((exception (| ExceptionRecord_syndrome := tmp_40 |))) in
      AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))
    else return () ))))))"
@@ -33153,7 +33353,7 @@ definition DecodeBitMasks  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>(6)Wo
    ((assert_exp ((len \<ge> (( 0 :: int)::ii))) ('''') \<then>
    (if ((len < (( 1 :: int)::ii))) then ReservedValue () 
     else return () )) \<then>
-   assert_exp ((M__tv \<ge> ((ex_int ((shl_int0 (( 1 :: int)::ii) len)))))) (''(M >= (1 << len))'')) \<then>
+   assert_exp ((M__tv \<ge> ((ex_int ((shl_int (( 1 :: int)::ii) len)))))) (''(M >= (1 << len))'')) \<then>
    ((let levels = ((zext_ones (( 6 :: int)::ii) len  ::  6 Word.word)) in
    (if (((immediate \<and> (((((and_vec imms levels  ::  6 Word.word)) = levels)))))) then
       ReservedValue () 
@@ -33401,7 +33601,7 @@ definition DecodeBitMasks  :: " int \<Rightarrow>(1)Word.word \<Rightarrow>(6)Wo
      (if (((((GetSlice_int ((make_the_value (( 1 :: int)::ii)  ::  1 itself)) diff (( 6 :: int)::ii)  ::  1 Word.word)) \<noteq> (vec_of_bits [B0]  ::  1 Word.word)))) then
        (and_vec wmask tmask  ::  64 Word.word)
      else (or_vec wmask tmask  ::  64 Word.word)) in
-   return ((slice0 wmask (( 0 :: int)::ii) M__tv  :: ( 'M::len)Word.word), (slice0 tmask (( 0 :: int)::ii) M__tv  :: ( 'M::len)Word.word))))))))))))))))))))))))))))))))))))"
+   return ((slice wmask (( 0 :: int)::ii) M__tv  :: ( 'M::len)Word.word), (slice tmask (( 0 :: int)::ii) M__tv  :: ( 'M::len)Word.word))))))))))))))))))))))))))))))))))))"
 
 
 (*val integer_logical_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*)
@@ -34546,56 +34746,6 @@ definition decode  :: "(32)Word.word \<Rightarrow>((register_value),(unit),(exce
      integer_arithmetic_div_decode sf op1 S Rm opcode2 o1 Rn Rd)))))))))"
 
 
-(*val fetch_and_execute : unit -> M unit*)
-
-definition fetch_and_execute  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " fetch_and_execute _ = (
-   (whileM () 
-     (\<lambda> unit_var .  return True)
-     (\<lambda> unit_var . 
-       (try_catch ((read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-                  (aget_Mem w__0 (( 4 :: int)::ii) AccType_IFETCH  :: ( 32 Word.word) M) \<bind> (\<lambda> instr . 
-                  decode instr))) (\<lambda>x .  
-  (case  x of
-      Error_Undefined _ => exit0 () 
-    | Error_See s =>
-  if(s = (''HINT'')) then (return () ) else (exit0 () )
-    | Error_Implementation_Defined _ => exit0 () 
-    | Error_ReservedEncoding _ => exit0 () 
-    | Error_ExceptionTaken _ => exit0 () 
-  )) \<then>
-       read_reg BranchTaken_ref) \<bind> (\<lambda> (w__1 :: bool) . 
-       if w__1 then write_reg BranchTaken_ref False
-       else
-         (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
-         write_reg PC_ref ((add_vec_int w__2 (( 4 :: int)::ii)  ::  64 Word.word)))))))"
-
-
-(*val main : unit -> M unit*)
-
-definition main  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " main _ = (
-   (write_reg
-     PC_ref
-     ((GetSlice_int ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) ((elf_entry () )) (( 0 :: int)::ii)
-        ::  64 Word.word)) \<then>
-   (ZeroExtend__0 (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)
-      ((make_the_value (( 64 :: int)::ii)  ::  64 itself))
-     :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . 
-   (write_reg SP_EL0_ref w__0 \<then>
-   read_reg PSTATE_ref) \<bind> (\<lambda> (w__1 :: ProcState) . 
-   (write_reg PSTATE_ref (w__1 (| ProcState_D := ((vec_of_bits [B1]  ::  1 Word.word))|)) \<then>
-   read_reg PSTATE_ref) \<bind> (\<lambda> (w__2 :: ProcState) . 
-   (write_reg PSTATE_ref (w__2 (| ProcState_A := ((vec_of_bits [B1]  ::  1 Word.word))|)) \<then>
-   read_reg PSTATE_ref) \<bind> (\<lambda> (w__3 :: ProcState) . 
-   (write_reg PSTATE_ref (w__3 (| ProcState_I := ((vec_of_bits [B1]  ::  1 Word.word))|)) \<then>
-   read_reg PSTATE_ref) \<bind> (\<lambda> (w__4 :: ProcState) . 
-   (write_reg PSTATE_ref (w__4 (| ProcState_F := ((vec_of_bits [B1]  ::  1 Word.word))|)) \<then>
-   (ZeroExtend__0 (vec_of_bits [B1,B0]  ::  2 Word.word) ((make_the_value (( 32 :: int)::ii)  ::  32 itself))
-     :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 bits) . 
-   (write_reg OSLSR_EL1_ref w__5 \<then> write_reg BranchTaken_ref False) \<then> fetch_and_execute () )))))))"
-
-
 (*val initialize_registers : unit -> M unit*)
 
 definition initialize_registers  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
diff --git a/snapshots/isabelle/aarch64/Aarch64_lemmas.thy b/snapshots/isabelle/aarch64/Aarch64_lemmas.thy
index 5a06d97e..5cd63a99 100644
--- a/snapshots/isabelle/aarch64/Aarch64_lemmas.thy
+++ b/snapshots/isabelle/aarch64/Aarch64_lemmas.thy
@@ -1,11 +1,11 @@
 theory Aarch64_lemmas
   imports
-    Sail.Sail_values_lemmas
-    Sail.State_lemmas
+    Sail.Sail2_values_lemmas
+    Sail.Sail2_state_lemmas
     Aarch64
 begin
 
-abbreviation "liftS \<equiv> liftState (get_regval, set_regval)"
+abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)"
 
 lemmas register_defs = get_regval_def set_regval_def APDAKeyHi_EL1_ref_def APDAKeyLo_EL1_ref_def
   APDBKeyHi_EL1_ref_def APDBKeyLo_EL1_ref_def APGAKeyHi_EL1_ref_def APGAKeyLo_EL1_ref_def
@@ -80,996 +80,1009 @@ proof -
   then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def)
 qed
 
-lemma liftS_read_reg_APDAKeyHi_EL1[simp]:
-  "liftS (read_reg APDAKeyHi_EL1_ref) = readS (APDAKeyHi_EL1 \<circ> regstate)"
+lemma option_of_rv_rv_of_option[simp]:
+  assumes "\<And>v. of_rv (rv_of v) = Some v"
+  shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v"
+  using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def)
+
+lemma list_of_rv_rv_of_list[simp]:
+  assumes "\<And>v. of_rv (rv_of v) = Some v"
+  shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v"
+proof -
+  from assms have "of_rv \<circ> rv_of = Some" by auto
+  with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def)
+qed
+
+lemma liftS_read_reg_APDAKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APDAKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APDAKeyHi_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APDAKeyHi_EL1[simp]:
-  "liftS (write_reg APDAKeyHi_EL1_ref v) = updateS (regstate_update (APDAKeyHi_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APDAKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APDAKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDAKeyHi_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APDAKeyLo_EL1[simp]:
-  "liftS (read_reg APDAKeyLo_EL1_ref) = readS (APDAKeyLo_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APDAKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APDAKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APDAKeyLo_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APDAKeyLo_EL1[simp]:
-  "liftS (write_reg APDAKeyLo_EL1_ref v) = updateS (regstate_update (APDAKeyLo_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APDAKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APDAKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDAKeyLo_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APDBKeyHi_EL1[simp]:
-  "liftS (read_reg APDBKeyHi_EL1_ref) = readS (APDBKeyHi_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APDBKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APDBKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APDBKeyHi_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APDBKeyHi_EL1[simp]:
-  "liftS (write_reg APDBKeyHi_EL1_ref v) = updateS (regstate_update (APDBKeyHi_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APDBKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APDBKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDBKeyHi_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APDBKeyLo_EL1[simp]:
-  "liftS (read_reg APDBKeyLo_EL1_ref) = readS (APDBKeyLo_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APDBKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APDBKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APDBKeyLo_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APDBKeyLo_EL1[simp]:
-  "liftS (write_reg APDBKeyLo_EL1_ref v) = updateS (regstate_update (APDBKeyLo_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APDBKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APDBKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDBKeyLo_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APGAKeyHi_EL1[simp]:
-  "liftS (read_reg APGAKeyHi_EL1_ref) = readS (APGAKeyHi_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APGAKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APGAKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APGAKeyHi_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APGAKeyHi_EL1[simp]:
-  "liftS (write_reg APGAKeyHi_EL1_ref v) = updateS (regstate_update (APGAKeyHi_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APGAKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APGAKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APGAKeyHi_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APGAKeyLo_EL1[simp]:
-  "liftS (read_reg APGAKeyLo_EL1_ref) = readS (APGAKeyLo_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APGAKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APGAKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APGAKeyLo_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APGAKeyLo_EL1[simp]:
-  "liftS (write_reg APGAKeyLo_EL1_ref v) = updateS (regstate_update (APGAKeyLo_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APGAKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APGAKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APGAKeyLo_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APIAKeyHi_EL1[simp]:
-  "liftS (read_reg APIAKeyHi_EL1_ref) = readS (APIAKeyHi_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APIAKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APIAKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APIAKeyHi_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APIAKeyHi_EL1[simp]:
-  "liftS (write_reg APIAKeyHi_EL1_ref v) = updateS (regstate_update (APIAKeyHi_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APIAKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APIAKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIAKeyHi_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APIAKeyLo_EL1[simp]:
-  "liftS (read_reg APIAKeyLo_EL1_ref) = readS (APIAKeyLo_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APIAKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APIAKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APIAKeyLo_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APIAKeyLo_EL1[simp]:
-  "liftS (write_reg APIAKeyLo_EL1_ref v) = updateS (regstate_update (APIAKeyLo_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APIAKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APIAKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIAKeyLo_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APIBKeyHi_EL1[simp]:
-  "liftS (read_reg APIBKeyHi_EL1_ref) = readS (APIBKeyHi_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APIBKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APIBKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APIBKeyHi_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APIBKeyHi_EL1[simp]:
-  "liftS (write_reg APIBKeyHi_EL1_ref v) = updateS (regstate_update (APIBKeyHi_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APIBKeyHi_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APIBKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIBKeyHi_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_APIBKeyLo_EL1[simp]:
-  "liftS (read_reg APIBKeyLo_EL1_ref) = readS (APIBKeyLo_EL1 \<circ> regstate)"
+lemma liftS_read_reg_APIBKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>read_reg APIBKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APIBKeyLo_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_APIBKeyLo_EL1[simp]:
-  "liftS (write_reg APIBKeyLo_EL1_ref v) = updateS (regstate_update (APIBKeyLo_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_APIBKeyLo_EL1[liftState_simp]:
+  "\<lbrakk>write_reg APIBKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIBKeyLo_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CONTEXTIDR_EL1[simp]:
-  "liftS (read_reg CONTEXTIDR_EL1_ref) = readS (CONTEXTIDR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_CONTEXTIDR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg CONTEXTIDR_EL1_ref\<rbrakk>\<^sub>S = readS (CONTEXTIDR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CONTEXTIDR_EL1[simp]:
-  "liftS (write_reg CONTEXTIDR_EL1_ref v) = updateS (regstate_update (CONTEXTIDR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CONTEXTIDR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg CONTEXTIDR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CONTEXTIDR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CONTEXTIDR_EL2[simp]:
-  "liftS (read_reg CONTEXTIDR_EL2_ref) = readS (CONTEXTIDR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_CONTEXTIDR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg CONTEXTIDR_EL2_ref\<rbrakk>\<^sub>S = readS (CONTEXTIDR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CONTEXTIDR_EL2[simp]:
-  "liftS (write_reg CONTEXTIDR_EL2_ref v) = updateS (regstate_update (CONTEXTIDR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CONTEXTIDR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg CONTEXTIDR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CONTEXTIDR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CPACR_EL1[simp]:
-  "liftS (read_reg CPACR_EL1_ref) = readS (CPACR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_CPACR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg CPACR_EL1_ref\<rbrakk>\<^sub>S = readS (CPACR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CPACR_EL1[simp]:
-  "liftS (write_reg CPACR_EL1_ref v) = updateS (regstate_update (CPACR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CPACR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg CPACR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CPACR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CPTR_EL2[simp]:
-  "liftS (read_reg CPTR_EL2_ref) = readS (CPTR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_CPTR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg CPTR_EL2_ref\<rbrakk>\<^sub>S = readS (CPTR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CPTR_EL2[simp]:
-  "liftS (write_reg CPTR_EL2_ref v) = updateS (regstate_update (CPTR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CPTR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg CPTR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CPTR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CPTR_EL3[simp]:
-  "liftS (read_reg CPTR_EL3_ref) = readS (CPTR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_CPTR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg CPTR_EL3_ref\<rbrakk>\<^sub>S = readS (CPTR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CPTR_EL3[simp]:
-  "liftS (write_reg CPTR_EL3_ref v) = updateS (regstate_update (CPTR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CPTR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg CPTR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CPTR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGBCR_EL1[simp]:
-  "liftS (read_reg DBGBCR_EL1_ref) = readS (DBGBCR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_DBGBCR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg DBGBCR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGBCR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGBCR_EL1[simp]:
-  "liftS (write_reg DBGBCR_EL1_ref v) = updateS (regstate_update (DBGBCR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGBCR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg DBGBCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGBCR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGBVR_EL1[simp]:
-  "liftS (read_reg DBGBVR_EL1_ref) = readS (DBGBVR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_DBGBVR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg DBGBVR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGBVR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGBVR_EL1[simp]:
-  "liftS (write_reg DBGBVR_EL1_ref v) = updateS (regstate_update (DBGBVR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGBVR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg DBGBVR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGBVR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGEN[simp]:
-  "liftS (read_reg DBGEN_ref) = readS (DBGEN \<circ> regstate)"
+lemma liftS_read_reg_DBGEN[liftState_simp]:
+  "\<lbrakk>read_reg DBGEN_ref\<rbrakk>\<^sub>S = readS (DBGEN \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGEN[simp]:
-  "liftS (write_reg DBGEN_ref v) = updateS (regstate_update (DBGEN_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGEN[liftState_simp]:
+  "\<lbrakk>write_reg DBGEN_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGEN_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGOSDLR[simp]:
-  "liftS (read_reg DBGOSDLR_ref) = readS (DBGOSDLR \<circ> regstate)"
+lemma liftS_read_reg_DBGOSDLR[liftState_simp]:
+  "\<lbrakk>read_reg DBGOSDLR_ref\<rbrakk>\<^sub>S = readS (DBGOSDLR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGOSDLR[simp]:
-  "liftS (write_reg DBGOSDLR_ref v) = updateS (regstate_update (DBGOSDLR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGOSDLR[liftState_simp]:
+  "\<lbrakk>write_reg DBGOSDLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGOSDLR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGOSLSR[simp]:
-  "liftS (read_reg DBGOSLSR_ref) = readS (DBGOSLSR \<circ> regstate)"
+lemma liftS_read_reg_DBGOSLSR[liftState_simp]:
+  "\<lbrakk>read_reg DBGOSLSR_ref\<rbrakk>\<^sub>S = readS (DBGOSLSR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGOSLSR[simp]:
-  "liftS (write_reg DBGOSLSR_ref v) = updateS (regstate_update (DBGOSLSR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGOSLSR[liftState_simp]:
+  "\<lbrakk>write_reg DBGOSLSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGOSLSR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGPRCR[simp]:
-  "liftS (read_reg DBGPRCR_ref) = readS (DBGPRCR \<circ> regstate)"
+lemma liftS_read_reg_DBGPRCR[liftState_simp]:
+  "\<lbrakk>read_reg DBGPRCR_ref\<rbrakk>\<^sub>S = readS (DBGPRCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGPRCR[simp]:
-  "liftS (write_reg DBGPRCR_ref v) = updateS (regstate_update (DBGPRCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGPRCR[liftState_simp]:
+  "\<lbrakk>write_reg DBGPRCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGPRCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGPRCR_EL1[simp]:
-  "liftS (read_reg DBGPRCR_EL1_ref) = readS (DBGPRCR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_DBGPRCR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg DBGPRCR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGPRCR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGPRCR_EL1[simp]:
-  "liftS (write_reg DBGPRCR_EL1_ref v) = updateS (regstate_update (DBGPRCR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGPRCR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg DBGPRCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGPRCR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGWCR_EL1[simp]:
-  "liftS (read_reg DBGWCR_EL1_ref) = readS (DBGWCR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_DBGWCR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg DBGWCR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGWCR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGWCR_EL1[simp]:
-  "liftS (write_reg DBGWCR_EL1_ref v) = updateS (regstate_update (DBGWCR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGWCR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg DBGWCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGWCR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DBGWVR_EL1[simp]:
-  "liftS (read_reg DBGWVR_EL1_ref) = readS (DBGWVR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_DBGWVR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg DBGWVR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGWVR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DBGWVR_EL1[simp]:
-  "liftS (write_reg DBGWVR_EL1_ref v) = updateS (regstate_update (DBGWVR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DBGWVR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg DBGWVR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGWVR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DLR[simp]:
-  "liftS (read_reg DLR_ref) = readS (DLR \<circ> regstate)"
+lemma liftS_read_reg_DLR[liftState_simp]:
+  "\<lbrakk>read_reg DLR_ref\<rbrakk>\<^sub>S = readS (DLR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DLR[simp]:
-  "liftS (write_reg DLR_ref v) = updateS (regstate_update (DLR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DLR[liftState_simp]:
+  "\<lbrakk>write_reg DLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DLR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DLR_EL0[simp]:
-  "liftS (read_reg DLR_EL0_ref) = readS (DLR_EL0 \<circ> regstate)"
+lemma liftS_read_reg_DLR_EL0[liftState_simp]:
+  "\<lbrakk>read_reg DLR_EL0_ref\<rbrakk>\<^sub>S = readS (DLR_EL0 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DLR_EL0[simp]:
-  "liftS (write_reg DLR_EL0_ref v) = updateS (regstate_update (DLR_EL0_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DLR_EL0[liftState_simp]:
+  "\<lbrakk>write_reg DLR_EL0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DLR_EL0_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DSPSR[simp]:
-  "liftS (read_reg DSPSR_ref) = readS (DSPSR \<circ> regstate)"
+lemma liftS_read_reg_DSPSR[liftState_simp]:
+  "\<lbrakk>read_reg DSPSR_ref\<rbrakk>\<^sub>S = readS (DSPSR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DSPSR[simp]:
-  "liftS (write_reg DSPSR_ref v) = updateS (regstate_update (DSPSR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DSPSR[liftState_simp]:
+  "\<lbrakk>write_reg DSPSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DSPSR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_DSPSR_EL0[simp]:
-  "liftS (read_reg DSPSR_EL0_ref) = readS (DSPSR_EL0 \<circ> regstate)"
+lemma liftS_read_reg_DSPSR_EL0[liftState_simp]:
+  "\<lbrakk>read_reg DSPSR_EL0_ref\<rbrakk>\<^sub>S = readS (DSPSR_EL0 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_DSPSR_EL0[simp]:
-  "liftS (write_reg DSPSR_EL0_ref v) = updateS (regstate_update (DSPSR_EL0_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DSPSR_EL0[liftState_simp]:
+  "\<lbrakk>write_reg DSPSR_EL0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DSPSR_EL0_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_EDSCR[simp]:
-  "liftS (read_reg EDSCR_ref) = readS (EDSCR \<circ> regstate)"
+lemma liftS_read_reg_EDSCR[liftState_simp]:
+  "\<lbrakk>read_reg EDSCR_ref\<rbrakk>\<^sub>S = readS (EDSCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_EDSCR[simp]:
-  "liftS (write_reg EDSCR_ref v) = updateS (regstate_update (EDSCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_EDSCR[liftState_simp]:
+  "\<lbrakk>write_reg EDSCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (EDSCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ELR_EL1[simp]:
-  "liftS (read_reg ELR_EL1_ref) = readS (ELR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_ELR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg ELR_EL1_ref\<rbrakk>\<^sub>S = readS (ELR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ELR_EL1[simp]:
-  "liftS (write_reg ELR_EL1_ref v) = updateS (regstate_update (ELR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ELR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg ELR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ELR_EL2[simp]:
-  "liftS (read_reg ELR_EL2_ref) = readS (ELR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_ELR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg ELR_EL2_ref\<rbrakk>\<^sub>S = readS (ELR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ELR_EL2[simp]:
-  "liftS (write_reg ELR_EL2_ref v) = updateS (regstate_update (ELR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ELR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg ELR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ELR_EL3[simp]:
-  "liftS (read_reg ELR_EL3_ref) = readS (ELR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_ELR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg ELR_EL3_ref\<rbrakk>\<^sub>S = readS (ELR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ELR_EL3[simp]:
-  "liftS (write_reg ELR_EL3_ref v) = updateS (regstate_update (ELR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ELR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg ELR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ELR_hyp[simp]:
-  "liftS (read_reg ELR_hyp_ref) = readS (ELR_hyp \<circ> regstate)"
+lemma liftS_read_reg_ELR_hyp[liftState_simp]:
+  "\<lbrakk>read_reg ELR_hyp_ref\<rbrakk>\<^sub>S = readS (ELR_hyp \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ELR_hyp[simp]:
-  "liftS (write_reg ELR_hyp_ref v) = updateS (regstate_update (ELR_hyp_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ELR_hyp[liftState_simp]:
+  "\<lbrakk>write_reg ELR_hyp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_hyp_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ESR_EL1[simp]:
-  "liftS (read_reg ESR_EL1_ref) = readS (ESR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_ESR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg ESR_EL1_ref\<rbrakk>\<^sub>S = readS (ESR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ESR_EL1[simp]:
-  "liftS (write_reg ESR_EL1_ref v) = updateS (regstate_update (ESR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ESR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg ESR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ESR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ESR_EL2[simp]:
-  "liftS (read_reg ESR_EL2_ref) = readS (ESR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_ESR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg ESR_EL2_ref\<rbrakk>\<^sub>S = readS (ESR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ESR_EL2[simp]:
-  "liftS (write_reg ESR_EL2_ref v) = updateS (regstate_update (ESR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ESR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg ESR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ESR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ESR_EL3[simp]:
-  "liftS (read_reg ESR_EL3_ref) = readS (ESR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_ESR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg ESR_EL3_ref\<rbrakk>\<^sub>S = readS (ESR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ESR_EL3[simp]:
-  "liftS (write_reg ESR_EL3_ref v) = updateS (regstate_update (ESR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ESR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg ESR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ESR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_EventRegister[simp]:
-  "liftS (read_reg EventRegister_ref) = readS (EventRegister \<circ> regstate)"
+lemma liftS_read_reg_EventRegister[liftState_simp]:
+  "\<lbrakk>read_reg EventRegister_ref\<rbrakk>\<^sub>S = readS (EventRegister \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_EventRegister[simp]:
-  "liftS (write_reg EventRegister_ref v) = updateS (regstate_update (EventRegister_update (\<lambda>_. v)))"
+lemma liftS_write_reg_EventRegister[liftState_simp]:
+  "\<lbrakk>write_reg EventRegister_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (EventRegister_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FAR_EL1[simp]:
-  "liftS (read_reg FAR_EL1_ref) = readS (FAR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_FAR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg FAR_EL1_ref\<rbrakk>\<^sub>S = readS (FAR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FAR_EL1[simp]:
-  "liftS (write_reg FAR_EL1_ref v) = updateS (regstate_update (FAR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FAR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg FAR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FAR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FAR_EL2[simp]:
-  "liftS (read_reg FAR_EL2_ref) = readS (FAR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_FAR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg FAR_EL2_ref\<rbrakk>\<^sub>S = readS (FAR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FAR_EL2[simp]:
-  "liftS (write_reg FAR_EL2_ref v) = updateS (regstate_update (FAR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FAR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg FAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FAR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FAR_EL3[simp]:
-  "liftS (read_reg FAR_EL3_ref) = readS (FAR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_FAR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg FAR_EL3_ref\<rbrakk>\<^sub>S = readS (FAR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FAR_EL3[simp]:
-  "liftS (write_reg FAR_EL3_ref v) = updateS (regstate_update (FAR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FAR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg FAR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FAR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FPCR[simp]:
-  "liftS (read_reg FPCR_ref) = readS (FPCR \<circ> regstate)"
+lemma liftS_read_reg_FPCR[liftState_simp]:
+  "\<lbrakk>read_reg FPCR_ref\<rbrakk>\<^sub>S = readS (FPCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FPCR[simp]:
-  "liftS (write_reg FPCR_ref v) = updateS (regstate_update (FPCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FPCR[liftState_simp]:
+  "\<lbrakk>write_reg FPCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FPEXC[simp]:
-  "liftS (read_reg FPEXC_ref) = readS (FPEXC \<circ> regstate)"
+lemma liftS_read_reg_FPEXC[liftState_simp]:
+  "\<lbrakk>read_reg FPEXC_ref\<rbrakk>\<^sub>S = readS (FPEXC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FPEXC[simp]:
-  "liftS (write_reg FPEXC_ref v) = updateS (regstate_update (FPEXC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FPEXC[liftState_simp]:
+  "\<lbrakk>write_reg FPEXC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPEXC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FPSCR[simp]:
-  "liftS (read_reg FPSCR_ref) = readS (FPSCR \<circ> regstate)"
+lemma liftS_read_reg_FPSCR[liftState_simp]:
+  "\<lbrakk>read_reg FPSCR_ref\<rbrakk>\<^sub>S = readS (FPSCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FPSCR[simp]:
-  "liftS (write_reg FPSCR_ref v) = updateS (regstate_update (FPSCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FPSCR[liftState_simp]:
+  "\<lbrakk>write_reg FPSCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPSCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_FPSR[simp]:
-  "liftS (read_reg FPSR_ref) = readS (FPSR \<circ> regstate)"
+lemma liftS_read_reg_FPSR[liftState_simp]:
+  "\<lbrakk>read_reg FPSR_ref\<rbrakk>\<^sub>S = readS (FPSR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_FPSR[simp]:
-  "liftS (write_reg FPSR_ref v) = updateS (regstate_update (FPSR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_FPSR[liftState_simp]:
+  "\<lbrakk>write_reg FPSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPSR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HCR[simp]:
-  "liftS (read_reg HCR_ref) = readS (HCR \<circ> regstate)"
+lemma liftS_read_reg_HCR[liftState_simp]:
+  "\<lbrakk>read_reg HCR_ref\<rbrakk>\<^sub>S = readS (HCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HCR[simp]:
-  "liftS (write_reg HCR_ref v) = updateS (regstate_update (HCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HCR[liftState_simp]:
+  "\<lbrakk>write_reg HCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HCR2[simp]:
-  "liftS (read_reg HCR2_ref) = readS (HCR2 \<circ> regstate)"
+lemma liftS_read_reg_HCR2[liftState_simp]:
+  "\<lbrakk>read_reg HCR2_ref\<rbrakk>\<^sub>S = readS (HCR2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HCR2[simp]:
-  "liftS (write_reg HCR2_ref v) = updateS (regstate_update (HCR2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HCR2[liftState_simp]:
+  "\<lbrakk>write_reg HCR2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HCR2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HCR_EL2[simp]:
-  "liftS (read_reg HCR_EL2_ref) = readS (HCR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_HCR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg HCR_EL2_ref\<rbrakk>\<^sub>S = readS (HCR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HCR_EL2[simp]:
-  "liftS (write_reg HCR_EL2_ref v) = updateS (regstate_update (HCR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HCR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg HCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HCR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HDCR[simp]:
-  "liftS (read_reg HDCR_ref) = readS (HDCR \<circ> regstate)"
+lemma liftS_read_reg_HDCR[liftState_simp]:
+  "\<lbrakk>read_reg HDCR_ref\<rbrakk>\<^sub>S = readS (HDCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HDCR[simp]:
-  "liftS (write_reg HDCR_ref v) = updateS (regstate_update (HDCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HDCR[liftState_simp]:
+  "\<lbrakk>write_reg HDCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HDCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HDFAR[simp]:
-  "liftS (read_reg HDFAR_ref) = readS (HDFAR \<circ> regstate)"
+lemma liftS_read_reg_HDFAR[liftState_simp]:
+  "\<lbrakk>read_reg HDFAR_ref\<rbrakk>\<^sub>S = readS (HDFAR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HDFAR[simp]:
-  "liftS (write_reg HDFAR_ref v) = updateS (regstate_update (HDFAR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HDFAR[liftState_simp]:
+  "\<lbrakk>write_reg HDFAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HDFAR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HIFAR[simp]:
-  "liftS (read_reg HIFAR_ref) = readS (HIFAR \<circ> regstate)"
+lemma liftS_read_reg_HIFAR[liftState_simp]:
+  "\<lbrakk>read_reg HIFAR_ref\<rbrakk>\<^sub>S = readS (HIFAR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HIFAR[simp]:
-  "liftS (write_reg HIFAR_ref v) = updateS (regstate_update (HIFAR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HIFAR[liftState_simp]:
+  "\<lbrakk>write_reg HIFAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HIFAR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HPFAR[simp]:
-  "liftS (read_reg HPFAR_ref) = readS (HPFAR \<circ> regstate)"
+lemma liftS_read_reg_HPFAR[liftState_simp]:
+  "\<lbrakk>read_reg HPFAR_ref\<rbrakk>\<^sub>S = readS (HPFAR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HPFAR[simp]:
-  "liftS (write_reg HPFAR_ref v) = updateS (regstate_update (HPFAR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HPFAR[liftState_simp]:
+  "\<lbrakk>write_reg HPFAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HPFAR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HPFAR_EL2[simp]:
-  "liftS (read_reg HPFAR_EL2_ref) = readS (HPFAR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_HPFAR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg HPFAR_EL2_ref\<rbrakk>\<^sub>S = readS (HPFAR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HPFAR_EL2[simp]:
-  "liftS (write_reg HPFAR_EL2_ref v) = updateS (regstate_update (HPFAR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HPFAR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg HPFAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HPFAR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HSCTLR[simp]:
-  "liftS (read_reg HSCTLR_ref) = readS (HSCTLR \<circ> regstate)"
+lemma liftS_read_reg_HSCTLR[liftState_simp]:
+  "\<lbrakk>read_reg HSCTLR_ref\<rbrakk>\<^sub>S = readS (HSCTLR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HSCTLR[simp]:
-  "liftS (write_reg HSCTLR_ref v) = updateS (regstate_update (HSCTLR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HSCTLR[liftState_simp]:
+  "\<lbrakk>write_reg HSCTLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HSCTLR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HSR[simp]:
-  "liftS (read_reg HSR_ref) = readS (HSR \<circ> regstate)"
+lemma liftS_read_reg_HSR[liftState_simp]:
+  "\<lbrakk>read_reg HSR_ref\<rbrakk>\<^sub>S = readS (HSR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HSR[simp]:
-  "liftS (write_reg HSR_ref v) = updateS (regstate_update (HSR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HSR[liftState_simp]:
+  "\<lbrakk>write_reg HSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HSR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HVBAR[simp]:
-  "liftS (read_reg HVBAR_ref) = readS (HVBAR \<circ> regstate)"
+lemma liftS_read_reg_HVBAR[liftState_simp]:
+  "\<lbrakk>read_reg HVBAR_ref\<rbrakk>\<^sub>S = readS (HVBAR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HVBAR[simp]:
-  "liftS (write_reg HVBAR_ref v) = updateS (regstate_update (HVBAR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HVBAR[liftState_simp]:
+  "\<lbrakk>write_reg HVBAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HVBAR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ID_AA64DFR0_EL1[simp]:
-  "liftS (read_reg ID_AA64DFR0_EL1_ref) = readS (ID_AA64DFR0_EL1 \<circ> regstate)"
+lemma liftS_read_reg_ID_AA64DFR0_EL1[liftState_simp]:
+  "\<lbrakk>read_reg ID_AA64DFR0_EL1_ref\<rbrakk>\<^sub>S = readS (ID_AA64DFR0_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ID_AA64DFR0_EL1[simp]:
-  "liftS (write_reg ID_AA64DFR0_EL1_ref v) = updateS (regstate_update (ID_AA64DFR0_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ID_AA64DFR0_EL1[liftState_simp]:
+  "\<lbrakk>write_reg ID_AA64DFR0_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ID_AA64DFR0_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_LR_mon[simp]:
-  "liftS (read_reg LR_mon_ref) = readS (LR_mon \<circ> regstate)"
+lemma liftS_read_reg_LR_mon[liftState_simp]:
+  "\<lbrakk>read_reg LR_mon_ref\<rbrakk>\<^sub>S = readS (LR_mon \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_LR_mon[simp]:
-  "liftS (write_reg LR_mon_ref v) = updateS (regstate_update (LR_mon_update (\<lambda>_. v)))"
+lemma liftS_write_reg_LR_mon[liftState_simp]:
+  "\<lbrakk>write_reg LR_mon_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (LR_mon_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_MAIR_EL1[simp]:
-  "liftS (read_reg MAIR_EL1_ref) = readS (MAIR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_MAIR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg MAIR_EL1_ref\<rbrakk>\<^sub>S = readS (MAIR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_MAIR_EL1[simp]:
-  "liftS (write_reg MAIR_EL1_ref v) = updateS (regstate_update (MAIR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_MAIR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg MAIR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MAIR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_MAIR_EL2[simp]:
-  "liftS (read_reg MAIR_EL2_ref) = readS (MAIR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_MAIR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg MAIR_EL2_ref\<rbrakk>\<^sub>S = readS (MAIR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_MAIR_EL2[simp]:
-  "liftS (write_reg MAIR_EL2_ref v) = updateS (regstate_update (MAIR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_MAIR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg MAIR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MAIR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_MAIR_EL3[simp]:
-  "liftS (read_reg MAIR_EL3_ref) = readS (MAIR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_MAIR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg MAIR_EL3_ref\<rbrakk>\<^sub>S = readS (MAIR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_MAIR_EL3[simp]:
-  "liftS (write_reg MAIR_EL3_ref v) = updateS (regstate_update (MAIR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_MAIR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg MAIR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MAIR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_MDCR_EL2[simp]:
-  "liftS (read_reg MDCR_EL2_ref) = readS (MDCR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_MDCR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg MDCR_EL2_ref\<rbrakk>\<^sub>S = readS (MDCR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_MDCR_EL2[simp]:
-  "liftS (write_reg MDCR_EL2_ref v) = updateS (regstate_update (MDCR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_MDCR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg MDCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MDCR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_MDCR_EL3[simp]:
-  "liftS (read_reg MDCR_EL3_ref) = readS (MDCR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_MDCR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg MDCR_EL3_ref\<rbrakk>\<^sub>S = readS (MDCR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_MDCR_EL3[simp]:
-  "liftS (write_reg MDCR_EL3_ref v) = updateS (regstate_update (MDCR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_MDCR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg MDCR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MDCR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_MDSCR_EL1[simp]:
-  "liftS (read_reg MDSCR_EL1_ref) = readS (MDSCR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_MDSCR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg MDSCR_EL1_ref\<rbrakk>\<^sub>S = readS (MDSCR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_MDSCR_EL1[simp]:
-  "liftS (write_reg MDSCR_EL1_ref v) = updateS (regstate_update (MDSCR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_MDSCR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg MDSCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MDSCR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_OSDLR_EL1[simp]:
-  "liftS (read_reg OSDLR_EL1_ref) = readS (OSDLR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_OSDLR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg OSDLR_EL1_ref\<rbrakk>\<^sub>S = readS (OSDLR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_OSDLR_EL1[simp]:
-  "liftS (write_reg OSDLR_EL1_ref v) = updateS (regstate_update (OSDLR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_OSDLR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg OSDLR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (OSDLR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_OSLSR_EL1[simp]:
-  "liftS (read_reg OSLSR_EL1_ref) = readS (OSLSR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_OSLSR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg OSLSR_EL1_ref\<rbrakk>\<^sub>S = readS (OSLSR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_OSLSR_EL1[simp]:
-  "liftS (write_reg OSLSR_EL1_ref v) = updateS (regstate_update (OSLSR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_OSLSR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg OSLSR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (OSLSR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PSTATE[simp]:
-  "liftS (read_reg PSTATE_ref) = readS (PSTATE \<circ> regstate)"
+lemma liftS_read_reg_PSTATE[liftState_simp]:
+  "\<lbrakk>read_reg PSTATE_ref\<rbrakk>\<^sub>S = readS (PSTATE \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PSTATE[simp]:
-  "liftS (write_reg PSTATE_ref v) = updateS (regstate_update (PSTATE_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PSTATE[liftState_simp]:
+  "\<lbrakk>write_reg PSTATE_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PSTATE_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_RC[simp]:
-  "liftS (read_reg RC_ref) = readS (RC \<circ> regstate)"
+lemma liftS_read_reg_RC[liftState_simp]:
+  "\<lbrakk>read_reg RC_ref\<rbrakk>\<^sub>S = readS (RC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_RC[simp]:
-  "liftS (write_reg RC_ref v) = updateS (regstate_update (RC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_RC[liftState_simp]:
+  "\<lbrakk>write_reg RC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_RVBAR_EL1[simp]:
-  "liftS (read_reg RVBAR_EL1_ref) = readS (RVBAR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_RVBAR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg RVBAR_EL1_ref\<rbrakk>\<^sub>S = readS (RVBAR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_RVBAR_EL1[simp]:
-  "liftS (write_reg RVBAR_EL1_ref v) = updateS (regstate_update (RVBAR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_RVBAR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg RVBAR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RVBAR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_RVBAR_EL2[simp]:
-  "liftS (read_reg RVBAR_EL2_ref) = readS (RVBAR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_RVBAR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg RVBAR_EL2_ref\<rbrakk>\<^sub>S = readS (RVBAR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_RVBAR_EL2[simp]:
-  "liftS (write_reg RVBAR_EL2_ref v) = updateS (regstate_update (RVBAR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_RVBAR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg RVBAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RVBAR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_RVBAR_EL3[simp]:
-  "liftS (read_reg RVBAR_EL3_ref) = readS (RVBAR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_RVBAR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg RVBAR_EL3_ref\<rbrakk>\<^sub>S = readS (RVBAR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_RVBAR_EL3[simp]:
-  "liftS (write_reg RVBAR_EL3_ref v) = updateS (regstate_update (RVBAR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_RVBAR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg RVBAR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RVBAR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SCR[simp]:
-  "liftS (read_reg SCR_ref) = readS (SCR \<circ> regstate)"
+lemma liftS_read_reg_SCR[liftState_simp]:
+  "\<lbrakk>read_reg SCR_ref\<rbrakk>\<^sub>S = readS (SCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SCR[simp]:
-  "liftS (write_reg SCR_ref v) = updateS (regstate_update (SCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SCR[liftState_simp]:
+  "\<lbrakk>write_reg SCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SCR_EL3[simp]:
-  "liftS (read_reg SCR_EL3_ref) = readS (SCR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_SCR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg SCR_EL3_ref\<rbrakk>\<^sub>S = readS (SCR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SCR_EL3[simp]:
-  "liftS (write_reg SCR_EL3_ref v) = updateS (regstate_update (SCR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SCR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg SCR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SCTLR[simp]:
-  "liftS (read_reg SCTLR_ref) = readS (SCTLR \<circ> regstate)"
+lemma liftS_read_reg_SCTLR[liftState_simp]:
+  "\<lbrakk>read_reg SCTLR_ref\<rbrakk>\<^sub>S = readS (SCTLR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SCTLR[simp]:
-  "liftS (write_reg SCTLR_ref v) = updateS (regstate_update (SCTLR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SCTLR[liftState_simp]:
+  "\<lbrakk>write_reg SCTLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SCTLR_EL1[simp]:
-  "liftS (read_reg SCTLR_EL1_ref) = readS (SCTLR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_SCTLR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg SCTLR_EL1_ref\<rbrakk>\<^sub>S = readS (SCTLR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SCTLR_EL1[simp]:
-  "liftS (write_reg SCTLR_EL1_ref v) = updateS (regstate_update (SCTLR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SCTLR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg SCTLR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SCTLR_EL2[simp]:
-  "liftS (read_reg SCTLR_EL2_ref) = readS (SCTLR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_SCTLR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg SCTLR_EL2_ref\<rbrakk>\<^sub>S = readS (SCTLR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SCTLR_EL2[simp]:
-  "liftS (write_reg SCTLR_EL2_ref v) = updateS (regstate_update (SCTLR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SCTLR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg SCTLR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SCTLR_EL3[simp]:
-  "liftS (read_reg SCTLR_EL3_ref) = readS (SCTLR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_SCTLR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg SCTLR_EL3_ref\<rbrakk>\<^sub>S = readS (SCTLR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SCTLR_EL3[simp]:
-  "liftS (write_reg SCTLR_EL3_ref v) = updateS (regstate_update (SCTLR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SCTLR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg SCTLR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SDCR[simp]:
-  "liftS (read_reg SDCR_ref) = readS (SDCR \<circ> regstate)"
+lemma liftS_read_reg_SDCR[liftState_simp]:
+  "\<lbrakk>read_reg SDCR_ref\<rbrakk>\<^sub>S = readS (SDCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SDCR[simp]:
-  "liftS (write_reg SDCR_ref v) = updateS (regstate_update (SDCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SDCR[liftState_simp]:
+  "\<lbrakk>write_reg SDCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SDCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SDER[simp]:
-  "liftS (read_reg SDER_ref) = readS (SDER \<circ> regstate)"
+lemma liftS_read_reg_SDER[liftState_simp]:
+  "\<lbrakk>read_reg SDER_ref\<rbrakk>\<^sub>S = readS (SDER \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SDER[simp]:
-  "liftS (write_reg SDER_ref v) = updateS (regstate_update (SDER_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SDER[liftState_simp]:
+  "\<lbrakk>write_reg SDER_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SDER_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPIDEN[simp]:
-  "liftS (read_reg SPIDEN_ref) = readS (SPIDEN \<circ> regstate)"
+lemma liftS_read_reg_SPIDEN[liftState_simp]:
+  "\<lbrakk>read_reg SPIDEN_ref\<rbrakk>\<^sub>S = readS (SPIDEN \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPIDEN[simp]:
-  "liftS (write_reg SPIDEN_ref v) = updateS (regstate_update (SPIDEN_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPIDEN[liftState_simp]:
+  "\<lbrakk>write_reg SPIDEN_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPIDEN_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_EL1[simp]:
-  "liftS (read_reg SPSR_EL1_ref) = readS (SPSR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_SPSR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_EL1_ref\<rbrakk>\<^sub>S = readS (SPSR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_EL1[simp]:
-  "liftS (write_reg SPSR_EL1_ref v) = updateS (regstate_update (SPSR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_EL2[simp]:
-  "liftS (read_reg SPSR_EL2_ref) = readS (SPSR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_SPSR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_EL2_ref\<rbrakk>\<^sub>S = readS (SPSR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_EL2[simp]:
-  "liftS (write_reg SPSR_EL2_ref v) = updateS (regstate_update (SPSR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_EL3[simp]:
-  "liftS (read_reg SPSR_EL3_ref) = readS (SPSR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_SPSR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_EL3_ref\<rbrakk>\<^sub>S = readS (SPSR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_EL3[simp]:
-  "liftS (write_reg SPSR_EL3_ref v) = updateS (regstate_update (SPSR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_abt[simp]:
-  "liftS (read_reg SPSR_abt_ref) = readS (SPSR_abt \<circ> regstate)"
+lemma liftS_read_reg_SPSR_abt[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_abt_ref\<rbrakk>\<^sub>S = readS (SPSR_abt \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_abt[simp]:
-  "liftS (write_reg SPSR_abt_ref v) = updateS (regstate_update (SPSR_abt_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_abt[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_abt_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_abt_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_fiq[simp]:
-  "liftS (read_reg SPSR_fiq_ref) = readS (SPSR_fiq \<circ> regstate)"
+lemma liftS_read_reg_SPSR_fiq[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_fiq_ref\<rbrakk>\<^sub>S = readS (SPSR_fiq \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_fiq[simp]:
-  "liftS (write_reg SPSR_fiq_ref v) = updateS (regstate_update (SPSR_fiq_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_fiq[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_fiq_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_fiq_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_hyp[simp]:
-  "liftS (read_reg SPSR_hyp_ref) = readS (SPSR_hyp \<circ> regstate)"
+lemma liftS_read_reg_SPSR_hyp[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_hyp_ref\<rbrakk>\<^sub>S = readS (SPSR_hyp \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_hyp[simp]:
-  "liftS (write_reg SPSR_hyp_ref v) = updateS (regstate_update (SPSR_hyp_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_hyp[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_hyp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_hyp_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_irq[simp]:
-  "liftS (read_reg SPSR_irq_ref) = readS (SPSR_irq \<circ> regstate)"
+lemma liftS_read_reg_SPSR_irq[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_irq_ref\<rbrakk>\<^sub>S = readS (SPSR_irq \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_irq[simp]:
-  "liftS (write_reg SPSR_irq_ref v) = updateS (regstate_update (SPSR_irq_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_irq[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_irq_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_irq_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_mon[simp]:
-  "liftS (read_reg SPSR_mon_ref) = readS (SPSR_mon \<circ> regstate)"
+lemma liftS_read_reg_SPSR_mon[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_mon_ref\<rbrakk>\<^sub>S = readS (SPSR_mon \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_mon[simp]:
-  "liftS (write_reg SPSR_mon_ref v) = updateS (regstate_update (SPSR_mon_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_mon[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_mon_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_mon_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_svc[simp]:
-  "liftS (read_reg SPSR_svc_ref) = readS (SPSR_svc \<circ> regstate)"
+lemma liftS_read_reg_SPSR_svc[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_svc_ref\<rbrakk>\<^sub>S = readS (SPSR_svc \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_svc[simp]:
-  "liftS (write_reg SPSR_svc_ref v) = updateS (regstate_update (SPSR_svc_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_svc[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_svc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_svc_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SPSR_und[simp]:
-  "liftS (read_reg SPSR_und_ref) = readS (SPSR_und \<circ> regstate)"
+lemma liftS_read_reg_SPSR_und[liftState_simp]:
+  "\<lbrakk>read_reg SPSR_und_ref\<rbrakk>\<^sub>S = readS (SPSR_und \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SPSR_und[simp]:
-  "liftS (write_reg SPSR_und_ref v) = updateS (regstate_update (SPSR_und_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SPSR_und[liftState_simp]:
+  "\<lbrakk>write_reg SPSR_und_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_und_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SP_EL0[simp]:
-  "liftS (read_reg SP_EL0_ref) = readS (SP_EL0 \<circ> regstate)"
+lemma liftS_read_reg_SP_EL0[liftState_simp]:
+  "\<lbrakk>read_reg SP_EL0_ref\<rbrakk>\<^sub>S = readS (SP_EL0 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SP_EL0[simp]:
-  "liftS (write_reg SP_EL0_ref v) = updateS (regstate_update (SP_EL0_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SP_EL0[liftState_simp]:
+  "\<lbrakk>write_reg SP_EL0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL0_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SP_EL1[simp]:
-  "liftS (read_reg SP_EL1_ref) = readS (SP_EL1 \<circ> regstate)"
+lemma liftS_read_reg_SP_EL1[liftState_simp]:
+  "\<lbrakk>read_reg SP_EL1_ref\<rbrakk>\<^sub>S = readS (SP_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SP_EL1[simp]:
-  "liftS (write_reg SP_EL1_ref v) = updateS (regstate_update (SP_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SP_EL1[liftState_simp]:
+  "\<lbrakk>write_reg SP_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SP_EL2[simp]:
-  "liftS (read_reg SP_EL2_ref) = readS (SP_EL2 \<circ> regstate)"
+lemma liftS_read_reg_SP_EL2[liftState_simp]:
+  "\<lbrakk>read_reg SP_EL2_ref\<rbrakk>\<^sub>S = readS (SP_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SP_EL2[simp]:
-  "liftS (write_reg SP_EL2_ref v) = updateS (regstate_update (SP_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SP_EL2[liftState_simp]:
+  "\<lbrakk>write_reg SP_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SP_EL3[simp]:
-  "liftS (read_reg SP_EL3_ref) = readS (SP_EL3 \<circ> regstate)"
+lemma liftS_read_reg_SP_EL3[liftState_simp]:
+  "\<lbrakk>read_reg SP_EL3_ref\<rbrakk>\<^sub>S = readS (SP_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SP_EL3[simp]:
-  "liftS (write_reg SP_EL3_ref v) = updateS (regstate_update (SP_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SP_EL3[liftState_simp]:
+  "\<lbrakk>write_reg SP_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_SP_mon[simp]:
-  "liftS (read_reg SP_mon_ref) = readS (SP_mon \<circ> regstate)"
+lemma liftS_read_reg_SP_mon[liftState_simp]:
+  "\<lbrakk>read_reg SP_mon_ref\<rbrakk>\<^sub>S = readS (SP_mon \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_SP_mon[simp]:
-  "liftS (write_reg SP_mon_ref v) = updateS (regstate_update (SP_mon_update (\<lambda>_. v)))"
+lemma liftS_write_reg_SP_mon[liftState_simp]:
+  "\<lbrakk>write_reg SP_mon_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_mon_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TCR_EL1[simp]:
-  "liftS (read_reg TCR_EL1_ref) = readS (TCR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_TCR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg TCR_EL1_ref\<rbrakk>\<^sub>S = readS (TCR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TCR_EL1[simp]:
-  "liftS (write_reg TCR_EL1_ref v) = updateS (regstate_update (TCR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TCR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg TCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TCR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TCR_EL2[simp]:
-  "liftS (read_reg TCR_EL2_ref) = readS (TCR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_TCR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg TCR_EL2_ref\<rbrakk>\<^sub>S = readS (TCR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TCR_EL2[simp]:
-  "liftS (write_reg TCR_EL2_ref v) = updateS (regstate_update (TCR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TCR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg TCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TCR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TCR_EL3[simp]:
-  "liftS (read_reg TCR_EL3_ref) = readS (TCR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_TCR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg TCR_EL3_ref\<rbrakk>\<^sub>S = readS (TCR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TCR_EL3[simp]:
-  "liftS (write_reg TCR_EL3_ref v) = updateS (regstate_update (TCR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TCR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg TCR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TCR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TTBCR[simp]:
-  "liftS (read_reg TTBCR_ref) = readS (TTBCR \<circ> regstate)"
+lemma liftS_read_reg_TTBCR[liftState_simp]:
+  "\<lbrakk>read_reg TTBCR_ref\<rbrakk>\<^sub>S = readS (TTBCR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TTBCR[simp]:
-  "liftS (write_reg TTBCR_ref v) = updateS (regstate_update (TTBCR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TTBCR[liftState_simp]:
+  "\<lbrakk>write_reg TTBCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBCR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TTBR0_EL1[simp]:
-  "liftS (read_reg TTBR0_EL1_ref) = readS (TTBR0_EL1 \<circ> regstate)"
+lemma liftS_read_reg_TTBR0_EL1[liftState_simp]:
+  "\<lbrakk>read_reg TTBR0_EL1_ref\<rbrakk>\<^sub>S = readS (TTBR0_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TTBR0_EL1[simp]:
-  "liftS (write_reg TTBR0_EL1_ref v) = updateS (regstate_update (TTBR0_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TTBR0_EL1[liftState_simp]:
+  "\<lbrakk>write_reg TTBR0_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR0_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TTBR0_EL2[simp]:
-  "liftS (read_reg TTBR0_EL2_ref) = readS (TTBR0_EL2 \<circ> regstate)"
+lemma liftS_read_reg_TTBR0_EL2[liftState_simp]:
+  "\<lbrakk>read_reg TTBR0_EL2_ref\<rbrakk>\<^sub>S = readS (TTBR0_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TTBR0_EL2[simp]:
-  "liftS (write_reg TTBR0_EL2_ref v) = updateS (regstate_update (TTBR0_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TTBR0_EL2[liftState_simp]:
+  "\<lbrakk>write_reg TTBR0_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR0_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TTBR0_EL3[simp]:
-  "liftS (read_reg TTBR0_EL3_ref) = readS (TTBR0_EL3 \<circ> regstate)"
+lemma liftS_read_reg_TTBR0_EL3[liftState_simp]:
+  "\<lbrakk>read_reg TTBR0_EL3_ref\<rbrakk>\<^sub>S = readS (TTBR0_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TTBR0_EL3[simp]:
-  "liftS (write_reg TTBR0_EL3_ref v) = updateS (regstate_update (TTBR0_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TTBR0_EL3[liftState_simp]:
+  "\<lbrakk>write_reg TTBR0_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR0_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TTBR1_EL1[simp]:
-  "liftS (read_reg TTBR1_EL1_ref) = readS (TTBR1_EL1 \<circ> regstate)"
+lemma liftS_read_reg_TTBR1_EL1[liftState_simp]:
+  "\<lbrakk>read_reg TTBR1_EL1_ref\<rbrakk>\<^sub>S = readS (TTBR1_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TTBR1_EL1[simp]:
-  "liftS (write_reg TTBR1_EL1_ref v) = updateS (regstate_update (TTBR1_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TTBR1_EL1[liftState_simp]:
+  "\<lbrakk>write_reg TTBR1_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR1_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TTBR1_EL2[simp]:
-  "liftS (read_reg TTBR1_EL2_ref) = readS (TTBR1_EL2 \<circ> regstate)"
+lemma liftS_read_reg_TTBR1_EL2[liftState_simp]:
+  "\<lbrakk>read_reg TTBR1_EL2_ref\<rbrakk>\<^sub>S = readS (TTBR1_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TTBR1_EL2[simp]:
-  "liftS (write_reg TTBR1_EL2_ref v) = updateS (regstate_update (TTBR1_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TTBR1_EL2[liftState_simp]:
+  "\<lbrakk>write_reg TTBR1_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR1_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VBAR[simp]:
-  "liftS (read_reg VBAR_ref) = readS (VBAR \<circ> regstate)"
+lemma liftS_read_reg_VBAR[liftState_simp]:
+  "\<lbrakk>read_reg VBAR_ref\<rbrakk>\<^sub>S = readS (VBAR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VBAR[simp]:
-  "liftS (write_reg VBAR_ref v) = updateS (regstate_update (VBAR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VBAR[liftState_simp]:
+  "\<lbrakk>write_reg VBAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VBAR_EL1[simp]:
-  "liftS (read_reg VBAR_EL1_ref) = readS (VBAR_EL1 \<circ> regstate)"
+lemma liftS_read_reg_VBAR_EL1[liftState_simp]:
+  "\<lbrakk>read_reg VBAR_EL1_ref\<rbrakk>\<^sub>S = readS (VBAR_EL1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VBAR_EL1[simp]:
-  "liftS (write_reg VBAR_EL1_ref v) = updateS (regstate_update (VBAR_EL1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VBAR_EL1[liftState_simp]:
+  "\<lbrakk>write_reg VBAR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_EL1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VBAR_EL2[simp]:
-  "liftS (read_reg VBAR_EL2_ref) = readS (VBAR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_VBAR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg VBAR_EL2_ref\<rbrakk>\<^sub>S = readS (VBAR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VBAR_EL2[simp]:
-  "liftS (write_reg VBAR_EL2_ref v) = updateS (regstate_update (VBAR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VBAR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg VBAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VBAR_EL3[simp]:
-  "liftS (read_reg VBAR_EL3_ref) = readS (VBAR_EL3 \<circ> regstate)"
+lemma liftS_read_reg_VBAR_EL3[liftState_simp]:
+  "\<lbrakk>read_reg VBAR_EL3_ref\<rbrakk>\<^sub>S = readS (VBAR_EL3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VBAR_EL3[simp]:
-  "liftS (write_reg VBAR_EL3_ref v) = updateS (regstate_update (VBAR_EL3_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VBAR_EL3[liftState_simp]:
+  "\<lbrakk>write_reg VBAR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_EL3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VDFSR[simp]:
-  "liftS (read_reg VDFSR_ref) = readS (VDFSR \<circ> regstate)"
+lemma liftS_read_reg_VDFSR[liftState_simp]:
+  "\<lbrakk>read_reg VDFSR_ref\<rbrakk>\<^sub>S = readS (VDFSR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VDFSR[simp]:
-  "liftS (write_reg VDFSR_ref v) = updateS (regstate_update (VDFSR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VDFSR[liftState_simp]:
+  "\<lbrakk>write_reg VDFSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VDFSR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VSESR_EL2[simp]:
-  "liftS (read_reg VSESR_EL2_ref) = readS (VSESR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_VSESR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg VSESR_EL2_ref\<rbrakk>\<^sub>S = readS (VSESR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VSESR_EL2[simp]:
-  "liftS (write_reg VSESR_EL2_ref v) = updateS (regstate_update (VSESR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VSESR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg VSESR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VSESR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VTCR_EL2[simp]:
-  "liftS (read_reg VTCR_EL2_ref) = readS (VTCR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_VTCR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg VTCR_EL2_ref\<rbrakk>\<^sub>S = readS (VTCR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VTCR_EL2[simp]:
-  "liftS (write_reg VTCR_EL2_ref v) = updateS (regstate_update (VTCR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VTCR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg VTCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VTCR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_VTTBR_EL2[simp]:
-  "liftS (read_reg VTTBR_EL2_ref) = readS (VTTBR_EL2 \<circ> regstate)"
+lemma liftS_read_reg_VTTBR_EL2[liftState_simp]:
+  "\<lbrakk>read_reg VTTBR_EL2_ref\<rbrakk>\<^sub>S = readS (VTTBR_EL2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_VTTBR_EL2[simp]:
-  "liftS (write_reg VTTBR_EL2_ref v) = updateS (regstate_update (VTTBR_EL2_update (\<lambda>_. v)))"
+lemma liftS_write_reg_VTTBR_EL2[liftState_simp]:
+  "\<lbrakk>write_reg VTTBR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VTTBR_EL2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PC[simp]:
-  "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)"
+lemma liftS_read_reg_PC[liftState_simp]:
+  "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PC[simp]:
-  "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PC[liftState_simp]:
+  "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_R[simp]:
-  "liftS (read_reg R_ref) = readS (R \<circ> regstate)"
+lemma liftS_read_reg_R[liftState_simp]:
+  "\<lbrakk>read_reg R_ref\<rbrakk>\<^sub>S = readS (R \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_R[simp]:
-  "liftS (write_reg R_ref v) = updateS (regstate_update (R_update (\<lambda>_. v)))"
+lemma liftS_write_reg_R[liftState_simp]:
+  "\<lbrakk>write_reg R_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (R_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_V[simp]:
-  "liftS (read_reg V_ref) = readS (V \<circ> regstate)"
+lemma liftS_read_reg_V[liftState_simp]:
+  "\<lbrakk>read_reg V_ref\<rbrakk>\<^sub>S = readS (V \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_V[simp]:
-  "liftS (write_reg V_ref v) = updateS (regstate_update (V_update (\<lambda>_. v)))"
+lemma liftS_write_reg_V[liftState_simp]:
+  "\<lbrakk>write_reg V_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (V_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_BranchTaken[simp]:
-  "liftS (read_reg BranchTaken_ref) = readS (BranchTaken \<circ> regstate)"
+lemma liftS_read_reg_BranchTaken[liftState_simp]:
+  "\<lbrakk>read_reg BranchTaken_ref\<rbrakk>\<^sub>S = readS (BranchTaken \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_BranchTaken[simp]:
-  "liftS (write_reg BranchTaken_ref v) = updateS (regstate_update (BranchTaken_update (\<lambda>_. v)))"
+lemma liftS_write_reg_BranchTaken[liftState_simp]:
+  "\<lbrakk>write_reg BranchTaken_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (BranchTaken_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ExclusiveLocal[simp]:
-  "liftS (read_reg ExclusiveLocal_ref) = readS (ExclusiveLocal \<circ> regstate)"
+lemma liftS_read_reg_ExclusiveLocal[liftState_simp]:
+  "\<lbrakk>read_reg ExclusiveLocal_ref\<rbrakk>\<^sub>S = readS (ExclusiveLocal \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ExclusiveLocal[simp]:
-  "liftS (write_reg ExclusiveLocal_ref v) = updateS (regstate_update (ExclusiveLocal_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ExclusiveLocal[liftState_simp]:
+  "\<lbrakk>write_reg ExclusiveLocal_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ExclusiveLocal_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_Memory[simp]:
-  "liftS (read_reg Memory_ref) = readS (Memory \<circ> regstate)"
+lemma liftS_read_reg_Memory[liftState_simp]:
+  "\<lbrakk>read_reg Memory_ref\<rbrakk>\<^sub>S = readS (Memory \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_Memory[simp]:
-  "liftS (write_reg Memory_ref v) = updateS (regstate_update (Memory_update (\<lambda>_. v)))"
+lemma liftS_write_reg_Memory[liftState_simp]:
+  "\<lbrakk>write_reg Memory_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Memory_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PendingInterrupt[simp]:
-  "liftS (read_reg PendingInterrupt_ref) = readS (PendingInterrupt \<circ> regstate)"
+lemma liftS_read_reg_PendingInterrupt[liftState_simp]:
+  "\<lbrakk>read_reg PendingInterrupt_ref\<rbrakk>\<^sub>S = readS (PendingInterrupt \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PendingInterrupt[simp]:
-  "liftS (write_reg PendingInterrupt_ref v) = updateS (regstate_update (PendingInterrupt_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PendingInterrupt[liftState_simp]:
+  "\<lbrakk>write_reg PendingInterrupt_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PendingInterrupt_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PendingPhysicalSError[simp]:
-  "liftS (read_reg PendingPhysicalSError_ref) = readS (PendingPhysicalSError \<circ> regstate)"
+lemma liftS_read_reg_PendingPhysicalSError[liftState_simp]:
+  "\<lbrakk>read_reg PendingPhysicalSError_ref\<rbrakk>\<^sub>S = readS (PendingPhysicalSError \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PendingPhysicalSError[simp]:
-  "liftS (write_reg PendingPhysicalSError_ref v) = updateS (regstate_update (PendingPhysicalSError_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PendingPhysicalSError[liftState_simp]:
+  "\<lbrakk>write_reg PendingPhysicalSError_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PendingPhysicalSError_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_Sleeping[simp]:
-  "liftS (read_reg Sleeping_ref) = readS (Sleeping \<circ> regstate)"
+lemma liftS_read_reg_Sleeping[liftState_simp]:
+  "\<lbrakk>read_reg Sleeping_ref\<rbrakk>\<^sub>S = readS (Sleeping \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_Sleeping[simp]:
-  "liftS (write_reg Sleeping_ref v) = updateS (regstate_update (Sleeping_update (\<lambda>_. v)))"
+lemma liftS_write_reg_Sleeping[liftState_simp]:
+  "\<lbrakk>write_reg Sleeping_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Sleeping_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ThisInstr[simp]:
-  "liftS (read_reg ThisInstr_ref) = readS (ThisInstr \<circ> regstate)"
+lemma liftS_read_reg_ThisInstr[liftState_simp]:
+  "\<lbrakk>read_reg ThisInstr_ref\<rbrakk>\<^sub>S = readS (ThisInstr \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ThisInstr[simp]:
-  "liftS (write_reg ThisInstr_ref v) = updateS (regstate_update (ThisInstr_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ThisInstr[liftState_simp]:
+  "\<lbrakk>write_reg ThisInstr_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ThisInstr_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_ThisInstrEnc[simp]:
-  "liftS (read_reg ThisInstrEnc_ref) = readS (ThisInstrEnc \<circ> regstate)"
+lemma liftS_read_reg_ThisInstrEnc[liftState_simp]:
+  "\<lbrakk>read_reg ThisInstrEnc_ref\<rbrakk>\<^sub>S = readS (ThisInstrEnc \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_ThisInstrEnc[simp]:
-  "liftS (write_reg ThisInstrEnc_ref v) = updateS (regstate_update (ThisInstrEnc_update (\<lambda>_. v)))"
+lemma liftS_write_reg_ThisInstrEnc[liftState_simp]:
+  "\<lbrakk>write_reg ThisInstrEnc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ThisInstrEnc_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_currentCond[simp]:
-  "liftS (read_reg currentCond_ref) = readS (currentCond \<circ> regstate)"
+lemma liftS_read_reg_currentCond[liftState_simp]:
+  "\<lbrakk>read_reg currentCond_ref\<rbrakk>\<^sub>S = readS (currentCond \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_currentCond[simp]:
-  "liftS (write_reg currentCond_ref v) = updateS (regstate_update (currentCond_update (\<lambda>_. v)))"
+lemma liftS_write_reg_currentCond[liftState_simp]:
+  "\<lbrakk>write_reg currentCond_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (currentCond_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_unconditional[simp]:
-  "liftS (read_reg unconditional_ref) = readS (unconditional \<circ> regstate)"
+lemma liftS_read_reg_unconditional[liftState_simp]:
+  "\<lbrakk>read_reg unconditional_ref\<rbrakk>\<^sub>S = readS (unconditional \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_unconditional[simp]:
-  "liftS (write_reg unconditional_ref v) = updateS (regstate_update (unconditional_update (\<lambda>_. v)))"
+lemma liftS_write_reg_unconditional[liftState_simp]:
+  "\<lbrakk>write_reg unconditional_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (unconditional_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
 end
diff --git a/snapshots/isabelle/aarch64/Aarch64_types.thy b/snapshots/isabelle/aarch64/Aarch64_types.thy
index b2379614..33d9cafc 100644
--- a/snapshots/isabelle/aarch64/Aarch64_types.thy
+++ b/snapshots/isabelle/aarch64/Aarch64_types.thy
@@ -5,23 +5,23 @@ theory "Aarch64_types"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
+	 "/tmp/sail/src/lem_interp/Sail2_instr_kinds" 
+	 "/tmp/sail/src/gen_lib/Sail2_values" 
+	 "/tmp/sail/src/gen_lib/Sail2_operators_mwords" 
+	 "/tmp/sail/src/gen_lib/Sail2_prompt_monad" 
+	 "/tmp/sail/src/gen_lib/Sail2_prompt" 
+	 "/tmp/sail/src/gen_lib/Sail2_string" 
 
 begin 
 
 (*Generated by Sail from aarch64.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 type_synonym 'n bits =" ( 'n::len)Word.word "
 
 datatype exception  =
@@ -957,7 +957,7 @@ record regstate  =
 
 fun ProcState_of_regval  :: " register_value \<Rightarrow>(ProcState)option "  where 
      " ProcState_of_regval (Regval_ProcState (v)) = ( Some v )"
-|" ProcState_of_regval g__605 = ( None )"
+|" ProcState_of_regval g__281 = ( None )"
 
 
 (*val regval_of_ProcState : ProcState -> register_value*)
@@ -970,7 +970,7 @@ definition regval_of_ProcState  :: " ProcState \<Rightarrow> register_value "  w
 
 fun InstrEnc_of_regval  :: " register_value \<Rightarrow>(InstrEnc)option "  where 
      " InstrEnc_of_regval (Regval___InstrEnc (v)) = ( Some v )"
-|" InstrEnc_of_regval g__604 = ( None )"
+|" InstrEnc_of_regval g__280 = ( None )"
 
 
 (*val regval_of___InstrEnc : __InstrEnc -> register_value*)
@@ -983,7 +983,7 @@ definition regval_of___InstrEnc  :: " InstrEnc \<Rightarrow> register_value "  w
 
 fun bool_of_regval  :: " register_value \<Rightarrow>(bool)option "  where 
      " bool_of_regval (Regval_bool (v)) = ( Some v )"
-|" bool_of_regval g__603 = ( None )"
+|" bool_of_regval g__279 = ( None )"
 
 
 (*val regval_of_bool : bool -> register_value*)
@@ -996,7 +996,7 @@ definition regval_of_bool  :: " bool \<Rightarrow> register_value "  where
 
 fun signal_of_regval  :: " register_value \<Rightarrow>(signal)option "  where 
      " signal_of_regval (Regval_signal (v)) = ( Some v )"
-|" signal_of_regval g__602 = ( None )"
+|" signal_of_regval g__278 = ( None )"
 
 
 (*val regval_of_signal : signal -> register_value*)
@@ -1009,7 +1009,7 @@ definition regval_of_signal  :: " signal \<Rightarrow> register_value "  where
 
 fun vector_128_dec_bit_of_regval  :: " register_value \<Rightarrow>((128)Word.word)option "  where 
      " vector_128_dec_bit_of_regval (Regval_vector_128_dec_bit (v)) = ( Some v )"
-|" vector_128_dec_bit_of_regval g__601 = ( None )"
+|" vector_128_dec_bit_of_regval g__277 = ( None )"
 
 
 (*val regval_of_vector_128_dec_bit : mword ty128 -> register_value*)
@@ -1022,7 +1022,7 @@ definition regval_of_vector_128_dec_bit  :: "(128)Word.word \<Rightarrow> regist
 
 fun vector_1_dec_bit_of_regval  :: " register_value \<Rightarrow>((1)Word.word)option "  where 
      " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )"
-|" vector_1_dec_bit_of_regval g__600 = ( None )"
+|" vector_1_dec_bit_of_regval g__276 = ( None )"
 
 
 (*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*)
@@ -1035,7 +1035,7 @@ definition regval_of_vector_1_dec_bit  :: "(1)Word.word \<Rightarrow> register_v
 
 fun vector_32_dec_bit_of_regval  :: " register_value \<Rightarrow>((32)Word.word)option "  where 
      " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )"
-|" vector_32_dec_bit_of_regval g__599 = ( None )"
+|" vector_32_dec_bit_of_regval g__275 = ( None )"
 
 
 (*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
@@ -1048,7 +1048,7 @@ definition regval_of_vector_32_dec_bit  :: "(32)Word.word \<Rightarrow> register
 
 fun vector_4_dec_bit_of_regval  :: " register_value \<Rightarrow>((4)Word.word)option "  where 
      " vector_4_dec_bit_of_regval (Regval_vector_4_dec_bit (v)) = ( Some v )"
-|" vector_4_dec_bit_of_regval g__598 = ( None )"
+|" vector_4_dec_bit_of_regval g__274 = ( None )"
 
 
 (*val regval_of_vector_4_dec_bit : mword ty4 -> register_value*)
@@ -1061,7 +1061,7 @@ definition regval_of_vector_4_dec_bit  :: "(4)Word.word \<Rightarrow> register_v
 
 fun vector_52_dec_bit_of_regval  :: " register_value \<Rightarrow>((52)Word.word)option "  where 
      " vector_52_dec_bit_of_regval (Regval_vector_52_dec_bit (v)) = ( Some v )"
-|" vector_52_dec_bit_of_regval g__597 = ( None )"
+|" vector_52_dec_bit_of_regval g__273 = ( None )"
 
 
 (*val regval_of_vector_52_dec_bit : mword ty52 -> register_value*)
@@ -1074,7 +1074,7 @@ definition regval_of_vector_52_dec_bit  :: "(52)Word.word \<Rightarrow> register
 
 fun vector_64_dec_bit_of_regval  :: " register_value \<Rightarrow>((64)Word.word)option "  where 
      " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )"
-|" vector_64_dec_bit_of_regval g__596 = ( None )"
+|" vector_64_dec_bit_of_regval g__272 = ( None )"
 
 
 (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
@@ -1116,7 +1116,10 @@ definition regval_of_list  :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a
 (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
 definition option_of_regval  :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option "  where 
      " option_of_regval of_regval1 = ( \<lambda>x .  
-  (case  x of   Regval_option v => map_option of_regval1 v | _ => None ) )"
+  (case  x of
+        Regval_option v => Some (Option.bind v of_regval1)
+    | _ => None
+  ) )"
 
 
 (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
@@ -2506,6 +2509,6 @@ definition register_accessors  :: "(string \<Rightarrow> regstate \<Rightarrow>(
 
 
 
-type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR "
-type_synonym 'a M =" (register_value, 'a, exception) monad "
+type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR "
+type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad "
 end
diff --git a/snapshots/isabelle/cheri/Cheri.thy b/snapshots/isabelle/cheri/Cheri.thy
index eed49a23..af6852b6 100644
--- a/snapshots/isabelle/cheri/Cheri.thy
+++ b/snapshots/isabelle/cheri/Cheri.thy
@@ -5,12 +5,12 @@ theory "Cheri"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_string" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
 	 "Cheri_types" 
 	 "Mips_extras" 
 
@@ -18,12 +18,12 @@ begin
 
 (*Generated by Sail from cheri.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 (*open import Cheri_types*)
 (*open import Mips_extras*)
 
@@ -31,12 +31,6 @@ definition cap_size  :: " int "  where
      " cap_size = ( (( 32 :: int)::ii))"
 
 
-(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*)
-
-definition undefined_option  :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad "  where 
-     " undefined_option typ_a = ( undefined_unit ()  \<then> internal_pick [None,Some typ_a])"
-
-
 
 
 
@@ -49,15 +43,39 @@ definition neq_bool  :: " bool \<Rightarrow> bool \<Rightarrow> bool "  where
      " neq_bool x y = ( \<not> (((x = y))))"
 
 
+(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*)
+
+definition undefined_option  :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad "  where 
+     " undefined_option typ_a = (
+   undefined_unit ()  \<bind> (\<lambda> (u_0 :: unit) . 
+   (let (u_1 :: 'a) = typ_a in
+   internal_pick [Some u_1,None])))"
+
+
+(*val is_none : forall 'a. maybe 'a -> bool*)
+
+fun is_none  :: " 'a option \<Rightarrow> bool "  where 
+     " is_none (Some (_)) = ( False )"
+|" is_none None = ( True )"
+
 
+(*val is_some : forall 'a. maybe 'a -> bool*)
 
+fun is_some  :: " 'a option \<Rightarrow> bool "  where 
+     " is_some (Some (_)) = ( True )"
+|" is_some None = ( False )"
 
 
-(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
+(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*)
+
+definition sail_mask  :: "('len::len)itself \<Rightarrow>('v::len)Word.word \<Rightarrow>('len::len)Word.word "  where 
+     " sail_mask len v = (
+   (let len = (size_itself_int len) in
+   if ((len \<le> ((int (size v))))) then (vector_truncate v len  :: ( 'len::len)Word.word)
+   else (zero_extend v len  :: ( 'len::len)Word.word)))"
 
 
 
-(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
 
 
 
@@ -65,29 +83,25 @@ definition neq_bool  :: " bool \<Rightarrow> bool \<Rightarrow> bool "  where
 
 fun cast_unit_vec0  :: " bitU \<Rightarrow>(1)Word.word "  where 
      " cast_unit_vec0 B0 = ( (vec_of_bits [B0]  ::  1 Word.word))"
-|" cast_unit_vec0 B1 = ( (vec_of_bits [B1]  ::  1 Word.word))"
-
+|" cast_unit_vec0 _ = ( (vec_of_bits [B1]  ::  1 Word.word))"
 
-(*val DecStr : ii -> string*)
-
-(*val HexStr : ii -> string*)
 
 (*val __MIPS_write : forall  'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*)
 
 definition MIPS_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " MIPS_write addr width data = (
-   write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width
+   write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width
      (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
        ::  64 Word.word) addr data )"
 
 
-(*val __MIPS_read : forall  'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
+(*val __MIPS_read : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
 
 definition MIPS_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad "  where 
      " MIPS_read addr width = (
-   (read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width
+   (read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width
       (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
@@ -101,27 +115,22 @@ definition MIPS_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((registe
 
 definition undefined_exception  :: " unit \<Rightarrow>((register_value),(exception),(exception))monad "  where 
      " undefined_exception _ = (
-   (undefined_unit ()  \<then>
-   undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . 
-   ((undefined_unit ()  \<then>
-   undefined_unit () ) \<then>
-   undefined_unit () ) \<then>
+   undefined_string ()  \<bind> (\<lambda> (u_0 :: string) . 
+   undefined_unit ()  \<bind> (\<lambda> (u_1 :: unit) . 
    internal_pick
-     [ISAException () ,Error_not_implemented w__0,Error_misaligned_access () ,Error_EBREAK () ,Error_internal_error () ]))"
+     [ISAException u_1,Error_not_implemented u_0,Error_misaligned_access u_1,Error_EBREAK u_1,Error_internal_error u_1])))"
 
 
-(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
 
-(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
 
-definition sign_extend1  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
-     " sign_extend1 (m__tv :: int) v = ( (sign_extend0 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv  :: ( 'm::len)Word.word))"
+definition mips_sign_extend  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
+     " mips_sign_extend (m__tv :: int) v = ( (sign_extend v m__tv  :: ( 'm::len)Word.word))"
 
 
-definition zero_extend1  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
-     " zero_extend1 (m__tv :: int) v = ( (zero_extend0 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv  :: ( 'm::len)Word.word))"
+definition mips_zero_extend  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
+     " mips_zero_extend (m__tv :: int) v = ( (zero_extend v m__tv  :: ( 'm::len)Word.word))"
 
 
 (*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*)
@@ -136,13 +145,13 @@ definition ones  :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word "
      " ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1]  ::  1 Word.word) n__tv  :: ( 'n::len)Word.word))"
 
 
-(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
-(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
-(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
-(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
 
 definition zopz0zI_s  :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool "  where 
      " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))"
@@ -170,7 +179,7 @@ definition bool_to_bits  :: " bool \<Rightarrow>(1)Word.word "  where
 
 fun bit_to_bool  :: " bitU \<Rightarrow> bool "  where 
      " bit_to_bool B1 = ( True )"
-|" bit_to_bool B0 = ( False )"
+|" bit_to_bool _ = ( False )"
 
 
 (*val bits_to_bool : mword ty1 -> bool*)
@@ -182,12 +191,12 @@ definition bits_to_bool  :: "(1)Word.word \<Rightarrow> bool "  where
 (*
 function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits.
 *)
-(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*)
+(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*)
 
 definition to_bits  :: "('l::len)itself \<Rightarrow> int \<Rightarrow>('l::len)Word.word "  where 
      " to_bits l n = (
    (let l = (size_itself_int l) in
-   (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii)  :: ( 'l::len)Word.word)))"
+   (get_slice_int0 instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii)  :: ( 'l::len)Word.word)))"
 
 
 (*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*)
@@ -197,333 +206,245 @@ definition mask0  :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('n::len
    (subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii)  :: ( 'n::len)Word.word))"
 
 
-(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
-
-definition extzv  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
-     " extzv (m__tv :: int) v = ( (extz_vec m__tv v  :: ( 'm::len)Word.word))"
-
-
-(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
-
-definition extsv  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
-     " extsv (m__tv :: int) v = ( (exts_vec m__tv v  :: ( 'm::len)Word.word))"
-
-
-(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*)
-
-definition slice_mask  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
-     " slice_mask (n__tv :: int) i l = (
-   (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1]  ::  1 Word.word)  :: ( 'n::len)Word.word)) in
-   (shiftl ((sub_vec ((shiftl one l  :: ( 'n::len)Word.word)) one  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)))"
-
-
-(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
-
-definition is_zero_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
-     " is_zero_subrange xs i j = (
-   (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0]  ::  1 Word.word)  :: ( 'n::len)Word.word))))"
-
-
-(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
-
-definition is_ones_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
-     " is_ones_subrange xs i j = (
-   (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i))  :: ( 'n::len)Word.word)) in
-   (((and_vec xs m  :: ( 'n::len)Word.word)) = m)))"
-
-
-(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*)
-
-definition slice_slice_concat  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word "  where 
-     " slice_slice_concat (r__tv :: int) xs i l ys i' l' = (
-   (let xs =
-     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
-   (let ys =
-     ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l'  :: ( 'm::len)Word.word))  :: ( 'm::len)Word.word)) i'
-       :: ( 'm::len)Word.word)) in
-   (or_vec ((shiftl ((extzv r__tv xs  :: ( 'r::len)Word.word)) l'  :: ( 'r::len)Word.word)) ((extzv r__tv ys  :: ( 'r::len)Word.word))
-     :: ( 'r::len)Word.word))))"
-
-
-(*val slice_zeros_concat : forall 'n   'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*)
-
-definition slice_zeros_concat  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word "  where 
-     " slice_zeros_concat (r__tv :: int) xs i l l' = (
-   (let xs =
-     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
-   (shiftl ((extzv r__tv xs  :: ( 'r::len)Word.word)) l'  :: ( 'r::len)Word.word)))"
-
-
-(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*)
-
-definition subrange_subrange_eq  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
-     " subrange_subrange_eq xs i j ys i' j' = (
-   (let xs =
-     ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) j
-       :: ( 'n::len)Word.word)) in
-   (let ys =
-     ((shiftr
-        ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j'))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word))
-        j'
-       :: ( 'n::len)Word.word)) in
-   (xs = ys))))"
-
-
-(*val subrange_subrange_concat : forall 'n   'm   's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*)
-
-definition subrange_subrange_concat  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word "  where 
-     " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = (
-   (let xs =
-     ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) j
-       :: ( 'n::len)Word.word)) in
-   (let ys =
-     ((shiftr
-        ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j'))  :: ( 'm::len)Word.word))  :: ( 'm::len)Word.word))
-        j'
-       :: ( 'm::len)Word.word)) in
-   (or_vec
-      ((sub_vec_int ((shiftl ((extzv s__tv xs  :: ( 's::len)Word.word)) i'  :: ( 's::len)Word.word))
-          ((j' - (( 1 :: int)::ii)))
-         :: ( 's::len)Word.word)) ((extzv s__tv ys  :: ( 's::len)Word.word))
-     :: ( 's::len)Word.word))))"
-
-
-(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
-
-definition place_subrange  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
-     " place_subrange (m__tv :: int) xs i j shift = (
-   (let xs =
-     ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) j
-       :: ( 'n::len)Word.word)) in
-   (shiftl ((extzv m__tv xs  :: ( 'm::len)Word.word)) shift  :: ( 'm::len)Word.word)))"
-
-
-(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
-
-definition place_slice  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
-     " place_slice (m__tv :: int) xs i l shift = (
-   (let xs =
-     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
-   (shiftl ((extzv m__tv xs  :: ( 'm::len)Word.word)) shift  :: ( 'm::len)Word.word)))"
-
-
-(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
-
-definition zext_slice  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
-     " zext_slice (m__tv :: int) xs i l = (
-   (let xs =
-     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
-   (extzv m__tv xs  :: ( 'm::len)Word.word)))"
-
-
-(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
-
-definition sext_slice  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
-     " sext_slice (m__tv :: int) xs i l = (
-   (let xs =
-     ((arith_shiftr
-        ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word))
-            ((((((int (size xs))) - i)) - l))
-           :: ( 'n::len)Word.word)) ((((int (size xs))) - l))
-       :: ( 'n::len)Word.word)) in
-   (extsv m__tv xs  :: ( 'm::len)Word.word)))"
-
-
-(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
-
-definition unsigned_slice  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int "  where 
-     " unsigned_slice xs i l = (
-   (let xs =
-     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
-   Word.uint xs))"
-
+(*val undefined_CauseReg : unit -> M CauseReg*)
 
-(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+definition undefined_CauseReg  :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad "  where 
+     " undefined_CauseReg _ = (
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 ::  32 Word.word) . 
+   return ((| CauseReg_CauseReg_chunk_0 = w__0 |))))"
 
-definition unsigned_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int "  where 
-     " unsigned_subrange xs i j = (
-   (let xs =
-     ((shiftr
-        ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j))  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i
-       :: ( 'n::len)Word.word)) in
-   Word.uint xs))"
 
+(*val Mk_CauseReg : mword ty32 -> CauseReg*)
 
-(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*)
+definition Mk_CauseReg  :: "(32)Word.word \<Rightarrow> CauseReg "  where 
+     " Mk_CauseReg v = (
+   (| CauseReg_CauseReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) |) )"
 
-definition zext_ones  :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
-     " zext_ones (n__tv :: int) m = (
-   (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1]  ::  1 Word.word)  :: ( 'n::len)Word.word)) in
-   (shiftr v ((((int (size v))) - m))  :: ( 'n::len)Word.word)))"
 
+(*val _get_CauseReg_bits : CauseReg -> mword ty32*)
 
-(*val undefined_CauseReg : unit -> M CauseReg*)
+definition get_CauseReg_bits  :: " CauseReg \<Rightarrow>(32)Word.word "  where 
+     " get_CauseReg_bits v = (
+   (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))"
 
-definition undefined_CauseReg  :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad "  where 
-     " undefined_CauseReg _ = (
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 ::  32 Word.word) . 
-   internal_pick [Mk_CauseReg w__0]))"
 
+(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*)
 
-(*val _get_CauseReg : CauseReg -> mword ty32*)
+definition set_CauseReg_bits  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_CauseReg_bits r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
-fun get_CauseReg  :: " CauseReg \<Rightarrow>(32)Word.word "  where 
-     " get_CauseReg (Mk_CauseReg (v)) = ( v )"
 
+(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*)
 
-(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*)
+definition update_CauseReg_bits  :: " CauseReg \<Rightarrow>(32)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_bits v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+          ::  32 Word.word))|)))"
 
-definition set_CauseReg  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_CauseReg r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_CauseReg v) in
-   write_reg r_ref r)))"
 
+(*val _update_CapCauseReg_bits : CapCauseReg -> mword ty16 -> CapCauseReg*)
 
-(*val _get_CapCauseReg : CapCauseReg -> mword ty16*)
+(*val _get_CapCauseReg_bits : CapCauseReg -> mword ty16*)
 
-(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*)
+(*val _set_CapCauseReg_bits : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*)
 
 (*val _get_CauseReg_BD : CauseReg -> mword ty1*)
 
-fun get_CauseReg_BD  :: " CauseReg \<Rightarrow>(1)Word.word "  where 
-     " get_CauseReg_BD (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii)  ::  1 Word.word))"
+definition get_CauseReg_BD  :: " CauseReg \<Rightarrow>(1)Word.word "  where 
+     " get_CauseReg_BD v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 31 :: int)::ii) (( 31 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
 
 definition set_CauseReg_BD  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CauseReg_BD r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . 
-   (let r = ((get_CauseReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_CauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*)
 
-fun update_CauseReg_BD  :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg "  where 
-     " update_CauseReg_BD (Mk_CauseReg (v)) x = (
-   Mk_CauseReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x  ::  32 Word.word)))"
+definition update_CauseReg_BD  :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_BD v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_CauseReg_CE : CauseReg -> mword ty2*)
 
-fun get_CauseReg_CE  :: " CauseReg \<Rightarrow>(2)Word.word "  where 
-     " get_CauseReg_CE (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii)  ::  2 Word.word))"
+definition get_CauseReg_CE  :: " CauseReg \<Rightarrow>(2)Word.word "  where 
+     " get_CauseReg_CE v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 29 :: int)::ii) (( 28 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*)
 
 definition set_CauseReg_CE  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CauseReg_CE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . 
-   (let r = ((get_CauseReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 28 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_CauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 29 :: int)::ii) (( 28 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*)
 
-fun update_CauseReg_CE  :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg "  where 
-     " update_CauseReg_CE (Mk_CauseReg (v)) x = (
-   Mk_CauseReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) x  ::  32 Word.word)))"
+definition update_CauseReg_CE  :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_CE v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 29 :: int)::ii) (( 28 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_CauseReg_IV : CauseReg -> mword ty1*)
 
-fun get_CauseReg_IV  :: " CauseReg \<Rightarrow>(1)Word.word "  where 
-     " get_CauseReg_IV (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii)  ::  1 Word.word))"
+definition get_CauseReg_IV  :: " CauseReg \<Rightarrow>(1)Word.word "  where 
+     " get_CauseReg_IV v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 23 :: int)::ii) (( 23 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
 
 definition set_CauseReg_IV  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CauseReg_IV r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . 
-   (let r = ((get_CauseReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_CauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 23 :: int)::ii) (( 23 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*)
 
-fun update_CauseReg_IV  :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg "  where 
-     " update_CauseReg_IV (Mk_CauseReg (v)) x = (
-   Mk_CauseReg ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x  ::  32 Word.word)))"
+definition update_CauseReg_IV  :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_IV v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 23 :: int)::ii) (( 23 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_CauseReg_WP : CauseReg -> mword ty1*)
 
-fun get_CauseReg_WP  :: " CauseReg \<Rightarrow>(1)Word.word "  where 
-     " get_CauseReg_WP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
+definition get_CauseReg_WP  :: " CauseReg \<Rightarrow>(1)Word.word "  where 
+     " get_CauseReg_WP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
 
 definition set_CauseReg_WP  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CauseReg_WP r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . 
-   (let r = ((get_CauseReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_CauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*)
 
-fun update_CauseReg_WP  :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg "  where 
-     " update_CauseReg_WP (Mk_CauseReg (v)) x = (
-   Mk_CauseReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x  ::  32 Word.word)))"
+definition update_CauseReg_WP  :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_WP v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_CauseReg_IP : CauseReg -> mword ty8*)
 
-fun get_CauseReg_IP  :: " CauseReg \<Rightarrow>(8)Word.word "  where 
-     " get_CauseReg_IP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))"
+definition get_CauseReg_IP  :: " CauseReg \<Rightarrow>(8)Word.word "  where 
+     " get_CauseReg_IP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))"
 
 
 (*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*)
 
 definition set_CauseReg_IP  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CauseReg_IP r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . 
-   (let r = ((get_CauseReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_CauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 15 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*)
 
-fun update_CauseReg_IP  :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg "  where 
-     " update_CauseReg_IP (Mk_CauseReg (v)) x = (
-   Mk_CauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x  ::  32 Word.word)))"
+definition update_CauseReg_IP  :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_IP v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 15 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*)
 
-fun get_CauseReg_ExcCode  :: " CauseReg \<Rightarrow>(5)Word.word "  where 
-     " get_CauseReg_ExcCode (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word))"
+definition get_CauseReg_ExcCode  :: " CauseReg \<Rightarrow>(5)Word.word "  where 
+     " get_CauseReg_ExcCode v = (
+   (subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word))"
 
 
 (*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*)
 
 definition set_CauseReg_ExcCode  :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CauseReg_ExcCode r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . 
-   (let r = ((get_CauseReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 2 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_CauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CauseReg_CauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   r) (( 6 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*)
 
-fun update_CauseReg_ExcCode  :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg "  where 
-     " update_CauseReg_ExcCode (Mk_CauseReg (v)) x = (
-   Mk_CauseReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) x  ::  32 Word.word)))"
+definition update_CauseReg_ExcCode  :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg "  where 
+     " update_CauseReg_ExcCode v x = (
+   (v (|
+     CauseReg_CauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0   v) (( 6 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*)
@@ -537,187 +458,271 @@ fun update_CauseReg_ExcCode  :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarro
 definition undefined_TLBEntryLoReg  :: " unit \<Rightarrow>((register_value),(TLBEntryLoReg),(exception))monad "  where 
      " undefined_TLBEntryLoReg _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   internal_pick [Mk_TLBEntryLoReg w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   return ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = w__0 |))))"
+
 
+(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*)
 
-(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*)
+definition Mk_TLBEntryLoReg  :: "(64)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " Mk_TLBEntryLoReg v = (
+   (| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-fun get_TLBEntryLoReg  :: " TLBEntryLoReg \<Rightarrow>(64)Word.word "  where 
-     " get_TLBEntryLoReg (Mk_TLBEntryLoReg (v)) = ( v )"
 
+(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*)
 
-(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*)
+definition get_TLBEntryLoReg_bits  :: " TLBEntryLoReg \<Rightarrow>(64)Word.word "  where 
+     " get_TLBEntryLoReg_bits v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-definition set_TLBEntryLoReg  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_TLBEntryLoReg r_ref v = (
+
+(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*)
+
+definition set_TLBEntryLoReg_bits  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_TLBEntryLoReg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_TLBEntryLoReg v) in
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*)
+
+definition update_TLBEntryLoReg_bits  :: " TLBEntryLoReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_bits v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*)
 
-fun get_TLBEntryLoReg_CapS  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) = (
-   (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntryLoReg_CapS  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntryLoReg_CapS v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 definition set_TLBEntryLoReg_CapS  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_CapS r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_CapS  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_CapS  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_CapS v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*)
 
-fun get_TLBEntryLoReg_CapL  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) = (
-   (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntryLoReg_CapL  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntryLoReg_CapL v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 62 :: int)::ii) (( 62 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 definition set_TLBEntryLoReg_CapL  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_CapL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 62 :: int)::ii) (( 62 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_CapL  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_CapL  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_CapL v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 62 :: int)::ii) (( 62 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*)
 
-fun get_TLBEntryLoReg_PFN  :: " TLBEntryLoReg \<Rightarrow>(24)Word.word "  where 
-     " get_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) = (
-   (subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii)  ::  24 Word.word))"
+definition get_TLBEntryLoReg_PFN  :: " TLBEntryLoReg \<Rightarrow>(24)Word.word "  where 
+     " get_TLBEntryLoReg_PFN v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 29 :: int)::ii) (( 6 :: int)::ii)  ::  24 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*)
 
 definition set_TLBEntryLoReg_PFN  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_PFN r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 6 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 29 :: int)::ii) (( 6 :: int)::ii)
+             ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_PFN  :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_PFN  :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_PFN v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 29 :: int)::ii) (( 6 :: int)::ii)
+           ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*)
 
-fun get_TLBEntryLoReg_C  :: " TLBEntryLoReg \<Rightarrow>(3)Word.word "  where 
-     " get_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word))"
+definition get_TLBEntryLoReg_C  :: " TLBEntryLoReg \<Rightarrow>(3)Word.word "  where 
+     " get_TLBEntryLoReg_C v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 5 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*)
 
 definition set_TLBEntryLoReg_C  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_C r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 3 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 5 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_C  :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_C  :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_C v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 5 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*)
 
-fun get_TLBEntryLoReg_D  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntryLoReg_D  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntryLoReg_D v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 definition set_TLBEntryLoReg_D  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_D r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_D  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_D  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_D v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*)
 
-fun get_TLBEntryLoReg_V  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntryLoReg_V  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntryLoReg_V v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 definition set_TLBEntryLoReg_V  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_V r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_V  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_V  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_V v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*)
 
-fun get_TLBEntryLoReg_G  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntryLoReg_G  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntryLoReg_G v = (
+   (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
 
 definition set_TLBEntryLoReg_G  :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryLoReg_G r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . 
-   (let r = ((get_TLBEntryLoReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryLoReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
 
-fun update_TLBEntryLoReg_G  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
-     " update_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) x = (
-   Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryLoReg_G  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg "  where 
+     " update_TLBEntryLoReg_G v x = (
+   (v (|
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*)
@@ -725,93 +730,143 @@ fun update_TLBEntryLoReg_G  :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Right
 definition undefined_TLBEntryHiReg  :: " unit \<Rightarrow>((register_value),(TLBEntryHiReg),(exception))monad "  where 
      " undefined_TLBEntryHiReg _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   internal_pick [Mk_TLBEntryHiReg w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   return ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = w__0 |))))"
+
 
+(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*)
 
-(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*)
+definition Mk_TLBEntryHiReg  :: "(64)Word.word \<Rightarrow> TLBEntryHiReg "  where 
+     " Mk_TLBEntryHiReg v = (
+   (| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-fun get_TLBEntryHiReg  :: " TLBEntryHiReg \<Rightarrow>(64)Word.word "  where 
-     " get_TLBEntryHiReg (Mk_TLBEntryHiReg (v)) = ( v )"
 
+(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*)
 
-(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*)
+definition get_TLBEntryHiReg_bits  :: " TLBEntryHiReg \<Rightarrow>(64)Word.word "  where 
+     " get_TLBEntryHiReg_bits v = (
+   (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-definition set_TLBEntryHiReg  :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_TLBEntryHiReg r_ref v = (
+
+(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*)
+
+definition set_TLBEntryHiReg_bits  :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_TLBEntryHiReg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_TLBEntryHiReg v) in
+   (let r =
+     ((r (|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*)
+
+definition update_TLBEntryHiReg_bits  :: " TLBEntryHiReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryHiReg "  where 
+     " update_TLBEntryHiReg_bits v x = (
+   (v (|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*)
 
-fun get_TLBEntryHiReg_R  :: " TLBEntryHiReg \<Rightarrow>(2)Word.word "  where 
-     " get_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii)  ::  2 Word.word))"
+definition get_TLBEntryHiReg_R  :: " TLBEntryHiReg \<Rightarrow>(2)Word.word "  where 
+     " get_TLBEntryHiReg_R v = (
+   (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 63 :: int)::ii) (( 62 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*)
 
 definition set_TLBEntryHiReg_R  :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryHiReg_R r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . 
-   (let r = ((get_TLBEntryHiReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryHiReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   r) (( 63 :: int)::ii) (( 62 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*)
 
-fun update_TLBEntryHiReg_R  :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg "  where 
-     " update_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) x = (
-   Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryHiReg_R  :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg "  where 
+     " update_TLBEntryHiReg_R v x = (
+   (v (|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 63 :: int)::ii) (( 62 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*)
 
-fun get_TLBEntryHiReg_VPN2  :: " TLBEntryHiReg \<Rightarrow>(27)Word.word "  where 
-     " get_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) = (
-   (subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii)  ::  27 Word.word))"
+definition get_TLBEntryHiReg_VPN2  :: " TLBEntryHiReg \<Rightarrow>(27)Word.word "  where 
+     " get_TLBEntryHiReg_VPN2 v = (
+   (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 39 :: int)::ii) (( 13 :: int)::ii)  ::  27 Word.word))"
 
 
 (*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*)
 
 definition set_TLBEntryHiReg_VPN2  :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryHiReg_VPN2 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . 
-   (let r = ((get_TLBEntryHiReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 39 :: int)::ii) (( 13 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryHiReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   r) (( 39 :: int)::ii) (( 13 :: int)::ii)
+             ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*)
 
-fun update_TLBEntryHiReg_VPN2  :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg "  where 
-     " update_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) x = (
-   Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryHiReg_VPN2  :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg "  where 
+     " update_TLBEntryHiReg_VPN2 v x = (
+   (v (|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 39 :: int)::ii) (( 13 :: int)::ii)
+           ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*)
 
-fun get_TLBEntryHiReg_ASID  :: " TLBEntryHiReg \<Rightarrow>(8)Word.word "  where 
-     " get_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
+definition get_TLBEntryHiReg_ASID  :: " TLBEntryHiReg \<Rightarrow>(8)Word.word "  where 
+     " get_TLBEntryHiReg_ASID v = (
+   (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
 
 
 (*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*)
 
 definition set_TLBEntryHiReg_ASID  :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntryHiReg_ASID r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . 
-   (let r = ((get_TLBEntryHiReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_TLBEntryHiReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*)
 
-fun update_TLBEntryHiReg_ASID  :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg "  where 
-     " update_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) x = (
-   Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_TLBEntryHiReg_ASID  :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg "  where 
+     " update_TLBEntryHiReg_ASID v x = (
+   (v (|
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val undefined_ContextReg : unit -> M ContextReg*)
@@ -819,69 +874,111 @@ fun update_TLBEntryHiReg_ASID  :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Ri
 definition undefined_ContextReg  :: " unit \<Rightarrow>((register_value),(ContextReg),(exception))monad "  where 
      " undefined_ContextReg _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   internal_pick [Mk_ContextReg w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   return ((| ContextReg_ContextReg_chunk_0 = w__0 |))))"
+
 
+(*val Mk_ContextReg : mword ty64 -> ContextReg*)
 
-(*val _get_ContextReg : ContextReg -> mword ty64*)
+definition Mk_ContextReg  :: "(64)Word.word \<Rightarrow> ContextReg "  where 
+     " Mk_ContextReg v = (
+   (| ContextReg_ContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-fun get_ContextReg  :: " ContextReg \<Rightarrow>(64)Word.word "  where 
-     " get_ContextReg (Mk_ContextReg (v)) = ( v )"
 
+(*val _get_ContextReg_bits : ContextReg -> mword ty64*)
 
-(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*)
+definition get_ContextReg_bits  :: " ContextReg \<Rightarrow>(64)Word.word "  where 
+     " get_ContextReg_bits v = (
+   (subrange_vec_dec(ContextReg_ContextReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-definition set_ContextReg  :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_ContextReg r_ref v = (
+
+(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*)
+
+definition set_ContextReg_bits  :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_ContextReg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_ContextReg v) in
+   (let r =
+     ((r (|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*)
+
+definition update_ContextReg_bits  :: " ContextReg \<Rightarrow>(64)Word.word \<Rightarrow> ContextReg "  where 
+     " update_ContextReg_bits v x = (
+   (v (|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*)
 
-fun get_ContextReg_PTEBase  :: " ContextReg \<Rightarrow>(41)Word.word "  where 
-     " get_ContextReg_PTEBase (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii)  ::  41 Word.word))"
+definition get_ContextReg_PTEBase  :: " ContextReg \<Rightarrow>(41)Word.word "  where 
+     " get_ContextReg_PTEBase v = (
+   (subrange_vec_dec(ContextReg_ContextReg_chunk_0   v) (( 63 :: int)::ii) (( 23 :: int)::ii)  ::  41 Word.word))"
 
 
 (*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*)
 
 definition set_ContextReg_PTEBase  :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(41)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_ContextReg_PTEBase r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . 
-   (let r = ((get_ContextReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 23 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_ContextReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0   r) (( 63 :: int)::ii) (( 23 :: int)::ii)
+             ((subrange_vec_dec v (( 40 :: int)::ii) (( 0 :: int)::ii)  ::  41 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*)
 
-fun update_ContextReg_PTEBase  :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg "  where 
-     " update_ContextReg_PTEBase (Mk_ContextReg (v)) x = (
-   Mk_ContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) x  ::  64 Word.word)))"
+definition update_ContextReg_PTEBase  :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg "  where 
+     " update_ContextReg_PTEBase v x = (
+   (v (|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0   v) (( 63 :: int)::ii) (( 23 :: int)::ii)
+           ((subrange_vec_dec x (( 40 :: int)::ii) (( 0 :: int)::ii)  ::  41 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*)
 
-fun get_ContextReg_BadVPN2  :: " ContextReg \<Rightarrow>(19)Word.word "  where 
-     " get_ContextReg_BadVPN2 (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii)  ::  19 Word.word))"
+definition get_ContextReg_BadVPN2  :: " ContextReg \<Rightarrow>(19)Word.word "  where 
+     " get_ContextReg_BadVPN2 v = (
+   (subrange_vec_dec(ContextReg_ContextReg_chunk_0   v) (( 22 :: int)::ii) (( 4 :: int)::ii)  ::  19 Word.word))"
 
 
 (*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*)
 
 definition set_ContextReg_BadVPN2  :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(19)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_ContextReg_BadVPN2 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . 
-   (let r = ((get_ContextReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_ContextReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       ContextReg_ContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0   r) (( 22 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 18 :: int)::ii) (( 0 :: int)::ii)  ::  19 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*)
 
-fun update_ContextReg_BadVPN2  :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg "  where 
-     " update_ContextReg_BadVPN2 (Mk_ContextReg (v)) x = (
-   Mk_ContextReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_ContextReg_BadVPN2  :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg "  where 
+     " update_ContextReg_BadVPN2 v x = (
+   (v (|
+     ContextReg_ContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0   v) (( 22 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 18 :: int)::ii) (( 0 :: int)::ii)  ::  19 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val undefined_XContextReg : unit -> M XContextReg*)
@@ -889,94 +986,143 @@ fun update_ContextReg_BadVPN2  :: " ContextReg \<Rightarrow>(19)Word.word \<Righ
 definition undefined_XContextReg  :: " unit \<Rightarrow>((register_value),(XContextReg),(exception))monad "  where 
      " undefined_XContextReg _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   internal_pick [Mk_XContextReg w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   return ((| XContextReg_XContextReg_chunk_0 = w__0 |))))"
+
+
+(*val Mk_XContextReg : mword ty64 -> XContextReg*)
+
+definition Mk_XContextReg  :: "(64)Word.word \<Rightarrow> XContextReg "  where 
+     " Mk_XContextReg v = (
+   (| XContextReg_XContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
 
-(*val _get_XContextReg : XContextReg -> mword ty64*)
+(*val _get_XContextReg_bits : XContextReg -> mword ty64*)
 
-fun get_XContextReg  :: " XContextReg \<Rightarrow>(64)Word.word "  where 
-     " get_XContextReg (Mk_XContextReg (v)) = ( v )"
+definition get_XContextReg_bits  :: " XContextReg \<Rightarrow>(64)Word.word "  where 
+     " get_XContextReg_bits v = (
+   (subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*)
+(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*)
 
-definition set_XContextReg  :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_XContextReg r_ref v = (
+definition set_XContextReg_bits  :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_XContextReg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_XContextReg v) in
+   (let r =
+     ((r (|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*)
+
+definition update_XContextReg_bits  :: " XContextReg \<Rightarrow>(64)Word.word \<Rightarrow> XContextReg "  where 
+     " update_XContextReg_bits v x = (
+   (v (|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*)
 
-fun get_XContextReg_XPTEBase  :: " XContextReg \<Rightarrow>(31)Word.word "  where 
-     " get_XContextReg_XPTEBase (Mk_XContextReg (v)) = (
-   (subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii)  ::  31 Word.word))"
+definition get_XContextReg_XPTEBase  :: " XContextReg \<Rightarrow>(31)Word.word "  where 
+     " get_XContextReg_XPTEBase v = (
+   (subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 63 :: int)::ii) (( 33 :: int)::ii)  ::  31 Word.word))"
 
 
 (*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*)
 
 definition set_XContextReg_XPTEBase  :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(31)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_XContextReg_XPTEBase r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . 
-   (let r = ((get_XContextReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 33 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_XContextReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   r) (( 63 :: int)::ii) (( 33 :: int)::ii)
+             ((subrange_vec_dec v (( 30 :: int)::ii) (( 0 :: int)::ii)  ::  31 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*)
 
-fun update_XContextReg_XPTEBase  :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg "  where 
-     " update_XContextReg_XPTEBase (Mk_XContextReg (v)) x = (
-   Mk_XContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) x  ::  64 Word.word)))"
+definition update_XContextReg_XPTEBase  :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg "  where 
+     " update_XContextReg_XPTEBase v x = (
+   (v (|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 63 :: int)::ii) (( 33 :: int)::ii)
+           ((subrange_vec_dec x (( 30 :: int)::ii) (( 0 :: int)::ii)  ::  31 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_XContextReg_XR : XContextReg -> mword ty2*)
 
-fun get_XContextReg_XR  :: " XContextReg \<Rightarrow>(2)Word.word "  where 
-     " get_XContextReg_XR (Mk_XContextReg (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii)  ::  2 Word.word))"
+definition get_XContextReg_XR  :: " XContextReg \<Rightarrow>(2)Word.word "  where 
+     " get_XContextReg_XR v = (
+   (subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 32 :: int)::ii) (( 31 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*)
 
 definition set_XContextReg_XR  :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_XContextReg_XR r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . 
-   (let r = ((get_XContextReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 31 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_XContextReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   r) (( 32 :: int)::ii) (( 31 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*)
 
-fun update_XContextReg_XR  :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg "  where 
-     " update_XContextReg_XR (Mk_XContextReg (v)) x = (
-   Mk_XContextReg ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) x  ::  64 Word.word)))"
+definition update_XContextReg_XR  :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg "  where 
+     " update_XContextReg_XR v x = (
+   (v (|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 32 :: int)::ii) (( 31 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*)
 
-fun get_XContextReg_XBadVPN2  :: " XContextReg \<Rightarrow>(27)Word.word "  where 
-     " get_XContextReg_XBadVPN2 (Mk_XContextReg (v)) = (
-   (subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii)  ::  27 Word.word))"
+definition get_XContextReg_XBadVPN2  :: " XContextReg \<Rightarrow>(27)Word.word "  where 
+     " get_XContextReg_XBadVPN2 v = (
+   (subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 30 :: int)::ii) (( 4 :: int)::ii)  ::  27 Word.word))"
 
 
 (*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*)
 
 definition set_XContextReg_XBadVPN2  :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_XContextReg_XBadVPN2 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . 
-   (let r = ((get_XContextReg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_XContextReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       XContextReg_XContextReg_chunk_0 :=
+         ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   r) (( 30 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*)
 
-fun update_XContextReg_XBadVPN2  :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg "  where 
-     " update_XContextReg_XBadVPN2 (Mk_XContextReg (v)) x = (
-   Mk_XContextReg ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_XContextReg_XBadVPN2  :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg "  where 
+     " update_XContextReg_XBadVPN2 v x = (
+   (v (|
+     XContextReg_XContextReg_chunk_0 :=
+       ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0   v) (( 30 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+          ::  64 Word.word))|)))"
 
 
 definition TLBNumEntries  :: " int "  where 
@@ -1010,437 +1156,632 @@ definition MAX_PA  :: " int "  where
 definition undefined_TLBEntry  :: " unit \<Rightarrow>((register_value),(TLBEntry),(exception))monad "  where 
      " undefined_TLBEntry _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 :: int)::ii)  :: ( 117 Word.word) M) \<bind> (\<lambda> (w__0 ::  117 Word.word) . 
-   internal_pick [Mk_TLBEntry w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 :: int)::ii)  :: ( 53 Word.word) M) \<bind> (\<lambda> (w__0 ::  53 Word.word) . 
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
+   return ((| TLBEntry_TLBEntry_chunk_1 = w__0, 
+              TLBEntry_TLBEntry_chunk_0 = w__1 |)))))"
+
+
+(*val Mk_TLBEntry : mword ty117 -> TLBEntry*)
 
+definition Mk_TLBEntry  :: "(117)Word.word \<Rightarrow> TLBEntry "  where 
+     " Mk_TLBEntry v = (
+   (| TLBEntry_TLBEntry_chunk_1 = ((subrange_vec_dec v (( 116 :: int)::ii) (( 64 :: int)::ii)  ::  53 Word.word)), 
+      TLBEntry_TLBEntry_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-(*val _get_TLBEntry : TLBEntry -> mword ty117*)
 
-fun get_TLBEntry  :: " TLBEntry \<Rightarrow>(117)Word.word "  where 
-     " get_TLBEntry (Mk_TLBEntry (v)) = ( v )"
+(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*)
 
+definition get_TLBEntry_bits  :: " TLBEntry \<Rightarrow>(117)Word.word "  where 
+     " get_TLBEntry_bits v = (
+   (concat_vec ((subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 52 :: int)::ii) (( 0 :: int)::ii)  ::  53 Word.word))
+      ((subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+     ::  117 Word.word))"
 
-(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*)
 
-definition set_TLBEntry  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_TLBEntry r_ref v = (
+(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*)
+
+definition set_TLBEntry_bits  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_TLBEntry_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_TLBEntry v) in
-   write_reg r_ref r)))"
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   r) (( 52 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 116 :: int)::ii) (( 64 :: int)::ii)  ::  53 Word.word))
+            ::  53 Word.word))|))) in
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r))))"
+
+
+(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*)
+
+definition update_TLBEntry_bits  :: " TLBEntry \<Rightarrow>(117)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_bits v x = (
+   (let v =
+     ((v (|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 52 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec x (( 116 :: int)::ii) (( 64 :: int)::ii)  ::  53 Word.word))
+            ::  53 Word.word))|))) in
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|))))"
 
 
 (*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*)
 
-fun get_TLBEntry_pagemask  :: " TLBEntry \<Rightarrow>(16)Word.word "  where 
-     " get_TLBEntry_pagemask (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii)  ::  16 Word.word))"
+definition get_TLBEntry_pagemask  :: " TLBEntry \<Rightarrow>(16)Word.word "  where 
+     " get_TLBEntry_pagemask v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 52 :: int)::ii) (( 37 :: int)::ii)  ::  16 Word.word))"
 
 
 (*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*)
 
 definition set_TLBEntry_pagemask  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_pagemask r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 116 :: int)::ii) (( 101 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   r) (( 52 :: int)::ii) (( 37 :: int)::ii)
+             ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+            ::  53 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*)
 
-fun update_TLBEntry_pagemask  :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_pagemask (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_pagemask  :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_pagemask v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 52 :: int)::ii) (( 37 :: int)::ii)
+           ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+          ::  53 Word.word))|)))"
 
 
 (*val _get_TLBEntry_r : TLBEntry -> mword ty2*)
 
-fun get_TLBEntry_r  :: " TLBEntry \<Rightarrow>(2)Word.word "  where 
-     " get_TLBEntry_r (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii)  ::  2 Word.word))"
+definition get_TLBEntry_r  :: " TLBEntry \<Rightarrow>(2)Word.word "  where 
+     " get_TLBEntry_r v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 36 :: int)::ii) (( 35 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*)
 
 definition set_TLBEntry_r  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_r r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 100 :: int)::ii) (( 99 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   r) (( 36 :: int)::ii) (( 35 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  53 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*)
 
-fun update_TLBEntry_r  :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_r (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_r  :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_r v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 36 :: int)::ii) (( 35 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  53 Word.word))|)))"
 
 
 (*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*)
 
-fun get_TLBEntry_vpn2  :: " TLBEntry \<Rightarrow>(27)Word.word "  where 
-     " get_TLBEntry_vpn2 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii)  ::  27 Word.word))"
+definition get_TLBEntry_vpn2  :: " TLBEntry \<Rightarrow>(27)Word.word "  where 
+     " get_TLBEntry_vpn2 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 34 :: int)::ii) (( 8 :: int)::ii)  ::  27 Word.word))"
 
 
 (*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*)
 
 definition set_TLBEntry_vpn2  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_vpn2 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 98 :: int)::ii) (( 72 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   r) (( 34 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+            ::  53 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*)
 
-fun update_TLBEntry_vpn2  :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_vpn2 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_vpn2  :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_vpn2 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 34 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+          ::  53 Word.word))|)))"
 
 
 (*val _get_TLBEntry_asid : TLBEntry -> mword ty8*)
 
-fun get_TLBEntry_asid  :: " TLBEntry \<Rightarrow>(8)Word.word "  where 
-     " get_TLBEntry_asid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii)  ::  8 Word.word))"
+definition get_TLBEntry_asid  :: " TLBEntry \<Rightarrow>(8)Word.word "  where 
+     " get_TLBEntry_asid v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
 
 
 (*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*)
 
 definition set_TLBEntry_asid  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_asid r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 71 :: int)::ii) (( 64 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_1 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  53 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*)
 
-fun update_TLBEntry_asid  :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_asid (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_asid  :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_asid v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_1 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1   v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  53 Word.word))|)))"
 
 
 (*val _get_TLBEntry_g : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_g  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_g (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_g  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_g v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_g  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_g r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_g  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_g (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_g  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_g v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_valid : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_valid  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_valid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_valid  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_valid v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 62 :: int)::ii) (( 62 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_valid  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_valid r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 62 :: int)::ii) (( 62 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_valid  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_valid (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_valid  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_valid v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 62 :: int)::ii) (( 62 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_caps1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_caps1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_caps1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_caps1 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 61 :: int)::ii) (( 61 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_caps1  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_caps1 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 61 :: int)::ii) (( 61 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 61 :: int)::ii) (( 61 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_caps1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_caps1 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_caps1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_caps1 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 61 :: int)::ii) (( 61 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_capl1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_capl1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_capl1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_capl1 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 60 :: int)::ii) (( 60 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_capl1  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_capl1 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 60 :: int)::ii) (( 60 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 60 :: int)::ii) (( 60 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_capl1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_capl1 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_capl1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_capl1 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 60 :: int)::ii) (( 60 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*)
 
-fun get_TLBEntry_pfn1  :: " TLBEntry \<Rightarrow>(24)Word.word "  where 
-     " get_TLBEntry_pfn1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii)  ::  24 Word.word))"
+definition get_TLBEntry_pfn1  :: " TLBEntry \<Rightarrow>(24)Word.word "  where 
+     " get_TLBEntry_pfn1 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 59 :: int)::ii) (( 36 :: int)::ii)  ::  24 Word.word))"
 
 
 (*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*)
 
 definition set_TLBEntry_pfn1  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_pfn1 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 36 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 59 :: int)::ii) (( 36 :: int)::ii)
+             ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*)
 
-fun update_TLBEntry_pfn1  :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_pfn1 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_pfn1  :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_pfn1 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 59 :: int)::ii) (( 36 :: int)::ii)
+           ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*)
 
-fun get_TLBEntry_c1  :: " TLBEntry \<Rightarrow>(3)Word.word "  where 
-     " get_TLBEntry_c1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii)  ::  3 Word.word))"
+definition get_TLBEntry_c1  :: " TLBEntry \<Rightarrow>(3)Word.word "  where 
+     " get_TLBEntry_c1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 35 :: int)::ii) (( 33 :: int)::ii)  ::  3 Word.word))"
 
 
 (*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*)
 
 definition set_TLBEntry_c1  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_c1 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 33 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 35 :: int)::ii) (( 33 :: int)::ii)
+             ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*)
 
-fun update_TLBEntry_c1  :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_c1 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_c1  :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_c1 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 35 :: int)::ii) (( 33 :: int)::ii)
+           ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_d1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_d1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_d1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_d1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 32 :: int)::ii) (( 32 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_d1  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_d1 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 32 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 32 :: int)::ii) (( 32 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_d1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_d1 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_d1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_d1 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 32 :: int)::ii) (( 32 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_v1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_v1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_v1  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_v1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 31 :: int)::ii) (( 31 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_v1  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_v1 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_v1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_v1 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_v1  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_v1 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_caps0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_caps0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_caps0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_caps0 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 30 :: int)::ii) (( 30 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_caps0  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_caps0 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 30 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 30 :: int)::ii) (( 30 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_caps0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_caps0 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_caps0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_caps0 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 30 :: int)::ii) (( 30 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_capl0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_capl0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_capl0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_capl0 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 29 :: int)::ii) (( 29 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_capl0  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_capl0 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 29 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 29 :: int)::ii) (( 29 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_capl0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_capl0 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_capl0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_capl0 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 29 :: int)::ii) (( 29 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*)
 
-fun get_TLBEntry_pfn0  :: " TLBEntry \<Rightarrow>(24)Word.word "  where 
-     " get_TLBEntry_pfn0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii)  ::  24 Word.word))"
+definition get_TLBEntry_pfn0  :: " TLBEntry \<Rightarrow>(24)Word.word "  where 
+     " get_TLBEntry_pfn0 v = (
+   (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 28 :: int)::ii) (( 5 :: int)::ii)  ::  24 Word.word))"
 
 
 (*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*)
 
 definition set_TLBEntry_pfn0  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_pfn0 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 28 :: int)::ii) (( 5 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 28 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*)
 
-fun update_TLBEntry_pfn0  :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_pfn0 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_pfn0  :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_pfn0 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 28 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*)
 
-fun get_TLBEntry_c0  :: " TLBEntry \<Rightarrow>(3)Word.word "  where 
-     " get_TLBEntry_c0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word))"
+definition get_TLBEntry_c0  :: " TLBEntry \<Rightarrow>(3)Word.word "  where 
+     " get_TLBEntry_c0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word))"
 
 
 (*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*)
 
 definition set_TLBEntry_c0  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_c0 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 2 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 4 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*)
 
-fun update_TLBEntry_c0  :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_c0 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_c0  :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_c0 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 4 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_d0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_d0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_d0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_d0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_d0  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_d0 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_d0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_d0 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_d0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_d0 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*)
 
-fun get_TLBEntry_v0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
-     " get_TLBEntry_v0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_TLBEntry_v0  :: " TLBEntry \<Rightarrow>(1)Word.word "  where 
+     " get_TLBEntry_v0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*)
 
 definition set_TLBEntry_v0  :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_TLBEntry_v0 r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . 
-   (let r = ((get_TLBEntry w__0  ::  117 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  117 Word.word)) in
-   write_reg r_ref (Mk_TLBEntry r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       TLBEntry_TLBEntry_chunk_0 :=
+         ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*)
 
-fun update_TLBEntry_v0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
-     " update_TLBEntry_v0 (Mk_TLBEntry (v)) x = (
-   Mk_TLBEntry ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  117 Word.word)))"
+definition update_TLBEntry_v0  :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry "  where 
+     " update_TLBEntry_v0 v x = (
+   (v (|
+     TLBEntry_TLBEntry_chunk_0 :=
+       ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 definition TLBEntries  :: "(((regstate),(register_value),(TLBEntry))register_ref)list "  where 
@@ -1463,253 +1804,367 @@ definition TLBEntries  :: "(((regstate),(register_value),(TLBEntry))register_ref
 definition undefined_StatusReg  :: " unit \<Rightarrow>((register_value),(StatusReg),(exception))monad "  where 
      " undefined_StatusReg _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 ::  32 Word.word) . 
-   internal_pick [Mk_StatusReg w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 ::  32 Word.word) . 
+   return ((| StatusReg_StatusReg_chunk_0 = w__0 |))))"
+
+
+(*val Mk_StatusReg : mword ty32 -> StatusReg*)
 
+definition Mk_StatusReg  :: "(32)Word.word \<Rightarrow> StatusReg "  where 
+     " Mk_StatusReg v = (
+   (| StatusReg_StatusReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) |) )"
 
-(*val _get_StatusReg : StatusReg -> mword ty32*)
 
-fun get_StatusReg  :: " StatusReg \<Rightarrow>(32)Word.word "  where 
-     " get_StatusReg (Mk_StatusReg (v)) = ( v )"
+(*val _get_StatusReg_bits : StatusReg -> mword ty32*)
 
+definition get_StatusReg_bits  :: " StatusReg \<Rightarrow>(32)Word.word "  where 
+     " get_StatusReg_bits v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))"
 
-(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*)
 
-definition set_StatusReg  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_StatusReg r_ref v = (
+(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*)
+
+definition set_StatusReg_bits  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_StatusReg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_StatusReg v) in
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+            ::  32 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*)
+
+definition update_StatusReg_bits  :: " StatusReg \<Rightarrow>(32)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_bits v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+          ::  32 Word.word))|)))"
+
+
 (*val _get_StatusReg_CU : StatusReg -> mword ty4*)
 
-fun get_StatusReg_CU  :: " StatusReg \<Rightarrow>(4)Word.word "  where 
-     " get_StatusReg_CU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii)  ::  4 Word.word))"
+definition get_StatusReg_CU  :: " StatusReg \<Rightarrow>(4)Word.word "  where 
+     " get_StatusReg_CU v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 31 :: int)::ii) (( 28 :: int)::ii)  ::  4 Word.word))"
 
 
 (*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*)
 
 definition set_StatusReg_CU  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_CU r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 28 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 31 :: int)::ii) (( 28 :: int)::ii)
+             ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii)  ::  4 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*)
 
-fun update_StatusReg_CU  :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_CU (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_CU  :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_CU v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 31 :: int)::ii) (( 28 :: int)::ii)
+           ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii)  ::  4 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_BEV : StatusReg -> mword ty1*)
 
-fun get_StatusReg_BEV  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_BEV (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_BEV  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_BEV v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_BEV  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_BEV r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_BEV  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_BEV (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_BEV  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_BEV v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_IM : StatusReg -> mword ty8*)
 
-fun get_StatusReg_IM  :: " StatusReg \<Rightarrow>(8)Word.word "  where 
-     " get_StatusReg_IM (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))"
+definition get_StatusReg_IM  :: " StatusReg \<Rightarrow>(8)Word.word "  where 
+     " get_StatusReg_IM v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))"
 
 
 (*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*)
 
 definition set_StatusReg_IM  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_IM r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 15 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*)
 
-fun update_StatusReg_IM  :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_IM (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_IM  :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_IM v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 15 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_KX : StatusReg -> mword ty1*)
 
-fun get_StatusReg_KX  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_KX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_KX  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_KX v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_KX  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_KX r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_KX  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_KX (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_KX  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_KX v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_SX : StatusReg -> mword ty1*)
 
-fun get_StatusReg_SX  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_SX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_SX  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_SX v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_SX  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_SX r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_SX  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_SX (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_SX  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_SX v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_UX : StatusReg -> mword ty1*)
 
-fun get_StatusReg_UX  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_UX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_UX  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_UX v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_UX  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_UX r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_UX  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_UX (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_UX  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_UX v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_KSU : StatusReg -> mword ty2*)
 
-fun get_StatusReg_KSU  :: " StatusReg \<Rightarrow>(2)Word.word "  where 
-     " get_StatusReg_KSU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word))"
+definition get_StatusReg_KSU  :: " StatusReg \<Rightarrow>(2)Word.word "  where 
+     " get_StatusReg_KSU v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*)
 
 definition set_StatusReg_KSU  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_KSU r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 3 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 4 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*)
 
-fun update_StatusReg_KSU  :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_KSU (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_KSU  :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_KSU v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 4 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_ERL : StatusReg -> mword ty1*)
 
-fun get_StatusReg_ERL  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_ERL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_ERL  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_ERL v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_ERL  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_ERL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_ERL  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_ERL (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_ERL  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_ERL v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_EXL : StatusReg -> mword ty1*)
 
-fun get_StatusReg_EXL  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_EXL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_EXL  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_EXL v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_EXL  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_EXL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_EXL  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_EXL (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_EXL  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_EXL v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val _get_StatusReg_IE : StatusReg -> mword ty1*)
 
-fun get_StatusReg_IE  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
-     " get_StatusReg_IE (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_StatusReg_IE  :: " StatusReg \<Rightarrow>(1)Word.word "  where 
+     " get_StatusReg_IE v = (
+   (subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*)
 
 definition set_StatusReg_IE  :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_StatusReg_IE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let r = ((get_StatusReg w__0  ::  32 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  32 Word.word)) in
-   write_reg r_ref (Mk_StatusReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       StatusReg_StatusReg_chunk_0 :=
+         ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*)
 
-fun update_StatusReg_IE  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
-     " update_StatusReg_IE (Mk_StatusReg (v)) x = (
-   Mk_StatusReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  32 Word.word)))"
+definition update_StatusReg_IE  :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg "  where 
+     " update_StatusReg_IE v x = (
+   (v (|
+     StatusReg_StatusReg_chunk_0 :=
+       ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
 
 
 (*val execute_branch : mword ty64 -> M unit*)
@@ -1747,10 +2202,10 @@ definition rGPR  :: "(5)Word.word \<Rightarrow>((register_value),((64)Word.word)
 definition wGPR  :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " wGPR idx v = (
    (let i = (Word.uint idx) in
-   if (((i = (( 0 :: int)::ii)))) then return () 
-   else
+   if (((i \<noteq> (( 0 :: int)::ii)))) then
      read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . 
-     write_reg GPR_ref ((update_list_dec w__0 i v  :: ( 64 Word.word) list)))))"
+     write_reg GPR_ref ((update_list_dec w__0 i v  :: ( 64 Word.word) list)))
+   else return () ))"
 
 
 
@@ -1771,25 +2226,25 @@ definition wGPR  :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((regi
 
 definition Exception_of_num  :: " int \<Rightarrow> Exception "  where 
      " Exception_of_num arg0 = (
-   (let l__81 = arg0 in
-   if (((l__81 = (( 0 :: int)::ii)))) then Interrupt
-   else if (((l__81 = (( 1 :: int)::ii)))) then TLBMod
-   else if (((l__81 = (( 2 :: int)::ii)))) then TLBL
-   else if (((l__81 = (( 3 :: int)::ii)))) then TLBS
-   else if (((l__81 = (( 4 :: int)::ii)))) then AdEL
-   else if (((l__81 = (( 5 :: int)::ii)))) then AdES
-   else if (((l__81 = (( 6 :: int)::ii)))) then Sys
-   else if (((l__81 = (( 7 :: int)::ii)))) then Bp
-   else if (((l__81 = (( 8 :: int)::ii)))) then ResI
-   else if (((l__81 = (( 9 :: int)::ii)))) then CpU
-   else if (((l__81 = (( 10 :: int)::ii)))) then Ov
-   else if (((l__81 = (( 11 :: int)::ii)))) then Tr
-   else if (((l__81 = (( 12 :: int)::ii)))) then C2E
-   else if (((l__81 = (( 13 :: int)::ii)))) then C2Trap
-   else if (((l__81 = (( 14 :: int)::ii)))) then XTLBRefillL
-   else if (((l__81 = (( 15 :: int)::ii)))) then XTLBRefillS
-   else if (((l__81 = (( 16 :: int)::ii)))) then XTLBInvL
-   else if (((l__81 = (( 17 :: int)::ii)))) then XTLBInvS
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Interrupt
+   else if (((p00 = (( 1 :: int)::ii)))) then TLBMod
+   else if (((p00 = (( 2 :: int)::ii)))) then TLBL
+   else if (((p00 = (( 3 :: int)::ii)))) then TLBS
+   else if (((p00 = (( 4 :: int)::ii)))) then AdEL
+   else if (((p00 = (( 5 :: int)::ii)))) then AdES
+   else if (((p00 = (( 6 :: int)::ii)))) then Sys
+   else if (((p00 = (( 7 :: int)::ii)))) then Bp
+   else if (((p00 = (( 8 :: int)::ii)))) then ResI
+   else if (((p00 = (( 9 :: int)::ii)))) then CpU
+   else if (((p00 = (( 10 :: int)::ii)))) then Ov
+   else if (((p00 = (( 11 :: int)::ii)))) then Tr
+   else if (((p00 = (( 12 :: int)::ii)))) then C2E
+   else if (((p00 = (( 13 :: int)::ii)))) then C2Trap
+   else if (((p00 = (( 14 :: int)::ii)))) then XTLBRefillL
+   else if (((p00 = (( 15 :: int)::ii)))) then XTLBRefillS
+   else if (((p00 = (( 16 :: int)::ii)))) then XTLBInvL
+   else if (((p00 = (( 17 :: int)::ii)))) then XTLBInvS
    else MCheck))"
 
 
@@ -1892,7 +2347,7 @@ definition SignalExceptionMIPS  :: " Exception \<Rightarrow>(64)Word.word \<Righ
    ((write_reg
      nextPC_ref
      ((sub_vec
-         ((add_vec vectorBase ((sign_extend1 (( 64 :: int)::ii) vectorOffset  ::  64 Word.word))  ::  64 Word.word))
+         ((add_vec vectorBase ((mips_sign_extend (( 64 :: int)::ii) vectorOffset  ::  64 Word.word))  ::  64 Word.word))
          kccBase
         ::  64 Word.word)) \<then>
    set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex  ::  5 Word.word))) \<then>
@@ -2051,10 +2506,10 @@ definition SignalException  :: " Exception \<Rightarrow>((register_value),'o,(ex
       (read_reg PCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 ::  257 Word.word) . 
       (let pcc = (capRegToCapStruct w__1) in
       (let (success, epcc) = (setCapOffset pcc pc) in
-      if success then write_reg C31_ref ((capStructToCapReg epcc  ::  257 Word.word))
+      if success then write_reg EPCC_ref ((capStructToCapReg epcc  ::  257 Word.word))
       else
         write_reg
-          C31_ref
+          EPCC_ref
           ((capStructToCapReg
               ((int_to_cap
                   ((add_vec_int
@@ -2063,11 +2518,11 @@ definition SignalException  :: " Exception \<Rightarrow>((register_value),'o,(ex
                      ::  64 Word.word))))
              ::  257 Word.word))))))
     else return () ) \<then>
-   (read_reg C29_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . 
+   (read_reg KCC_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . 
    (write_reg nextPCC_ref w__2 \<then>
-   (read_reg C29_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . 
+   (read_reg KCC_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . 
    (write_reg delayedPCC_ref w__3 \<then>
-   (read_reg C29_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 ::  257 Word.word) . 
+   (read_reg KCC_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 ::  257 Word.word) . 
    (let base = (getCapBase ((capRegToCapStruct w__4))) in
    SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) base  ::  64 Word.word))))))))"
 
@@ -2094,9 +2549,9 @@ definition SignalExceptionTLB  :: " Exception \<Rightarrow>(64)Word.word \<Right
 
 definition MemAccessType_of_num  :: " int \<Rightarrow> MemAccessType "  where 
      " MemAccessType_of_num arg0 = (
-   (let l__79 = arg0 in
-   if (((l__79 = (( 0 :: int)::ii)))) then Instruction
-   else if (((l__79 = (( 1 :: int)::ii)))) then LoadData
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Instruction
+   else if (((p00 = (( 1 :: int)::ii)))) then LoadData
    else StoreData))"
 
 
@@ -2118,9 +2573,9 @@ definition undefined_MemAccessType  :: " unit \<Rightarrow>((register_value),(Me
 
 definition AccessLevel_of_num  :: " int \<Rightarrow> AccessLevel "  where 
      " AccessLevel_of_num arg0 = (
-   (let l__77 = arg0 in
-   if (((l__77 = (( 0 :: int)::ii)))) then User
-   else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then User
+   else if (((p00 = (( 1 :: int)::ii)))) then Supervisor
    else Kernel))"
 
 
@@ -2171,8 +2626,8 @@ definition getAccessLevel  :: " unit \<Rightarrow>((register_value),(AccessLevel
    if w__2 then return Kernel
    else
      read_reg CP0Status_ref \<bind> (\<lambda> (w__3 :: StatusReg) . 
-     (let p__133 = ((get_StatusReg_KSU w__3  ::  2 Word.word)) in
-     (let b__0 = p__133 in
+     (let p__31 = ((get_StatusReg_KSU w__3  ::  2 Word.word)) in
+     (let b__0 = p__31 in
      return (if (((b__0 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then Kernel
              else if (((b__0 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then Supervisor
              else if (((b__0 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then User
@@ -2234,10 +2689,10 @@ definition incrementCP0Count  :: " unit \<Rightarrow>((register_value),(unit),(e
 
 definition decode_failure_of_num  :: " int \<Rightarrow> decode_failure "  where 
      " decode_failure_of_num arg0 = (
-   (let l__74 = arg0 in
-   if (((l__74 = (( 0 :: int)::ii)))) then No_matching_pattern
-   else if (((l__74 = (( 1 :: int)::ii)))) then Unsupported_instruction
-   else if (((l__74 = (( 2 :: int)::ii)))) then Illegal_instruction
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then No_matching_pattern
+   else if (((p00 = (( 1 :: int)::ii)))) then Unsupported_instruction
+   else if (((p00 = (( 2 :: int)::ii)))) then Illegal_instruction
    else Internal_error))"
 
 
@@ -2258,14 +2713,14 @@ definition undefined_decode_failure  :: " unit \<Rightarrow>((register_value),(d
 
 definition Comparison_of_num  :: " int \<Rightarrow> Comparison "  where 
      " Comparison_of_num arg0 = (
-   (let l__67 = arg0 in
-   if (((l__67 = (( 0 :: int)::ii)))) then EQ'
-   else if (((l__67 = (( 1 :: int)::ii)))) then NE
-   else if (((l__67 = (( 2 :: int)::ii)))) then GE
-   else if (((l__67 = (( 3 :: int)::ii)))) then GEU
-   else if (((l__67 = (( 4 :: int)::ii)))) then GT'
-   else if (((l__67 = (( 5 :: int)::ii)))) then LE
-   else if (((l__67 = (( 6 :: int)::ii)))) then LT'
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then EQ'
+   else if (((p00 = (( 1 :: int)::ii)))) then NE
+   else if (((p00 = (( 2 :: int)::ii)))) then GE
+   else if (((p00 = (( 3 :: int)::ii)))) then GEU
+   else if (((p00 = (( 4 :: int)::ii)))) then GT'
+   else if (((p00 = (( 5 :: int)::ii)))) then LE
+   else if (((p00 = (( 6 :: int)::ii)))) then LT'
    else LTU))"
 
 
@@ -2305,10 +2760,10 @@ fun compare  :: " Comparison \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.wo
 
 definition WordType_of_num  :: " int \<Rightarrow> WordType "  where 
      " WordType_of_num arg0 = (
-   (let l__64 = arg0 in
-   if (((l__64 = (( 0 :: int)::ii)))) then B
-   else if (((l__64 = (( 1 :: int)::ii)))) then H
-   else if (((l__64 = (( 2 :: int)::ii)))) then W
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then B
+   else if (((p00 = (( 1 :: int)::ii)))) then H
+   else if (((p00 = (( 2 :: int)::ii)))) then W
    else D))"
 
 
@@ -2327,6 +2782,32 @@ definition undefined_WordType  :: " unit \<Rightarrow>((register_value),(WordTyp
      " undefined_WordType _ = ( internal_pick [B,H,W,D])"
 
 
+(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*)
+
+definition WordTypeUnaligned_of_num  :: " int \<Rightarrow> WordTypeUnaligned "  where 
+     " WordTypeUnaligned_of_num arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then WL
+   else if (((p00 = (( 1 :: int)::ii)))) then WR
+   else if (((p00 = (( 2 :: int)::ii)))) then DL
+   else DR))"
+
+
+(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*)
+
+fun num_of_WordTypeUnaligned  :: " WordTypeUnaligned \<Rightarrow> int "  where 
+     " num_of_WordTypeUnaligned WL = ( (( 0 :: int)::ii))"
+|" num_of_WordTypeUnaligned WR = ( (( 1 :: int)::ii))"
+|" num_of_WordTypeUnaligned DL = ( (( 2 :: int)::ii))"
+|" num_of_WordTypeUnaligned DR = ( (( 3 :: int)::ii))"
+
+
+(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*)
+
+definition undefined_WordTypeUnaligned  :: " unit \<Rightarrow>((register_value),(WordTypeUnaligned),(exception))monad "  where 
+     " undefined_WordTypeUnaligned _ = ( internal_pick [WL,WR,DL,DR])"
+
+
 (*val wordWidthBytes : WordType -> integer*)
 
 fun wordWidthBytes  :: " WordType \<Rightarrow> int "  where 
@@ -2349,19 +2830,52 @@ definition isAddressAligned  :: "(64)Word.word \<Rightarrow> WordType \<Rightarr
          alignment_width)))))"
 
 
-(*val MEMr_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
+(*val MEMr_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*)
 
-definition MEMr_wrapper  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad "  where 
-     " MEMr_wrapper addr size1 = (
-   (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1  :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . 
-   return ((reverse_endianness w__0  :: ( 'p8_times_n_::len)Word.word))))"
+definition MEMr_wrapper  :: " int \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad "  where 
+     " MEMr_wrapper (p8_times_n___tv :: int) addr size1 = (
+   if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                        B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                        B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+            ::  64 Word.word)))) then
+     (read_reg UART_RVALID_ref  :: ( 1 Word.word) M) \<bind> (\<lambda> rvalid . 
+     (write_reg UART_RVALID_ref (vec_of_bits [B0]  ::  1 Word.word) \<then>
+     (read_reg UART_RDATA_ref  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__0 :: 8 bits) . 
+     return ((mask0 p8_times_n___tv
+                ((concat_vec
+                    (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                      ::  32 Word.word)
+                    ((concat_vec w__0
+                        ((concat_vec rvalid
+                            ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+                                (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                                  ::  16 Word.word)
+                               ::  23 Word.word))
+                           ::  24 Word.word))
+                       ::  32 Word.word))
+                   ::  64 Word.word))
+               :: ( 'p8_times_n_::len)Word.word))))
+   else if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                             B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,
+                             B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0]
+                 ::  64 Word.word)))) then
+     return ((mask0 p8_times_n___tv
+                (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                              B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
+                              B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1]
+                  ::  64 Word.word)
+               :: ( 'p8_times_n_::len)Word.word))
+   else
+     (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1  :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__1 . 
+     return ((reverse_endianness w__1  :: ( 'p8_times_n_::len)Word.word))))"
 
 
 (*val MEMr_reserve_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
 
 definition MEMr_reserve_wrapper  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad "  where 
      " MEMr_reserve_wrapper addr size1 = (
-   (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1  :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . 
+   (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1  :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . 
    return ((reverse_endianness w__0  :: ( 'p8_times_n_::len)Word.word))))"
 
 
@@ -2377,6 +2891,181 @@ definition init_cp0_state  :: " unit \<Rightarrow>((register_value),(unit),(exce
 
 (*val dump_cp2_state : unit -> M unit*)
 
+(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+definition extzv  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
+     " extzv (m__tv :: int) v = ( (extz_vec m__tv v  :: ( 'm::len)Word.word))"
+
+
+(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+definition extsv  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
+     " extsv (m__tv :: int) v = ( (exts_vec m__tv v  :: ( 'm::len)Word.word))"
+
+
+(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*)
+
+definition slice_mask  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
+     " slice_mask (n__tv :: int) i l = (
+   (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1]  ::  1 Word.word)  :: ( 'n::len)Word.word)) in
+   (shiftl ((sub_vec ((shiftl one l  :: ( 'n::len)Word.word)) one  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)))"
+
+
+(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
+
+definition is_zero_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
+     " is_zero_subrange xs i j = (
+   (((and_vec xs
+         ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+        :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0]  ::  1 Word.word)  :: ( 'n::len)Word.word))))"
+
+
+(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
+
+definition is_ones_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
+     " is_ones_subrange xs i j = (
+   (let (m :: 'n bits) =
+     ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word)) in
+   (((and_vec xs m  :: ( 'n::len)Word.word)) = m)))"
+
+
+(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*)
+
+definition slice_slice_concat  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word "  where 
+     " slice_slice_concat (r__tv :: int) xs i l ys i' l' = (
+   (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
+   (let ys =
+     ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l'  :: ( 'm::len)Word.word))  :: ( 'm::len)Word.word)) i'
+       :: ( 'm::len)Word.word)) in
+   (or_vec ((shiftl ((extzv r__tv xs  :: ( 'r::len)Word.word)) l'  :: ( 'r::len)Word.word)) ((extzv r__tv ys  :: ( 'r::len)Word.word))
+     :: ( 'r::len)Word.word))))"
+
+
+(*val slice_zeros_concat : forall 'n   'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*)
+
+definition slice_zeros_concat  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word "  where 
+     " slice_zeros_concat (r__tv :: int) xs i l l' = (
+   (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
+   (shiftl ((extzv r__tv xs  :: ( 'r::len)Word.word)) l'  :: ( 'r::len)Word.word)))"
+
+
+(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*)
+
+definition subrange_subrange_eq  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
+     " subrange_subrange_eq xs i j ys i' j' = (
+   (let xs =
+     ((shiftr
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j
+       :: ( 'n::len)Word.word)) in
+   (let ys =
+     ((shiftr
+        ((and_vec ys
+            ((slice_mask ((int (size xs))) j' ((((i' - j')) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j'
+       :: ( 'n::len)Word.word)) in
+   (xs = ys))))"
+
+
+(*val subrange_subrange_concat : forall 'n   'm   's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*)
+
+definition subrange_subrange_concat  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word "  where 
+     " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = (
+   (let xs =
+     ((shiftr
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j
+       :: ( 'n::len)Word.word)) in
+   (let ys =
+     ((shiftr
+        ((and_vec ys
+            ((slice_mask ((int (size ys))) j' ((((i' - j')) + (( 1 :: int)::ii)))  :: ( 'm::len)Word.word))
+           :: ( 'm::len)Word.word)) j'
+       :: ( 'm::len)Word.word)) in
+   (or_vec
+      ((shiftl ((extzv s__tv xs  :: ( 's::len)Word.word)) ((((i' - j')) + (( 1 :: int)::ii)))
+         :: ( 's::len)Word.word)) ((extzv s__tv ys  :: ( 's::len)Word.word))
+     :: ( 's::len)Word.word))))"
+
+
+(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
+
+definition place_subrange  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
+     " place_subrange (m__tv :: int) xs i j shift = (
+   (let xs =
+     ((shiftr
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) j
+       :: ( 'n::len)Word.word)) in
+   (shiftl ((extzv m__tv xs  :: ( 'm::len)Word.word)) shift  :: ( 'm::len)Word.word)))"
+
+
+(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*)
+
+definition place_slice  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
+     " place_slice (m__tv :: int) xs i l shift = (
+   (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
+   (shiftl ((extzv m__tv xs  :: ( 'm::len)Word.word)) shift  :: ( 'm::len)Word.word)))"
+
+
+(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
+
+definition zext_slice  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
+     " zext_slice (m__tv :: int) xs i l = (
+   (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
+   (extzv m__tv xs  :: ( 'm::len)Word.word)))"
+
+
+(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*)
+
+definition sext_slice  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word "  where 
+     " sext_slice (m__tv :: int) xs i l = (
+   (let xs =
+     ((arith_shiftr
+        ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word))
+            ((((((int (size xs))) - i)) - l))
+           :: ( 'n::len)Word.word)) ((((int (size xs))) - l))
+       :: ( 'n::len)Word.word)) in
+   (extsv m__tv xs  :: ( 'm::len)Word.word)))"
+
+
+(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+
+definition unsigned_slice  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int "  where 
+     " unsigned_slice xs i l = (
+   (let xs =
+     ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l  :: ( 'n::len)Word.word))  :: ( 'n::len)Word.word)) i  :: ( 'n::len)Word.word)) in
+   Word.uint xs))"
+
+
+(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*)
+
+definition unsigned_subrange  :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int "  where 
+     " unsigned_subrange xs i j = (
+   (let xs =
+     ((shiftr
+        ((and_vec xs
+            ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii)))  :: ( 'n::len)Word.word))
+           :: ( 'n::len)Word.word)) i
+       :: ( 'n::len)Word.word)) in
+   Word.uint xs))"
+
+
+(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*)
+
+definition zext_ones  :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
+     " zext_ones (n__tv :: int) m = (
+   (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1]  ::  1 Word.word)  :: ( 'n::len)Word.word)) in
+   (shiftr v ((((int (size v))) - m))  :: ( 'n::len)Word.word)))"
+
+
 (*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*)
 
 definition tlbEntryMatch  :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry \<Rightarrow> bool "  where 
@@ -2388,7 +3077,7 @@ definition tlbEntryMatch  :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarr
    (let entryASID = ((get_TLBEntry_asid entry  ::  8 Word.word)) in
    (let entryG = ((get_TLBEntry_g entry  ::  1 Word.word)) in
    (let (vpnMask :: 27 bits) =
-     ((not_vec ((zero_extend1 (( 27 :: int)::ii) entryMask  ::  27 Word.word))  ::  27 Word.word)) in
+     ((not_vec ((mips_zero_extend (( 27 :: int)::ii) entryMask  ::  27 Word.word))  ::  27 Word.word)) in
    (((bits_to_bool entryValid)) \<and> ((((((r = entryR))) \<and> ((((((((and_vec vpn2 vpnMask  ::  27 Word.word)) = ((and_vec entryVPN vpnMask  ::  27 Word.word))))) \<and> ((((((asid = entryASID))) \<or> ((bits_to_bool entryG))))))))))))))))))))"
 
 
@@ -2470,7 +3159,7 @@ definition TLBTranslate2  :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta
         (SignalExceptionTLB TLBMod vAddr  :: (( 64 Word.word * bool)) M)
       else
         (let (res :: 64 bits) =
-          ((zero_extend1 (( 64 :: int)::ii)
+          ((mips_zero_extend (( 64 :: int)::ii)
              ((subrange_subrange_concat
                  (((((((( 23 :: int)::ii) -
                              ((((evenOddBit - (( 12 :: int)::ii))) - (( 1 :: int)::ii)))))
@@ -2514,7 +3203,7 @@ definition TLBTranslateC  :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta
                           ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii)  ::  29 Word.word))
                          ::  32 Word.word))
                      ::  64 Word.word)))
-          else
+          else if (((b__1 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then
             (Kernel,
              Some ((concat_vec
                       (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -2524,7 +3213,8 @@ definition TLBTranslateC  :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta
                           ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii)  ::  29 Word.word))
                          ::  32 Word.word))
                      ::  64 Word.word)))
-       | (g__131, g__132) => (Kernel, None)
+          else (case  (True, b__1) of   (g__29, g__30) => (Kernel, None) )
+       | (g__29, g__30) => (Kernel, None)
        )
      else if (((b__0 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then
        (Kernel,
@@ -2563,14 +3253,14 @@ definition TLBTranslate  :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightar
 
 definition CPtrCmpOp_of_num  :: " int \<Rightarrow> CPtrCmpOp "  where 
      " CPtrCmpOp_of_num arg0 = (
-   (let l__57 = arg0 in
-   if (((l__57 = (( 0 :: int)::ii)))) then CEQ
-   else if (((l__57 = (( 1 :: int)::ii)))) then CNE
-   else if (((l__57 = (( 2 :: int)::ii)))) then CLT
-   else if (((l__57 = (( 3 :: int)::ii)))) then CLE
-   else if (((l__57 = (( 4 :: int)::ii)))) then CLTU
-   else if (((l__57 = (( 5 :: int)::ii)))) then CLEU
-   else if (((l__57 = (( 6 :: int)::ii)))) then CEXEQ
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CEQ
+   else if (((p00 = (( 1 :: int)::ii)))) then CNE
+   else if (((p00 = (( 2 :: int)::ii)))) then CLT
+   else if (((p00 = (( 3 :: int)::ii)))) then CLE
+   else if (((p00 = (( 4 :: int)::ii)))) then CLTU
+   else if (((p00 = (( 5 :: int)::ii)))) then CLEU
+   else if (((p00 = (( 6 :: int)::ii)))) then CEXEQ
    else CNEXEQ))"
 
 
@@ -2597,10 +3287,10 @@ definition undefined_CPtrCmpOp  :: " unit \<Rightarrow>((register_value),(CPtrCm
 
 definition ClearRegSet_of_num  :: " int \<Rightarrow> ClearRegSet "  where 
      " ClearRegSet_of_num arg0 = (
-   (let l__54 = arg0 in
-   if (((l__54 = (( 0 :: int)::ii)))) then GPLo
-   else if (((l__54 = (( 1 :: int)::ii)))) then GPHi
-   else if (((l__54 = (( 2 :: int)::ii)))) then CLo
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then GPLo
+   else if (((p00 = (( 1 :: int)::ii)))) then GPHi
+   else if (((p00 = (( 2 :: int)::ii)))) then CLo
    else CHi))"
 
 
@@ -2625,13 +3315,13 @@ definition undefined_CapStruct  :: " unit \<Rightarrow>((register_value),(CapStr
      " undefined_CapStruct _ = (
    undefined_bool ()  \<bind> (\<lambda> (w__0 :: bool) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii)  :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii)  :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii)  :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . 
    undefined_bool ()  \<bind> (\<lambda> (w__5 :: bool) . 
    undefined_bool ()  \<bind> (\<lambda> (w__6 :: bool) . 
    undefined_bool ()  \<bind> (\<lambda> (w__7 :: bool) . 
@@ -2645,11 +3335,11 @@ definition undefined_CapStruct  :: " unit \<Rightarrow>((register_value),(CapStr
    undefined_bool ()  \<bind> (\<lambda> (w__15 :: bool) . 
    undefined_bool ()  \<bind> (\<lambda> (w__16 :: bool) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . 
    return ((| CapStruct_tag = w__0, 
               CapStruct_padding = w__1, 
               CapStruct_otype = w__2, 
@@ -2678,7 +3368,7 @@ definition default_cap  :: " CapStruct "  where
      CapStruct_padding = ((zeros0 (( 8 :: int)::ii) ()   ::  8 Word.word)), 
      CapStruct_otype = ((zeros0 (( 24 :: int)::ii) ()   ::  24 Word.word)), 
      CapStruct_uperms = ((ones (( 16 :: int)::ii) ()   ::  16 Word.word)), 
-     CapStruct_perm_reserved11_14 = ((ones (( 4 :: int)::ii) ()   ::  4 Word.word)), 
+     CapStruct_perm_reserved11_14 = ((zeros0 (( 4 :: int)::ii) ()   ::  4 Word.word)), 
      CapStruct_access_system_regs = True, 
      CapStruct_permit_unseal = True, 
      CapStruct_permit_ccall = True, 
@@ -2721,818 +3411,149 @@ definition memBitsToCapBits  :: " bool \<Rightarrow>(256)Word.word \<Rightarrow>
 
 (*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*)
 
-definition setCapPerms  :: " CapStruct \<Rightarrow>(31)Word.word \<Rightarrow> CapStruct "  where 
-     " setCapPerms cap perms = (
-   (cap (|
-     CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii)  ::  16 Word.word)), CapStruct_perm_reserved11_14 :=
-       ((subrange_vec_dec perms (( 14 :: int)::ii) (( 11 :: int)::ii)  ::  4 Word.word)), CapStruct_access_system_regs :=
-       ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal :=
-       ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall :=
-       ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal :=
-       ((bit_to_bool ((access_vec_dec perms (( 7 :: int)::ii))))), CapStruct_permit_store_local_cap :=
-       ((bit_to_bool ((access_vec_dec perms (( 6 :: int)::ii))))), CapStruct_permit_store_cap :=
-       ((bit_to_bool ((access_vec_dec perms (( 5 :: int)::ii))))), CapStruct_permit_load_cap :=
-       ((bit_to_bool ((access_vec_dec perms (( 4 :: int)::ii))))), CapStruct_permit_store :=
-       ((bit_to_bool ((access_vec_dec perms (( 3 :: int)::ii))))), CapStruct_permit_load :=
-       ((bit_to_bool ((access_vec_dec perms (( 2 :: int)::ii))))), CapStruct_permit_execute :=
-       ((bit_to_bool ((access_vec_dec perms (( 1 :: int)::ii))))), CapStruct_global :=
-       ((bit_to_bool ((access_vec_dec perms (( 0 :: int)::ii)))))|)))"
-
-
-(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*)
-
-definition sealCap  :: " CapStruct \<Rightarrow>(24)Word.word \<Rightarrow> bool*CapStruct "  where 
-     " sealCap cap otype = ( (True, (cap (| CapStruct_sealed := True, CapStruct_otype := otype |))))"
-
-
-(*val getCapTop : CapStruct -> integer*)
-
-definition getCapTop  :: " CapStruct \<Rightarrow> int "  where 
-     " getCapTop c = ( ((Word.uint(CapStruct_base   c))) + ((Word.uint(CapStruct_length   c))))"
-
-
-(*val getCapOffset : CapStruct -> integer*)
-
-definition getCapOffset  :: " CapStruct \<Rightarrow> int "  where 
-     " getCapOffset c = (
-   hardware_mod ((((Word.uint(CapStruct_address   c))) - ((Word.uint(CapStruct_base   c)))))
-     ((pow2 (( 64 :: int)::ii))))"
-
-
-(*val getCapLength : CapStruct -> integer*)
-
-definition getCapLength  :: " CapStruct \<Rightarrow> int "  where 
-     " getCapLength c = ( Word.uint(CapStruct_length   c))"
-
-
-(*val getCapCursor : CapStruct -> integer*)
-
-definition getCapCursor  :: " CapStruct \<Rightarrow> int "  where 
-     " getCapCursor c = ( Word.uint(CapStruct_address   c))"
-
-
-(*
-function{incCapOffset} is the same as function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic).
- *)
-(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*)
-
-definition incCapOffset  :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> bool*CapStruct "  where 
-     " incCapOffset c delta = (
-   (let (newAddr :: 64 bits) = ((add_vec(CapStruct_address   c) delta  ::  64 Word.word)) in
-   (True, (c (| CapStruct_address := newAddr |)))))"
-
-
-(*
-Returns a capability derived from the given capability by setting the base and top to values provided.  The offset of the resulting capability is zero.  In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values.
- *)
-(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*)
-
-definition setCapBounds  :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow>(65)Word.word \<Rightarrow> bool*CapStruct "  where 
-     " setCapBounds cap base top1 = (
-   (let (length1 :: 65 bits) =
-     ((sub_vec top1 ((concat_vec (vec_of_bits [B0]  ::  1 Word.word) base  ::  65 Word.word))  ::  65 Word.word)) in
-   (True,
-    (cap (|
-      CapStruct_base := base, CapStruct_length :=
-        ((subrange_vec_dec length1 (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)), CapStruct_address := base |)))))"
-
-
-(*val undefined_ast : unit -> M ast*)
-
-definition undefined_ast  :: " unit \<Rightarrow>((register_value),(ast),(exception))monad "  where 
-     " undefined_ast _ = (
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__0 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__1 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 ::  16 Word.word) . 
-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__18 ::  5 Word.word) . 
-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__261 ::  5 Word.word) . 
-   undefined_CPtrCmpOp ()  \<bind> (\<lambda> (w__262 :: CPtrCmpOp) . 
-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__285 ::  5 Word.word) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__286 :: bool) . 
-   undefined_ClearRegSet ()  \<bind> (\<lambda> (w__287 :: ClearRegSet) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__288 ::  16 Word.word) . 
-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii)  :: ( 11 Word.word) M) \<bind> (\<lambda> (w__316 ::  11 Word.word) . 
-   (undefined_unit ()  \<then>
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__318 ::  16 Word.word) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__319 :: bool) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__320 ::  5 Word.word) . 
-   (undefined_bitvector 
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-   undefined_bool ()  \<bind> (\<lambda> (w__322 :: bool) . 
-   (undefined_bitvector 
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-   (undefined_bitvector 
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-   undefined_bool ()  \<bind> (\<lambda> (w__325 :: bool) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__326 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__327 ::  5 Word.word) . 
-   (undefined_bitvector 
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-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__329 ::  8 Word.word) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__330 :: bool) . 
-   undefined_WordType ()  \<bind> (\<lambda> (w__331 :: WordType) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__332 :: bool) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__333 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__334 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__335 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__336 ::  5 Word.word) . 
-   (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__337 ::  8 Word.word) . 
-   undefined_WordType ()  \<bind> (\<lambda> (w__338 :: WordType) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__339 :: bool) . 
+definition setCapPerms  :: " CapStruct \<Rightarrow>(31)Word.word \<Rightarrow> CapStruct "  where 
+     " setCapPerms cap perms = (
+   (cap (|
+     CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii)  ::  16 Word.word)), CapStruct_access_system_regs :=
+       ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal :=
+       ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall :=
+       ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal :=
+       ((bit_to_bool ((access_vec_dec perms (( 7 :: int)::ii))))), CapStruct_permit_store_local_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 6 :: int)::ii))))), CapStruct_permit_store_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 5 :: int)::ii))))), CapStruct_permit_load_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 4 :: int)::ii))))), CapStruct_permit_store :=
+       ((bit_to_bool ((access_vec_dec perms (( 3 :: int)::ii))))), CapStruct_permit_load :=
+       ((bit_to_bool ((access_vec_dec perms (( 2 :: int)::ii))))), CapStruct_permit_execute :=
+       ((bit_to_bool ((access_vec_dec perms (( 1 :: int)::ii))))), CapStruct_global :=
+       ((bit_to_bool ((access_vec_dec perms (( 0 :: int)::ii)))))|)))"
+
+
+(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*)
+
+definition sealCap  :: " CapStruct \<Rightarrow>(24)Word.word \<Rightarrow> bool*CapStruct "  where 
+     " sealCap cap otype = ( (True, (cap (| CapStruct_sealed := True, CapStruct_otype := otype |))))"
+
+
+(*val getCapTop : CapStruct -> integer*)
+
+definition getCapTop  :: " CapStruct \<Rightarrow> int "  where 
+     " getCapTop c = ( ((Word.uint(CapStruct_base   c))) + ((Word.uint(CapStruct_length   c))))"
+
+
+(*val getCapOffset : CapStruct -> integer*)
+
+definition getCapOffset  :: " CapStruct \<Rightarrow> int "  where 
+     " getCapOffset c = (
+   hardware_mod ((((Word.uint(CapStruct_address   c))) - ((Word.uint(CapStruct_base   c)))))
+     ((pow2 (( 64 :: int)::ii))))"
+
+
+(*val getCapLength : CapStruct -> integer*)
+
+definition getCapLength  :: " CapStruct \<Rightarrow> int "  where 
+     " getCapLength c = ( Word.uint(CapStruct_length   c))"
+
+
+(*val getCapCursor : CapStruct -> integer*)
+
+definition getCapCursor  :: " CapStruct \<Rightarrow> int "  where 
+     " getCapCursor c = ( Word.uint(CapStruct_address   c))"
+
+
+(*
+function{incCapOffset} is the same as function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic).
+ *)
+(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*)
+
+definition incCapOffset  :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> bool*CapStruct "  where 
+     " incCapOffset c delta = (
+   (let (newAddr :: 64 bits) = ((add_vec(CapStruct_address   c) delta  ::  64 Word.word)) in
+   (True, (c (| CapStruct_address := newAddr |)))))"
+
+
+(*
+Returns a capability derived from the given capability by setting the base and top to values provided.  The offset of the resulting capability is zero.  In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values.
+ *)
+(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*)
+
+definition setCapBounds  :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow>(65)Word.word \<Rightarrow> bool*CapStruct "  where 
+     " setCapBounds cap base top1 = (
+   (let (length1 :: 65 bits) =
+     ((sub_vec top1 ((concat_vec (vec_of_bits [B0]  ::  1 Word.word) base  ::  65 Word.word))  ::  65 Word.word)) in
+   (True,
+    (cap (|
+      CapStruct_base := base, CapStruct_length :=
+        ((subrange_vec_dec length1 (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)), CapStruct_address := base |)))))"
+
+
+(*val undefined_ast : unit -> M ast*)
+
+definition undefined_ast  :: " unit \<Rightarrow>((register_value),(ast),(exception))monad "  where 
+     " undefined_ast _ = (
+   undefined_CPtrCmpOp ()  \<bind> (\<lambda> (u_0 :: CPtrCmpOp) . 
+   undefined_ClearRegSet ()  \<bind> (\<lambda> (u_1 :: ClearRegSet) . 
+   undefined_Comparison ()  \<bind> (\<lambda> (u_2 :: Comparison) . 
+   undefined_WordType ()  \<bind> (\<lambda> (u_3 :: WordType) . 
+   undefined_bool ()  \<bind> (\<lambda> (u_5 :: bool) . 
+   undefined_bool ()  \<bind> (\<lambda> (u_4 :: bool) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__340 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (u_6 :: imm16) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__341 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (u_10 :: regno) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__342 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (u_9 :: regno) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__343 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (u_8 :: regno) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii)  :: ( 11 Word.word) M) \<bind> (\<lambda> (w__344 ::  11 Word.word) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__345 :: bool) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (u_7 :: regno) . 
+   undefined_unit ()  \<bind> (\<lambda> (u_11 :: unit) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__346 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii)  :: ( 3 Word.word) M) \<bind> (\<lambda> (u_12 :: 3 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__347 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (u_13 :: 8 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__348 ::  5 Word.word) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii)  :: ( 11 Word.word) M) \<bind> (\<lambda> (u_14 :: 11 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii)  :: ( 11 Word.word) M) \<bind> (\<lambda> (w__349 ::  11 Word.word) . 
-   undefined_bool ()  \<bind> (\<lambda> (w__350 :: bool) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (u_15 :: 16 bits) . 
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii)  :: ( 5 Word.word) M) \<bind> (\<lambda> (w__351 ::  5 Word.word) . 
-   undefined_unit ()  \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii)  :: ( 26 Word.word) M) \<bind> (\<lambda> (u_16 :: 26 bits) . 
    internal_pick
-     [DADDIU (w__0,w__1,w__2),DADDU (w__3,w__4,w__5),DADDI (w__6,w__7,w__8),DADD (w__9,w__10,w__11),ADD (w__12,w__13,w__14),ADDI (w__15,w__16,w__17),ADDU (w__18,w__19,w__20),ADDIU (w__21,w__22,w__23),DSUBU (w__24,w__25,w__26),DSUB (w__27,w__28,w__29),SUB (w__30,w__31,w__32),SUBU (w__33,w__34,w__35),AND0 (w__36,w__37,w__38),ANDI (w__39,w__40,w__41),OR0 (w__42,w__43,w__44),ORI (w__45,w__46,w__47),NOR (w__48,w__49,w__50),XOR0 (w__51,w__52,w__53),XORI (w__54,w__55,w__56),LUI (w__57,w__58),DSLL (w__59,w__60,w__61),DSLL32 (w__62,w__63,w__64),DSLLV (w__65,w__66,w__67),DSRA (w__68,w__69,w__70),DSRA32 (w__71,w__72,w__73),DSRAV (w__74,w__75,w__76),DSRL (w__77,w__78,w__79),DSRL32 (w__80,w__81,w__82),DSRLV (w__83,w__84,w__85),SLL (w__86,w__87,w__88),SLLV (w__89,w__90,w__91),SRA (w__92,w__93,w__94),SRAV (w__95,w__96,w__97),SRL (w__98,w__99,w__100),SRLV (w__101,w__102,w__103),SLT (w__104,w__105,w__106),SLTI (w__107,w__108,w__109),SLTU (w__110,w__111,w__112),SLTIU (w__113,w__114,w__115),MOVN (w__116,w__117,w__118),MOVZ (w__119,w__120,w__121),MFHI w__122,MFLO w__123,MTHI w__124,MTLO w__125,MUL (w__126,w__127,w__128),MULT (w__129,w__130),MULTU (w__131,w__132),DMULT (w__133,w__134),DMULTU (w__135,w__136),MADD (w__137,w__138),MADDU (w__139,w__140),MSUB (w__141,w__142),MSUBU (w__143,w__144),DIV (w__145,w__146),DIVU (w__147,w__148),DDIV (w__149,w__150),DDIVU (w__151,w__152),J w__153,JAL w__154,JR w__155,JALR (w__156,w__157),BEQ (w__158,w__159,w__160,w__161,w__162),BCMPZ (w__163,w__164,w__165,w__166,w__167),SYSCALL_THREAD_START () ,ImplementationDefinedStopFetching () ,SYSCALL () ,BREAK () ,WAIT () ,TRAPREG (w__168,w__169,w__170),TRAPIMM (w__171,w__172,w__173),Load (w__174,w__175,w__176,w__177,w__178,w__179),Store (w__180,w__181,w__182,w__183,w__184),LWL (w__185,w__186,w__187),LWR (w__188,w__189,w__190),SWL (w__191,w__192,w__193),SWR (w__194,w__195,w__196),LDL (w__197,w__198,w__199),LDR (w__200,w__201,w__202),SDL (w__203,w__204,w__205),SDR (w__206,w__207,w__208),CACHE (w__209,w__210,w__211),PREF (w__212,w__213,w__214),SYNC () ,MFC0 (w__215,w__216,w__217,w__218),HCF () ,MTC0 (w__219,w__220,w__221,w__222),TLBWI () ,TLBWR () ,TLBR () ,TLBP () ,RDHWR (w__223,w__224),ERET () ,CGetPerm (w__225,w__226),CGetType (w__227,w__228),CGetBase (w__229,w__230),CGetLen (w__231,w__232),CGetTag (w__233,w__234),CGetSealed (w__235,w__236),CGetOffset (w__237,w__238),CGetAddr (w__239,w__240),CGetPCC w__241,CGetPCCSetOffset (w__242,w__243),CGetCause w__244,CSetCause w__245,CReadHwr (w__246,w__247),CWriteHwr (w__248,w__249),CAndPerm (w__250,w__251,w__252),CToPtr (w__253,w__254,w__255),CSub (w__256,w__257,w__258),CPtrCmp (w__259,w__260,w__261,w__262),CIncOffset (w__263,w__264,w__265),CIncOffsetImmediate (w__266,w__267,w__268),CSetOffset (w__269,w__270,w__271),CSetBounds (w__272,w__273,w__274),CSetBoundsImmediate (w__275,w__276,w__277),CSetBoundsExact (w__278,w__279,w__280),CClearTag (w__281,w__282),CMOVX (w__283,w__284,w__285,w__286),ClearRegs (w__287,w__288),CFromPtr (w__289,w__290,w__291),CBuildCap (w__292,w__293,w__294),CCopyType (w__295,w__296,w__297),CCheckPerm (w__298,w__299),CCheckType (w__300,w__301),CTestSubset (w__302,w__303,w__304),CSeal (w__305,w__306,w__307),CCSeal (w__308,w__309,w__310),CUnseal (w__311,w__312,w__313),CCall (w__314,w__315,w__316),CReturn () ,CBX (w__317,w__318,w__319),CBZ (w__320,w__321,w__322),CJALR (w__323,w__324,w__325),CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332),CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339),CSC (w__340,w__341,w__342,w__343,w__344,w__345),CLC (w__346,w__347,w__348,w__349,w__350),C2Dump w__351,RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))"
+     [DADDIU (u_8,u_7,u_6),DADDU (u_9,u_8,u_7),DADDI (u_8,u_7,u_15),DADD (u_9,u_8,u_7),ADD (u_9,u_8,u_7),ADDI (u_8,u_7,u_15),ADDU (u_9,u_8,u_7),ADDIU (u_8,u_7,u_15),DSUBU (u_9,u_8,u_7),DSUB (u_9,u_8,u_7),SUB (u_9,u_8,u_7),SUBU (u_9,u_8,u_7),AND0 (u_9,u_8,u_7),ANDI (u_8,u_7,u_15),OR0 (u_9,u_8,u_7),ORI (u_8,u_7,u_15),NOR (u_9,u_8,u_7),XOR0 (u_9,u_8,u_7),XORI (u_8,u_7,u_15),LUI (u_7,u_6),DSLL (u_9,u_8,u_7),DSLL32 (u_9,u_8,u_7),DSLLV (u_9,u_8,u_7),DSRA (u_9,u_8,u_7),DSRA32 (u_9,u_8,u_7),DSRAV (u_9,u_8,u_7),DSRL (u_9,u_8,u_7),DSRL32 (u_9,u_8,u_7),DSRLV (u_9,u_8,u_7),SLL (u_9,u_8,u_7),SLLV (u_9,u_8,u_7),SRA (u_9,u_8,u_7),SRAV (u_9,u_8,u_7),SRL (u_9,u_8,u_7),SRLV (u_9,u_8,u_7),SLT (u_9,u_8,u_7),SLTI (u_8,u_7,u_15),SLTU (u_9,u_8,u_7),SLTIU (u_8,u_7,u_15),MOVN (u_9,u_8,u_7),MOVZ (u_9,u_8,u_7),MFHI u_7,MFLO u_7,MTHI u_7,MTLO u_7,MUL (u_9,u_8,u_7),MULT (u_8,u_7),MULTU (u_8,u_7),DMULT (u_8,u_7),DMULTU (u_8,u_7),MADD (u_8,u_7),MADDU (u_8,u_7),MSUB (u_8,u_7),MSUBU (u_8,u_7),DIV (u_8,u_7),DIVU (u_8,u_7),DDIV (u_8,u_7),DDIVU (u_8,u_7),J u_16,JAL u_16,JR u_7,JALR (u_8,u_7),BEQ (u_8,u_7,u_6,u_5,u_4),BCMPZ (u_7,u_6,u_2,u_5,u_4),SYSCALL u_11,BREAK u_11,WAIT u_11,TRAPREG (u_8,u_7,u_2),TRAPIMM (u_7,u_6,u_2),Load (u_3,u_5,u_4,u_8,u_7,u_6),Store (u_3,u_4,u_8,u_7,u_6),LWL (u_8,u_7,u_15),LWR (u_8,u_7,u_15),SWL (u_8,u_7,u_15),SWR (u_8,u_7,u_15),LDL (u_8,u_7,u_15),LDR (u_8,u_7,u_15),SDL (u_8,u_7,u_15),SDR (u_8,u_7,u_15),CACHE (u_8,u_7,u_15),SYNC u_11,MFC0 (u_8,u_7,u_12,u_4),HCF u_11,MTC0 (u_8,u_7,u_12,u_4),TLBWI u_11,TLBWR u_11,TLBR u_11,TLBP u_11,RDHWR (u_8,u_7),ERET u_11,CGetPerm (u_8,u_7),CGetType (u_8,u_7),CGetBase (u_8,u_7),CGetLen (u_8,u_7),CGetTag (u_8,u_7),CGetSealed (u_8,u_7),CGetOffset (u_8,u_7),CGetAddr (u_8,u_7),CGetPCC u_7,CGetPCCSetOffset (u_8,u_7),CGetCause u_7,CSetCause u_7,CReadHwr (u_8,u_7),CWriteHwr (u_8,u_7),CAndPerm (u_9,u_8,u_7),CToPtr (u_9,u_8,u_7),CSub (u_9,u_8,u_7),CPtrCmp (u_9,u_8,u_7,u_0),CIncOffset (u_9,u_8,u_7),CIncOffsetImmediate (u_8,u_7,u_14),CSetOffset (u_9,u_8,u_7),CSetBounds (u_9,u_8,u_7),CSetBoundsImmediate (u_8,u_7,u_14),CSetBoundsExact (u_9,u_8,u_7),CClearTag (u_8,u_7),CMOVX (u_9,u_8,u_7,u_4),ClearRegs (u_1,u_15),CFromPtr (u_9,u_8,u_7),CBuildCap (u_9,u_8,u_7),CCopyType (u_9,u_8,u_7),CCheckPerm (u_8,u_7),CCheckType (u_8,u_7),CTestSubset (u_9,u_8,u_7),CSeal (u_9,u_8,u_7),CCSeal (u_9,u_8,u_7),CUnseal (u_9,u_8,u_7),CCall (u_8,u_7,u_14),CReturn u_11,CBX (u_7,u_15,u_4),CBZ (u_7,u_15,u_4),CJALR (u_8,u_7,u_4),CLoad (u_9,u_8,u_7,u_13,u_5,u_3,u_4),CStore (u_10,u_9,u_8,u_7,u_13,u_3,u_4),CSC (u_10,u_9,u_8,u_7,u_14,u_4),CLC (u_9,u_8,u_7,u_15,u_4),C2Dump u_7,RI u_11]))))))))))))))))))"
 
 
 (*val execute : ast -> M unit*)
 
 (*val decode : mword ty32 -> maybe ast*)
 
-definition DDC  :: "(5)Word.word "  where 
-     " DDC = ( (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))"
-
-
-definition IDC  :: "(5)Word.word "  where 
-     " IDC = ( (vec_of_bits [B1,B1,B0,B1,B0]  ::  5 Word.word))"
+definition IDCNO  :: "(5)Word.word "  where 
+     " IDCNO = ( (vec_of_bits [B1,B1,B0,B1,B0]  ::  5 Word.word))"
 
 
-definition KR1C  :: "(5)Word.word "  where 
-     " KR1C = ( (vec_of_bits [B1,B1,B0,B1,B1]  ::  5 Word.word))"
+definition KR1CNO  :: "(5)Word.word "  where 
+     " KR1CNO = ( (vec_of_bits [B1,B1,B0,B1,B1]  ::  5 Word.word))"
 
 
-definition KR2C  :: "(5)Word.word "  where 
-     " KR2C = ( (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word))"
+definition KR2CNO  :: "(5)Word.word "  where 
+     " KR2CNO = ( (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word))"
 
 
-definition KCC  :: "(5)Word.word "  where 
-     " KCC = ( (vec_of_bits [B1,B1,B1,B0,B1]  ::  5 Word.word))"
+definition KCCNO  :: "(5)Word.word "  where 
+     " KCCNO = ( (vec_of_bits [B1,B1,B1,B0,B1]  ::  5 Word.word))"
 
 
-definition KDC  :: "(5)Word.word "  where 
-     " KDC = ( (vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word))"
+definition KDCNO  :: "(5)Word.word "  where 
+     " KDCNO = ( (vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word))"
 
 
-definition EPCC  :: "(5)Word.word "  where 
-     " EPCC = ( (vec_of_bits [B1,B1,B1,B1,B1]  ::  5 Word.word))"
+definition EPCCNO  :: "(5)Word.word "  where 
+     " EPCCNO = ( (vec_of_bits [B1,B1,B1,B1,B1]  ::  5 Word.word))"
 
 
 definition CapRegs  :: "(((regstate),(register_value),((257)Word.word))register_ref)list "  where 
      " CapRegs = (
   [C31_ref,C30_ref,C29_ref,C28_ref,C27_ref,C26_ref,C25_ref,C24_ref,C23_ref,C22_ref,C21_ref,C20_ref,
    C19_ref,C18_ref,C17_ref,C16_ref,C15_ref,C14_ref,C13_ref,C12_ref,C11_ref,C10_ref,C09_ref,C08_ref,
-   C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,C00_ref])"
+   C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,DDC_ref])"
 
 
 definition max_otype  :: " int "  where 
@@ -3545,11 +3566,29 @@ definition have_cp2  :: " bool "  where
 
 (*
 This function reads a given capability register and returns its contents converted to a CapStruct.
+If the argument is zero then the null capability is returned.
 *)
 (*val readCapReg : mword ty5 -> M CapStruct*)
 
 definition readCapReg  :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad "  where 
      " readCapReg n = (
+   if (((n = (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))) then return null_cap
+   else
+     (let i = (Word.uint n) in
+     (reg_deref ((access_list_dec CapRegs i  :: (regstate, register_value, ( 257 Word.word)) register_ref))
+       :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 ::  257 Word.word) . 
+     return ((capRegToCapStruct w__0)))))"
+
+
+(*
+This is the same as readCapReg except that when the argument is zero the value of DDC is returned 
+instead of the null capability. This is used for instructions that expect an address, where using
+null would always generate an exception.
+*)
+(*val readCapRegDDC : mword ty5 -> M CapStruct*)
+
+definition readCapRegDDC  :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad "  where 
+     " readCapRegDDC n = (
    (let i = (Word.uint n) in
    (reg_deref ((access_list_dec CapRegs i  :: (regstate, register_value, ( 257 Word.word)) register_ref))
      :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 ::  257 Word.word) . 
@@ -3560,39 +3599,41 @@ definition readCapReg  :: "(5)Word.word \<Rightarrow>((register_value),(CapStruc
 
 definition writeCapReg  :: "(5)Word.word \<Rightarrow> CapStruct \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " writeCapReg n cap = (
-   (let i = (Word.uint n) in
-   write_reg
-     ((access_list_dec CapRegs i  :: (regstate, register_value, ( 257 Word.word)) register_ref))
-     ((capStructToCapReg cap  ::  257 Word.word))))"
+   if (((n = (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))) then return () 
+   else
+     (let i = (Word.uint n) in
+     write_reg
+       ((access_list_dec CapRegs i  :: (regstate, register_value, ( 257 Word.word)) register_ref))
+       ((capStructToCapReg cap  ::  257 Word.word))))"
 
 
 (*val CapEx_of_num : integer -> CapEx*)
 
 definition CapEx_of_num  :: " int \<Rightarrow> CapEx "  where 
      " CapEx_of_num arg0 = (
-   (let l__32 = arg0 in
-   if (((l__32 = (( 0 :: int)::ii)))) then CapEx_None
-   else if (((l__32 = (( 1 :: int)::ii)))) then CapEx_LengthViolation
-   else if (((l__32 = (( 2 :: int)::ii)))) then CapEx_TagViolation
-   else if (((l__32 = (( 3 :: int)::ii)))) then CapEx_SealViolation
-   else if (((l__32 = (( 4 :: int)::ii)))) then CapEx_TypeViolation
-   else if (((l__32 = (( 5 :: int)::ii)))) then CapEx_CallTrap
-   else if (((l__32 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap
-   else if (((l__32 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow
-   else if (((l__32 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation
-   else if (((l__32 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap
-   else if (((l__32 = (( 10 :: int)::ii)))) then CapEx_InexactBounds
-   else if (((l__32 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation
-   else if (((l__32 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation
-   else if (((l__32 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation
-   else if (((l__32 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation
-   else if (((l__32 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation
-   else if (((l__32 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation
-   else if (((l__32 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation
-   else if (((l__32 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation
-   else if (((l__32 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation
-   else if (((l__32 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation
-   else if (((l__32 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CapEx_None
+   else if (((p00 = (( 1 :: int)::ii)))) then CapEx_LengthViolation
+   else if (((p00 = (( 2 :: int)::ii)))) then CapEx_TagViolation
+   else if (((p00 = (( 3 :: int)::ii)))) then CapEx_SealViolation
+   else if (((p00 = (( 4 :: int)::ii)))) then CapEx_TypeViolation
+   else if (((p00 = (( 5 :: int)::ii)))) then CapEx_CallTrap
+   else if (((p00 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap
+   else if (((p00 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow
+   else if (((p00 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation
+   else if (((p00 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap
+   else if (((p00 = (( 10 :: int)::ii)))) then CapEx_InexactBounds
+   else if (((p00 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation
+   else if (((p00 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation
+   else if (((p00 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation
+   else if (((p00 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation
+   else if (((p00 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation
+   else if (((p00 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation
+   else if (((p00 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation
+   else if (((p00 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation
+   else if (((p00 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation
+   else if (((p00 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation
+   else if (((p00 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation
    else CapEx_PermitUnsealViolation))"
 
 
@@ -3665,59 +3706,99 @@ fun CapExCode  :: " CapEx \<Rightarrow>(8)Word.word "  where
 definition undefined_CapCauseReg  :: " unit \<Rightarrow>((register_value),(CapCauseReg),(exception))monad "  where 
      " undefined_CapCauseReg _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 ::  16 Word.word) . 
-   internal_pick [Mk_CapCauseReg w__0]))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 ::  16 Word.word) . 
+   return ((| CapCauseReg_CapCauseReg_chunk_0 = w__0 |))))"
+
+
+(*val Mk_CapCauseReg : mword ty16 -> CapCauseReg*)
+
+definition Mk_CapCauseReg  :: "(16)Word.word \<Rightarrow> CapCauseReg "  where 
+     " Mk_CapCauseReg v = (
+   (| CapCauseReg_CapCauseReg_chunk_0 = ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) |) )"
 
 
-fun get_CapCauseReg  :: " CapCauseReg \<Rightarrow>(16)Word.word "  where 
-     " get_CapCauseReg (Mk_CapCauseReg (v)) = ( v )"
+definition get_CapCauseReg_bits  :: " CapCauseReg \<Rightarrow>(16)Word.word "  where 
+     " get_CapCauseReg_bits v = (
+   (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   v) (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))"
 
 
-definition set_CapCauseReg  :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_CapCauseReg r_ref v = (
+definition set_CapCauseReg_bits  :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_CapCauseReg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_CapCauseReg v) in
+   (let r =
+     ((r (|
+       CapCauseReg_CapCauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   r) (( 15 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+            ::  16 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-fun get_CapCauseReg_ExcCode  :: " CapCauseReg \<Rightarrow>(8)Word.word "  where 
-     " get_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))"
+definition update_CapCauseReg_bits  :: " CapCauseReg \<Rightarrow>(16)Word.word \<Rightarrow> CapCauseReg "  where 
+     " update_CapCauseReg_bits v x = (
+   (v (|
+     CapCauseReg_CapCauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   v) (( 15 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+          ::  16 Word.word))|)))"
+
+
+definition get_CapCauseReg_ExcCode  :: " CapCauseReg \<Rightarrow>(8)Word.word "  where 
+     " get_CapCauseReg_ExcCode v = (
+   (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   v) (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))"
 
 
 definition set_CapCauseReg_ExcCode  :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CapCauseReg_ExcCode r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . 
-   (let r = ((get_CapCauseReg w__0  ::  16 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v  ::  16 Word.word)) in
-   write_reg r_ref (Mk_CapCauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CapCauseReg_CapCauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   r) (( 15 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  16 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_CapCauseReg_ExcCode  :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg "  where 
-     " update_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) x = (
-   Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x  ::  16 Word.word)))"
+definition update_CapCauseReg_ExcCode  :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg "  where 
+     " update_CapCauseReg_ExcCode v x = (
+   (v (|
+     CapCauseReg_CapCauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   v) (( 15 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  16 Word.word))|)))"
 
 
 (*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*)
 
-fun get_CapCauseReg_RegNum  :: " CapCauseReg \<Rightarrow>(8)Word.word "  where 
-     " get_CapCauseReg_RegNum (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
+definition get_CapCauseReg_RegNum  :: " CapCauseReg \<Rightarrow>(8)Word.word "  where 
+     " get_CapCauseReg_RegNum v = (
+   (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
 
 
 (*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*)
 
 definition set_CapCauseReg_RegNum  :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_CapCauseReg_RegNum r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . 
-   (let r = ((get_CapCauseReg w__0  ::  16 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v  ::  16 Word.word)) in
-   write_reg r_ref (Mk_CapCauseReg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       CapCauseReg_CapCauseReg_chunk_0 :=
+         ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  16 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*)
 
-fun update_CapCauseReg_RegNum  :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg "  where 
-     " update_CapCauseReg_RegNum (Mk_CapCauseReg (v)) x = (
-   Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x  ::  16 Word.word)))"
+definition update_CapCauseReg_RegNum  :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg "  where 
+     " update_CapCauseReg_RegNum v x = (
+   (v (|
+     CapCauseReg_CapCauseReg_chunk_0 :=
+       ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  16 Word.word))|)))"
 
 
 (*val execute_branch_pcc : CapStruct -> M unit*)
@@ -3735,9 +3816,9 @@ definition execute_branch_pcc  :: " CapStruct \<Rightarrow>((register_value),(un
 
 definition ERETHook  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " ERETHook _ = (
-   (read_reg C31_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . 
+   (read_reg EPCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . 
    (write_reg nextPCC_ref w__0 \<then>
-   (read_reg C31_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) .  write_reg delayedPCC_ref w__1)))"
+   (read_reg EPCC_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) .  write_reg delayedPCC_ref w__1)))"
 
 
 (*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*)
@@ -3757,7 +3838,7 @@ definition raise_c2_exception8  :: " CapEx \<Rightarrow>(8)Word.word \<Rightarro
 definition raise_c2_exception  :: " CapEx \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),'o,(exception))monad "  where 
      " raise_c2_exception capEx regnum = (
    (let reg8 = ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word) regnum  ::  8 Word.word)) in
-   if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDC)))))) then
+   if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDCNO)))))) then
      raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8
    else raise_c2_exception8 capEx reg8))"
 
@@ -3786,11 +3867,11 @@ The following function should be called before reading or writing any capability
 definition register_inaccessible  :: "(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " register_inaccessible r = (
    or_boolM
-     (and_boolM (return (((r = IDC))))
+     (and_boolM (return (((r = IDCNO))))
         ((read_reg inCCallDelay_ref  :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 ::  1 Word.word) . 
          return ((bits_to_bool w__0)))))
      (and_boolM
-        (return ((((((r = KR1C))) \<or> ((((((r = KR2C))) \<or> ((((((r = KDC))) \<or> ((((((r = KCC))) \<or> (((r = EPCC))))))))))))))))
+        (return ((((((r = KR1CNO))) \<or> ((((((r = KR2CNO))) \<or> ((((((r = KDCNO))) \<or> ((((((r = KCCNO))) \<or> (((r = EPCCNO))))))))))))))))
         (pcc_access_system_regs ()  \<bind> (\<lambda> (w__2 :: bool) .  return ((\<not> w__2))))))"
 
 
@@ -3798,44 +3879,42 @@ definition register_inaccessible  :: "(5)Word.word \<Rightarrow>((register_value
 
 definition MEMr_tagged  :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad "  where 
      " MEMr_tagged addr = (
-   (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
-   read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . 
-   (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size  :: ( 256 Word.word) M) \<bind> (\<lambda> data . 
-   (let ((cast_0 :: bool), (cast_1 ::  256 Word.word)) = (tag, (reverse_endianness data  ::  256 Word.word)) in
-   return (cast_0, (Word.ucast cast_1  ::  256 Word.word))))))"
+   (assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
+   read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . 
+   (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size  :: ( 256 Word.word) M) \<bind> (\<lambda> data . 
+   return (tag, (reverse_endianness data  ::  256 Word.word)))))"
 
 
 (*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*)
 
 definition MEMr_tagged_reserve  :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad "  where 
      " MEMr_tagged_reserve addr = (
-   (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
-   read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . 
-   (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size  :: ( 256 Word.word) M) \<bind> (\<lambda> data . 
-   (let ((cast_0 :: bool), (cast_1 ::  256 Word.word)) = (tag, (reverse_endianness data  ::  256 Word.word)) in
-   return (cast_0, (Word.ucast cast_1  ::  256 Word.word))))))"
+   (assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
+   read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . 
+   (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size  :: ( 256 Word.word) M) \<bind> (\<lambda> data . 
+   return (tag, (reverse_endianness data  ::  256 Word.word)))))"
 
 
 (*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*)
 
 definition MEMw_tagged  :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " MEMw_tagged addr tag data = (
-   ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
-   MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then>
-   MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  ::  256 Word.word))) \<then> write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag )"
+   ((assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
+   MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then>
+   MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  ::  256 Word.word))) \<then> write_tag_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag )"
 
 
 (*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*)
 
 definition MEMw_tagged_conditional  :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " MEMw_tagged_conditional addr tag data = (
-   ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
-   MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then>
+   ((assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then>
+   MEMea_conditional instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then>
    MEMval_conditional 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  ::  256 Word.word))) \<bind> (\<lambda> success . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  ::  256 Word.word))) \<bind> (\<lambda> success . 
    (if success then write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))"
 
 
 definition cap_addr_mask  :: "(64)Word.word "  where 
@@ -3863,9 +3942,9 @@ definition MEMw_wrapper  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_t
                                ::  64 Word.word))
                            ::  64 Word.word)) cap_addr_mask
                        ::  64 Word.word))))) ('''') \<then>
-     MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then>
-     MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  ::  64 Word.word)) False))"
+     MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) \<then>
+     MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  ::  64 Word.word)) False))"
 
 
 (*val MEMw_conditional_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*)
@@ -3879,47 +3958,87 @@ definition MEMw_conditional_wrapper  :: "(64)Word.word \<Rightarrow> int \<Right
                              ::  64 Word.word))
                          ::  64 Word.word)) cap_addr_mask
                      ::  64 Word.word))))) ('''') \<then>
-   MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then>
+   MEMea_conditional instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) \<then>
    MEMval_conditional 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data  :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data  :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . 
    (if success then write_tag_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  ::  64 Word.word)) False
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  ::  64 Word.word)) False
     else return () ) \<then>
    return success))"
 
 
-(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*)
+(*val checkDDCPerms : CapStruct -> MemAccessType -> M unit*)
 
-definition addrWrapper  :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
-     " addrWrapper addr accessType width = (
-   (let capno = ((vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)) in
-   readCapReg capno \<bind> (\<lambda> cap . 
-   ((if ((\<not>(CapStruct_tag   cap))) then raise_c2_exception CapEx_TagViolation capno
-    else if(CapStruct_sealed   cap) then raise_c2_exception CapEx_SealViolation capno
+definition checkDDCPerms  :: " CapStruct \<Rightarrow> MemAccessType \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " checkDDCPerms (ddc :: CapStruct) (accessType :: MemAccessType) = (
+   (if ((\<not>(CapStruct_tag   ddc))) then
+      raise_c2_exception CapEx_TagViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+    else if(CapStruct_sealed   ddc) then
+      raise_c2_exception CapEx_SealViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
     else return () ) \<then>
    (case  accessType of
-     Instruction =>
-      if ((\<not>(CapStruct_permit_execute   cap))) then
-        raise_c2_exception CapEx_PermitExecuteViolation capno
-      else return () 
+     Instruction => assert_exp False ('''')
    | LoadData =>
-      if ((\<not>(CapStruct_permit_load   cap))) then raise_c2_exception CapEx_PermitLoadViolation capno
+      if ((\<not>(CapStruct_permit_load   ddc))) then
+        raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
       else return () 
    | StoreData =>
-      if ((\<not>(CapStruct_permit_store   cap))) then raise_c2_exception CapEx_PermitStoreViolation capno
+      if ((\<not>(CapStruct_permit_store   ddc))) then
+        raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
       else return () 
-   )) \<then>
-   ((let cursor = (getCapCursor cap) in
-   (let vAddr = (hardware_mod ((cursor + ((Word.uint addr)))) ((pow2 (( 64 :: int)::ii)))) in
+   ))"
+
+
+(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*)
+
+definition addrWrapper  :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
+     " addrWrapper addr accessType width = (
+   (read_reg DDC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 ::  257 Word.word) . 
+   (let ddc = (capRegToCapStruct w__0) in
+   checkDDCPerms ddc accessType \<then>
+   ((let cursor = (getCapCursor ddc) in
+   (let vAddr = (((cursor + ((Word.uint addr)))) mod ((pow2 (( 64 :: int)::ii)))) in
    (let size1 = (wordWidthBytes width) in
-   (let base = (getCapBase cap) in
-   (let top1 = (getCapTop cap) in
+   (let base = (getCapBase ddc) in
+   (let top1 = (getCapTop ddc) in
    if ((((vAddr + size1)) > top1)) then
-     (raise_c2_exception CapEx_LengthViolation capno  :: ( 64 Word.word) M)
-   else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno  :: ( 64 Word.word) M)
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+       :: ( 64 Word.word) M)
+   else if ((vAddr < base)) then
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+       :: ( 64 Word.word) M)
    else return ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)))))))))))"
 
 
+(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> M (mword ty64)*)
+
+definition addrWrapperUnaligned  :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordTypeUnaligned \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
+     " addrWrapperUnaligned addr accessType width = (
+   (read_reg DDC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 ::  257 Word.word) . 
+   (let ddc = (capRegToCapStruct w__0) in
+   checkDDCPerms ddc accessType \<then>
+   ((let cursor = (getCapCursor ddc) in
+   (let vAddr = (((cursor + ((Word.uint addr)))) mod ((pow2 (( 64 :: int)::ii)))) in
+   (let woffset = (vAddr mod (( 4 :: int)::ii)) in
+   (let doffset = (vAddr mod (( 8 :: int)::ii)) in
+   (let ((waddr :: ii), (size1 :: ii)) =
+     ((case  width of
+       WL => (vAddr, (( 4 :: int)::ii) - woffset)
+     | WR => (vAddr - woffset, woffset + (( 1 :: int)::ii))
+     | DL => (vAddr, (( 8 :: int)::ii) - doffset)
+     | DR => (vAddr - doffset, doffset + (( 1 :: int)::ii))
+     )) in
+   (let base = (getCapBase ddc) in
+   (let top1 = (getCapTop ddc) in
+   if ((((waddr + size1)) > top1)) then
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+       :: ( 64 Word.word) M)
+   else if ((waddr < base)) then
+     (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+       :: ( 64 Word.word) M)
+   else return ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)))))))))))))"
+
+
 (*val TranslatePC : mword ty64 -> M (mword ty64)*)
 
 definition TranslatePC  :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
@@ -3964,13 +4083,22 @@ definition checkCP2usable  :: " unit \<Rightarrow>((register_value),(unit),(exce
 definition init_cp2_state  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " init_cp2_state _ = (
    (let defaultBits = ((capStructToCapReg default_cap  ::  257 Word.word)) in
-   ((write_reg PCC_ref defaultBits \<then>
+   (let nullBits = ((capStructToCapReg null_cap  ::  257 Word.word)) in
+   ((((((((((write_reg PCC_ref defaultBits \<then>
    write_reg nextPCC_ref defaultBits) \<then>
    write_reg delayedPCC_ref defaultBits) \<then>
-   (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () 
+   write_reg DDC_ref defaultBits) \<then>
+   write_reg KCC_ref defaultBits) \<then>
+   write_reg EPCC_ref defaultBits) \<then>
+   write_reg KDC_ref nullBits) \<then>
+   write_reg KR1C_ref nullBits) \<then>
+   write_reg KR2C_ref nullBits) \<then>
+   write_reg CTLSP_ref nullBits) \<then>
+   write_reg CTLSU_ref nullBits) \<then>
+   (foreachM (index_list (( 1 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () 
      (\<lambda> i unit_var . 
        (let idx = ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) i  ::  5 Word.word)) in
-       writeCapReg idx default_cap)))))"
+       writeCapReg idx null_cap))))))"
 
 
 definition cp2_next_pc  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
@@ -3995,34 +4123,29 @@ definition capToString  :: " CapStruct \<Rightarrow>((register_value),(string),(
                       (((op@) (if(CapStruct_sealed   cap) then (''1'') else (''0''))
                           (((op@) ('' perms:'')
                               (((op@)
-                                  ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                  ((string_of_bits
                                       ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
                                           ((getCapPerms cap  ::  31 Word.word))
                                          ::  32 Word.word))))
                                   (((op@) ('' type:'')
-                                      (((op@) ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict(CapStruct_otype   cap)))
+                                      (((op@) ((string_of_bits(CapStruct_otype   cap)))
                                           (((op@) ('' offset:'')
                                               (((op@)
-                                                  ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                  ((string_of_bits
                                                       ((to_bits
                                                           ((make_the_value (( 64 :: int)::ii)  ::  64 itself))
                                                           ((getCapOffset cap))
                                                          ::  64 Word.word))))
                                                   (((op@) ('' base:'')
                                                       (((op@)
-                                                          ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                          ((string_of_bits
                                                               ((to_bits
                                                                   ((make_the_value (( 64 :: int)::ii)
                                                                      ::  64 itself))
                                                                   ((getCapBase cap))
                                                                  ::  64 Word.word))))
                                                           (((op@) ('' length:'')
-                                                              ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                              ((string_of_bits
                                                                   ((to_bits
                                                                       ((make_the_value (( 64 :: int)::ii)
                                                                          ::  64 itself))
@@ -4035,24 +4158,48 @@ definition dump_cp2_state  :: " unit \<Rightarrow>((register_value),(unit),(exce
      " dump_cp2_state _ = (
    (read_reg PCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 ::  257 Word.word) . 
    capToString ((capRegToCapStruct w__0)) \<bind> (\<lambda> (w__1 :: string) . 
-   (let (_ :: unit) = (prerr_endline (((op@) (''DEBUG CAP PCC'') w__1))) in
-   (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP PCC'') w__1))) in
+   ((foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () 
      (\<lambda> i unit_var . 
        readCapReg ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) i  ::  5 Word.word)) \<bind> (\<lambda> (w__2 ::
          CapStruct) . 
        capToString w__2 \<bind> (\<lambda> (w__3 :: string) . 
        return ((let _ =
-         (prerr_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int 
+         (print_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int 
   instance_Show_Show_Num_integer_dict i)) w__3))))) in
-       () ))))))))))"
+       () )))))) \<then>
+   (read_reg DDC_ref  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__4)) \<bind> (\<lambda> (w__5 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 00'') w__5))) in
+   (read_reg CTLSU_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__6 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__6)) \<bind> (\<lambda> (w__7 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 01'') w__7))) in
+   (read_reg CTLSP_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__8 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__8)) \<bind> (\<lambda> (w__9 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 08'') w__9))) in
+   (read_reg KR1C_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__10 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__10)) \<bind> (\<lambda> (w__11 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 22'') w__11))) in
+   (read_reg KR2C_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__12 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__12)) \<bind> (\<lambda> (w__13 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 23'') w__13))) in
+   (read_reg KCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__14)) \<bind> (\<lambda> (w__15 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 29'') w__15))) in
+   (read_reg KDC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__16 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__16)) \<bind> (\<lambda> (w__17 :: string) . 
+   (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 30'') w__17))) in
+   (read_reg EPCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__18 ::  257 Word.word) . 
+   capToString ((capRegToCapStruct w__18)) \<bind> (\<lambda> (w__19 :: string) . 
+   return ((print_endline (((op@) (''DEBUG CAP HWREG 31'') w__19)))))))))))))))))))))))))))))))"
 
 
 (*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*)
 
 definition extendLoad  :: "('sz::len)Word.word \<Rightarrow> bool \<Rightarrow>(64)Word.word "  where 
      " extendLoad memResult sign = (
-   if sign then (sign_extend1 (( 64 :: int)::ii) memResult  ::  64 Word.word)
-   else (zero_extend1 (( 64 :: int)::ii) memResult  ::  64 Word.word))"
+   if sign then (mips_sign_extend (( 64 :: int)::ii) memResult  ::  64 Word.word)
+   else (mips_zero_extend (( 64 :: int)::ii) memResult  ::  64 Word.word))"
 
 
 (*val TLBWriteEntry : mword ty6 -> M unit*)
@@ -4489,10 +4636,6 @@ definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where
      (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii)  ::  5 Word.word)) in
      (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) in
      Some (BCMPZ (rs,imm,LE,False,True))))
-   else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,
-                             B1,B1,B0,B0,B1,B1,B0,B0]
-                 ::  32 Word.word)))) then
-     Some (SYSCALL_THREAD_START () )
    else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0]  ::  6 Word.word))))))) then
      Some (SYSCALL () )
    else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1]  ::  6 Word.word))))))) then
@@ -4669,11 +4812,6 @@ definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where
      (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii)  ::  5 Word.word)) in
      (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) in
      Some (CACHE (base,op1,imm)))))
-   else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1]  ::  6 Word.word)))) then
-     (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii)  ::  5 Word.word)) in
-     (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) in
-     Some (PREF (base,op1,imm)))))
    else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii)  ::  21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
                      ::  21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1]  ::  6 Word.word))))))) then
      Some (SYNC () )
@@ -5267,13 +5405,19 @@ definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where
      (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii)  ::  5 Word.word)) in
      (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii)  ::  5 Word.word)) in
      (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii)  ::  11 Word.word)) in
-     Some (CLC (cd1,cb,rt,offset,False))))))
+     Some (CLC (cd1,cb,rt,(mips_sign_extend (( 16 :: int)::ii) offset  ::  16 Word.word),False))))))
    else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii)  ::  11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0]  ::  11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii)  ::  11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]  ::  11 Word.word))))))) then
      (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii)  ::  5 Word.word)) in
      (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii)  ::  5 Word.word)) in
      Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,
-                                                                                B0,B0,B0,B0]
-                                                                    ::  11 Word.word),True))))
+                                                                                B0,B0,B0,B0,B0,B0,B0,
+                                                                                B0,B0]
+                                                                    ::  16 Word.word),True))))
+   else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1]  ::  6 Word.word)))) then
+     (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii)  ::  5 Word.word)) in
+     (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii)  ::  5 Word.word)) in
+     (let (offset :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) in
+     Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word),offset,False)))))
    else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii)  ::  11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0]  ::  11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0]  ::  16 Word.word)))))))
    then
      (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii)  ::  5 Word.word)) in
@@ -5286,7 +5430,7 @@ definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where
 definition execute_XORI  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_XORI rs rt imm = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
+   wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
 
 
 (*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5301,7 +5445,7 @@ definition execute_XOR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 (*val execute_WAIT : unit -> M unit*)
 
 definition execute_WAIT  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_WAIT g__121 = (
+     " execute_WAIT g__19 = (
    (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) .  write_reg nextPC_ref w__0))"
 
 
@@ -5321,7 +5465,7 @@ definition execute_TRAPREG  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar
 definition execute_TRAPIMM  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_TRAPIMM rs imm cmp = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . 
-   (let (imm_val :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word)) in
+   (let (imm_val :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm  ::  64 Word.word)) in
    (let condition = (compare cmp rs_val imm_val) in
    if condition then SignalException Tr
    else return () ))))"
@@ -5330,7 +5474,7 @@ definition execute_TRAPIMM  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Righta
 (*val execute_TLBWR : unit -> M unit*)
 
 definition execute_TLBWR  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_TLBWR g__125 = (
+     " execute_TLBWR g__23 = (
    (checkCP0Access ()  \<then>
    (read_reg TLBRandom_ref  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 ::  6 Word.word) .  TLBWriteEntry w__0))"
 
@@ -5338,7 +5482,7 @@ definition execute_TLBWR  :: " unit \<Rightarrow>((register_value),(unit),(excep
 (*val execute_TLBWI : unit -> M unit*)
 
 definition execute_TLBWI  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_TLBWI g__124 = (
+     " execute_TLBWI g__22 = (
    (checkCP0Access ()  \<then>
    (read_reg TLBIndex_ref  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 ::  6 Word.word) .  TLBWriteEntry w__0))"
 
@@ -5346,7 +5490,7 @@ definition execute_TLBWI  :: " unit \<Rightarrow>((register_value),(unit),(excep
 (*val execute_TLBR : unit -> M unit*)
 
 definition execute_TLBR  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_TLBR g__126 = (
+     " execute_TLBR g__24 = (
    (checkCP0Access ()  \<then>
    (read_reg TLBIndex_ref  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: TLBIndexT) . 
    (let i = (Word.uint w__0) in
@@ -5374,10 +5518,10 @@ definition execute_TLBR  :: " unit \<Rightarrow>((register_value),(unit),(except
 (*val execute_TLBP : unit -> M unit*)
 
 definition execute_TLBP  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_TLBP g__127 = (
+     " execute_TLBP g__25 = (
    (checkCP0Access ()  \<then>
    read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . 
-   (tlbSearch ((get_TLBEntryHiReg w__0  ::  64 Word.word))  :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . 
+   (tlbSearch ((get_TLBEntryHiReg_bits w__0  ::  64 Word.word))  :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . 
    (case  result of
      Some (idx) =>
       write_reg TLBProbe_ref (vec_of_bits [B0]  ::  1 Word.word) \<then> write_reg TLBIndex_ref idx
@@ -5392,7 +5536,7 @@ definition execute_TLBP  :: " unit \<Rightarrow>((register_value),(unit),(except
 definition execute_Store  :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_Store width conditional base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
+   (addrWrapper ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
       StoreData width
      :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . 
@@ -5403,19 +5547,14 @@ definition execute_Store  :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.
        (read_reg CP0LLBit_ref  :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . 
        (if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then
           (case  width of
-            B =>
-             MEMw_conditional_wrapper pAddr (( 1 :: int)::ii)
-               ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
-          | H =>
-             MEMw_conditional_wrapper pAddr (( 2 :: int)::ii)
-               ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
-          | W =>
+            W =>
              MEMw_conditional_wrapper pAddr (( 4 :: int)::ii)
                ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
           | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rt_val
+          | _ => throw (Error_internal_error () )
           )
         else return False) \<bind> (\<lambda> (success :: bool) . 
-       wGPR rt ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success  ::  1 Word.word))  ::  64 Word.word))))
+       wGPR rt ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success  ::  1 Word.word))  ::  64 Word.word))))
      else
        (case  width of
          B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
@@ -5425,22 +5564,16 @@ definition execute_Store  :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.
        ))))))"
 
 
-(*val execute_SYSCALL_THREAD_START : unit -> unit*)
-
-definition execute_SYSCALL_THREAD_START  :: " unit \<Rightarrow> unit "  where 
-     " execute_SYSCALL_THREAD_START g__117 = ( ()  )"
-
-
 (*val execute_SYSCALL : unit -> M unit*)
 
 definition execute_SYSCALL  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_SYSCALL g__119 = ( SignalException Sys )"
+     " execute_SYSCALL g__17 = ( SignalException Sys )"
 
 
 (*val execute_SYNC : unit -> M unit*)
 
 definition execute_SYNC  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_SYNC g__122 = ( MEM_sync ()  )"
+     " execute_SYNC g__20 = ( MEM_sync ()  )"
 
 
 (*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
@@ -5448,8 +5581,8 @@ definition execute_SYNC  :: " unit \<Rightarrow>((register_value),(unit),(except
 definition execute_SWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_SWR base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
-      StoreData W
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) StoreData WR
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
    (TLBTranslate vAddr StoreData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
    (let wordAddr =
@@ -5472,8 +5605,8 @@ definition execute_SWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 definition execute_SWL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_SWL base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
-      StoreData W
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) StoreData WL
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
    (TLBTranslate vAddr StoreData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . 
@@ -5495,10 +5628,10 @@ definition execute_SUBU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> opB . 
    if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
    else
      wGPR rd
-       ((sign_extend1 (( 64 :: int)::ii)
+       ((mips_sign_extend (( 64 :: int)::ii)
            ((sub_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
               ::  32 Word.word))
@@ -5513,19 +5646,21 @@ definition execute_SUB  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> opB . 
    if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
    else
      (let (temp33 :: 33 bits) =
        ((sub_vec
-          ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  33 Word.word))
-          ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  33 Word.word))
+          ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+             ::  33 Word.word))
+          ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+             ::  33 Word.word))
          ::  33 Word.word)) in
      if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 :: int)::ii)))))
             ((bit_to_bool ((access_vec_dec temp33 (( 31 :: int)::ii))))))) then
        SignalException Ov
      else
        wGPR rd
-         ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+         ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
             ::  64 Word.word))))))"
 
 
@@ -5538,12 +5673,12 @@ definition execute_SRLV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word)) in
    if ((NotWordVal temp)) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)
    else
      (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
      (shift_bits_right 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
-     wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2  ::  64 Word.word))))))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
+     wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2  ::  64 Word.word))))))))"
 
 
 (*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5553,12 +5688,12 @@ definition execute_SRL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
    if ((NotWordVal temp)) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
    else
      (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
      (shift_bits_right 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
-     wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1  ::  64 Word.word))))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
+     wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1  ::  64 Word.word))))))"
 
 
 (*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5570,12 +5705,12 @@ definition execute_SRAV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word)) in
    if ((NotWordVal temp)) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)
    else
      (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
      (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
-     wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2  ::  64 Word.word))))))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
+     wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2  ::  64 Word.word))))))))"
 
 
 (*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5585,12 +5720,12 @@ definition execute_SRA  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
    if ((NotWordVal temp)) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
    else
      (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
      (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
-     wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1  ::  64 Word.word))))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
+     wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1  ::  64 Word.word))))))"
 
 
 (*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5600,7 +5735,7 @@ definition execute_SLTU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . 
    wGPR rd
-     ((zero_extend1 (( 64 :: int)::ii)
+     ((mips_zero_extend (( 64 :: int)::ii)
          (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1]  ::  1 Word.word)
           else (vec_of_bits [B0]  ::  1 Word.word))
         ::  64 Word.word)))))"
@@ -5611,9 +5746,9 @@ definition execute_SLTU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
 definition execute_SLTIU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_SLTIU rs rt imm = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . 
-   (let (immext :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word)) in
+   (let (immext :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm  ::  64 Word.word)) in
    wGPR rt
-     ((zero_extend1 (( 64 :: int)::ii)
+     ((mips_zero_extend (( 64 :: int)::ii)
          (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1]  ::  1 Word.word)
           else (vec_of_bits [B0]  ::  1 Word.word))
         ::  64 Word.word)))))"
@@ -5627,7 +5762,7 @@ definition execute_SLTI  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rs_val = (Word.sint w__0) in
    wGPR rt
-     ((zero_extend1 (( 64 :: int)::ii)
+     ((mips_zero_extend (( 64 :: int)::ii)
          (if ((rs_val < imm_val)) then (vec_of_bits [B1]  ::  1 Word.word)
           else (vec_of_bits [B0]  ::  1 Word.word))
         ::  64 Word.word))))))"
@@ -5640,7 +5775,7 @@ definition execute_SLT  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
    wGPR rd
-     ((zero_extend1 (( 64 :: int)::ii)
+     ((mips_zero_extend (( 64 :: int)::ii)
          (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1]  ::  1 Word.word)
           else (vec_of_bits [B0]  ::  1 Word.word))
         ::  64 Word.word)))))"
@@ -5654,8 +5789,8 @@ definition execute_SLLV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word)) in
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
    (let rt32 = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
-   wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2  ::  64 Word.word))))))))"
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
+   wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2  ::  64 Word.word))))))))"
 
 
 (*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5664,8 +5799,8 @@ definition execute_SLL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
      " execute_SLL rt rd sa = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rt32 = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
-   wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1  ::  64 Word.word))))))"
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
+   wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1  ::  64 Word.word))))))"
 
 
 (*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
@@ -5673,8 +5808,8 @@ definition execute_SLL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 definition execute_SDR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_SDR base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
-      StoreData D
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) StoreData DR
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
    (TLBTranslate vAddr StoreData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . 
@@ -5705,8 +5840,8 @@ definition execute_SDR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 definition execute_SDL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_SDL base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
-      StoreData D
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) StoreData DL
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
    (TLBTranslate vAddr StoreData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . 
@@ -5731,7 +5866,7 @@ definition execute_SDL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 (*val execute_RI : unit -> M unit*)
 
 definition execute_RI  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_RI g__130 = ( SignalException ResI )"
+     " execute_RI g__28 = ( SignalException ResI )"
 
 
 (*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*)
@@ -5741,7 +5876,8 @@ definition execute_RDHWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    getAccessLevel ()  \<bind> (\<lambda> accessLevel . 
    (let (haveAccessLevel :: bool) = (accessLevel = Kernel) in
    read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . 
-   (let (haveCU0 :: bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0  ::  4 Word.word)) (( 0 :: int)::ii)))) in
+   (let (haveCU0 :: bool) =
+     (B1 = ((access_vec_dec ((get_StatusReg_CU w__0  ::  4 Word.word)) (( 0 :: int)::ii)))) in
    (let rdi = (Word.uint rd) in
    (read_reg CP0HWREna_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
    (let (haveHWREna :: bool) = (B1 = ((access_vec_dec w__1 rdi))) in
@@ -5749,32 +5885,26 @@ definition execute_RDHWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
     else return () ) \<then>
    ((let b__146 = rd in
    (if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))) then
-      return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
     else if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))) then
-      return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
     else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))) then
       (read_reg CP0Count_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . 
-      return ((zero_extend1 (( 64 :: int)::ii) w__2  ::  64 Word.word)))
+      return ((mips_zero_extend (( 64 :: int)::ii) w__2  ::  64 Word.word)))
     else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))) then
-      return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word))
+      return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word))
     else if (((b__146 = (vec_of_bits [B1,B1,B1,B0,B1]  ::  5 Word.word)))) then
       (read_reg CP0UserLocal_ref  :: ( 64 Word.word) M)
     else (SignalException ResI  :: ( 64 Word.word) M)) \<bind> (\<lambda> (temp :: 64 bits) . 
    wGPR rt temp)))))))))))"
 
 
-(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*)
-
-definition execute_PREF  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> unit "  where 
-     " execute_PREF base op1 imm = ( ()  )"
-
-
 (*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
 
 definition execute_ORI  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_ORI rs rt imm = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
+   wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
 
 
 (*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5803,17 +5933,19 @@ definition execute_MULTU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
       return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                  ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                 ::  64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . 
    write_reg
      HI_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)) \<then>
    write_reg
      LO_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word))))))"
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word))))))"
 
 
 (*val execute_MULT : mword ty5 -> mword ty5 -> M unit*)
@@ -5824,17 +5956,19 @@ definition execute_MULT  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
       return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                  ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                 ::  64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . 
    write_reg
      HI_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)) \<then>
    write_reg
      LO_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word))))))"
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word))))))"
 
 
 (*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -5844,16 +5978,16 @@ definition execute_MUL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (let (result :: 64 bits) =
-     ((sign_extend1 (( 64 :: int)::ii)
+     ((mips_sign_extend (( 64 :: int)::ii)
         ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
             ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
            ::  64 Word.word))
        ::  64 Word.word)) in
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
-      return ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+      return ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                 ::  64 Word.word))) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
    wGPR rd w__1)))))"
 
@@ -5877,204 +6011,93 @@ definition execute_MTHI  :: "(5)Word.word \<Rightarrow>((register_value),(unit),
 definition execute_MTC0  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_MTC0 rt rd sel double = (
    (checkCP0Access ()  \<then>
-   (rGPR rt  :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val .  
-  (case  (rd, sel) of
-        (b__108, b__109) =>
-  if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and>
-          (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-    write_reg TLBIndex_ref
-      ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) else
-    if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and>
-            (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-      return ()  else
-      if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))
-              \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-        set_TLBEntryLoReg TLBEntryLo0_ref reg_val else
-        if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word))))
-                \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-          set_TLBEntryLoReg TLBEntryLo1_ref reg_val else
-          if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))))
-                  \<and>
-                  (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-            set_ContextReg_PTEBase TLBContext_ref
-              ((subrange_vec_dec reg_val (( 63 :: int):: ii)
-                  (( 23 :: int):: ii) :: 41 Word.word)) else
-            if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))))
-                    \<and>
-                    (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then
-              write_reg CP0UserLocal_ref reg_val else
-              if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word))))
-                      \<and>
-                      (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                write_reg TLBPageMask_ref
-                  ((subrange_vec_dec reg_val (( 28 :: int):: ii)
-                      (( 13 :: int):: ii) :: 16 Word.word)) else
-                if ((((((b__108 =
-                           (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word))))
-                        \<and>
-                        (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                  write_reg TLBWired_ref
-                    ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word))
-                    \<then> write_reg TLBRandom_ref TLBIndexMax else
-                  if ((((((b__108 =
-                             (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word))))
-                          \<and>
-                          (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                    write_reg CP0HWREna_ref
-                      ((concat_vec
-                          ((subrange_vec_dec reg_val (( 31 :: int):: ii)
-                              (( 29 :: int):: ii) :: 3 Word.word))
-                          ((concat_vec
-                              (vec_of_bits
-                                 [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0] :: 25 Word.word)
-                              ((subrange_vec_dec reg_val (( 3 :: int):: ii)
-                                  (( 0 :: int):: ii) :: 4 Word.word))
-                           :: 29 Word.word)) :: 32 Word.word)) else
-                    if ((((((b__108 =
-                               (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))))
-                            \<and>
-                            (((b__109 =
-                                 (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                      return ()  else
-                      if ((((((b__108 =
-                                 (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word))))
-                              \<and>
-                              (((b__109 =
-                                   (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                        write_reg CP0Count_ref
-                          ((subrange_vec_dec reg_val (( 31 :: int):: ii)
-                              (( 0 :: int):: ii) :: 32 Word.word)) else
-                        if ((((((b__108 =
-                                   (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word))))
-                                \<and>
-                                (((b__109 =
-                                     (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                          (set_TLBEntryHiReg_R TLBEntryHi_ref
-                             ((subrange_vec_dec reg_val (( 63 :: int):: ii)
-                                 (( 62 :: int):: ii) :: 2 Word.word)) \<then>
-                             set_TLBEntryHiReg_VPN2 TLBEntryHi_ref
-                               ((subrange_vec_dec reg_val (( 39 :: int):: ii)
-                                   (( 13 :: int):: ii) :: 27 Word.word)))
-                            \<then>
-                            set_TLBEntryHiReg_ASID TLBEntryHi_ref
-                              ((subrange_vec_dec reg_val (( 7 :: int):: ii)
-                                  (( 0 :: int):: ii) :: 8 Word.word)) else
-                          if ((((((b__108 =
-                                     (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word))))
-                                  \<and>
-                                  (((b__109 =
-                                       (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                            (write_reg CP0Compare_ref
-                               ((subrange_vec_dec reg_val (( 31 :: int):: ii)
-                                   (( 0 :: int):: ii) :: 32 Word.word))
-                               \<then> read_reg CP0Cause_ref) \<bind>
-                              (\<lambda> (w__0 :: CauseReg) . 
-                               set_CauseReg_IP CP0Cause_ref
-                                 ((and_vec
-                                     ((get_CauseReg_IP w__0 :: 8 Word.word))
-                                     (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word)
-                                  :: 8 Word.word))) else
-                            if ((((((b__108 =
-                                       (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))))
-                                    \<and>
-                                    (((b__109 =
-                                         (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                              ((((((((set_StatusReg_CU CP0Status_ref
-                                        ((subrange_vec_dec reg_val
-                                            (( 31 :: int):: ii)
-                                            (( 28 :: int):: ii) :: 4 Word.word))
-                                        \<then>
-                                        set_StatusReg_BEV CP0Status_ref
-                                          ((cast_unit_vec0
-                                              ((access_vec_dec reg_val
-                                                  (( 22 :: int):: ii))) :: 1 Word.word)))
-                                       \<then>
-                                       set_StatusReg_IM CP0Status_ref
-                                         ((subrange_vec_dec reg_val
-                                             (( 15 :: int):: ii)
-                                             (( 8 :: int):: ii) :: 8 Word.word)))
-                                      \<then>
-                                      set_StatusReg_KX CP0Status_ref
-                                        ((cast_unit_vec0
-                                            ((access_vec_dec reg_val
-                                                (( 7 :: int):: ii))) :: 1 Word.word)))
-                                     \<then>
-                                     set_StatusReg_SX CP0Status_ref
-                                       ((cast_unit_vec0
-                                           ((access_vec_dec reg_val
-                                               (( 6 :: int):: ii))) :: 1 Word.word)))
-                                    \<then>
-                                    set_StatusReg_UX CP0Status_ref
-                                      ((cast_unit_vec0
-                                          ((access_vec_dec reg_val
-                                              (( 5 :: int):: ii))) :: 1 Word.word)))
-                                   \<then>
-                                   set_StatusReg_KSU CP0Status_ref
-                                     ((subrange_vec_dec reg_val
-                                         (( 4 :: int):: ii)
-                                         (( 3 :: int):: ii) :: 2 Word.word)))
-                                  \<then>
-                                  set_StatusReg_ERL CP0Status_ref
-                                    ((cast_unit_vec0
-                                        ((access_vec_dec reg_val
-                                            (( 2 :: int):: ii))) :: 1 Word.word)))
-                                 \<then>
-                                 set_StatusReg_EXL CP0Status_ref
-                                   ((cast_unit_vec0
-                                       ((access_vec_dec reg_val
-                                           (( 1 :: int):: ii))) :: 1 Word.word)))
-                                \<then>
-                                set_StatusReg_IE CP0Status_ref
-                                  ((cast_unit_vec0
-                                      ((access_vec_dec reg_val
-                                          (( 0 :: int):: ii))) :: 1 Word.word))
-                            else
-                              if ((((((b__108 =
-                                         (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word))))
-                                      \<and>
-                                      (((b__109 =
-                                           (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                (set_CauseReg_IV CP0Cause_ref
-                                   ((cast_unit_vec0
-                                       ((access_vec_dec reg_val
-                                           (( 23 :: int):: ii))) :: 1 Word.word))
-                                   \<then> read_reg CP0Cause_ref) \<bind>
-                                  (\<lambda> (w__1 :: CauseReg) . 
-                                   (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in
-                                   set_CauseReg_IP CP0Cause_ref
-                                     ((concat_vec
-                                         ((subrange_vec_dec ip
-                                             (( 7 :: int):: ii)
-                                             (( 2 :: int):: ii) :: 6 Word.word))
-                                         ((subrange_vec_dec reg_val
-                                             (( 9 :: int):: ii)
-                                             (( 8 :: int):: ii) :: 2 Word.word))
-                                      :: 8 Word.word)))) else
-                                if ((((((b__108 =
-                                           (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word))))
-                                        \<and>
-                                        (((b__109 =
-                                             (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                  write_reg CP0EPC_ref reg_val else
-                                  if ((((((b__108 =
-                                             (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))))
-                                          \<and>
-                                          (((b__109 =
-                                               (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                    return ()  else
-                                    if ((((((b__108 =
-                                               (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word))))
-                                            \<and>
-                                            (((b__109 =
-                                                 (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                      set_XContextReg_XPTEBase
-                                        TLBXContext_ref
-                                        ((subrange_vec_dec reg_val
-                                            (( 63 :: int):: ii)
-                                            (( 33 :: int):: ii) :: 31 Word.word))
-                                    else write_reg CP0ErrorEPC_ref reg_val
-  )))"
+   (rGPR rt  :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . 
+   (case  (rd, sel) of
+     (b__108, b__109) =>
+      if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg TLBIndex_ref ((mask0 (( 6 :: int)::ii) reg_val  ::  6 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        return () 
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        set_ContextReg_PTEBase TLBContext_ref
+          ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 23 :: int)::ii)  ::  41 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) then
+        write_reg CP0UserLocal_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 :: int)::ii) (( 13 :: int)::ii)  ::  16 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B1,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg TLBWired_ref ((mask0 (( 6 :: int)::ii) reg_val  ::  6 Word.word)) \<then>
+        write_reg TLBRandom_ref TLBIndexMax
+      else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B1,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg
+          CP0HWREna_ref
+          ((concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 29 :: int)::ii)  ::  3 Word.word))
+              ((concat_vec
+                  (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                                B0,B0]
+                    ::  25 Word.word) ((subrange_vec_dec reg_val (( 3 :: int)::ii) (( 0 :: int)::ii)  ::  4 Word.word))
+                 ::  29 Word.word))
+             ::  32 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        return () 
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B0,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg CP0Count_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B1,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (set_TLBEntryHiReg_R TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 62 :: int)::ii)  ::  2 Word.word)) \<then>
+        set_TLBEntryHiReg_VPN2 TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 13 :: int)::ii)  ::  27 Word.word))) \<then>
+        set_TLBEntryHiReg_ASID TLBEntryHi_ref
+          ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B1,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (write_reg CP0Compare_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) \<then>
+        read_reg CP0Cause_ref) \<bind> (\<lambda> (w__0 :: CauseReg) . 
+        set_CauseReg_IP CP0Cause_ref
+          ((and_vec ((get_CauseReg_IP w__0  ::  8 Word.word))
+              (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1]  ::  8 Word.word)
+             ::  8 Word.word)))
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        ((((((((set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 28 :: int)::ii)  ::  4 Word.word)) \<then>
+        set_StatusReg_BEV CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 :: int)::ii)))  ::  1 Word.word))) \<then>
+        set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word))) \<then>
+        set_StatusReg_KX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 :: int)::ii)))  ::  1 Word.word))) \<then>
+        set_StatusReg_SX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 :: int)::ii)))  ::  1 Word.word))) \<then>
+        set_StatusReg_UX CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 :: int)::ii)))  ::  1 Word.word))) \<then>
+        set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word))) \<then>
+        set_StatusReg_ERL CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 :: int)::ii)))  ::  1 Word.word))) \<then>
+        set_StatusReg_EXL CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 :: int)::ii)))  ::  1 Word.word))) \<then>
+        set_StatusReg_IE CP0Status_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 :: int)::ii)))  ::  1 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B0,B1]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (set_CauseReg_IV CP0Cause_ref
+          ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 :: int)::ii)))  ::  1 Word.word)) \<then>
+        read_reg CP0Cause_ref) \<bind> (\<lambda> (w__1 :: CauseReg) . 
+        (let ip = ((get_CauseReg_IP w__1  ::  8 Word.word)) in
+        set_CauseReg_IP CP0Cause_ref
+          ((concat_vec ((subrange_vec_dec ip (( 7 :: int)::ii) (( 2 :: int)::ii)  ::  6 Word.word))
+              ((subrange_vec_dec reg_val (( 9 :: int)::ii) (( 8 :: int)::ii)  ::  2 Word.word))
+             ::  8 Word.word))))
+      else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B1,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg CP0EPC_ref reg_val
+      else if ((((((b__108 = (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        set_XContextReg_XPTEBase TLBXContext_ref
+          ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 33 :: int)::ii)  ::  31 Word.word))
+      else if ((((((b__108 = (vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        write_reg CP0ErrorEPC_ref reg_val
+      else SignalException ResI
+   )))"
 
 
 (*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*)
@@ -6085,7 +6108,7 @@ definition execute_MSUBU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
       return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                  ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
@@ -6100,10 +6123,12 @@ definition execute_MSUBU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
        ::  64 Word.word)) in
    write_reg
      HI_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)) \<then>
    write_reg
      LO_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)))))))))"
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)))))))))"
 
 
 (*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*)
@@ -6114,7 +6139,7 @@ definition execute_MSUB  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
       return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                  ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
@@ -6129,10 +6154,12 @@ definition execute_MSUB  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
        ::  64 Word.word)) in
    write_reg
      HI_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)) \<then>
    write_reg
      LO_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)))))))))"
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)))))))))"
 
 
 (*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -6179,483 +6206,184 @@ definition execute_MFHI  :: "(5)Word.word \<Rightarrow>((register_value),(unit),
 
 definition execute_MFC0  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_MFC0 rt rd sel double = (
-   (checkCP0Access ()  \<then>  
-  (case  (rd, sel) of
-        (b__48, b__49) =>
-  if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and>
-          (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-    (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind>
-      (\<lambda> (w__0 :: TLBIndexT) . 
-       (let (idx :: 31 bits) = ((zero_extend1 (( 31 :: int):: ii) w__0 :: 31 Word.word)) in
-       (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind>
-         (\<lambda> (w__1 :: 1 bits) . 
-          return
-            ((concat_vec
-                (vec_of_bits
-                   [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                   B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 32 Word.word)
-                ((concat_vec w__1 idx :: 32 Word.word)) :: 64 Word.word)))))
-  else
-    if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and>
-            (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-      (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind>
-        (\<lambda> (w__2 :: TLBIndexT) . 
-         return ((zero_extend1 (( 64 :: int):: ii) w__2 :: 64 Word.word)))
-    else
-      if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))
-              \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-        read_reg TLBEntryLo0_ref \<bind>
-          (\<lambda> (w__3 :: TLBEntryLoReg) . 
-           return ((get_TLBEntryLoReg w__3 :: 64 Word.word))) else
-        if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word))))
-                \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-          read_reg TLBEntryLo1_ref \<bind>
-            (\<lambda> (w__4 :: TLBEntryLoReg) . 
-             return ((get_TLBEntryLoReg w__4 :: 64 Word.word))) else
-          if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))))
-                  \<and>
-                  (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-            read_reg TLBContext_ref \<bind>
-              (\<lambda> (w__5 :: ContextReg) . 
-               return ((get_ContextReg w__5 :: 64 Word.word))) else
-            if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))))
-                    \<and>
-                    (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then
-              (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else
-              if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word))))
-                      \<and>
-                      (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind>
-                  (\<lambda> (w__7 :: 16 bits) . 
-                   return
-                     ((zero_extend1 (( 64 :: int):: ii)
-                         ((concat_vec w__7
-                             (vec_of_bits
-                                [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
-                          :: 28 Word.word)) :: 64 Word.word))) else
-                if ((((((b__48 =
-                           (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word))))
-                        \<and>
-                        (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                  (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind>
-                    (\<lambda> (w__8 :: TLBIndexT) . 
-                     return
-                       ((zero_extend1 (( 64 :: int):: ii) w__8 :: 64 Word.word)))
-                else
-                  if ((((((b__48 =
-                             (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word))))
-                          \<and>
-                          (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                    (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind>
-                      (\<lambda> (w__9 :: 32 bits) . 
-                       return
-                         ((zero_extend1 (( 64 :: int):: ii) w__9 :: 64 Word.word)))
-                  else
-                    if ((((((b__48 =
-                               (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))))
-                            \<and>
-                            (((b__49 =
-                                 (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                      (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) else
-                      if ((((((b__48 =
-                                 (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))))
-                              \<and>
-                              (((b__49 =
-                                   (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then
-                        return
-                          ((zero_extend1 (( 64 :: int):: ii)
-                              (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))
-                      else
-                        if ((((((b__48 =
-                                   (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word))))
-                                \<and>
-                                (((b__49 =
-                                     (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                          (read_reg CP0Count_ref :: ( 32 Word.word) M)
-                            \<bind>
-                            (\<lambda> (w__11 :: 32 bits) . 
-                             return
-                               ((zero_extend1 (( 64 :: int):: ii) w__11 :: 64 Word.word)))
-                        else
-                          if ((((((b__48 =
-                                     (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word))))
-                                  \<and>
-                                  (((b__49 =
-                                       (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                            read_reg TLBEntryHi_ref \<bind>
-                              (\<lambda> (w__12 :: TLBEntryHiReg) . 
-                               return
-                                 ((get_TLBEntryHiReg w__12 :: 64 Word.word)))
-                          else
-                            if ((((((b__48 =
-                                       (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word))))
-                                    \<and>
-                                    (((b__49 =
-                                         (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                              (read_reg CP0Compare_ref :: ( 32 Word.word) M)
-                                \<bind>
-                                (\<lambda> (w__13 :: 32 bits) . 
-                                 return
-                                   ((zero_extend1 (( 64 :: int):: ii) w__13 :: 64 Word.word)))
-                            else
-                              if ((((((b__48 =
-                                         (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))))
-                                      \<and>
-                                      (((b__49 =
-                                           (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                read_reg CP0Status_ref \<bind>
-                                  (\<lambda> (w__14 :: StatusReg) . 
-                                   return
-                                     ((zero_extend1 (( 64 :: int):: ii)
-                                         ((get_StatusReg w__14 :: 32 Word.word)) :: 64 Word.word)))
-                              else
-                                if ((((((b__48 =
-                                           (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word))))
-                                        \<and>
-                                        (((b__49 =
-                                             (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                  read_reg CP0Cause_ref \<bind>
-                                    (\<lambda> (w__15 :: CauseReg) . 
-                                     return
-                                       ((zero_extend1 (( 64 :: int):: ii)
-                                           ((get_CauseReg w__15 :: 32 Word.word)) :: 64 Word.word)))
-                                else
-                                  if ((((((b__48 =
-                                             (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word))))
-                                          \<and>
-                                          (((b__49 =
-                                               (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                    (read_reg CP0EPC_ref :: ( 64 Word.word) M)
-                                  else
-                                    if ((((((b__48 =
-                                               (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word))))
-                                            \<and>
-                                            (((b__49 =
-                                                 (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then
-                                      return
-                                        ((zero_extend1 (( 64 :: int):: ii)
-                                            (vec_of_bits
-                                               [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
-                                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                                            :: 32 Word.word) :: 64 Word.word))
-                                    else
-                                      if ((((((b__48 =
-                                                 (vec_of_bits
-                                                    [B0,B1,B1,B1,B1] :: 5 Word.word))))
-                                              \<and>
-                                              (((b__49 =
-                                                   (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then
-                                        return
-                                          ((zero_extend1 (( 64 :: int):: ii)
-                                              (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))
-                                      else
-                                        if ((((((b__48 =
-                                                   (vec_of_bits
-                                                      [B0,B1,B1,B1,B1] :: 5 Word.word))))
-                                                \<and>
-                                                (((b__49 =
-                                                     (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then
-                                          return
-                                            ((zero_extend1
-                                                (( 64 :: int):: ii)
-                                                (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))
-                                        else
-                                          if ((((((b__48 =
-                                                     (vec_of_bits
-                                                        [B1,B0,B0,B0,B0] :: 5 Word.word))))
-                                                  \<and>
-                                                  (((b__49 =
-                                                       (vec_of_bits
-                                                          [B0,B0,B0] :: 3 Word.word))))))) then
-                                            return
-                                              ((zero_extend1
-                                                  (( 64 :: int):: ii)
-                                                  ((concat_vec
-                                                      (vec_of_bits [B1] :: 1 Word.word)
-                                                      ((concat_vec
-                                                          (vec_of_bits
-                                                             [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word)
-                                                          ((concat_vec
-                                                              (vec_of_bits
-                                                                 [B1] :: 1 Word.word)
-                                                              ((concat_vec
-                                                                  (vec_of_bits
-                                                                    [B1,B0] :: 2 Word.word)
-                                                                  ((concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B1] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    :: 7 Word.word))
-                                                                    :: 10 Word.word))
-                                                                   :: 13 Word.word))
-                                                               :: 15 Word.word))
-                                                           :: 16 Word.word))
-                                                       :: 31 Word.word))
-                                                   :: 32 Word.word))
-                                               :: 64 Word.word)) else
-                                            if ((((((b__48 =
-                                                       (vec_of_bits
-                                                          [B1,B0,B0,B0,B0] :: 5 Word.word))))
-                                                    \<and>
-                                                    (((b__49 =
-                                                         (vec_of_bits
-                                                            [B0,B0,B1] :: 3 Word.word))))))) then
-                                              return
-                                                ((zero_extend1
-                                                    (( 64 :: int):: ii)
-                                                    ((concat_vec
-                                                        (vec_of_bits [B1] :: 1 Word.word)
-                                                        ((concat_vec
-                                                            TLBIndexMax
-                                                            ((concat_vec
-                                                                (vec_of_bits
-                                                                   [B0,B0,B0] :: 3 Word.word)
-                                                                ((concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    (
-                                                                    bool_to_bits
-                                                                    have_cp2 :: 1 Word.word))
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0] :: 1 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0] :: 1 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0] :: 1 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0]
-                                                                    :: 1 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0]
-                                                                    :: 1 Word.word)
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0]
-                                                                    :: 1 Word.word)
-                                                                    :: 2 Word.word))
-                                                                    :: 3 Word.word))
-                                                                    :: 4 Word.word))
-                                                                    :: 5 Word.word))
-                                                                    :: 6 Word.word))
-                                                                    :: 7 Word.word))
-                                                                    :: 10 Word.word))
-                                                                    :: 13 Word.word))
-                                                                    :: 16 Word.word))
-                                                                    :: 19 Word.word))
-                                                                 :: 22 Word.word))
-                                                             :: 25 Word.word))
-                                                         :: 31 Word.word))
-                                                     :: 32 Word.word))
-                                                 :: 64 Word.word)) else
-                                              if ((((((b__48 =
-                                                         (vec_of_bits
-                                                            [B1,B0,B0,B0,B0] :: 5 Word.word))))
-                                                      \<and>
-                                                      (((b__49 =
-                                                           (vec_of_bits
-                                                              [B0,B1,B0] :: 3 Word.word))))))) then
-                                                return
-                                                  ((zero_extend1
-                                                      (( 64 :: int):: ii)
-                                                      ((concat_vec
-                                                          (vec_of_bits [B1] :: 1 Word.word)
-                                                          ((concat_vec
-                                                              (vec_of_bits
-                                                                 [B0,B0,B0] :: 3 Word.word)
-                                                              ((concat_vec
-                                                                  (vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                  ((concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    (
-                                                                    (
-                                                                    concat_vec
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0,B0] :: 4 Word.word)
-                                                                    :: 8 Word.word))
-                                                                    :: 12 Word.word))
-                                                                    :: 16 Word.word))
-                                                                    :: 20 Word.word))
-                                                                   :: 24 Word.word))
-                                                               :: 28 Word.word))
-                                                           :: 31 Word.word))
-                                                       :: 32 Word.word))
-                                                   :: 64 Word.word)) else
-                                                if ((((((b__48 =
-                                                           (vec_of_bits
-                                                              [B1,B0,B0,B0,B0] :: 5 Word.word))))
-                                                        \<and>
-                                                        (((b__49 =
-                                                             (vec_of_bits
-                                                                [B0,B1,B1] :: 3 Word.word))))))) then
-                                                  return
-                                                    (vec_of_bits
-                                                       [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                                       B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                                                    :: 64 Word.word) else
-                                                  if ((((((b__48 =
-                                                             (vec_of_bits
-                                                                [B1,B0,B0,B0,B0] :: 5 Word.word))))
-                                                          \<and>
-                                                          (((b__49 =
-                                                               (vec_of_bits
-                                                                  [B1,B0,B1] :: 3 Word.word))))))) then
-                                                    return
-                                                      (vec_of_bits
-                                                         [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                                         B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                                         B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                                                      :: 64 Word.word) else
-                                                    if ((((((b__48 =
-                                                               (vec_of_bits
-                                                                  [B1,B0,B0,B0,B1] :: 5 Word.word))))
-                                                            \<and>
-                                                            (((b__49 =
-                                                                 (vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word))))))) then
-                                                      (read_reg CP0LLAddr_ref :: ( 64 Word.word) M)
-                                                    else
-                                                      if ((((((b__48 =
-                                                                 (vec_of_bits
-                                                                    [B1,B0,B0,B1,B0] :: 5 Word.word))))
-                                                              \<and>
-                                                              (((b__49 =
-                                                                   (vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word))))))) then
-                                                        return
-                                                          ((zero_extend1
-                                                              (( 64 :: int):: ii)
-                                                              (vec_of_bits
-                                                                 [B0] :: 1 Word.word) :: 64 Word.word))
-                                                      else
-                                                        if ((((((b__48 =
-                                                                   (vec_of_bits
-                                                                    [B1,B0,B0,B1,B1] :: 5 Word.word))))
-                                                                \<and>
-                                                                (((b__49 =
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word))))))) then
-                                                          return
-                                                            ((zero_extend1
-                                                                (( 64 :: int):: ii)
-                                                                (vec_of_bits
-                                                                   [B0] :: 1 Word.word) :: 64 Word.word))
-                                                        else
-                                                          if ((((((b__48 =
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B1,B0,B1,B0,B0] :: 5 Word.word))))
-                                                                  \<and>
-                                                                  (((
-                                                                    b__49 =
-                                                                    (
-                                                                    vec_of_bits
-                                                                    [B0,B0,B0] :: 3 Word.word))))))) then
-                                                            read_reg
-                                                              TLBXContext_ref
-                                                              \<bind>
-                                                              (\<lambda> (w__18 :: XContextReg) . 
-                                                               return
-                                                                 ((get_XContextReg
-                                                                    w__18 :: 64 Word.word)))
-                                                          else
-                                                            (read_reg
-                                                               CP0ErrorEPC_ref :: ( 64 Word.word) M)
-  )) \<bind> (\<lambda> (result :: 64 bits) . 
+   (checkCP0Access ()  \<then>
+   (case  (rd, sel) of
+     (b__48, b__49) =>
+      if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg TLBIndex_ref  :: ( 6 Word.word) M) \<bind> (\<lambda> (w__0 :: TLBIndexT) . 
+        (let (idx :: 31 bits) = ((mips_zero_extend (( 31 :: int)::ii) w__0  ::  31 Word.word)) in
+        (read_reg TLBProbe_ref  :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . 
+        return ((concat_vec
+                   (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                     ::  32 Word.word) ((concat_vec w__1 idx  ::  32 Word.word))
+                  ::  64 Word.word)))))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg TLBRandom_ref  :: ( 6 Word.word) M) \<bind> (\<lambda> (w__2 :: TLBIndexT) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) w__2  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg TLBEntryLo0_ref \<bind> (\<lambda> (w__3 :: TLBEntryLoReg) . 
+        return ((get_TLBEntryLoReg_bits w__3  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg TLBEntryLo1_ref \<bind> (\<lambda> (w__4 :: TLBEntryLoReg) . 
+        return ((get_TLBEntryLoReg_bits w__4  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg TLBContext_ref \<bind> (\<lambda> (w__5 :: ContextReg) . 
+        return ((get_ContextReg_bits w__5  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0UserLocal_ref  :: ( 64 Word.word) M)
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg TLBPageMask_ref  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 bits) . 
+        return ((mips_zero_extend (( 64 :: int)::ii)
+                   ((concat_vec w__7
+                       (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)
+                      ::  28 Word.word))
+                  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B1,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg TLBWired_ref  :: ( 6 Word.word) M) \<bind> (\<lambda> (w__8 :: TLBIndexT) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) w__8  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0HWREna_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) w__9  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0BadVAddr_ref  :: ( 64 Word.word) M)
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0Count_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 bits) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) w__11  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B1,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg TLBEntryHi_ref \<bind> (\<lambda> (w__12 :: TLBEntryHiReg) . 
+        return ((get_TLBEntryHiReg_bits w__12  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0Compare_ref  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) w__13  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg CP0Status_ref \<bind> (\<lambda> (w__14 :: StatusReg) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) ((get_StatusReg_bits w__14  ::  32 Word.word))  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B0,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg CP0Cause_ref \<bind> (\<lambda> (w__15 :: CauseReg) . 
+        return ((mips_zero_extend (( 64 :: int)::ii) ((get_CauseReg_bits w__15  ::  32 Word.word))  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0EPC_ref  :: ( 64 Word.word) M)
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii)
+                   (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
+                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                     ::  32 Word.word)
+                  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B1,B1]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0ConfigK0_ref  :: ( 3 Word.word) M) \<bind> (\<lambda> (w__17 :: 3 bits) . 
+        return ((mips_zero_extend (( 64 :: int)::ii)
+                   ((concat_vec (vec_of_bits [B1]  ::  1 Word.word)
+                       ((concat_vec
+                           (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  15 Word.word)
+                           ((concat_vec (vec_of_bits [B1]  ::  1 Word.word)
+                               ((concat_vec (vec_of_bits [B1,B0]  ::  2 Word.word)
+                                   ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                                       ((concat_vec (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+                                           ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                               w__17
+                                              ::  7 Word.word))
+                                          ::  10 Word.word))
+                                      ::  13 Word.word))
+                                  ::  15 Word.word))
+                              ::  16 Word.word))
+                          ::  31 Word.word))
+                      ::  32 Word.word))
+                  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii)
+                   ((concat_vec (vec_of_bits [B1]  ::  1 Word.word)
+                       ((concat_vec TLBIndexMax
+                           ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                               ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                                   ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                                       ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                                           ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                                               ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                                                   ((concat_vec
+                                                       ((bool_to_bits have_cp2  ::  1 Word.word))
+                                                       ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                                                           ((concat_vec
+                                                               (vec_of_bits [B0]  ::  1 Word.word)
+                                                               ((concat_vec
+                                                                   (vec_of_bits [B0]  ::  1 Word.word)
+                                                                   ((concat_vec
+                                                                       (vec_of_bits [B0]
+                                                                         ::  1 Word.word)
+                                                                       ((concat_vec
+                                                                           (vec_of_bits [B0]
+                                                                             ::  1 Word.word)
+                                                                           (vec_of_bits [B0]
+                                                                             ::  1 Word.word)
+                                                                          ::  2 Word.word))
+                                                                      ::  3 Word.word))
+                                                                  ::  4 Word.word))
+                                                              ::  5 Word.word))
+                                                          ::  6 Word.word))
+                                                      ::  7 Word.word))
+                                                  ::  10 Word.word))
+                                              ::  13 Word.word))
+                                          ::  16 Word.word))
+                                      ::  19 Word.word))
+                                  ::  22 Word.word))
+                              ::  25 Word.word))
+                          ::  31 Word.word))
+                      ::  32 Word.word))
+                  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii)
+                   ((concat_vec (vec_of_bits [B1]  ::  1 Word.word)
+                       ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                           ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                               ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                   ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                       ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                           ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                               ((concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                                   (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+                                                  ::  8 Word.word))
+                                              ::  12 Word.word))
+                                          ::  16 Word.word))
+                                      ::  20 Word.word))
+                                  ::  24 Word.word))
+                              ::  28 Word.word))
+                          ::  31 Word.word))
+                      ::  32 Word.word))
+                  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B1]  ::  3 Word.word))))))) then
+        return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                             B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                             B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                 ::  64 Word.word)
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) then
+        return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                             B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                             B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                 ::  64 Word.word)
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0LLAddr_ref  :: ( 64 Word.word) M)
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B1,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B1,B1]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))
+      else if ((((((b__48 = (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        read_reg TLBXContext_ref \<bind> (\<lambda> (w__19 :: XContextReg) . 
+        return ((get_XContextReg_bits w__19  ::  64 Word.word)))
+      else if ((((((b__48 = (vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) then
+        (read_reg CP0ErrorEPC_ref  :: ( 64 Word.word) M)
+      else (SignalException ResI  :: ( 64 Word.word) M)
+   )) \<bind> (\<lambda> (result :: 64 bits) . 
    wGPR rt
      (if double then result
       else
-        (sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word))))"
+        (mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+          ::  64 Word.word))))"
 
 
 (*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*)
@@ -6666,7 +6394,7 @@ definition execute_MADDU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
       return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                  ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
@@ -6681,10 +6409,12 @@ definition execute_MADDU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
        ::  64 Word.word)) in
    write_reg
      HI_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)) \<then>
    write_reg
      LO_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)))))))))"
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)))))))))"
 
 
 (*val execute_MADD : mword ty5 -> mword ty5 -> M unit*)
@@ -6695,7 +6425,7 @@ definition execute_MADD  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . 
    (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)
     else
       return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                  ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
@@ -6710,10 +6440,12 @@ definition execute_MADD  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
        ::  64 Word.word)) in
    write_reg
      HI_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)) \<then>
    write_reg
      LO_ref
-     ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)))))))))"
+     ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+        ::  64 Word.word)))))))))"
 
 
 (*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
@@ -6721,8 +6453,8 @@ definition execute_MADD  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
 definition execute_Load  :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_Load width sign linked base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData
-      width
+   (addrWrapper ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word))
+      LoadData width
      :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . 
    if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr
    else
@@ -6731,33 +6463,28 @@ definition execute_Load  :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<R
         (write_reg CP0LLBit_ref (vec_of_bits [B1]  ::  1 Word.word) \<then>
         write_reg CP0LLAddr_ref pAddr) \<then>
         (case  width of
-          B =>
-           (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 ::  8 Word.word) . 
+          W =>
+           (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 ::  32 Word.word) . 
            return ((extendLoad w__1 sign  ::  64 Word.word)))
-        | H =>
-           (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 ::  16 Word.word) . 
-           return ((extendLoad w__2 sign  ::  64 Word.word)))
-        | W =>
-           (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
-           return ((extendLoad w__3 sign  ::  64 Word.word)))
         | D =>
-           (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 ::  64 Word.word) . 
-           return ((extendLoad w__4 sign  ::  64 Word.word)))
+           (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
+           return ((extendLoad w__2 sign  ::  64 Word.word)))
+        | _ => throw (Error_internal_error () )
         )
       else
         (case  width of
           B =>
-           (MEMr_wrapper pAddr (( 1 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__6 ::  8 Word.word) . 
-           return ((extendLoad w__6 sign  ::  64 Word.word)))
+           (MEMr_wrapper (( 8 :: int)::ii) pAddr (( 1 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__5 ::  8 Word.word) . 
+           return ((extendLoad w__5 sign  ::  64 Word.word)))
         | H =>
-           (MEMr_wrapper pAddr (( 2 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 ::  16 Word.word) . 
-           return ((extendLoad w__7 sign  ::  64 Word.word)))
+           (MEMr_wrapper (( 16 :: int)::ii) pAddr (( 2 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 ::  16 Word.word) . 
+           return ((extendLoad w__6 sign  ::  64 Word.word)))
         | W =>
-           (MEMr_wrapper pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 ::  32 Word.word) . 
-           return ((extendLoad w__8 sign  ::  64 Word.word)))
+           (MEMr_wrapper (( 32 :: int)::ii) pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 ::  32 Word.word) . 
+           return ((extendLoad w__7 sign  ::  64 Word.word)))
         | D =>
-           (MEMr_wrapper pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 ::  64 Word.word) . 
-           return ((extendLoad w__9 sign  ::  64 Word.word)))
+           (MEMr_wrapper (( 64 :: int)::ii) pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 ::  64 Word.word) . 
+           return ((extendLoad w__8 sign  ::  64 Word.word)))
         )) \<bind> (\<lambda> (memResult :: 64 bits) . 
      wGPR rt memResult)))))"
 
@@ -6767,11 +6494,11 @@ definition execute_Load  :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<R
 definition execute_LWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_LWR base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData
-      W
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData WR
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
    (TLBTranslate vAddr LoadData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
-   (MEMr_wrapper
+   (MEMr_wrapper (( 32 :: int)::ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii)  ::  62 Word.word))
           (vec_of_bits [B0,B0]  ::  2 Word.word)
          ::  64 Word.word)) (( 4 :: int)::ii)
@@ -6792,7 +6519,7 @@ definition execute_LWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
           ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 8 :: int)::ii)  ::  24 Word.word))
          ::  32 Word.word)
      else mem_val) in
-   wGPR rt ((sign_extend1 (( 64 :: int)::ii) result  ::  64 Word.word))))))))))"
+   wGPR rt ((mips_sign_extend (( 64 :: int)::ii) result  ::  64 Word.word))))))))))"
 
 
 (*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
@@ -6800,11 +6527,11 @@ definition execute_LWR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 definition execute_LWL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_LWL base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData
-      W
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData WL
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
    (TLBTranslate vAddr LoadData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
-   (MEMr_wrapper
+   (MEMr_wrapper (( 32 :: int)::ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii)  ::  62 Word.word))
           (vec_of_bits [B0,B0]  ::  2 Word.word)
          ::  64 Word.word)) (( 4 :: int)::ii)
@@ -6825,7 +6552,7 @@ definition execute_LWL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
        (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
           ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii)  ::  24 Word.word))
          ::  32 Word.word)) in
-   wGPR rt ((sign_extend1 (( 64 :: int)::ii) result  ::  64 Word.word))))))))))"
+   wGPR rt ((mips_sign_extend (( 64 :: int)::ii) result  ::  64 Word.word))))))))))"
 
 
 (*val execute_LUI : mword ty5 -> mword ty16 -> M unit*)
@@ -6833,7 +6560,7 @@ definition execute_LWL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 definition execute_LUI  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_LUI rt imm = (
    wGPR rt
-     ((sign_extend1 (( 64 :: int)::ii)
+     ((mips_sign_extend (( 64 :: int)::ii)
          ((concat_vec imm
              (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)
             ::  32 Word.word))
@@ -6845,11 +6572,11 @@ definition execute_LUI  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow
 definition execute_LDR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_LDR base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData
-      D
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData DR
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
-   (TLBTranslate vAddr StoreData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
-   (MEMr_wrapper
+   (TLBTranslate vAddr LoadData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
+   (MEMr_wrapper (( 64 :: int)::ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii)  ::  61 Word.word))
           (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
          ::  64 Word.word)) (( 8 :: int)::ii)
@@ -6893,11 +6620,11 @@ definition execute_LDR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
 definition execute_LDL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_LDL base rt offset = (
    (rGPR base  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData
-      D
+   (addrWrapperUnaligned
+      ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset  ::  64 Word.word)) w__0  ::  64 Word.word)) LoadData DL
      :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . 
-   (TLBTranslate vAddr StoreData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
-   (MEMr_wrapper
+   (TLBTranslate vAddr LoadData  :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . 
+   (MEMr_wrapper (( 64 :: int)::ii)
       ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii)  ::  61 Word.word))
           (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
          ::  64 Word.word)) (( 8 :: int)::ii)
@@ -6978,22 +6705,16 @@ definition execute_J  :: "(26)Word.word \<Rightarrow>((register_value),(unit),(e
         ::  64 Word.word))))"
 
 
-(*val execute_ImplementationDefinedStopFetching : unit -> unit*)
-
-definition execute_ImplementationDefinedStopFetching  :: " unit \<Rightarrow> unit "  where 
-     " execute_ImplementationDefinedStopFetching g__118 = ( ()  )"
-
-
 (*val execute_HCF : unit -> unit*)
 
 definition execute_HCF  :: " unit \<Rightarrow> unit "  where 
-     " execute_HCF g__123 = ( ()  )"
+     " execute_HCF g__21 = ( ()  )"
 
 
 (*val execute_ERET : unit -> M unit*)
 
 definition execute_ERET  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_ERET g__128 = (
+     " execute_ERET g__26 = (
    (((checkCP0Access ()  \<then>
    ERETHook () ) \<then>
    write_reg CP0LLBit_ref (vec_of_bits [B0]  ::  1 Word.word)) \<then>
@@ -7022,7 +6743,8 @@ definition execute_DSUB  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
    (let (temp65 :: 65 bits) =
-     ((sub_vec ((sign_extend1 (( 65 :: int)::ii) w__0  ::  65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1  ::  65 Word.word))
+     ((sub_vec ((mips_sign_extend (( 65 :: int)::ii) w__0  ::  65 Word.word))
+        ((mips_sign_extend (( 65 :: int)::ii) w__1  ::  65 Word.word))
        ::  65 Word.word)) in
    if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 :: int)::ii)))))
           ((bit_to_bool ((access_vec_dec temp65 (( 63 :: int)::ii))))))) then
@@ -7037,7 +6759,7 @@ definition execute_DSRLV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word)) in
-   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)))))"
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)))))"
 
 
 (*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7046,7 +6768,7 @@ definition execute_DSRL32  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
      " execute_DSRL32 rt rd sa = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
    (let sa32 = ((concat_vec (vec_of_bits [B1]  ::  1 Word.word) sa  ::  6 Word.word)) in
-   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0))))"
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0))))"
 
 
 (*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7054,7 +6776,7 @@ definition execute_DSRL32  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
 definition execute_DSRL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_DSRL rt rd sa = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
-   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)))"
+   (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)))"
 
 
 (*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7065,7 +6787,7 @@ definition execute_DSRAV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word)) in
    (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)))))"
 
 
 (*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7075,7 +6797,7 @@ definition execute_DSRA32  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
    (let sa32 = ((concat_vec (vec_of_bits [B1]  ::  1 Word.word) sa  ::  6 Word.word)) in
    (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0))))"
 
 
 (*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7084,7 +6806,7 @@ definition execute_DSRA  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
      " execute_DSRA rt rd sa = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> temp . 
    (shift_bits_right_arith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)))"
 
 
 (*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7093,7 +6815,7 @@ definition execute_DSLLV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
      " execute_DSLLV rs rt rd = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::
       64 Word.word) . 
    wGPR rd w__2))))"
 
@@ -7103,7 +6825,7 @@ definition execute_DSLLV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
 definition execute_DSLL32  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_DSLL32 rt rd sa = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1]  ::  1 Word.word) sa  ::  6 Word.word))
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1]  ::  1 Word.word) sa  ::  6 Word.word))
      :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
    wGPR rd w__1)))"
 
@@ -7113,7 +6835,7 @@ definition execute_DSLL32  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
 definition execute_DSLL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_DSLL rt rd sa = (
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)))"
+   (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) .  wGPR rd w__1)))"
 
 
 (*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*)
@@ -7149,9 +6871,9 @@ definition execute_DIVU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
                      ::  64 Word.word)))))))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
       return (w__0, w__1)))
     else
       (let si = (Word.uint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))) in
@@ -7160,8 +6882,8 @@ definition execute_DIVU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
       (let ri = (hardware_mod si ti) in
       return ((to_bits ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) qi  ::  32 Word.word),
               (to_bits ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) ri  ::  32 Word.word))))))) \<bind> (\<lambda> varstup .  (let (q, r) = varstup in
-   write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r  ::  64 Word.word)) \<then>
-   write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q  ::  64 Word.word)))))))"
+   write_reg HI_ref ((mips_sign_extend (( 64 :: int)::ii) r  ::  64 Word.word)) \<then>
+   write_reg LO_ref ((mips_sign_extend (( 64 :: int)::ii) q  ::  64 Word.word)))))))"
 
 
 (*val execute_DIV : mword ty5 -> mword ty5 -> M unit*)
@@ -7175,9 +6897,9 @@ definition execute_DIV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
                      ::  64 Word.word)))))))))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . 
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . 
       return (w__0, w__1)))
     else
       (let si = (Word.sint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))) in
@@ -7186,8 +6908,8 @@ definition execute_DIV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
       (let ri = (si - ((ti * qi))) in
       return ((to_bits ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) qi  ::  32 Word.word),
               (to_bits ((make_the_value (( 32 :: int)::ii)  ::  32 itself)) ri  ::  32 Word.word))))))) \<bind> (\<lambda> varstup .  (let (q, r) = varstup in
-   write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r  ::  64 Word.word)) \<then>
-   write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q  ::  64 Word.word)))))))"
+   write_reg HI_ref ((mips_sign_extend (( 64 :: int)::ii) r  ::  64 Word.word)) \<then>
+   write_reg LO_ref ((mips_sign_extend (( 64 :: int)::ii) q  ::  64 Word.word)))))))"
 
 
 (*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*)
@@ -7200,9 +6922,9 @@ definition execute_DDIVU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (let rtVal = (Word.uint w__1) in
    (if (((rtVal = (( 0 :: int)::ii)))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
       return (w__2, w__3)))
     else
       (let qi = (hardware_quot rsVal rtVal) in
@@ -7222,9 +6944,9 @@ definition execute_DDIV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (let rtVal = (Word.sint w__1) in
    (if (((rtVal = (( 0 :: int)::ii)))) then
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . 
       (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . 
       return (w__2, w__3)))
     else
       (let qi = (hardware_quot rsVal rtVal) in
@@ -7248,7 +6970,7 @@ definition execute_DADDU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
 definition execute_DADDIU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_DADDIU rs rt imm = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
+   wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
 
 
 (*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*)
@@ -7257,7 +6979,8 @@ definition execute_DADDI  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
      " execute_DADDI rs rt imm = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let (sum65 :: 65 bits) =
-     ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0  ::  65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) imm  ::  65 Word.word))
+     ((add_vec ((mips_sign_extend (( 65 :: int)::ii) w__0  ::  65 Word.word))
+        ((mips_sign_extend (( 65 :: int)::ii) imm  ::  65 Word.word))
        ::  65 Word.word)) in
    if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii)))))
           ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then
@@ -7272,7 +6995,8 @@ definition execute_DADD  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
    (let (sum65 :: 65 bits) =
-     ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0  ::  65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1  ::  65 Word.word))
+     ((add_vec ((mips_sign_extend (( 65 :: int)::ii) w__0  ::  65 Word.word))
+        ((mips_sign_extend (( 65 :: int)::ii) w__1  ::  65 Word.word))
        ::  65 Word.word)) in
    if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii)))))
           ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then
@@ -7308,7 +7032,10 @@ definition execute_ClearRegs  :: " ClearRegSet \<Rightarrow>(16)Word.word \<Righ
               ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) ((i + (( 16 :: int)::ii)))
                  ::  5 Word.word)) ((zeros0 (( 64 :: int)::ii) ()   ::  64 Word.word))
          | CLo =>
-            writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) i  ::  5 Word.word)) null_cap
+            if (((i = (( 0 :: int)::ii)))) then write_reg DDC_ref ((capStructToCapReg null_cap  ::  257 Word.word))
+            else
+              writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) i  ::  5 Word.word))
+                null_cap
          | CHi =>
             writeCapReg
               ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) ((i + (( 16 :: int)::ii)))
@@ -7322,15 +7049,15 @@ definition execute_ClearRegs  :: " ClearRegSet \<Rightarrow>(16)Word.word \<Righ
 definition execute_CWriteHwr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CWriteHwr cb sel = (
    checkCP2usable ()  \<then>
-   ((let l__24 = (Word.uint sel) in
-   (if (((l__24 = (( 0 :: int)::ii)))) then return (False, False)
-    else if (((l__24 = (( 1 :: int)::ii)))) then return (False, False)
-    else if (((l__24 = (( 8 :: int)::ii)))) then return (False, True)
-    else if (((l__24 = (( 22 :: int)::ii)))) then return (True, False)
-    else if (((l__24 = (( 23 :: int)::ii)))) then return (True, False)
-    else if (((l__24 = (( 29 :: int)::ii)))) then return (True, True)
-    else if (((l__24 = (( 30 :: int)::ii)))) then return (True, True)
-    else if (((l__24 = (( 31 :: int)::ii)))) then return (True, True)
+   ((let p00 = (Word.uint sel) in
+   (if (((p00 = (( 0 :: int)::ii)))) then return (False, False)
+    else if (((p00 = (( 1 :: int)::ii)))) then return (False, False)
+    else if (((p00 = (( 8 :: int)::ii)))) then return (False, True)
+    else if (((p00 = (( 22 :: int)::ii)))) then return (True, False)
+    else if (((p00 = (( 23 :: int)::ii)))) then return (True, False)
+    else if (((p00 = (( 29 :: int)::ii)))) then return (True, True)
+    else if (((p00 = (( 30 :: int)::ii)))) then return (True, True)
+    else if (((p00 = (( 31 :: int)::ii)))) then return (True, True)
     else SignalException ResI) \<bind> (\<lambda> varstup .  (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in
    register_inaccessible cb \<bind> (\<lambda> (w__8 :: bool) . 
    if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
@@ -7346,17 +7073,22 @@ definition execute_CWriteHwr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Right
        if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel
        else
          readCapReg cb \<bind> (\<lambda> capVal . 
-         (let l__16 = (Word.uint sel) in
-         if (((l__16 = (( 0 :: int)::ii)))) then writeCapReg DDC capVal
-         else if (((l__16 = (( 1 :: int)::ii)))) then
+         (let p00 = (Word.uint sel) in
+         if (((p00 = (( 0 :: int)::ii)))) then write_reg DDC_ref ((capStructToCapReg capVal  ::  257 Word.word))
+         else if (((p00 = (( 1 :: int)::ii)))) then
            write_reg CTLSU_ref ((capStructToCapReg capVal  ::  257 Word.word))
-         else if (((l__16 = (( 8 :: int)::ii)))) then
+         else if (((p00 = (( 8 :: int)::ii)))) then
            write_reg CTLSP_ref ((capStructToCapReg capVal  ::  257 Word.word))
-         else if (((l__16 = (( 22 :: int)::ii)))) then writeCapReg KR1C capVal
-         else if (((l__16 = (( 23 :: int)::ii)))) then writeCapReg KR2C capVal
-         else if (((l__16 = (( 29 :: int)::ii)))) then writeCapReg KCC capVal
-         else if (((l__16 = (( 30 :: int)::ii)))) then writeCapReg KDC capVal
-         else if (((l__16 = (( 31 :: int)::ii)))) then writeCapReg EPCC capVal
+         else if (((p00 = (( 22 :: int)::ii)))) then
+           write_reg KR1C_ref ((capStructToCapReg capVal  ::  257 Word.word))
+         else if (((p00 = (( 23 :: int)::ii)))) then
+           write_reg KR2C_ref ((capStructToCapReg capVal  ::  257 Word.word))
+         else if (((p00 = (( 29 :: int)::ii)))) then
+           write_reg KCC_ref ((capStructToCapReg capVal  ::  257 Word.word))
+         else if (((p00 = (( 30 :: int)::ii)))) then
+           write_reg KDC_ref ((capStructToCapReg capVal  ::  257 Word.word))
+         else if (((p00 = (( 31 :: int)::ii)))) then
+           write_reg EPCC_ref ((capStructToCapReg capVal  ::  257 Word.word))
          else assert_exp False (''should be unreachable code'')))))))))))"
 
 
@@ -7400,7 +7132,7 @@ definition execute_CUnseal  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar
 definition execute_CToPtr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CToPtr rd cb ct = (
    (checkCP2usable ()  \<then>
-   readCapReg ct) \<bind> (\<lambda> ct_val . 
+   readCapRegDDC ct) \<bind> (\<lambda> ct_val . 
    readCapReg cb \<bind> (\<lambda> cb_val . 
    register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
@@ -7429,7 +7161,7 @@ definition execute_CToPtr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
 definition execute_CTestSubset  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CTestSubset rd cb ct = (
    (checkCP2usable ()  \<then>
-   readCapReg cb) \<bind> (\<lambda> cb_val . 
+   readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
    readCapReg ct \<bind> (\<lambda> ct_val . 
    (let ct_top = (getCapTop ct_val) in
    (let ct_base = (getCapBase ct_val) in
@@ -7451,7 +7183,7 @@ definition execute_CTestSubset  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rig
          else if (((((and_vec ct_perms cb_perms  ::  31 Word.word)) \<noteq> ct_perms))) then
            (vec_of_bits [B0]  ::  1 Word.word)
          else (vec_of_bits [B1]  ::  1 Word.word)) in
-       wGPR rd ((zero_extend1 (( 64 :: int)::ii) result  ::  64 Word.word))))))))))))))"
+       wGPR rd ((mips_zero_extend (( 64 :: int)::ii) result  ::  64 Word.word))))))))))))))"
 
 
 (*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -7478,7 +7210,7 @@ definition execute_CSub  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
 definition execute_CStore  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CStore rs cb rt rd offset width conditional = (
    (checkCP2usable ()  \<then>
-   readCapReg cb) \<bind> (\<lambda> cb_val . 
+   readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
    register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
    else if ((\<not>(CapStruct_tag   cb_val))) then raise_c2_exception CapEx_TagViolation cb
@@ -7490,8 +7222,8 @@ definition execute_CStore  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
      (let cursor = (getCapCursor cb_val) in
      (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
      (let vAddr =
-       (hardware_mod
-         ((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset))))))
+       (((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset))))))
+         mod
          ((pow2 (( 64 :: int)::ii)))) in
      (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
      if ((((vAddr + size1)) > ((getCapTop cb_val)))) then
@@ -7517,7 +7249,7 @@ definition execute_CStore  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
             | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rs_val
             )
           else return False) \<bind> (\<lambda> (success :: bool) . 
-         wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success  ::  1 Word.word))  ::  64 Word.word))))
+         wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success  ::  1 Word.word))  ::  64 Word.word))))
        else
          (case  width of
            B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
@@ -7694,7 +7426,7 @@ definition execute_CSC  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
      " execute_CSC cs cb rt rd offset conditional = (
    (checkCP2usable ()  \<then>
    readCapReg cs) \<bind> (\<lambda> cs_val . 
-   readCapReg cb \<bind> (\<lambda> cb_val . 
+   readCapRegDDC cb \<bind> (\<lambda> cb_val . 
    register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
    else
@@ -7712,15 +7444,14 @@ definition execute_CSC  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
        (let cursor = (getCapCursor cb_val) in
        (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
        (let vAddr =
-         (hardware_mod
-           ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset))))))
+         (((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset))))))
+           mod
            ((pow2 (( 64 :: int)::ii)))) in
        (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
        if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then
          raise_c2_exception CapEx_LengthViolation cb
        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
-       else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then
-         SignalExceptionBadAddr AdES vAddr64
+       else if (((((vAddr mod cap_size)) \<noteq> (( 0 :: int)::ii)))) then SignalExceptionBadAddr AdES vAddr64
        else
          (TLBTranslateC vAddr64 StoreData  :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup .  (let (pAddr, noStoreCap) = varstup in
          if ((((CapStruct_tag   cs_val) \<and> noStoreCap))) then
@@ -7731,14 +7462,14 @@ definition execute_CSC  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
               MEMw_tagged_conditional pAddr(CapStruct_tag   cs_val)
                 ((capStructToMemBits cs_val  ::  256 Word.word))
             else return False) \<bind> (\<lambda> success . 
-           wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success  ::  1 Word.word))  ::  64 Word.word))))
+           wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success  ::  1 Word.word))  ::  64 Word.word))))
          else MEMw_tagged pAddr(CapStruct_tag   cs_val) ((capStructToMemBits cs_val  ::  256 Word.word)))))))))))))"
 
 
 (*val execute_CReturn : unit -> M unit*)
 
 definition execute_CReturn  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_CReturn g__129 = ( checkCP2usable ()  \<then> raise_c2_exception_noreg CapEx_ReturnTrap )"
+     " execute_CReturn g__27 = ( checkCP2usable ()  \<then> raise_c2_exception_noreg CapEx_ReturnTrap )"
 
 
 (*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*)
@@ -7746,15 +7477,15 @@ definition execute_CReturn  :: " unit \<Rightarrow>((register_value),(unit),(exc
 definition execute_CReadHwr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CReadHwr cd1 sel = (
    checkCP2usable ()  \<then>
-   ((let l__8 = (Word.uint sel) in
-   (if (((l__8 = (( 0 :: int)::ii)))) then return (False, False)
-    else if (((l__8 = (( 1 :: int)::ii)))) then return (False, False)
-    else if (((l__8 = (( 8 :: int)::ii)))) then return (False, True)
-    else if (((l__8 = (( 22 :: int)::ii)))) then return (True, False)
-    else if (((l__8 = (( 23 :: int)::ii)))) then return (True, False)
-    else if (((l__8 = (( 29 :: int)::ii)))) then return (True, True)
-    else if (((l__8 = (( 30 :: int)::ii)))) then return (True, True)
-    else if (((l__8 = (( 31 :: int)::ii)))) then return (True, True)
+   ((let p00 = (Word.uint sel) in
+   (if (((p00 = (( 0 :: int)::ii)))) then return (False, False)
+    else if (((p00 = (( 1 :: int)::ii)))) then return (False, False)
+    else if (((p00 = (( 8 :: int)::ii)))) then return (False, True)
+    else if (((p00 = (( 22 :: int)::ii)))) then return (True, False)
+    else if (((p00 = (( 23 :: int)::ii)))) then return (True, False)
+    else if (((p00 = (( 29 :: int)::ii)))) then return (True, True)
+    else if (((p00 = (( 30 :: int)::ii)))) then return (True, True)
+    else if (((p00 = (( 31 :: int)::ii)))) then return (True, True)
     else SignalException ResI) \<bind> (\<lambda> varstup .  (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in
    register_inaccessible cd1 \<bind> (\<lambda> (w__8 :: bool) . 
    if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1
@@ -7769,19 +7500,31 @@ definition execute_CReadHwr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta
           return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . 
        if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel
        else
-         (let l__0 = (Word.uint sel) in
-         (if (((l__0 = (( 0 :: int)::ii)))) then readCapReg DDC
-          else if (((l__0 = (( 1 :: int)::ii)))) then
+         (let p00 = (Word.uint sel) in
+         (if (((p00 = (( 0 :: int)::ii)))) then
+            (read_reg DDC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__13 ::  257 Word.word) . 
+            return ((capRegToCapStruct w__13)))
+          else if (((p00 = (( 1 :: int)::ii)))) then
             (read_reg CTLSU_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 ::  257 Word.word) . 
             return ((capRegToCapStruct w__14)))
-          else if (((l__0 = (( 8 :: int)::ii)))) then
+          else if (((p00 = (( 8 :: int)::ii)))) then
             (read_reg CTLSP_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__15 ::  257 Word.word) . 
             return ((capRegToCapStruct w__15)))
-          else if (((l__0 = (( 22 :: int)::ii)))) then readCapReg KR1C
-          else if (((l__0 = (( 23 :: int)::ii)))) then readCapReg KR2C
-          else if (((l__0 = (( 29 :: int)::ii)))) then readCapReg KCC
-          else if (((l__0 = (( 30 :: int)::ii)))) then readCapReg KDC
-          else if (((l__0 = (( 31 :: int)::ii)))) then readCapReg EPCC
+          else if (((p00 = (( 22 :: int)::ii)))) then
+            (read_reg KR1C_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__16 ::  257 Word.word) . 
+            return ((capRegToCapStruct w__16)))
+          else if (((p00 = (( 23 :: int)::ii)))) then
+            (read_reg KR2C_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__17 ::  257 Word.word) . 
+            return ((capRegToCapStruct w__17)))
+          else if (((p00 = (( 29 :: int)::ii)))) then
+            (read_reg KCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__18 ::  257 Word.word) . 
+            return ((capRegToCapStruct w__18)))
+          else if (((p00 = (( 30 :: int)::ii)))) then
+            (read_reg KDC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__19 ::  257 Word.word) . 
+            return ((capRegToCapStruct w__19)))
+          else if (((p00 = (( 31 :: int)::ii)))) then
+            (read_reg EPCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__20 ::  257 Word.word) . 
+            return ((capRegToCapStruct w__20)))
           else assert_exp False (''should be unreachable code'') \<then> undefined_CapStruct () ) \<bind> (\<lambda> (capVal ::
            CapStruct) . 
          writeCapReg cd1 capVal))))))))))"
@@ -7832,7 +7575,7 @@ definition execute_CPtrCmp  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar
          | CEXEQ => (cb_val = ct_val)
          | CNEXEQ => (cb_val \<noteq> ct_val)
          )) in
-       wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits cmp  ::  1 Word.word))  ::  64 Word.word))))))))))))"
+       wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits cmp  ::  1 Word.word))  ::  64 Word.word))))))))))))"
 
 
 (*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
@@ -7864,7 +7607,7 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (case  merge_var of
      (rd, cb, rt, offset, signext, B, linked) =>
       (checkCP2usable ()  \<then>
-      readCapReg cb) \<bind> (\<lambda> cb_val . 
+      readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
       register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((\<not>(CapStruct_tag   cb_val))) then raise_c2_exception CapEx_TagViolation cb
@@ -7875,8 +7618,8 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
         (let cursor = (getCapCursor cb_val) in
         (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
         (let vAddr =
-          (hardware_mod
-            ((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset))))))
+          (((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset))))))
+            mod
             ((pow2 (( 64 :: int)::ii)))) in
         (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
         if ((((vAddr + (( 1 :: int)::ii))) > ((getCapTop cb_val)))) then
@@ -7891,12 +7634,12 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
              (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii)  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__2 ::  8 Word.word) . 
              return ((extendLoad w__2 signext  ::  64 Word.word)))
            else
-             (MEMr_wrapper pAddr (( 1 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 ::  8 Word.word) . 
+             (MEMr_wrapper (( 8 :: int)::ii) pAddr (( 1 :: int)::ii)  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 ::  8 Word.word) . 
              return ((extendLoad w__3 signext  ::  64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . 
           wGPR rd memResult))))))))
    | (rd, cb, rt, offset, signext, D, linked) =>
       (checkCP2usable ()  \<then>
-      readCapReg cb) \<bind> (\<lambda> cb_val . 
+      readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
       register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((\<not>(CapStruct_tag   cb_val))) then raise_c2_exception CapEx_TagViolation cb
@@ -7907,8 +7650,8 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
         (let cursor = (getCapCursor cb_val) in
         (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
         (let vAddr =
-          (hardware_mod
-            ((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset))))))
+          (((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset))))))
+            mod
             ((pow2 (( 64 :: int)::ii)))) in
         (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
         if ((((vAddr + (( 8 :: int)::ii))) > ((getCapTop cb_val)))) then
@@ -7923,12 +7666,12 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
              (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
              return ((extendLoad w__2 signext  ::  64 Word.word)))
            else
-             (MEMr_wrapper pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 ::  64 Word.word) . 
+             (MEMr_wrapper (( 64 :: int)::ii) pAddr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 ::  64 Word.word) . 
              return ((extendLoad w__3 signext  ::  64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . 
           wGPR rd memResult))))))))
    | (rd, cb, rt, offset, signext, H, linked) =>
       (checkCP2usable ()  \<then>
-      readCapReg cb) \<bind> (\<lambda> cb_val . 
+      readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
       register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((\<not>(CapStruct_tag   cb_val))) then raise_c2_exception CapEx_TagViolation cb
@@ -7939,8 +7682,8 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
         (let cursor = (getCapCursor cb_val) in
         (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
         (let vAddr =
-          (hardware_mod
-            ((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset))))))
+          (((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset))))))
+            mod
             ((pow2 (( 64 :: int)::ii)))) in
         (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
         if ((((vAddr + (( 2 :: int)::ii))) > ((getCapTop cb_val)))) then
@@ -7955,12 +7698,12 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
              (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii)  :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__2 ::  16 Word.word) . 
              return ((extendLoad w__2 signext  ::  64 Word.word)))
            else
-             (MEMr_wrapper pAddr (( 2 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 ::  16 Word.word) . 
+             (MEMr_wrapper (( 16 :: int)::ii) pAddr (( 2 :: int)::ii)  :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 ::  16 Word.word) . 
              return ((extendLoad w__3 signext  ::  64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . 
           wGPR rd memResult))))))))
    | (rd, cb, rt, offset, signext, W, linked) =>
       (checkCP2usable ()  \<then>
-      readCapReg cb) \<bind> (\<lambda> cb_val . 
+      readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
       register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . 
       if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
       else if ((\<not>(CapStruct_tag   cb_val))) then raise_c2_exception CapEx_TagViolation cb
@@ -7971,8 +7714,8 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
         (let cursor = (getCapCursor cb_val) in
         (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
         (let vAddr =
-          (hardware_mod
-            ((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset))))))
+          (((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset))))))
+            mod
             ((pow2 (( 64 :: int)::ii)))) in
         (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
         if ((((vAddr + (( 4 :: int)::ii))) > ((getCapTop cb_val)))) then
@@ -7987,18 +7730,18 @@ definition execute_CLoad  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
              (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 ::  32 Word.word) . 
              return ((extendLoad w__2 signext  ::  64 Word.word)))
            else
-             (MEMr_wrapper pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
+             (MEMr_wrapper (( 32 :: int)::ii) pAddr (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 ::  32 Word.word) . 
              return ((extendLoad w__3 signext  ::  64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . 
           wGPR rd memResult))))))))
    )))"
 
 
-(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*)
+(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty16 -> bool -> M unit*)
 
-definition execute_CLC  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+definition execute_CLC  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CLC cd1 cb rt offset linked = (
    (checkCP2usable ()  \<then>
-   readCapReg cb) \<bind> (\<lambda> cb_val . 
+   readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
    register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1
    else
@@ -8012,15 +7755,14 @@ definition execute_CLC  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
        (let cursor = (getCapCursor cb_val) in
        (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
        (let vAddr =
-         (hardware_mod
-           ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset))))))
+         (((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset))))))
+           mod
            ((pow2 (( 64 :: int)::ii)))) in
        (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) vAddr  ::  64 Word.word)) in
        if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then
          raise_c2_exception CapEx_LengthViolation cb
        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
-       else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then
-         SignalExceptionBadAddr AdEL vAddr64
+       else if (((((vAddr mod cap_size)) \<noteq> (( 0 :: int)::ii)))) then SignalExceptionBadAddr AdEL vAddr64
        else
          (TLBTranslateC vAddr64 LoadData  :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup .  (let (pAddr, suppressTag) = varstup in
          (let cd1 = (Word.uint cd1) in
@@ -8065,7 +7807,7 @@ definition execute_CJALR  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
      else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb
      else if ((((cb_ptr + (( 4 :: int)::ii))) > cb_top)) then
        raise_c2_exception CapEx_LengthViolation cb
-     else if (((((hardware_mod cb_ptr (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL
+     else if (((((cb_ptr mod (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL
      else
        (if link then
           (read_reg PCC_ref  :: ( 257 Word.word) M) \<bind> (\<lambda> (w__3 ::  257 Word.word) . 
@@ -8084,7 +7826,7 @@ definition execute_CIncOffsetImmediate  :: "(5)Word.word \<Rightarrow>(5)Word.wo
      " execute_CIncOffsetImmediate cd1 cb imm = (
    (checkCP2usable ()  \<then>
    readCapReg cb) \<bind> (\<lambda> cb_val . 
-   (let (imm64 :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word)) in
+   (let (imm64 :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm  ::  64 Word.word)) in
    register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1
    else
@@ -8144,7 +7886,8 @@ definition execute_CGetType  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta
    else
      readCapReg cb \<bind> (\<lambda> capVal . 
      wGPR rd
-       (if(CapStruct_sealed   capVal) then (zero_extend1 (( 64 :: int)::ii)(CapStruct_otype   capVal)  ::  64 Word.word)
+       (if(CapStruct_sealed   capVal) then
+          (mips_zero_extend (( 64 :: int)::ii)(CapStruct_otype   capVal)  ::  64 Word.word)
         else (replicate_bits ((cast_unit_vec0 B1  ::  1 Word.word)) (( 64 :: int)::ii)  ::  64 Word.word)))))"
 
 
@@ -8158,7 +7901,7 @@ definition execute_CGetTag  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar
    else
      readCapReg cb \<bind> (\<lambda> capVal . 
      wGPR rd
-       ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag   capVal)  ::  1 Word.word))  ::  64 Word.word)))))"
+       ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag   capVal)  ::  1 Word.word))  ::  64 Word.word)))))"
 
 
 (*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*)
@@ -8171,7 +7914,8 @@ definition execute_CGetSealed  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righ
    else
      readCapReg cb \<bind> (\<lambda> capVal . 
      wGPR rd
-       ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed   capVal)  ::  1 Word.word))  ::  64 Word.word)))))"
+       ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed   capVal)  ::  1 Word.word))
+          ::  64 Word.word)))))"
 
 
 (*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*)
@@ -8183,7 +7927,7 @@ definition execute_CGetPerm  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
    else
      readCapReg cb \<bind> (\<lambda> capVal . 
-     wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms capVal  ::  31 Word.word))  ::  64 Word.word)))))"
+     wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((getCapPerms capVal  ::  31 Word.word))  ::  64 Word.word)))))"
 
 
 (*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*)
@@ -8256,7 +8000,7 @@ definition execute_CGetCause  :: "(5)Word.word \<Rightarrow>((register_value),(u
    if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation
    else
      read_reg CapCause_ref \<bind> (\<lambda> (w__1 :: CapCauseReg) . 
-     wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((get_CapCauseReg w__1  ::  16 Word.word))  ::  64 Word.word)))))"
+     wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((get_CapCauseReg_bits w__1  ::  16 Word.word))  ::  64 Word.word)))))"
 
 
 (*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*)
@@ -8290,14 +8034,18 @@ definition execute_CGetAddr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta
 definition execute_CFromPtr  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CFromPtr cd1 cb rt = (
    (checkCP2usable ()  \<then>
-   readCapReg cb) \<bind> (\<lambda> cb_val . 
+   readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . 
    register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1
    else
      register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . 
      if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
-     else if (((rt = (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))) then writeCapReg cd1 null_cap
+     else if (((rt_val = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+                   ::  64 Word.word)))) then
+       writeCapReg cd1 null_cap
      else if ((\<not>(CapStruct_tag   cb_val))) then raise_c2_exception CapEx_TagViolation cb
      else if(CapStruct_sealed   cb_val) then raise_c2_exception CapEx_SealViolation cb
      else
@@ -8387,7 +8135,7 @@ definition execute_CCheckPerm  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righ
    (checkCP2usable ()  \<then>
    readCapReg cs) \<bind> (\<lambda> cs_val . 
    (let (cs_perms :: 64 bits) =
-     ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms cs_val  ::  31 Word.word))  ::  64 Word.word)) in
+     ((mips_zero_extend (( 64 :: int)::ii) ((getCapPerms cs_val  ::  31 Word.word))  ::  64 Word.word)) in
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> rt_perms . 
    register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . 
    if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
@@ -8509,7 +8257,7 @@ definition execute_CCSeal  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr
 definition execute_CBuildCap  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_CBuildCap cd1 cb ct = (
    (checkCP2usable ()  \<then>
-   readCapReg cb) \<bind> (\<lambda> cb_val . 
+   readCapRegDDC cb) \<bind> (\<lambda> cb_val . 
    readCapReg ct \<bind> (\<lambda> ct_val . 
    (let cb_base = (getCapBase cb_val) in
    (let ct_base = (getCapBase ct_val) in
@@ -8560,7 +8308,7 @@ definition execute_CBZ  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow
                ::  1 Word.word)))) then
        (let (offset :: 64 bits) =
          ((add_vec_int
-            ((sign_extend1 (( 64 :: int)::ii)
+            ((mips_sign_extend (( 64 :: int)::ii)
                 ((concat_vec imm (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  18 Word.word))
                ::  64 Word.word)) (( 4 :: int)::ii)
            ::  64 Word.word)) in
@@ -8584,7 +8332,7 @@ definition execute_CBX  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow
                ::  1 Word.word)))) then
        (let (offset :: 64 bits) =
          ((add_vec_int
-            ((sign_extend1 (( 64 :: int)::ii)
+            ((mips_sign_extend (( 64 :: int)::ii)
                 ((concat_vec imm (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  18 Word.word))
                ::  64 Word.word)) (( 4 :: int)::ii)
            ::  64 Word.word)) in
@@ -8630,7 +8378,7 @@ definition execute_C2Dump  :: "(5)Word.word \<Rightarrow> unit "  where
 (*val execute_BREAK : unit -> M unit*)
 
 definition execute_BREAK  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_BREAK g__120 = ( SignalException Bp )"
+     " execute_BREAK g__18 = ( SignalException Bp )"
 
 
 (*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*)
@@ -8645,7 +8393,8 @@ definition execute_BEQ  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
              ::  1 Word.word)))) then
      (let (offset :: 64 bits) =
        ((add_vec_int
-          ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  18 Word.word))
+          ((mips_sign_extend (( 64 :: int)::ii)
+              ((concat_vec imm (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  18 Word.word))
              ::  64 Word.word)) (( 4 :: int)::ii)
          ::  64 Word.word)) in
      (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
@@ -8664,11 +8413,12 @@ definition execute_BCMPZ  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarr
    (let linkVal = ((add_vec_int w__0 (( 8 :: int)::ii)  ::  64 Word.word)) in
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> regVal . 
    (let condition =
-     (compare cmp regVal ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) in
+     (compare cmp regVal ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) in
    (if condition then
       (let (offset :: 64 bits) =
         ((add_vec_int
-           ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  18 Word.word))
+           ((mips_sign_extend (( 64 :: int)::ii)
+               ((concat_vec imm (vec_of_bits [B0,B0]  ::  2 Word.word)  ::  18 Word.word))
               ::  64 Word.word)) (( 4 :: int)::ii)
           ::  64 Word.word)) in
       (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
@@ -8686,7 +8436,7 @@ definition execute_BCMPZ  :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarr
 definition execute_ANDI  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " execute_ANDI rs rt imm = (
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
+   wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word))))"
 
 
 (*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -8706,10 +8456,10 @@ definition execute_ADDU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> opB . 
    if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
    else
      wGPR rd
-       ((sign_extend1 (( 64 :: int)::ii)
+       ((mips_sign_extend (( 64 :: int)::ii)
            ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
                ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
               ::  32 Word.word))
@@ -8723,12 +8473,12 @@ definition execute_ADDIU  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> opA . 
    if ((NotWordVal opA)) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rt w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rt w__0)
    else
      wGPR rt
-       ((sign_extend1 (( 64 :: int)::ii)
+       ((mips_sign_extend (( 64 :: int)::ii)
            ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
-               ((sign_extend1 (( 32 :: int)::ii) imm  ::  32 Word.word))
+               ((mips_sign_extend (( 32 :: int)::ii) imm  ::  32 Word.word))
               ::  32 Word.word))
           ::  64 Word.word))))"
 
@@ -8740,19 +8490,20 @@ definition execute_ADDI  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
    (rGPR rs  :: ( 64 Word.word) M) \<bind> (\<lambda> opA . 
    if ((NotWordVal opA)) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rt w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rt w__0)
    else
      (let (sum33 :: 33 bits) =
        ((add_vec
-          ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  33 Word.word))
-          ((sign_extend1 (( 33 :: int)::ii) imm  ::  33 Word.word))
+          ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+             ::  33 Word.word)) ((mips_sign_extend (( 33 :: int)::ii) imm  ::  33 Word.word))
          ::  33 Word.word)) in
      if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii)))))
             ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then
        SignalException Ov
      else
        wGPR rt
-         ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)))))"
+         ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+            ::  64 Word.word)))))"
 
 
 (*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
@@ -8763,19 +8514,22 @@ definition execute_ADD  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>
    (rGPR rt  :: ( 64 Word.word) M) \<bind> (\<lambda> (opB :: 64 bits) . 
    if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then
      (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) .  wGPR rd w__0)
    else
      (let (sum33 :: 33 bits) =
        ((add_vec
-          ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  33 Word.word))
-          ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  33 Word.word))
+          ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+             ::  33 Word.word))
+          ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+             ::  33 Word.word))
          ::  33 Word.word)) in
      if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii)))))
             ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then
        SignalException Ov
      else
        wGPR rd
-         ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word))))))"
+         ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+            ::  64 Word.word))))))"
 
 
 fun execute  :: " ast \<Rightarrow>((register_value),(unit),(exception))monad "  where 
@@ -8843,12 +8597,9 @@ fun execute  :: " ast \<Rightarrow>((register_value),(unit),(exception))monad "
 |" execute (JALR (rs,rd)) = ( execute_JALR rs rd )"
 |" execute (BEQ (rs,rd,imm,ne,likely)) = ( execute_BEQ rs rd imm ne likely )"
 |" execute (BCMPZ (rs,imm,cmp,link,likely)) = ( execute_BCMPZ rs imm cmp link likely )"
-|" execute (SYSCALL_THREAD_START (g__117)) = ( return ((execute_SYSCALL_THREAD_START g__117)))"
-|" execute (ImplementationDefinedStopFetching (g__118)) = (
-      return ((execute_ImplementationDefinedStopFetching g__118)))"
-|" execute (SYSCALL (g__119)) = ( execute_SYSCALL g__119 )"
-|" execute (BREAK (g__120)) = ( execute_BREAK g__120 )"
-|" execute (WAIT (g__121)) = ( execute_WAIT g__121 )"
+|" execute (SYSCALL (g__17)) = ( execute_SYSCALL g__17 )"
+|" execute (BREAK (g__18)) = ( execute_BREAK g__18 )"
+|" execute (WAIT (g__19)) = ( execute_WAIT g__19 )"
 |" execute (TRAPREG (rs,rt,cmp)) = ( execute_TRAPREG rs rt cmp )"
 |" execute (TRAPIMM (rs,imm,cmp)) = ( execute_TRAPIMM rs imm cmp )"
 |" execute (Load (width,sign,linked,base,rt,offset)) = ( execute_Load width sign linked base rt offset )"
@@ -8862,17 +8613,16 @@ fun execute  :: " ast \<Rightarrow>((register_value),(unit),(exception))monad "
 |" execute (SDL (base,rt,offset)) = ( execute_SDL base rt offset )"
 |" execute (SDR (base,rt,offset)) = ( execute_SDR base rt offset )"
 |" execute (CACHE (base,op1,imm)) = ( execute_CACHE base op1 imm )"
-|" execute (PREF (base,op1,imm)) = ( return ((execute_PREF base op1 imm)))"
-|" execute (SYNC (g__122)) = ( execute_SYNC g__122 )"
+|" execute (SYNC (g__20)) = ( execute_SYNC g__20 )"
 |" execute (MFC0 (rt,rd,sel,double)) = ( execute_MFC0 rt rd sel double )"
-|" execute (HCF (g__123)) = ( return ((execute_HCF g__123)))"
+|" execute (HCF (g__21)) = ( return ((execute_HCF g__21)))"
 |" execute (MTC0 (rt,rd,sel,double)) = ( execute_MTC0 rt rd sel double )"
-|" execute (TLBWI (g__124)) = ( execute_TLBWI g__124 )"
-|" execute (TLBWR (g__125)) = ( execute_TLBWR g__125 )"
-|" execute (TLBR (g__126)) = ( execute_TLBR g__126 )"
-|" execute (TLBP (g__127)) = ( execute_TLBP g__127 )"
+|" execute (TLBWI (g__22)) = ( execute_TLBWI g__22 )"
+|" execute (TLBWR (g__23)) = ( execute_TLBWR g__23 )"
+|" execute (TLBR (g__24)) = ( execute_TLBR g__24 )"
+|" execute (TLBP (g__25)) = ( execute_TLBP g__25 )"
 |" execute (RDHWR (rt,rd)) = ( execute_RDHWR rt rd )"
-|" execute (ERET (g__128)) = ( execute_ERET g__128 )"
+|" execute (ERET (g__26)) = ( execute_ERET g__26 )"
 |" execute (CGetPerm (rd,cb)) = ( execute_CGetPerm rd cb )"
 |" execute (CGetType (rd,cb)) = ( execute_CGetType rd cb )"
 |" execute (CGetBase (rd,cb)) = ( execute_CGetBase rd cb )"
@@ -8910,7 +8660,7 @@ fun execute  :: " ast \<Rightarrow>((register_value),(unit),(exception))monad "
 |" execute (CCSeal (cd1,cs,ct)) = ( execute_CCSeal cd1 cs ct )"
 |" execute (CUnseal (cd1,cs,ct)) = ( execute_CUnseal cd1 cs ct )"
 |" execute (CCall (cs,cb,b__151)) = ( execute_CCall cs cb b__151 )"
-|" execute (CReturn (g__129)) = ( execute_CReturn g__129 )"
+|" execute (CReturn (g__27)) = ( execute_CReturn g__27 )"
 |" execute (CBX (cb,imm,notset)) = ( execute_CBX cb imm notset )"
 |" execute (CBZ (cb,imm,notzero)) = ( execute_CBZ cb imm notzero )"
 |" execute (CJALR (cd1,cb,link)) = ( execute_CJALR cd1 cb link )"
@@ -8921,7 +8671,7 @@ fun execute  :: " ast \<Rightarrow>((register_value),(unit),(exception))monad "
 |" execute (CSC (cs,cb,rt,rd,offset,conditional)) = ( execute_CSC cs cb rt rd offset conditional )"
 |" execute (CLC (cd1,cb,rt,offset,linked)) = ( execute_CLC cd1 cb rt offset linked )"
 |" execute (C2Dump (rt)) = ( return ((execute_C2Dump rt)))"
-|" execute (RI (g__130)) = ( execute_RI g__130 )"
+|" execute (RI (g__28)) = ( execute_RI g__28 )"
 
 
 (*val supported_instructions : ast -> maybe ast*)
@@ -8930,50 +8680,62 @@ definition supported_instructions  :: " ast \<Rightarrow>(ast)option "  where
      " supported_instructions instr = ( Some instr )"
 
 
-(*val fetch_and_execute : unit -> M unit*)
+(*val cycle_limit_reached : unit -> bool*)
 
-definition fetch_and_execute  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " fetch_and_execute _ = (
-   catch_early_return
-     (((whileM () 
-        (\<lambda> unit_var .  return True)
-        (\<lambda> unit_var . 
-          liftR ((read_reg nextPC_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . 
-          (liftR (write_reg PC_ref w__0) \<then>
-          liftR ((read_reg branchPending_ref  :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__1 :: 1 bits) . 
-          ((liftR (write_reg inBranchDelay_ref w__1) \<then>
-          liftR (write_reg branchPending_ref (vec_of_bits [B0]  ::  1 Word.word))) \<then>
-          liftR ((read_reg inBranchDelay_ref  :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__2 ::  1 Word.word) . 
-          (if ((bits_to_bool w__2)) then liftR ((read_reg delayedPC_ref  :: ( 64 Word.word) M))
-           else
-             liftR ((read_reg PC_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 ::  64 Word.word) . 
-             return ((add_vec_int w__4 (( 4 :: int)::ii)  ::  64 Word.word)))) \<bind> (\<lambda> (w__5 ::  64 Word.word) . 
-          ((liftR (write_reg nextPC_ref w__5) \<then>
-          liftR (cp2_next_pc () )) \<then>
-          liftR (read_reg instCount_ref)) \<bind> (\<lambda> (w__6 :: ii) . 
-          (liftR (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii)))) \<then>
-          liftR ((read_reg PC_ref  :: ( 64 Word.word) M))) \<bind> (\<lambda> (w__7 :: 64 bits) . 
-          (let (_ :: unit) = (print_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (''PC: '') w__7) in
-          try_catchR (liftR ((read_reg PC_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 ::  64 Word.word) . 
-                      liftR ((TranslatePC w__8  :: ( 64 Word.word) M)) \<bind> (\<lambda> pc_pa . 
-                      liftR ((MEMr_wrapper pc_pa (( 4 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> instr . 
-                      (let instr_ast = (decode instr) in
-                      (case  instr_ast of
-                        Some ((HCF (_))) =>
-                         (let (_ :: unit) =
-                           (prerr_endline (''simulation stopped due to halt instruction.'')) in
-                         (early_return ()  :: (unit, unit) MR))
-                      | Some (ast) => liftR (execute ast)
-                      | None =>
-                         (let (_ :: unit) = (prerr_endline (''Decode failed'')) in
-                         liftR (exit0 () ))
-                      )))))) (\<lambda>x .  
-  (case  x of   ISAException (_) => return ((prerr_endline (''EXCEPTION''))) ))))))))))) \<then>
-      liftR (skip () )) \<then> liftR (skip () )))"
+definition cycle_limit_reached  :: " unit \<Rightarrow> bool "  where 
+     " cycle_limit_reached _ = ( False )"
 
 
-(*val main : unit -> M unit*)
+(*val fetch_and_execute : unit -> M bool*)
+
+definition fetch_and_execute  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " fetch_and_execute _ = (
+   (read_reg nextPC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
+   (write_reg PC_ref w__0 \<then>
+   (read_reg branchPending_ref  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__1 :: 1 bits) . 
+   ((write_reg inBranchDelay_ref w__1 \<then>
+   write_reg branchPending_ref (vec_of_bits [B0]  ::  1 Word.word)) \<then>
+   (read_reg inBranchDelay_ref  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 ::  1 Word.word) . 
+   (if ((bits_to_bool w__2)) then (read_reg delayedPC_ref  :: ( 64 Word.word) M)
+    else
+      (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 ::  64 Word.word) . 
+      return ((add_vec_int w__4 (( 4 :: int)::ii)  ::  64 Word.word)))) \<bind> (\<lambda> (w__5 ::  64 Word.word) . 
+   ((write_reg nextPC_ref w__5 \<then>
+   cp2_next_pc () ) \<then>
+   read_reg instCount_ref) \<bind> (\<lambda> (w__6 :: ii) . 
+   (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii))) \<then>
+   (read_reg UART_WRITTEN_ref  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__7 ::  1 Word.word) . 
+   (((if ((bits_to_bool w__7)) then
+      (read_reg UART_WDATA_ref  :: ( 8 Word.word) M) \<bind> (\<lambda> (w__8 :: 8 bits) . 
+      (let (_ :: unit) = (putchar ((Word.uint w__8))) in
+      write_reg UART_WRITTEN_ref (vec_of_bits [B0]  ::  1 Word.word)))
+    else return () ) \<then>
+   skip () ) \<then>
+   skip () ) \<then>
+   ((let loop_again = True in
+   try_catch ((read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 ::  64 Word.word) . 
+              (TranslatePC w__9  :: ( 64 Word.word) M) \<bind> (\<lambda> pc_pa . 
+              (MEMr_wrapper (( 32 :: int)::ii) pc_pa (( 4 :: int)::ii)  :: ( 32 Word.word) M) \<bind> (\<lambda> instr . 
+              (let instr_ast = (decode instr) in
+              (case  instr_ast of
+                Some ((HCF (_))) =>
+                 (let (_ :: unit) = (print_endline (''simulation stopped due to halt instruction.'')) in
+                 return False)
+              | Some (ast) => execute ast \<then> return loop_again
+              | None =>
+                 (let (_ :: unit) = (print_endline (''Decode failed'')) in
+                 return False)
+              )))))) (\<lambda>x .  
+  (case  x of   ISAException (_) => return loop_again )) \<bind> (\<lambda> (loop_again :: bool) . 
+   return (((loop_again \<and> ((\<not> ((cycle_limit_reached () )))))))))))))))))"
+
+
+(*val init_registers : mword ty64 -> M unit*)
+
+definition init_registers  :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " init_registers initialPC = (
+   (init_cp0_state ()  \<then> init_cp2_state () ) \<then> write_reg nextPC_ref initialPC )"
+
 
 (*val dump_mips_state : unit -> M unit*)
 
@@ -8981,38 +8743,36 @@ definition dump_mips_state  :: " unit \<Rightarrow>((register_value),(unit),(exc
      " dump_mips_state _ = (
    (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (let (_ :: unit) = (print_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in
    (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () 
      (\<lambda> idx unit_var . 
        (rGPR ((to_bits ((make_the_value (( 5 :: int)::ii)  ::  5 itself)) idx  ::  5 Word.word))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::
           64 Word.word) . 
        return ((let _ =
-         (prerr_endline
+         (print_endline
            (((op@) (''DEBUG MIPS REG '')
                (((op@) ((string_of_int 
-  instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in
+  instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits w__1))))))))) in
        () ))))))))"
 
 
+(*val main : unit -> M unit*)
+
 definition main  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " main _ = (
-   ((init_cp0_state ()  \<then>
-   init_cp2_state () ) \<then>
-   write_reg
-     nextPC_ref
-     ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) ((elf_entry () ))  ::  64 Word.word))) \<then>
+   init_registers
+     ((to_bits ((make_the_value (( 64 :: int)::ii)  ::  64 itself)) ((elf_entry () ))  ::  64 Word.word)) \<then>
    ((let startTime = (get_time_ns () ) in
-   fetch_and_execute ()  \<then>
+   (whileM ()  (\<lambda> unit_var .  fetch_and_execute () ) (\<lambda> unit_var .  return () )) \<then>
    ((let endTime = (get_time_ns () ) in
    (let elapsed = (endTime - startTime) in
-   read_reg instCount_ref \<bind> (\<lambda> (w__0 :: ii) . 
-   (let inst_1e9 = (w__0 * (( 1000000000 :: int)::ii)) in
+   read_reg instCount_ref \<bind> (\<lambda> (w__1 :: ii) . 
+   (let inst_1e9 = (w__1 * (( 1000000000 :: int)::ii)) in
    (let ips = (inst_1e9 div elapsed) in
    ((dump_mips_state ()  \<then>
    dump_cp2_state () ) \<then>
-   read_reg instCount_ref) \<bind> (\<lambda> (w__1 :: ii) . 
-   (let (_ :: unit) = (print_int (''Executed instructions: '') w__1) in
+   read_reg instCount_ref) \<bind> (\<lambda> (w__2 :: ii) . 
+   (let (_ :: unit) = (print_int (''Executed instructions: '') w__2) in
    (let (_ :: unit) = (print_int (''Nanoseconds elapsed: '') elapsed) in
    return ((print_int (''Instructions per second: '') ips))))))))))))))"
 
@@ -9022,19 +8782,19 @@ definition main  :: " unit \<Rightarrow>((register_value),(unit),(exception))mon
 definition initialize_registers  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " initialize_registers _ = (
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . 
    (write_reg PC_ref w__0 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . 
    (write_reg nextPC_ref w__1 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . 
    (write_reg TLBProbe_ref w__2 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii)  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii)  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . 
    (write_reg TLBIndex_ref w__3 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii)  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii)  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . 
    (write_reg TLBRandom_ref w__4 \<then>
    undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__5 :: TLBEntryLoReg) . 
    (write_reg TLBEntryLo0_ref w__5 \<then>
@@ -9043,10 +8803,10 @@ definition initialize_registers  :: " unit \<Rightarrow>((register_value),(unit)
    undefined_ContextReg () ) \<bind> (\<lambda> (w__7 :: ContextReg) . 
    (write_reg TLBContext_ref w__7 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii)  :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . 
    (write_reg TLBPageMask_ref w__8 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii)  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii)  :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . 
    (write_reg TLBWired_ref w__9 \<then>
    undefined_TLBEntryHiReg () ) \<bind> (\<lambda> (w__10 :: TLBEntryHiReg) . 
    (write_reg TLBEntryHi_ref w__10 \<then>
@@ -9181,191 +8941,270 @@ definition initialize_registers  :: " unit \<Rightarrow>((register_value),(unit)
    undefined_TLBEntry () ) \<bind> (\<lambda> (w__75 :: TLBEntry) . 
    (write_reg TLBEntry63_ref w__75 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . 
    (write_reg CP0Compare_ref w__76 \<then>
    undefined_CauseReg () ) \<bind> (\<lambda> (w__77 :: CauseReg) . 
    (write_reg CP0Cause_ref w__77 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . 
    (write_reg CP0EPC_ref w__78 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . 
    (write_reg CP0ErrorEPC_ref w__79 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . 
    (write_reg CP0LLBit_ref w__80 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . 
    (write_reg CP0LLAddr_ref w__81 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . 
    (write_reg CP0BadVAddr_ref w__82 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . 
    (write_reg CP0Count_ref w__83 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii)  :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . 
    (write_reg CP0HWREna_ref w__84 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . 
    (write_reg CP0UserLocal_ref w__85 \<then>
-   undefined_StatusReg () ) \<bind> (\<lambda> (w__86 :: StatusReg) . 
-   (write_reg CP0Status_ref w__86 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__87 :: 1 bits) . 
-   (write_reg branchPending_ref w__87 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii)  :: ( 3 Word.word) M)) \<bind> (\<lambda> (w__86 :: 3 bits) . 
+   (write_reg CP0ConfigK0_ref w__86 \<then>
+   undefined_StatusReg () ) \<bind> (\<lambda> (w__87 :: StatusReg) . 
+   (write_reg CP0Status_ref w__87 \<then>
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . 
+   (write_reg branchPending_ref w__88 \<then>
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__89 :: 1 bits) . 
+   (write_reg inBranchDelay_ref w__89 \<then>
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . 
+   (write_reg delayedPC_ref w__90 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . 
-   (write_reg inBranchDelay_ref w__88 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . 
+   (write_reg HI_ref w__91 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . 
-   (write_reg delayedPC_ref w__89 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 bits) . 
+   (write_reg LO_ref w__92 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . 
-   (write_reg HI_ref w__90 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__93 ::  64 Word.word) . 
+   (undefined_vector (( 32 :: int)::ii) w__93  :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__94 :: ( 64 bits) list) . 
+   (write_reg GPR_ref w__94 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . 
-   (write_reg LO_ref w__91 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__95 :: 8 bits) . 
+   (write_reg UART_WDATA_ref w__95 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii)  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 ::  64 Word.word) . 
-   (undefined_vector (( 32 :: int)::ii) w__92  :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__93 :: ( 64 bits) list) . 
-   (write_reg GPR_ref w__93 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__96 :: 1 bits) . 
+   (write_reg UART_WRITTEN_ref w__96 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__94 :: 8 bits) . 
-   (write_reg UART_WDATA_ref w__94 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__97 :: 8 bits) . 
+   (write_reg UART_RDATA_ref w__97 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__95 :: 1 bits) . 
-   (write_reg UART_WRITTEN_ref w__95 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__98 :: 1 bits) . 
+   (write_reg UART_RVALID_ref w__98 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii)  :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__96 :: 8 bits) . 
-   (write_reg UART_RDATA_ref w__96 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . 
+   (write_reg PCC_ref w__99 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__97 :: 1 bits) . 
-   (write_reg UART_RVALID_ref w__97 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . 
+   (write_reg nextPCC_ref w__100 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__98 :: CapReg) . 
-   (write_reg PCC_ref w__98 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__101 :: CapReg) . 
+   (write_reg delayedPCC_ref w__101 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . 
-   (write_reg nextPCC_ref w__99 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__102 :: 1 bits) . 
+   (write_reg inCCallDelay_ref w__102 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . 
-   (write_reg delayedPCC_ref w__100 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . 
+   (write_reg DDC_ref w__103 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii)  :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__101 :: 1 bits) . 
-   (write_reg inCCallDelay_ref w__101 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . 
+   (write_reg C01_ref w__104 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__102 :: CapReg) . 
-   (write_reg C00_ref w__102 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . 
+   (write_reg C02_ref w__105 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . 
-   (write_reg C01_ref w__103 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . 
+   (write_reg C03_ref w__106 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . 
-   (write_reg C02_ref w__104 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . 
+   (write_reg C04_ref w__107 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . 
-   (write_reg C03_ref w__105 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . 
+   (write_reg C05_ref w__108 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . 
-   (write_reg C04_ref w__106 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . 
+   (write_reg C06_ref w__109 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . 
-   (write_reg C05_ref w__107 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . 
+   (write_reg C07_ref w__110 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . 
-   (write_reg C06_ref w__108 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . 
+   (write_reg C08_ref w__111 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . 
-   (write_reg C07_ref w__109 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . 
+   (write_reg C09_ref w__112 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . 
-   (write_reg C08_ref w__110 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . 
+   (write_reg C10_ref w__113 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . 
-   (write_reg C09_ref w__111 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . 
+   (write_reg C11_ref w__114 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . 
-   (write_reg C10_ref w__112 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . 
+   (write_reg C12_ref w__115 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . 
-   (write_reg C11_ref w__113 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . 
+   (write_reg C13_ref w__116 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . 
-   (write_reg C12_ref w__114 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . 
+   (write_reg C14_ref w__117 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . 
-   (write_reg C13_ref w__115 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . 
+   (write_reg C15_ref w__118 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . 
-   (write_reg C14_ref w__116 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . 
+   (write_reg C16_ref w__119 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . 
-   (write_reg C15_ref w__117 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . 
+   (write_reg C17_ref w__120 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . 
-   (write_reg C16_ref w__118 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . 
+   (write_reg C18_ref w__121 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . 
-   (write_reg C17_ref w__119 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . 
+   (write_reg C19_ref w__122 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . 
-   (write_reg C18_ref w__120 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . 
+   (write_reg C20_ref w__123 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . 
-   (write_reg C19_ref w__121 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . 
+   (write_reg C21_ref w__124 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . 
-   (write_reg C20_ref w__122 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . 
+   (write_reg C22_ref w__125 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . 
-   (write_reg C21_ref w__123 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . 
+   (write_reg C23_ref w__126 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . 
-   (write_reg C22_ref w__124 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . 
+   (write_reg C24_ref w__127 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . 
-   (write_reg C23_ref w__125 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . 
+   (write_reg C25_ref w__128 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . 
-   (write_reg C24_ref w__126 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . 
+   (write_reg C26_ref w__129 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . 
-   (write_reg C25_ref w__127 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . 
+   (write_reg C27_ref w__130 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . 
-   (write_reg C26_ref w__128 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . 
+   (write_reg C28_ref w__131 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . 
-   (write_reg C27_ref w__129 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . 
+   (write_reg C29_ref w__132 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . 
-   (write_reg C28_ref w__130 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . 
+   (write_reg C30_ref w__133 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . 
-   (write_reg C29_ref w__131 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . 
+   (write_reg C31_ref w__134 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . 
-   (write_reg C30_ref w__132 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . 
+   (write_reg CTLSU_ref w__135 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . 
-   (write_reg C31_ref w__133 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__136 :: CapReg) . 
+   (write_reg CTLSP_ref w__136 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . 
-   (write_reg CTLSU_ref w__134 \<then>
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__137 :: CapReg) . 
+   (write_reg KR1C_ref w__137 \<then>
    (undefined_bitvector 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . 
-   (write_reg CTLSP_ref w__135 \<then>
-   undefined_CapCauseReg () ) \<bind> (\<lambda> (w__136 :: CapCauseReg) . 
-   (write_reg CapCause_ref w__136 \<then>
-   undefined_int () ) \<bind> (\<lambda> (w__137 :: ii) .  write_reg instCount_ref w__137)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__138 :: CapReg) . 
+   (write_reg KR2C_ref w__138 \<then>
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__139 :: CapReg) . 
+   (write_reg KCC_ref w__139 \<then>
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__140 :: CapReg) . 
+   (write_reg KDC_ref w__140 \<then>
+   (undefined_bitvector 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii)  :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__141 :: CapReg) . 
+   (write_reg EPCC_ref w__141 \<then>
+   undefined_CapCauseReg () ) \<bind> (\<lambda> (w__142 :: CapCauseReg) . 
+   (write_reg CapCause_ref w__142 \<then>
+   undefined_int () ) \<bind> (\<lambda> (w__143 :: ii) .  write_reg instCount_ref w__143)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))"
 
 
 definition initial_regstate  :: " regstate "  where 
      " initial_regstate = (
   (| instCount = ((( 0 :: int)::ii)), 
      CapCause =
-       (Mk_CapCauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)), 
+       ((| CapCauseReg_CapCauseReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)) |)), 
+     EPCC =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  257 Word.word)), 
+     KDC =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  257 Word.word)), 
+     KCC =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  257 Word.word)), 
+     KR2C =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  257 Word.word)), 
+     KR1C =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  257 Word.word)), 
      CTLSP =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -9762,7 +9601,7 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  257 Word.word)), 
-     C00 =
+     DDC =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -9962,9 +9801,11 @@ definition initial_regstate  :: " regstate "  where
      inBranchDelay = ((vec_of_bits [B0]  ::  1 Word.word)), 
      branchPending = ((vec_of_bits [B0]  ::  1 Word.word)), 
      CP0Status =
-       (Mk_StatusReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                   B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                       ::  32 Word.word)), 
+       ((| StatusReg_StatusReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  32 Word.word)) |)), 
+     CP0ConfigK0 = ((vec_of_bits [B0,B0,B0]  ::  3 Word.word)), 
      CP0UserLocal =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -10000,557 +9841,750 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
      CP0Cause =
-       (Mk_CauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                      ::  32 Word.word)), 
+       ((| CauseReg_CauseReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  32 Word.word)) |)), 
      CP0Compare =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0]
          ::  32 Word.word)), 
      TLBEntry63 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry62 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry61 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry60 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry59 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry58 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry57 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry56 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry55 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry54 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry53 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry52 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry51 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry50 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry49 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry48 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry47 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry46 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry45 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry44 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry43 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry42 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry41 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry40 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry39 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry38 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry37 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry36 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry35 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry34 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry33 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry32 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry31 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry30 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry29 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry28 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry27 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry26 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry25 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry24 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry23 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry22 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry21 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry20 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry19 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry18 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry17 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry16 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry15 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry14 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry13 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry12 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry11 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry10 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry09 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry08 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry07 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry06 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry05 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry04 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry03 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry02 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry01 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntry00 =
-       (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                  B0,B0,B0,B0,B0,B0,B0]
-                      ::  117 Word.word)), 
+       ((| TLBEntry_TLBEntry_chunk_1 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0]
+               ::  53 Word.word)), 
+           TLBEntry_TLBEntry_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBXContext =
-       (Mk_XContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0]
-                         ::  64 Word.word)), 
+       ((| XContextReg_XContextReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntryHi =
-       (Mk_TLBEntryHiReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0]
-                           ::  64 Word.word)), 
+       ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBWired = ((vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)), 
      TLBPageMask = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)), 
      TLBContext =
-       (Mk_ContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                    B0]
-                        ::  64 Word.word)), 
+       ((| ContextReg_ContextReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntryLo1 =
-       (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0]
-                           ::  64 Word.word)), 
+       ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBEntryLo0 =
-       (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                       B0,B0,B0,B0]
-                           ::  64 Word.word)), 
+       ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      TLBRandom = ((vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)), 
      TLBIndex = ((vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)), 
      TLBProbe = ((vec_of_bits [B0]  ::  1 Word.word)), 
diff --git a/snapshots/isabelle/cheri/Cheri_lemmas.thy b/snapshots/isabelle/cheri/Cheri_lemmas.thy
index 6dbee433..50ef7af2 100644
--- a/snapshots/isabelle/cheri/Cheri_lemmas.thy
+++ b/snapshots/isabelle/cheri/Cheri_lemmas.thy
@@ -1,38 +1,38 @@
 theory Cheri_lemmas
   imports
-    Sail.Sail_values_lemmas
-    Sail.State_lemmas
+    Sail.Sail2_values_lemmas
+    Sail.Sail2_state_lemmas
     Cheri
 begin
 
-abbreviation "liftS \<equiv> liftState (get_regval, set_regval)"
-
-lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def
-  CTLSP_ref_def CTLSU_ref_def C30_ref_def C28_ref_def C27_ref_def C26_ref_def C25_ref_def
-  C24_ref_def C23_ref_def C22_ref_def C21_ref_def C20_ref_def C19_ref_def C18_ref_def C17_ref_def
-  C16_ref_def C15_ref_def C14_ref_def C13_ref_def C12_ref_def C11_ref_def C10_ref_def C09_ref_def
-  C08_ref_def C07_ref_def C06_ref_def C05_ref_def C04_ref_def C03_ref_def C02_ref_def C01_ref_def
-  C00_ref_def inCCallDelay_ref_def nextPCC_ref_def delayedPCC_ref_def PCC_ref_def C31_ref_def
-  C29_ref_def UART_RVALID_ref_def UART_RDATA_ref_def UART_WRITTEN_ref_def UART_WDATA_ref_def
-  GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def inBranchDelay_ref_def branchPending_ref_def
-  CP0Status_ref_def CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def
-  CP0LLAddr_ref_def CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def
-  CP0Compare_ref_def TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def
-  TLBEntry59_ref_def TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def
-  TLBEntry54_ref_def TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def
-  TLBEntry49_ref_def TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def
-  TLBEntry44_ref_def TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def
-  TLBEntry39_ref_def TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def
-  TLBEntry34_ref_def TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def
-  TLBEntry29_ref_def TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def
-  TLBEntry24_ref_def TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def
-  TLBEntry19_ref_def TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def
-  TLBEntry14_ref_def TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def
-  TLBEntry09_ref_def TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def
-  TLBEntry04_ref_def TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def
-  TLBXContext_ref_def TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def
-  TLBEntryLo1_ref_def TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def
-  nextPC_ref_def PC_ref_def
+abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)"
+
+lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def KDC_ref_def
+  KR2C_ref_def KR1C_ref_def CTLSP_ref_def CTLSU_ref_def C31_ref_def C30_ref_def C29_ref_def
+  C28_ref_def C27_ref_def C26_ref_def C25_ref_def C24_ref_def C23_ref_def C22_ref_def C21_ref_def
+  C20_ref_def C19_ref_def C18_ref_def C17_ref_def C16_ref_def C15_ref_def C14_ref_def C13_ref_def
+  C12_ref_def C11_ref_def C10_ref_def C09_ref_def C08_ref_def C07_ref_def C06_ref_def C05_ref_def
+  C04_ref_def C03_ref_def C02_ref_def C01_ref_def DDC_ref_def inCCallDelay_ref_def nextPCC_ref_def
+  delayedPCC_ref_def PCC_ref_def KCC_ref_def EPCC_ref_def UART_RVALID_ref_def UART_RDATA_ref_def
+  UART_WRITTEN_ref_def UART_WDATA_ref_def GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def
+  inBranchDelay_ref_def branchPending_ref_def CP0Status_ref_def CP0ConfigK0_ref_def
+  CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def CP0LLAddr_ref_def
+  CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def CP0Compare_ref_def
+  TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def TLBEntry59_ref_def
+  TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def TLBEntry54_ref_def
+  TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def TLBEntry49_ref_def
+  TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def TLBEntry44_ref_def
+  TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def TLBEntry39_ref_def
+  TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def TLBEntry34_ref_def
+  TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def TLBEntry29_ref_def
+  TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def TLBEntry24_ref_def
+  TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def TLBEntry19_ref_def
+  TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def TLBEntry14_ref_def
+  TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def TLBEntry09_ref_def
+  TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def TLBEntry04_ref_def
+  TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def TLBXContext_ref_def
+  TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def TLBEntryLo1_ref_def
+  TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def nextPC_ref_def PC_ref_def
 
 lemma regval_CapCauseReg[simp]:
   "CapCauseReg_of_regval (regval_of_CapCauseReg v) = Some v"
@@ -86,6 +86,10 @@ lemma regval_vector_32_dec_bit[simp]:
   "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v"
   by (auto simp: regval_of_vector_32_dec_bit_def)
 
+lemma regval_vector_3_dec_bit[simp]:
+  "vector_3_dec_bit_of_regval (regval_of_vector_3_dec_bit v) = Some v"
+  by (auto simp: regval_of_vector_3_dec_bit_def)
+
 lemma regval_vector_64_dec_bit[simp]:
   "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v"
   by (auto simp: regval_of_vector_64_dec_bit_def)
@@ -106,1100 +110,1161 @@ proof -
   then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def)
 qed
 
-lemma liftS_read_reg_instCount[simp]:
-  "liftS (read_reg instCount_ref) = readS (instCount \<circ> regstate)"
+lemma option_of_rv_rv_of_option[simp]:
+  assumes "\<And>v. of_rv (rv_of v) = Some v"
+  shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v"
+  using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def)
+
+lemma list_of_rv_rv_of_list[simp]:
+  assumes "\<And>v. of_rv (rv_of v) = Some v"
+  shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v"
+proof -
+  from assms have "of_rv \<circ> rv_of = Some" by auto
+  with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def)
+qed
+
+lemma liftS_read_reg_instCount[liftState_simp]:
+  "\<lbrakk>read_reg instCount_ref\<rbrakk>\<^sub>S = readS (instCount \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_instCount[liftState_simp]:
+  "\<lbrakk>write_reg instCount_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (instCount_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_CapCause[liftState_simp]:
+  "\<lbrakk>read_reg CapCause_ref\<rbrakk>\<^sub>S = readS (CapCause \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_CapCause[liftState_simp]:
+  "\<lbrakk>write_reg CapCause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CapCause_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_KDC[liftState_simp]:
+  "\<lbrakk>read_reg KDC_ref\<rbrakk>\<^sub>S = readS (KDC \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_KDC[liftState_simp]:
+  "\<lbrakk>write_reg KDC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KDC_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_KR2C[liftState_simp]:
+  "\<lbrakk>read_reg KR2C_ref\<rbrakk>\<^sub>S = readS (KR2C \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_KR2C[liftState_simp]:
+  "\<lbrakk>write_reg KR2C_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KR2C_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_KR1C[liftState_simp]:
+  "\<lbrakk>read_reg KR1C_ref\<rbrakk>\<^sub>S = readS (KR1C \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_KR1C[liftState_simp]:
+  "\<lbrakk>write_reg KR1C_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KR1C_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_CTLSP[liftState_simp]:
+  "\<lbrakk>read_reg CTLSP_ref\<rbrakk>\<^sub>S = readS (CTLSP \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_CTLSP[liftState_simp]:
+  "\<lbrakk>write_reg CTLSP_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CTLSP_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_CTLSU[liftState_simp]:
+  "\<lbrakk>read_reg CTLSU_ref\<rbrakk>\<^sub>S = readS (CTLSU \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_instCount[simp]:
-  "liftS (write_reg instCount_ref v) = updateS (regstate_update (instCount_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CTLSU[liftState_simp]:
+  "\<lbrakk>write_reg CTLSU_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CTLSU_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CapCause[simp]:
-  "liftS (read_reg CapCause_ref) = readS (CapCause \<circ> regstate)"
+lemma liftS_read_reg_C31[liftState_simp]:
+  "\<lbrakk>read_reg C31_ref\<rbrakk>\<^sub>S = readS (C31 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CapCause[simp]:
-  "liftS (write_reg CapCause_ref v) = updateS (regstate_update (CapCause_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C31[liftState_simp]:
+  "\<lbrakk>write_reg C31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C31_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CTLSP[simp]:
-  "liftS (read_reg CTLSP_ref) = readS (CTLSP \<circ> regstate)"
+lemma liftS_read_reg_C30[liftState_simp]:
+  "\<lbrakk>read_reg C30_ref\<rbrakk>\<^sub>S = readS (C30 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CTLSP[simp]:
-  "liftS (write_reg CTLSP_ref v) = updateS (regstate_update (CTLSP_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C30[liftState_simp]:
+  "\<lbrakk>write_reg C30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C30_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CTLSU[simp]:
-  "liftS (read_reg CTLSU_ref) = readS (CTLSU \<circ> regstate)"
+lemma liftS_read_reg_C29[liftState_simp]:
+  "\<lbrakk>read_reg C29_ref\<rbrakk>\<^sub>S = readS (C29 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CTLSU[simp]:
-  "liftS (write_reg CTLSU_ref v) = updateS (regstate_update (CTLSU_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C29[liftState_simp]:
+  "\<lbrakk>write_reg C29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C29_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C30[simp]:
-  "liftS (read_reg C30_ref) = readS (C30 \<circ> regstate)"
+lemma liftS_read_reg_C28[liftState_simp]:
+  "\<lbrakk>read_reg C28_ref\<rbrakk>\<^sub>S = readS (C28 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C30[simp]:
-  "liftS (write_reg C30_ref v) = updateS (regstate_update (C30_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C28[liftState_simp]:
+  "\<lbrakk>write_reg C28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C28_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C28[simp]:
-  "liftS (read_reg C28_ref) = readS (C28 \<circ> regstate)"
+lemma liftS_read_reg_C27[liftState_simp]:
+  "\<lbrakk>read_reg C27_ref\<rbrakk>\<^sub>S = readS (C27 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C28[simp]:
-  "liftS (write_reg C28_ref v) = updateS (regstate_update (C28_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C27[liftState_simp]:
+  "\<lbrakk>write_reg C27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C27_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C27[simp]:
-  "liftS (read_reg C27_ref) = readS (C27 \<circ> regstate)"
+lemma liftS_read_reg_C26[liftState_simp]:
+  "\<lbrakk>read_reg C26_ref\<rbrakk>\<^sub>S = readS (C26 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C27[simp]:
-  "liftS (write_reg C27_ref v) = updateS (regstate_update (C27_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C26[liftState_simp]:
+  "\<lbrakk>write_reg C26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C26_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C26[simp]:
-  "liftS (read_reg C26_ref) = readS (C26 \<circ> regstate)"
+lemma liftS_read_reg_C25[liftState_simp]:
+  "\<lbrakk>read_reg C25_ref\<rbrakk>\<^sub>S = readS (C25 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C26[simp]:
-  "liftS (write_reg C26_ref v) = updateS (regstate_update (C26_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C25[liftState_simp]:
+  "\<lbrakk>write_reg C25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C25_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C25[simp]:
-  "liftS (read_reg C25_ref) = readS (C25 \<circ> regstate)"
+lemma liftS_read_reg_C24[liftState_simp]:
+  "\<lbrakk>read_reg C24_ref\<rbrakk>\<^sub>S = readS (C24 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C25[simp]:
-  "liftS (write_reg C25_ref v) = updateS (regstate_update (C25_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C24[liftState_simp]:
+  "\<lbrakk>write_reg C24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C24_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C24[simp]:
-  "liftS (read_reg C24_ref) = readS (C24 \<circ> regstate)"
+lemma liftS_read_reg_C23[liftState_simp]:
+  "\<lbrakk>read_reg C23_ref\<rbrakk>\<^sub>S = readS (C23 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C24[simp]:
-  "liftS (write_reg C24_ref v) = updateS (regstate_update (C24_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C23[liftState_simp]:
+  "\<lbrakk>write_reg C23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C23_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C23[simp]:
-  "liftS (read_reg C23_ref) = readS (C23 \<circ> regstate)"
+lemma liftS_read_reg_C22[liftState_simp]:
+  "\<lbrakk>read_reg C22_ref\<rbrakk>\<^sub>S = readS (C22 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C23[simp]:
-  "liftS (write_reg C23_ref v) = updateS (regstate_update (C23_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C22[liftState_simp]:
+  "\<lbrakk>write_reg C22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C22_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C22[simp]:
-  "liftS (read_reg C22_ref) = readS (C22 \<circ> regstate)"
+lemma liftS_read_reg_C21[liftState_simp]:
+  "\<lbrakk>read_reg C21_ref\<rbrakk>\<^sub>S = readS (C21 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C22[simp]:
-  "liftS (write_reg C22_ref v) = updateS (regstate_update (C22_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C21[liftState_simp]:
+  "\<lbrakk>write_reg C21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C21_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C21[simp]:
-  "liftS (read_reg C21_ref) = readS (C21 \<circ> regstate)"
+lemma liftS_read_reg_C20[liftState_simp]:
+  "\<lbrakk>read_reg C20_ref\<rbrakk>\<^sub>S = readS (C20 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C21[simp]:
-  "liftS (write_reg C21_ref v) = updateS (regstate_update (C21_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C20[liftState_simp]:
+  "\<lbrakk>write_reg C20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C20_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C20[simp]:
-  "liftS (read_reg C20_ref) = readS (C20 \<circ> regstate)"
+lemma liftS_read_reg_C19[liftState_simp]:
+  "\<lbrakk>read_reg C19_ref\<rbrakk>\<^sub>S = readS (C19 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C20[simp]:
-  "liftS (write_reg C20_ref v) = updateS (regstate_update (C20_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C19[liftState_simp]:
+  "\<lbrakk>write_reg C19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C19_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C19[simp]:
-  "liftS (read_reg C19_ref) = readS (C19 \<circ> regstate)"
+lemma liftS_read_reg_C18[liftState_simp]:
+  "\<lbrakk>read_reg C18_ref\<rbrakk>\<^sub>S = readS (C18 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C19[simp]:
-  "liftS (write_reg C19_ref v) = updateS (regstate_update (C19_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C18[liftState_simp]:
+  "\<lbrakk>write_reg C18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C18_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C18[simp]:
-  "liftS (read_reg C18_ref) = readS (C18 \<circ> regstate)"
+lemma liftS_read_reg_C17[liftState_simp]:
+  "\<lbrakk>read_reg C17_ref\<rbrakk>\<^sub>S = readS (C17 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C18[simp]:
-  "liftS (write_reg C18_ref v) = updateS (regstate_update (C18_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C17[liftState_simp]:
+  "\<lbrakk>write_reg C17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C17_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C17[simp]:
-  "liftS (read_reg C17_ref) = readS (C17 \<circ> regstate)"
+lemma liftS_read_reg_C16[liftState_simp]:
+  "\<lbrakk>read_reg C16_ref\<rbrakk>\<^sub>S = readS (C16 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C17[simp]:
-  "liftS (write_reg C17_ref v) = updateS (regstate_update (C17_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C16[liftState_simp]:
+  "\<lbrakk>write_reg C16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C16_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C16[simp]:
-  "liftS (read_reg C16_ref) = readS (C16 \<circ> regstate)"
+lemma liftS_read_reg_C15[liftState_simp]:
+  "\<lbrakk>read_reg C15_ref\<rbrakk>\<^sub>S = readS (C15 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C16[simp]:
-  "liftS (write_reg C16_ref v) = updateS (regstate_update (C16_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C15[liftState_simp]:
+  "\<lbrakk>write_reg C15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C15_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C15[simp]:
-  "liftS (read_reg C15_ref) = readS (C15 \<circ> regstate)"
+lemma liftS_read_reg_C14[liftState_simp]:
+  "\<lbrakk>read_reg C14_ref\<rbrakk>\<^sub>S = readS (C14 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C15[simp]:
-  "liftS (write_reg C15_ref v) = updateS (regstate_update (C15_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C14[liftState_simp]:
+  "\<lbrakk>write_reg C14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C14_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C14[simp]:
-  "liftS (read_reg C14_ref) = readS (C14 \<circ> regstate)"
+lemma liftS_read_reg_C13[liftState_simp]:
+  "\<lbrakk>read_reg C13_ref\<rbrakk>\<^sub>S = readS (C13 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C14[simp]:
-  "liftS (write_reg C14_ref v) = updateS (regstate_update (C14_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C13[liftState_simp]:
+  "\<lbrakk>write_reg C13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C13_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C13[simp]:
-  "liftS (read_reg C13_ref) = readS (C13 \<circ> regstate)"
+lemma liftS_read_reg_C12[liftState_simp]:
+  "\<lbrakk>read_reg C12_ref\<rbrakk>\<^sub>S = readS (C12 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C13[simp]:
-  "liftS (write_reg C13_ref v) = updateS (regstate_update (C13_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C12[liftState_simp]:
+  "\<lbrakk>write_reg C12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C12_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C12[simp]:
-  "liftS (read_reg C12_ref) = readS (C12 \<circ> regstate)"
+lemma liftS_read_reg_C11[liftState_simp]:
+  "\<lbrakk>read_reg C11_ref\<rbrakk>\<^sub>S = readS (C11 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C12[simp]:
-  "liftS (write_reg C12_ref v) = updateS (regstate_update (C12_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C11[liftState_simp]:
+  "\<lbrakk>write_reg C11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C11_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C11[simp]:
-  "liftS (read_reg C11_ref) = readS (C11 \<circ> regstate)"
+lemma liftS_read_reg_C10[liftState_simp]:
+  "\<lbrakk>read_reg C10_ref\<rbrakk>\<^sub>S = readS (C10 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C11[simp]:
-  "liftS (write_reg C11_ref v) = updateS (regstate_update (C11_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C10[liftState_simp]:
+  "\<lbrakk>write_reg C10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C10_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C10[simp]:
-  "liftS (read_reg C10_ref) = readS (C10 \<circ> regstate)"
+lemma liftS_read_reg_C09[liftState_simp]:
+  "\<lbrakk>read_reg C09_ref\<rbrakk>\<^sub>S = readS (C09 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C10[simp]:
-  "liftS (write_reg C10_ref v) = updateS (regstate_update (C10_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C09[liftState_simp]:
+  "\<lbrakk>write_reg C09_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C09_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C09[simp]:
-  "liftS (read_reg C09_ref) = readS (C09 \<circ> regstate)"
+lemma liftS_read_reg_C08[liftState_simp]:
+  "\<lbrakk>read_reg C08_ref\<rbrakk>\<^sub>S = readS (C08 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C09[simp]:
-  "liftS (write_reg C09_ref v) = updateS (regstate_update (C09_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C08[liftState_simp]:
+  "\<lbrakk>write_reg C08_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C08_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C08[simp]:
-  "liftS (read_reg C08_ref) = readS (C08 \<circ> regstate)"
+lemma liftS_read_reg_C07[liftState_simp]:
+  "\<lbrakk>read_reg C07_ref\<rbrakk>\<^sub>S = readS (C07 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C08[simp]:
-  "liftS (write_reg C08_ref v) = updateS (regstate_update (C08_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C07[liftState_simp]:
+  "\<lbrakk>write_reg C07_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C07_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C07[simp]:
-  "liftS (read_reg C07_ref) = readS (C07 \<circ> regstate)"
+lemma liftS_read_reg_C06[liftState_simp]:
+  "\<lbrakk>read_reg C06_ref\<rbrakk>\<^sub>S = readS (C06 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C07[simp]:
-  "liftS (write_reg C07_ref v) = updateS (regstate_update (C07_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C06[liftState_simp]:
+  "\<lbrakk>write_reg C06_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C06_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C06[simp]:
-  "liftS (read_reg C06_ref) = readS (C06 \<circ> regstate)"
+lemma liftS_read_reg_C05[liftState_simp]:
+  "\<lbrakk>read_reg C05_ref\<rbrakk>\<^sub>S = readS (C05 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C06[simp]:
-  "liftS (write_reg C06_ref v) = updateS (regstate_update (C06_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C05[liftState_simp]:
+  "\<lbrakk>write_reg C05_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C05_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C05[simp]:
-  "liftS (read_reg C05_ref) = readS (C05 \<circ> regstate)"
+lemma liftS_read_reg_C04[liftState_simp]:
+  "\<lbrakk>read_reg C04_ref\<rbrakk>\<^sub>S = readS (C04 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C05[simp]:
-  "liftS (write_reg C05_ref v) = updateS (regstate_update (C05_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C04[liftState_simp]:
+  "\<lbrakk>write_reg C04_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C04_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C04[simp]:
-  "liftS (read_reg C04_ref) = readS (C04 \<circ> regstate)"
+lemma liftS_read_reg_C03[liftState_simp]:
+  "\<lbrakk>read_reg C03_ref\<rbrakk>\<^sub>S = readS (C03 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C04[simp]:
-  "liftS (write_reg C04_ref v) = updateS (regstate_update (C04_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C03[liftState_simp]:
+  "\<lbrakk>write_reg C03_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C03_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C03[simp]:
-  "liftS (read_reg C03_ref) = readS (C03 \<circ> regstate)"
+lemma liftS_read_reg_C02[liftState_simp]:
+  "\<lbrakk>read_reg C02_ref\<rbrakk>\<^sub>S = readS (C02 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C03[simp]:
-  "liftS (write_reg C03_ref v) = updateS (regstate_update (C03_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C02[liftState_simp]:
+  "\<lbrakk>write_reg C02_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C02_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C02[simp]:
-  "liftS (read_reg C02_ref) = readS (C02 \<circ> regstate)"
+lemma liftS_read_reg_C01[liftState_simp]:
+  "\<lbrakk>read_reg C01_ref\<rbrakk>\<^sub>S = readS (C01 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C02[simp]:
-  "liftS (write_reg C02_ref v) = updateS (regstate_update (C02_update (\<lambda>_. v)))"
+lemma liftS_write_reg_C01[liftState_simp]:
+  "\<lbrakk>write_reg C01_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C01_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C01[simp]:
-  "liftS (read_reg C01_ref) = readS (C01 \<circ> regstate)"
+lemma liftS_read_reg_DDC[liftState_simp]:
+  "\<lbrakk>read_reg DDC_ref\<rbrakk>\<^sub>S = readS (DDC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C01[simp]:
-  "liftS (write_reg C01_ref v) = updateS (regstate_update (C01_update (\<lambda>_. v)))"
+lemma liftS_write_reg_DDC[liftState_simp]:
+  "\<lbrakk>write_reg DDC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DDC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C00[simp]:
-  "liftS (read_reg C00_ref) = readS (C00 \<circ> regstate)"
+lemma liftS_read_reg_inCCallDelay[liftState_simp]:
+  "\<lbrakk>read_reg inCCallDelay_ref\<rbrakk>\<^sub>S = readS (inCCallDelay \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C00[simp]:
-  "liftS (write_reg C00_ref v) = updateS (regstate_update (C00_update (\<lambda>_. v)))"
+lemma liftS_write_reg_inCCallDelay[liftState_simp]:
+  "\<lbrakk>write_reg inCCallDelay_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (inCCallDelay_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_inCCallDelay[simp]:
-  "liftS (read_reg inCCallDelay_ref) = readS (inCCallDelay \<circ> regstate)"
+lemma liftS_read_reg_nextPCC[liftState_simp]:
+  "\<lbrakk>read_reg nextPCC_ref\<rbrakk>\<^sub>S = readS (nextPCC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_inCCallDelay[simp]:
-  "liftS (write_reg inCCallDelay_ref v) = updateS (regstate_update (inCCallDelay_update (\<lambda>_. v)))"
+lemma liftS_write_reg_nextPCC[liftState_simp]:
+  "\<lbrakk>write_reg nextPCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPCC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_nextPCC[simp]:
-  "liftS (read_reg nextPCC_ref) = readS (nextPCC \<circ> regstate)"
+lemma liftS_read_reg_delayedPCC[liftState_simp]:
+  "\<lbrakk>read_reg delayedPCC_ref\<rbrakk>\<^sub>S = readS (delayedPCC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_nextPCC[simp]:
-  "liftS (write_reg nextPCC_ref v) = updateS (regstate_update (nextPCC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_delayedPCC[liftState_simp]:
+  "\<lbrakk>write_reg delayedPCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (delayedPCC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_delayedPCC[simp]:
-  "liftS (read_reg delayedPCC_ref) = readS (delayedPCC \<circ> regstate)"
+lemma liftS_read_reg_PCC[liftState_simp]:
+  "\<lbrakk>read_reg PCC_ref\<rbrakk>\<^sub>S = readS (PCC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_delayedPCC[simp]:
-  "liftS (write_reg delayedPCC_ref v) = updateS (regstate_update (delayedPCC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PCC[liftState_simp]:
+  "\<lbrakk>write_reg PCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PCC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PCC[simp]:
-  "liftS (read_reg PCC_ref) = readS (PCC \<circ> regstate)"
+lemma liftS_read_reg_KCC[liftState_simp]:
+  "\<lbrakk>read_reg KCC_ref\<rbrakk>\<^sub>S = readS (KCC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PCC[simp]:
-  "liftS (write_reg PCC_ref v) = updateS (regstate_update (PCC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_KCC[liftState_simp]:
+  "\<lbrakk>write_reg KCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KCC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C31[simp]:
-  "liftS (read_reg C31_ref) = readS (C31 \<circ> regstate)"
+lemma liftS_read_reg_EPCC[liftState_simp]:
+  "\<lbrakk>read_reg EPCC_ref\<rbrakk>\<^sub>S = readS (EPCC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C31[simp]:
-  "liftS (write_reg C31_ref v) = updateS (regstate_update (C31_update (\<lambda>_. v)))"
+lemma liftS_write_reg_EPCC[liftState_simp]:
+  "\<lbrakk>write_reg EPCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (EPCC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_C29[simp]:
-  "liftS (read_reg C29_ref) = readS (C29 \<circ> regstate)"
+lemma liftS_read_reg_UART_RVALID[liftState_simp]:
+  "\<lbrakk>read_reg UART_RVALID_ref\<rbrakk>\<^sub>S = readS (UART_RVALID \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_C29[simp]:
-  "liftS (write_reg C29_ref v) = updateS (regstate_update (C29_update (\<lambda>_. v)))"
+lemma liftS_write_reg_UART_RVALID[liftState_simp]:
+  "\<lbrakk>write_reg UART_RVALID_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_RVALID_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_UART_RVALID[simp]:
-  "liftS (read_reg UART_RVALID_ref) = readS (UART_RVALID \<circ> regstate)"
+lemma liftS_read_reg_UART_RDATA[liftState_simp]:
+  "\<lbrakk>read_reg UART_RDATA_ref\<rbrakk>\<^sub>S = readS (UART_RDATA \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_UART_RVALID[simp]:
-  "liftS (write_reg UART_RVALID_ref v) = updateS (regstate_update (UART_RVALID_update (\<lambda>_. v)))"
+lemma liftS_write_reg_UART_RDATA[liftState_simp]:
+  "\<lbrakk>write_reg UART_RDATA_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_RDATA_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_UART_RDATA[simp]:
-  "liftS (read_reg UART_RDATA_ref) = readS (UART_RDATA \<circ> regstate)"
+lemma liftS_read_reg_UART_WRITTEN[liftState_simp]:
+  "\<lbrakk>read_reg UART_WRITTEN_ref\<rbrakk>\<^sub>S = readS (UART_WRITTEN \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_UART_RDATA[simp]:
-  "liftS (write_reg UART_RDATA_ref v) = updateS (regstate_update (UART_RDATA_update (\<lambda>_. v)))"
+lemma liftS_write_reg_UART_WRITTEN[liftState_simp]:
+  "\<lbrakk>write_reg UART_WRITTEN_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_WRITTEN_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_UART_WRITTEN[simp]:
-  "liftS (read_reg UART_WRITTEN_ref) = readS (UART_WRITTEN \<circ> regstate)"
+lemma liftS_read_reg_UART_WDATA[liftState_simp]:
+  "\<lbrakk>read_reg UART_WDATA_ref\<rbrakk>\<^sub>S = readS (UART_WDATA \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_UART_WRITTEN[simp]:
-  "liftS (write_reg UART_WRITTEN_ref v) = updateS (regstate_update (UART_WRITTEN_update (\<lambda>_. v)))"
+lemma liftS_write_reg_UART_WDATA[liftState_simp]:
+  "\<lbrakk>write_reg UART_WDATA_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_WDATA_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_UART_WDATA[simp]:
-  "liftS (read_reg UART_WDATA_ref) = readS (UART_WDATA \<circ> regstate)"
+lemma liftS_read_reg_GPR[liftState_simp]:
+  "\<lbrakk>read_reg GPR_ref\<rbrakk>\<^sub>S = readS (GPR \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_UART_WDATA[simp]:
-  "liftS (write_reg UART_WDATA_ref v) = updateS (regstate_update (UART_WDATA_update (\<lambda>_. v)))"
+lemma liftS_write_reg_GPR[liftState_simp]:
+  "\<lbrakk>write_reg GPR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (GPR_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_GPR[simp]:
-  "liftS (read_reg GPR_ref) = readS (GPR \<circ> regstate)"
+lemma liftS_read_reg_LO[liftState_simp]:
+  "\<lbrakk>read_reg LO_ref\<rbrakk>\<^sub>S = readS (LO \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_GPR[simp]:
-  "liftS (write_reg GPR_ref v) = updateS (regstate_update (GPR_update (\<lambda>_. v)))"
+lemma liftS_write_reg_LO[liftState_simp]:
+  "\<lbrakk>write_reg LO_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (LO_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_LO[simp]:
-  "liftS (read_reg LO_ref) = readS (LO \<circ> regstate)"
+lemma liftS_read_reg_HI[liftState_simp]:
+  "\<lbrakk>read_reg HI_ref\<rbrakk>\<^sub>S = readS (HI \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_LO[simp]:
-  "liftS (write_reg LO_ref v) = updateS (regstate_update (LO_update (\<lambda>_. v)))"
+lemma liftS_write_reg_HI[liftState_simp]:
+  "\<lbrakk>write_reg HI_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HI_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_HI[simp]:
-  "liftS (read_reg HI_ref) = readS (HI \<circ> regstate)"
+lemma liftS_read_reg_delayedPC[liftState_simp]:
+  "\<lbrakk>read_reg delayedPC_ref\<rbrakk>\<^sub>S = readS (delayedPC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_HI[simp]:
-  "liftS (write_reg HI_ref v) = updateS (regstate_update (HI_update (\<lambda>_. v)))"
+lemma liftS_write_reg_delayedPC[liftState_simp]:
+  "\<lbrakk>write_reg delayedPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (delayedPC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_delayedPC[simp]:
-  "liftS (read_reg delayedPC_ref) = readS (delayedPC \<circ> regstate)"
+lemma liftS_read_reg_inBranchDelay[liftState_simp]:
+  "\<lbrakk>read_reg inBranchDelay_ref\<rbrakk>\<^sub>S = readS (inBranchDelay \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_delayedPC[simp]:
-  "liftS (write_reg delayedPC_ref v) = updateS (regstate_update (delayedPC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_inBranchDelay[liftState_simp]:
+  "\<lbrakk>write_reg inBranchDelay_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (inBranchDelay_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_inBranchDelay[simp]:
-  "liftS (read_reg inBranchDelay_ref) = readS (inBranchDelay \<circ> regstate)"
+lemma liftS_read_reg_branchPending[liftState_simp]:
+  "\<lbrakk>read_reg branchPending_ref\<rbrakk>\<^sub>S = readS (branchPending \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_inBranchDelay[simp]:
-  "liftS (write_reg inBranchDelay_ref v) = updateS (regstate_update (inBranchDelay_update (\<lambda>_. v)))"
+lemma liftS_write_reg_branchPending[liftState_simp]:
+  "\<lbrakk>write_reg branchPending_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (branchPending_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_branchPending[simp]:
-  "liftS (read_reg branchPending_ref) = readS (branchPending \<circ> regstate)"
+lemma liftS_read_reg_CP0Status[liftState_simp]:
+  "\<lbrakk>read_reg CP0Status_ref\<rbrakk>\<^sub>S = readS (CP0Status \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_branchPending[simp]:
-  "liftS (write_reg branchPending_ref v) = updateS (regstate_update (branchPending_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0Status[liftState_simp]:
+  "\<lbrakk>write_reg CP0Status_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Status_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0Status[simp]:
-  "liftS (read_reg CP0Status_ref) = readS (CP0Status \<circ> regstate)"
+lemma liftS_read_reg_CP0ConfigK0[liftState_simp]:
+  "\<lbrakk>read_reg CP0ConfigK0_ref\<rbrakk>\<^sub>S = readS (CP0ConfigK0 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0Status[simp]:
-  "liftS (write_reg CP0Status_ref v) = updateS (regstate_update (CP0Status_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0ConfigK0[liftState_simp]:
+  "\<lbrakk>write_reg CP0ConfigK0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0ConfigK0_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0UserLocal[simp]:
-  "liftS (read_reg CP0UserLocal_ref) = readS (CP0UserLocal \<circ> regstate)"
+lemma liftS_read_reg_CP0UserLocal[liftState_simp]:
+  "\<lbrakk>read_reg CP0UserLocal_ref\<rbrakk>\<^sub>S = readS (CP0UserLocal \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0UserLocal[simp]:
-  "liftS (write_reg CP0UserLocal_ref v) = updateS (regstate_update (CP0UserLocal_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0UserLocal[liftState_simp]:
+  "\<lbrakk>write_reg CP0UserLocal_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0UserLocal_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0HWREna[simp]:
-  "liftS (read_reg CP0HWREna_ref) = readS (CP0HWREna \<circ> regstate)"
+lemma liftS_read_reg_CP0HWREna[liftState_simp]:
+  "\<lbrakk>read_reg CP0HWREna_ref\<rbrakk>\<^sub>S = readS (CP0HWREna \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0HWREna[simp]:
-  "liftS (write_reg CP0HWREna_ref v) = updateS (regstate_update (CP0HWREna_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0HWREna[liftState_simp]:
+  "\<lbrakk>write_reg CP0HWREna_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0HWREna_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0Count[simp]:
-  "liftS (read_reg CP0Count_ref) = readS (CP0Count \<circ> regstate)"
+lemma liftS_read_reg_CP0Count[liftState_simp]:
+  "\<lbrakk>read_reg CP0Count_ref\<rbrakk>\<^sub>S = readS (CP0Count \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0Count[simp]:
-  "liftS (write_reg CP0Count_ref v) = updateS (regstate_update (CP0Count_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0Count[liftState_simp]:
+  "\<lbrakk>write_reg CP0Count_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Count_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0BadVAddr[simp]:
-  "liftS (read_reg CP0BadVAddr_ref) = readS (CP0BadVAddr \<circ> regstate)"
+lemma liftS_read_reg_CP0BadVAddr[liftState_simp]:
+  "\<lbrakk>read_reg CP0BadVAddr_ref\<rbrakk>\<^sub>S = readS (CP0BadVAddr \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0BadVAddr[simp]:
-  "liftS (write_reg CP0BadVAddr_ref v) = updateS (regstate_update (CP0BadVAddr_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0BadVAddr[liftState_simp]:
+  "\<lbrakk>write_reg CP0BadVAddr_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0BadVAddr_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0LLAddr[simp]:
-  "liftS (read_reg CP0LLAddr_ref) = readS (CP0LLAddr \<circ> regstate)"
+lemma liftS_read_reg_CP0LLAddr[liftState_simp]:
+  "\<lbrakk>read_reg CP0LLAddr_ref\<rbrakk>\<^sub>S = readS (CP0LLAddr \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0LLAddr[simp]:
-  "liftS (write_reg CP0LLAddr_ref v) = updateS (regstate_update (CP0LLAddr_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0LLAddr[liftState_simp]:
+  "\<lbrakk>write_reg CP0LLAddr_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0LLAddr_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0LLBit[simp]:
-  "liftS (read_reg CP0LLBit_ref) = readS (CP0LLBit \<circ> regstate)"
+lemma liftS_read_reg_CP0LLBit[liftState_simp]:
+  "\<lbrakk>read_reg CP0LLBit_ref\<rbrakk>\<^sub>S = readS (CP0LLBit \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0LLBit[simp]:
-  "liftS (write_reg CP0LLBit_ref v) = updateS (regstate_update (CP0LLBit_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0LLBit[liftState_simp]:
+  "\<lbrakk>write_reg CP0LLBit_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0LLBit_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0ErrorEPC[simp]:
-  "liftS (read_reg CP0ErrorEPC_ref) = readS (CP0ErrorEPC \<circ> regstate)"
+lemma liftS_read_reg_CP0ErrorEPC[liftState_simp]:
+  "\<lbrakk>read_reg CP0ErrorEPC_ref\<rbrakk>\<^sub>S = readS (CP0ErrorEPC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0ErrorEPC[simp]:
-  "liftS (write_reg CP0ErrorEPC_ref v) = updateS (regstate_update (CP0ErrorEPC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0ErrorEPC[liftState_simp]:
+  "\<lbrakk>write_reg CP0ErrorEPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0ErrorEPC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0EPC[simp]:
-  "liftS (read_reg CP0EPC_ref) = readS (CP0EPC \<circ> regstate)"
+lemma liftS_read_reg_CP0EPC[liftState_simp]:
+  "\<lbrakk>read_reg CP0EPC_ref\<rbrakk>\<^sub>S = readS (CP0EPC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0EPC[simp]:
-  "liftS (write_reg CP0EPC_ref v) = updateS (regstate_update (CP0EPC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0EPC[liftState_simp]:
+  "\<lbrakk>write_reg CP0EPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0EPC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0Cause[simp]:
-  "liftS (read_reg CP0Cause_ref) = readS (CP0Cause \<circ> regstate)"
+lemma liftS_read_reg_CP0Cause[liftState_simp]:
+  "\<lbrakk>read_reg CP0Cause_ref\<rbrakk>\<^sub>S = readS (CP0Cause \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0Cause[simp]:
-  "liftS (write_reg CP0Cause_ref v) = updateS (regstate_update (CP0Cause_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0Cause[liftState_simp]:
+  "\<lbrakk>write_reg CP0Cause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Cause_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_CP0Compare[simp]:
-  "liftS (read_reg CP0Compare_ref) = readS (CP0Compare \<circ> regstate)"
+lemma liftS_read_reg_CP0Compare[liftState_simp]:
+  "\<lbrakk>read_reg CP0Compare_ref\<rbrakk>\<^sub>S = readS (CP0Compare \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_CP0Compare[simp]:
-  "liftS (write_reg CP0Compare_ref v) = updateS (regstate_update (CP0Compare_update (\<lambda>_. v)))"
+lemma liftS_write_reg_CP0Compare[liftState_simp]:
+  "\<lbrakk>write_reg CP0Compare_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Compare_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry63[simp]:
-  "liftS (read_reg TLBEntry63_ref) = readS (TLBEntry63 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry63[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry63_ref\<rbrakk>\<^sub>S = readS (TLBEntry63 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry63[simp]:
-  "liftS (write_reg TLBEntry63_ref v) = updateS (regstate_update (TLBEntry63_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry63[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry63_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry63_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry62[simp]:
-  "liftS (read_reg TLBEntry62_ref) = readS (TLBEntry62 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry62[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry62_ref\<rbrakk>\<^sub>S = readS (TLBEntry62 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry62[simp]:
-  "liftS (write_reg TLBEntry62_ref v) = updateS (regstate_update (TLBEntry62_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry62[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry62_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry62_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry61[simp]:
-  "liftS (read_reg TLBEntry61_ref) = readS (TLBEntry61 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry61[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry61_ref\<rbrakk>\<^sub>S = readS (TLBEntry61 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry61[simp]:
-  "liftS (write_reg TLBEntry61_ref v) = updateS (regstate_update (TLBEntry61_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry61[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry61_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry61_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry60[simp]:
-  "liftS (read_reg TLBEntry60_ref) = readS (TLBEntry60 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry60[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry60_ref\<rbrakk>\<^sub>S = readS (TLBEntry60 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry60[simp]:
-  "liftS (write_reg TLBEntry60_ref v) = updateS (regstate_update (TLBEntry60_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry60[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry60_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry60_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry59[simp]:
-  "liftS (read_reg TLBEntry59_ref) = readS (TLBEntry59 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry59[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry59_ref\<rbrakk>\<^sub>S = readS (TLBEntry59 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry59[simp]:
-  "liftS (write_reg TLBEntry59_ref v) = updateS (regstate_update (TLBEntry59_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry59[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry59_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry59_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry58[simp]:
-  "liftS (read_reg TLBEntry58_ref) = readS (TLBEntry58 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry58[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry58_ref\<rbrakk>\<^sub>S = readS (TLBEntry58 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry58[simp]:
-  "liftS (write_reg TLBEntry58_ref v) = updateS (regstate_update (TLBEntry58_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry58[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry58_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry58_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry57[simp]:
-  "liftS (read_reg TLBEntry57_ref) = readS (TLBEntry57 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry57[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry57_ref\<rbrakk>\<^sub>S = readS (TLBEntry57 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry57[simp]:
-  "liftS (write_reg TLBEntry57_ref v) = updateS (regstate_update (TLBEntry57_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry57[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry57_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry57_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry56[simp]:
-  "liftS (read_reg TLBEntry56_ref) = readS (TLBEntry56 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry56[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry56_ref\<rbrakk>\<^sub>S = readS (TLBEntry56 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry56[simp]:
-  "liftS (write_reg TLBEntry56_ref v) = updateS (regstate_update (TLBEntry56_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry56[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry56_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry56_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry55[simp]:
-  "liftS (read_reg TLBEntry55_ref) = readS (TLBEntry55 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry55[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry55_ref\<rbrakk>\<^sub>S = readS (TLBEntry55 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry55[simp]:
-  "liftS (write_reg TLBEntry55_ref v) = updateS (regstate_update (TLBEntry55_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry55[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry55_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry55_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry54[simp]:
-  "liftS (read_reg TLBEntry54_ref) = readS (TLBEntry54 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry54[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry54_ref\<rbrakk>\<^sub>S = readS (TLBEntry54 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry54[simp]:
-  "liftS (write_reg TLBEntry54_ref v) = updateS (regstate_update (TLBEntry54_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry54[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry54_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry54_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry53[simp]:
-  "liftS (read_reg TLBEntry53_ref) = readS (TLBEntry53 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry53[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry53_ref\<rbrakk>\<^sub>S = readS (TLBEntry53 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry53[simp]:
-  "liftS (write_reg TLBEntry53_ref v) = updateS (regstate_update (TLBEntry53_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry53[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry53_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry53_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry52[simp]:
-  "liftS (read_reg TLBEntry52_ref) = readS (TLBEntry52 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry52[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry52_ref\<rbrakk>\<^sub>S = readS (TLBEntry52 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry52[simp]:
-  "liftS (write_reg TLBEntry52_ref v) = updateS (regstate_update (TLBEntry52_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry52[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry52_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry52_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry51[simp]:
-  "liftS (read_reg TLBEntry51_ref) = readS (TLBEntry51 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry51[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry51_ref\<rbrakk>\<^sub>S = readS (TLBEntry51 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry51[simp]:
-  "liftS (write_reg TLBEntry51_ref v) = updateS (regstate_update (TLBEntry51_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry51[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry51_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry51_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry50[simp]:
-  "liftS (read_reg TLBEntry50_ref) = readS (TLBEntry50 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry50[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry50_ref\<rbrakk>\<^sub>S = readS (TLBEntry50 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry50[simp]:
-  "liftS (write_reg TLBEntry50_ref v) = updateS (regstate_update (TLBEntry50_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry50[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry50_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry50_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry49[simp]:
-  "liftS (read_reg TLBEntry49_ref) = readS (TLBEntry49 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry49[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry49_ref\<rbrakk>\<^sub>S = readS (TLBEntry49 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry49[simp]:
-  "liftS (write_reg TLBEntry49_ref v) = updateS (regstate_update (TLBEntry49_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry49[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry49_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry49_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry48[simp]:
-  "liftS (read_reg TLBEntry48_ref) = readS (TLBEntry48 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry48[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry48_ref\<rbrakk>\<^sub>S = readS (TLBEntry48 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry48[simp]:
-  "liftS (write_reg TLBEntry48_ref v) = updateS (regstate_update (TLBEntry48_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry48[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry48_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry48_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry47[simp]:
-  "liftS (read_reg TLBEntry47_ref) = readS (TLBEntry47 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry47[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry47_ref\<rbrakk>\<^sub>S = readS (TLBEntry47 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry47[simp]:
-  "liftS (write_reg TLBEntry47_ref v) = updateS (regstate_update (TLBEntry47_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry47[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry47_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry47_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry46[simp]:
-  "liftS (read_reg TLBEntry46_ref) = readS (TLBEntry46 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry46[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry46_ref\<rbrakk>\<^sub>S = readS (TLBEntry46 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry46[simp]:
-  "liftS (write_reg TLBEntry46_ref v) = updateS (regstate_update (TLBEntry46_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry46[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry46_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry46_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry45[simp]:
-  "liftS (read_reg TLBEntry45_ref) = readS (TLBEntry45 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry45[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry45_ref\<rbrakk>\<^sub>S = readS (TLBEntry45 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry45[simp]:
-  "liftS (write_reg TLBEntry45_ref v) = updateS (regstate_update (TLBEntry45_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry45[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry45_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry45_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry44[simp]:
-  "liftS (read_reg TLBEntry44_ref) = readS (TLBEntry44 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry44[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry44_ref\<rbrakk>\<^sub>S = readS (TLBEntry44 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry44[simp]:
-  "liftS (write_reg TLBEntry44_ref v) = updateS (regstate_update (TLBEntry44_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry44[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry44_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry44_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry43[simp]:
-  "liftS (read_reg TLBEntry43_ref) = readS (TLBEntry43 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry43[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry43_ref\<rbrakk>\<^sub>S = readS (TLBEntry43 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry43[simp]:
-  "liftS (write_reg TLBEntry43_ref v) = updateS (regstate_update (TLBEntry43_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry43[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry43_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry43_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry42[simp]:
-  "liftS (read_reg TLBEntry42_ref) = readS (TLBEntry42 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry42[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry42_ref\<rbrakk>\<^sub>S = readS (TLBEntry42 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry42[simp]:
-  "liftS (write_reg TLBEntry42_ref v) = updateS (regstate_update (TLBEntry42_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry42[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry42_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry42_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry41[simp]:
-  "liftS (read_reg TLBEntry41_ref) = readS (TLBEntry41 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry41[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry41_ref\<rbrakk>\<^sub>S = readS (TLBEntry41 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry41[simp]:
-  "liftS (write_reg TLBEntry41_ref v) = updateS (regstate_update (TLBEntry41_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry41[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry41_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry41_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry40[simp]:
-  "liftS (read_reg TLBEntry40_ref) = readS (TLBEntry40 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry40[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry40_ref\<rbrakk>\<^sub>S = readS (TLBEntry40 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry40[simp]:
-  "liftS (write_reg TLBEntry40_ref v) = updateS (regstate_update (TLBEntry40_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry40[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry40_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry40_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry39[simp]:
-  "liftS (read_reg TLBEntry39_ref) = readS (TLBEntry39 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry39[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry39_ref\<rbrakk>\<^sub>S = readS (TLBEntry39 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry39[simp]:
-  "liftS (write_reg TLBEntry39_ref v) = updateS (regstate_update (TLBEntry39_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry39[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry39_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry39_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry38[simp]:
-  "liftS (read_reg TLBEntry38_ref) = readS (TLBEntry38 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry38[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry38_ref\<rbrakk>\<^sub>S = readS (TLBEntry38 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry38[simp]:
-  "liftS (write_reg TLBEntry38_ref v) = updateS (regstate_update (TLBEntry38_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry38[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry38_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry38_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry37[simp]:
-  "liftS (read_reg TLBEntry37_ref) = readS (TLBEntry37 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry37[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry37_ref\<rbrakk>\<^sub>S = readS (TLBEntry37 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry37[simp]:
-  "liftS (write_reg TLBEntry37_ref v) = updateS (regstate_update (TLBEntry37_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry37[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry37_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry37_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry36[simp]:
-  "liftS (read_reg TLBEntry36_ref) = readS (TLBEntry36 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry36[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry36_ref\<rbrakk>\<^sub>S = readS (TLBEntry36 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry36[simp]:
-  "liftS (write_reg TLBEntry36_ref v) = updateS (regstate_update (TLBEntry36_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry36[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry36_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry36_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry35[simp]:
-  "liftS (read_reg TLBEntry35_ref) = readS (TLBEntry35 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry35[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry35_ref\<rbrakk>\<^sub>S = readS (TLBEntry35 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry35[simp]:
-  "liftS (write_reg TLBEntry35_ref v) = updateS (regstate_update (TLBEntry35_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry35[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry35_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry35_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry34[simp]:
-  "liftS (read_reg TLBEntry34_ref) = readS (TLBEntry34 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry34[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry34_ref\<rbrakk>\<^sub>S = readS (TLBEntry34 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry34[simp]:
-  "liftS (write_reg TLBEntry34_ref v) = updateS (regstate_update (TLBEntry34_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry34[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry34_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry34_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry33[simp]:
-  "liftS (read_reg TLBEntry33_ref) = readS (TLBEntry33 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry33[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry33_ref\<rbrakk>\<^sub>S = readS (TLBEntry33 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry33[simp]:
-  "liftS (write_reg TLBEntry33_ref v) = updateS (regstate_update (TLBEntry33_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry33[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry33_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry33_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry32[simp]:
-  "liftS (read_reg TLBEntry32_ref) = readS (TLBEntry32 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry32[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry32_ref\<rbrakk>\<^sub>S = readS (TLBEntry32 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry32[simp]:
-  "liftS (write_reg TLBEntry32_ref v) = updateS (regstate_update (TLBEntry32_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry32[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry32_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry32_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry31[simp]:
-  "liftS (read_reg TLBEntry31_ref) = readS (TLBEntry31 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry31[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry31_ref\<rbrakk>\<^sub>S = readS (TLBEntry31 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry31[simp]:
-  "liftS (write_reg TLBEntry31_ref v) = updateS (regstate_update (TLBEntry31_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry31[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry31_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry30[simp]:
-  "liftS (read_reg TLBEntry30_ref) = readS (TLBEntry30 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry30[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry30_ref\<rbrakk>\<^sub>S = readS (TLBEntry30 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry30[simp]:
-  "liftS (write_reg TLBEntry30_ref v) = updateS (regstate_update (TLBEntry30_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry30[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry30_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry29[simp]:
-  "liftS (read_reg TLBEntry29_ref) = readS (TLBEntry29 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry29[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry29_ref\<rbrakk>\<^sub>S = readS (TLBEntry29 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry29[simp]:
-  "liftS (write_reg TLBEntry29_ref v) = updateS (regstate_update (TLBEntry29_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry29[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry29_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry28[simp]:
-  "liftS (read_reg TLBEntry28_ref) = readS (TLBEntry28 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry28[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry28_ref\<rbrakk>\<^sub>S = readS (TLBEntry28 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry28[simp]:
-  "liftS (write_reg TLBEntry28_ref v) = updateS (regstate_update (TLBEntry28_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry28[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry28_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry27[simp]:
-  "liftS (read_reg TLBEntry27_ref) = readS (TLBEntry27 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry27[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry27_ref\<rbrakk>\<^sub>S = readS (TLBEntry27 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry27[simp]:
-  "liftS (write_reg TLBEntry27_ref v) = updateS (regstate_update (TLBEntry27_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry27[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry27_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry26[simp]:
-  "liftS (read_reg TLBEntry26_ref) = readS (TLBEntry26 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry26[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry26_ref\<rbrakk>\<^sub>S = readS (TLBEntry26 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry26[simp]:
-  "liftS (write_reg TLBEntry26_ref v) = updateS (regstate_update (TLBEntry26_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry26[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry26_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry25[simp]:
-  "liftS (read_reg TLBEntry25_ref) = readS (TLBEntry25 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry25[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry25_ref\<rbrakk>\<^sub>S = readS (TLBEntry25 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry25[simp]:
-  "liftS (write_reg TLBEntry25_ref v) = updateS (regstate_update (TLBEntry25_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry25[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry25_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry24[simp]:
-  "liftS (read_reg TLBEntry24_ref) = readS (TLBEntry24 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry24[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry24_ref\<rbrakk>\<^sub>S = readS (TLBEntry24 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry24[simp]:
-  "liftS (write_reg TLBEntry24_ref v) = updateS (regstate_update (TLBEntry24_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry24[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry24_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry23[simp]:
-  "liftS (read_reg TLBEntry23_ref) = readS (TLBEntry23 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry23[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry23_ref\<rbrakk>\<^sub>S = readS (TLBEntry23 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry23[simp]:
-  "liftS (write_reg TLBEntry23_ref v) = updateS (regstate_update (TLBEntry23_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry23[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry23_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry22[simp]:
-  "liftS (read_reg TLBEntry22_ref) = readS (TLBEntry22 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry22[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry22_ref\<rbrakk>\<^sub>S = readS (TLBEntry22 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry22[simp]:
-  "liftS (write_reg TLBEntry22_ref v) = updateS (regstate_update (TLBEntry22_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry22[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry22_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry21[simp]:
-  "liftS (read_reg TLBEntry21_ref) = readS (TLBEntry21 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry21[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry21_ref\<rbrakk>\<^sub>S = readS (TLBEntry21 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry21[simp]:
-  "liftS (write_reg TLBEntry21_ref v) = updateS (regstate_update (TLBEntry21_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry21[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry21_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry20[simp]:
-  "liftS (read_reg TLBEntry20_ref) = readS (TLBEntry20 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry20[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry20_ref\<rbrakk>\<^sub>S = readS (TLBEntry20 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry20[simp]:
-  "liftS (write_reg TLBEntry20_ref v) = updateS (regstate_update (TLBEntry20_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry20[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry20_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry19[simp]:
-  "liftS (read_reg TLBEntry19_ref) = readS (TLBEntry19 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry19[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry19_ref\<rbrakk>\<^sub>S = readS (TLBEntry19 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry19[simp]:
-  "liftS (write_reg TLBEntry19_ref v) = updateS (regstate_update (TLBEntry19_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry19[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry19_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry18[simp]:
-  "liftS (read_reg TLBEntry18_ref) = readS (TLBEntry18 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry18[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry18_ref\<rbrakk>\<^sub>S = readS (TLBEntry18 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry18[simp]:
-  "liftS (write_reg TLBEntry18_ref v) = updateS (regstate_update (TLBEntry18_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry18[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry18_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry17[simp]:
-  "liftS (read_reg TLBEntry17_ref) = readS (TLBEntry17 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry17[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry17_ref\<rbrakk>\<^sub>S = readS (TLBEntry17 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry17[simp]:
-  "liftS (write_reg TLBEntry17_ref v) = updateS (regstate_update (TLBEntry17_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry17[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry17_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry16[simp]:
-  "liftS (read_reg TLBEntry16_ref) = readS (TLBEntry16 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry16[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry16_ref\<rbrakk>\<^sub>S = readS (TLBEntry16 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry16[simp]:
-  "liftS (write_reg TLBEntry16_ref v) = updateS (regstate_update (TLBEntry16_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry16[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry16_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry15[simp]:
-  "liftS (read_reg TLBEntry15_ref) = readS (TLBEntry15 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry15[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry15_ref\<rbrakk>\<^sub>S = readS (TLBEntry15 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry15[simp]:
-  "liftS (write_reg TLBEntry15_ref v) = updateS (regstate_update (TLBEntry15_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry15[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry15_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry14[simp]:
-  "liftS (read_reg TLBEntry14_ref) = readS (TLBEntry14 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry14[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry14_ref\<rbrakk>\<^sub>S = readS (TLBEntry14 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry14[simp]:
-  "liftS (write_reg TLBEntry14_ref v) = updateS (regstate_update (TLBEntry14_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry14[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry14_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry13[simp]:
-  "liftS (read_reg TLBEntry13_ref) = readS (TLBEntry13 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry13[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry13_ref\<rbrakk>\<^sub>S = readS (TLBEntry13 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry13[simp]:
-  "liftS (write_reg TLBEntry13_ref v) = updateS (regstate_update (TLBEntry13_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry13[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry13_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry12[simp]:
-  "liftS (read_reg TLBEntry12_ref) = readS (TLBEntry12 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry12[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry12_ref\<rbrakk>\<^sub>S = readS (TLBEntry12 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry12[simp]:
-  "liftS (write_reg TLBEntry12_ref v) = updateS (regstate_update (TLBEntry12_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry12[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry12_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry11[simp]:
-  "liftS (read_reg TLBEntry11_ref) = readS (TLBEntry11 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry11[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry11_ref\<rbrakk>\<^sub>S = readS (TLBEntry11 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry11[simp]:
-  "liftS (write_reg TLBEntry11_ref v) = updateS (regstate_update (TLBEntry11_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry11[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry11_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry10[simp]:
-  "liftS (read_reg TLBEntry10_ref) = readS (TLBEntry10 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry10[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry10_ref\<rbrakk>\<^sub>S = readS (TLBEntry10 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry10[simp]:
-  "liftS (write_reg TLBEntry10_ref v) = updateS (regstate_update (TLBEntry10_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry10[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry10_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry09[simp]:
-  "liftS (read_reg TLBEntry09_ref) = readS (TLBEntry09 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry09[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry09_ref\<rbrakk>\<^sub>S = readS (TLBEntry09 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry09[simp]:
-  "liftS (write_reg TLBEntry09_ref v) = updateS (regstate_update (TLBEntry09_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry09[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry09_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry09_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry08[simp]:
-  "liftS (read_reg TLBEntry08_ref) = readS (TLBEntry08 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry08[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry08_ref\<rbrakk>\<^sub>S = readS (TLBEntry08 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry08[simp]:
-  "liftS (write_reg TLBEntry08_ref v) = updateS (regstate_update (TLBEntry08_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry08[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry08_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry08_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry07[simp]:
-  "liftS (read_reg TLBEntry07_ref) = readS (TLBEntry07 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry07[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry07_ref\<rbrakk>\<^sub>S = readS (TLBEntry07 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry07[simp]:
-  "liftS (write_reg TLBEntry07_ref v) = updateS (regstate_update (TLBEntry07_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry07[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry07_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry07_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry06[simp]:
-  "liftS (read_reg TLBEntry06_ref) = readS (TLBEntry06 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry06[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry06_ref\<rbrakk>\<^sub>S = readS (TLBEntry06 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry06[simp]:
-  "liftS (write_reg TLBEntry06_ref v) = updateS (regstate_update (TLBEntry06_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry06[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry06_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry06_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry05[simp]:
-  "liftS (read_reg TLBEntry05_ref) = readS (TLBEntry05 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry05[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry05_ref\<rbrakk>\<^sub>S = readS (TLBEntry05 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry05[simp]:
-  "liftS (write_reg TLBEntry05_ref v) = updateS (regstate_update (TLBEntry05_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry05[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry05_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry05_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry04[simp]:
-  "liftS (read_reg TLBEntry04_ref) = readS (TLBEntry04 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry04[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry04_ref\<rbrakk>\<^sub>S = readS (TLBEntry04 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry04[simp]:
-  "liftS (write_reg TLBEntry04_ref v) = updateS (regstate_update (TLBEntry04_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry04[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry04_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry04_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry03[simp]:
-  "liftS (read_reg TLBEntry03_ref) = readS (TLBEntry03 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry03[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry03_ref\<rbrakk>\<^sub>S = readS (TLBEntry03 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry03[simp]:
-  "liftS (write_reg TLBEntry03_ref v) = updateS (regstate_update (TLBEntry03_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry03[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry03_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry03_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry02[simp]:
-  "liftS (read_reg TLBEntry02_ref) = readS (TLBEntry02 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry02[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry02_ref\<rbrakk>\<^sub>S = readS (TLBEntry02 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry02[simp]:
-  "liftS (write_reg TLBEntry02_ref v) = updateS (regstate_update (TLBEntry02_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry02[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry02_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry02_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry01[simp]:
-  "liftS (read_reg TLBEntry01_ref) = readS (TLBEntry01 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry01[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry01_ref\<rbrakk>\<^sub>S = readS (TLBEntry01 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry01[simp]:
-  "liftS (write_reg TLBEntry01_ref v) = updateS (regstate_update (TLBEntry01_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry01[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry01_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry01_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntry00[simp]:
-  "liftS (read_reg TLBEntry00_ref) = readS (TLBEntry00 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntry00[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntry00_ref\<rbrakk>\<^sub>S = readS (TLBEntry00 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntry00[simp]:
-  "liftS (write_reg TLBEntry00_ref v) = updateS (regstate_update (TLBEntry00_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntry00[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntry00_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry00_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBXContext[simp]:
-  "liftS (read_reg TLBXContext_ref) = readS (TLBXContext \<circ> regstate)"
+lemma liftS_read_reg_TLBXContext[liftState_simp]:
+  "\<lbrakk>read_reg TLBXContext_ref\<rbrakk>\<^sub>S = readS (TLBXContext \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBXContext[simp]:
-  "liftS (write_reg TLBXContext_ref v) = updateS (regstate_update (TLBXContext_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBXContext[liftState_simp]:
+  "\<lbrakk>write_reg TLBXContext_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBXContext_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntryHi[simp]:
-  "liftS (read_reg TLBEntryHi_ref) = readS (TLBEntryHi \<circ> regstate)"
+lemma liftS_read_reg_TLBEntryHi[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntryHi_ref\<rbrakk>\<^sub>S = readS (TLBEntryHi \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntryHi[simp]:
-  "liftS (write_reg TLBEntryHi_ref v) = updateS (regstate_update (TLBEntryHi_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntryHi[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntryHi_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntryHi_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBWired[simp]:
-  "liftS (read_reg TLBWired_ref) = readS (TLBWired \<circ> regstate)"
+lemma liftS_read_reg_TLBWired[liftState_simp]:
+  "\<lbrakk>read_reg TLBWired_ref\<rbrakk>\<^sub>S = readS (TLBWired \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBWired[simp]:
-  "liftS (write_reg TLBWired_ref v) = updateS (regstate_update (TLBWired_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBWired[liftState_simp]:
+  "\<lbrakk>write_reg TLBWired_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBWired_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBPageMask[simp]:
-  "liftS (read_reg TLBPageMask_ref) = readS (TLBPageMask \<circ> regstate)"
+lemma liftS_read_reg_TLBPageMask[liftState_simp]:
+  "\<lbrakk>read_reg TLBPageMask_ref\<rbrakk>\<^sub>S = readS (TLBPageMask \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBPageMask[simp]:
-  "liftS (write_reg TLBPageMask_ref v) = updateS (regstate_update (TLBPageMask_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBPageMask[liftState_simp]:
+  "\<lbrakk>write_reg TLBPageMask_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBPageMask_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBContext[simp]:
-  "liftS (read_reg TLBContext_ref) = readS (TLBContext \<circ> regstate)"
+lemma liftS_read_reg_TLBContext[liftState_simp]:
+  "\<lbrakk>read_reg TLBContext_ref\<rbrakk>\<^sub>S = readS (TLBContext \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBContext[simp]:
-  "liftS (write_reg TLBContext_ref v) = updateS (regstate_update (TLBContext_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBContext[liftState_simp]:
+  "\<lbrakk>write_reg TLBContext_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBContext_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntryLo1[simp]:
-  "liftS (read_reg TLBEntryLo1_ref) = readS (TLBEntryLo1 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntryLo1[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntryLo1_ref\<rbrakk>\<^sub>S = readS (TLBEntryLo1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntryLo1[simp]:
-  "liftS (write_reg TLBEntryLo1_ref v) = updateS (regstate_update (TLBEntryLo1_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntryLo1[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntryLo1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntryLo1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBEntryLo0[simp]:
-  "liftS (read_reg TLBEntryLo0_ref) = readS (TLBEntryLo0 \<circ> regstate)"
+lemma liftS_read_reg_TLBEntryLo0[liftState_simp]:
+  "\<lbrakk>read_reg TLBEntryLo0_ref\<rbrakk>\<^sub>S = readS (TLBEntryLo0 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBEntryLo0[simp]:
-  "liftS (write_reg TLBEntryLo0_ref v) = updateS (regstate_update (TLBEntryLo0_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBEntryLo0[liftState_simp]:
+  "\<lbrakk>write_reg TLBEntryLo0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntryLo0_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBRandom[simp]:
-  "liftS (read_reg TLBRandom_ref) = readS (TLBRandom \<circ> regstate)"
+lemma liftS_read_reg_TLBRandom[liftState_simp]:
+  "\<lbrakk>read_reg TLBRandom_ref\<rbrakk>\<^sub>S = readS (TLBRandom \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBRandom[simp]:
-  "liftS (write_reg TLBRandom_ref v) = updateS (regstate_update (TLBRandom_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBRandom[liftState_simp]:
+  "\<lbrakk>write_reg TLBRandom_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBRandom_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBIndex[simp]:
-  "liftS (read_reg TLBIndex_ref) = readS (TLBIndex \<circ> regstate)"
+lemma liftS_read_reg_TLBIndex[liftState_simp]:
+  "\<lbrakk>read_reg TLBIndex_ref\<rbrakk>\<^sub>S = readS (TLBIndex \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBIndex[simp]:
-  "liftS (write_reg TLBIndex_ref v) = updateS (regstate_update (TLBIndex_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBIndex[liftState_simp]:
+  "\<lbrakk>write_reg TLBIndex_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBIndex_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_TLBProbe[simp]:
-  "liftS (read_reg TLBProbe_ref) = readS (TLBProbe \<circ> regstate)"
+lemma liftS_read_reg_TLBProbe[liftState_simp]:
+  "\<lbrakk>read_reg TLBProbe_ref\<rbrakk>\<^sub>S = readS (TLBProbe \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_TLBProbe[simp]:
-  "liftS (write_reg TLBProbe_ref v) = updateS (regstate_update (TLBProbe_update (\<lambda>_. v)))"
+lemma liftS_write_reg_TLBProbe[liftState_simp]:
+  "\<lbrakk>write_reg TLBProbe_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBProbe_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_nextPC[simp]:
-  "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)"
+lemma liftS_read_reg_nextPC[liftState_simp]:
+  "\<lbrakk>read_reg nextPC_ref\<rbrakk>\<^sub>S = readS (nextPC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_nextPC[simp]:
-  "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_nextPC[liftState_simp]:
+  "\<lbrakk>write_reg nextPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PC[simp]:
-  "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)"
+lemma liftS_read_reg_PC[liftState_simp]:
+  "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PC[simp]:
-  "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PC[liftState_simp]:
+  "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
 end
diff --git a/snapshots/isabelle/cheri/Cheri_types.thy b/snapshots/isabelle/cheri/Cheri_types.thy
index 4139164a..3f439184 100644
--- a/snapshots/isabelle/cheri/Cheri_types.thy
+++ b/snapshots/isabelle/cheri/Cheri_types.thy
@@ -5,23 +5,23 @@ theory "Cheri_types"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_string" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
 
 begin 
 
 (*Generated by Sail from cheri.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 type_synonym 'n bits =" ( 'n::len)Word.word "
 
 
@@ -35,37 +35,47 @@ datatype exception  =
 
 
 
-datatype CauseReg  =   Mk_CauseReg " ( 32 Word.word)"
+record CauseReg  = 
+ CauseReg_CauseReg_chunk_0 ::"  32 Word.word "  
 
 
 
-datatype CapCauseReg  =   Mk_CapCauseReg " ( 16 Word.word)"
+record CapCauseReg  = 
+ CapCauseReg_CapCauseReg_chunk_0 ::"  16 Word.word "  
 
 
 
-datatype TLBEntryLoReg  =   Mk_TLBEntryLoReg " ( 64 Word.word)"
+record TLBEntryLoReg  = 
+ TLBEntryLoReg_TLBEntryLoReg_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype TLBEntryHiReg  =   Mk_TLBEntryHiReg " ( 64 Word.word)"
+record TLBEntryHiReg  = 
+ TLBEntryHiReg_TLBEntryHiReg_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype ContextReg  =   Mk_ContextReg " ( 64 Word.word)"
+record ContextReg  = 
+ ContextReg_ContextReg_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype XContextReg  =   Mk_XContextReg " ( 64 Word.word)"
+record XContextReg  = 
+ XContextReg_XContextReg_chunk_0 ::"  64 Word.word "  
 
 
 
 type_synonym TLBIndexT  =" 6 bits "
 
-datatype TLBEntry  =   Mk_TLBEntry " ( 117 Word.word)"
+record TLBEntry  =
+  
+ TLBEntry_TLBEntry_chunk_1 ::"  53 Word.word " 
+ TLBEntry_TLBEntry_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype StatusReg  =   Mk_StatusReg " ( 32 Word.word)"
+record StatusReg  = 
+ StatusReg_StatusReg_chunk_0 ::"  32 Word.word "  
 
 
 
@@ -167,6 +177,10 @@ datatype WordType = B | H | W | D
 
 
 
+datatype WordTypeUnaligned = WL | WR | DL | DR
+
+
+
 type_synonym CapLen  =" int "
 
 type_synonym uint64  =" int "
@@ -244,8 +258,6 @@ datatype (plugins only: size) ast  =
   | JALR " ((regno * regno))"
   | BEQ " ((regno * regno * imm16 * bool * bool))"
   | BCMPZ " ((regno * imm16 * Comparison * bool * bool))"
-  | SYSCALL_THREAD_START " (unit)"
-  | ImplementationDefinedStopFetching " (unit)"
   | SYSCALL " (unit)"
   | BREAK " (unit)"
   | WAIT " (unit)"
@@ -262,7 +274,6 @@ datatype (plugins only: size) ast  =
   | SDL " ((regno * regno * 16 bits))"
   | SDR " ((regno * regno * 16 bits))"
   | CACHE " ((regno * regno * 16 bits))"
-  | PREF " ((regno * regno * 16 bits))"
   | SYNC " (unit)"
   | MFC0 " ((regno * regno * 3 bits * bool))"
   | HCF " (unit)"
@@ -317,7 +328,7 @@ datatype (plugins only: size) ast  =
   | CLoad " ((regno * regno * regno * 8 bits * bool * WordType * bool))"
   | CStore " ((regno * regno * regno * regno * 8 bits * WordType * bool))"
   | CSC " ((regno * regno * regno * regno * 11 bits * bool))"
-  | CLC " ((regno * regno * regno * 11 bits * bool))"
+  | CLC " ((regno * regno * regno * 16 bits * bool))"
   | C2Dump " (regno)"
   | RI " (unit)"
 
@@ -367,6 +378,7 @@ datatype register_value  =
   | Regval_vector_1_dec_bit " ( 1 Word.word)"
   | Regval_vector_257_dec_bit " ( 257 Word.word)"
   | Regval_vector_32_dec_bit " ( 32 Word.word)"
+  | Regval_vector_3_dec_bit " ( 3 Word.word)"
   | Regval_vector_64_dec_bit " ( 64 Word.word)"
   | Regval_vector_6_dec_bit " ( 6 Word.word)"
   | Regval_vector_8_dec_bit " ( 8 Word.word)"
@@ -379,6 +391,16 @@ record regstate  =
 
      CapCause ::" CapCauseReg " 
 
+     EPCC ::"  257 Word.word " 
+
+     KDC ::"  257 Word.word " 
+
+     KCC ::"  257 Word.word " 
+
+     KR2C ::"  257 Word.word " 
+
+     KR1C ::"  257 Word.word " 
+
      CTLSP ::"  257 Word.word " 
 
      CTLSU ::"  257 Word.word " 
@@ -445,7 +467,7 @@ record regstate  =
 
      C01 ::"  257 Word.word " 
 
-     C00 ::"  257 Word.word " 
+     DDC ::"  257 Word.word " 
 
      inCCallDelay ::"  1 Word.word " 
 
@@ -477,6 +499,8 @@ record regstate  =
 
      CP0Status ::" StatusReg " 
 
+     CP0ConfigK0 ::"  3 Word.word " 
+
      CP0UserLocal ::"  64 Word.word " 
 
      CP0HWREna ::"  32 Word.word " 
@@ -657,7 +681,7 @@ record regstate  =
 
 fun CapCauseReg_of_regval  :: " register_value \<Rightarrow>(CapCauseReg)option "  where 
      " CapCauseReg_of_regval (Regval_CapCauseReg (v)) = ( Some v )"
-|" CapCauseReg_of_regval g__114 = ( None )"
+|" CapCauseReg_of_regval g__16 = ( None )"
 
 
 (*val regval_of_CapCauseReg : CapCauseReg -> register_value*)
@@ -670,7 +694,7 @@ definition regval_of_CapCauseReg  :: " CapCauseReg \<Rightarrow> register_value
 
 fun CauseReg_of_regval  :: " register_value \<Rightarrow>(CauseReg)option "  where 
      " CauseReg_of_regval (Regval_CauseReg (v)) = ( Some v )"
-|" CauseReg_of_regval g__113 = ( None )"
+|" CauseReg_of_regval g__15 = ( None )"
 
 
 (*val regval_of_CauseReg : CauseReg -> register_value*)
@@ -683,7 +707,7 @@ definition regval_of_CauseReg  :: " CauseReg \<Rightarrow> register_value "  whe
 
 fun ContextReg_of_regval  :: " register_value \<Rightarrow>(ContextReg)option "  where 
      " ContextReg_of_regval (Regval_ContextReg (v)) = ( Some v )"
-|" ContextReg_of_regval g__112 = ( None )"
+|" ContextReg_of_regval g__14 = ( None )"
 
 
 (*val regval_of_ContextReg : ContextReg -> register_value*)
@@ -696,7 +720,7 @@ definition regval_of_ContextReg  :: " ContextReg \<Rightarrow> register_value "
 
 fun StatusReg_of_regval  :: " register_value \<Rightarrow>(StatusReg)option "  where 
      " StatusReg_of_regval (Regval_StatusReg (v)) = ( Some v )"
-|" StatusReg_of_regval g__111 = ( None )"
+|" StatusReg_of_regval g__13 = ( None )"
 
 
 (*val regval_of_StatusReg : StatusReg -> register_value*)
@@ -709,7 +733,7 @@ definition regval_of_StatusReg  :: " StatusReg \<Rightarrow> register_value "  w
 
 fun TLBEntry_of_regval  :: " register_value \<Rightarrow>(TLBEntry)option "  where 
      " TLBEntry_of_regval (Regval_TLBEntry (v)) = ( Some v )"
-|" TLBEntry_of_regval g__110 = ( None )"
+|" TLBEntry_of_regval g__12 = ( None )"
 
 
 (*val regval_of_TLBEntry : TLBEntry -> register_value*)
@@ -722,7 +746,7 @@ definition regval_of_TLBEntry  :: " TLBEntry \<Rightarrow> register_value "  whe
 
 fun TLBEntryHiReg_of_regval  :: " register_value \<Rightarrow>(TLBEntryHiReg)option "  where 
      " TLBEntryHiReg_of_regval (Regval_TLBEntryHiReg (v)) = ( Some v )"
-|" TLBEntryHiReg_of_regval g__109 = ( None )"
+|" TLBEntryHiReg_of_regval g__11 = ( None )"
 
 
 (*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*)
@@ -735,7 +759,7 @@ definition regval_of_TLBEntryHiReg  :: " TLBEntryHiReg \<Rightarrow> register_va
 
 fun TLBEntryLoReg_of_regval  :: " register_value \<Rightarrow>(TLBEntryLoReg)option "  where 
      " TLBEntryLoReg_of_regval (Regval_TLBEntryLoReg (v)) = ( Some v )"
-|" TLBEntryLoReg_of_regval g__108 = ( None )"
+|" TLBEntryLoReg_of_regval g__10 = ( None )"
 
 
 (*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*)
@@ -748,7 +772,7 @@ definition regval_of_TLBEntryLoReg  :: " TLBEntryLoReg \<Rightarrow> register_va
 
 fun XContextReg_of_regval  :: " register_value \<Rightarrow>(XContextReg)option "  where 
      " XContextReg_of_regval (Regval_XContextReg (v)) = ( Some v )"
-|" XContextReg_of_regval g__107 = ( None )"
+|" XContextReg_of_regval g__9 = ( None )"
 
 
 (*val regval_of_XContextReg : XContextReg -> register_value*)
@@ -761,7 +785,7 @@ definition regval_of_XContextReg  :: " XContextReg \<Rightarrow> register_value
 
 fun int_of_regval  :: " register_value \<Rightarrow>(int)option "  where 
      " int_of_regval (Regval_int (v)) = ( Some v )"
-|" int_of_regval g__106 = ( None )"
+|" int_of_regval g__8 = ( None )"
 
 
 (*val regval_of_int : ii -> register_value*)
@@ -774,7 +798,7 @@ definition regval_of_int  :: " int \<Rightarrow> register_value "  where
 
 fun vector_16_dec_bit_of_regval  :: " register_value \<Rightarrow>((16)Word.word)option "  where 
      " vector_16_dec_bit_of_regval (Regval_vector_16_dec_bit (v)) = ( Some v )"
-|" vector_16_dec_bit_of_regval g__105 = ( None )"
+|" vector_16_dec_bit_of_regval g__7 = ( None )"
 
 
 (*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*)
@@ -787,7 +811,7 @@ definition regval_of_vector_16_dec_bit  :: "(16)Word.word \<Rightarrow> register
 
 fun vector_1_dec_bit_of_regval  :: " register_value \<Rightarrow>((1)Word.word)option "  where 
      " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )"
-|" vector_1_dec_bit_of_regval g__104 = ( None )"
+|" vector_1_dec_bit_of_regval g__6 = ( None )"
 
 
 (*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*)
@@ -800,7 +824,7 @@ definition regval_of_vector_1_dec_bit  :: "(1)Word.word \<Rightarrow> register_v
 
 fun vector_257_dec_bit_of_regval  :: " register_value \<Rightarrow>((257)Word.word)option "  where 
      " vector_257_dec_bit_of_regval (Regval_vector_257_dec_bit (v)) = ( Some v )"
-|" vector_257_dec_bit_of_regval g__103 = ( None )"
+|" vector_257_dec_bit_of_regval g__5 = ( None )"
 
 
 (*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*)
@@ -813,7 +837,7 @@ definition regval_of_vector_257_dec_bit  :: "(257)Word.word \<Rightarrow> regist
 
 fun vector_32_dec_bit_of_regval  :: " register_value \<Rightarrow>((32)Word.word)option "  where 
      " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )"
-|" vector_32_dec_bit_of_regval g__102 = ( None )"
+|" vector_32_dec_bit_of_regval g__4 = ( None )"
 
 
 (*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
@@ -822,11 +846,24 @@ definition regval_of_vector_32_dec_bit  :: "(32)Word.word \<Rightarrow> register
      " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )"
 
 
+(*val vector_3_dec_bit_of_regval : register_value -> maybe (mword ty3)*)
+
+fun vector_3_dec_bit_of_regval  :: " register_value \<Rightarrow>((3)Word.word)option "  where 
+     " vector_3_dec_bit_of_regval (Regval_vector_3_dec_bit (v)) = ( Some v )"
+|" vector_3_dec_bit_of_regval g__3 = ( None )"
+
+
+(*val regval_of_vector_3_dec_bit : mword ty3 -> register_value*)
+
+definition regval_of_vector_3_dec_bit  :: "(3)Word.word \<Rightarrow> register_value "  where 
+     " regval_of_vector_3_dec_bit v = ( Regval_vector_3_dec_bit v )"
+
+
 (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
 
 fun vector_64_dec_bit_of_regval  :: " register_value \<Rightarrow>((64)Word.word)option "  where 
      " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )"
-|" vector_64_dec_bit_of_regval g__101 = ( None )"
+|" vector_64_dec_bit_of_regval g__2 = ( None )"
 
 
 (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
@@ -839,7 +876,7 @@ definition regval_of_vector_64_dec_bit  :: "(64)Word.word \<Rightarrow> register
 
 fun vector_6_dec_bit_of_regval  :: " register_value \<Rightarrow>((6)Word.word)option "  where 
      " vector_6_dec_bit_of_regval (Regval_vector_6_dec_bit (v)) = ( Some v )"
-|" vector_6_dec_bit_of_regval g__100 = ( None )"
+|" vector_6_dec_bit_of_regval g__1 = ( None )"
 
 
 (*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*)
@@ -852,7 +889,7 @@ definition regval_of_vector_6_dec_bit  :: "(6)Word.word \<Rightarrow> register_v
 
 fun vector_8_dec_bit_of_regval  :: " register_value \<Rightarrow>((8)Word.word)option "  where 
      " vector_8_dec_bit_of_regval (Regval_vector_8_dec_bit (v)) = ( Some v )"
-|" vector_8_dec_bit_of_regval g__99 = ( None )"
+|" vector_8_dec_bit_of_regval g__0 = ( None )"
 
 
 (*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*)
@@ -894,7 +931,10 @@ definition regval_of_list  :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a
 (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
 definition option_of_regval  :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option "  where 
      " option_of_regval of_regval1 = ( \<lambda>x .  
-  (case  x of   Regval_option v => map_option of_regval1 v | _ => None ) )"
+  (case  x of
+        Regval_option v => Some (Option.bind v of_regval1)
+    | _ => None
+  ) )"
 
 
 (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
@@ -921,6 +961,33 @@ definition CapCause_ref  :: "((regstate),(register_value),(CapCauseReg))register
   regval_of = (\<lambda> v .  regval_of_CapCauseReg v) |) )"
 
 
+definition KDC_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " KDC_ref = ( (|
+  name = (''KDC''),
+  read_from = (\<lambda> s . (KDC   s)),
+  write_to = (\<lambda> v s .  (( s (| KDC := v |)))),
+  of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
+
+
+definition KR2C_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " KR2C_ref = ( (|
+  name = (''KR2C''),
+  read_from = (\<lambda> s . (KR2C   s)),
+  write_to = (\<lambda> v s .  (( s (| KR2C := v |)))),
+  of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
+
+
+definition KR1C_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " KR1C_ref = ( (|
+  name = (''KR1C''),
+  read_from = (\<lambda> s . (KR1C   s)),
+  write_to = (\<lambda> v s .  (( s (| KR1C := v |)))),
+  of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
+
+
 definition CTLSP_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
      " CTLSP_ref = ( (|
   name = (''CTLSP''),
@@ -939,6 +1006,15 @@ definition CTLSU_ref  :: "((regstate),(register_value),((257)Word.word))register
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
 
+definition C31_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " C31_ref = ( (|
+  name = (''C31''),
+  read_from = (\<lambda> s . (C31   s)),
+  write_to = (\<lambda> v s .  (( s (| C31 := v |)))),
+  of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
+
+
 definition C30_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
      " C30_ref = ( (|
   name = (''C30''),
@@ -948,6 +1024,15 @@ definition C30_ref  :: "((regstate),(register_value),((257)Word.word))register_r
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
 
+definition C29_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " C29_ref = ( (|
+  name = (''C29''),
+  read_from = (\<lambda> s . (C29   s)),
+  write_to = (\<lambda> v s .  (( s (| C29 := v |)))),
+  of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
+
+
 definition C28_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
      " C28_ref = ( (|
   name = (''C28''),
@@ -1200,11 +1285,11 @@ definition C01_ref  :: "((regstate),(register_value),((257)Word.word))register_r
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
 
-definition C00_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
-     " C00_ref = ( (|
-  name = (''C00''),
-  read_from = (\<lambda> s . (C00   s)),
-  write_to = (\<lambda> v s .  (( s (| C00 := v |)))),
+definition DDC_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " DDC_ref = ( (|
+  name = (''DDC''),
+  read_from = (\<lambda> s . (DDC   s)),
+  write_to = (\<lambda> v s .  (( s (| DDC := v |)))),
   of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
@@ -1245,20 +1330,20 @@ definition PCC_ref  :: "((regstate),(register_value),((257)Word.word))register_r
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
 
-definition C31_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
-     " C31_ref = ( (|
-  name = (''C31''),
-  read_from = (\<lambda> s . (C31   s)),
-  write_to = (\<lambda> v s .  (( s (| C31 := v |)))),
+definition KCC_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " KCC_ref = ( (|
+  name = (''KCC''),
+  read_from = (\<lambda> s . (KCC   s)),
+  write_to = (\<lambda> v s .  (( s (| KCC := v |)))),
   of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
 
-definition C29_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
-     " C29_ref = ( (|
-  name = (''C29''),
-  read_from = (\<lambda> s . (C29   s)),
-  write_to = (\<lambda> v s .  (( s (| C29 := v |)))),
+definition EPCC_ref  :: "((regstate),(register_value),((257)Word.word))register_ref "  where 
+     " EPCC_ref = ( (|
+  name = (''EPCC''),
+  read_from = (\<lambda> s . (EPCC   s)),
+  write_to = (\<lambda> v s .  (( s (| EPCC := v |)))),
   of_regval = (\<lambda> v .  vector_257_dec_bit_of_regval v),
   regval_of = (\<lambda> v .  regval_of_vector_257_dec_bit v) |) )"
 
@@ -1362,6 +1447,15 @@ definition CP0Status_ref  :: "((regstate),(register_value),(StatusReg))register_
   regval_of = (\<lambda> v .  regval_of_StatusReg v) |) )"
 
 
+definition CP0ConfigK0_ref  :: "((regstate),(register_value),((3)Word.word))register_ref "  where 
+     " CP0ConfigK0_ref = ( (|
+  name = (''CP0ConfigK0''),
+  read_from = (\<lambda> s . (CP0ConfigK0   s)),
+  write_to = (\<lambda> v s .  (( s (| CP0ConfigK0 := v |)))),
+  of_regval = (\<lambda> v .  vector_3_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_3_dec_bit v) |) )"
+
+
 definition CP0UserLocal_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
      " CP0UserLocal_ref = ( (|
   name = (''CP0UserLocal''),
@@ -2141,9 +2235,14 @@ definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register
      " get_regval reg_name s = (
   if reg_name = (''instCount'') then Some ((regval_of   instCount_ref) ((read_from   instCount_ref) s)) else
   if reg_name = (''CapCause'') then Some ((regval_of   CapCause_ref) ((read_from   CapCause_ref) s)) else
+  if reg_name = (''KDC'') then Some ((regval_of   KDC_ref) ((read_from   KDC_ref) s)) else
+  if reg_name = (''KR2C'') then Some ((regval_of   KR2C_ref) ((read_from   KR2C_ref) s)) else
+  if reg_name = (''KR1C'') then Some ((regval_of   KR1C_ref) ((read_from   KR1C_ref) s)) else
   if reg_name = (''CTLSP'') then Some ((regval_of   CTLSP_ref) ((read_from   CTLSP_ref) s)) else
   if reg_name = (''CTLSU'') then Some ((regval_of   CTLSU_ref) ((read_from   CTLSU_ref) s)) else
+  if reg_name = (''C31'') then Some ((regval_of   C31_ref) ((read_from   C31_ref) s)) else
   if reg_name = (''C30'') then Some ((regval_of   C30_ref) ((read_from   C30_ref) s)) else
+  if reg_name = (''C29'') then Some ((regval_of   C29_ref) ((read_from   C29_ref) s)) else
   if reg_name = (''C28'') then Some ((regval_of   C28_ref) ((read_from   C28_ref) s)) else
   if reg_name = (''C27'') then Some ((regval_of   C27_ref) ((read_from   C27_ref) s)) else
   if reg_name = (''C26'') then Some ((regval_of   C26_ref) ((read_from   C26_ref) s)) else
@@ -2172,13 +2271,13 @@ definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register
   if reg_name = (''C03'') then Some ((regval_of   C03_ref) ((read_from   C03_ref) s)) else
   if reg_name = (''C02'') then Some ((regval_of   C02_ref) ((read_from   C02_ref) s)) else
   if reg_name = (''C01'') then Some ((regval_of   C01_ref) ((read_from   C01_ref) s)) else
-  if reg_name = (''C00'') then Some ((regval_of   C00_ref) ((read_from   C00_ref) s)) else
+  if reg_name = (''DDC'') then Some ((regval_of   DDC_ref) ((read_from   DDC_ref) s)) else
   if reg_name = (''inCCallDelay'') then Some ((regval_of   inCCallDelay_ref) ((read_from   inCCallDelay_ref) s)) else
   if reg_name = (''nextPCC'') then Some ((regval_of   nextPCC_ref) ((read_from   nextPCC_ref) s)) else
   if reg_name = (''delayedPCC'') then Some ((regval_of   delayedPCC_ref) ((read_from   delayedPCC_ref) s)) else
   if reg_name = (''PCC'') then Some ((regval_of   PCC_ref) ((read_from   PCC_ref) s)) else
-  if reg_name = (''C31'') then Some ((regval_of   C31_ref) ((read_from   C31_ref) s)) else
-  if reg_name = (''C29'') then Some ((regval_of   C29_ref) ((read_from   C29_ref) s)) else
+  if reg_name = (''KCC'') then Some ((regval_of   KCC_ref) ((read_from   KCC_ref) s)) else
+  if reg_name = (''EPCC'') then Some ((regval_of   EPCC_ref) ((read_from   EPCC_ref) s)) else
   if reg_name = (''UART_RVALID'') then Some ((regval_of   UART_RVALID_ref) ((read_from   UART_RVALID_ref) s)) else
   if reg_name = (''UART_RDATA'') then Some ((regval_of   UART_RDATA_ref) ((read_from   UART_RDATA_ref) s)) else
   if reg_name = (''UART_WRITTEN'') then Some ((regval_of   UART_WRITTEN_ref) ((read_from   UART_WRITTEN_ref) s)) else
@@ -2190,6 +2289,7 @@ definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register
   if reg_name = (''inBranchDelay'') then Some ((regval_of   inBranchDelay_ref) ((read_from   inBranchDelay_ref) s)) else
   if reg_name = (''branchPending'') then Some ((regval_of   branchPending_ref) ((read_from   branchPending_ref) s)) else
   if reg_name = (''CP0Status'') then Some ((regval_of   CP0Status_ref) ((read_from   CP0Status_ref) s)) else
+  if reg_name = (''CP0ConfigK0'') then Some ((regval_of   CP0ConfigK0_ref) ((read_from   CP0ConfigK0_ref) s)) else
   if reg_name = (''CP0UserLocal'') then Some ((regval_of   CP0UserLocal_ref) ((read_from   CP0UserLocal_ref) s)) else
   if reg_name = (''CP0HWREna'') then Some ((regval_of   CP0HWREna_ref) ((read_from   CP0HWREna_ref) s)) else
   if reg_name = (''CP0Count'') then Some ((regval_of   CP0Count_ref) ((read_from   CP0Count_ref) s)) else
@@ -2284,9 +2384,14 @@ definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> re
      " set_regval reg_name v s = (
   if reg_name = (''instCount'') then map_option (\<lambda> v . (write_to   instCount_ref) v s) ((of_regval   instCount_ref) v) else
   if reg_name = (''CapCause'') then map_option (\<lambda> v . (write_to   CapCause_ref) v s) ((of_regval   CapCause_ref) v) else
+  if reg_name = (''KDC'') then map_option (\<lambda> v . (write_to   KDC_ref) v s) ((of_regval   KDC_ref) v) else
+  if reg_name = (''KR2C'') then map_option (\<lambda> v . (write_to   KR2C_ref) v s) ((of_regval   KR2C_ref) v) else
+  if reg_name = (''KR1C'') then map_option (\<lambda> v . (write_to   KR1C_ref) v s) ((of_regval   KR1C_ref) v) else
   if reg_name = (''CTLSP'') then map_option (\<lambda> v . (write_to   CTLSP_ref) v s) ((of_regval   CTLSP_ref) v) else
   if reg_name = (''CTLSU'') then map_option (\<lambda> v . (write_to   CTLSU_ref) v s) ((of_regval   CTLSU_ref) v) else
+  if reg_name = (''C31'') then map_option (\<lambda> v . (write_to   C31_ref) v s) ((of_regval   C31_ref) v) else
   if reg_name = (''C30'') then map_option (\<lambda> v . (write_to   C30_ref) v s) ((of_regval   C30_ref) v) else
+  if reg_name = (''C29'') then map_option (\<lambda> v . (write_to   C29_ref) v s) ((of_regval   C29_ref) v) else
   if reg_name = (''C28'') then map_option (\<lambda> v . (write_to   C28_ref) v s) ((of_regval   C28_ref) v) else
   if reg_name = (''C27'') then map_option (\<lambda> v . (write_to   C27_ref) v s) ((of_regval   C27_ref) v) else
   if reg_name = (''C26'') then map_option (\<lambda> v . (write_to   C26_ref) v s) ((of_regval   C26_ref) v) else
@@ -2315,13 +2420,13 @@ definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> re
   if reg_name = (''C03'') then map_option (\<lambda> v . (write_to   C03_ref) v s) ((of_regval   C03_ref) v) else
   if reg_name = (''C02'') then map_option (\<lambda> v . (write_to   C02_ref) v s) ((of_regval   C02_ref) v) else
   if reg_name = (''C01'') then map_option (\<lambda> v . (write_to   C01_ref) v s) ((of_regval   C01_ref) v) else
-  if reg_name = (''C00'') then map_option (\<lambda> v . (write_to   C00_ref) v s) ((of_regval   C00_ref) v) else
+  if reg_name = (''DDC'') then map_option (\<lambda> v . (write_to   DDC_ref) v s) ((of_regval   DDC_ref) v) else
   if reg_name = (''inCCallDelay'') then map_option (\<lambda> v . (write_to   inCCallDelay_ref) v s) ((of_regval   inCCallDelay_ref) v) else
   if reg_name = (''nextPCC'') then map_option (\<lambda> v . (write_to   nextPCC_ref) v s) ((of_regval   nextPCC_ref) v) else
   if reg_name = (''delayedPCC'') then map_option (\<lambda> v . (write_to   delayedPCC_ref) v s) ((of_regval   delayedPCC_ref) v) else
   if reg_name = (''PCC'') then map_option (\<lambda> v . (write_to   PCC_ref) v s) ((of_regval   PCC_ref) v) else
-  if reg_name = (''C31'') then map_option (\<lambda> v . (write_to   C31_ref) v s) ((of_regval   C31_ref) v) else
-  if reg_name = (''C29'') then map_option (\<lambda> v . (write_to   C29_ref) v s) ((of_regval   C29_ref) v) else
+  if reg_name = (''KCC'') then map_option (\<lambda> v . (write_to   KCC_ref) v s) ((of_regval   KCC_ref) v) else
+  if reg_name = (''EPCC'') then map_option (\<lambda> v . (write_to   EPCC_ref) v s) ((of_regval   EPCC_ref) v) else
   if reg_name = (''UART_RVALID'') then map_option (\<lambda> v . (write_to   UART_RVALID_ref) v s) ((of_regval   UART_RVALID_ref) v) else
   if reg_name = (''UART_RDATA'') then map_option (\<lambda> v . (write_to   UART_RDATA_ref) v s) ((of_regval   UART_RDATA_ref) v) else
   if reg_name = (''UART_WRITTEN'') then map_option (\<lambda> v . (write_to   UART_WRITTEN_ref) v s) ((of_regval   UART_WRITTEN_ref) v) else
@@ -2333,6 +2438,7 @@ definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> re
   if reg_name = (''inBranchDelay'') then map_option (\<lambda> v . (write_to   inBranchDelay_ref) v s) ((of_regval   inBranchDelay_ref) v) else
   if reg_name = (''branchPending'') then map_option (\<lambda> v . (write_to   branchPending_ref) v s) ((of_regval   branchPending_ref) v) else
   if reg_name = (''CP0Status'') then map_option (\<lambda> v . (write_to   CP0Status_ref) v s) ((of_regval   CP0Status_ref) v) else
+  if reg_name = (''CP0ConfigK0'') then map_option (\<lambda> v . (write_to   CP0ConfigK0_ref) v s) ((of_regval   CP0ConfigK0_ref) v) else
   if reg_name = (''CP0UserLocal'') then map_option (\<lambda> v . (write_to   CP0UserLocal_ref) v s) ((of_regval   CP0UserLocal_ref) v) else
   if reg_name = (''CP0HWREna'') then map_option (\<lambda> v . (write_to   CP0HWREna_ref) v s) ((of_regval   CP0HWREna_ref) v) else
   if reg_name = (''CP0Count'') then map_option (\<lambda> v . (write_to   CP0Count_ref) v s) ((of_regval   CP0Count_ref) v) else
@@ -2427,6 +2533,6 @@ definition register_accessors  :: "(string \<Rightarrow> regstate \<Rightarrow>(
 
 
 
-type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR "
-type_synonym 'a M =" (register_value, 'a, exception) monad "
+type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR "
+type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad "
 end
diff --git a/snapshots/isabelle/cheri/Mips_extras.thy b/snapshots/isabelle/cheri/Mips_extras.thy
index c0379d3a..387b5ea7 100644
--- a/snapshots/isabelle/cheri/Mips_extras.thy
+++ b/snapshots/isabelle/cheri/Mips_extras.thy
@@ -1,4 +1,4 @@
-chapter \<open>Generated by Lem from /auto/homes/tb592/REMS/rems/sail/mips/mips_extras.lem.\<close>
+chapter \<open>Generated by Lem from /tmp/sail/mips/mips_extras.lem.\<close>
 
 theory "Mips_extras" 
 
@@ -6,21 +6,21 @@ imports
  	 Main
 	 "Lem_pervasives" 
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "Sail_operators" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+	 "Sail2_operators" 
 
 begin 
 
 (*open import Pervasives*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 
 (*val MEMr             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*)
 (*val MEMr_reserve     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*)
@@ -28,39 +28,39 @@ begin
 (*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*)
 
 definition MEMr  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad "              where 
-     " MEMr dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1             = ( read_mem 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 )"
+     " MEMr dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1             = ( read_mem 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1 )"
 
 definition MEMr_reserve  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad "      where 
-     " MEMr_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1     = ( read_mem 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1 )"
+     " MEMr_reserve dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1     = ( read_mem 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_reserve addr size1 )"
 
 
 (*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*)
 definition read_tag_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regval,(bool),'e)monad "  where 
-     " read_tag_bool dict_Sail_values_Bitvector_a addr = (
-  read_tag dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . 
+     " read_tag_bool dict_Sail2_values_Bitvector_a addr = (
+  read_tag dict_Sail2_values_Bitvector_a addr \<bind> (\<lambda> t . 
   maybe_fail (''read_tag_bool'') (bool_of_bitU t)))"
 
 
 (*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*)
 definition write_tag_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow>('regval,(unit),'e)monad "  where 
-     " write_tag_bool dict_Sail_values_Bitvector_a addr t = ( write_tag 
-  dict_Sail_values_Bitvector_a addr (bitU_of_bool t) \<bind>  
+     " write_tag_bool dict_Sail2_values_Bitvector_a addr t = ( write_tag 
+  dict_Sail2_values_Bitvector_a addr (bitU_of_bool t) \<bind>  
   (\<lambda>x .  (case  x of _ => return ()  )) )"
 
 
 definition MEMr_tag  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad "  where 
-     " MEMr_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = (
-  read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . 
-  read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . 
+     " MEMr_tag dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 = (
+  read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . 
+  read_tag_bool dict_Sail2_values_Bitvector_a addr \<bind> (\<lambda> t . 
   return (t, v))))"
 
 
 definition MEMr_tag_reserve  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad "  where 
-     " MEMr_tag_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = (
-  read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . 
-  read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . 
+     " MEMr_tag_reserve dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 = (
+  read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . 
+  read_tag_bool dict_Sail2_values_Bitvector_a addr \<bind> (\<lambda> t . 
   return (t, v))))"
 
 
@@ -71,21 +71,21 @@ definition MEMr_tag_reserve  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_
 (*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*)
 
 definition MEMea  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad "                  where 
-     " MEMea dict_Sail_values_Bitvector_a addr size1                 = ( write_mem_ea 
-  dict_Sail_values_Bitvector_a Write_plain addr size1 )"
+     " MEMea dict_Sail2_values_Bitvector_a addr size1                 = ( write_mem_ea 
+  dict_Sail2_values_Bitvector_a Write_plain addr size1 )"
 
 definition MEMea_conditional  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad "      where 
-     " MEMea_conditional dict_Sail_values_Bitvector_a addr size1     = ( write_mem_ea 
-  dict_Sail_values_Bitvector_a Write_conditional addr size1 )"
+     " MEMea_conditional dict_Sail2_values_Bitvector_a addr size1     = ( write_mem_ea 
+  dict_Sail2_values_Bitvector_a Write_conditional addr size1 )"
 
 
 definition MEMea_tag  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad "              where 
-     " MEMea_tag dict_Sail_values_Bitvector_a addr size1             = ( write_mem_ea 
-  dict_Sail_values_Bitvector_a Write_plain addr size1 )"
+     " MEMea_tag dict_Sail2_values_Bitvector_a addr size1             = ( write_mem_ea 
+  dict_Sail2_values_Bitvector_a Write_plain addr size1 )"
 
 definition MEMea_tag_conditional  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad "  where 
-     " MEMea_tag_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea 
-  dict_Sail_values_Bitvector_a Write_conditional addr size1 )"
+     " MEMea_tag_conditional dict_Sail2_values_Bitvector_a addr size1 = ( write_mem_ea 
+  dict_Sail2_values_Bitvector_a Write_conditional addr size1 )"
 
 
 
@@ -95,25 +95,25 @@ definition MEMea_tag_conditional  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rig
 (*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*)
 
 definition MEMval  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad "                       where 
-     " MEMval dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v                      = ( write_mem_val 
-  dict_Sail_values_Bitvector_b v \<bind>  (\<lambda>x .  (case  x of _ => return ()  )) )"
+     " MEMval dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v                      = ( write_mem_val 
+  dict_Sail2_values_Bitvector_b v \<bind>  (\<lambda>x .  (case  x of _ => return ()  )) )"
 
 definition MEMval_conditional  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad "           where 
-     " MEMval_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v          = ( write_mem_val 
-  dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b .  return (if b then True else False)))"
+     " MEMval_conditional dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v          = ( write_mem_val 
+  dict_Sail2_values_Bitvector_b v \<bind> (\<lambda> b .  return (if b then True else False)))"
 
 definition MEMval_tag  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad "              where 
-     " MEMval_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v             = ( write_mem_val 
-  dict_Sail_values_Bitvector_b v \<bind>  (\<lambda>x .  (case  x of
-                    _ => write_tag_bool dict_Sail_values_Bitvector_a addr t
+     " MEMval_tag dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v             = ( write_mem_val 
+  dict_Sail2_values_Bitvector_b v \<bind>  (\<lambda>x .  (case  x of
+                    _ => write_tag_bool dict_Sail2_values_Bitvector_a addr t
                            \<bind>
                            (\<lambda>x .  (case  x of _ => return ()  ))
                 )) )"
 
 definition MEMval_tag_conditional  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad "  where 
-     " MEMval_tag_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val 
-  dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b .  write_tag_bool 
-  dict_Sail_values_Bitvector_a addr t \<bind>  (\<lambda>x .  (case  x of _ => return (if b then True else False) ))))"
+     " MEMval_tag_conditional dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v = ( write_mem_val 
+  dict_Sail2_values_Bitvector_b v \<bind> (\<lambda> b .  write_tag_bool 
+  dict_Sail2_values_Bitvector_a addr t \<bind>  (\<lambda>x .  (case  x of _ => return (if b then True else False) ))))"
 
 
 (*val MEM_sync  : forall 'regval 'e. unit -> monad 'regval unit 'e*)
@@ -135,62 +135,45 @@ definition get_slice_int_bl  :: " int \<Rightarrow> int \<Rightarrow> int \<Righ
 
 (*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
 definition get_slice_int0  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a "  where 
-     " get_slice_int0 dict_Sail_values_Bitvector_a len n lo = (
-  (of_bools_method   dict_Sail_values_Bitvector_a) (get_slice_int_bl len n lo))"
+     " get_slice_int0 dict_Sail2_values_Bitvector_a len n lo = (
+  (of_bools_method   dict_Sail2_values_Bitvector_a) (get_slice_int_bl len n lo))"
 
 
 definition write_ram  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'b \<Rightarrow> 'a \<Rightarrow>('d,(unit),'c)monad "  where 
-     " write_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data = (
-  MEMea dict_Sail_values_Bitvector_b addr size1 \<then>
-  MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data )"
+     " write_ram dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 _ addr data = (
+  MEMea dict_Sail2_values_Bitvector_b addr size1 \<then>
+  MEMval dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a addr size1 data )"
 
 
 definition read_ram  :: " 'a Bitvector_class \<Rightarrow> 'c Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'a \<Rightarrow>('d,'c,'b)monad "  where 
-     " read_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr = ( MEMr 
-  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1 )"
+     " read_ram dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c _ size1 _ addr = ( MEMr 
+  dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c addr size1 )"
 
 
-definition string_of_bits  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string "  where 
-     " string_of_bits dict_Sail_values_Bitvector_a bs = ( string_of_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) ((bits_of_method   dict_Sail_values_Bitvector_a) bs))"
-
 definition string_of_int  :: " 'a Show_class \<Rightarrow> 'a \<Rightarrow> string "  where 
      " string_of_int dict_Show_Show_a = ((show_method   dict_Show_Show_a))"
 
 
-definition sign_extend0  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b "  where 
-     " sign_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith (
-  (of_bits_method   dict_Sail_values_Bitvector_b) (exts_bv dict_Sail_values_Bitvector_a len bits)))"
-
-definition zero_extend0  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b "  where 
-     " zero_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith (
-  (of_bits_method   dict_Sail_values_Bitvector_b) (extz_bv dict_Sail_values_Bitvector_a len bits)))"
-
-
 definition shift_bits_left  :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad "  where 
-     " shift_bits_left dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = (
+     " shift_bits_left dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n = (
   (let r = (Option.bind (
-  (unsigned_method   dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method   dict_Sail_values_Bitvector_b) (shiftl_bv dict_Sail_values_Bitvector_d v n))) in
+  (unsigned_method   dict_Sail2_values_Bitvector_e) n) (\<lambda> n . (of_bits_method   dict_Sail2_values_Bitvector_b) (shiftl_bv dict_Sail2_values_Bitvector_d v n))) in
   maybe_fail (''shift_bits_left'') r))"
 
 definition shift_bits_right  :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad "  where 
-     " shift_bits_right dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = (
+     " shift_bits_right dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n = (
   (let r = (Option.bind (
-  (unsigned_method   dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method   dict_Sail_values_Bitvector_b) (shiftr_bv dict_Sail_values_Bitvector_d v n))) in
+  (unsigned_method   dict_Sail2_values_Bitvector_e) n) (\<lambda> n . (of_bits_method   dict_Sail2_values_Bitvector_b) (shiftr_bv dict_Sail2_values_Bitvector_d v n))) in
   maybe_fail (''shift_bits_right'') r))"
 
 definition shift_bits_right_arith  :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad "  where 
-     " shift_bits_right_arith dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = (
+     " shift_bits_right_arith dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n = (
   (let r = (Option.bind (
-  (unsigned_method   dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method   dict_Sail_values_Bitvector_b) (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in
+  (unsigned_method   dict_Sail2_values_Bitvector_e) n) (\<lambda> n . (of_bits_method   dict_Sail2_values_Bitvector_b) (arith_shiftr_bv dict_Sail2_values_Bitvector_d v n))) in
   maybe_fail (''shift_bits_right_arith'') r))"
 
 
 (* Use constants for undefined values for now *)
-definition internal_pick  :: " 'a list \<Rightarrow>('c,'a,'b)monad "  where 
-     " internal_pick vs = ( return (List.hd vs))"
-
 definition undefined_string  :: " unit \<Rightarrow>('b,(string),'a)monad "  where 
      " undefined_string _ = ( return (''''))"
 
@@ -206,13 +189,13 @@ definition undefined_vector  :: " int \<Rightarrow> 'a \<Rightarrow>('rv,('a lis
 
 (*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
 definition undefined_bitvector  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad "  where 
-     " undefined_bitvector dict_Sail_values_Bitvector_a len = ( return (
-  (of_bools_method   dict_Sail_values_Bitvector_a) (repeat [False] len)))"
+     " undefined_bitvector dict_Sail2_values_Bitvector_a len = ( return (
+  (of_bools_method   dict_Sail2_values_Bitvector_a) (repeat [False] len)))"
 
 (*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
 definition undefined_bits  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad "  where 
-     " undefined_bits dict_Sail_values_Bitvector_a = ( 
-  undefined_bitvector dict_Sail_values_Bitvector_a )"
+     " undefined_bits dict_Sail2_values_Bitvector_a = ( 
+  undefined_bitvector dict_Sail2_values_Bitvector_a )"
 
 definition undefined_bit  :: " unit \<Rightarrow>('b,(bitU),'a)monad "  where 
      " undefined_bit _ = ( return B0 )"
@@ -240,12 +223,26 @@ definition elf_entry  :: " unit \<Rightarrow> int "  where
 
 
 definition print_bits  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit "  where 
-     " print_bits dict_Sail_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bits 
-  dict_Sail_values_Bitvector_a bs)))"
+     " print_bits dict_Sail2_values_Bitvector_a msg bs = ( print_endline (msg @ (string_of_bv 
+  dict_Sail2_values_Bitvector_a bs)))"
+
+definition prerr_bits  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit "  where 
+     " prerr_bits dict_Sail2_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bv 
+  dict_Sail2_values_Bitvector_a bs)))"
+
+
+(*val prerr_string : string -> unit*)
+definition prerr_string  :: " string \<Rightarrow> unit "  where 
+     " prerr_string _ = ( ()  )"
 
 
 (*val get_time_ns : unit -> integer*)
 definition get_time_ns  :: " unit \<Rightarrow> int "  where 
      " get_time_ns _ = (( 0 :: int))"
 
+
+(*val cycle_count : unit -> unit*)
+definition cycle_count  :: " unit \<Rightarrow> unit "  where 
+     " cycle_count _ = ( ()  )"
+
 end
diff --git a/snapshots/isabelle/lib/lem/Lem_basic_classes.thy b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy
index c2032dc1..c23da22b 100644
--- a/snapshots/isabelle/lib/lem/Lem_basic_classes.thy
+++ b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy
@@ -15,6 +15,7 @@ begin
 (*open import Bool*) 
 
 (*open import {coq} `Coq.Strings.Ascii`*)
+(*open import {hol} `ternaryComparisonsTheory`*)
 
 (* ========================================================================== *)
 (* Equality                                                                   *)
diff --git a/snapshots/isabelle/lib/lem/Lem_machine_word.thy b/snapshots/isabelle/lib/lem/Lem_machine_word.thy
index 3f83789c..85323bb2 100644
--- a/snapshots/isabelle/lib/lem/Lem_machine_word.thy
+++ b/snapshots/isabelle/lib/lem/Lem_machine_word.thy
@@ -8,13 +8,14 @@ imports
 	 "Lem_num" 
 	 "Lem_basic_classes" 
 	 "Lem_show" 
+	 "Lem_function" 
 	 "~~/src/HOL/Word/Word" 
 
 begin 
 
 
 
-(*open import Bool Num Basic_classes Show*)
+(*open import Bool Num Basic_classes Show Function*)
 
 (*open import {isabelle} `~~/src/HOL/Word/Word`*)
 (*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*)
diff --git a/snapshots/isabelle/lib/lem/Lem_num.thy b/snapshots/isabelle/lib/lem/Lem_num.thy
index 0d7a72ea..ddbdd533 100644
--- a/snapshots/isabelle/lib/lem/Lem_num.thy
+++ b/snapshots/isabelle/lib/lem/Lem_num.thy
@@ -16,8 +16,8 @@ begin
 
 (*open import Bool Basic_classes*)
 (*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*)
-(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*)
-(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) 
+(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory` `transcTheory`*)
+(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.QArith.Qround` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) 
 
 (*class inline ( Numeral 'a ) 
   val fromNumeral : numeral -> 'a 
diff --git a/snapshots/isabelle/lib/sail/Hoare.thy b/snapshots/isabelle/lib/sail/Hoare.thy
index ee7a5fa6..76750117 100644
--- a/snapshots/isabelle/lib/sail/Hoare.thy
+++ b/snapshots/isabelle/lib/sail/Hoare.thy
@@ -1,6 +1,6 @@
 theory Hoare
   imports
-    State_lemmas
+    Sail2_state_lemmas
     "HOL-Eisbach.Eisbach_Tools"
 begin
 
@@ -13,7 +13,7 @@ subsection \<open>Hoare triples\<close>
 
 type_synonym 'regs predS = "'regs sequential_state \<Rightarrow> bool"
 
-definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool"
+definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_\<rbrace>")
   where "PrePost P f Q \<equiv> (\<forall>s. P s \<longrightarrow> (\<forall>(r, s') \<in> f s. Q r s'))"
 
 lemma PrePostI:
@@ -42,19 +42,20 @@ lemma PrePost_weaken_post:
   shows "PrePost A f C"
   using assms by (blast intro: PrePost_consequence)
 
-named_theorems PrePost_intro
+named_theorems PrePost_compositeI
+named_theorems PrePost_atomI
 
-lemma PrePost_True_post[PrePost_intro, intro, simp]:
+lemma PrePost_True_post[PrePost_atomI, intro, simp]:
   "PrePost P m (\<lambda>_ _. True)"
   unfolding PrePost_def by auto
 
 lemma PrePost_any: "PrePost (\<lambda>s. \<forall>(r, s') \<in> m s. Q r s') m Q"
   unfolding PrePost_def by auto
 
-lemma PrePost_returnS[intro, PrePost_intro]: "PrePost (P (Value x)) (returnS x) P"
+lemma PrePost_returnS[intro, PrePost_atomI]: "PrePost (P (Value x)) (returnS x) P"
   unfolding PrePost_def returnS_def by auto
 
-lemma PrePost_bindS[intro, PrePost_intro]:
+lemma PrePost_bindS[intro, PrePost_compositeI]:
   assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePost (R a) (f a) Q"
     and m: "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R a | Ex e \<Rightarrow> Q (Ex e))"
   shows "PrePost P (bindS m f) Q"
@@ -89,10 +90,10 @@ lemma PrePost_bindS_unit:
   shows "PrePost P (bindS m f) Q"
   using assms by auto
 
-lemma PrePost_readS[intro, PrePost_intro]: "PrePost (\<lambda>s. P (Value (f s)) s) (readS f) P"
+lemma PrePost_readS[intro, PrePost_atomI]: "PrePost (\<lambda>s. P (Value (f s)) s) (readS f) P"
   unfolding PrePost_def readS_def returnS_def by auto
 
-lemma PrePost_updateS[intro, PrePost_intro]: "PrePost (\<lambda>s. P (Value ()) (f s)) (updateS f) P"
+lemma PrePost_updateS[intro, PrePost_atomI]: "PrePost (\<lambda>s. P (Value ()) (f s)) (updateS f) P"
   unfolding PrePost_def updateS_def returnS_def by auto
 
 lemma PrePost_if:
@@ -100,7 +101,7 @@ lemma PrePost_if:
   shows "PrePost P (if b then f else g) Q"
   using assms by auto
 
-lemma PrePost_if_branch[PrePost_intro]:
+lemma PrePost_if_branch[PrePost_compositeI]:
   assumes "b \<Longrightarrow> PrePost Pf f Q" and "\<not>b \<Longrightarrow> PrePost Pg g Q"
   shows "PrePost (if b then Pf else Pg) (if b then f else g) Q"
   using assms by auto
@@ -115,35 +116,65 @@ lemma PrePost_if_else:
   shows "PrePost P (if b then f else g) Q"
   using assms by auto
 
-lemma PrePost_prod_cases[PrePost_intro]:
+lemma PrePost_prod_cases[PrePost_compositeI]:
   assumes "PrePost P (f (fst x) (snd x)) Q"
   shows "PrePost P (case x of (a, b) \<Rightarrow> f a b) Q"
   using assms by (auto split: prod.splits)
 
-lemma PrePost_option_cases[PrePost_intro]:
+lemma PrePost_option_cases[PrePost_compositeI]:
   assumes "\<And>a. PrePost (PS a) (s a) Q" and "PrePost PN n Q"
   shows "PrePost (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q"
   using assms by (auto split: option.splits)
 
-lemma PrePost_let[intro, PrePost_intro]:
+lemma PrePost_let[intro, PrePost_compositeI]:
   assumes "PrePost P (m y) Q"
   shows "PrePost P (let x = y in m x) Q"
   using assms by auto
 
-lemma PrePost_assert_expS[intro, PrePost_intro]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P"
+lemma PrePost_and_boolS[PrePost_compositeI]:
+  assumes r: "PrePost R r Q"
+    and l: "PrePost P l (\<lambda>r. case r of Value True \<Rightarrow> R | _ \<Rightarrow> Q r)"
+  shows "PrePost P (and_boolS l r) Q"
+  unfolding and_boolS_def
+proof (rule PrePost_bindS)
+  fix s a s'
+  assume "(Value a, s') \<in> l s"
+  show "PrePost (if a then R else Q (Value False)) (if a then r else returnS False) Q"
+    using r by auto
+next
+  show "PrePost P l (\<lambda>r. case r of Value a \<Rightarrow> if a then R else Q (Value False) | Ex e \<Rightarrow> Q (Ex e))"
+    using l by (elim PrePost_weaken_post) (auto split: result.splits)
+qed
+
+lemma PrePost_or_boolS[PrePost_compositeI]:
+  assumes r: "PrePost R r Q"
+    and l: "PrePost P l (\<lambda>r. case r of Value False \<Rightarrow> R | _ \<Rightarrow> Q r)"
+  shows "PrePost P (or_boolS l r) Q"
+  unfolding or_boolS_def
+proof (rule PrePost_bindS)
+  fix s a s'
+  assume "(Value a, s') \<in> l s"
+  show "PrePost (if a then Q (Value True) else R) (if a then returnS True else r) Q"
+    using r by auto
+next
+  show "PrePost P l (\<lambda>r. case r of Value a \<Rightarrow> if a then Q (Value True) else R | Ex e \<Rightarrow> Q (Ex e))"
+    using l by (elim PrePost_weaken_post) (auto split: result.splits)
+qed
+
+lemma PrePost_assert_expS[intro, PrePost_atomI]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P"
   unfolding PrePost_def assert_expS_def by (auto simp: returnS_def failS_def)
 
-lemma PrePost_chooseS[intro, PrePost_intro]: "PrePost (\<lambda>s. \<forall>x \<in> xs. Q (Value x) s) (chooseS xs) Q"
+lemma PrePost_chooseS[intro, PrePost_atomI]: "PrePost (\<lambda>s. \<forall>x \<in> xs. Q (Value x) s) (chooseS xs) Q"
   by (auto simp: PrePost_def chooseS_def)
 
-lemma PrePost_failS[intro, PrePost_intro]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q"
+lemma PrePost_failS[intro, PrePost_atomI]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q"
   by (auto simp: PrePost_def failS_def)
 
 lemma case_result_combine[simp]:
   "(case r of Value a \<Rightarrow> Q (Value a) | Ex e \<Rightarrow> Q (Ex e)) = Q r"
   by (auto split: result.splits)
 
-lemma PrePost_foreachS_Nil[intro, simp, PrePost_intro]:
+lemma PrePost_foreachS_Nil[intro, simp, PrePost_atomI]:
   "PrePost (Q (Value vars)) (foreachS [] vars body) Q"
   by auto
 
@@ -180,7 +211,7 @@ there is an exception.
 [1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’,
 in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\<close>
 
-definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool"
+definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_ \<bar> _\<rbrace>")
   where "PrePostE P f Q E \<equiv> PrePost P f (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)"
 
 lemmas PrePost_defs = PrePost_def PrePostE_def
@@ -219,20 +250,42 @@ lemma PrePostE_weaken_post:
   shows "PrePostE A f C E"
   using assms by (blast intro: PrePostE_consequence)
 
-named_theorems PrePostE_intro
+named_theorems PrePostE_compositeI
+named_theorems PrePostE_atomI
+
+lemma PrePostE_conj_conds:
+  assumes "PrePostE P1 m Q1 E1"
+    and "PrePostE P2 m Q2 E2"
+  shows "PrePostE (\<lambda>s. P1 s \<and> P2 s) m (\<lambda>r s. Q1 r s \<and> Q2 r s) (\<lambda>e s. E1 e s \<and> E2 e s)"
+  using assms by (auto intro: PrePostE_I elim: PrePostE_elim)
+
+lemmas PrePostE_conj_conds_consequence = PrePostE_conj_conds[THEN PrePostE_consequence]
+
+lemma PrePostE_post_mp:
+  assumes "PrePostE P m Q' E"
+    and "PrePostE P m (\<lambda>r s. Q' r s \<longrightarrow> Q r s) E"
+  shows "PrePostE P m Q E"
+  using PrePostE_conj_conds[OF assms] by (auto intro: PrePostE_weaken_post)
+
+lemma PrePostE_cong:
+  assumes "\<And>s. P1 s \<longleftrightarrow> P2 s" and "\<And>s. P1 s \<Longrightarrow> m1 s = m2 s" and "\<And>r s. Q1 r s \<longleftrightarrow> Q2 r s"
+    and "\<And>e s. E1 e s \<longleftrightarrow> E2 e s"
+  shows "PrePostE P1 m1 Q1 E1 \<longleftrightarrow> PrePostE P2 m2 Q2 E2"
+  using assms unfolding PrePostE_def PrePost_def
+  by (auto split: result.splits)
 
-lemma PrePostE_True_post[PrePost_intro, intro, simp]:
+lemma PrePostE_True_post[PrePostE_atomI, intro, simp]:
   "PrePostE P m (\<lambda>_ _. True) (\<lambda>_ _. True)"
   unfolding PrePost_defs by (auto split: result.splits)
 
 lemma PrePostE_any: "PrePostE (\<lambda>s. \<forall>(r, s') \<in> m s. case r of Value a \<Rightarrow> Q a s' | Ex e \<Rightarrow> E e s') m Q E"
   by (intro PrePostE_I) auto
 
-lemma PrePostE_returnS[PrePostE_intro, intro, simp]:
+lemma PrePostE_returnS[PrePostE_atomI, intro, simp]:
   "PrePostE (P x) (returnS x) P Q"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
-lemma PrePostE_bindS[intro, PrePostE_intro]:
+lemma PrePostE_bindS[intro, PrePostE_compositeI]:
   assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePostE (R a) (f a) Q E"
     and m: "PrePostE P m R E"
   shows "PrePostE P (bindS m f) Q E"
@@ -252,13 +305,13 @@ lemma PrePostE_bindS_unit:
   shows "PrePostE P (bindS m f) Q E"
   using assms by auto
 
-lemma PrePostE_readS[PrePostE_intro, intro]: "PrePostE (\<lambda>s. Q (f s) s) (readS f) Q E"
+lemma PrePostE_readS[PrePostE_atomI, intro]: "PrePostE (\<lambda>s. Q (f s) s) (readS f) Q E"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
-lemma PrePostE_updateS[PrePostE_intro, intro]: "PrePostE (\<lambda>s. Q () (f s)) (updateS f) Q E"
+lemma PrePostE_updateS[PrePostE_atomI, intro]: "PrePostE (\<lambda>s. Q () (f s)) (updateS f) Q E"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
-lemma PrePostE_if_branch[PrePostE_intro]:
+lemma PrePostE_if_branch[PrePostE_compositeI]:
   assumes "b \<Longrightarrow> PrePostE Pf f Q E" and "\<not>b \<Longrightarrow> PrePostE Pg g Q E"
   shows "PrePostE (if b then Pf else Pg) (if b then f else g) Q E"
   using assms by (auto)
@@ -278,33 +331,93 @@ lemma PrePostE_if_else:
   shows "PrePostE P (if b then f else g) Q E"
   using assms by auto
 
-lemma PrePostE_prod_cases[PrePostE_intro]:
+lemma PrePostE_prod_cases[PrePostE_compositeI]:
   assumes "PrePostE P (f (fst x) (snd x)) Q E"
   shows "PrePostE P (case x of (a, b) \<Rightarrow> f a b) Q E"
   using assms by (auto split: prod.splits)
 
-lemma PrePostE_option_cases[PrePostE_intro]:
+lemma PrePostE_option_cases[PrePostE_compositeI]:
   assumes "\<And>a. PrePostE (PS a) (s a) Q E" and "PrePostE PN n Q E"
   shows "PrePostE (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q E"
   using assms by (auto split: option.splits)
 
-lemma PrePostE_let[PrePostE_intro]:
+lemma PrePostE_sum_cases[PrePostE_compositeI]:
+  assumes "\<And>a. PrePostE (Pl a) (l a) Q E" and "\<And>b. PrePostE (Pr b) (r b) Q E"
+  shows "PrePostE (case x of Inl a \<Rightarrow> Pl a | Inr b \<Rightarrow> Pr b) (case x of Inl a \<Rightarrow> l a | Inr b \<Rightarrow> r b) Q E"
+  using assms by (auto split: sum.splits)
+
+lemma PrePostE_let[PrePostE_compositeI]:
   assumes "PrePostE P (m y) Q E"
   shows "PrePostE P (let x = y in m x) Q E"
   using assms by auto
 
-lemma PrePostE_assert_expS[PrePostE_intro, intro]:
+lemma PrePostE_and_boolS[PrePostE_compositeI]:
+  assumes r: "PrePostE R r Q E"
+    and l: "PrePostE P l (\<lambda>r. if r then R else Q False) E"
+  shows "PrePostE P (and_boolS l r) Q E"
+  using assms unfolding PrePostE_def
+  by (intro PrePost_and_boolS) (auto elim: PrePost_weaken_post split: if_splits result.splits)
+
+lemma PrePostE_or_boolS[PrePostE_compositeI]:
+  assumes r: "PrePostE R r Q E"
+    and l: "PrePostE P l (\<lambda>r. if r then Q True else R) E"
+  shows "PrePostE P (or_boolS l r) Q E"
+  using assms unfolding PrePostE_def
+  by (intro PrePost_or_boolS) (auto elim: PrePost_weaken_post split: if_splits result.splits)
+
+lemma PrePostE_assert_expS[PrePostE_atomI, intro]:
   "PrePostE (if c then P () else Q (Failure m)) (assert_expS c m) P Q"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
-lemma PrePostE_failS[PrePost_intro, intro]:
+lemma PrePostE_failS[PrePostE_atomI, intro]:
   "PrePostE (E (Failure msg)) (failS msg) Q E"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
-lemma PrePostE_chooseS[intro, PrePostE_intro]:
+lemma PrePostE_maybe_failS[PrePostE_atomI]:
+  "PrePostE (\<lambda>s. case v of Some v \<Rightarrow> Q v s | None \<Rightarrow> E (Failure msg) s) (maybe_failS msg v) Q E"
+  by (auto simp: maybe_failS_def split: option.splits)
+
+lemma PrePostE_exitS[PrePostE_atomI, intro]: "PrePostE (E (Failure ''exit'')) (exitS msg) Q E"
+  unfolding exitS_def PrePostE_def PrePost_def failS_def by auto
+
+lemma PrePostE_chooseS[intro, PrePostE_atomI]:
   "PrePostE (\<lambda>s. \<forall>x \<in> xs. Q x s) (chooseS xs) Q E"
   unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
 
+lemma PrePostE_throwS[PrePostE_atomI]: "PrePostE (E (Throw e)) (throwS e) Q E"
+  by (intro PrePostE_I) (auto simp: throwS_def)
+
+lemma PrePostE_try_catchS[PrePostE_compositeI]:
+  assumes Ph: "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<Longrightarrow> PrePostE (Ph e) (h e) Q E"
+    and m: "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> Ph e | Failure msg \<Rightarrow> E (Failure msg))"
+  shows "PrePostE P (try_catchS m h) Q E"
+  unfolding PrePostE_def
+proof (intro PrePostI)
+  fix s r s'
+  assume "(r, s') \<in> try_catchS m h s" and P: "P s"
+  then show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'" using m
+  proof (cases rule: try_catchS_cases)
+    case (h e s'')
+    then have "Ph e s''" using P m by (auto elim!: PrePostE_elim)
+    then show ?thesis using Ph[OF h(1)] h(2) by (auto elim!: PrePostE_elim)
+  qed (auto elim!: PrePostE_elim)
+qed
+
+lemma PrePostE_catch_early_returnS[PrePostE_compositeI]:
+  assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw (Inl a) \<Rightarrow> Q a | Throw (Inr e) \<Rightarrow> E (Throw e) | Failure msg \<Rightarrow> E (Failure msg))"
+  shows "PrePostE P (catch_early_returnS m) Q E"
+  unfolding catch_early_returnS_def
+  by (rule PrePostE_try_catchS, rule PrePostE_sum_cases[OF PrePostE_returnS PrePostE_throwS])
+     (auto intro: assms)
+
+lemma PrePostE_early_returnS[PrePostE_atomI]: "PrePostE (E (Throw (Inl r))) (early_returnS r) Q E"
+  by (auto simp: early_returnS_def intro: PrePostE_throwS)
+
+lemma PrePostE_liftRS[PrePostE_compositeI]:
+  assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> E (Throw (Inr e)) | Failure msg \<Rightarrow> E (Failure msg))"
+  shows "PrePostE P (liftRS m) Q E"
+  using assms unfolding liftRS_def by (intro PrePostE_try_catchS[OF PrePostE_throwS])
+
 lemma PrePostE_foreachS_Cons:
   assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePostE (Q vars') (foreachS xs vars' body) Q E"
     and "PrePostE (Q vars) (body x vars) Q E"
@@ -317,4 +430,88 @@ lemma PrePostE_foreachS_invariant:
   using assms unfolding PrePostE_def
   by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto
 
+lemma PrePostE_untilS:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, cond, body, s)"
+    and cond: "\<And>vars. PrePostE (Inv' Q vars) (cond vars) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (Inv' Q) E"
+  shows "PrePostE (Inv Q vars) (untilS vars cond body) Q E"
+proof (unfold PrePostE_def, rule PrePostI)
+  fix s r s'
+  assume Inv_s: "Inv Q vars s" and r: "(r, s') \<in> untilS vars cond body s"
+  with dom[OF Inv_s] cond body
+  show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'"
+  proof (induction vars cond body s rule: untilS.pinduct[case_names Step])
+    case (Step vars cond body s)
+    consider
+        (Value) vars' c sb sc where "(Value vars', sb) \<in> body vars s" and "(Value c, sc) \<in> cond vars' sb"
+                                and "if c then r = Value vars' \<and> s' = sc else (r, s') \<in> untilS vars' cond body sc"
+      | (Ex) e where "(Ex e, s') \<in> bindS (body vars) cond s" and "r = Ex e"
+      using Step(1,6)
+      by (auto simp: untilS.psimps returnS_def Ex_bindS_iff elim!: bindS_cases split: if_splits; fastforce)
+    then show ?case
+    proof cases
+      case Value
+      then show ?thesis using Step.IH[OF Value(1,2) _ Step(3,4)] Step(3,4,5)
+        by (auto split: if_splits elim: PrePostE_elim)
+    next
+      case Ex
+      then show ?thesis using Step(3,4,5) by (auto elim!: bindS_cases PrePostE_elim)
+    qed
+  qed
+qed
+
+lemma PrePostE_untilS_pure_cond:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, returnS \<circ> cond, body, s)"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E"
+  shows "PrePostE (Inv Q vars) (untilS vars (returnS \<circ> cond) body) Q E"
+  using assms by (intro PrePostE_untilS) (auto simp: comp_def)
+
+lemma PrePostE_liftState_untilM:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, cond, body)"
+    and cond: "\<And>vars. PrePostE (Inv' Q vars) (liftState r (cond vars)) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (Inv' Q) E"
+  shows "PrePostE (Inv Q vars) (liftState r (untilM vars cond body)) Q E"
+proof -
+  have domS: "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" if "Inv Q vars s" for s
+    using dom that by (intro untilM_dom_untilS_dom)
+  then have "PrePostE (Inv Q vars) (untilS vars (liftState r \<circ> cond) (liftState r \<circ> body)) Q E"
+    using cond body by (auto intro: PrePostE_untilS simp: comp_def)
+  moreover have "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+    if "Inv Q vars s" for s
+    unfolding liftState_untilM[OF domS[OF that] dom[OF that]] ..
+  ultimately show ?thesis by (auto cong: PrePostE_cong)
+qed
+
+lemma PrePostE_liftState_untilM_pure_cond:
+  assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, return \<circ> cond, body)"
+    and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E"
+  shows "PrePostE (Inv Q vars) (liftState r (untilM vars (return \<circ> cond) body)) Q E"
+  using assms by (intro PrePostE_liftState_untilM) (auto simp: comp_def liftState_simp)
+
+lemma PrePostE_undefined_boolS[PrePostE_atomI]:
+  "PrePostE (\<lambda>s. \<forall>b. Q b s)
+            (undefined_boolS unit) Q E"
+  unfolding undefined_boolS_def seqS_def
+  by (auto intro: PrePostE_strengthen_pre PrePostE_chooseS)
+
+lemma PrePostE_bool_of_bitU_nondetS_any:
+  "PrePostE (\<lambda>s. \<forall>b. Q b s) (bool_of_bitU_nondetS b) Q E"
+  unfolding bool_of_bitU_nondetS_def undefined_boolS_def
+  by (cases b; simp; rule PrePostE_strengthen_pre, rule PrePostE_atomI) auto
+
+lemma PrePostE_bools_of_bits_nondetS_any:
+  "PrePostE (\<lambda>s. \<forall>bs. Q bs s) (bools_of_bits_nondetS bs) Q E"
+  unfolding bools_of_bits_nondetS_def
+  by (rule PrePostE_weaken_post[where B = "\<lambda>_ s. \<forall>bs. Q bs s"], rule PrePostE_strengthen_pre,
+      (rule PrePostE_foreachS_invariant[OF PrePostE_strengthen_pre] PrePostE_bindS PrePostE_returnS
+            PrePostE_bool_of_bitU_nondetS_any)+)
+     auto
+
+lemma PrePostE_internal_pick:
+  "xs \<noteq> [] \<Longrightarrow> PrePostE (\<lambda>s. \<forall>x \<in> set xs. Q x s) (internal_pickS xs) Q E"
+  unfolding internal_pickS_def Let_def
+  by (rule PrePostE_strengthen_pre,
+      (rule PrePostE_compositeI PrePostE_atomI PrePostE_bools_of_bits_nondetS_any)+)
+     (auto split: option.splits)
+
 end
diff --git a/snapshots/isabelle/lib/sail/Prompt.thy b/snapshots/isabelle/lib/sail/Prompt.thy
deleted file mode 100644
index 5792e575..00000000
--- a/snapshots/isabelle/lib/sail/Prompt.thy
+++ /dev/null
@@ -1,150 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/prompt.lem.\<close>
-
-theory "Prompt" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Sail_values" 
-	 "Prompt_monad" 
-	 "Prompt_monad_lemmas" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Sail_impl_base*)
-(*open import Sail_values*)
-(*open import Prompt_monad*)
-(*open import {isabelle} `Prompt_monad_lemmas`*)
-
-(*val >>= : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*)
-
-(*val >> : forall 'rv 'b 'e. monad 'rv unit 'e -> monad 'rv 'b 'e -> monad 'rv 'b 'e*)
-
-(*val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*)
-fun  iter_aux  :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " iter_aux i f (x # xs) = ( f i x \<then> iter_aux (i +( 1 :: int)) f xs )"
-|" iter_aux i f ([]) = ( return ()  )"
-
-
-(*val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*)
-definition iteri  :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " iteri f xs = ( iter_aux(( 0 :: int)) f xs )"
-
-
-(*val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*)
-definition iter  :: "('a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " iter f xs = ( iteri ( \<lambda>x .  
-  (case  x of _ => \<lambda> x .  f x )) xs )"
-
-
-(*val foreachM : forall 'a 'rv 'vars 'e.
-  list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
-fun  foreachM  :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad "  where 
-     " foreachM ([]) vars body = ( return vars )"
-|" foreachM (x # xs) vars body = (
-  body x vars \<bind> (\<lambda> vars . 
-  foreachM xs vars body))"
-
-
-(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
-definition and_boolM  :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " and_boolM l r = ( l \<bind> (\<lambda> l .  if l then r else return False))"
-
-
-(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
-definition or_boolM  :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " or_boolM l r = ( l \<bind> (\<lambda> l .  if l then return True else r))"
-
-
-(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
-definition bool_of_bitU_fail  :: " bitU \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " bool_of_bitU_fail = ( \<lambda>x .  
-  (case  x of
-        B0 => return False
-    | B1 => return True
-    | BU => Fail (''bool_of_bitU'')
-  ) )"
-
-
-(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
-definition bool_of_bitU_oracle  :: " bitU \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " bool_of_bitU_oracle = ( \<lambda>x .  
-  (case  x of
-        B0 => return False
-    | B1 => return True
-    | BU => undefined_bool () 
-  ) )"
-
-
-(*val bools_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e*)
-definition bools_of_bits_oracle  :: "(bitU)list \<Rightarrow>('rv,((bool)list),'e)monad "  where 
-     " bools_of_bits_oracle bits = (
-  foreachM bits []
-    (\<lambda> b bools . 
-      bool_of_bitU_oracle b \<bind> (\<lambda> b . 
-      return (bools @ [b]))))"
-
-
-(*val of_bits_oracle : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*)
-definition of_bits_oracle  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad "  where 
-     " of_bits_oracle dict_Sail_values_Bitvector_a bits = (
-  bools_of_bits_oracle bits \<bind> (\<lambda> bs . 
-  return ((of_bools_method   dict_Sail_values_Bitvector_a) bs)))"
-
-
-(*val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*)
-definition of_bits_fail  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad "  where 
-     " of_bits_fail dict_Sail_values_Bitvector_a bits = ( maybe_fail (''of_bits'') (
-  (of_bits_method   dict_Sail_values_Bitvector_a) bits))"
-
-
-(*val mword_oracle : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e*)
-definition mword_oracle  :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " mword_oracle _ = (
-  bools_of_bits_oracle (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \<bind> (\<lambda> bs . 
-  return (Word.of_bl bs)))"
-
-
-(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
-                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
-function (sequential,domintros)  whileM  :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad "  where 
-     " whileM vars cond body = (
-  cond vars \<bind> (\<lambda> cond_val . 
-  if cond_val then
-    body vars \<bind> (\<lambda> vars .  whileM vars cond body)
-  else return vars))" 
-by pat_completeness auto
-
-
-(*val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
-                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
-function (sequential,domintros)  untilM  :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad "  where 
-     " untilM vars cond body = (
-  body vars \<bind> (\<lambda> vars . 
-  cond vars \<bind> (\<lambda> cond_val . 
-  if cond_val then return vars else untilM vars cond body)))" 
-by pat_completeness auto
-
-
-(*let write_two_regs r1 r2 vec =
-  let is_inc =
-    let is_inc_r1 = is_inc_of_reg r1 in
-    let is_inc_r2 = is_inc_of_reg r2 in
-    let () = ensure (is_inc_r1 = is_inc_r2)
-                    write_two_regs called with vectors of different direction in
-    is_inc_r1 in
-
-  let (size_r1 : integer) = size_of_reg r1 in
-  let (start_vec : integer) = get_start vec in
-  let size_vec = length vec in
-  let r1_v =
-    if is_inc
-    then slice vec start_vec (size_r1 - start_vec - 1)
-    else slice vec start_vec (start_vec - size_r1 - 1) in
-  let r2_v =
-    if is_inc
-    then slice vec (size_r1 - start_vec) (size_vec - start_vec)
-    else slice vec (start_vec - size_r1) (start_vec - size_vec) in
-  write_reg r1 r1_v >> write_reg r2 r2_v*)
-end
diff --git a/snapshots/isabelle/lib/sail/Prompt_monad.thy b/snapshots/isabelle/lib/sail/Prompt_monad.thy
deleted file mode 100644
index e4aecfba..00000000
--- a/snapshots/isabelle/lib/sail/Prompt_monad.thy
+++ /dev/null
@@ -1,267 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/prompt_monad.lem.\<close>
-
-theory "Prompt_monad" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Sail_impl_base*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-
-type_synonym register_name =" string "
-type_synonym address =" bitU list "
-
-datatype( 'regval, 'a, 'e) monad =
-    Done " 'a "
-  (* Read a number of bytes from memory, returned in little endian order *)
-  | Read_mem " read_kind " " address " " nat " " ( memory_byte list \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Read the tag of a memory address *)
-  | Read_tag " address " " (bitU \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Tell the system a write is imminent, at address lifted, of size nat *)
-  | Write_ea " write_kind " " address " " nat " " ('regval, 'a, 'e) monad "
-  (* Request the result of store-exclusive *)
-  | Excl_res " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Request to write memory at last signalled address. Memory value should be 8
-     times the size given in ea signal, given in little endian order *)
-  | Write_memv " memory_byte list " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Request to write the tag at given address. *)
-  | Write_tag " address " " bitU " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Tell the system to dynamically recalculate dependency footprint *)
-  | Footprint " ('regval, 'a, 'e) monad "
-  (* Request a memory barrier *)
-  | Barrier " barrier_kind " " ('regval, 'a, 'e) monad "
-  (* Request to read register, will track dependency when mode.track_values *)
-  | Read_reg " register_name " " ('regval \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Request to write register *)
-  | Write_reg " register_name " " 'regval " " ('regval, 'a, 'e) monad "
-  | Undefined " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
-  (* Print debugging or tracing information *)
-  | Print " string " " ('regval, 'a, 'e) monad "
-  (*Result of a failed assert with possible error message to report*)
-  | Fail " string "
-  (* Exception of type 'e *)
-  | Exception " 'e "
-
-(*val return : forall 'rv 'a 'e. 'a -> monad 'rv 'a 'e*)
-definition return  :: " 'a \<Rightarrow>('rv,'a,'e)monad "  where 
-     " return a = ( Done a )"
-
-
-(*val bind : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*)
-function (sequential,domintros)  bind  :: "('rv,'a,'e)monad \<Rightarrow>('a \<Rightarrow>('rv,'b,'e)monad)\<Rightarrow>('rv,'b,'e)monad "  where 
-     " bind (Done a) f = ( f a )"
-|" bind (Read_mem rk a sz k) f = ( Read_mem rk a sz (\<lambda> v .  bind (k v) f))"
-|" bind (Read_tag a k) f = (       Read_tag a       (\<lambda> v .  bind (k v) f))"
-|" bind (Write_memv descr k) f = ( Write_memv descr (\<lambda> v .  bind (k v) f))"
-|" bind (Write_tag a t k) f = (    Write_tag a t    (\<lambda> v .  bind (k v) f))"
-|" bind (Read_reg descr k) f = (   Read_reg descr   (\<lambda> v .  bind (k v) f))"
-|" bind (Excl_res k) f = (         Excl_res         (\<lambda> v .  bind (k v) f))"
-|" bind (Undefined k) f = (        Undefined        (\<lambda> v .  bind (k v) f))"
-|" bind (Write_ea wk a sz k) f = ( Write_ea wk a sz (bind k f))"
-|" bind (Footprint k) f = (        Footprint        (bind k f))"
-|" bind (Barrier bk k) f = (       Barrier bk       (bind k f))"
-|" bind (Write_reg r v k) f = (    Write_reg r v    (bind k f))"
-|" bind (Print msg k) f = (        Print msg        (bind k f))"
-|" bind (Fail descr) f = (         Fail descr )"
-|" bind (Exception e) f = (        Exception e )" 
-by pat_completeness auto
-
-
-(*val exit : forall 'rv 'a 'e. unit -> monad 'rv 'a 'e*)
-definition exit0  :: " unit \<Rightarrow>('rv,'a,'e)monad "  where 
-     " exit0 _ = ( Fail (''exit''))"
-
-
-(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*)
-definition undefined_bool  :: " unit \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " undefined_bool _ = ( Undefined return )"
-
-
-(*val assert_exp : forall 'rv 'e. bool -> string -> monad 'rv unit 'e*)
-definition assert_exp  :: " bool \<Rightarrow> string \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " assert_exp exp msg = ( if exp then Done ()  else Fail msg )"
-
-
-(*val throw : forall 'rv 'a 'e. 'e -> monad 'rv 'a 'e*)
-definition throw  :: " 'e \<Rightarrow>('rv,'a,'e)monad "  where 
-     " throw e = ( Exception e )"
-
-
-(*val try_catch : forall 'rv 'a 'e1 'e2. monad 'rv 'a 'e1 -> ('e1 -> monad 'rv 'a 'e2) -> monad 'rv 'a 'e2*)
-function (sequential,domintros)  try_catch  :: "('rv,'a,'e1)monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,'e2)monad)\<Rightarrow>('rv,'a,'e2)monad "  where 
-     " try_catch (Done a) h = (             Done a )"
-|" try_catch (Read_mem rk a sz k) h = ( Read_mem rk a sz (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Read_tag a k) h = (       Read_tag a       (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Write_memv descr k) h = ( Write_memv descr (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Write_tag a t k) h = (    Write_tag a t    (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Read_reg descr k) h = (   Read_reg descr   (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Excl_res k) h = (         Excl_res         (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Undefined k) h = (        Undefined        (\<lambda> v .  try_catch (k v) h))"
-|" try_catch (Write_ea wk a sz k) h = ( Write_ea wk a sz (try_catch k h))"
-|" try_catch (Footprint k) h = (        Footprint        (try_catch k h))"
-|" try_catch (Barrier bk k) h = (       Barrier bk       (try_catch k h))"
-|" try_catch (Write_reg r v k) h = (    Write_reg r v    (try_catch k h))"
-|" try_catch (Print msg k) h = (        Print msg        (try_catch k h))"
-|" try_catch (Fail descr) h = (         Fail descr )"
-|" try_catch (Exception e) h = (        h e )" 
-by pat_completeness auto
-
-
-(* For early return, we abuse exceptions by throwing and catching
-   the return value. The exception type is either 'r 'e, where Right e
-   represents a proper exception and Left r an early return of value r. *)
-type_synonym( 'rv, 'a, 'r, 'e) monadR =" ('rv, 'a, ( ('r, 'e)sum)) monad "
-
-(*val early_return : forall 'rv 'a 'r 'e. 'r -> monadR 'rv 'a 'r 'e*)
-definition early_return  :: " 'r \<Rightarrow>('rv,'a,(('r,'e)sum))monad "  where 
-     " early_return r = ( throw (Inl r))"
-
-
-(*val catch_early_return : forall 'rv 'a 'e. monadR 'rv 'a 'a 'e -> monad 'rv 'a 'e*)
-definition catch_early_return  :: "('rv,'a,(('a,'e)sum))monad \<Rightarrow>('rv,'a,'e)monad "  where 
-     " catch_early_return m = (
-  try_catch m
-    (\<lambda>x .  (case  x of   Inl a => return a | Inr e => throw e )))"
-
-
-(* Lift to monad with early return by wrapping exceptions *)
-(*val liftR : forall 'rv 'a 'r 'e. monad 'rv 'a 'e -> monadR 'rv 'a 'r 'e*)
-definition liftR  :: "('rv,'a,'e)monad \<Rightarrow>('rv,'a,(('r,'e)sum))monad "  where 
-     " liftR m = ( try_catch m (\<lambda> e .  throw (Inr e)))"
-
-
-(* Catch exceptions in the presence of early returns *)
-(*val try_catchR : forall 'rv 'a 'r 'e1 'e2. monadR 'rv 'a 'r 'e1 -> ('e1 -> monadR 'rv 'a 'r 'e2) ->  monadR 'rv 'a 'r 'e2*)
-definition try_catchR  :: "('rv,'a,(('r,'e1)sum))monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,(('r,'e2)sum))monad)\<Rightarrow>('rv,'a,(('r,'e2)sum))monad "  where 
-     " try_catchR m h = (
-  try_catch m
-    (\<lambda>x .  (case  x of   Inl r => throw (Inl r) | Inr e => h e )))"
-
-
-(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*)
-definition maybe_fail  :: " string \<Rightarrow> 'a option \<Rightarrow>('rv,'a,'e)monad "  where 
-     " maybe_fail msg = ( \<lambda>x .  
-  (case  x of   Some a => return a | None => Fail msg ) )"
-
-
-(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*)
-definition read_mem_bytes  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,((memory_byte)list),'e)monad "  where 
-     " read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = (
-  Read_mem rk ((bits_of_method   dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) return )"
-
-
-(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*)
-definition read_mem  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,'b,'e)monad "  where 
-     " read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = (
-  bind
-    (read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_a rk addr sz)
-    (\<lambda> bytes . 
-       maybe_fail (''bits_of_mem_bytes'') (
-  (of_bits_method   dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))"
-
-
-(*val read_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bitU 'e*)
-definition read_tag  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bitU),'e)monad "  where 
-     " read_tag dict_Sail_values_Bitvector_a addr = ( Read_tag (
-  (bits_of_method   dict_Sail_values_Bitvector_a) addr) return )"
-
-
-(*val excl_result : forall 'rv 'e. unit -> monad 'rv bool 'e*)
-definition excl_result  :: " unit \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " excl_result _ = ( 
-  (let k = (\<lambda> successful .  (return successful)) in Excl_res k) )"
-
-
-(*val write_mem_ea : forall 'rv 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> monad 'rv unit 'e*)
-definition write_mem_ea  :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " write_mem_ea dict_Sail_values_Bitvector_a wk addr sz = ( Write_ea wk (
-  (bits_of_method   dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) (Done () ))"
-
-
-(*val write_mem_val : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bool 'e*)
-definition write_mem_val  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " write_mem_val dict_Sail_values_Bitvector_a v = ( (case  mem_bytes_of_bits 
-  dict_Sail_values_Bitvector_a v of
-    Some v => Write_memv v return
-  | None => Fail (''write_mem_val'')
-))"
-
-
-(*val write_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> bitU -> monad 'rv bool 'e*)
-definition write_tag  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('rv,(bool),'e)monad "  where 
-     " write_tag dict_Sail_values_Bitvector_a addr b = ( Write_tag (
-  (bits_of_method   dict_Sail_values_Bitvector_a) addr) b return )"
-
-
-(*val read_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> monad 'rv 'a 'e*)
-definition read_reg  :: "('s,'rv,'a)register_ref \<Rightarrow>('rv,'a,'e)monad "  where 
-     " read_reg reg = ( 
-  (let k = (\<lambda> v . 
-            (case (of_regval   reg) v of
-                  Some v => Done v
-              | None => Fail (''read_reg: unrecognised value'')
-            )) in Read_reg (name   reg) k) )"
-
-
-(* TODO
-val read_reg_range : forall 's 'r 'rv 'a 'e. Bitvector 'a => register_ref 's 'rv 'r -> integer -> integer -> monad 'rv 'a 'e
-let read_reg_range reg i j =
-  read_reg_aux of_bits (external_reg_slice reg (nat_of_int i,nat_of_int j))
-
-let read_reg_bit reg i =
-  read_reg_aux (fun v -> v) (external_reg_slice reg (nat_of_int i,nat_of_int i)) >>= fun v ->
-  return (extract_only_element v)
-
-let read_reg_field reg regfield =
-  read_reg_aux (external_reg_field_whole reg regfield)
-
-let read_reg_bitfield reg regfield =
-  read_reg_aux (external_reg_field_whole reg regfield) >>= fun v ->
-  return (extract_only_element v)*)
-
-definition reg_deref  :: "('d,'c,'b)register_ref \<Rightarrow>('c,'b,'a)monad "  where 
-     " reg_deref = ( read_reg )"
-
-
-(*val write_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> 'a -> monad 'rv unit 'e*)
-definition write_reg  :: "('s,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " write_reg reg v = ( Write_reg(name   reg) ((regval_of   reg) v) (Done () ))"
-
-
-(* TODO
-let write_reg reg v =
-  write_reg_aux (external_reg_whole reg) v
-let write_reg_range reg i j v =
-  write_reg_aux (external_reg_slice reg (nat_of_int i,nat_of_int j)) v
-let write_reg_pos reg i v =
-  let iN = nat_of_int i in
-  write_reg_aux (external_reg_slice reg (iN,iN)) [v]
-let write_reg_bit = write_reg_pos
-let write_reg_field reg regfield v =
-  write_reg_aux (external_reg_field_whole reg regfield.field_name) v
-let write_reg_field_bit reg regfield bit =
-  write_reg_aux (external_reg_field_whole reg regfield.field_name)
-                (Vector [bit] 0 (is_inc_of_reg reg))
-let write_reg_field_range reg regfield i j v =
-  write_reg_aux (external_reg_field_slice reg regfield.field_name (nat_of_int i,nat_of_int j)) v
-let write_reg_field_pos reg regfield i v =
-  write_reg_field_range reg regfield i i [v]
-let write_reg_field_bit = write_reg_field_pos*)
-
-(*val barrier : forall 'rv 'e. barrier_kind -> monad 'rv unit 'e*)
-definition barrier  :: " barrier_kind \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " barrier bk = ( Barrier bk (Done () ))"
-
-
-(*val footprint : forall 'rv 'e. unit -> monad 'rv unit 'e*)
-definition footprint  :: " unit \<Rightarrow>('rv,(unit),'e)monad "  where 
-     " footprint _ = ( Footprint (Done () ))"
-
-end
diff --git a/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy
deleted file mode 100644
index e883c2a0..00000000
--- a/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy
+++ /dev/null
@@ -1,170 +0,0 @@
-theory Prompt_monad_lemmas
-  imports
-    Prompt_monad
-    Sail_values_lemmas
-begin
-
-notation bind (infixr "\<bind>" 54)
-
-abbreviation seq :: "('rv,unit,'e)monad \<Rightarrow> ('rv,'b,'e)monad \<Rightarrow>('rv,'b,'e)monad" (infixr "\<then>" 54) where
-  "m \<then> n \<equiv> m \<bind> (\<lambda>_. n)"
-
-lemma All_bind_dom: "bind_dom (m, f)"
-  by (induction m) (auto intro: bind.domintros)
-
-termination bind using All_bind_dom by auto
-lemmas bind_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = bind.induct
-
-lemma bind_return[simp]: "bind (return a) f = f a"
-  by (auto simp: return_def)
-
-lemma bind_assoc[simp]: "bind (bind m f) g = bind m (\<lambda>x. bind (f x) g)"
-  by (induction m f arbitrary: g rule: bind.induct) auto
-
-lemma bind_assert_True[simp]: "bind (assert_exp True msg) f = f ()"
-  by (auto simp: assert_exp_def)
-
-lemma All_try_catch_dom: "try_catch_dom (m, h)"
-  by (induction m) (auto intro: try_catch.domintros)
-termination try_catch using All_try_catch_dom by auto
-lemmas try_catch_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = try_catch.induct
-
-datatype 'regval event =
-  (* Request to read memory *)
-    e_read_mem read_kind "bitU list" nat "memory_byte list"
-  | e_read_tag "bitU list" bitU
-  (* Write is imminent, at address lifted, of size nat *)
-  | e_write_ea write_kind "bitU list" nat
-  (* Request the result of store-exclusive *)
-  | e_excl_res bool
-  (* Request to write memory at last signalled address. Memory value should be 8
-     times the size given in ea signal *)
-  | e_write_memv "memory_byte list" bool
-  | e_write_tag "bitU list" bitU bool
-  (* Tell the system to dynamically recalculate dependency footprint *)
-  | e_footprint
-  (* Request a memory barrier *)
-  | e_barrier " barrier_kind "
-  (* Request to read register *)
-  | e_read_reg string 'regval
-  (* Request to write register *)
-  | e_write_reg string 'regval
-  | e_undefined bool
-  | e_print string
-
-inductive_set T :: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a, 'e) monad) set" where
-  Read_mem: "((Read_mem rk addr sz k), e_read_mem rk addr sz v, k v) \<in> T"
-| Read_tag: "((Read_tag addr k), e_read_tag addr v, k v) \<in> T"
-| Write_ea: "((Write_ea wk addr sz k), e_write_ea wk addr sz, k) \<in> T"
-| Excl_res: "((Excl_res k), e_excl_res r, k r) \<in> T"
-| Write_memv: "((Write_memv v k), e_write_memv v r, k r) \<in> T"
-| Write_tag: "((Write_tag a v k), e_write_tag a v r, k r) \<in> T"
-| Footprint: "((Footprint k), e_footprint, k) \<in> T"
-| Barrier: "((Barrier bk k), e_barrier bk, k) \<in> T"
-| Read_reg: "((Read_reg r k), e_read_reg r v, k v) \<in> T"
-| Write_reg: "((Write_reg r v k), e_write_reg r v, k) \<in> T"
-| Undefined : "((Undefined k), e_undefined v, k v) \<in> T"
-| Print: "((Print msg k), e_print msg, k) \<in> T"
-
-inductive_set Traces :: "(('rv, 'a, 'e) monad \<times> 'rv event list \<times> ('rv, 'a, 'e) monad) set" where
-  Nil: "(s, [], s) \<in> Traces"
-| Step: "\<lbrakk>(s, e, s'') \<in> T; (s'', t, s') \<in> Traces\<rbrakk> \<Longrightarrow> (s, e # t, s') \<in> Traces"
-
-declare Traces.intros[intro]
-declare T.intros[intro]
-
-declare prod.splits[split]
-
-lemmas Traces_ConsI = T.intros[THEN Step, rotated]
-
-inductive_cases Traces_NilE[elim]: "(s, [], s') \<in> Traces"
-inductive_cases Traces_ConsE[elim]: "(s, e # t, s') \<in> Traces"
-
-lemma Traces_cases:
-  fixes m :: "('rv, 'a, 'e) monad"
-  assumes Run: "(m, t, m') \<in> Traces"
-  obtains (Nil) a where "m = m'" and "t = []"
-  | (Read_mem) rk addr s k t' v where "m = Read_mem rk addr s k" and "t = e_read_mem rk addr s v # t'" and "(k v, t', m') \<in> Traces"
-  | (Read_tag) addr k t' v where "m = Read_tag addr k" and "t = e_read_tag addr v # t'" and "(k v, t', m') \<in> Traces"
-  | (Write_memv) val k t' v where "m = Write_memv val k" and "t = e_write_memv val v # t'" and "(k v, t', m') \<in> Traces"
-  | (Write_tag) a val k t' v where "m = Write_tag a val k" and "t = e_write_tag a val v # t'" and "(k v, t', m') \<in> Traces"
-  | (Barrier) bk k t' v where "m = Barrier bk k" and "t = e_barrier bk # t'" and "(k, t', m') \<in> Traces"
-  | (Read_reg) reg k t' v where "m = Read_reg reg k" and "t = e_read_reg reg v # t'" and "(k v, t', m') \<in> Traces"
-  | (Excl_res) k t' v where "m = Excl_res k" and "t = e_excl_res v # t'" and "(k v, t', m') \<in> Traces"
-  | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = e_write_ea wk addr s # t'" and "(k, t', m') \<in> Traces"
-  | (Footprint) k t' where "m = Footprint k" and "t = e_footprint # t'" and "(k, t', m') \<in> Traces"
-  | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = e_write_reg reg v # t'" and "(k, t', m') \<in> Traces"
-  | (Undefined) v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces"
-  | (Print) msg k t' where "m = Print msg k" and "t = e_print msg # t'" and "(k, t', m') \<in> Traces"
-proof (use Run in \<open>cases m t m' set: Traces\<close>)
-  case Nil
-  then show ?thesis by (auto intro: that(1))
-next
-  case (Step e m'' t')
-  from \<open>(m, e, m'') \<in> T\<close> and \<open>t = e # t'\<close> and \<open>(m'', t', m') \<in> Traces\<close>
-  show ?thesis by (cases m e m'' rule: T.cases; elim that; blast)
-qed
-
-abbreviation Run :: "('rv, 'a, 'e) monad \<Rightarrow> 'rv event list \<Rightarrow> 'a \<Rightarrow> bool"
-  where "Run s t a \<equiv> (s, t, Done a) \<in> Traces"
-
-lemma Run_appendI:
-  assumes "(s, t1, s') \<in> Traces"
-    and "Run s' t2 a"
-  shows "Run s (t1 @ t2) a"
-proof (use assms in \<open>induction t1 arbitrary: s\<close>)
-  case (Cons e t1)
-  then show ?case by (elim Traces_ConsE) auto
-qed auto
-
-lemma bind_DoneE:
-  assumes "bind m f = Done a"
-  obtains a' where "m = Done a'" and "f a' = Done a"
-  using assms by (auto elim: bind.elims)
-
-lemma bind_T_cases:
-  assumes "(bind m f, e, s') \<in> T"
-  obtains (Done) a where "m = Done a"
-  | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T"
-  using assms by (cases; blast elim: bind.elims)
-
-lemma Run_bindE:
-  fixes m :: "('rv, 'b, 'e) monad" and a :: 'a
-  assumes "Run (bind m f) t a"
-  obtains tm am tf where "t = tm @ tf" and "Run m tm am" and "Run (f am) tf a"
-proof (use assms in \<open>induction "bind m f" t "Done a :: ('rv, 'a, 'e) monad" arbitrary: m rule: Traces.induct\<close>)
-  case Nil
-  obtain am where "m = Done am" and "f am = Done a" using Nil(1) by (elim bind_DoneE)
-  then show ?case by (intro Nil(2)) auto
-next
-  case (Step e s'' t m)
-  show thesis using Step(1)
-  proof (cases rule: bind_T_cases)
-    case (Done am)
-    then show ?thesis using Step(1,2) by (intro Step(4)[of "[]" "e # t" am]) auto
-  next
-    case (Bind m')
-    show ?thesis proof (rule Step(3)[OF Bind(1)])
-      fix tm tf am
-      assume "t = tm @ tf" and "Run m' tm am" and "Run (f am) tf a"
-      then show thesis using Bind by (intro Step(4)[of "e # tm" tf am]) auto
-    qed
-  qed
-qed
-
-lemma Run_DoneE:
-  assumes "Run (Done a) t a'"
-  obtains "t = []" and "a' = a"
-  using assms by (auto elim: Traces.cases T.cases)
-
-lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a"
-  by (auto elim: Run_DoneE)
-
-lemma bind_cong[fundef_cong]:
-  assumes m: "m1 = m2"
-    and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a"
-  shows "bind m1 f1 = bind m2 f2"
-  unfolding m using f
-  by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast)
-
-end
diff --git a/snapshots/isabelle/lib/sail/ROOT b/snapshots/isabelle/lib/sail/ROOT
index 3189f216..6bdedc43 100644
--- a/snapshots/isabelle/lib/sail/ROOT
+++ b/snapshots/isabelle/lib/sail/ROOT
@@ -3,9 +3,10 @@ session "Sail" = "LEM" +
   sessions
     "HOL-Eisbach"
   theories
-    Sail_values_lemmas
-    Prompt
-    State_lemmas
-    Sail_operators_mwords_lemmas
-    Sail_operators_bitlists
+    Sail2_values_lemmas
+    Sail2_prompt
+    Sail2_state_lemmas
+    Sail2_operators_mwords_lemmas
+    Sail2_operators_bitlists
+    Sail2_string
     Hoare
diff --git a/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy b/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
new file mode 100644
index 00000000..7f9fc60b
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
@@ -0,0 +1,514 @@
+chapter \<open>Generated by Lem from ../../src/lem_interp/sail2_instr_kinds.lem.\<close>
+
+theory "Sail2_instr_kinds" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+
+begin 
+
+(*========================================================================*)
+(*     Sail                                                               *)
+(*                                                                        *)
+(*  Copyright (c) 2013-2017                                               *)
+(*    Kathyrn Gray                                                        *)
+(*    Shaked Flur                                                         *)
+(*    Stephen Kell                                                        *)
+(*    Gabriel Kerneis                                                     *)
+(*    Robert Norton-Wright                                                *)
+(*    Christopher Pulte                                                   *)
+(*    Peter Sewell                                                        *)
+(*    Alasdair Armstrong                                                  *)
+(*    Brian Campbell                                                      *)
+(*    Thomas Bauereiss                                                    *)
+(*    Anthony Fox                                                         *)
+(*    Jon French                                                          *)
+(*    Dominic Mulligan                                                    *)
+(*    Stephen Kell                                                        *)
+(*    Mark Wassell                                                        *)
+(*                                                                        *)
+(*  All rights reserved.                                                  *)
+(*                                                                        *)
+(*  This software was developed by the University of Cambridge Computer   *)
+(*  Laboratory as part of the Rigorous Engineering of Mainstream Systems  *)
+(*  (REMS) project, funded by EPSRC grant EP/K008528/1.                   *)
+(*                                                                        *)
+(*  Redistribution and use in source and binary forms, with or without    *)
+(*  modification, are permitted provided that the following conditions    *)
+(*  are met:                                                              *)
+(*  1. Redistributions of source code must retain the above copyright     *)
+(*     notice, this list of conditions and the following disclaimer.      *)
+(*  2. Redistributions in binary form must reproduce the above copyright  *)
+(*     notice, this list of conditions and the following disclaimer in    *)
+(*     the documentation and/or other materials provided with the         *)
+(*     distribution.                                                      *)
+(*                                                                        *)
+(*  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''    *)
+(*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     *)
+(*  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A       *)
+(*  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR   *)
+(*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,          *)
+(*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      *)
+(*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF      *)
+(*  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   *)
+(*  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,    *)
+(*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    *)
+(*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    *)
+(*  SUCH DAMAGE.                                                          *)
+(*========================================================================*)
+
+(*open import Pervasives_extra*)
+
+
+record 'a EnumerationType_class= 
+
+  toNat_method ::" 'a \<Rightarrow> nat "
+
+
+
+
+(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*)
+definition enumeration_typeCompare  :: " 'a EnumerationType_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering "  where 
+     " enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a e1 e2 = (
+  (genericCompare (op<) (op=) (
+  (toNat_method   dict_Sail2_instr_kinds_EnumerationType_a) e1) ((toNat_method   dict_Sail2_instr_kinds_EnumerationType_a) e2)))"
+
+
+
+definition instance_Basic_classes_Ord_var_dict  :: " 'a EnumerationType_class \<Rightarrow> 'a Ord_class "  where 
+     " instance_Basic_classes_Ord_var_dict dict_Sail2_instr_kinds_EnumerationType_a = ((|
+
+  compare_method = 
+  (enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a),
+
+  isLess_method = (\<lambda>  r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = LT),
+
+  isLessEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) \<noteq> GT),
+
+  isGreater_method = (\<lambda>  r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = GT),
+
+  isGreaterEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare 
+  dict_Sail2_instr_kinds_EnumerationType_a r1 r2) \<noteq> LT)|) )"
+
+
+
+(* Data structures for building up instructions *)
+
+(* careful: changes in the read/write/barrier kinds have to be
+   reflected in deep_shallow_convert *)
+datatype read_kind =
+  (* common reads *)
+    Read_plain
+  (* Power reads *)
+  | Read_reserve
+  (* AArch64 reads *)
+  | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+  (* RISC-V reads *)
+  | Read_RISCV_acquire  | Read_RISCV_strong_acquire
+  | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+  | Read_RISCV_reserved_strong_acquire
+  (* x86 reads *)
+  | Read_X86_locked (* the read part of a lock'd instruction (rmw) *)
+
+definition instance_Show_Show_Sail2_instr_kinds_read_kind_dict  :: "(read_kind)Show_class "  where 
+     " instance_Show_Show_Sail2_instr_kinds_read_kind_dict = ((|
+
+  show_method = (\<lambda>x .  
+  (case  x of
+        Read_plain => (''Read_plain'')
+    | Read_reserve => (''Read_reserve'')
+    | Read_acquire => (''Read_acquire'')
+    | Read_exclusive => (''Read_exclusive'')
+    | Read_exclusive_acquire => (''Read_exclusive_acquire'')
+    | Read_stream => (''Read_stream'')
+    | Read_RISCV_acquire => (''Read_RISCV_acquire'')
+    | Read_RISCV_strong_acquire => (''Read_RISCV_strong_acquire'')
+    | Read_RISCV_reserved => (''Read_RISCV_reserved'')
+    | Read_RISCV_reserved_acquire => (''Read_RISCV_reserved_acquire'')
+    | Read_RISCV_reserved_strong_acquire => (''Read_RISCV_reserved_strong_acquire'')
+    | Read_X86_locked => (''Read_X86_locked'')
+  ))|) )"
+
+
+datatype write_kind =
+  (* common writes *)
+    Write_plain
+  (* Power writes *)
+  | Write_conditional
+  (* AArch64 writes *)
+  | Write_release | Write_exclusive | Write_exclusive_release
+  (* RISC-V *)
+  | Write_RISCV_release     | Write_RISCV_strong_release
+  | Write_RISCV_conditional | Write_RISCV_conditional_release
+  | Write_RISCV_conditional_strong_release
+  (* x86 writes *)
+  | Write_X86_locked (* the write part of a lock'd instruction (rmw) *)
+
+definition instance_Show_Show_Sail2_instr_kinds_write_kind_dict  :: "(write_kind)Show_class "  where 
+     " instance_Show_Show_Sail2_instr_kinds_write_kind_dict = ((|
+
+  show_method = (\<lambda>x .  
+  (case  x of
+        Write_plain => (''Write_plain'')
+    | Write_conditional => (''Write_conditional'')
+    | Write_release => (''Write_release'')
+    | Write_exclusive => (''Write_exclusive'')
+    | Write_exclusive_release => (''Write_exclusive_release'')
+    | Write_RISCV_release => (''Write_RISCV_release'')
+    | Write_RISCV_strong_release => (''Write_RISCV_strong_release'')
+    | Write_RISCV_conditional => (''Write_RISCV_conditional'')
+    | Write_RISCV_conditional_release => (''Write_RISCV_conditional_release'')
+    | Write_RISCV_conditional_strong_release => (''Write_RISCV_conditional_strong_release'')
+    | Write_X86_locked => (''Write_X86_locked'')
+  ))|) )"
+
+
+datatype barrier_kind =
+  (* Power barriers *)
+  Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
+  (* AArch64 barriers *)
+  | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
+  | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
+  | Barrier_TM_COMMIT
+  (* MIPS barriers *)
+  | Barrier_MIPS_SYNC
+  (* RISC-V barriers *)
+  | Barrier_RISCV_rw_rw
+  | Barrier_RISCV_r_rw
+  | Barrier_RISCV_r_r
+  | Barrier_RISCV_rw_w
+  | Barrier_RISCV_w_w
+  | Barrier_RISCV_w_rw
+  | Barrier_RISCV_rw_r
+  | Barrier_RISCV_r_w
+  | Barrier_RISCV_w_r
+  | Barrier_RISCV_i
+  (* X86 *)
+  | Barrier_x86_MFENCE
+
+
+definition instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict  :: "(barrier_kind)Show_class "  where 
+     " instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict = ((|
+
+  show_method = (\<lambda>x .  
+  (case  x of
+        Barrier_Sync => (''Barrier_Sync'')
+    | Barrier_LwSync => (''Barrier_LwSync'')
+    | Barrier_Eieio => (''Barrier_Eieio'')
+    | Barrier_Isync => (''Barrier_Isync'')
+    | Barrier_DMB => (''Barrier_DMB'')
+    | Barrier_DMB_ST => (''Barrier_DMB_ST'')
+    | Barrier_DMB_LD => (''Barrier_DMB_LD'')
+    | Barrier_DSB => (''Barrier_DSB'')
+    | Barrier_DSB_ST => (''Barrier_DSB_ST'')
+    | Barrier_DSB_LD => (''Barrier_DSB_LD'')
+    | Barrier_ISB => (''Barrier_ISB'')
+    | Barrier_TM_COMMIT => (''Barrier_TM_COMMIT'')
+    | Barrier_MIPS_SYNC => (''Barrier_MIPS_SYNC'')
+    | Barrier_RISCV_rw_rw => (''Barrier_RISCV_rw_rw'')
+    | Barrier_RISCV_r_rw => (''Barrier_RISCV_r_rw'')
+    | Barrier_RISCV_r_r => (''Barrier_RISCV_r_r'')
+    | Barrier_RISCV_rw_w => (''Barrier_RISCV_rw_w'')
+    | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'')
+    | Barrier_RISCV_w_rw => (''Barrier_RISCV_w_rw'')
+    | Barrier_RISCV_rw_r => (''Barrier_RISCV_rw_r'')
+    | Barrier_RISCV_r_w => (''Barrier_RISCV_r_w'')
+    | Barrier_RISCV_w_r => (''Barrier_RISCV_w_r'')
+    | Barrier_RISCV_i => (''Barrier_RISCV_i'')
+    | Barrier_x86_MFENCE => (''Barrier_x86_MFENCE'')
+  ))|) )"
+
+
+datatype trans_kind =
+  (* AArch64 *)
+    Transaction_start | Transaction_commit | Transaction_abort
+
+definition instance_Show_Show_Sail2_instr_kinds_trans_kind_dict  :: "(trans_kind)Show_class "  where 
+     " instance_Show_Show_Sail2_instr_kinds_trans_kind_dict = ((|
+
+  show_method = (\<lambda>x .  
+  (case  x of
+        Transaction_start => (''Transaction_start'')
+    | Transaction_commit => (''Transaction_commit'')
+    | Transaction_abort => (''Transaction_abort'')
+  ))|) )"
+
+
+datatype instruction_kind =
+    IK_barrier   " barrier_kind "
+  | IK_mem_read  " read_kind "
+  | IK_mem_write " write_kind "
+  | IK_mem_rmw   " (read_kind * write_kind)"
+  | IK_branch    " unit "(* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+  indirect/computed-branch (single nia of kind NIA_indirect_address)
+  and branch/jump (single nia of kind NIA_concrete_address) *)
+  | IK_trans     " trans_kind "
+  | IK_simple    " unit "
+
+
+definition instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict  :: "(instruction_kind)Show_class "  where 
+     " instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict = ((|
+
+  show_method = (\<lambda>x .  
+  (case  x of
+        IK_barrier barrier_kind => (''IK_barrier '') @
+                                     (((\<lambda>x .  (case  x of
+                                                            Barrier_Sync => 
+                                                      (''Barrier_Sync'')
+                                                        | Barrier_LwSync => 
+                                                      (''Barrier_LwSync'')
+                                                        | Barrier_Eieio => 
+                                                      (''Barrier_Eieio'')
+                                                        | Barrier_Isync => 
+                                                      (''Barrier_Isync'')
+                                                        | Barrier_DMB => 
+                                                      (''Barrier_DMB'')
+                                                        | Barrier_DMB_ST => 
+                                                      (''Barrier_DMB_ST'')
+                                                        | Barrier_DMB_LD => 
+                                                      (''Barrier_DMB_LD'')
+                                                        | Barrier_DSB => 
+                                                      (''Barrier_DSB'')
+                                                        | Barrier_DSB_ST => 
+                                                      (''Barrier_DSB_ST'')
+                                                        | Barrier_DSB_LD => 
+                                                      (''Barrier_DSB_LD'')
+                                                        | Barrier_ISB => 
+                                                      (''Barrier_ISB'')
+                                                        | Barrier_TM_COMMIT => 
+                                                      (''Barrier_TM_COMMIT'')
+                                                        | Barrier_MIPS_SYNC => 
+                                                      (''Barrier_MIPS_SYNC'')
+                                                        | Barrier_RISCV_rw_rw => 
+                                                      (''Barrier_RISCV_rw_rw'')
+                                                        | Barrier_RISCV_r_rw => 
+                                                      (''Barrier_RISCV_r_rw'')
+                                                        | Barrier_RISCV_r_r => 
+                                                      (''Barrier_RISCV_r_r'')
+                                                        | Barrier_RISCV_rw_w => 
+                                                      (''Barrier_RISCV_rw_w'')
+                                                        | Barrier_RISCV_w_w => 
+                                                      (''Barrier_RISCV_w_w'')
+                                                        | Barrier_RISCV_w_rw => 
+                                                      (''Barrier_RISCV_w_rw'')
+                                                        | Barrier_RISCV_rw_r => 
+                                                      (''Barrier_RISCV_rw_r'')
+                                                        | Barrier_RISCV_r_w => 
+                                                      (''Barrier_RISCV_r_w'')
+                                                        | Barrier_RISCV_w_r => 
+                                                      (''Barrier_RISCV_w_r'')
+                                                        | Barrier_RISCV_i => 
+                                                      (''Barrier_RISCV_i'')
+                                                        | Barrier_x86_MFENCE => 
+                                                      (''Barrier_x86_MFENCE'')
+                                                      )) barrier_kind))
+    | IK_mem_read read_kind => (''IK_mem_read '') @
+                                 (((\<lambda>x .  (case  x of
+                                                        Read_plain => 
+                                                  (''Read_plain'')
+                                                    | Read_reserve => 
+                                                  (''Read_reserve'')
+                                                    | Read_acquire => 
+                                                  (''Read_acquire'')
+                                                    | Read_exclusive => 
+                                                  (''Read_exclusive'')
+                                                    | Read_exclusive_acquire => 
+                                                  (''Read_exclusive_acquire'')
+                                                    | Read_stream => 
+                                                  (''Read_stream'')
+                                                    | Read_RISCV_acquire => 
+                                                  (''Read_RISCV_acquire'')
+                                                    | Read_RISCV_strong_acquire => 
+                                                  (''Read_RISCV_strong_acquire'')
+                                                    | Read_RISCV_reserved => 
+                                                  (''Read_RISCV_reserved'')
+                                                    | Read_RISCV_reserved_acquire => 
+                                                  (''Read_RISCV_reserved_acquire'')
+                                                    | Read_RISCV_reserved_strong_acquire => 
+                                                  (''Read_RISCV_reserved_strong_acquire'')
+                                                    | Read_X86_locked => 
+                                                  (''Read_X86_locked'')
+                                                  )) read_kind))
+    | IK_mem_write write_kind => (''IK_mem_write '') @
+                                   (((\<lambda>x .  (case  x of
+                                                          Write_plain => 
+                                                    (''Write_plain'')
+                                                      | Write_conditional => 
+                                                    (''Write_conditional'')
+                                                      | Write_release => 
+                                                    (''Write_release'')
+                                                      | Write_exclusive => 
+                                                    (''Write_exclusive'')
+                                                      | Write_exclusive_release => 
+                                                    (''Write_exclusive_release'')
+                                                      | Write_RISCV_release => 
+                                                    (''Write_RISCV_release'')
+                                                      | Write_RISCV_strong_release => 
+                                                    (''Write_RISCV_strong_release'')
+                                                      | Write_RISCV_conditional => 
+                                                    (''Write_RISCV_conditional'')
+                                                      | Write_RISCV_conditional_release => 
+                                                    (''Write_RISCV_conditional_release'')
+                                                      | Write_RISCV_conditional_strong_release => 
+                                                    (''Write_RISCV_conditional_strong_release'')
+                                                      | Write_X86_locked => 
+                                                    (''Write_X86_locked'')
+                                                    )) write_kind))
+    | IK_mem_rmw (r, w) => (''IK_mem_rmw '') @
+                             ((((\<lambda>x .  (case  x of
+                                                     Read_plain => (''Read_plain'')
+                                                 | Read_reserve => (''Read_reserve'')
+                                                 | Read_acquire => (''Read_acquire'')
+                                                 | Read_exclusive => 
+                                               (''Read_exclusive'')
+                                                 | Read_exclusive_acquire => 
+                                               (''Read_exclusive_acquire'')
+                                                 | Read_stream => (''Read_stream'')
+                                                 | Read_RISCV_acquire => 
+                                               (''Read_RISCV_acquire'')
+                                                 | Read_RISCV_strong_acquire => 
+                                               (''Read_RISCV_strong_acquire'')
+                                                 | Read_RISCV_reserved => 
+                                               (''Read_RISCV_reserved'')
+                                                 | Read_RISCV_reserved_acquire => 
+                                               (''Read_RISCV_reserved_acquire'')
+                                                 | Read_RISCV_reserved_strong_acquire => 
+                                               (''Read_RISCV_reserved_strong_acquire'')
+                                                 | Read_X86_locked => 
+                                               (''Read_X86_locked'')
+                                               )) r)) @
+                                (('' '') @
+                                   (((\<lambda>x .  (case  x of
+                                                          Write_plain => 
+                                                    (''Write_plain'')
+                                                      | Write_conditional => 
+                                                    (''Write_conditional'')
+                                                      | Write_release => 
+                                                    (''Write_release'')
+                                                      | Write_exclusive => 
+                                                    (''Write_exclusive'')
+                                                      | Write_exclusive_release => 
+                                                    (''Write_exclusive_release'')
+                                                      | Write_RISCV_release => 
+                                                    (''Write_RISCV_release'')
+                                                      | Write_RISCV_strong_release => 
+                                                    (''Write_RISCV_strong_release'')
+                                                      | Write_RISCV_conditional => 
+                                                    (''Write_RISCV_conditional'')
+                                                      | Write_RISCV_conditional_release => 
+                                                    (''Write_RISCV_conditional_release'')
+                                                      | Write_RISCV_conditional_strong_release => 
+                                                    (''Write_RISCV_conditional_strong_release'')
+                                                      | Write_X86_locked => 
+                                                    (''Write_X86_locked'')
+                                                    )) w))))
+    | IK_branch _ => (''IK_branch'')
+    | IK_trans trans_kind => (''IK_trans '') @
+                               (((\<lambda>x .  (case  x of
+                                                      Transaction_start => 
+                                                (''Transaction_start'')
+                                                  | Transaction_commit => 
+                                                (''Transaction_commit'')
+                                                  | Transaction_abort => 
+                                                (''Transaction_abort'')
+                                                )) trans_kind))
+    | IK_simple _ => (''IK_simple'')
+  ))|) )"
+
+
+
+definition read_is_exclusive  :: " read_kind \<Rightarrow> bool "  where 
+     " read_is_exclusive = ( \<lambda>x .  
+  (case  x of
+        Read_plain => False
+    | Read_reserve => True
+    | Read_acquire => False
+    | Read_exclusive => True
+    | Read_exclusive_acquire => True
+    | Read_stream => False
+    | Read_RISCV_acquire => False
+    | Read_RISCV_strong_acquire => False
+    | Read_RISCV_reserved => True
+    | Read_RISCV_reserved_acquire => True
+    | Read_RISCV_reserved_strong_acquire => True
+    | Read_X86_locked => True
+  ) )"
+
+
+
+
+definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict  :: "(read_kind)EnumerationType_class "  where 
+     " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict = ((|
+
+  toNat_method = (\<lambda>x .  
+  (case  x of
+        Read_plain =>( 0 :: nat)
+    | Read_reserve =>( 1 :: nat)
+    | Read_acquire =>( 2 :: nat)
+    | Read_exclusive =>( 3 :: nat)
+    | Read_exclusive_acquire =>( 4 :: nat)
+    | Read_stream =>( 5 :: nat)
+    | Read_RISCV_acquire =>( 6 :: nat)
+    | Read_RISCV_strong_acquire =>( 7 :: nat)
+    | Read_RISCV_reserved =>( 8 :: nat)
+    | Read_RISCV_reserved_acquire =>( 9 :: nat)
+    | Read_RISCV_reserved_strong_acquire =>( 10 :: nat)
+    | Read_X86_locked =>( 11 :: nat)
+  ))|) )"
+
+
+definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict  :: "(write_kind)EnumerationType_class "  where 
+     " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict = ((|
+
+  toNat_method = (\<lambda>x .  
+  (case  x of
+        Write_plain =>( 0 :: nat)
+    | Write_conditional =>( 1 :: nat)
+    | Write_release =>( 2 :: nat)
+    | Write_exclusive =>( 3 :: nat)
+    | Write_exclusive_release =>( 4 :: nat)
+    | Write_RISCV_release =>( 5 :: nat)
+    | Write_RISCV_strong_release =>( 6 :: nat)
+    | Write_RISCV_conditional =>( 7 :: nat)
+    | Write_RISCV_conditional_release =>( 8 :: nat)
+    | Write_RISCV_conditional_strong_release =>( 9 :: nat)
+    | Write_X86_locked =>( 10 :: nat)
+  ))|) )"
+
+
+definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict  :: "(barrier_kind)EnumerationType_class "  where 
+     " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict = ((|
+
+  toNat_method = (\<lambda>x .  
+  (case  x of
+        Barrier_Sync =>( 0 :: nat)
+    | Barrier_LwSync =>( 1 :: nat)
+    | Barrier_Eieio =>( 2 :: nat)
+    | Barrier_Isync =>( 3 :: nat)
+    | Barrier_DMB =>( 4 :: nat)
+    | Barrier_DMB_ST =>( 5 :: nat)
+    | Barrier_DMB_LD =>( 6 :: nat)
+    | Barrier_DSB =>( 7 :: nat)
+    | Barrier_DSB_ST =>( 8 :: nat)
+    | Barrier_DSB_LD =>( 9 :: nat)
+    | Barrier_ISB =>( 10 :: nat)
+    | Barrier_TM_COMMIT =>( 11 :: nat)
+    | Barrier_MIPS_SYNC =>( 12 :: nat)
+    | Barrier_RISCV_rw_rw =>( 13 :: nat)
+    | Barrier_RISCV_r_rw =>( 14 :: nat)
+    | Barrier_RISCV_r_r =>( 15 :: nat)
+    | Barrier_RISCV_rw_w =>( 16 :: nat)
+    | Barrier_RISCV_w_w =>( 17 :: nat)
+    | Barrier_RISCV_w_rw =>( 18 :: nat)
+    | Barrier_RISCV_rw_r =>( 19 :: nat)
+    | Barrier_RISCV_r_w =>( 20 :: nat)
+    | Barrier_RISCV_w_r =>( 21 :: nat)
+    | Barrier_RISCV_i =>( 22 :: nat)
+    | Barrier_x86_MFENCE =>( 23 :: nat)
+  ))|) )"
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators.thy b/snapshots/isabelle/lib/sail/Sail2_operators.thy
new file mode 100644
index 00000000..fc4d4749
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_operators.thy
@@ -0,0 +1,326 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_operators.lem.\<close>
+
+theory "Sail2_operators" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Lem_machine_word" 
+	 "Sail2_values" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+
+(*** Bit vector operations *)
+
+(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*)
+definition concat_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow>(bitU)list "  where 
+     " concat_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b l r = ( (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) l @(bits_of_method   dict_Sail2_values_Bitvector_b) r))"
+
+
+(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*)
+definition cons_bv  :: " 'a Bitvector_class \<Rightarrow> bitU \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
+     " cons_bv dict_Sail2_values_Bitvector_a b v = ( b # 
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v )"
+
+
+(*val cast_unit_bv : bitU -> list bitU*)
+definition cast_unit_bv  :: " bitU \<Rightarrow>(bitU)list "  where 
+     " cast_unit_bv b = ( [b])"
+
+
+(*val bv_of_bit : integer -> bitU -> list bitU*)
+definition bv_of_bit  :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " bv_of_bit len b = ( extz_bits len [b])"
+
+
+definition most_significant  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU "  where 
+     " most_significant dict_Sail2_values_Bitvector_a v = ( (case  
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v of
+    b # _ => b
+  | _ => B0 (* Treat empty bitvector as all zeros *)
+  ))"
+
+
+definition get_max_representable_in  :: " bool \<Rightarrow> int \<Rightarrow> int "  where 
+     " get_max_representable_in sign (n :: int) = (
+  if (n =( 64 :: int)) then (case  sign of   True => max_64 | False => max_64u )
+  else if (n=( 32 :: int)) then (case  sign of   True => max_32 | False => max_32u )
+  else if (n=( 8 :: int)) then max_8
+  else if (n=( 5 :: int)) then max_5
+  else (case  sign of   True => (( 2 :: int))^ ((nat (abs ( n))) -( 1 :: nat))
+                       | False => (( 2 :: int))^ (nat (abs ( n)))
+       ))"
+
+
+definition get_min_representable_in  :: " 'a \<Rightarrow> int \<Rightarrow> int "  where 
+     " get_min_representable_in _ (n :: int) = (
+  if n =( 64 :: int) then min_64
+  else if n =( 32 :: int) then min_32
+  else if n =( 8 :: int) then min_8
+  else if n =( 5 :: int) then min_5
+  else( 0 :: int) - ((( 2 :: int))^ (nat (abs ( n)))))"
+
+
+(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
+definition arith_op_bv_int  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'a "  where 
+     " arith_op_bv_int dict_Sail2_values_Bitvector_a op1 sign l r = (
+  (let r' = ((of_int_method   dict_Sail2_values_Bitvector_a) ((length_method   dict_Sail2_values_Bitvector_a) l) r) in (arith_op_bv_method   dict_Sail2_values_Bitvector_a) op1 sign l r'))"
+
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
+definition arith_op_int_bv  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a "  where 
+     " arith_op_int_bv dict_Sail2_values_Bitvector_a op1 sign l r = (
+  (let l' = ((of_int_method   dict_Sail2_values_Bitvector_a) ((length_method   dict_Sail2_values_Bitvector_a) r) l) in (arith_op_bv_method   dict_Sail2_values_Bitvector_a) op1 sign l' r))"
+
+
+definition arith_op_bv_bool  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
+     " arith_op_bv_bool dict_Sail2_values_Bitvector_a op1 sign l r = ( arith_op_bv_int 
+  dict_Sail2_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))"
+
+definition arith_op_bv_bit  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
+     " arith_op_bv_bit dict_Sail2_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a op1 sign l) (bool_of_bitU r))"
+
+
+(* TODO (or just omit and define it per spec if needed)
+val arith_op_overflow_bv : forall 'a. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv op sign size l r =
+  let len = length l in
+  let act_size = len * size in
+  match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with
+    | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) ->
+       let n = op l_sign r_sign in
+       let n_unsign = op l_unsign r_unsign in
+       let correct_size = of_int act_size n in
+       let one_more_size_u = bits_of_int (act_size + 1) n_unsign in
+       let overflow =
+         if n <= get_max_representable_in sign len &&
+              n >= get_min_representable_in sign len
+         then B0 else B1 in
+       let c_out = most_significant one_more_size_u in
+       (correct_size,overflow,c_out)
+    | (_, _, _, _) ->
+       (repeat [BU] act_size, BU, BU)
+  end
+
+let add_overflow_bv = arith_op_overflow_bv integerAdd false 1
+let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1
+let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1
+let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1
+let mult_overflow_bv = arith_op_overflow_bv integerMult false 2
+let mults_overflow_bv = arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv_bit op sign size l r_bit =
+  let act_size = length l * size in
+  match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with
+    | (Just l', Just l_u, false) ->
+       let (n, nu, changed) = match r_bit with
+         | B1 -> (op l' 1, op l_u 1, true)
+         | B0 -> (l', l_u, false)
+         | BU -> (* unreachable due to check above *)
+            failwith arith_op_overflow_bv_bit applied to undefined bit
+         end in
+       let correct_size = of_int act_size n in
+       let one_larger = bits_of_int (act_size + 1) nu in
+       let overflow =
+         if changed
+         then
+           if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+           then B0 else B1
+         else B0 in
+       (correct_size, overflow, most_significant one_larger)
+    | (_, _, _) ->
+       (repeat [BU] act_size, BU, BU)
+  end
+
+let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1
+let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1
+let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1
+let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*)
+
+datatype shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot
+
+definition invert_shift  :: " shift \<Rightarrow> shift "  where 
+     " invert_shift = ( \<lambda>x .  
+  (case  x of
+        LL_shift => RR_shift
+    | RR_shift => LL_shift
+    | RR_shift_arith => LL_shift
+    | LL_rot => RR_rot
+    | RR_rot => LL_rot
+  ) )"
+
+
+(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*)
+definition shift_op_bv  :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " shift_op_bv dict_Sail2_values_Bitvector_a op1 v n = (
+  (let v = ((bits_of_method   dict_Sail2_values_Bitvector_a) v) in
+  if n =( 0 :: int) then v else
+  (let (op1, n) = (if n >( 0 :: int) then (op1, n) else (invert_shift op1, - n)) in
+  (case  op1 of
+    LL_shift =>
+     subrange_list True v n (int (List.length v) -( 1 :: int)) @ repeat [B0] n
+  | RR_shift =>
+     repeat [B0] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int))
+  | RR_shift_arith =>
+     repeat [most_significant 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int))
+  | LL_rot =>
+     subrange_list True v n (int (List.length v) -( 1 :: int)) @ subrange_list True v(( 0 :: int)) (n -( 1 :: int))
+  | RR_rot =>
+     subrange_list False v(( 0 :: int)) (n -( 1 :: int)) @ subrange_list False v n (int (List.length v) -( 1 :: int))
+  ))))"
+
+
+definition shiftl_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " shiftl_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv 
+  dict_Sail2_values_Bitvector_a LL_shift )"
+ (*<<*)
+definition shiftr_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " shiftr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv 
+  dict_Sail2_values_Bitvector_a RR_shift )"
+ (*>>*)
+definition arith_shiftr_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " arith_shiftr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv 
+  dict_Sail2_values_Bitvector_a RR_shift_arith )"
+
+definition rotl_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " rotl_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv 
+  dict_Sail2_values_Bitvector_a LL_rot )"
+ (*<<<*)
+definition rotr_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " rotr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv 
+  dict_Sail2_values_Bitvector_a LL_rot )"
+ (*>>>*)
+
+definition shiftl_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " shiftl_mword w n = ( w << (nat_of_int n))"
+
+definition shiftr_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " shiftr_mword w n = ( w >> (nat_of_int n))"
+
+definition arith_shiftr_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " arith_shiftr_mword w n = ( w >>> (nat_of_int n))"
+
+definition rotl_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " rotl_mword w n = ( Word.word_rotl (nat_of_int n) w )"
+
+definition rotr_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " rotr_mword w n = ( Word.word_rotr (nat_of_int n) w )"
+
+
+fun  arith_op_no0  :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)option "  where 
+     " arith_op_no0 (op1 :: int \<Rightarrow> int \<Rightarrow> int) l r = (
+  if r =( 0 :: int)
+  then None
+  else Some (op1 l r))"
+
+
+(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*)
+definition arith_op_bv_no0  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'b option "  where 
+     " arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l r = (
+  Option.bind (int_of_bv 
+  dict_Sail2_values_Bitvector_a sign l) (\<lambda> l' . 
+  Option.bind (int_of_bv 
+  dict_Sail2_values_Bitvector_a sign r) (\<lambda> r' . 
+  if r' =( 0 :: int) then None else Some (
+  (of_int_method   dict_Sail2_values_Bitvector_b) ((length_method   dict_Sail2_values_Bitvector_a) l * size1) (op1 l' r')))))"
+
+
+definition mod_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option "  where 
+     " mod_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod False(( 1 :: int)))"
+
+definition quot_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option "  where 
+     " quot_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot False(( 1 :: int)))"
+
+definition quots_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option "  where 
+     " quots_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot True(( 1 :: int)))"
+
+
+definition mod_mword  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " mod_mword = ( (op mod))"
+
+definition quot_mword  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " quot_mword = ( (op div))"
+
+definition quots_mword  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " quots_mword = ( Lem_machine_word.signedDivide )"
+
+
+definition arith_op_bv_int_no0  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b option "  where 
+     " arith_op_bv_int_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l r = (
+  arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l ((of_int_method   dict_Sail2_values_Bitvector_a) ((length_method   dict_Sail2_values_Bitvector_a) l) r))"
+
+
+definition quot_bv_int  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option "  where 
+     " quot_bv_int dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_int_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot False(( 1 :: int)))"
+
+definition mod_bv_int  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option "  where 
+     " mod_bv_int dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_int_no0 
+  dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod False(( 1 :: int)))"
+
+
+definition mod_mword_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " mod_mword_int l r = ( l mod (Word.word_of_int r))"
+
+definition quot_mword_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " quot_mword_int l r = ( l div (Word.word_of_int r))"
+
+definition quots_mword_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " quots_mword_int l r = ( Lem_machine_word.signedDivide l (Word.word_of_int r))"
+
+
+definition replicate_bits_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " replicate_bits_bv dict_Sail2_values_Bitvector_a v count1 = ( repeat (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) count1 )"
+
+definition duplicate_bit_bv  :: " 'a BitU_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " duplicate_bit_bv dict_Sail2_values_BitU_a bit len = ( replicate_bits_bv 
+  (instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a) [bit] len )"
+
+
+(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+definition eq_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool "  where 
+     " eq_bv dict_Sail2_values_Bitvector_a l r = ( (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) l =(bits_of_method   dict_Sail2_values_Bitvector_a) r))"
+
+
+(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+definition neq_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool "  where 
+     " neq_bv dict_Sail2_values_Bitvector_a l r = ( \<not> (eq_bv 
+  dict_Sail2_values_Bitvector_a l r))"
+
+
+(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
+definition get_slice_int_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a "  where 
+     " get_slice_int_bv dict_Sail2_values_Bitvector_a len n lo = (
+  (let hi = ((lo + len) -( 1 :: int)) in
+  (let bs = (bools_of_int (hi +( 1 :: int)) n) in 
+  (of_bools_method   dict_Sail2_values_Bitvector_a) (subrange_list False bs hi lo))))"
+
+
+(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*)
+definition set_slice_int_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int "  where 
+     " set_slice_int_bv dict_Sail2_values_Bitvector_a len n lo v = (
+  (let hi = ((lo + len) -( 1 :: int)) in
+  (let bs = (bits_of_int (hi +( 1 :: int)) n) in
+  maybe_failwith (signed_of_bits (update_subrange_list False bs hi lo (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v))))))"
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy b/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
new file mode 100644
index 00000000..96c38a6a
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
@@ -0,0 +1,737 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_operators_bitlists.lem.\<close>
+
+theory "Sail2_operators_bitlists" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Lem_machine_word" 
+	 "Sail2_values" 
+	 "Sail2_operators" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+(* Specialisation of operators to bit lists *)
+
+(*val uint_maybe : list bitU -> maybe integer*)
+definition uint_maybe  :: "(bitU)list \<Rightarrow>(int)option "  where 
+     " uint_maybe v = ( unsigned_of_bits (List.map (\<lambda> b. b) v))"
+
+definition uint_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad "  where 
+     " uint_fail dict_Sail2_values_Bitvector_a v = ( maybe_fail (''uint'') (
+  (unsigned_method   dict_Sail2_values_Bitvector_a) v))"
+
+definition uint_nondet  :: "(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
+     " uint_nondet v = (
+  bools_of_bits_nondet v \<bind> (\<lambda> bs . 
+  return (int_of_bools False bs)))"
+
+definition uint  :: "(bitU)list \<Rightarrow> int "  where 
+     " uint v = ( maybe_failwith (uint_maybe v))"
+
+
+(*val sint_maybe : list bitU -> maybe integer*)
+definition sint_maybe  :: "(bitU)list \<Rightarrow>(int)option "  where 
+     " sint_maybe v = ( signed_of_bits (List.map (\<lambda> b. b) v))"
+
+definition sint_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad "  where 
+     " sint_fail dict_Sail2_values_Bitvector_a v = ( maybe_fail (''sint'') (
+  (signed_method   dict_Sail2_values_Bitvector_a) v))"
+
+definition sint_nondet  :: "(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
+     " sint_nondet v = (
+  bools_of_bits_nondet v \<bind> (\<lambda> bs . 
+  return (int_of_bools True bs)))"
+
+definition sint  :: "(bitU)list \<Rightarrow> int "  where 
+     " sint v = ( maybe_failwith (sint_maybe v))"
+
+
+(*val extz_vec : integer -> list bitU -> list bitU*)
+definition extz_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " extz_vec = ( 
+  extz_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val exts_vec : integer -> list bitU -> list bitU*)
+definition exts_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " exts_vec = ( 
+  exts_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val zero_extend : list bitU -> integer -> list bitU*)
+definition zero_extend  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " zero_extend bits len = ( extz_bits len bits )"
+
+
+(*val sign_extend : list bitU -> integer -> list bitU*)
+definition sign_extend  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " sign_extend bits len = ( exts_bits len bits )"
+
+
+(*val zeros : integer -> list bitU*)
+definition zeros  :: " int \<Rightarrow>(bitU)list "  where 
+     " zeros len = ( repeat [B0] len )"
+
+
+(*val vector_truncate : list bitU -> integer -> list bitU*)
+definition vector_truncate  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " vector_truncate bs len = ( extz_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) len bs )"
+
+
+(*val vec_of_bits_maybe    : list bitU -> maybe (list bitU)*)
+(*val vec_of_bits_fail     : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
+(*val vec_of_bits_nondet   : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
+(*val vec_of_bits_failwith : list bitU -> list bitU*)
+(*val vec_of_bits          : list bitU -> list bitU*)
+
+(*val access_vec_inc : list bitU -> integer -> bitU*)
+definition access_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_vec_inc = ( 
+  access_bv_inc
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val access_vec_dec : list bitU -> integer -> bitU*)
+definition access_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_vec_dec = ( 
+  access_bv_dec
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*)
+definition update_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " update_vec_inc = ( 
+  update_bv_inc
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition update_vec_inc_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option "  where 
+     " update_vec_inc_maybe v i b = ( Some (update_vec_inc v i b))"
+
+definition update_vec_inc_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " update_vec_inc_fail v i b = ( return (update_vec_inc v i b))"
+
+definition update_vec_inc_nondet  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " update_vec_inc_nondet v i b = ( return (update_vec_inc v i b))"
+
+
+(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*)
+definition update_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " update_vec_dec = ( 
+  update_bv_dec
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition update_vec_dec_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option "  where 
+     " update_vec_dec_maybe v i b = ( Some (update_vec_dec v i b))"
+
+definition update_vec_dec_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " update_vec_dec_fail v i b = ( return (update_vec_dec v i b))"
+
+definition update_vec_dec_nondet  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " update_vec_dec_nondet v i b = ( return (update_vec_dec v i b))"
+
+
+(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*)
+definition subrange_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " subrange_vec_inc = ( 
+  subrange_bv_inc
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*)
+definition subrange_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " subrange_vec_dec = ( 
+  subrange_bv_dec
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*)
+definition update_subrange_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " update_subrange_vec_inc = ( 
+  update_subrange_bv_inc
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*)
+definition update_subrange_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " update_subrange_vec_dec = ( 
+  update_subrange_bv_dec
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val concat_vec : list bitU -> list bitU -> list bitU*)
+definition concat_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " concat_vec = ( 
+  concat_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val cons_vec : bitU -> list bitU -> list bitU*)
+definition cons_vec  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " cons_vec = ( 
+  cons_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition cons_vec_maybe  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
+     " cons_vec_maybe b v = ( Some (cons_vec b v))"
+
+definition cons_vec_fail  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " cons_vec_fail b v = ( return (cons_vec b v))"
+
+definition cons_vec_nondet  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " cons_vec_nondet b v = ( return (cons_vec b v))"
+
+
+(*val cast_unit_vec : bitU -> list bitU*)
+definition cast_unit_vec  :: " bitU \<Rightarrow>(bitU)list "  where 
+     " cast_unit_vec = ( cast_unit_bv )"
+
+definition cast_unit_vec_maybe  :: " bitU \<Rightarrow>((bitU)list)option "  where 
+     " cast_unit_vec_maybe b = ( Some (cast_unit_vec b))"
+
+definition cast_unit_vec_fail  :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " cast_unit_vec_fail b = ( return (cast_unit_vec b))"
+
+definition cast_unit_vec_nondet  :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " cast_unit_vec_nondet b = ( return (cast_unit_vec b))"
+
+
+(*val vec_of_bit : integer -> bitU -> list bitU*)
+definition vec_of_bit  :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " vec_of_bit = ( bv_of_bit )"
+
+definition vec_of_bit_maybe  :: " int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option "  where 
+     " vec_of_bit_maybe len b = ( Some (vec_of_bit len b))"
+
+definition vec_of_bit_fail  :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " vec_of_bit_fail len b = ( return (vec_of_bit len b))"
+
+definition vec_of_bit_nondet  :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " vec_of_bit_nondet len b = ( return (vec_of_bit len b))"
+
+
+(*val msb : list bitU -> bitU*)
+definition msb  :: "(bitU)list \<Rightarrow> bitU "  where 
+     " msb = ( 
+  most_significant
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*)
+definition int_of_vec_maybe  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option "  where 
+     " int_of_vec_maybe = ( 
+  int_of_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition int_of_vec_fail  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
+     " int_of_vec_fail sign v = ( maybe_fail (''int_of_vec'') (int_of_vec_maybe sign v))"
+
+definition int_of_vec_nondet  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
+     " int_of_vec_nondet sign v = ( bools_of_bits_nondet v \<bind> (\<lambda> v .  return (int_of_bools sign v)))"
+
+definition int_of_vec  :: " bool \<Rightarrow>(bitU)list \<Rightarrow> int "  where 
+     " int_of_vec sign v = ( maybe_failwith (int_of_vec_maybe sign v))"
+
+
+(*val string_of_bits : list bitU -> string*)
+definition string_of_bits  :: "(bitU)list \<Rightarrow> string "  where 
+     " string_of_bits = ( 
+  string_of_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val and_vec : list bitU -> list bitU -> list bitU*)
+(*val or_vec  : list bitU -> list bitU -> list bitU*)
+(*val xor_vec : list bitU -> list bitU -> list bitU*)
+(*val not_vec : list bitU -> list bitU*)
+definition and_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " and_vec = ( binop_list and_bit )"
+
+definition or_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
+     " or_vec  = ( binop_list or_bit )"
+
+definition xor_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " xor_vec = ( binop_list xor_bit )"
+
+definition not_vec  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
+     " not_vec = ( List.map not_bit )"
+
+
+(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*)
+definition arith_op_double_bl  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
+     " arith_op_double_bl dict_Sail2_values_Bitvector_a op1 sign l r = (
+  (let len =(( 2 :: int) *
+  (length_method   dict_Sail2_values_Bitvector_a) l) in
+  (let l' = (if sign then exts_bv 
+  dict_Sail2_values_Bitvector_a len l else extz_bv dict_Sail2_values_Bitvector_a len l) in
+  (let r' = (if sign then exts_bv 
+  dict_Sail2_values_Bitvector_a len r else extz_bv dict_Sail2_values_Bitvector_a len r) in
+  List.map (\<lambda> b. b) (arith_op_bits op1 sign (List.map (\<lambda> b. b) l') (List.map (\<lambda> b. b) r'))))))"
+
+
+(*val add_vec   : list bitU -> list bitU -> list bitU*)
+(*val adds_vec  : list bitU -> list bitU -> list bitU*)
+(*val sub_vec   : list bitU -> list bitU -> list bitU*)
+(*val subs_vec  : list bitU -> list bitU -> list bitU*)
+(*val mult_vec  : list bitU -> list bitU -> list bitU*)
+(*val mults_vec : list bitU -> list bitU -> list bitU*)
+definition add_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "    where 
+     " add_vec   = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op+) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition adds_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
+     " adds_vec  = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op+) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition sub_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "    where 
+     " sub_vec   = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op-) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition subs_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
+     " subs_vec  = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op-) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition mult_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
+     " mult_vec  = ( arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) False )"
+
+definition mults_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " mults_vec = ( arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True )"
+
+
+(*val add_vec_int      : list bitU -> integer -> list bitU*)
+(*val sub_vec_int      : list bitU -> integer -> list bitU*)
+(*val mult_vec_int     : list bitU -> integer -> list bitU*)
+definition add_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " add_vec_int  l r = ( arith_op_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) True l r )"
+
+definition sub_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " sub_vec_int  l r = ( arith_op_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) True l r )"
+
+definition mult_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " mult_vec_int l r = ( arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))"
+
+
+(*val add_int_vec      : integer -> list bitU -> list bitU*)
+(*val sub_int_vec      : integer -> list bitU -> list bitU*)
+(*val mult_int_vec     : integer -> list bitU -> list bitU*)
+definition add_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " add_int_vec  l r = ( arith_op_int_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) True l r )"
+
+definition sub_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " sub_int_vec  l r = ( arith_op_int_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) True l r )"
+
+definition mult_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " mult_int_vec l r = ( arith_op_double_bl 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )"
+
+
+(*val add_vec_bit      : list bitU -> bitU -> list bitU*)
+(*val adds_vec_bit     : list bitU -> bitU -> list bitU*)
+(*val sub_vec_bit      : list bitU -> bitU -> list bitU*)
+(*val subs_vec_bit     : list bitU -> bitU -> list bitU*)
+
+definition add_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
+     " add_vec_bool dict_Sail2_values_Bitvector_a       l r = ( arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (op+) False l r )"
+
+definition add_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
+     " add_vec_bit_maybe dict_Sail2_values_Bitvector_a  l r = ( arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (op+) False l r )"
+
+definition add_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " add_vec_bit_fail dict_Sail2_values_Bitvector_a   l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe 
+  dict_Sail2_values_Bitvector_a l r))"
+
+definition add_vec_bit_nondet  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " add_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (add_vec_bool 
+  dict_Sail2_values_Bitvector_a l r)))"
+
+definition add_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " add_vec_bit        l r = ( case_option (repeat [BU] (int (List.length l))) id (add_vec_bit_maybe 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+definition adds_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
+     " adds_vec_bool dict_Sail2_values_Bitvector_a       l r = ( arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (op+) True l r )"
+
+definition adds_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
+     " adds_vec_bit_maybe dict_Sail2_values_Bitvector_a  l r = ( arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (op+) True l r )"
+
+definition adds_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " adds_vec_bit_fail dict_Sail2_values_Bitvector_a   l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe 
+  dict_Sail2_values_Bitvector_a l r))"
+
+definition adds_vec_bit_nondet  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " adds_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (adds_vec_bool 
+  dict_Sail2_values_Bitvector_a l r)))"
+
+definition adds_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " adds_vec_bit        l r = ( case_option (repeat [BU] (int (List.length l))) id (adds_vec_bit_maybe 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+definition sub_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
+     " sub_vec_bool dict_Sail2_values_Bitvector_a        l r = ( arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (op-) False l r )"
+
+definition sub_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
+     " sub_vec_bit_maybe dict_Sail2_values_Bitvector_a   l r = ( arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (op-) False l r )"
+
+definition sub_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " sub_vec_bit_fail dict_Sail2_values_Bitvector_a    l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe 
+  dict_Sail2_values_Bitvector_a l r))"
+
+definition sub_vec_bit_nondet  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " sub_vec_bit_nondet dict_Sail2_values_Bitvector_a  l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (sub_vec_bool 
+  dict_Sail2_values_Bitvector_a l r)))"
+
+definition sub_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " sub_vec_bit         l r = ( case_option (repeat [BU] (int (List.length l))) id (sub_vec_bit_maybe 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+definition subs_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
+     " subs_vec_bool dict_Sail2_values_Bitvector_a       l r = ( arith_op_bv_bool 
+  dict_Sail2_values_Bitvector_a (op-) True l r )"
+
+definition subs_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
+     " subs_vec_bit_maybe dict_Sail2_values_Bitvector_a  l r = ( arith_op_bv_bit 
+  dict_Sail2_values_Bitvector_a (op-) True l r )"
+
+definition subs_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " subs_vec_bit_fail dict_Sail2_values_Bitvector_a   l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe 
+  dict_Sail2_values_Bitvector_a l r))"
+
+definition subs_vec_bit_nondet  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
+     " subs_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (subs_vec_bool 
+  dict_Sail2_values_Bitvector_a l r)))"
+
+definition subs_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " subs_vec_bit        l r = ( case_option (repeat [BU] (int (List.length l))) id (subs_vec_bit_maybe 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+(*val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec        : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec         = add_overflow_bv
+let add_overflow_vec_signed  = add_overflow_bv_signed
+let sub_overflow_vec         = sub_overflow_bv
+let sub_overflow_vec_signed  = sub_overflow_bv_signed
+let mult_overflow_vec        = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit         = add_overflow_bv_bit
+let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit         = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
+
+(*val shiftl       : list bitU -> integer -> list bitU*)
+(*val shiftr       : list bitU -> integer -> list bitU*)
+(*val arith_shiftr : list bitU -> integer -> list bitU*)
+(*val rotl         : list bitU -> integer -> list bitU*)
+(*val rotr         : list bitU -> integer -> list bitU*)
+definition shiftl  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "        where 
+     " shiftl       = ( 
+  shiftl_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition shiftr  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "        where 
+     " shiftr       = ( 
+  shiftr_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition arith_shiftr  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " arith_shiftr = ( 
+  arith_shiftr_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition rotl  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "          where 
+     " rotl         = ( 
+  rotl_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition rotr  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "          where 
+     " rotr         = ( 
+  rotr_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val mod_vec        : list bitU -> list bitU -> list bitU*)
+(*val mod_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
+(*val mod_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+definition mod_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " mod_vec        l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_maybe  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
+     " mod_vec_maybe  l r = ( mod_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition mod_vec_fail  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " mod_vec_fail   l r = ( maybe_fail (''mod_vec'') (mod_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_nondet  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " mod_vec_nondet l r = ( of_bits_nondet 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec l r))"
+
+
+(*val quot_vec        : list bitU -> list bitU -> list bitU*)
+(*val quot_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
+(*val quot_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+definition quot_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " quot_vec        l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_maybe  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
+     " quot_vec_maybe  l r = ( quot_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition quot_vec_fail  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " quot_vec_fail   l r = ( maybe_fail (''quot_vec'') (quot_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_nondet  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " quot_vec_nondet l r = ( of_bits_nondet 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec l r))"
+
+
+(*val quots_vec        : list bitU -> list bitU -> list bitU*)
+(*val quots_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
+(*val quots_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+definition quots_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " quots_vec        l r = ( case_option (repeat [BU] (int (List.length l))) id (quots_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quots_vec_maybe  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
+     " quots_vec_maybe  l r = ( quots_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition quots_vec_fail  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " quots_vec_fail   l r = ( maybe_fail (''quots_vec'') (quots_bv 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quots_vec_nondet  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " quots_vec_nondet l r = ( of_bits_nondet 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quots_vec l r))"
+
+
+(*val mod_vec_int        : list bitU -> integer -> list bitU*)
+(*val mod_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
+(*val mod_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+(*val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+definition mod_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " mod_vec_int        l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_int_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option "  where 
+     " mod_vec_int_maybe  l r = ( mod_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition mod_vec_int_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " mod_vec_int_fail   l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_int_nondet  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " mod_vec_int_nondet l r = ( of_bits_nondet 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec_int l r))"
+
+
+(*val quot_vec_int        : list bitU -> integer -> list bitU*)
+(*val quot_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
+(*val quot_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+(*val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+definition quot_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " quot_vec_int        l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_int_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option "  where 
+     " quot_vec_int_maybe  l r = ( quot_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition quot_vec_int_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " quot_vec_int_fail   l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+   instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_int_nondet  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
+     " quot_vec_int_nondet l r = ( of_bits_nondet 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec_int l r))"
+
+
+(*val replicate_bits : list bitU -> integer -> list bitU*)
+definition replicate_bits  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " replicate_bits = ( 
+  replicate_bits_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val duplicate : bitU -> integer -> list bitU*)
+definition duplicate  :: " bitU \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " duplicate = ( 
+  duplicate_bit_bv instance_Sail2_values_BitU_Sail2_values_bitU_dict )"
+
+definition duplicate_maybe  :: " bitU \<Rightarrow> int \<Rightarrow>((bitU)list)option "  where 
+     " duplicate_maybe b n = ( Some (duplicate b n))"
+
+definition duplicate_fail  :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " duplicate_fail b n = ( return (duplicate b n))"
+
+definition duplicate_nondet  :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad "  where 
+     " duplicate_nondet b n = (
+  bool_of_bitU_nondet b \<bind> (\<lambda> b . 
+  return (duplicate (bitU_of_bool b) n)))"
+
+
+(*val reverse_endianness : list bitU -> list bitU*)
+definition reverse_endianness  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
+     " reverse_endianness v = ( reverse_endianness_list v )"
+
+
+(*val get_slice_int : integer -> integer -> integer -> list bitU*)
+definition get_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " get_slice_int = ( 
+  get_slice_int_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*)
+definition set_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int "  where 
+     " set_slice_int = ( 
+  set_slice_int_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+(*val slice : list bitU -> integer -> integer -> list bitU*)
+definition slice  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " slice v lo len = (
+  subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
+
+
+(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*)
+definition set_slice  :: " int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = (
+  update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
+
+
+(*val eq_vec    : list bitU -> list bitU -> bool*)
+(*val neq_vec   : list bitU -> list bitU -> bool*)
+definition eq_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool "     where 
+     " eq_vec    = ( 
+  eq_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition neq_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool "    where 
+     " neq_vec   = ( 
+  neq_bv
+    (instance_Sail2_values_Bitvector_list_dict
+       instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy b/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
new file mode 100644
index 00000000..c6d1a865
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
@@ -0,0 +1,608 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_operators_mwords.lem.\<close>
+
+theory "Sail2_operators_mwords" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Lem_machine_word" 
+	 "Sail2_values" 
+	 "Sail2_operators" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+definition uint_maybe  :: "('a::len)Word.word \<Rightarrow>(int)option "  where 
+     " uint_maybe v = ( Some (Word.uint v))"
+
+definition uint_fail  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
+     " uint_fail v = ( return (Word.uint v))"
+
+definition uint_nondet  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
+     " uint_nondet v = ( return (Word.uint v))"
+
+definition sint_maybe  :: "('a::len)Word.word \<Rightarrow>(int)option "  where 
+     " sint_maybe v = ( Some (Word.sint v))"
+
+definition sint_fail  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
+     " sint_fail v = ( return (Word.sint v))"
+
+definition sint_nondet  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
+     " sint_nondet v = ( return (Word.sint v))"
+
+
+(*val vec_of_bits_maybe    : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*)
+(*val vec_of_bits_fail     : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
+(*val vec_of_bits_nondet   : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
+(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*)
+(*val vec_of_bits          : forall 'a. Size 'a => list bitU -> mword 'a*)
+definition vec_of_bits_maybe  :: "(bitU)list \<Rightarrow>(('a::len)Word.word)option "  where 
+     " vec_of_bits_maybe bits = ( map_option Word.of_bl (just_list (List.map bool_of_bitU bits)))"
+
+definition vec_of_bits_fail  :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " vec_of_bits_fail bits = ( of_bits_fail 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+definition vec_of_bits_nondet  :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " vec_of_bits_nondet bits = ( of_bits_nondet 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+definition vec_of_bits_failwith  :: "(bitU)list \<Rightarrow>('a::len)Word.word "  where 
+     " vec_of_bits_failwith bits = ( of_bits_failwith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+definition vec_of_bits  :: "(bitU)list \<Rightarrow>('a::len)Word.word "  where 
+     " vec_of_bits bits = ( of_bits_failwith 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+
+(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+definition access_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_vec_inc = ( 
+  access_bv_inc instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+definition access_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_vec_dec = ( 
+  access_bv_dec instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+definition update_vec_dec_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " update_vec_dec_maybe w i b = ( update_mword_dec w i b )"
+
+definition update_vec_dec_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " update_vec_dec_fail w i b = (
+  bool_of_bitU_fail b \<bind> (\<lambda> b . 
+  return (update_mword_bool_dec w i b)))"
+
+definition update_vec_dec_nondet  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " update_vec_dec_nondet w i b = (
+  bool_of_bitU_nondet b \<bind> (\<lambda> b . 
+  return (update_mword_bool_dec w i b)))"
+
+definition update_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " update_vec_dec w i b = ( maybe_failwith (update_vec_dec_maybe w i b))"
+
+
+definition update_vec_inc_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " update_vec_inc_maybe w i b = ( update_mword_inc w i b )"
+
+definition update_vec_inc_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " update_vec_inc_fail w i b = (
+  bool_of_bitU_fail b \<bind> (\<lambda> b . 
+  return (update_mword_bool_inc w i b)))"
+
+definition update_vec_inc_nondet  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " update_vec_inc_nondet w i b = (
+  bool_of_bitU_nondet b \<bind> (\<lambda> b . 
+  return (update_mword_bool_inc w i b)))"
+
+definition update_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " update_vec_inc w i b = ( maybe_failwith (update_vec_inc_maybe w i b))"
+
+
+(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+definition subrange_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " subrange_vec_dec w i j = ( Word.slice (nat_of_int j) w )"
+
+
+(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+definition subrange_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " subrange_vec_inc w i j = ( subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j))"
+
+
+(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+definition update_subrange_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " update_subrange_vec_dec w i j w' = ( Lem.word_update w (nat_of_int j) (nat_of_int i) w' )"
+
+
+(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+definition update_subrange_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " update_subrange_vec_inc w i j w' = ( update_subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j) w' )"
+
+
+(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+definition extz_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " extz_vec _ w = ( Word.ucast w )"
+
+
+(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+definition exts_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " exts_vec _ w = ( Word.scast w )"
+
+
+(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+definition zero_extend  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " zero_extend w _ = ( Word.ucast w )"
+
+
+(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+definition sign_extend  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " sign_extend w _ = ( Word.scast w )"
+
+
+(*val zeros : forall 'a. Size 'a => integer -> mword 'a*)
+definition zeros  :: " int \<Rightarrow>('a::len)Word.word "  where 
+     " zeros _ = ( Word.word_of_int (int(( 0 :: nat))))"
+
+
+(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+definition vector_truncate  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " vector_truncate w _ = ( Word.ucast w )"
+
+
+(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
+definition concat_vec  :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('c::len)Word.word "  where 
+     " concat_vec = ( Word.word_cat )"
+
+
+(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*)
+definition cons_vec_bool  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " cons_vec_bool b w = ( Word.of_bl (b # Word.to_bl w))"
+
+definition cons_vec_maybe  :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>(('b::len)Word.word)option "  where 
+     " cons_vec_maybe b w = ( map_option (\<lambda> b .  cons_vec_bool b w) (bool_of_bitU b))"
+
+definition cons_vec_fail  :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad "  where 
+     " cons_vec_fail b w = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (cons_vec_bool b w)))"
+
+definition cons_vec_nondet  :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad "  where 
+     " cons_vec_nondet b w = ( bool_of_bitU_nondet b \<bind> (\<lambda> b .  return (cons_vec_bool b w)))"
+
+definition cons_vec  :: " bitU \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " cons_vec b w = ( maybe_failwith (cons_vec_maybe b w))"
+
+
+(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*)
+definition vec_of_bool  :: " int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " vec_of_bool _ b = ( Word.of_bl [b])"
+
+definition vec_of_bit_maybe  :: " int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " vec_of_bit_maybe len b = ( map_option (vec_of_bool len) (bool_of_bitU b))"
+
+definition vec_of_bit_fail  :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " vec_of_bit_fail len b = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (vec_of_bool len b)))"
+
+definition vec_of_bit_nondet  :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " vec_of_bit_nondet len b = ( bool_of_bitU_nondet b \<bind> (\<lambda> b .  return (vec_of_bool len b)))"
+
+definition vec_of_bit  :: " int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " vec_of_bit len b = ( maybe_failwith (vec_of_bit_maybe len b))"
+
+
+(*val cast_bool_vec : bool -> mword ty1*)
+definition cast_bool_vec  :: " bool \<Rightarrow>(1)Word.word "  where 
+     " cast_bool_vec b = ( vec_of_bool(( 1 :: int)) b )"
+
+definition cast_unit_vec_maybe  :: " bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " cast_unit_vec_maybe b = ( vec_of_bit_maybe(( 1 :: int)) b )"
+
+definition cast_unit_vec_fail  :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad "  where 
+     " cast_unit_vec_fail b = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (cast_bool_vec b)))"
+
+definition cast_unit_vec_nondet  :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad "  where 
+     " cast_unit_vec_nondet b = ( bool_of_bitU_nondet b \<bind> (\<lambda> b .  return (cast_bool_vec b)))"
+
+definition cast_unit_vec  :: " bitU \<Rightarrow>('a::len)Word.word "  where 
+     " cast_unit_vec b = ( maybe_failwith (cast_unit_vec_maybe b))"
+
+
+(*val msb : forall 'a. Size 'a => mword 'a -> bitU*)
+definition msb  :: "('a::len)Word.word \<Rightarrow> bitU "  where 
+     " msb = ( 
+  most_significant instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*)
+definition int_of_vec  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
+     " int_of_vec sign w = (
+  if sign
+  then Word.sint w
+  else Word.uint w )"
+
+definition int_of_vec_maybe  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>(int)option "  where 
+     " int_of_vec_maybe sign w = ( Some (int_of_vec sign w))"
+
+definition int_of_vec_fail  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
+     " int_of_vec_fail sign w = ( return (int_of_vec sign w))"
+
+
+(*val string_of_bits : forall 'a. Size 'a => mword 'a -> string*)
+definition string_of_bits  :: "('a::len)Word.word \<Rightarrow> string "  where 
+     " string_of_bits = ( 
+  string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val or_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
+definition and_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " and_vec = ( Bits.bitAND )"
+
+definition or_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "   where 
+     " or_vec  = ( Bits.bitOR )"
+
+definition xor_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " xor_vec = ( Bits.bitXOR )"
+
+definition not_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " not_vec = ( Bits.bitNOT )"
+
+
+(*val add_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val adds_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val sub_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val subs_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val mult_vec  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+definition add_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " add_vec   l r = ( Word.word_of_int ((int_of_mword False l) + (int_of_mword False r)))"
+
+definition adds_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " adds_vec  l r = ( Word.word_of_int ((int_of_mword True l) + (int_of_mword True r)))"
+
+definition sub_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " sub_vec   l r = ( Word.word_of_int ((int_of_mword False l) - (int_of_mword False r)))"
+
+definition subs_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " subs_vec  l r = ( Word.word_of_int ((int_of_mword True l) - (int_of_mword True r)))"
+
+definition mult_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " mult_vec  l r = ( Word.word_of_int ((int_of_mword False (Word.ucast l :: ( 'b::len)Word.word)) * (int_of_mword False (Word.ucast r :: ( 'b::len)Word.word))))"
+
+definition mults_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))"
+
+
+(*val add_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val sub_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+definition add_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " add_vec_int  l r = ( arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+)   True  l r )"
+
+definition sub_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " sub_vec_int  l r = ( arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
+
+definition mult_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " mult_vec_int l r = ( arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*)  True  (Word.scast l :: ( 'b::len)Word.word) r )"
+
+
+(*val add_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val sub_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+definition add_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " add_int_vec  l r = ( arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+)   True  l r )"
+
+definition sub_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " sub_int_vec  l r = ( arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
+
+definition mult_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
+     " mult_int_vec l r = ( arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*)  True  l (Word.scast r :: ( 'b::len)Word.word))"
+
+
+(*val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val sub_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+
+definition add_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " add_vec_bool        l r = ( arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+) False l r )"
+
+definition add_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " add_vec_bit_maybe   l r = ( map_option (add_vec_bool l) (bool_of_bitU r))"
+
+definition add_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " add_vec_bit_fail    l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (add_vec_bool l r)))"
+
+definition add_vec_bit_nondet  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " add_vec_bit_nondet  l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (add_vec_bool l r)))"
+
+definition add_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " add_vec_bit         l r = ( maybe_failwith (add_vec_bit_maybe  l r))"
+
+
+definition adds_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " adds_vec_bool       l r = ( arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+) True  l r )"
+
+definition adds_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " adds_vec_bit_maybe  l r = ( map_option (adds_vec_bool l) (bool_of_bitU r))"
+
+definition adds_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " adds_vec_bit_fail   l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (adds_vec_bool l r)))"
+
+definition adds_vec_bit_nondet  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " adds_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (adds_vec_bool l r)))"
+
+definition adds_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " adds_vec_bit        l r = ( maybe_failwith (adds_vec_bit_maybe l r))"
+
+
+definition sub_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " sub_vec_bool        l r = ( arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) False l r )"
+
+definition sub_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " sub_vec_bit_maybe   l r = ( map_option (sub_vec_bool l) (bool_of_bitU r))"
+
+definition sub_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " sub_vec_bit_fail    l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (sub_vec_bool l r)))"
+
+definition sub_vec_bit_nondet  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " sub_vec_bit_nondet  l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (sub_vec_bool l r)))"
+
+definition sub_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " sub_vec_bit         l r = ( maybe_failwith (sub_vec_bit_maybe  l r))"
+
+
+definition subs_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " subs_vec_bool       l r = ( arith_op_bv_bool 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
+
+definition subs_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " subs_vec_bit_maybe  l r = ( map_option (subs_vec_bool l) (bool_of_bitU r))"
+
+definition subs_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " subs_vec_bit_fail   l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (subs_vec_bool l r)))"
+
+definition subs_vec_bit_nondet  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " subs_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r .  return (subs_vec_bool l r)))"
+
+definition subs_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
+     " subs_vec_bit        l r = ( maybe_failwith (subs_vec_bit_maybe  l r))"
+
+
+(* TODO
+val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU)
+let maybe_mword_of_bits_overflow (bits, overflow, carry) =
+  Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits)
+
+val add_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val adds_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val sub_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val subs_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mult_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+let add_overflow_vec   l r = maybe_mword_of_bits_overflow (add_overflow_bv l r)
+let adds_overflow_vec  l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r)
+let sub_overflow_vec   l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r)
+let subs_overflow_vec  l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r)
+let mult_overflow_vec  l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r)
+let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r)
+
+val add_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+let add_overflow_vec_bit         = add_overflow_bv_bit
+let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit         = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
+
+(*val shiftl       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val shiftr       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val rotl         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val rotr         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+definition shiftl  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "        where 
+     " shiftl       = ( shiftl_mword )"
+
+definition shiftr  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "        where 
+     " shiftr       = ( shiftr_mword )"
+
+definition arith_shiftr  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " arith_shiftr = ( arith_shiftr_mword )"
+
+definition rotl  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "          where 
+     " rotl         = ( rotl_mword )"
+
+definition rotr  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "          where 
+     " rotr         = ( rotr_mword )"
+
+
+(*val mod_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val mod_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val mod_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+definition mod_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " mod_vec        l r = ( mod_mword l r )"
+
+definition mod_vec_maybe  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option "  where 
+     " mod_vec_maybe  l r = ( mod_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition mod_vec_fail  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " mod_vec_fail   l r = ( maybe_fail (''mod_vec'') (mod_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition mod_vec_nondet  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " mod_vec_nondet l r = (
+  (case  (mod_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      Some w => return w
+    | None => mword_nondet () 
+  ))"
+
+
+(*val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val quot_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val quot_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+definition quot_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " quot_vec        l r = ( quot_mword l r )"
+
+definition quot_vec_maybe  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option "  where 
+     " quot_vec_maybe  l r = ( quot_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition quot_vec_fail  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " quot_vec_fail   l r = ( maybe_fail (''quot_vec'') (quot_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition quot_vec_nondet  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " quot_vec_nondet l r = (
+  (case  (quot_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      Some w => return w
+    | None => mword_nondet () 
+  ))"
+
+
+(*val quots_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val quots_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val quots_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+definition quots_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " quots_vec        l r = ( quots_mword l r )"
+
+definition quots_vec_maybe  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option "  where 
+     " quots_vec_maybe  l r = ( quots_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition quots_vec_fail  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " quots_vec_fail   l r = ( maybe_fail (''quots_vec'') (quots_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition quots_vec_nondet  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " quots_vec_nondet l r = (
+  (case  (quots_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      Some w => return w
+    | None => mword_nondet () 
+  ))"
+
+
+(*val mod_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mod_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
+(*val mod_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+(*val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+definition mod_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " mod_vec_int        l r = ( mod_mword_int l r )"
+
+definition mod_vec_int_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option "  where 
+     " mod_vec_int_maybe  l r = ( mod_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition mod_vec_int_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " mod_vec_int_fail   l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition mod_vec_int_nondet  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " mod_vec_int_nondet l r = (
+  (case  (mod_bv_int instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      Some w => return w
+    | None => mword_nondet () 
+  ))"
+
+
+(*val quot_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val quot_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
+(*val quot_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+(*val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+definition quot_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " quot_vec_int        l r = ( quot_mword_int l r )"
+
+definition quot_vec_int_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option "  where 
+     " quot_vec_int_maybe  l r = ( quot_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition quot_vec_int_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " quot_vec_int_fail   l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition quot_vec_int_nondet  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " quot_vec_int_nondet l r = (
+  (case  (quot_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+      Some w => return w
+    | None => mword_nondet () 
+  ))"
+
+
+(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+definition replicate_bits  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " replicate_bits v count1 = ( Word.of_bl (repeat (Word.to_bl v) count1))"
+
+
+(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*)
+definition duplicate_bool  :: " bool \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " duplicate_bool   b n = ( Word.of_bl (repeat [b] n))"
+
+definition duplicate_maybe  :: " bitU \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option "  where 
+     " duplicate_maybe  b n = ( map_option (\<lambda> b .  duplicate_bool b n) (bool_of_bitU b))"
+
+definition duplicate_fail  :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " duplicate_fail   b n = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (duplicate_bool b n)))"
+
+definition duplicate_nondet  :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
+     " duplicate_nondet b n = ( bool_of_bitU_nondet b \<bind> (\<lambda> b .  return (duplicate_bool b n)))"
+
+definition duplicate  :: " bitU \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " duplicate        b n = ( maybe_failwith (duplicate_maybe b n))"
+
+
+(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*)
+definition reverse_endianness  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " reverse_endianness v = ( Word.of_bl (reverse_endianness_list (Word.to_bl v)))"
+
+
+(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*)
+definition get_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
+     " get_slice_int = ( 
+  get_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*)
+definition set_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
+     " set_slice_int = ( 
+  set_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+definition slice  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " slice v lo len = (
+  subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
+
+
+(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*)
+definition set_slice  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = (
+  update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
+
+
+(*val eq_vec    : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+(*val neq_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
new file mode 100644
index 00000000..47bf32b2
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
@@ -0,0 +1,170 @@
+theory Sail2_operators_mwords_lemmas
+  imports Sail2_operators_mwords
+begin
+
+lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_nondet_def
+lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_nondet_def
+
+lemma bools_of_bits_nondet_just_list[simp]:
+  assumes "just_list (map bool_of_bitU bus) = Some bs"
+  shows "bools_of_bits_nondet bus = return bs"
+proof -
+  have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_nondet b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)"
+    if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools
+  proof (use that in \<open>induction bus arbitrary: bs bools\<close>)
+    case (Cons bu bus bs)
+    obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b"
+      using Cons.prems by (cases bu) (auto split: option.splits)
+    then show ?case
+      using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"]
+      by (cases bu) (auto simp: bool_of_bitU_nondet_def split: option.splits)
+  qed auto
+  then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_nondet_def
+    by auto
+qed
+
+lemma of_bits_mword_return_of_bl[simp]:
+  assumes "just_list (map bool_of_bitU bus) = Some bs"
+  shows "of_bits_nondet BC_mword bus = return (of_bl bs)"
+    and "of_bits_fail BC_mword bus = return (of_bl bs)"
+  by (auto simp: of_bits_nondet_def of_bits_fail_def maybe_fail_def assms BC_mword_defs)
+
+lemma vec_of_bits_of_bl[simp]:
+  assumes "just_list (map bool_of_bitU bus) = Some bs"
+  shows "vec_of_bits_maybe bus = Some (of_bl bs)"
+    and "vec_of_bits_fail bus = return (of_bl bs)"
+    and "vec_of_bits_nondet bus = return (of_bl bs)"
+    and "vec_of_bits_failwith bus = of_bl bs"
+    and "vec_of_bits bus = of_bl bs"
+  unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_nondet_def
+            vec_of_bits_failwith_def vec_of_bits_def
+  by (auto simp: assms)
+
+lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def]
+
+lemma access_vec_inc_test_bit[simp]:
+  fixes w :: "('a::len) word"
+  assumes "n \<ge> 0" and "nat n < LENGTH('a)"
+  shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))"
+  using assms
+  by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl)
+
+lemma bool_of_bitU_monadic_simps[simp]:
+  "bool_of_bitU_fail B0 = return False"
+  "bool_of_bitU_fail B1 = return True"
+  "bool_of_bitU_fail BU = Fail ''bool_of_bitU''"
+  "bool_of_bitU_nondet B0 = return False"
+  "bool_of_bitU_nondet B1 = return True"
+  "bool_of_bitU_nondet BU = undefined_bool ()"
+  unfolding bool_of_bitU_fail_def bool_of_bitU_nondet_def
+  by auto
+
+lemma update_vec_dec_simps[simp]:
+  "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)"
+  "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)"
+  "update_vec_dec_maybe w i BU = None"
+  "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)"
+  "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)"
+  "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''"
+  "update_vec_dec_nondet w i B0 = return (set_bit w (nat i) False)"
+  "update_vec_dec_nondet w i B1 = return (set_bit w (nat i) True)"
+  "update_vec_dec_nondet w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))"
+  "update_vec_dec w i B0 = set_bit w (nat i) False"
+  "update_vec_dec w i B1 = set_bit w (nat i) True"
+  unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_nondet_def update_vec_dec_def
+  by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def)
+
+lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]:
+  "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)"
+  by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq)
+
+declare subrange_vec_dec_def[simp]
+
+lemma update_subrange_vec_dec_update_subrange_list_dec:
+  assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)"
+  shows "update_subrange_vec_dec (w :: 'a::len word) i j w' =
+         of_bl (update_subrange_list_dec (to_bl w) i j (to_bl w'))"
+  using assms
+  unfolding update_subrange_vec_dec_def update_subrange_list_dec_def update_subrange_list_inc_def
+  by (auto simp: word_update_def split_at_def Let_def nat_diff_distrib min_def)
+
+lemma subrange_vec_dec_subrange_list_dec:
+  assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)" and "int LENGTH('b) = i - j + 1"
+  shows "subrange_vec_dec (w :: 'a::len word) i j = (of_bl (subrange_list_dec (to_bl w) i j) :: 'b::len word)"
+  using assms unfolding subrange_vec_dec_def
+  by (auto simp: subrange_list_dec_drop_take slice_take of_bl_drop')
+
+lemma slice_simp[simp]: "slice w lo len = Word.slice (nat lo) w"
+  by (auto simp: slice_def)
+
+declare slice_id[simp]
+
+lemma of_bools_of_bl[simp]: "of_bools_method BC_mword = of_bl"
+  by (auto simp: BC_mword_defs)
+
+lemma of_bl_bin_word_of_int:
+  "len = LENGTH('a) \<Longrightarrow> of_bl (bin_to_bl_aux len n []) = (word_of_int n :: ('a::len) word)"
+  by (auto simp: of_bl_def bin_bl_bin')
+
+lemma get_slice_int_0_bin_to_bl[simp]:
+  "len > 0 \<Longrightarrow> get_slice_int len n 0 = of_bl (bin_to_bl (nat len) n)"
+  unfolding get_slice_int_def get_slice_int_bv_def subrange_list_def
+  by (auto simp: subrange_list_dec_drop_take len_bin_to_bl_aux)
+
+lemma to_bl_of_bl[simp]:
+  fixes bl :: "bool list"
+  defines w: "w \<equiv> of_bl bl :: 'a::len word"
+  assumes len: "length bl = LENGTH('a)"
+  shows "to_bl w = bl"
+  using len unfolding w by (intro word_bl.Abs_inverse) auto
+
+lemma reverse_endianness_byte[simp]:
+  "LENGTH('a) = 8 \<Longrightarrow> reverse_endianness (w :: 'a::len word) = w"
+  unfolding reverse_endianness_def by (auto simp: reverse_endianness_list_simps)
+
+lemma reverse_reverse_endianness[simp]:
+  "8 dvd LENGTH('a) \<Longrightarrow> reverse_endianness (reverse_endianness w) = (w :: 'a::len word)"
+  unfolding reverse_endianness_def by (simp)
+
+lemma replicate_bits_zero[simp]: "replicate_bits 0 n = 0"
+  by (intro word_eqI) (auto simp: replicate_bits_def test_bit_of_bl rev_nth nth_repeat simp del: repeat.simps)
+
+declare extz_vec_def[simp]
+declare exts_vec_def[simp]
+declare concat_vec_def[simp]
+
+lemma msb_Bits_msb[simp]:
+  "msb w = bitU_of_bool (Bits.msb w)"
+  by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits)
+
+declare and_vec_def[simp]
+declare or_vec_def[simp]
+declare xor_vec_def[simp]
+declare not_vec_def[simp]
+
+lemma arith_vec_simps[simp]:
+  "add_vec l r = l + r"
+  "sub_vec l r = l - r"
+  "mult_vec l r = (ucast l) * (ucast r)"
+  unfolding add_vec_def sub_vec_def mult_vec_def
+  by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def)
+
+declare adds_vec_def[simp]
+declare subs_vec_def[simp]
+declare mults_vec_def[simp]
+
+lemma arith_vec_int_simps:
+  fixes l :: "'a::len word"
+  shows "add_vec_int l r = word_of_int (sint l + sint (word_of_int r :: 'a word))"
+    and "sub_vec_int l r = word_of_int (sint l - sint (word_of_int r :: 'a word))"
+    and "(mult_vec_int l r :: 'b::len word) = word_of_int (sint (scast l :: 'b word) * sint (word_of_int r :: 'b word))"
+  unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
+  by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
+
+lemma shiftl_simp[simp]: "shiftl w l = w << (nat l)"
+  by (auto simp: shiftl_def shiftl_mword_def)
+
+lemma shiftr_simp[simp]: "shiftr w l = w >> (nat l)"
+  by (auto simp: shiftr_def shiftr_mword_def)
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_prompt.thy b/snapshots/isabelle/lib/sail/Sail2_prompt.thy
new file mode 100644
index 00000000..e639d59a
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_prompt.thy
@@ -0,0 +1,162 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_prompt.lem.\<close>
+
+theory "Sail2_prompt" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Sail2_values" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt_monad_lemmas" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Sail_impl_base*)
+(*open import Sail2_values*)
+(*open import Sail2_prompt_monad*)
+(*open import {isabelle} `Sail2_prompt_monad_lemmas`*)
+
+(*val >>= : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*)
+
+(*val >> : forall 'rv 'b 'e. monad 'rv unit 'e -> monad 'rv 'b 'e -> monad 'rv 'b 'e*)
+
+(*val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*)
+fun  iter_aux  :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " iter_aux i f (x # xs) = ( f i x \<then> iter_aux (i +( 1 :: int)) f xs )"
+|" iter_aux i f ([]) = ( return ()  )"
+
+
+(*val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*)
+definition iteri  :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " iteri f xs = ( iter_aux(( 0 :: int)) f xs )"
+
+
+(*val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*)
+definition iter  :: "('a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " iter f xs = ( iteri ( \<lambda>x .  
+  (case  x of _ => \<lambda> x .  f x )) xs )"
+
+
+(*val foreachM : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+fun  foreachM  :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad "  where 
+     " foreachM ([]) vars body = ( return vars )"
+|" foreachM (x # xs) vars body = (
+  body x vars \<bind> (\<lambda> vars . 
+  foreachM xs vars body))"
+
+
+(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+definition and_boolM  :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " and_boolM l r = ( l \<bind> (\<lambda> l .  if l then r else return False))"
+
+
+(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+definition or_boolM  :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " or_boolM l r = ( l \<bind> (\<lambda> l .  if l then return True else r))"
+
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+definition bool_of_bitU_fail  :: " bitU \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " bool_of_bitU_fail = ( \<lambda>x .  
+  (case  x of
+        B0 => return False
+    | B1 => return True
+    | BU => Fail (''bool_of_bitU'')
+  ) )"
+
+
+(*val bool_of_bitU_nondet : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+definition bool_of_bitU_nondet  :: " bitU \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " bool_of_bitU_nondet = ( \<lambda>x .  
+  (case  x of
+        B0 => return False
+    | B1 => return True
+    | BU => undefined_bool () 
+  ) )"
+
+
+(*val bools_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e*)
+definition bools_of_bits_nondet  :: "(bitU)list \<Rightarrow>('rv,((bool)list),'e)monad "  where 
+     " bools_of_bits_nondet bits = (
+  foreachM bits []
+    (\<lambda> b bools . 
+      bool_of_bitU_nondet b \<bind> (\<lambda> b . 
+      return (bools @ [b]))))"
+
+
+(*val of_bits_nondet : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*)
+definition of_bits_nondet  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad "  where 
+     " of_bits_nondet dict_Sail2_values_Bitvector_a bits = (
+  bools_of_bits_nondet bits \<bind> (\<lambda> bs . 
+  return ((of_bools_method   dict_Sail2_values_Bitvector_a) bs)))"
+
+
+(*val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*)
+definition of_bits_fail  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad "  where 
+     " of_bits_fail dict_Sail2_values_Bitvector_a bits = ( maybe_fail (''of_bits'') (
+  (of_bits_method   dict_Sail2_values_Bitvector_a) bits))"
+
+
+(*val mword_nondet : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e*)
+definition mword_nondet  :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
+     " mword_nondet _ = (
+  bools_of_bits_nondet (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \<bind> (\<lambda> bs . 
+  return (Word.of_bl bs)))"
+
+
+(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+function (sequential,domintros)  whileM  :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad "  where 
+     " whileM vars cond body = (
+  cond vars \<bind> (\<lambda> cond_val . 
+  if cond_val then
+    body vars \<bind> (\<lambda> vars .  whileM vars cond body)
+  else return vars))" 
+by pat_completeness auto
+
+
+(*val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+function (sequential,domintros)  untilM  :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad "  where 
+     " untilM vars cond body = (
+  body vars \<bind> (\<lambda> vars . 
+  cond vars \<bind> (\<lambda> cond_val . 
+  if cond_val then return vars else untilM vars cond body)))" 
+by pat_completeness auto
+
+
+(*val internal_pick : forall 'rv 'a 'e. list 'a -> monad 'rv 'a 'e*)
+definition internal_pick  :: " 'a list \<Rightarrow>('rv,'a,'e)monad "  where 
+     " internal_pick xs = (
+  (* Use sufficiently many undefined bits and convert into an index into the list *)
+  bools_of_bits_nondet (repeat [BU] (int (List.length xs))) \<bind> (\<lambda> bs . 
+  (let idx = (( (nat_of_bools bs)) mod List.length xs) in
+  (case  index xs idx of
+      Some x => return x
+    | None => Fail (''internal_pick'')
+  ))))"
+
+
+(*let write_two_regs r1 r2 vec =
+  let is_inc =
+    let is_inc_r1 = is_inc_of_reg r1 in
+    let is_inc_r2 = is_inc_of_reg r2 in
+    let () = ensure (is_inc_r1 = is_inc_r2)
+                    write_two_regs called with vectors of different direction in
+    is_inc_r1 in
+
+  let (size_r1 : integer) = size_of_reg r1 in
+  let (start_vec : integer) = get_start vec in
+  let size_vec = length vec in
+  let r1_v =
+    if is_inc
+    then slice vec start_vec (size_r1 - start_vec - 1)
+    else slice vec start_vec (start_vec - size_r1 - 1) in
+  let r2_v =
+    if is_inc
+    then slice vec (size_r1 - start_vec) (size_vec - start_vec)
+    else slice vec (start_vec - size_r1) (start_vec - size_vec) in
+  write_reg r1 r1_v >> write_reg r2 r2_v*)
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy b/snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy
new file mode 100644
index 00000000..d1259332
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy
@@ -0,0 +1,275 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_prompt_monad.lem.\<close>
+
+theory "Sail2_prompt_monad" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Sail_impl_base*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+
+type_synonym register_name =" string "
+type_synonym address =" bitU list "
+
+datatype( 'regval, 'a, 'e) monad =
+    Done " 'a "
+  (* Read a number of bytes from memory, returned in little endian order *)
+  | Read_mem " read_kind " " address " " nat " " ( memory_byte list \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Read the tag of a memory address *)
+  | Read_tag " address " " (bitU \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Tell the system a write is imminent, at address lifted, of size nat *)
+  | Write_ea " write_kind " " address " " nat " " ('regval, 'a, 'e) monad "
+  (* Request the result of store-exclusive *)
+  | Excl_res " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Request to write memory at last signalled address. Memory value should be 8
+     times the size given in ea signal, given in little endian order *)
+  | Write_memv " memory_byte list " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Request to write the tag at given address. *)
+  | Write_tag " address " " bitU " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Tell the system to dynamically recalculate dependency footprint *)
+  | Footprint " ('regval, 'a, 'e) monad "
+  (* Request a memory barrier *)
+  | Barrier " barrier_kind " " ('regval, 'a, 'e) monad "
+  (* Request to read register, will track dependency when mode.track_values *)
+  | Read_reg " register_name " " ('regval \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Request to write register *)
+  | Write_reg " register_name " " 'regval " " ('regval, 'a, 'e) monad "
+  (* Request to choose a Boolean, e.g. to resolve an undefined bit *)
+  | Undefined " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+  (* Print debugging or tracing information *)
+  | Print " string " " ('regval, 'a, 'e) monad "
+  (*Result of a failed assert with possible error message to report*)
+  | Fail " string "
+  (* Exception of type 'e *)
+  | Exception " 'e "
+
+(*val return : forall 'rv 'a 'e. 'a -> monad 'rv 'a 'e*)
+definition return  :: " 'a \<Rightarrow>('rv,'a,'e)monad "  where 
+     " return a = ( Done a )"
+
+
+(*val bind : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*)
+function (sequential,domintros)  bind  :: "('rv,'a,'e)monad \<Rightarrow>('a \<Rightarrow>('rv,'b,'e)monad)\<Rightarrow>('rv,'b,'e)monad "  where 
+     " bind (Done a) f = ( f a )"
+|" bind (Read_mem rk a sz k) f = ( Read_mem rk a sz (\<lambda> v .  bind (k v) f))"
+|" bind (Read_tag a k) f = (       Read_tag a       (\<lambda> v .  bind (k v) f))"
+|" bind (Write_memv descr k) f = ( Write_memv descr (\<lambda> v .  bind (k v) f))"
+|" bind (Write_tag a t k) f = (    Write_tag a t    (\<lambda> v .  bind (k v) f))"
+|" bind (Read_reg descr k) f = (   Read_reg descr   (\<lambda> v .  bind (k v) f))"
+|" bind (Excl_res k) f = (         Excl_res         (\<lambda> v .  bind (k v) f))"
+|" bind (Undefined k) f = (        Undefined        (\<lambda> v .  bind (k v) f))"
+|" bind (Write_ea wk a sz k) f = ( Write_ea wk a sz (bind k f))"
+|" bind (Footprint k) f = (        Footprint        (bind k f))"
+|" bind (Barrier bk k) f = (       Barrier bk       (bind k f))"
+|" bind (Write_reg r v k) f = (    Write_reg r v    (bind k f))"
+|" bind (Print msg k) f = (        Print msg        (bind k f))"
+|" bind (Fail descr) f = (         Fail descr )"
+|" bind (Exception e) f = (        Exception e )" 
+by pat_completeness auto
+
+
+(*val exit : forall 'rv 'a 'e. unit -> monad 'rv 'a 'e*)
+definition exit0  :: " unit \<Rightarrow>('rv,'a,'e)monad "  where 
+     " exit0 _ = ( Fail (''exit''))"
+
+
+(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*)
+definition undefined_bool  :: " unit \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " undefined_bool _ = ( Undefined return )"
+
+
+(*val assert_exp : forall 'rv 'e. bool -> string -> monad 'rv unit 'e*)
+definition assert_exp  :: " bool \<Rightarrow> string \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " assert_exp exp msg = ( if exp then Done ()  else Fail msg )"
+
+
+(*val throw : forall 'rv 'a 'e. 'e -> monad 'rv 'a 'e*)
+definition throw  :: " 'e \<Rightarrow>('rv,'a,'e)monad "  where 
+     " throw e = ( Exception e )"
+
+
+(*val try_catch : forall 'rv 'a 'e1 'e2. monad 'rv 'a 'e1 -> ('e1 -> monad 'rv 'a 'e2) -> monad 'rv 'a 'e2*)
+function (sequential,domintros)  try_catch  :: "('rv,'a,'e1)monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,'e2)monad)\<Rightarrow>('rv,'a,'e2)monad "  where 
+     " try_catch (Done a) h = (             Done a )"
+|" try_catch (Read_mem rk a sz k) h = ( Read_mem rk a sz (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Read_tag a k) h = (       Read_tag a       (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Write_memv descr k) h = ( Write_memv descr (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Write_tag a t k) h = (    Write_tag a t    (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Read_reg descr k) h = (   Read_reg descr   (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Excl_res k) h = (         Excl_res         (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Undefined k) h = (        Undefined        (\<lambda> v .  try_catch (k v) h))"
+|" try_catch (Write_ea wk a sz k) h = ( Write_ea wk a sz (try_catch k h))"
+|" try_catch (Footprint k) h = (        Footprint        (try_catch k h))"
+|" try_catch (Barrier bk k) h = (       Barrier bk       (try_catch k h))"
+|" try_catch (Write_reg r v k) h = (    Write_reg r v    (try_catch k h))"
+|" try_catch (Print msg k) h = (        Print msg        (try_catch k h))"
+|" try_catch (Fail descr) h = (         Fail descr )"
+|" try_catch (Exception e) h = (        h e )" 
+by pat_completeness auto
+
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is either 'r 'e, where Right e
+   represents a proper exception and Left r an early return of value r. *)
+type_synonym( 'rv, 'a, 'r, 'e) monadR =" ('rv, 'a, ( ('r, 'e)sum)) monad "
+
+(*val early_return : forall 'rv 'a 'r 'e. 'r -> monadR 'rv 'a 'r 'e*)
+definition early_return  :: " 'r \<Rightarrow>('rv,'a,(('r,'e)sum))monad "  where 
+     " early_return r = ( throw (Inl r))"
+
+
+(*val catch_early_return : forall 'rv 'a 'e. monadR 'rv 'a 'a 'e -> monad 'rv 'a 'e*)
+definition catch_early_return  :: "('rv,'a,(('a,'e)sum))monad \<Rightarrow>('rv,'a,'e)monad "  where 
+     " catch_early_return m = (
+  try_catch m
+    (\<lambda>x .  (case  x of   Inl a => return a | Inr e => throw e )))"
+
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftR : forall 'rv 'a 'r 'e. monad 'rv 'a 'e -> monadR 'rv 'a 'r 'e*)
+definition liftR  :: "('rv,'a,'e)monad \<Rightarrow>('rv,'a,(('r,'e)sum))monad "  where 
+     " liftR m = ( try_catch m (\<lambda> e .  throw (Inr e)))"
+
+
+(* Catch exceptions in the presence of early returns *)
+(*val try_catchR : forall 'rv 'a 'r 'e1 'e2. monadR 'rv 'a 'r 'e1 -> ('e1 -> monadR 'rv 'a 'r 'e2) ->  monadR 'rv 'a 'r 'e2*)
+definition try_catchR  :: "('rv,'a,(('r,'e1)sum))monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,(('r,'e2)sum))monad)\<Rightarrow>('rv,'a,(('r,'e2)sum))monad "  where 
+     " try_catchR m h = (
+  try_catch m
+    (\<lambda>x .  (case  x of   Inl r => throw (Inl r) | Inr e => h e )))"
+
+
+(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*)
+definition maybe_fail  :: " string \<Rightarrow> 'a option \<Rightarrow>('rv,'a,'e)monad "  where 
+     " maybe_fail msg = ( \<lambda>x .  
+  (case  x of   Some a => return a | None => Fail msg ) )"
+
+
+(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*)
+definition read_mem_bytes  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,((memory_byte)list),'e)monad "  where 
+     " read_mem_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = (
+  Read_mem rk ((bits_of_method   dict_Sail2_values_Bitvector_a) addr) (nat_of_int sz) return )"
+
+
+(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*)
+definition read_mem  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,'b,'e)monad "  where 
+     " read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = (
+  bind
+    (read_mem_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_a rk addr sz)
+    (\<lambda> bytes . 
+       maybe_fail (''bits_of_mem_bytes'') (
+  (of_bits_method   dict_Sail2_values_Bitvector_b) (bits_of_mem_bytes bytes))))"
+
+
+(*val read_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bitU 'e*)
+definition read_tag  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bitU),'e)monad "  where 
+     " read_tag dict_Sail2_values_Bitvector_a addr = ( Read_tag (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) addr) return )"
+
+
+(*val excl_result : forall 'rv 'e. unit -> monad 'rv bool 'e*)
+definition excl_result  :: " unit \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " excl_result _ = ( 
+  (let k = (\<lambda> successful .  (return successful)) in Excl_res k) )"
+
+
+(*val write_mem_ea : forall 'rv 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> monad 'rv unit 'e*)
+definition write_mem_ea  :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " write_mem_ea dict_Sail2_values_Bitvector_a wk addr sz = ( Write_ea wk (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) addr) (nat_of_int sz) (Done () ))"
+
+
+(*val write_mem_val : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bool 'e*)
+definition write_mem_val  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " write_mem_val dict_Sail2_values_Bitvector_a v = ( (case  mem_bytes_of_bits 
+  dict_Sail2_values_Bitvector_a v of
+    Some v => Write_memv v return
+  | None => Fail (''write_mem_val'')
+))"
+
+
+(*val write_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> bitU -> monad 'rv bool 'e*)
+definition write_tag  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('rv,(bool),'e)monad "  where 
+     " write_tag dict_Sail2_values_Bitvector_a addr b = ( Write_tag (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) addr) b return )"
+
+
+(*val read_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> monad 'rv 'a 'e*)
+definition read_reg  :: "('s,'rv,'a)register_ref \<Rightarrow>('rv,'a,'e)monad "  where 
+     " read_reg reg = ( 
+  (let k = (\<lambda> v . 
+            (case (of_regval   reg) v of
+                  Some v => Done v
+              | None => Fail (''read_reg: unrecognised value'')
+            )) in Read_reg (name   reg) k) )"
+
+
+(* TODO
+val read_reg_range : forall 's 'r 'rv 'a 'e. Bitvector 'a => register_ref 's 'rv 'r -> integer -> integer -> monad 'rv 'a 'e
+let read_reg_range reg i j =
+  read_reg_aux of_bits (external_reg_slice reg (nat_of_int i,nat_of_int j))
+
+let read_reg_bit reg i =
+  read_reg_aux (fun v -> v) (external_reg_slice reg (nat_of_int i,nat_of_int i)) >>= fun v ->
+  return (extract_only_element v)
+
+let read_reg_field reg regfield =
+  read_reg_aux (external_reg_field_whole reg regfield)
+
+let read_reg_bitfield reg regfield =
+  read_reg_aux (external_reg_field_whole reg regfield) >>= fun v ->
+  return (extract_only_element v)*)
+
+definition reg_deref  :: "('d,'c,'b)register_ref \<Rightarrow>('c,'b,'a)monad "  where 
+     " reg_deref = ( read_reg )"
+
+
+(*val write_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> 'a -> monad 'rv unit 'e*)
+definition write_reg  :: "('s,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " write_reg reg v = ( Write_reg(name   reg) ((regval_of   reg) v) (Done () ))"
+
+
+(* TODO
+let write_reg reg v =
+  write_reg_aux (external_reg_whole reg) v
+let write_reg_range reg i j v =
+  write_reg_aux (external_reg_slice reg (nat_of_int i,nat_of_int j)) v
+let write_reg_pos reg i v =
+  let iN = nat_of_int i in
+  write_reg_aux (external_reg_slice reg (iN,iN)) [v]
+let write_reg_bit = write_reg_pos
+let write_reg_field reg regfield v =
+  write_reg_aux (external_reg_field_whole reg regfield.field_name) v
+let write_reg_field_bit reg regfield bit =
+  write_reg_aux (external_reg_field_whole reg regfield.field_name)
+                (Vector [bit] 0 (is_inc_of_reg reg))
+let write_reg_field_range reg regfield i j v =
+  write_reg_aux (external_reg_field_slice reg regfield.field_name (nat_of_int i,nat_of_int j)) v
+let write_reg_field_pos reg regfield i v =
+  write_reg_field_range reg regfield i i [v]
+let write_reg_field_bit = write_reg_field_pos*)
+
+(*val barrier : forall 'rv 'e. barrier_kind -> monad 'rv unit 'e*)
+definition barrier  :: " barrier_kind \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " barrier bk = ( Barrier bk (Done () ))"
+
+
+(*val footprint : forall 'rv 'e. unit -> monad 'rv unit 'e*)
+definition footprint  :: " unit \<Rightarrow>('rv,(unit),'e)monad "  where 
+     " footprint _ = ( Footprint (Done () ))"
+
+
+(* Define a type synonym that also takes the register state as a type parameter,
+   in order to make switching to the state monad without changing generated
+   definitions easier, see also lib/hol/prompt_monad.lem. *)
+
+type_synonym( 'regval, 'regstate, 'a, 'e) base_monad =" ('regval, 'a, 'e) monad "
+type_synonym( 'regval, 'regstate, 'a, 'r, 'e) base_monadR =" ('regval, 'a, 'r, 'e) monadR "
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy
new file mode 100644
index 00000000..25eb9f52
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy
@@ -0,0 +1,212 @@
+theory Sail2_prompt_monad_lemmas
+  imports
+    Sail2_prompt_monad
+    Sail2_values_lemmas
+begin
+
+notation bind (infixr "\<bind>" 54)
+
+abbreviation seq :: "('rv,unit,'e)monad \<Rightarrow> ('rv,'b,'e)monad \<Rightarrow>('rv,'b,'e)monad" (infixr "\<then>" 54) where
+  "m \<then> n \<equiv> m \<bind> (\<lambda>_. n)"
+
+lemma All_bind_dom: "bind_dom (m, f)"
+  by (induction m) (auto intro: bind.domintros)
+
+termination bind using All_bind_dom by auto
+lemmas bind_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = bind.induct
+
+lemma bind_return[simp]: "bind (return a) f = f a"
+  by (auto simp: return_def)
+lemma bind_return_right[simp]: "bind x return = x" by (induction x) (auto simp: return_def)
+
+lemma bind_assoc[simp]: "bind (bind m f) g = bind m (\<lambda>x. bind (f x) g)"
+  by (induction m f arbitrary: g rule: bind.induct) auto
+
+lemma bind_assert_True[simp]: "bind (assert_exp True msg) f = f ()"
+  by (auto simp: assert_exp_def)
+
+lemma All_try_catch_dom: "try_catch_dom (m, h)"
+  by (induction m) (auto intro: try_catch.domintros)
+termination try_catch using All_try_catch_dom by auto
+lemmas try_catch_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = try_catch.induct
+
+datatype 'regval event =
+  (* Request to read memory *)
+    e_read_mem read_kind "bitU list" nat "memory_byte list"
+  | e_read_tag "bitU list" bitU
+  (* Write is imminent, at address lifted, of size nat *)
+  | e_write_ea write_kind "bitU list" nat
+  (* Request the result of store-exclusive *)
+  | e_excl_res bool
+  (* Request to write memory at last signalled address. Memory value should be 8
+     times the size given in ea signal *)
+  | e_write_memv "memory_byte list" bool
+  | e_write_tag "bitU list" bitU bool
+  (* Tell the system to dynamically recalculate dependency footprint *)
+  | e_footprint
+  (* Request a memory barrier *)
+  | e_barrier " barrier_kind "
+  (* Request to read register *)
+  | e_read_reg string 'regval
+  (* Request to write register *)
+  | e_write_reg string 'regval
+  | e_undefined bool
+  | e_print string
+
+inductive_set T :: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a, 'e) monad) set" where
+  Read_mem: "((Read_mem rk addr sz k), e_read_mem rk addr sz v, k v) \<in> T"
+| Read_tag: "((Read_tag addr k), e_read_tag addr v, k v) \<in> T"
+| Write_ea: "((Write_ea wk addr sz k), e_write_ea wk addr sz, k) \<in> T"
+| Excl_res: "((Excl_res k), e_excl_res r, k r) \<in> T"
+| Write_memv: "((Write_memv v k), e_write_memv v r, k r) \<in> T"
+| Write_tag: "((Write_tag a v k), e_write_tag a v r, k r) \<in> T"
+| Footprint: "((Footprint k), e_footprint, k) \<in> T"
+| Barrier: "((Barrier bk k), e_barrier bk, k) \<in> T"
+| Read_reg: "((Read_reg r k), e_read_reg r v, k v) \<in> T"
+| Write_reg: "((Write_reg r v k), e_write_reg r v, k) \<in> T"
+| Undefined: "((Undefined k), e_undefined v, k v) \<in> T"
+| Print: "((Print msg k), e_print msg, k) \<in> T"
+
+inductive_set Traces :: "(('rv, 'a, 'e) monad \<times> 'rv event list \<times> ('rv, 'a, 'e) monad) set" where
+  Nil: "(s, [], s) \<in> Traces"
+| Step: "\<lbrakk>(s, e, s'') \<in> T; (s'', t, s') \<in> Traces\<rbrakk> \<Longrightarrow> (s, e # t, s') \<in> Traces"
+
+declare Traces.intros[intro]
+declare T.intros[intro]
+
+declare prod.splits[split]
+
+lemmas Traces_ConsI = T.intros[THEN Step, rotated]
+
+inductive_cases Traces_NilE[elim]: "(s, [], s') \<in> Traces"
+inductive_cases Traces_ConsE[elim]: "(s, e # t, s') \<in> Traces"
+
+lemma Traces_cases:
+  fixes m :: "('rv, 'a, 'e) monad"
+  assumes Run: "(m, t, m') \<in> Traces"
+  obtains (Nil) a where "m = m'" and "t = []"
+  | (Read_mem) rk addr s k t' v where "m = Read_mem rk addr s k" and "t = e_read_mem rk addr s v # t'" and "(k v, t', m') \<in> Traces"
+  | (Read_tag) addr k t' v where "m = Read_tag addr k" and "t = e_read_tag addr v # t'" and "(k v, t', m') \<in> Traces"
+  | (Write_memv) val k t' v where "m = Write_memv val k" and "t = e_write_memv val v # t'" and "(k v, t', m') \<in> Traces"
+  | (Write_tag) a val k t' v where "m = Write_tag a val k" and "t = e_write_tag a val v # t'" and "(k v, t', m') \<in> Traces"
+  | (Barrier) bk k t' v where "m = Barrier bk k" and "t = e_barrier bk # t'" and "(k, t', m') \<in> Traces"
+  | (Read_reg) reg k t' v where "m = Read_reg reg k" and "t = e_read_reg reg v # t'" and "(k v, t', m') \<in> Traces"
+  | (Excl_res) k t' v where "m = Excl_res k" and "t = e_excl_res v # t'" and "(k v, t', m') \<in> Traces"
+  | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = e_write_ea wk addr s # t'" and "(k, t', m') \<in> Traces"
+  | (Footprint) k t' where "m = Footprint k" and "t = e_footprint # t'" and "(k, t', m') \<in> Traces"
+  | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = e_write_reg reg v # t'" and "(k, t', m') \<in> Traces"
+  | (Undefined) xs v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces"
+  | (Print) msg k t' where "m = Print msg k" and "t = e_print msg # t'" and "(k, t', m') \<in> Traces"
+proof (use Run in \<open>cases m t m' set: Traces\<close>)
+  case Nil
+  then show ?thesis by (auto intro: that(1))
+next
+  case (Step e m'' t')
+  from \<open>(m, e, m'') \<in> T\<close> and \<open>t = e # t'\<close> and \<open>(m'', t', m') \<in> Traces\<close>
+  show ?thesis by (cases m e m'' rule: T.cases; elim that; blast)
+qed
+
+abbreviation Run :: "('rv, 'a, 'e) monad \<Rightarrow> 'rv event list \<Rightarrow> 'a \<Rightarrow> bool"
+  where "Run s t a \<equiv> (s, t, Done a) \<in> Traces"
+
+lemma Run_appendI:
+  assumes "(s, t1, s') \<in> Traces"
+    and "Run s' t2 a"
+  shows "Run s (t1 @ t2) a"
+proof (use assms in \<open>induction t1 arbitrary: s\<close>)
+  case (Cons e t1)
+  then show ?case by (elim Traces_ConsE) auto
+qed auto
+
+lemma bind_DoneE:
+  assumes "bind m f = Done a"
+  obtains a' where "m = Done a'" and "f a' = Done a"
+  using assms by (auto elim: bind.elims)
+
+lemma bind_T_cases:
+  assumes "(bind m f, e, s') \<in> T"
+  obtains (Done) a where "m = Done a"
+  | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T"
+  using assms by (cases; blast elim: bind.elims)
+
+lemma Run_bindI:
+  fixes m :: "('r, 'a, 'e) monad"
+  assumes "Run m t1 a1"
+    and "Run (f a1) t2 a2"
+  shows "Run (m \<bind> f) (t1 @ t2) a2"
+proof (use assms in \<open>induction m t1 "Done a1 :: ('r, 'a, 'e) monad" rule: Traces.induct\<close>)
+  case (Step s e s'' t)
+  then show ?case by (elim T.cases) auto
+qed auto
+
+lemma Run_bindE:
+  fixes m :: "('rv, 'b, 'e) monad" and a :: 'a
+  assumes "Run (bind m f) t a"
+  obtains tm am tf where "t = tm @ tf" and "Run m tm am" and "Run (f am) tf a"
+proof (use assms in \<open>induction "bind m f" t "Done a :: ('rv, 'a, 'e) monad" arbitrary: m rule: Traces.induct\<close>)
+  case Nil
+  obtain am where "m = Done am" and "f am = Done a" using Nil(1) by (elim bind_DoneE)
+  then show ?case by (intro Nil(2)) auto
+next
+  case (Step e s'' t m)
+  show thesis using Step(1)
+  proof (cases rule: bind_T_cases)
+    case (Done am)
+    then show ?thesis using Step(1,2) by (intro Step(4)[of "[]" "e # t" am]) auto
+  next
+    case (Bind m')
+    show ?thesis proof (rule Step(3)[OF Bind(1)])
+      fix tm tf am
+      assume "t = tm @ tf" and "Run m' tm am" and "Run (f am) tf a"
+      then show thesis using Bind by (intro Step(4)[of "e # tm" tf am]) auto
+    qed
+  qed
+qed
+
+lemma Run_DoneE:
+  assumes "Run (Done a) t a'"
+  obtains "t = []" and "a' = a"
+  using assms by (auto elim: Traces.cases T.cases)
+
+lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a"
+  by (auto elim: Run_DoneE)
+
+lemma Run_bindE_ignore_trace:
+  assumes "Run (m \<bind> f) t a"
+  obtains tm tf am where "Run m tm am" and "Run (f am) tf a"
+  using assms by (elim Run_bindE)
+
+lemma Run_letE:
+  assumes "Run (let x = y in f x) t a"
+  obtains "Run (f y) t a"
+  using assms by auto
+
+lemma Run_ifE:
+  assumes "Run (if b then f else g) t a"
+  obtains "b" and "Run f t a" | "\<not>b" and "Run g t a"
+  using assms by (auto split: if_splits)
+
+lemma Run_returnE:
+  assumes "Run (return x) t a"
+  obtains "t = []" and "a = x"
+  using assms by (auto simp: return_def)
+
+lemma Run_early_returnE:
+  assumes "Run (early_return x) t a"
+  shows P
+  using assms by (auto simp: early_return_def throw_def elim: Traces_cases)
+
+lemma bind_cong[fundef_cong]:
+  assumes m: "m1 = m2"
+    and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a"
+  shows "bind m1 f1 = bind m2 f2"
+  unfolding m using f
+  by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast)
+
+lemma liftR_read_reg[simp]: "liftR (read_reg reg) = read_reg reg" by (auto simp: read_reg_def liftR_def split: option.splits)
+lemma try_catch_return[simp]: "try_catch (return x) h = return x" by (auto simp: return_def)
+lemma liftR_return[simp]: "liftR (return x) = return x" by (auto simp: liftR_def)
+lemma liftR_undefined_bool[simp]: "liftR (undefined_bool ()) = undefined_bool ()" by (auto simp: undefined_bool_def liftR_def)
+lemma assert_exp_True_return[simp]: "assert_exp True msg = return ()" by (auto simp: assert_exp_def return_def)
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_state.thy b/snapshots/isabelle/lib/sail/Sail2_state.thy
new file mode 100644
index 00000000..dd591a86
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_state.thy
@@ -0,0 +1,137 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_state.lem.\<close>
+
+theory "Sail2_state" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Sail2_values" 
+	 "Sail2_state_monad" 
+	 "Sail2_state_monad_lemmas" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Sail2_values*)
+(*open import Sail2_state_monad*)
+(*open import {isabelle} `Sail2_state_monad_lemmas`*)
+
+(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+fun  iterS_aux  :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monadS "  where 
+     " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))"
+|" iterS_aux i f ([]) = ( returnS ()  )"
+
+
+(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+definition iteriS  :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monadS)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set "  where 
+     " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )"
+
+
+(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+definition iterS  :: "('a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set "  where 
+     " iterS f xs = ( iteriS ( \<lambda>x .  
+  (case  x of _ => \<lambda> x .  f x )) xs )"
+
+
+(*val foreachS : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+fun  foreachS  :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set "  where 
+     " foreachS ([]) vars body = ( returnS vars )"
+|" foreachS (x # xs) vars body = ( bindS
+     (body x vars) (\<lambda> vars . 
+     foreachS xs vars body))"
+
+
+(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+definition and_boolS  :: "('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv,(bool),'e)monadS "  where 
+     " and_boolS l r = ( bindS l (\<lambda> l .  if l then r else returnS False))"
+
+
+(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+definition or_boolS  :: "('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv,(bool),'e)monadS "  where 
+     " or_boolS l r = ( bindS l (\<lambda> l .  if l then returnS True else r))"
+
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+definition bool_of_bitU_fail  :: " bitU \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set "  where 
+     " bool_of_bitU_fail = ( \<lambda>x .  
+  (case  x of
+        B0 => returnS False
+    | B1 => returnS True
+    | BU => failS (''bool_of_bitU'')
+  ) )"
+
+
+(*val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+definition bool_of_bitU_nondetS  :: " bitU \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set "  where 
+     " bool_of_bitU_nondetS = ( \<lambda>x .  
+  (case  x of
+        B0 => returnS False
+    | B1 => returnS True
+    | BU => undefined_boolS () 
+  ) )"
+
+
+(*val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*)
+definition bools_of_bits_nondetS  :: "(bitU)list \<Rightarrow> 'rv sequential_state \<Rightarrow>((((bool)list),'e)result*'rv sequential_state)set "  where 
+     " bools_of_bits_nondetS bits = (
+  foreachS bits []
+    (\<lambda> b bools .  bindS
+      (bool_of_bitU_nondetS b) (\<lambda> b . 
+      returnS (bools @ [b]))))"
+
+
+(*val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+definition of_bits_nondetS  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monadS "  where 
+     " of_bits_nondetS dict_Sail2_values_Bitvector_a bits = ( bindS
+  (bools_of_bits_nondetS bits) (\<lambda> bs . 
+  returnS ((of_bools_method   dict_Sail2_values_Bitvector_a) bs)))"
+
+
+(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+definition of_bits_failS  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'rv sequential_state \<Rightarrow>(('a,'e)result*'rv sequential_state)set "  where 
+     " of_bits_failS dict_Sail2_values_Bitvector_a bits = ( maybe_failS (''of_bits'') (
+  (of_bits_method   dict_Sail2_values_Bitvector_a) bits))"
+
+
+(*val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*)
+definition mword_nondetS  :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monadS "  where 
+     " mword_nondetS _ = ( bindS
+  (bools_of_bits_nondetS (repeat [BU] (int (len_of (TYPE(_) :: 'a itself))))) (\<lambda> bs . 
+  returnS (Word.of_bl bs)))"
+
+
+
+(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+function (sequential,domintros)  whileS  :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set "  where 
+     " whileS vars cond body s = (
+  ( bindS(cond vars) (\<lambda> cond_val s' . 
+  if cond_val then
+    ( bindS(body vars) (\<lambda> vars s'' .  whileS vars cond body s'')) s'
+  else returnS vars s')) s )" 
+by pat_completeness auto
+
+
+(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+function (sequential,domintros)  untilS  :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set "  where 
+     " untilS vars cond body s = (
+  ( bindS(body vars) (\<lambda> vars s' . 
+  ( bindS(cond vars) (\<lambda> cond_val s'' . 
+  if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )" 
+by pat_completeness auto
+
+
+(*val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e*)
+definition internal_pickS  :: " 'a list \<Rightarrow>('rv,'a,'e)monadS "  where 
+     " internal_pickS xs = ( bindS
+  (
+  (* Use sufficiently many undefined bits and convert into an index into the list *)bools_of_bits_nondetS (repeat [BU] (int (List.length xs)))) (\<lambda> bs . 
+  (let idx = (( (nat_of_bools bs)) mod List.length xs) in
+  (case  index xs idx of
+      Some x => returnS x
+    | None => failS (''internal_pick'')
+  ))))"
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy
new file mode 100644
index 00000000..ba69d0d8
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy
@@ -0,0 +1,387 @@
+theory Sail2_state_lemmas
+  imports Sail2_state Sail2_state_lifting
+begin
+
+lemma All_liftState_dom: "liftState_dom (r, m)"
+  by (induction m) (auto intro: liftState.domintros)
+termination liftState using All_liftState_dom by auto
+
+named_theorems liftState_simp
+
+lemma liftState_bind[liftState_simp]:
+  "liftState r (bind m f) = bindS (liftState r m) (liftState r \<circ> f)"
+  by (induction m f rule: bind.induct) auto
+
+lemma liftState_return[liftState_simp]: "liftState r (return a) = returnS a" by (auto simp: return_def)
+
+lemma Value_liftState_Run:
+  assumes "(Value a, s') \<in> liftState r m s"
+  obtains t where "Run m t a"
+  by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>;
+      auto simp add: failS_def throwS_def returnS_def simp del: read_regvalS.simps;
+      blast elim: Value_bindS_elim)
+
+lemmas liftState_if_distrib[liftState_simp] = if_distrib[where f = "liftState ra" for ra]
+
+lemma Value_bindS_iff:
+  "(Value b, s'') \<in> bindS m f s \<longleftrightarrow> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Value b, s'') \<in> f a s')"
+  by (auto elim!: bindS_cases intro: bindS_intros)
+
+lemma Ex_bindS_iff:
+  "(Ex e, s'') \<in> bindS m f s \<longleftrightarrow> (Ex e, s'') \<in> m s \<or> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Ex e, s'') \<in> f a s')"
+  by (auto elim!: bindS_cases intro: bindS_intros)
+
+lemma liftState_throw[liftState_simp]: "liftState r (throw e) = throwS e"
+  by (auto simp: throw_def)
+lemma liftState_assert[liftState_simp]: "liftState r (assert_exp c msg) = assert_expS c msg"
+  by (auto simp: assert_exp_def assert_expS_def)
+lemma liftState_exit[liftState_simp]: "liftState r (exit0 ()) = exitS ()"
+  by (auto simp: exit0_def exitS_def)
+lemma liftState_exclResult[liftState_simp]: "liftState r (excl_result ()) = excl_resultS ()"
+  by (auto simp: excl_result_def liftState_simp)
+lemma liftState_barrier[liftState_simp]: "liftState r (barrier bk) = returnS ()"
+  by (auto simp: barrier_def)
+lemma liftState_footprint[liftState_simp]: "liftState r (footprint ()) = returnS ()"
+  by (auto simp: footprint_def)
+lemma liftState_undefined[liftState_simp]: "liftState r (undefined_bool ()) = undefined_boolS ()"
+  by (auto simp: undefined_bool_def liftState_simp)
+lemma liftState_maybe_fail[liftState_simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x"
+  by (auto simp: maybe_fail_def maybe_failS_def liftState_simp split: option.splits)
+lemma liftState_and_boolM[liftState_simp]:
+  "liftState r (and_boolM x y) = and_boolS (liftState r x) (liftState r y)"
+  by (auto simp: and_boolM_def and_boolS_def liftState_simp cong: bindS_cong if_cong)
+lemma liftState_or_boolM[liftState_simp]:
+  "liftState r (or_boolM x y) = or_boolS (liftState r x) (liftState r y)"
+  by (auto simp: or_boolM_def or_boolS_def liftState_simp cong: bindS_cong if_cong)
+
+lemma liftState_try_catch[liftState_simp]:
+  "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \<circ> h)"
+  by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw)
+
+lemma liftState_early_return[liftState_simp]:
+  "liftState r (early_return x) = early_returnS x"
+  by (auto simp: early_return_def early_returnS_def liftState_simp)
+
+lemma liftState_catch_early_return[liftState_simp]:
+  "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)"
+  by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib liftState_simp cong: sum.case_cong)
+
+lemma liftState_liftR[liftState_simp]:
+  "liftState r (liftR m) = liftRS (liftState r m)"
+  by (auto simp: liftR_def liftRS_def liftState_simp)
+
+lemma liftState_try_catchR[liftState_simp]:
+  "liftState r (try_catchR m h) = try_catchRS (liftState r m) (liftState r \<circ> h)"
+  by (auto simp: try_catchR_def try_catchRS_def sum.case_distrib liftState_simp cong: sum.case_cong)
+
+lemma liftState_bool_of_bitU_nondet[liftState_simp]:
+  "liftState r (bool_of_bitU_nondet b) = bool_of_bitU_nondetS b"
+  by (cases b; auto simp: bool_of_bitU_nondet_def bool_of_bitU_nondetS_def liftState_simp)
+
+lemma liftState_read_mem_BC:
+  assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a"
+  shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz"
+  using assms
+  by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def liftState_simp split: option.splits)
+
+lemma liftState_read_mem[liftState_simp]:
+  "\<And>a. liftState r (read_mem BC_mword BC_mword rk a sz) = read_memS BC_mword BC_mword rk a sz"
+  "\<And>a. liftState r (read_mem BC_bitU_list BC_bitU_list rk a sz) = read_memS BC_bitU_list BC_bitU_list rk a sz"
+  by (auto simp: liftState_read_mem_BC)
+
+lemma liftState_write_mem_ea_BC:
+  assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a"
+  shows "liftState r (write_mem_ea BCa rk a sz) = write_mem_eaS BCa rk a (nat sz)"
+  using assms by (auto simp: write_mem_ea_def write_mem_eaS_def)
+
+lemma liftState_write_mem_ea[liftState_simp]:
+  "\<And>a. liftState r (write_mem_ea BC_mword rk a sz) = write_mem_eaS BC_mword rk a (nat sz)"
+  "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)"
+  by (auto simp: liftState_write_mem_ea_BC)
+
+lemma liftState_write_mem_val[liftState_simp]:
+  "liftState r (write_mem_val BC v) = write_mem_valS BC v"
+  by (auto simp: write_mem_val_def write_mem_valS_def liftState_simp split: option.splits)
+
+lemma liftState_read_reg_readS:
+  assumes "\<And>s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)"
+  shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \<circ> regstate)"
+proof
+  fix s :: "'a sequential_state"
+  obtain rv v where "get_regval' (name reg) (regstate s) = Some rv"
+    and "of_regval reg rv \<equiv> Some v" and "read_from reg (regstate s) = v"
+    using assms unfolding bind_eq_Some_conv by blast
+  then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \<circ> regstate) s"
+    by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def)
+qed
+
+lemma liftState_write_reg_updateS:
+  assumes "\<And>s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)"
+  shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))"
+  using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS)
+
+lemma liftState_iter_aux[liftState_simp]:
+  shows "liftState r (iter_aux i f xs) = iterS_aux i (\<lambda>i x. liftState r (f i x)) xs"
+  by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct)
+     (auto simp: liftState_simp cong: bindS_cong)
+
+lemma liftState_iteri[liftState_simp]:
+  "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs"
+  by (auto simp: iteri_def iteriS_def liftState_simp)
+
+lemma liftState_iter[liftState_simp]:
+  "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs"
+  by (auto simp: iter_def iterS_def liftState_simp)
+
+lemma liftState_foreachM[liftState_simp]:
+  "liftState r (foreachM xs vars body) = foreachS xs vars (\<lambda>x vars. liftState r (body x vars))"
+  by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct)
+     (auto simp: liftState_simp cong: bindS_cong)
+
+lemma liftState_bools_of_bits_nondet[liftState_simp]:
+  "liftState r (bools_of_bits_nondet bs) = bools_of_bits_nondetS bs"
+  unfolding bools_of_bits_nondet_def bools_of_bits_nondetS_def
+  by (auto simp: liftState_simp comp_def)
+
+lemma liftState_internal_pick[liftState_simp]:
+  "liftState r (internal_pick xs) = internal_pickS xs"
+  by (auto simp: internal_pick_def internal_pickS_def liftState_simp comp_def
+                 option.case_distrib[where h = "liftState r"]
+           simp del: repeat.simps
+           cong: option.case_cong)
+
+lemma liftRS_returnS[simp]: "liftRS (returnS x) = returnS x"
+  by (auto simp: liftRS_def)
+
+lemma liftRS_bindS:
+  fixes m :: "('regs, 'a, 'e) monadS" and f :: "'a \<Rightarrow> ('regs, 'b, 'e) monadS"
+  shows "(liftRS (bindS m f) :: ('regs, 'b, 'r, 'e) monadRS) = bindS (liftRS m) (liftRS \<circ> f)"
+proof (intro ext set_eqI iffI)
+  fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state"
+  assume lhs: "rs' \<in> liftRS (bindS m f) s"
+  then show "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s"
+    by (cases rs')
+       (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases
+                  intro: bindS_intros try_catchS_intros)
+next
+  fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state"
+  assume "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s"
+  then show "rs' \<in> liftRS (bindS m f) s"
+    by (cases rs')
+       (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases
+                  intro: bindS_intros try_catchS_intros)
+qed
+
+lemma liftRS_assert_expS_True[simp]: "liftRS (assert_expS True msg) = returnS ()"
+  by (auto simp: liftRS_def assert_expS_def)
+
+lemma untilM_domI:
+  fixes V :: "'vars \<Rightarrow> nat"
+  assumes "Inv vars"
+    and "\<And>vars t vars' t'. \<lbrakk>Inv vars; Run (body vars) t vars'; Run (cond vars') t' False\<rbrakk> \<Longrightarrow> V vars' < V vars \<and> Inv vars'"
+  shows "untilM_dom (vars, cond, body)"
+  using assms
+  by (induction vars rule: measure_induct_rule[where f = V])
+     (auto intro: untilM.domintros)
+
+lemma untilM_dom_untilS_dom:
+  assumes "untilM_dom (vars, cond, body)"
+  shows "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+  using assms
+  by (induction vars cond body arbitrary: s rule: untilM.pinduct)
+     (rule untilS.domintros, auto elim!: Value_liftState_Run)
+
+lemma measure2_induct:
+  fixes f :: "'a \<Rightarrow> 'b \<Rightarrow> nat"
+  assumes "\<And>x1 y1. (\<And>x2 y2. f x2 y2 < f x1 y1 \<Longrightarrow> P x2 y2) \<Longrightarrow> P x1 y1"
+  shows "P x y"
+proof -
+  have "P (fst x) (snd x)" for x
+    by (induction x rule: measure_induct_rule[where f = "\<lambda>x. f (fst x) (snd x)"]) (auto intro: assms)
+  then show ?thesis by auto
+qed
+
+lemma untilS_domI:
+  fixes V :: "'vars \<Rightarrow> 'regs sequential_state \<Rightarrow> nat"
+  assumes "Inv vars s"
+    and "\<And>vars s vars' s' s''.
+           \<lbrakk>Inv vars s; (Value vars', s') \<in> body vars s; (Value False, s'') \<in> cond vars' s'\<rbrakk>
+            \<Longrightarrow> V vars' s'' < V vars s \<and> Inv vars' s''"
+  shows "untilS_dom (vars, cond, body, s)"
+  using assms
+  by (induction vars s rule: measure2_induct[where f = V])
+     (auto intro: untilS.domintros)
+
+lemma whileS_dom_step:
+  assumes "whileS_dom (vars, cond, body, s)"
+    and "(Value True, s') \<in> cond vars s"
+    and "(Value vars', s'') \<in> body vars s'"
+  shows "whileS_dom (vars', cond, body, s'')"
+  by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>)
+     (auto intro: whileS.domintros)
+
+lemma whileM_dom_step:
+  assumes "whileM_dom (vars, cond, body)"
+    and "Run (cond vars) t True"
+    and "Run (body vars) t' vars'"
+  shows "whileM_dom (vars', cond, body)"
+  by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>)
+     (auto intro: whileM.domintros)
+
+lemma whileM_dom_ex_step:
+  assumes "whileM_dom (vars, cond, body)"
+    and "\<exists>t. Run (cond vars) t True"
+    and "\<exists>t'. Run (body vars) t' vars'"
+  shows "whileM_dom (vars', cond, body)"
+  using assms by (blast intro: whileM_dom_step)
+
+lemmas whileS_pinduct = whileS.pinduct[case_names Step]
+
+lemma liftState_whileM:
+  assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+    and "whileM_dom (vars, cond, body)"
+  shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>)
+  case Step: (1 vars s)
+  note domS = Step(1) and IH = Step(2) and domM = Step(3)
+  show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind
+  proof (intro bindS_ext_cong, goal_cases cond while)
+    case (while a s')
+    have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' =
+          bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'"
+      if "a"
+    proof (intro bindS_ext_cong, goal_cases body while')
+      case (while' vars' s'')
+      have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM])
+        show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run)
+        show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run)
+      qed
+      then show ?case using while while' that IH by auto
+    qed auto
+    then show ?case by (auto simp: liftState_simp)
+  qed auto
+qed
+
+
+lemma untilM_dom_step:
+  assumes "untilM_dom (vars, cond, body)"
+    and "Run (body vars) t vars'"
+    and "Run (cond vars') t' False"
+  shows "untilM_dom (vars', cond, body)"
+  by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>)
+     (auto intro: untilM.domintros)
+
+lemma untilM_dom_ex_step:
+  assumes "untilM_dom (vars, cond, body)"
+    and "\<exists>t. Run (body vars) t vars'"
+    and "\<exists>t'. Run (cond vars') t' False"
+  shows "untilM_dom (vars', cond, body)"
+  using assms by (blast intro: untilM_dom_step)
+
+lemma liftState_untilM:
+  assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+    and "untilM_dom (vars, cond, body)"
+  shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>)
+  case Step: (1 vars s)
+  note domS = Step(1) and IH = Step(2) and domM = Step(3)
+  show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind
+  proof (intro bindS_ext_cong, goal_cases body k)
+    case (k vars' s')
+    show ?case unfolding comp_def liftState_bind
+    proof (intro bindS_ext_cong, goal_cases cond until)
+      case (until a s'')
+      have "untilM_dom (vars', cond, body)" if "\<not>a"
+      proof (rule untilM_dom_ex_step[OF domM])
+        show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run)
+        show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run)
+      qed
+      then show ?case using k until IH by (auto simp: comp_def liftState_simp)
+    qed auto
+  qed auto
+qed
+
+(* Simplification rules for monadic Boolean connectives *)
+
+lemma if_return_return[simp]: "(if a then return True else return False) = return a" by auto
+
+lemma and_boolM_simps[simp]:
+  "and_boolM (return b) (return c) = return (b \<and> c)"
+  "and_boolM x (return True) = x"
+  "and_boolM x (return False) = x \<bind> (\<lambda>_. return False)"
+  "\<And>x y z. and_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. and_boolM (y r) z))"
+  by (auto simp: and_boolM_def)
+
+lemma and_boolM_return_if:
+  "and_boolM (return b) y = (if b then y else return False)"
+  by (auto simp: and_boolM_def)
+
+lemma and_boolM_return_return_and[simp]: "and_boolM (return l) (return r) = return (l \<and> r)"
+  by (auto simp: and_boolM_def)
+
+lemmas and_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolM x y" for y]
+
+lemma or_boolM_simps[simp]:
+  "or_boolM (return b) (return c) = return (b \<or> c)"
+  "or_boolM x (return True) = x \<bind> (\<lambda>_. return True)"
+  "or_boolM x (return False) = x"
+  "\<And>x y z. or_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. or_boolM (y r) z))"
+  by (auto simp: or_boolM_def)
+
+lemma or_boolM_return_if:
+  "or_boolM (return b) y = (if b then return True else y)"
+  by (auto simp: or_boolM_def)
+
+lemma or_boolM_return_return_or[simp]: "or_boolM (return l) (return r) = return (l \<or> r)"
+  by (auto simp: or_boolM_def)
+
+lemmas or_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolM x y" for y]
+
+lemma if_returnS_returnS[simp]: "(if a then returnS True else returnS False) = returnS a" by auto
+
+lemma and_boolS_simps[simp]:
+  "and_boolS (returnS b) (returnS c) = returnS (b \<and> c)"
+  "and_boolS x (returnS True) = x"
+  "and_boolS x (returnS False) = bindS x (\<lambda>_. returnS False)"
+  "\<And>x y z. and_boolS (bindS x y) z = (bindS x (\<lambda>r. and_boolS (y r) z))"
+  by (auto simp: and_boolS_def)
+
+lemma and_boolS_returnS_if:
+  "and_boolS (returnS b) y = (if b then y else returnS False)"
+  by (auto simp: and_boolS_def)
+
+lemmas and_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolS x y" for y]
+
+lemma and_boolS_returnS_True[simp]: "and_boolS (returnS True) c = c"
+  by (auto simp: and_boolS_def)
+
+lemma or_boolS_simps[simp]:
+  "or_boolS (returnS b) (returnS c) = returnS (b \<or> c)"
+  "or_boolS (returnS False) m = m"
+  "or_boolS x (returnS True) = bindS x (\<lambda>_. returnS True)"
+  "or_boolS x (returnS False) = x"
+  "\<And>x y z. or_boolS (bindS x y) z = (bindS x (\<lambda>r. or_boolS (y r) z))"
+  by (auto simp: or_boolS_def)
+
+lemma or_boolS_returnS_if:
+  "or_boolS (returnS b) y = (if b then returnS True else y)"
+  by (auto simp: or_boolS_def)
+
+lemmas or_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolS x y" for y]
+
+lemma Run_or_boolM_E:
+  assumes "Run (or_boolM l r) t a"
+  obtains "Run l t True" and "a"
+  | tl tr where "Run l tl False" and "Run r tr a" and "t = tl @ tr"
+  using assms by (auto simp: or_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma Run_and_boolM_E:
+  assumes "Run (and_boolM l r) t a"
+  obtains "Run l t False" and "\<not>a"
+  | tl tr where "Run l tl True" and "Run r tr a" and "t = tl @ tr"
+  using assms by (auto simp: and_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma maybe_failS_Some[simp]: "maybe_failS msg (Some v) = returnS v"
+  by (auto simp: maybe_failS_def)
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_state_lifting.thy b/snapshots/isabelle/lib/sail/Sail2_state_lifting.thy
new file mode 100644
index 00000000..957a7940
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_state_lifting.thy
@@ -0,0 +1,52 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_state_lifting.lem.\<close>
+
+theory "Sail2_state_lifting" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Sail2_values" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+	 "Sail2_state_monad" 
+	 "Sail2_state_monad_lemmas" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Sail2_values*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+(*open import Sail2_state_monad*)
+(*open import {isabelle} `Sail2_state_monad_lemmas`*)
+
+(* State monad wrapper around prompt monad *)
+
+(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*)
+function (sequential,domintros)  liftState  :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval,'a,'e)monad \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " liftState ra (Done a) = ( returnS a )"
+|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) rk a sz) (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Read_tag t k) = ( bindS (read_tagS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) t)             (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Write_memv a k) = ( bindS (write_mem_bytesS a)      (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Write_tag a t k) = ( bindS (write_tagS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) a t)          (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r)       (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Excl_res k) = ( bindS (excl_resultS () )         (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Undefined k) = ( bindS (undefined_boolS () )      (\<lambda> v .  liftState ra (k v)))"
+|" liftState ra (Write_ea wk a sz k) = ( seqS (write_mem_eaS 
+  (instance_Sail2_values_Bitvector_list_dict
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) wk a sz)    (liftState ra k))"
+|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v)     (liftState ra k))"
+|" liftState ra (Footprint k) = ( liftState ra k )"
+|" liftState ra (Barrier _ k) = ( liftState ra k )"
+|" liftState ra (Print _ k) = ( liftState ra k )"
+|" liftState ra (Fail descr) = ( failS descr )"
+|" liftState ra (Exception e) = ( throwS e )" 
+by pat_completeness auto
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_state_monad.thy b/snapshots/isabelle/lib/sail/Sail2_state_monad.thy
new file mode 100644
index 00000000..e1bf0048
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_state_monad.thy
@@ -0,0 +1,363 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_state_monad.lem.\<close>
+
+theory "Sail2_state_monad" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+
+(* 'a is result type *)
+
+type_synonym memstate =" (int, memory_byte) Map.map "
+type_synonym tagstate =" (int, bitU) Map.map "
+(* type regstate = map string (vector bitU) *)
+
+record 'regs sequential_state =
+  
+ regstate ::" 'regs " 
+
+     memstate ::" memstate " 
+
+     tagstate ::" tagstate " 
+
+     write_ea ::"  (write_kind * int * int)option " 
+
+     last_exclusive_operation_was_load ::" bool " 
+
+
+(*val init_state : forall 'regs. 'regs -> sequential_state 'regs*)
+definition init_state  :: " 'regs \<Rightarrow> 'regs sequential_state "  where 
+     " init_state regs = (
+  (| regstate = regs,
+     memstate = Map.empty,
+     tagstate = Map.empty,
+     write_ea = None,
+     last_exclusive_operation_was_load = False |) )"
+
+
+datatype 'e ex =
+    Failure " string "
+  | Throw " 'e "
+
+datatype( 'a, 'e) result =
+    Value " 'a "
+  | Ex " ( 'e ex)"
+
+(* State, nondeterminism and exception monad with result value type 'a
+   and exception type 'e. *)
+type_synonym( 'regs, 'a, 'e) monadS =" 'regs sequential_state \<Rightarrow> ( ('a, 'e)result * 'regs sequential_state) set "
+
+(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*)
+definition returnS  :: " 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " returnS a s = ( {(Value a,s)})"
+
+
+(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*)
+definition bindS  :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow>('a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set "  where 
+     " bindS m f (s :: 'regs sequential_state) = (
+  \<Union> (Set.image (\<lambda>x .  
+  (case  x of   (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s)))"
+
+
+(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*)
+definition seqS  :: "('regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set)\<Rightarrow>('regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set "  where 
+     " seqS m n = ( bindS m ( \<lambda>x .  
+  (case  x of (_ :: unit) => n )))"
+
+
+(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*)
+definition chooseS  :: " 'a set \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " chooseS xs s = ( Set.image (\<lambda> x .  (Value x, s)) xs )"
+
+
+(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*)
+definition readS  :: "('regs sequential_state \<Rightarrow> 'a)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " readS f = ( (\<lambda> s .  returnS (f s) s))"
+
+
+(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*)
+definition updateS  :: "('regs sequential_state \<Rightarrow> 'regs sequential_state)\<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set "  where 
+     " updateS f = ( (\<lambda> s .  returnS ()  (f s)))"
+
+
+(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*)
+definition failS  :: " string \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " failS msg s = ( {(Ex (Failure msg), s)})"
+
+
+(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*)
+definition undefined_boolS  :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set "  where 
+     " undefined_boolS _ = ( chooseS {False, True})"
+
+
+(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*)
+definition exitS  :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " exitS _ = ( failS (''exit''))"
+
+
+(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*)
+definition throwS  :: " 'e \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " throwS e s = ( {(Ex (Throw e), s)})"
+
+
+(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) ->  monadS 'regs 'a 'e2*)
+definition try_catchS  :: "('regs sequential_state \<Rightarrow>(('a,'e1)result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set "  where 
+     " try_catchS m h s = (
+  \<Union> (Set.image (\<lambda>x .  
+  (case  x of
+        (Value a, s') => returnS a s'
+    | (Ex (Throw e), s') => h e s'
+    | (Ex (Failure msg), s') => {(Ex (Failure msg), s')}
+  )) (m s)))"
+
+
+(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*)
+definition assert_expS  :: " bool \<Rightarrow> string \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set "  where 
+     " assert_expS exp msg = ( if exp then returnS ()  else failS msg )"
+
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is either 'r 'e, where Right e
+   represents a proper exception and Left r an early return of value r. *)
+type_synonym( 'regs, 'a, 'r, 'e) monadRS =" ('regs, 'a, ( ('r, 'e)sum)) monadS "
+
+(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*)
+definition early_returnS  :: " 'r \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set "  where 
+     " early_returnS r = ( throwS (Inl r))"
+
+
+(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*)
+definition catch_early_returnS  :: "('regs sequential_state \<Rightarrow>(('a,(('a,'e)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " catch_early_returnS m = (
+  try_catchS m
+    (\<lambda>x .  (case  x of   Inl a => returnS a | Inr e => throwS e )))"
+
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*)
+definition liftRS  :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set "  where 
+     " liftRS m = ( try_catchS m (\<lambda> e .  throwS (Inr e)))"
+
+
+(* Catch exceptions in the presence of early returns *)
+(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) ->  monadRS 'regs 'a 'r 'e2*)
+definition try_catchRS  :: "('regs sequential_state \<Rightarrow>(('a,(('r,'e1)sum))result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set "  where 
+     " try_catchRS m h = (
+  try_catchS m
+    (\<lambda>x .  (case  x of   Inl r => throwS (Inl r) | Inr e => h e )))"
+
+
+(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*)
+definition maybe_failS  :: " string \<Rightarrow> 'a option \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " maybe_failS msg = ( \<lambda>x .  
+  (case  x of   Some a => returnS a | None => failS msg ) )"
+
+
+(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*)
+definition read_tagS  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regs,(bitU),'e)monadS "  where 
+     " read_tagS dict_Sail2_values_Bitvector_a addr = ( bindS
+  (maybe_failS (''unsigned'') (
+  (unsigned_method   dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . 
+  readS (\<lambda> s .  case_option B0 id ((tagstate   s) addr))))"
+
+
+(* Read bytes from memory and return in little endian order *)
+(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*)
+definition read_mem_bytesS  :: " 'a Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(((bitU)list)list),'e)monadS "  where 
+     " read_mem_bytesS dict_Sail2_values_Bitvector_a read_kind addr sz = ( bindS
+  (maybe_failS (''unsigned'') (
+  (unsigned_method   dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . 
+  (let sz = (int sz) in
+  (let addrs = (index_list addr ((addr+sz)-( 1 :: int))(( 1 :: int))) in  
+  (let read_byte = (\<lambda> s addr .  (memstate   s) addr) in
+  bindS (readS (\<lambda> s .  just_list (List.map (read_byte s) addrs)))
+    (\<lambda>x .  (case  x of
+                         Some mem_val => seqS
+                                           (updateS
+                                              (\<lambda> s . 
+                                               if read_is_exclusive read_kind
+                                               then
+                                                 ( s (| last_exclusive_operation_was_load := True |))
+                                               else s)) (returnS mem_val)
+                     | None => failS (''read_memS'')
+                   )))))))"
+
+
+(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*)
+definition read_memS  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regs,'b,'e)monadS "  where 
+     " read_memS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz = ( bindS
+  (read_mem_bytesS dict_Sail2_values_Bitvector_a rk a (nat_of_int sz)) (\<lambda> bytes . 
+  maybe_failS (''bits_of_mem_bytes'') (
+  (of_bits_method   dict_Sail2_values_Bitvector_b) (bits_of_mem_bytes bytes))))"
+
+
+(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*)
+definition excl_resultS  :: " unit \<Rightarrow>('regs,(bool),'e)monadS "  where 
+     " excl_resultS _ = ( bindS
+  (readS (\<lambda> s . (last_exclusive_operation_was_load   s))) (\<lambda> excl_load .  seqS
+  (updateS (\<lambda> s .  ( s (| last_exclusive_operation_was_load := False |))))
+  (chooseS (if excl_load then {False, True} else {False}))))"
+
+
+(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*)
+definition write_mem_eaS  :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(unit),'e)monadS "  where 
+     " write_mem_eaS dict_Sail2_values_Bitvector_a write_kind addr sz = ( bindS
+  (maybe_failS (''unsigned'') (
+  (unsigned_method   dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . 
+  (let sz = (int sz) in
+  updateS (\<lambda> s .  ( s (| write_ea := (Some (write_kind, addr, sz)) |))))))"
+
+
+(* Write little-endian list of bytes to previously announced address *)
+(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*)
+definition write_mem_bytesS  :: "((bitU)list)list \<Rightarrow>('regs,(bool),'e)monadS "  where 
+     " write_mem_bytesS v = ( bindS
+  (readS (\<lambda> s . (write_ea   s))) (\<lambda>x .  
+  (case  x of
+        None => failS (''write ea has not been announced yet'')
+    | Some (_, addr, sz) =>
+  (let addrs = (index_list addr ((addr + sz) - ( 1 :: int)) (( 1 :: int))) in
+  (*let v = external_mem_value (bits_of v) in*)
+  (let a_v = (List.zip addrs v) in
+  (let write_byte = (\<lambda>mem p .  (case  (mem ,p ) of
+                                           ( mem , (addr, v) ) => map_update
+                                                                    addr 
+                                                                  v mem
+                                       )) in
+  seqS
+    (updateS
+       (\<lambda> s . 
+        ( s (| memstate := (List.foldl write_byte (memstate   s) a_v) |))))
+    (returnS True))))
+  )))"
+
+
+(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*)
+definition write_mem_valS  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set "  where 
+     " write_mem_valS dict_Sail2_values_Bitvector_a v = ( (case  mem_bytes_of_bits 
+  dict_Sail2_values_Bitvector_a v of
+    Some v => write_mem_bytesS v
+  | None => failS (''write_mem_val'')
+))"
+
+
+(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*)
+definition write_tagS  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('regs,(bool),'e)monadS "  where 
+     " write_tagS dict_Sail2_values_Bitvector_a addr t = ( bindS
+   (maybe_failS (''unsigned'') (
+  (unsigned_method   dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr .  seqS
+   (updateS (\<lambda> s .  ( s (| tagstate := (map_update addr t(tagstate   s)) |))))
+   (returnS True)))"
+
+
+(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*)
+definition read_regS  :: "('regs,'rv,'a)register_ref \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
+     " read_regS reg = ( readS (\<lambda> s . (read_from   reg)(regstate   s)))"
+
+
+(* TODO
+let read_reg_range reg i j state =
+  let v = slice (get_reg state (name_of_reg reg)) i j in
+  [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+  let v = access (get_reg state (name_of_reg reg)) i in
+  [(Value v,state)]
+let read_reg_field reg regfield =
+  let (i,j) = register_field_indices reg regfield in
+  read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+  let (i,_) = register_field_indices reg regfield in
+  read_reg_bit reg i *)
+
+(*val read_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*)
+fun read_regvalS  :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow>('regs,'rv,'e)monadS "  where 
+     " read_regvalS (read, _) reg = ( bindS
+  (readS (\<lambda> s .  read reg(regstate   s))) (\<lambda>x .  
+  (case  x of
+        Some v => returnS v
+    | None => failS ((''read_regvalS '') @ reg)
+  )))"
+
+
+(*val write_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*)
+fun write_regvalS  :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow> 'rv \<Rightarrow>('regs,(unit),'e)monadS "  where 
+     " write_regvalS (_, write1) reg v = ( bindS
+  (readS (\<lambda> s .  write1 reg v(regstate   s))) (\<lambda>x .  
+  (case  x of
+        Some rs' => updateS (\<lambda> s .  ( s (| regstate := rs' |)))
+    | None => failS ((''write_regvalS '') @ reg)
+  )))"
+
+
+(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*)
+definition write_regS  :: "('regs,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set "  where 
+     " write_regS reg v = (
+  updateS (\<lambda> s .  ( s (| regstate := ((write_to   reg) v(regstate   s)) |))))"
+
+
+(* TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+  let current_value = get_reg state reg in
+  let new_value = f current_value v in
+  [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
+
+(* TODO Add Show typeclass for value and exception type *)
+(*val show_result : forall 'a 'e. result 'a 'e -> string*)
+definition show_result  :: "('a,'e)result \<Rightarrow> string "  where 
+     " show_result = ( \<lambda>x .  
+  (case  x of
+        Value _ => (''Value ()'')
+    | Ex (Failure msg) => (''Failure '') @ msg
+    | Ex (Throw _) => (''Throw'')
+  ) )"
+
+
+(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*)
+definition prerr_results  :: "(('a,'e)result*'s)set \<Rightarrow> unit "  where 
+     " prerr_results rs = (
+  (let _ = (Set.image ( \<lambda>x .  
+  (case  x of (r, _) => (let _ = (prerr_endline (show_result r)) in () ) )) rs) in
+  () ))"
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy
new file mode 100644
index 00000000..3a286c10
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy
@@ -0,0 +1,238 @@
+theory Sail2_state_monad_lemmas
+  imports
+    Sail2_state_monad
+    Sail2_values_lemmas
+begin
+
+(*context
+  notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp]
+begin*)
+
+notation bindS (infixr "\<bind>\<^sub>S" 54)
+notation seqS (infixr "\<then>\<^sub>S" 54)
+
+lemma bindS_ext_cong[fundef_cong]:
+  assumes m: "m1 s = m2 s"
+    and f: "\<And>a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
+  shows "bindS m1 f1 s = bindS m2 f2 s"
+  using assms unfolding bindS_def by (auto split: result.splits)
+
+lemma bindS_cong[fundef_cong]:
+  assumes m: "m1 = m2"
+    and f: "\<And>s a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
+  shows "bindS m1 f1 = bindS m2 f2"
+  using assms by (intro ext bindS_ext_cong; blast)
+
+lemma bindS_returnS_left[simp]: "bindS (returnS x) f = f x"
+  by (auto simp add: bindS_def returnS_def)
+
+lemma bindS_returnS_right[simp]: "bindS m returnS = (m :: ('regs, 'a, 'e) monadS)"
+  by (intro ext) (auto simp: bindS_def returnS_def split: result.splits)
+
+lemma bindS_readS: "bindS (readS f) m = (\<lambda>s. m (f s) s)"
+  by (auto simp: bindS_def readS_def returnS_def)
+
+lemma bindS_updateS: "bindS (updateS f) m = (\<lambda>s. m () (f s))"
+  by (auto simp: bindS_def updateS_def returnS_def)
+
+lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()"
+  by (auto simp: assert_expS_def)
+
+lemma bindS_chooseS_returnS[simp]: "bindS (chooseS xs) (\<lambda>x. returnS (f x)) = chooseS (f ` xs)"
+  by (intro ext) (auto simp: bindS_def chooseS_def returnS_def)
+
+
+lemma result_cases:
+  fixes r :: "('a, 'e) result"
+  obtains (Value) a where "r = Value a"
+  | (Throw) e where "r = Ex (Throw e)"
+  | (Failure) msg where "r = Ex (Failure msg)"
+proof (cases r)
+  case (Ex ex) then show ?thesis by (cases ex; auto intro: that)
+qed
+
+lemma result_state_cases:
+  fixes rs :: "('a, 'e) result \<times> 's"
+  obtains (Value) a s where "rs = (Value a, s)"
+  | (Throw) e s where "rs = (Ex (Throw e), s)"
+  | (Failure) msg s where "rs = (Ex (Failure msg), s)"
+proof -
+  obtain r s where rs: "rs = (r, s)" by (cases rs)
+  then show thesis by (cases r rule: result_cases) (auto intro: that)
+qed
+
+lemma monadS_ext_eqI:
+  fixes m m' :: "('regs, 'a, 'e) monadS"
+  assumes "\<And>a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
+    and "\<And>e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
+    and "\<And>msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
+  shows "m s = m' s"
+proof (intro set_eqI)
+  fix x
+  show "x \<in> m s \<longleftrightarrow> x \<in> m' s" using assms by (cases x rule: result_state_cases) auto
+qed
+
+lemma monadS_eqI:
+  fixes m m' :: "('regs, 'a, 'e) monadS"
+  assumes "\<And>s a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
+    and "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
+    and "\<And>s msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
+  shows "m = m'"
+  using assms by (intro ext monadS_ext_eqI)
+
+lemma bindS_cases:
+  assumes "(r, s') \<in> bindS m f s"
+  obtains (Value) a a' s'' where "r = Value a" and "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''"
+  | (Ex_Left) e where "r = Ex e" and "(Ex e, s') \<in> m s"
+  | (Ex_Right) e a s'' where "r = Ex e" and "(Value a, s'') \<in> m s" and "(Ex e, s') \<in> f a s''"
+  using assms by (cases r; auto simp: bindS_def split: result.splits)
+
+lemma bindS_intros:
+  "\<And>m f s a s' a' s''. (Value a', s'') \<in> m s \<Longrightarrow> (Value a, s') \<in> f a' s'' \<Longrightarrow> (Value a, s') \<in> bindS m f s"
+  "\<And>m f s e s'. (Ex e, s') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s"
+  "\<And>m f s e s' a s''. (Ex e, s') \<in> f a s'' \<Longrightarrow> (Value a, s'') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s"
+  by (auto simp: bindS_def intro: bexI[rotated])
+
+lemma bindS_assoc[simp]: "bindS (bindS m f) g = bindS m (\<lambda>x. bindS (f x) g)"
+  by (auto elim!: bindS_cases intro: bindS_intros monadS_eqI)
+
+lemma bindS_failS[simp]: "bindS (failS msg) f = failS msg" by (auto simp: bindS_def failS_def)
+lemma bindS_throwS[simp]: "bindS (throwS e) f = throwS e" by (auto simp: bindS_def throwS_def)
+declare seqS_def[simp]
+
+lemma Value_bindS_elim:
+  assumes "(Value a, s') \<in> bindS m f s"
+  obtains s'' a' where "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''"
+  using assms by (auto elim: bindS_cases)
+
+lemma Ex_bindS_elim:
+  assumes "(Ex e, s') \<in> bindS m f s"
+  obtains (Left) "(Ex e, s') \<in> m s"
+  | (Right) s'' a' where "(Value a', s'') \<in> m s" and "(Ex e, s') \<in> f a' s''"
+  using assms by (auto elim: bindS_cases)
+
+lemma try_catchS_returnS[simp]: "try_catchS (returnS a) h = returnS a"
+  and try_catchS_failS[simp]: "try_catchS (failS msg) h = failS msg"
+  and try_catchS_throwS[simp]: "try_catchS (throwS e) h = h e"
+  by (auto simp: try_catchS_def returnS_def failS_def throwS_def)
+
+lemma try_catchS_cong[cong]:
+  assumes "\<And>s. m1 s = m2 s" and "\<And>e s. h1 e s = h2 e s"
+  shows "try_catchS m1 h1 = try_catchS m2 h2"
+  using assms by (intro arg_cong2[where f = try_catchS] ext) auto
+
+lemma try_catchS_cases:
+  assumes "(r, s') \<in> try_catchS m h s"
+  obtains (Value) a where "r = Value a" and "(Value a, s') \<in> m s"
+  | (Fail) msg where "r = Ex (Failure msg)" and "(Ex (Failure msg), s') \<in> m s"
+  | (h) e s'' where "(Ex (Throw e), s'') \<in> m s" and "(r, s') \<in> h e s''"
+  using assms
+  by (cases r rule: result_cases) (auto simp: try_catchS_def returnS_def split: result.splits ex.splits)
+
+lemma try_catchS_intros:
+  "\<And>m h s a s'. (Value a, s') \<in> m s \<Longrightarrow> (Value a, s') \<in> try_catchS m h s"
+  "\<And>m h s msg s'. (Ex (Failure msg), s') \<in> m s \<Longrightarrow> (Ex (Failure msg), s') \<in> try_catchS m h s"
+  "\<And>m h s e s'' r s'. (Ex (Throw e), s'') \<in> m s \<Longrightarrow> (r, s') \<in> h e s'' \<Longrightarrow> (r, s') \<in> try_catchS m h s"
+  by (auto simp: try_catchS_def returnS_def intro: bexI[rotated])
+
+lemma no_Ex_basic_builtins[simp]:
+  "\<And>s e s' a. (Ex e, s') \<in> returnS a s \<longleftrightarrow> False"
+  "\<And>s e s' f. (Ex e, s') \<in> readS f s \<longleftrightarrow> False"
+  "\<And>s e s' f. (Ex e, s') \<in> updateS f s \<longleftrightarrow> False"
+  "\<And>s e s' xs. (Ex e, s') \<in> chooseS xs s \<longleftrightarrow> False"
+  by (auto simp: readS_def updateS_def returnS_def chooseS_def)
+
+fun ignore_throw_aux :: "(('a, 'e1) result \<times> 's) \<Rightarrow> (('a, 'e2) result \<times> 's) set" where
+  "ignore_throw_aux (Value a, s') = {(Value a, s')}"
+| "ignore_throw_aux (Ex (Throw e), s') = {}"
+| "ignore_throw_aux (Ex (Failure msg), s') = {(Ex (Failure msg), s')}"
+definition "ignore_throw m s \<equiv> \<Union>(ignore_throw_aux ` m s)"
+
+lemma ignore_throw_cong:
+  assumes "\<And>s. m1 s = m2 s"
+  shows "ignore_throw m1 = ignore_throw m2"
+  using assms by (auto simp: ignore_throw_def)
+
+lemma ignore_throw_aux_member_simps[simp]:
+  "(Value a, s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Value a, s')"
+  "(Ex (Throw e), s') \<in> ignore_throw_aux ms \<longleftrightarrow> False"
+  "(Ex (Failure msg), s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Ex (Failure msg), s')"
+  by (cases ms rule: result_state_cases; auto)+
+
+lemma ignore_throw_member_simps[simp]:
+  "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s"
+  "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s"
+  "(Ex (Throw e), s') \<in> ignore_throw m s \<longleftrightarrow> False"
+  "(Ex (Failure msg), s') \<in> ignore_throw m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m s"
+  by (auto simp: ignore_throw_def)
+
+lemma ignore_throw_cases:
+  assumes no_throw: "ignore_throw m s = m s"
+    and r: "(r, s') \<in> m s"
+  obtains (Value) a where "r = Value a"
+  | (Failure) msg where "r = Ex (Failure msg)"
+  using r unfolding no_throw[symmetric]
+  by (cases r rule: result_cases) (auto simp: ignore_throw_def)
+
+lemma ignore_throw_bindS[simp]:
+  "ignore_throw (bindS m f) = bindS (ignore_throw m) (ignore_throw \<circ> f)"
+  by (intro monadS_eqI) (auto simp: ignore_throw_def elim!: bindS_cases intro: bindS_intros)
+
+lemma try_catchS_bindS_no_throw:
+  fixes m1 :: "('r, 'a, 'e1) monadS" and m2 :: "('r, 'a, 'e2) monadS"
+  assumes m1: "\<And>s. ignore_throw m1 s = m1 s"
+    and m2: "\<And>s. ignore_throw m1 s = m2 s"
+  shows "try_catchS (bindS m1 f) h = bindS m2 (\<lambda>a. try_catchS (f a) h)"
+proof
+  fix s
+  have "try_catchS (bindS m1 f) h s = bindS (ignore_throw m1) (\<lambda>a. try_catchS (f a) h) s"
+    by (intro monadS_ext_eqI;
+        auto elim!: bindS_cases try_catchS_cases elim: ignore_throw_cases[OF m1];
+        auto simp: ignore_throw_def intro: bindS_intros try_catchS_intros)
+  also have "\<dots> = bindS m2 (\<lambda>a. try_catchS (f a) h) s" using m2 by (intro bindS_ext_cong) auto
+  finally show "try_catchS (bindS m1 f) h s = bindS m2 (\<lambda>a. try_catchS (f a) h) s" .
+qed
+
+lemma no_throw_basic_builtins[simp]:
+  "ignore_throw (returnS a) = returnS a"
+  "\<And>f. ignore_throw (readS f) = readS f"
+  "\<And>f. ignore_throw (updateS f) = updateS f"
+  "ignore_throw (chooseS xs) = chooseS xs"
+  "ignore_throw (failS msg) = failS msg"
+  "ignore_throw (maybe_failS msg x) = maybe_failS msg x"
+  unfolding ignore_throw_def returnS_def chooseS_def maybe_failS_def failS_def readS_def updateS_def
+  by (intro ext; auto split: option.splits)+
+
+lemmas ignore_throw_option_case_distrib =
+  option.case_distrib[where h = "\<lambda>c. ignore_throw c s" and option = "c s" for c s]
+
+lemma no_throw_mem_builtins:
+  "\<And>BC rk a sz s. ignore_throw (read_mem_bytesS BC rk a sz) s = read_mem_bytesS BC rk a sz s"
+  "\<And>BC a s. ignore_throw (read_tagS BC a) s = read_tagS BC a s"
+  "\<And>BC wk a sz s. ignore_throw (write_mem_eaS BC wk a sz) s = write_mem_eaS BC wk a sz s"
+  "\<And>v s. ignore_throw (write_mem_bytesS v) s = write_mem_bytesS v s"
+  "\<And>BC v s. ignore_throw (write_mem_valS BC v) s = write_mem_valS BC v s"
+  "\<And>BC a t s. ignore_throw (write_tagS BC a t) s = write_tagS BC a t s"
+  "\<And>s. ignore_throw (excl_resultS ()) s = excl_resultS () s"
+  "\<And>s. ignore_throw (undefined_boolS ()) s = undefined_boolS () s"
+  unfolding read_mem_bytesS_def read_memS_def read_tagS_def write_mem_eaS_def
+  unfolding write_mem_valS_def write_mem_bytesS_def write_tagS_def
+  unfolding excl_resultS_def undefined_boolS_def
+  by (auto cong: bindS_cong bindS_ext_cong ignore_throw_cong option.case_cong
+           simp: option.case_distrib prod.case_distrib ignore_throw_option_case_distrib comp_def)
+
+lemma no_throw_read_memS: "ignore_throw (read_memS BCa BCb rk a sz) s = read_memS BCa BCb rk a sz s"
+  by (auto simp: read_memS_def no_throw_mem_builtins cong: bindS_ext_cong)
+
+lemma no_throw_read_regvalS: "ignore_throw (read_regvalS r reg_name) s = read_regvalS r reg_name s"
+  by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong)
+
+lemma no_throw_write_regvalS: "ignore_throw (write_regvalS r reg_name v) s = write_regvalS r reg_name v s"
+  by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong)
+
+lemmas no_throw_builtins[simp] =
+  no_throw_mem_builtins no_throw_read_regvalS no_throw_write_regvalS no_throw_read_memS
+
+(* end *)
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_string.thy b/snapshots/isabelle/lib/sail/Sail2_string.thy
new file mode 100644
index 00000000..fd2c1d04
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_string.thy
@@ -0,0 +1,215 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_string.lem.\<close>
+
+theory "Sail2_string" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives" 
+	 "Lem_list" 
+	 "Lem_list_extra" 
+	 "Lem_string" 
+	 "Lem_string_extra" 
+	 "Sail2_operators" 
+	 "Sail2_values" 
+
+begin 
+
+(*open import Pervasives*)
+(*open import List*)
+(*open import List_extra*)
+(*open import String*)
+(*open import String_extra*)
+
+(*open import Sail2_operators*)
+(*open import Sail2_values*)
+
+(*val string_sub : string -> ii -> ii -> string*)
+definition string_sub  :: " string \<Rightarrow> int \<Rightarrow> int \<Rightarrow> string "  where 
+     " string_sub str start len = (
+  (List.take (nat (abs ( len))) (List.drop (nat (abs ( start))) ( str))))"
+
+
+(*val string_startswith : string -> string -> bool*)
+definition string_startswith  :: " string \<Rightarrow> string \<Rightarrow> bool "  where 
+     " string_startswith str1 str2 = (
+  (let prefix = (string_sub str1(( 0 :: int)) (int (List.length str2))) in
+  (prefix = str2)))"
+
+
+(*val string_drop : string -> ii -> string*)
+definition string_drop  :: " string \<Rightarrow> int \<Rightarrow> string "  where 
+     " string_drop str n = (
+  (List.drop (nat (abs ( n))) ( str)))"
+
+
+(*val string_length : string -> ii*)
+definition string_length  :: " string \<Rightarrow> int "  where 
+     " string_length s = ( int (List.length s))"
+
+
+definition string_append  :: " string \<Rightarrow> string \<Rightarrow> string "  where 
+     " string_append = ( (op@))"
+
+
+(***********************************************
+ * Begin stuff that should be in Lem Num_extra *
+ ***********************************************)
+
+(*val maybeIntegerOfString : string -> maybe integer*)
+definition maybeIntegerOfString  :: " string \<Rightarrow>(int)option "  where 
+     " maybeIntegerOfString _ = ( None )"
+
+
+(***********************************************
+ * end stuff that should be in Lem Num_extra   *
+ ***********************************************)
+
+function (sequential,domintros)  maybe_int_of_prefix  :: " string \<Rightarrow>(int*int)option "  where 
+     " maybe_int_of_prefix s = ( 
+  if(s = ('''')) then None else
+    ((let len = (string_length s) in
+     (case  maybeIntegerOfString s of
+           Some n => Some (n, len)
+       | None => maybe_int_of_prefix
+                   (string_sub s (( 0 :: int)) (len - ( 1 :: int)))
+     ))) )" 
+by pat_completeness auto
+
+
+definition maybe_int_of_string  :: " string \<Rightarrow>(int)option "  where 
+     " maybe_int_of_string = ( maybeIntegerOfString )"
+
+
+(*val n_leading_spaces : string -> ii*)
+function (sequential,domintros)  n_leading_spaces  :: " string \<Rightarrow> int "  where 
+     " n_leading_spaces s = (
+  (let len = (string_length s) in
+  if len =( 0 :: int) then( 0 :: int) else
+    if len =( 1 :: int) then  
+  if(s = ('' '')) then ( 1 :: int) else ( 0 :: int)
+    else
+      (* match len with
+   *     (* | 0 -> 0 *)
+   * (* | 1 -> *) 
+   * | len -> *)
+           (* Isabelle generation for pattern matching on characters
+              is currently broken, so use an if-expression *)
+           if nth s(( 0 :: nat)) = (CHR '' '')
+           then( 1 :: int) + (n_leading_spaces (string_sub s(( 1 :: int)) (len -( 1 :: int))))
+           else( 0 :: int)))" 
+by pat_completeness auto
+
+  (* end *)
+
+definition opt_spc_matches_prefix  :: " string \<Rightarrow>(unit*int)option "  where 
+     " opt_spc_matches_prefix s = (
+  Some (() , n_leading_spaces s))"
+
+
+definition spc_matches_prefix  :: " string \<Rightarrow>(unit*int)option "  where 
+     " spc_matches_prefix s = (
+  (let n = (n_leading_spaces s) in
+  (* match n with *)
+(* | 0 -> Nothing *)
+  if n =( 0 :: int) then None else
+  (* | n -> *) Some (() , n)))"
+
+  (* end *)
+
+definition hex_bits_5_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_5_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 32 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 5 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+definition hex_bits_6_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_6_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 64 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 6 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+definition hex_bits_12_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_12_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 4096 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 12 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+definition hex_bits_13_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_13_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 8192 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 13 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+definition hex_bits_16_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_16_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 65536 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 16 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+
+definition hex_bits_20_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_20_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 1048576 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 20 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+definition hex_bits_21_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_21_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 2097152 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 21 :: int)) n, len))
+     else
+       None
+  ))"
+
+
+definition hex_bits_32_matches_prefix  :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option "  where 
+     " hex_bits_32_matches_prefix dict_Sail2_values_Bitvector_a s = (
+  (case  maybe_int_of_prefix s of
+    None => None
+  | Some (n, len) =>
+     if(( 0 :: int) \<le> n) \<and> (n <( 4294967296 :: int)) then
+       Some (((of_int_method   dict_Sail2_values_Bitvector_a)(( 2147483648 :: int)) n, len))
+     else
+       None
+  ))"
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_values.thy b/snapshots/isabelle/lib/sail/Sail2_values.thy
new file mode 100644
index 00000000..6278f8e3
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_values.thy
@@ -0,0 +1,1230 @@
+chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_values.lem.\<close>
+
+theory "Sail2_values" 
+
+imports 
+ 	 Main
+	 "Lem_pervasives_extra" 
+	 "Lem_machine_word" 
+
+begin 
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail_impl_base*)
+
+
+type_synonym ii =" int "
+type_synonym nn =" nat "
+
+(*val nat_of_int : integer -> nat*)
+definition nat_of_int  :: " int \<Rightarrow> nat "  where 
+     " nat_of_int i = ( if i <( 0 :: int) then( 0 :: nat) else nat (abs ( i)))"
+
+
+(*val pow : integer -> integer -> integer*)
+definition pow  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
+     " pow m n = ( m ^ (nat_of_int n))"
+
+
+definition pow2  :: " int \<Rightarrow> int "  where 
+     " pow2 n = ( pow(( 2 :: int)) n )"
+
+
+(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
+
+(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
+
+(*let add_int l r = integerAdd l r
+let add_signed l r = integerAdd l r
+let sub_int l r = integerMinus l r
+let mult_int l r = integerMult l r
+let div_int l r = integerDiv l r
+let div_nat l r = natDiv l r
+let power_int_nat l r = integerPow l r
+let power_int_int l r = integerPow l (nat_of_int r)
+let negate_int i = integerNegate i
+let min_int l r = integerMin l r
+let max_int l r = integerMax l r
+
+let add_real l r = realAdd l r
+let sub_real l r = realMinus l r
+let mult_real l r = realMult l r
+let div_real l r = realDiv l r
+let negate_real r = realNegate r
+let abs_real r = realAbs r
+let power_real b e = realPowInteger b e*)
+
+(*val print_endline : string -> unit*)
+definition print_endline  :: " string \<Rightarrow> unit "  where 
+     " print_endline _ = ( ()  )"
+
+(* declare ocaml target_rep function print_endline = `print_endline` *)
+
+(*val prerr_endline : string -> unit*)
+definition prerr_endline  :: " string \<Rightarrow> unit "  where 
+     " prerr_endline _ = ( ()  )"
+
+
+definition prerr  :: " string \<Rightarrow> unit "  where 
+     " prerr x = ( prerr_endline x )"
+
+
+(*val print_int : string -> integer -> unit*)
+definition print_int  :: " string \<Rightarrow> int \<Rightarrow> unit "  where 
+     " print_int msg i = ( print_endline (msg @ (stringFromInteger i)))"
+
+
+(*val prerr_int : string -> integer -> unit*)
+definition prerr_int  :: " string \<Rightarrow> int \<Rightarrow> unit "  where 
+     " prerr_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))"
+
+
+(*val putchar : integer -> unit*)
+definition putchar  :: " int \<Rightarrow> unit "  where 
+     " putchar _ = ( ()  )"
+
+
+(*val shr_int : ii -> ii -> ii*)
+function (sequential,domintros)  shr_int  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
+     " shr_int x s = ( if s >( 0 :: int) then shr_int (x div( 2 :: int)) (s -( 1 :: int)) else x )" 
+by pat_completeness auto
+
+
+(*val shl_int : integer -> integer -> integer*)
+function (sequential,domintros)  shl_int  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
+     " shl_int i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int i (shift -( 1 :: int)) else i )" 
+by pat_completeness auto
+
+definition take_list  :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " take_list n xs = ( List.take (nat_of_int n) xs )"
+
+definition drop_list  :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " drop_list n xs = ( List.drop (nat_of_int n) xs )"
+
+
+(*val repeat : forall 'a. list 'a -> integer -> list 'a*)
+fun  repeat  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a list "  where 
+     " repeat xs n = (
+  if n \<le>( 0 :: int) then []
+  else xs @ repeat xs (n-( 1 :: int)))"
+
+
+definition duplicate_to_list  :: " 'a \<Rightarrow> int \<Rightarrow> 'a list "  where 
+     " duplicate_to_list bit length1 = ( repeat [bit] length1 )"
+
+
+fun  replace  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
+     " replace ([]) (n :: int) b' = ( [])"
+|" replace (b # bs) (n :: int) b' = (
+     if n =( 0 :: int) then b' # bs
+              else b # replace bs (n -( 1 :: int)) b' )"
+
+
+definition upper  :: " 'a \<Rightarrow> 'a "  where 
+     " upper n = ( n )"
+
+
+(* Modulus operation corresponding to quot below -- result
+   has sign of dividend. *)
+definition hardware_mod  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
+     " hardware_mod (a:: int) (b::int) = (
+  (let m = ((abs a) mod (abs b)) in
+  if a <( 0 :: int) then - m else m))"
+
+
+(* There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that *)
+definition hardware_quot  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
+     " hardware_quot (a::int) (b::int) = (
+  (let q = ((abs a) div (abs b)) in
+  if ((a<( 0 :: int)) \<longleftrightarrow> (b<( 0 :: int))) then
+    q  (* same sign -- result positive *)
+  else
+    - q))"
+ (* different sign -- result negative *)
+
+definition max_64u  :: " int "  where 
+     " max_64u = ( ((( 2 :: int))^(( 64 :: nat))) -( 1 :: int))"
+
+definition max_64  :: " int "   where 
+     " max_64  = ( ((( 2 :: int))^(( 63 :: nat))) -( 1 :: int))"
+
+definition min_64  :: " int "   where 
+     " min_64  = (( 0 :: int) - ((( 2 :: int))^(( 63 :: nat))))"
+
+definition max_32u  :: " int "  where 
+     " max_32u = ( (( 4294967295 :: int) :: int))"
+
+definition max_32  :: " int "   where 
+     " max_32  = ( (( 2147483647 :: int) :: int))"
+
+definition min_32  :: " int "   where 
+     " min_32  = ( (( 0 :: int) -( 2147483648 :: int) :: int))"
+
+definition max_8  :: " int "    where 
+     " max_8   = ( (( 127 :: int) :: int))"
+
+definition min_8  :: " int "    where 
+     " min_8   = ( (( 0 :: int) -( 128 :: int) :: int))"
+
+definition max_5  :: " int "    where 
+     " max_5   = ( (( 31 :: int) :: int))"
+
+definition min_5  :: " int "    where 
+     " min_5   = ( (( 0 :: int) -( 32 :: int) :: int))"
+
+
+(* just_list takes a list of maybes and returns Just xs if all elements have
+   a value, and Nothing if one of the elements is Nothing. *)
+(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*)
+fun  just_list  :: "('a option)list \<Rightarrow>('a list)option "  where 
+     " just_list ([]) = ( Some [])"
+|" just_list (x # xs) = (
+    (case  (x, just_list xs) of
+        (Some x, Some xs) => Some (x # xs)
+      | (_, _) => None
+    ))"
+
+
+(*val maybe_failwith : forall 'a. maybe 'a -> 'a*)
+definition maybe_failwith  :: " 'a option \<Rightarrow> 'a "  where 
+     " maybe_failwith = ( \<lambda>x .  
+  (case  x of   Some a => a | None => failwith (''maybe_failwith'') ) )"
+
+
+(*** Bits *)
+datatype bitU = B0 | B1 | BU
+
+definition showBitU  :: " bitU \<Rightarrow> string "  where 
+     " showBitU = ( \<lambda>x .  
+  (case  x of   B0 => (''O'') | B1 => (''I'') | BU => (''U'') ) )"
+
+
+definition bitU_char  :: " bitU \<Rightarrow> char "  where 
+     " bitU_char = ( \<lambda>x .  
+  (case  x of   B0 => (CHR ''0'') | B1 => (CHR ''1'') | BU => (CHR ''?'') ) )"
+
+
+definition instance_Show_Show_Sail2_values_bitU_dict  :: "(bitU)Show_class "  where 
+     " instance_Show_Show_Sail2_values_bitU_dict = ((|
+
+  show_method = showBitU |) )"
+
+
+(*val compare_bitU : bitU -> bitU -> ordering*)
+fun compare_bitU  :: " bitU \<Rightarrow> bitU \<Rightarrow> ordering "  where 
+     " compare_bitU BU BU = ( EQ )"
+|" compare_bitU B0 B0 = ( EQ )"
+|" compare_bitU B1 B1 = ( EQ )"
+|" compare_bitU BU _ = ( LT )"
+|" compare_bitU _ BU = ( GT )"
+|" compare_bitU B0 _ = ( LT )"
+|" compare_bitU _ _ = ( GT )"
+
+
+definition instance_Basic_classes_Ord_Sail2_values_bitU_dict  :: "(bitU)Ord_class "  where 
+     " instance_Basic_classes_Ord_Sail2_values_bitU_dict = ((|
+
+  compare_method = compare_bitU,
+
+  isLess_method = (\<lambda>  l r. (compare_bitU l r) = LT),
+
+  isLessEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> GT),
+
+  isGreater_method = (\<lambda>  l r. (compare_bitU l r) = GT),
+
+  isGreaterEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> LT)|) )"
+
+
+record 'a BitU_class=
+
+  to_bitU_method ::" 'a \<Rightarrow> bitU " 
+
+  of_bitU_method ::" bitU \<Rightarrow> 'a "
+
+
+
+definition instance_Sail2_values_BitU_Sail2_values_bitU_dict  :: "(bitU)BitU_class "  where 
+     " instance_Sail2_values_BitU_Sail2_values_bitU_dict = ((|
+
+  to_bitU_method = (\<lambda> b. b),
+
+  of_bitU_method = (\<lambda> b. b)|) )"
+
+
+definition bool_of_bitU  :: " bitU \<Rightarrow>(bool)option "  where 
+     " bool_of_bitU = ( \<lambda>x .  
+  (case  x of   B0 => Some False | B1 => Some True | BU => None ) )"
+
+
+definition bitU_of_bool  :: " bool \<Rightarrow> bitU "  where 
+     " bitU_of_bool b = ( if b then B1 else B0 )"
+
+
+(*instance (BitU bool)
+  let to_bitU = bitU_of_bool
+  let of_bitU = bool_of_bitU
+end*)
+
+definition cast_bit_bool  :: " bitU \<Rightarrow>(bool)option "  where 
+     " cast_bit_bool = ( bool_of_bitU )"
+
+
+definition not_bit  :: " bitU \<Rightarrow> bitU "  where 
+     " not_bit = ( \<lambda>x .  
+  (case  x of   B1 => B0 | B0 => B1 | BU => BU ) )"
+
+
+(*val is_one : integer -> bitU*)
+definition is_one  :: " int \<Rightarrow> bitU "  where 
+     " is_one i = (
+  if i =( 1 :: int) then B1 else B0 )"
+
+
+(*val and_bit : bitU -> bitU -> bitU*)
+fun and_bit  :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU "  where 
+     " and_bit B0 _ = ( B0 )"
+|" and_bit _ B0 = ( B0 )"
+|" and_bit B1 B1 = ( B1 )"
+|" and_bit _ _ = ( BU )"
+
+
+(*val or_bit : bitU -> bitU -> bitU*)
+fun or_bit  :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU "  where 
+     " or_bit B1 _ = ( B1 )"
+|" or_bit _ B1 = ( B1 )"
+|" or_bit B0 B0 = ( B0 )"
+|" or_bit _ _ = ( BU )"
+
+
+(*val xor_bit : bitU -> bitU -> bitU*)
+fun xor_bit  :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU "  where 
+     " xor_bit B0 B0 = ( B0 )"
+|" xor_bit B0 B1 = ( B1 )"
+|" xor_bit B1 B0 = ( B1 )"
+|" xor_bit B1 B1 = ( B0 )"
+|" xor_bit _ _ = ( BU )"
+
+
+(*val &. : bitU -> bitU -> bitU*)
+
+(*val |. : bitU -> bitU -> bitU*)
+
+(*val +. : bitU -> bitU -> bitU*)
+
+
+(*** Bool lists ***)
+
+(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
+fun  bools_of_nat_aux  :: " int \<Rightarrow> nat \<Rightarrow>(bool)list \<Rightarrow>(bool)list "  where 
+     " bools_of_nat_aux len x acc1 = (
+  if len \<le>( 0 :: int) then acc1
+  else bools_of_nat_aux (len -( 1 :: int)) (x div( 2 :: nat)) ((if (x mod( 2 :: nat)) =( 1 :: nat) then True else False) # acc1))"
+
+definition bools_of_nat  :: " int \<Rightarrow> nat \<Rightarrow>(bool)list "  where 
+     " bools_of_nat len n = ( bools_of_nat_aux len n [])"
+ (*List.reverse (bools_of_nat_aux n)*)
+
+(*val nat_of_bools_aux : natural -> list bool -> natural*)
+fun  nat_of_bools_aux  :: " nat \<Rightarrow>(bool)list \<Rightarrow> nat "  where 
+     " nat_of_bools_aux acc1 ([]) = ( acc1 )"
+|" nat_of_bools_aux acc1 (True # bs) = ( nat_of_bools_aux ((( 2 :: nat) * acc1) +( 1 :: nat)) bs )"
+|" nat_of_bools_aux acc1 (False # bs) = ( nat_of_bools_aux (( 2 :: nat) * acc1) bs )"
+
+definition nat_of_bools  :: "(bool)list \<Rightarrow> nat "  where 
+     " nat_of_bools bs = ( nat_of_bools_aux(( 0 :: nat)) bs )"
+
+
+(*val unsigned_of_bools : list bool -> integer*)
+definition unsigned_of_bools  :: "(bool)list \<Rightarrow> int "  where 
+     " unsigned_of_bools bs = ( int (nat_of_bools bs))"
+
+
+(*val signed_of_bools : list bool -> integer*)
+definition signed_of_bools  :: "(bool)list \<Rightarrow> int "  where 
+     " signed_of_bools bs = (
+  (case  bs of
+      True # _  =>( 0 :: int) - (( 1 :: int) + (unsigned_of_bools (List.map (\<lambda> x. \<not> x) bs)))
+    | False # _ => unsigned_of_bools bs
+    | [] =>( 0 :: int) (* Treat empty list as all zeros *)
+  ))"
+
+
+(*val int_of_bools : bool -> list bool -> integer*)
+definition int_of_bools  :: " bool \<Rightarrow>(bool)list \<Rightarrow> int "  where 
+     " int_of_bools sign bs = ( if sign then signed_of_bools bs else unsigned_of_bools bs )"
+
+
+(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
+fun  pad_list  :: " 'a \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a list "  where 
+     " pad_list x xs n = (
+  if n \<le>( 0 :: int) then xs else pad_list x (x # xs) (n -( 1 :: int)))"
+
+
+definition ext_list  :: " 'a \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " ext_list pad len xs = (
+  (let longer = (len - (int (List.length xs))) in
+  if longer <( 0 :: int) then List.drop (nat_of_int (abs (longer))) xs
+  else pad_list pad xs longer))"
+
+
+definition extz_bools  :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list "  where 
+     " extz_bools len bs = ( ext_list False len bs )"
+
+definition exts_bools  :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list "  where 
+     " exts_bools len bs = (
+  (case  bs of
+      True # _ => ext_list True len bs
+    | _ => ext_list False len bs
+  ))"
+
+
+fun  add_one_bool_ignore_overflow_aux  :: "(bool)list \<Rightarrow>(bool)list "  where 
+     " add_one_bool_ignore_overflow_aux ([]) = ( [])"
+|" add_one_bool_ignore_overflow_aux (False # bits) = ( True # bits )"
+|" add_one_bool_ignore_overflow_aux (True # bits) = ( False # add_one_bool_ignore_overflow_aux bits )"
+
+
+definition add_one_bool_ignore_overflow  :: "(bool)list \<Rightarrow>(bool)list "  where 
+     " add_one_bool_ignore_overflow bits = (
+  List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)))"
+
+
+(*let bool_list_of_int n =
+  let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
+  if n >= (0 : integer) then bs_abs
+  else add_one_bool_ignore_overflow (List.map not bs_abs)
+let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
+definition bools_of_int  :: " int \<Rightarrow> int \<Rightarrow>(bool)list "  where 
+     " bools_of_int len n = (
+  (let bs_abs = (bools_of_nat len (nat (abs (abs n)))) in
+  if n \<ge> (( 0 :: int) :: int) then bs_abs
+  else add_one_bool_ignore_overflow (List.map (\<lambda> x. \<not> x) bs_abs)))"
+
+
+(*** Bit lists ***)
+
+(*val has_undefined_bits : list bitU -> bool*)
+definition has_undefined_bits  :: "(bitU)list \<Rightarrow> bool "  where 
+     " has_undefined_bits bs = ( ((\<exists> x \<in> (set bs).  (\<lambda>x .  
+  (case  x of BU => True | _ => False )) x)))"
+
+
+definition bits_of_nat  :: " int \<Rightarrow> nat \<Rightarrow>(bitU)list "  where 
+     " bits_of_nat len n = ( List.map bitU_of_bool (bools_of_nat len n))"
+
+
+definition nat_of_bits  :: "(bitU)list \<Rightarrow>(nat)option "  where 
+     " nat_of_bits bits = (
+  (case  (just_list (List.map bool_of_bitU bits)) of
+      Some bs => Some (nat_of_bools bs)
+    | None => None
+  ))"
+
+
+definition not_bits  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
+     " not_bits = ( List.map not_bit )"
+
+
+(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*)
+definition binop_list  :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " binop_list op1 xs ys = (
+  List.foldr ( \<lambda>x .  
+  (case  x of (x, y) => \<lambda> acc1 .  op1 x y # acc1 )) (List.zip xs ys) [])"
+
+
+definition unsigned_of_bits  :: "(bitU)list \<Rightarrow>(int)option "  where 
+     " unsigned_of_bits bits = (
+  (case  (just_list (List.map bool_of_bitU bits)) of
+      Some bs => Some (unsigned_of_bools bs)
+    | None => None
+  ))"
+
+
+definition signed_of_bits  :: "(bitU)list \<Rightarrow>(int)option "  where 
+     " signed_of_bits bits = (
+  (case  (just_list (List.map bool_of_bitU bits)) of
+      Some bs => Some (signed_of_bools bs)
+    | None => None
+  ))"
+
+
+(*val int_of_bits : bool -> list bitU -> maybe integer*)
+definition int_of_bits  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option "  where 
+     " int_of_bits sign bs = ( if sign then signed_of_bits bs else unsigned_of_bits bs )"
+
+
+definition extz_bits  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " extz_bits len bits = ( ext_list B0 len bits )"
+
+definition exts_bits  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " exts_bits len bits = (
+  (case  bits of
+    BU # _ => ext_list BU len bits
+  | B1 # _ => ext_list B1 len bits
+  | _ => ext_list B0 len bits
+  ))"
+
+
+fun  add_one_bit_ignore_overflow_aux  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
+     " add_one_bit_ignore_overflow_aux ([]) = ( [])"
+|" add_one_bit_ignore_overflow_aux (B0 # bits) = ( B1 # bits )"
+|" add_one_bit_ignore_overflow_aux (B1 # bits) = ( B0 # add_one_bit_ignore_overflow_aux bits )"
+|" add_one_bit_ignore_overflow_aux (BU # bits) = ( BU # List.map ( \<lambda>x .  
+  (case  x of _ => BU )) bits )"
+
+
+definition add_one_bit_ignore_overflow  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
+     " add_one_bit_ignore_overflow bits = (
+  List.rev (add_one_bit_ignore_overflow_aux (List.rev bits)))"
+
+
+(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n)
+let bits_of_int len n = exts_bits len (bit_list_of_int n)*)
+definition bits_of_int  :: " int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " bits_of_int len n = ( List.map bitU_of_bool (bools_of_int len n))"
+
+
+(*val arith_op_bits :
+  (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
+definition arith_op_bits  :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
+     " arith_op_bits op1 sign l r = (
+  (case  (int_of_bits sign l, int_of_bits sign r) of
+      (Some li, Some ri) => bits_of_int (int (List.length l)) (op1 li ri)
+    | (_, _) => repeat [BU] (int (List.length l))
+  ))"
+
+
+definition char_of_nibble  :: " bitU*bitU*bitU*bitU \<Rightarrow>(char)option "  where 
+     " char_of_nibble = ( \<lambda>x .  
+  (case  x of
+        (B0, B0, B0, B0) => Some (CHR ''0'')
+    | (B0, B0, B0, B1) => Some (CHR ''1'')
+    | (B0, B0, B1, B0) => Some (CHR ''2'')
+    | (B0, B0, B1, B1) => Some (CHR ''3'')
+    | (B0, B1, B0, B0) => Some (CHR ''4'')
+    | (B0, B1, B0, B1) => Some (CHR ''5'')
+    | (B0, B1, B1, B0) => Some (CHR ''6'')
+    | (B0, B1, B1, B1) => Some (CHR ''7'')
+    | (B1, B0, B0, B0) => Some (CHR ''8'')
+    | (B1, B0, B0, B1) => Some (CHR ''9'')
+    | (B1, B0, B1, B0) => Some (CHR ''A'')
+    | (B1, B0, B1, B1) => Some (CHR ''B'')
+    | (B1, B1, B0, B0) => Some (CHR ''C'')
+    | (B1, B1, B0, B1) => Some (CHR ''D'')
+    | (B1, B1, B1, B0) => Some (CHR ''E'')
+    | (B1, B1, B1, B1) => Some (CHR ''F'')
+    | _ => None
+  ) )"
+
+
+fun  hexstring_of_bits  :: "(bitU)list \<Rightarrow>((char)list)option "  where 
+     " hexstring_of_bits (b1 # b2 # b3 # b4 # bs) = (
+     (let n = (char_of_nibble (b1, b2, b3, b4)) in
+     (let s = (hexstring_of_bits bs) in
+     (case  (n, s) of
+       (Some n, Some s) => Some (n # s)
+     | _ => None
+     ))))"
+|" hexstring_of_bits ([]) = ( Some [])"
+|" hexstring_of_bits _ = ( None )"
+
+
+definition show_bitlist  :: "(bitU)list \<Rightarrow> string "  where 
+     " show_bitlist bs = (
+  (case  hexstring_of_bits bs of
+    Some s => ((CHR ''0'') # ((CHR ''x'') # s))
+  | None => ((CHR ''0'') # ((CHR ''b'') # List.map bitU_char bs))
+  ))"
+
+
+(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*)
+definition subrange_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list "  where 
+     " subrange_list_inc xs i j = (
+  (let (toJ,suffix0) = (split_at (nat_of_int (j +( 1 :: int))) xs) in
+  (let (prefix0,fromItoJ) = (split_at (nat_of_int i) toJ) in
+  fromItoJ)))"
+
+
+(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*)
+definition subrange_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list "  where 
+     " subrange_list_dec xs i j = (
+  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+  subrange_list_inc xs (top1 - i) (top1 - j)))"
+
+
+(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*)
+definition subrange_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list "  where 
+     " subrange_list is_inc xs i j = ( if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j )"
+
+
+(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
+definition update_subrange_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " update_subrange_list_inc xs i j xs' = (
+  (let (toJ,suffix) = (split_at (nat_of_int (j +( 1 :: int))) xs) in
+  (let (prefix,fromItoJ0) = (split_at (nat_of_int i) toJ) in
+  (prefix @ xs') @ suffix)))"
+
+
+(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
+definition update_subrange_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " update_subrange_list_dec xs i j xs' = (
+  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+  update_subrange_list_inc xs (top1 - i) (top1 - j) xs'))"
+
+
+(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*)
+definition update_subrange_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
+     " update_subrange_list is_inc xs i j xs' = (
+  if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs' )"
+
+
+(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*)
+definition access_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a "  where 
+     " access_list_inc xs n = ( List.nth xs (nat_of_int n))"
+
+
+(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*)
+definition access_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a "  where 
+     " access_list_dec xs n = (
+  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+  access_list_inc xs (top1 - n)))"
+
+
+(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*)
+definition access_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a "  where 
+     " access_list is_inc xs n = (
+  if is_inc then access_list_inc xs n else access_list_dec xs n )"
+
+
+(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*)
+definition update_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
+     " update_list_inc xs n x = ( List.list_update xs (nat_of_int n) x )"
+
+
+(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*)
+definition update_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
+     " update_list_dec xs n x = (
+  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+  update_list_inc xs (top1 - n) x))"
+
+
+(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*)
+definition update_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
+     " update_list is_inc xs n x = (
+  if is_inc then update_list_inc xs n x else update_list_dec xs n x )"
+
+
+definition extract_only_bit  :: "(bitU)list \<Rightarrow> bitU "  where 
+     " extract_only_bit = ( \<lambda>x .  
+  (case  x of   [] => BU | [e] => e | _ => BU ) )"
+
+
+(*** Machine words *)
+
+(*val length_mword : forall 'a. mword 'a -> integer*)
+
+(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
+definition slice_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " slice_mword_dec w i j = ( Word.slice (nat_of_int i) w )"
+
+
+(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
+definition slice_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " slice_mword_inc w i j = (
+  (let top1 = ((int (size w)) -( 1 :: int)) in
+  slice_mword_dec w (top1 - i) (top1 - j)))"
+
+
+(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*)
+definition slice_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
+     " slice_mword is_inc w i j = ( if is_inc then slice_mword_inc w i j else slice_mword_dec w i j )"
+
+
+(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+definition update_slice_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " update_slice_mword_dec w i j w' = ( Lem.word_update w (nat_of_int i) (nat_of_int j) w' )"
+
+
+(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+definition update_slice_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " update_slice_mword_inc w i j w' = (
+  (let top1 = ((int (size w)) -( 1 :: int)) in
+  update_slice_mword_dec w (top1 - i) (top1 - j) w'))"
+
+
+(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+definition update_slice_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
+     " update_slice_mword is_inc w i j w' = (
+  if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w' )"
+
+
+(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*)
+definition access_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_mword_dec w n = ( bitU_of_bool (Bits.test_bit w (nat_of_int n)))"
+
+
+(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*)
+definition access_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_mword_inc w n = (
+  (let top1 = ((int (size w)) -( 1 :: int)) in
+  access_mword_dec w (top1 - n)))"
+
+
+(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*)
+definition access_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_mword is_inc w n = (
+  if is_inc then access_mword_inc w n else access_mword_dec w n )"
+
+
+(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+definition update_mword_bool_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " update_mword_bool_dec w n b = ( Bits.set_bit w (nat_of_int n) b )"
+
+definition update_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " update_mword_dec w n b = ( map_option (update_mword_bool_dec w n) (bool_of_bitU b))"
+
+
+(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+definition update_mword_bool_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
+     " update_mword_bool_inc w n b = (
+  (let top1 = ((int (size w)) -( 1 :: int)) in
+  update_mword_bool_dec w (top1 - n) b))"
+
+definition update_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
+     " update_mword_inc w n b = ( map_option (update_mword_bool_inc w n) (bool_of_bitU b))"
+
+
+(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
+definition int_of_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
+     " int_of_mword sign w = (
+  if sign then Word.sint w else Word.uint w )"
+
+
+(* Translating between a type level number (itself 'n) and an integer *)
+
+definition size_itself_int  :: "('a::len)itself \<Rightarrow> int "  where 
+     " size_itself_int x = ( int (size_itself x))"
+
+
+(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n),
+   the actual integer is ignored. *)
+
+(*val make_the_value : forall 'n. integer -> itself 'n*)
+definition make_the_value  :: " int \<Rightarrow>('n::len)itself "  where 
+     " make_the_value _ = ( TYPE(_) )"
+
+
+(*** Bitvectors *)
+
+record 'a Bitvector_class=
+
+  bits_of_method ::" 'a \<Rightarrow> bitU list " 
+
+  (* We allow of_bits to be partial, as not all bitvector representations
+     support undefined bits *)
+  of_bits_method ::" bitU list \<Rightarrow>  'a option " 
+
+  of_bools_method ::" bool list \<Rightarrow> 'a " 
+
+  length_method ::" 'a \<Rightarrow> int " 
+
+  (* of_int: the first parameter specifies the desired length of the bitvector *)
+  of_int_method ::" int \<Rightarrow> int \<Rightarrow> 'a " 
+
+  (* Conversion to integers is undefined if any bit is undefined *)
+  unsigned_method ::" 'a \<Rightarrow>  int option " 
+
+  signed_method ::" 'a \<Rightarrow>  int option " 
+
+  (* Lifting of integer operations to bitvectors:  The boolean flag indicates
+     whether to treat the bitvectors as signed (true) or not (false). *)
+  arith_op_bv_method ::" (int \<Rightarrow> int \<Rightarrow> int) \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*)
+definition of_bits_failwith  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'a "  where 
+     " of_bits_failwith dict_Sail2_values_Bitvector_a bits = ( maybe_failwith (
+  (of_bits_method   dict_Sail2_values_Bitvector_a) bits))"
+
+
+definition int_of_bv  :: " 'a Bitvector_class \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow>(int)option "  where 
+     " int_of_bv dict_Sail2_values_Bitvector_a sign = ( if sign then 
+  (signed_method   dict_Sail2_values_Bitvector_a) else (unsigned_method   dict_Sail2_values_Bitvector_a) )"
+
+
+definition instance_Sail2_values_Bitvector_list_dict  :: " 'a BitU_class \<Rightarrow>('a list)Bitvector_class "  where 
+     " instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a = ((|
+
+  bits_of_method = (\<lambda> v. List.map 
+  (to_bitU_method   dict_Sail2_values_BitU_a) v),
+
+  of_bits_method = (\<lambda> v. Some (List.map 
+  (of_bitU_method   dict_Sail2_values_BitU_a) v)),
+
+  of_bools_method = (\<lambda> v. List.map 
+  (of_bitU_method   dict_Sail2_values_BitU_a) (List.map bitU_of_bool v)),
+
+  length_method = (\<lambda> xs. int (List.length xs)),
+
+  of_int_method = (\<lambda> len n. List.map 
+  (of_bitU_method   dict_Sail2_values_BitU_a) (bits_of_int len n)),
+
+  unsigned_method = (\<lambda> v. unsigned_of_bits (List.map 
+  (to_bitU_method   dict_Sail2_values_BitU_a) v)),
+
+  signed_method = (\<lambda> v. signed_of_bits (List.map 
+  (to_bitU_method   dict_Sail2_values_BitU_a) v)),
+
+  arith_op_bv_method = (\<lambda> op1 sign l r. List.map 
+  (of_bitU_method   dict_Sail2_values_BitU_a) (arith_op_bits op1 sign (List.map 
+  (to_bitU_method   dict_Sail2_values_BitU_a) l) (List.map (to_bitU_method   dict_Sail2_values_BitU_a) r)))|) )"
+
+
+definition instance_Sail2_values_Bitvector_Machine_word_mword_dict  :: "(('a::len)Word.word)Bitvector_class "  where 
+     " instance_Sail2_values_Bitvector_Machine_word_mword_dict = ((|
+
+  bits_of_method = (\<lambda> v. List.map bitU_of_bool (Word.to_bl v)),
+
+  of_bits_method = (\<lambda> v. map_option Word.of_bl (just_list (List.map bool_of_bitU v))),
+
+  of_bools_method = (\<lambda> v. Word.of_bl v),
+
+  length_method = (\<lambda> v. int (size v)),
+
+  of_int_method = ( \<lambda>x .  
+  (case  x of _ => \<lambda> n .  Word.word_of_int n )),
+
+  unsigned_method = (\<lambda> v. Some (Word.uint v)),
+
+  signed_method = (\<lambda> v. Some (Word.sint v)),
+
+  arith_op_bv_method = (\<lambda> op1 sign l r. Word.word_of_int (op1 (int_of_mword sign l) (int_of_mword sign r)))|) )"
+
+
+definition access_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_bv_inc dict_Sail2_values_Bitvector_a v n = ( access_list True  (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) n )"
+
+definition access_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU "  where 
+     " access_bv_dec dict_Sail2_values_Bitvector_a v n = ( access_list False (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) n )"
+
+
+definition update_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " update_bv_inc dict_Sail2_values_Bitvector_a v n b = ( update_list True  (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) n b )"
+
+definition update_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
+     " update_bv_dec dict_Sail2_values_Bitvector_a v n b = ( update_list False (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) n b )"
+
+
+definition subrange_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " subrange_bv_inc dict_Sail2_values_Bitvector_a v i j = ( subrange_list True  (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) i j )"
+
+definition subrange_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
+     " subrange_bv_dec dict_Sail2_values_Bitvector_a v i j = ( subrange_list False (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v) i j )"
+
+
+definition update_subrange_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
+     " update_subrange_bv_inc dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v' = ( update_subrange_list True  (
+  (bits_of_method   dict_Sail2_values_Bitvector_b) v) i j ((bits_of_method   dict_Sail2_values_Bitvector_a) v'))"
+
+definition update_subrange_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
+     " update_subrange_bv_dec dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v' = ( update_subrange_list False (
+  (bits_of_method   dict_Sail2_values_Bitvector_b) v) i j ((bits_of_method   dict_Sail2_values_Bitvector_a) v'))"
+
+
+(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
+definition extz_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
+     " extz_bv dict_Sail2_values_Bitvector_a n v = ( extz_bits n (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v))"
+
+
+(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
+definition exts_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
+     " exts_bv dict_Sail2_values_Bitvector_a n v = ( exts_bits n (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v))"
+
+
+(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*)
+definition string_of_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string "  where 
+     " string_of_bv dict_Sail2_values_Bitvector_a v = ( show_bitlist (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) v))"
+
+
+(*** Bytes and addresses *)
+
+type_synonym memory_byte =" bitU list "
+
+(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*)
+fun  byte_chunks  :: " 'a list \<Rightarrow>(('a list)list)option "  where 
+     " byte_chunks ([]) = ( Some [])"
+|" byte_chunks (a # b # c # d # e # f # g # h # rest) = (
+     Option.bind (byte_chunks rest) (\<lambda> rest .  Some ([a,b,c,d,e,f,g,h] # rest)))"
+|" byte_chunks _ = ( None )"
+
+
+(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*)
+definition bytes_of_bits  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option "  where 
+     " bytes_of_bits dict_Sail2_values_Bitvector_a bs = ( byte_chunks (
+  (bits_of_method   dict_Sail2_values_Bitvector_a) bs))"
+
+
+(*val bits_of_bytes : list memory_byte -> list bitU*)
+definition bits_of_bytes  :: "((bitU)list)list \<Rightarrow>(bitU)list "  where 
+     " bits_of_bytes bs = ( List.concat (List.map (\<lambda> v. List.map (\<lambda> b. b) v) bs))"
+
+
+definition mem_bytes_of_bits  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option "  where 
+     " mem_bytes_of_bits dict_Sail2_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits 
+  dict_Sail2_values_Bitvector_a bs))"
+
+definition bits_of_mem_bytes  :: "((bitU)list)list \<Rightarrow>(bitU)list "  where 
+     " bits_of_mem_bytes bs = ( bits_of_bytes (List.rev bs))"
+
+
+(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+let bitv_of_byte_lifteds v =
+  foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+let bitv_of_bytes v =
+  foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+let byte_lifteds_of_bitv bits =
+  let bits = List.map bit_lifted_of_bitU bits in
+  byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+let bytes_of_bitv bits =
+  let bits = List.map bit_of_bitU bits in
+  bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+let address_lifted_of_bitv v =
+  let byte_lifteds = byte_lifteds_of_bitv v in
+  let maybe_address_integer =
+    match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+    | Just bs -> Just (integer_of_byte_list bs)
+    | _ -> Nothing
+    end in
+  Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+let address_of_bitv v =
+  let bytes = bytes_of_bitv v in
+  address_of_byte_list bytes*)
+
+function (sequential,domintros)  reverse_endianness_list  :: " 'a list \<Rightarrow> 'a list "  where 
+     " reverse_endianness_list bits = (
+  if List.length bits \<le>( 8 :: nat) then bits else
+    reverse_endianness_list (drop_list(( 8 :: int)) bits) @ take_list(( 8 :: int)) bits )" 
+by pat_completeness auto
+
+
+
+(*** Registers *)
+
+(*type register_field = string
+type register_field_index = string * (integer * integer) (* name, start and end *)
+
+type register =
+  | Register of string * (* name *)
+                integer * (* length *)
+                integer * (* start index *)
+                bool * (* is increasing *)
+                  list register_field_index
+  | UndefinedRegister of integer (* length *)
+  | RegisterPair of register * register*)
+
+record( 'regstate, 'regval, 'a) register_ref =
+  
+ name ::" string " 
+
+     (*is_inc : bool;*)
+     read_from ::" 'regstate \<Rightarrow> 'a " 
+
+     write_to ::" 'a \<Rightarrow> 'regstate \<Rightarrow> 'regstate " 
+
+     of_regval ::" 'regval \<Rightarrow>  'a option " 
+
+     regval_of ::" 'a \<Rightarrow> 'regval " 
+
+
+(* Register accessors: pair of functions for reading and writing register values *)
+type_synonym( 'regstate, 'regval) register_accessors ="
+  ((string \<Rightarrow> 'regstate \<Rightarrow>  'regval option) *
+   (string \<Rightarrow> 'regval \<Rightarrow> 'regstate \<Rightarrow>  'regstate option))"
+
+record( 'regtype, 'a) field_ref =
+  
+ field_name ::" string " 
+
+     field_start ::" int " 
+
+     field_is_inc ::" bool " 
+
+     get_field ::" 'regtype \<Rightarrow> 'a " 
+
+     set_field ::" 'regtype \<Rightarrow> 'a \<Rightarrow> 'regtype " 
+
+
+(*let name_of_reg = function
+  | Register name _ _ _ _ -> name
+  | UndefinedRegister _ -> failwith name_of_reg UndefinedRegister
+  | RegisterPair _ _ -> failwith name_of_reg RegisterPair
+end
+
+let size_of_reg = function
+  | Register _ size _ _ _ -> size
+  | UndefinedRegister size -> size
+  | RegisterPair _ _ -> failwith size_of_reg RegisterPair
+end
+
+let start_of_reg = function
+  | Register _ _ start _ _ -> start
+  | UndefinedRegister _ -> failwith start_of_reg UndefinedRegister
+  | RegisterPair _ _ -> failwith start_of_reg RegisterPair
+end
+
+let is_inc_of_reg = function
+  | Register _ _ _ is_inc _ -> is_inc
+  | UndefinedRegister _ -> failwith is_inc_of_reg UndefinedRegister
+  | RegisterPair _ _ -> failwith in_inc_of_reg RegisterPair
+end
+
+let dir_of_reg = function
+  | Register _ _ _ is_inc _ -> dir_of_bool is_inc
+  | UndefinedRegister _ -> failwith dir_of_reg UndefinedRegister
+  | RegisterPair _ _ -> failwith dir_of_reg RegisterPair
+end
+
+let size_of_reg_nat reg = natFromInteger (size_of_reg reg)
+let start_of_reg_nat reg = natFromInteger (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> maybe (integer * integer)
+let rec register_field_indices_aux register rfield =
+  match register with
+  | Register _ _ _ _ rfields -> List.lookup rfield rfields
+  | RegisterPair r1 r2 ->
+      let m_indices = register_field_indices_aux r1 rfield in
+      if isJust m_indices then m_indices else register_field_indices_aux r2 rfield
+  | UndefinedRegister _ -> Nothing
+  end
+
+val register_field_indices : register -> register_field -> integer * integer
+let register_field_indices register rfield =
+  match register_field_indices_aux register rfield with
+  | Just indices -> indices
+  | Nothing -> failwith Invalid register/register-field combination
+  end
+
+let register_field_indices_nat reg regfield=
+  let (i,j) = register_field_indices reg regfield in
+  (natFromInteger i,natFromInteger j)*)
+
+(*let rec external_reg_value reg_name v =
+  let (internal_start, external_start, direction) =
+    match reg_name with
+     | Reg _ start size dir ->
+        (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+     | Reg_slice _ reg_start dir (slice_start, _) ->
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_field _ reg_start dir _ (slice_start, _) ->
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_f_slice _ reg_start dir _ _ (slice_start, _) ->
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     end in
+  let bits = bit_lifteds_of_bitv v in
+  <| rv_bits           = bits;
+     rv_dir            = direction;
+     rv_start          = external_start;
+     rv_start_internal = internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+let internal_reg_value v =
+  List.map bitU_of_bit_lifted v.rv_bits
+         (*(integerFromNat v.rv_start_internal)
+         (v.rv_dir = D_increasing)*)
+
+
+let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) =
+  match d with
+  (*This is the case the thread/concurrecny model expects, so no change needed*)
+  | D_increasing -> (i,j)
+  | D_decreasing -> let slice_i = start - i in
+                    let slice_j = (i - j) + slice_i in
+                    (slice_i,slice_j)
+  end *)
+
+(* TODO
+let external_reg_whole r =
+  Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc)
+
+let external_reg_slice r (i,j) =
+  let start = natFromInteger r.start in
+  let dir = dir_of_bool r.is_inc in
+  Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+let external_reg_field_whole reg rfield =
+  let (m,n) = register_field_indices_nat reg rfield in
+  let start = start_of_reg_nat reg in
+  let dir = dir_of_reg reg in
+  Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+let external_reg_field_slice reg rfield (i,j) =
+  let (m,n) = register_field_indices_nat reg rfield in
+  let start = start_of_reg_nat reg in
+  let dir = dir_of_reg reg in
+  Reg_f_slice (name_of_reg reg) start dir rfield
+              (external_slice dir start (m,n))
+              (external_slice dir start (i,j))*)
+
+(*val external_mem_value : list bitU -> memory_value
+let external_mem_value v =
+  byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+let internal_mem_value bytes =
+  List.reverse bytes $> bitv_of_byte_lifteds*)
+
+
+(*val foreach : forall 'a 'vars.
+  (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*)
+fun  foreach  :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'vars)\<Rightarrow> 'vars "  where 
+     " foreach ([]) vars body = ( vars )"
+|" foreach (x # xs) vars body = ( foreach xs (body x vars) body )"
+
+
+(*val index_list : integer -> integer -> integer -> list integer*)
+function (sequential,domintros)  index_list  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)list "  where 
+     " index_list from1 to1 step = (
+  if ((step >( 0 :: int)) \<and> (from1 \<le> to1)) \<or> ((step <( 0 :: int)) \<and> (to1 \<le> from1)) then
+    from1 # index_list (from1 + step) to1 step
+  else [])" 
+by pat_completeness auto
+
+
+(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
+function (sequential,domintros)  while  :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars "  where 
+     " while vars cond body = (
+  if cond vars then while (body vars) cond body else vars )" 
+by pat_completeness auto
+
+
+(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
+function (sequential,domintros)  until  :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars "  where 
+     " until vars cond body = (
+  (let vars = (body vars) in
+  if cond vars then vars else until (body vars) cond body))" 
+by pat_completeness auto
+
+
+
+(* convert numbers unsafely to naturals *)
+
+record 'a ToNatural_class=
+ toNatural_method ::" 'a \<Rightarrow> nat " 
+
+(* eta-expanded for Isabelle output, otherwise it breaks *)
+definition instance_Sail2_values_ToNatural_Num_integer_dict  :: "(int)ToNatural_class "  where 
+     " instance_Sail2_values_ToNatural_Num_integer_dict = ((|
+
+  toNatural_method = (\<lambda> n .  nat (abs n))|) )"
+
+definition instance_Sail2_values_ToNatural_Num_int_dict  :: "(int)ToNatural_class "  where 
+     " instance_Sail2_values_ToNatural_Num_int_dict = ((|
+
+  toNatural_method = (\<lambda> n .   (nat (abs n)))|) )"
+
+definition instance_Sail2_values_ToNatural_nat_dict  :: "(nat)ToNatural_class "  where 
+     " instance_Sail2_values_ToNatural_nat_dict = ((|
+
+  toNatural_method = (\<lambda> n .   n)|) )"
+
+definition instance_Sail2_values_ToNatural_Num_natural_dict  :: "(nat)ToNatural_class "  where 
+     " instance_Sail2_values_ToNatural_Num_natural_dict = ((|
+
+  toNatural_method = (\<lambda> n .  n)|) )"
+
+
+fun toNaturalFiveTup  :: " 'a ToNatural_class \<Rightarrow> 'b ToNatural_class \<Rightarrow> 'c ToNatural_class \<Rightarrow> 'd ToNatural_class \<Rightarrow> 'e ToNatural_class \<Rightarrow> 'd*'c*'b*'a*'e \<Rightarrow> nat*nat*nat*nat*nat "  where 
+     " toNaturalFiveTup dict_Sail2_values_ToNatural_a dict_Sail2_values_ToNatural_b dict_Sail2_values_ToNatural_c dict_Sail2_values_ToNatural_d dict_Sail2_values_ToNatural_e (n1,n2,n3,n4,n5) = (
+  ((toNatural_method   dict_Sail2_values_ToNatural_d) n1,(toNatural_method   dict_Sail2_values_ToNatural_c) n2,(toNatural_method   dict_Sail2_values_ToNatural_b) n3,(toNatural_method   dict_Sail2_values_ToNatural_a) n4,(toNatural_method   dict_Sail2_values_ToNatural_e) n5))"
+
+
+(* Let the following types be generated by Sail per spec, using either bitlists
+   or machine words as bitvector representation *)
+(*type regfp =
+  | RFull of (string)
+  | RSlice of (string * integer * integer)
+  | RSliceBit of (string * integer)
+  | RField of (string * string)
+
+type niafp =
+  | NIAFP_successor
+  | NIAFP_concrete_address of vector bitU
+  | NIAFP_indirect_address
+
+(* only for MIPS *)
+type diafp =
+  | DIAFP_none
+  | DIAFP_concrete of vector bitU
+  | DIAFP_reg of regfp
+
+let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function
+  | RFull name ->
+     let (start,length,direction,_) = reg_info name Nothing in
+     Reg name start length direction
+  | RSlice (name,i,j) ->
+     let i = natFromInteger i in
+     let j = natFromInteger j in
+     let (start,length,direction,_) = reg_info name Nothing in
+     let slice = external_slice direction start (i,j) in
+     Reg_slice name start direction slice
+  | RSliceBit (name,i) ->
+     let i = natFromInteger i in
+     let (start,length,direction,_) = reg_info name Nothing in
+     let slice = external_slice direction start (i,i) in
+     Reg_slice name start direction slice
+  | RField (name,field_name) ->
+     let (start,length,direction,span) = reg_info name (Just field_name) in
+     let slice = external_slice direction start span in
+     Reg_field name start direction field_name slice
+end
+
+let niafp_to_nia reginfo = function
+  | NIAFP_successor -> NIA_successor
+  | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v)
+  | NIAFP_indirect_address -> NIA_indirect_address
+end
+
+let diafp_to_dia reginfo = function
+  | DIAFP_none -> DIA_none
+  | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v)
+  | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r)
+end
+*)
+end
diff --git a/snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy
new file mode 100644
index 00000000..576cd8ea
--- /dev/null
+++ b/snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy
@@ -0,0 +1,340 @@
+theory Sail2_values_lemmas
+  imports Sail2_values
+begin
+
+lemma while_domI:
+  fixes V :: "'vars \<Rightarrow> nat"
+  assumes "\<And>vars. cond vars \<Longrightarrow> V (body vars) < V vars"
+  shows "while_dom (vars, cond, body)"
+  by (induction vars rule: measure_induct_rule[where f = V])
+     (use assms in \<open>auto intro: while.domintros\<close>)
+
+lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def)
+
+termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def)
+declare reverse_endianness_list.simps[simp del]
+declare take_list_def[simp]
+declare drop_list_def[simp]
+
+function take_chunks :: "nat \<Rightarrow> 'a list \<Rightarrow> 'a list list" where
+  "take_chunks n [] = []"
+| "take_chunks 0 xs = []"
+| "take_chunks n xs = take n xs # take_chunks n (drop n xs)" if "n > 0" and "xs \<noteq> []"
+  by auto blast
+termination by lexicographic_order
+
+lemma take_chunks_length_leq_n: "length xs \<le> n \<Longrightarrow> xs \<noteq> [] \<Longrightarrow> take_chunks n xs = [xs]"
+  by (cases n) auto
+
+lemma take_chunks_append: "n dvd length a \<Longrightarrow> take_chunks n (a @ b) = take_chunks n a @ take_chunks n b"
+  by (induction n a rule: take_chunks.induct) (auto simp: dvd_imp_le)
+
+lemma Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x"
+  by auto
+
+lemma byte_chunks_take_chunks_8:
+  assumes "8 dvd length xs"
+  shows "byte_chunks xs = Some (take_chunks 8 xs)"
+proof -
+  have Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x" for x
+    by auto
+  from assms show ?thesis
+    by (induction xs rule: byte_chunks.induct) (auto simp: Suc8_plus8 nat_dvd_not_less)
+qed
+
+lemma reverse_endianness_list_rev_take_chunks:
+  "reverse_endianness_list bits = List.concat (rev (take_chunks 8 bits))"
+  by (induction "8 :: nat" bits rule: take_chunks.induct)
+     (auto simp: reverse_endianness_list.simps)
+
+lemma reverse_endianness_list_simps:
+  "length bits \<le> 8 \<Longrightarrow> reverse_endianness_list bits = bits"
+  "length bits > 8 \<Longrightarrow> reverse_endianness_list bits = reverse_endianness_list (drop 8 bits) @ take 8 bits"
+  by (cases bits; auto simp: reverse_endianness_list_rev_take_chunks)+
+
+lemma reverse_endianness_list_append:
+  assumes "8 dvd length a"
+  shows "reverse_endianness_list (a @ b) = reverse_endianness_list b @ reverse_endianness_list a"
+  using assms by (auto simp: reverse_endianness_list_rev_take_chunks take_chunks_append)
+
+lemma length_reverse_endianness_list[simp]:
+  "length (reverse_endianness_list l) = length l"
+  by (induction l rule: reverse_endianness_list.induct) (auto simp: reverse_endianness_list.simps)
+
+lemma reverse_endianness_list_take_8[simp]:
+  "reverse_endianness_list (take 8 bits) = take 8 bits"
+  by (auto simp: reverse_endianness_list_simps)
+
+lemma reverse_reverse_endianness_list[simp]:
+  assumes "8 dvd length l"
+  shows "reverse_endianness_list (reverse_endianness_list l) = l"
+proof (use assms in \<open>induction l rule: reverse_endianness_list.induct[case_names Step]\<close>)
+  case (Step bits)
+  then show ?case
+    by (auto simp: reverse_endianness_list.simps[of bits] reverse_endianness_list_append)
+qed
+
+declare repeat.simps[simp del]
+
+lemma length_repeat[simp]: "length (repeat xs n) = nat n * length xs"
+proof (induction xs n rule: repeat.induct[case_names Step])
+  case (Step xs n)
+  then show ?case unfolding repeat.simps[of xs n]
+    by (auto simp del: mult_Suc simp: mult_Suc[symmetric])
+qed
+
+lemma nth_repeat:
+  assumes "i < nat n * length xs"
+  shows "repeat xs n ! i = xs ! (i mod length xs)"
+proof (use assms in \<open>induction xs n arbitrary: i rule: repeat.induct[case_names Step]\<close>)
+  case (Step xs n i)
+  show ?case
+    using Step.prems Step.IH[of "i - length xs"]
+    unfolding repeat.simps[of xs n]
+    by (auto simp: nth_append mod_geq[symmetric] nat_diff_distrib diff_mult_distrib)
+qed
+
+termination index_list
+  by (relation "measure (\<lambda>(i, j, step). nat ((j - i + step) * sgn step))") auto
+
+lemma index_list_Zero[simp]: "index_list i j 0 = []"
+  by auto
+
+lemma index_list_singleton[simp]: "n \<noteq> 0 \<Longrightarrow> index_list i i n = [i]"
+  by auto
+
+lemma index_list_simps:
+  "0 < step \<Longrightarrow> from \<le> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step"
+  "0 < step \<Longrightarrow> from > to \<Longrightarrow> index_list from to step = []"
+  "0 > step \<Longrightarrow> from \<ge> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step"
+  "0 > step \<Longrightarrow> from < to \<Longrightarrow> index_list from to step = []"
+  by auto
+
+lemma index_list_step1_upto[simp]: "index_list i j 1 = [i..j]"
+  by (induction i j "1 :: int" rule: index_list.induct)
+     (auto simp: index_list_simps upto.simps)
+
+lemma length_upto[simp]: "i \<le> j \<Longrightarrow> length [i..j] = nat (j - i + 1)"
+  by (induction i j rule: upto.induct) (auto simp: upto.simps)
+
+lemma nth_upto[simp]: "i + int n \<le> j \<Longrightarrow> [i..j] ! n = i + int n"
+  by (induction i j arbitrary: n rule: upto.induct)
+     (auto simp: upto.simps nth_Cons split: nat.splits)
+
+declare index_list.simps[simp del]
+
+lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto
+
+lemma just_list_None_iff[simp]: "just_list xs = None \<longleftrightarrow> None \<in> set xs"
+  by (induction xs) (auto split: option.splits)
+
+lemma just_list_None_member_None: "None \<in> set xs \<Longrightarrow> just_list xs = None"
+  by auto
+
+lemma just_list_Some_iff[simp]: "just_list xs = Some ys \<longleftrightarrow> xs = map Some ys"
+  by (induction xs arbitrary: ys) (auto split: option.splits)
+
+lemma just_list_cases:
+  assumes "just_list xs = y"
+  obtains (None) "None \<in> set xs" and "y = None"
+        | (Some) ys where "xs = map Some ys" and "y = Some ys"
+  using assms by (cases y) auto
+
+lemma repeat_singleton_replicate[simp]:
+  "repeat [x] n = replicate (nat n) x"
+proof (induction n)
+  case (nonneg n)
+  have "nat (1 + int m) = Suc m" for m by auto
+  then show ?case by (induction n) (auto simp: repeat.simps)
+next
+  case (neg n)
+  then show ?case by (auto simp: repeat.simps)
+qed
+
+lemma bool_of_bitU_simps[simp]:
+  "bool_of_bitU B0 = Some False"
+  "bool_of_bitU B1 = Some True"
+  "bool_of_bitU BU = None"
+  by (auto simp: bool_of_bitU_def)
+
+lemma bitops_bitU_of_bool[simp]:
+  "and_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<and> y)"
+  "or_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<or> y)"
+  "xor_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool ((x \<or> y) \<and> \<not>(x \<and> y))"
+  "not_bit (bitU_of_bool x) = bitU_of_bool (\<not>x)"
+  "not_bit \<circ> bitU_of_bool = bitU_of_bool \<circ> Not"
+  by (auto simp: bitU_of_bool_def not_bit_def)
+
+lemma image_bitU_of_bool_B0_B1: "bitU_of_bool ` bs \<subseteq> {B0, B1}"
+  by (auto simp: bitU_of_bool_def split: if_splits)
+
+lemma bool_of_bitU_bitU_of_bool[simp]:
+  "bool_of_bitU \<circ> bitU_of_bool = Some"
+  "bool_of_bitU \<circ> (bitU_of_bool \<circ> f) = Some \<circ> f"
+  "bool_of_bitU (bitU_of_bool x) = Some x"
+  by (intro ext, auto simp: bool_of_bitU_def bitU_of_bool_def)+
+
+abbreviation "BC_bitU_list \<equiv> instance_Sail2_values_Bitvector_list_dict instance_Sail2_values_BitU_Sail2_values_bitU_dict"
+lemmas BC_bitU_list_def = instance_Sail2_values_Bitvector_list_dict_def instance_Sail2_values_BitU_Sail2_values_bitU_dict_def
+abbreviation "BC_mword \<equiv> instance_Sail2_values_Bitvector_Machine_word_mword_dict"
+lemmas BC_mword_defs = instance_Sail2_values_Bitvector_Machine_word_mword_dict_def
+  access_mword_def access_mword_inc_def access_mword_dec_def
+  (*update_mword_def update_mword_inc_def update_mword_dec_def*)
+  subrange_list_def subrange_list_inc_def subrange_list_dec_def
+  update_subrange_list_def update_subrange_list_inc_def update_subrange_list_dec_def
+
+declare size_itself_int_def[simp]
+declare size_itself_def[simp]
+declare word_size[simp]
+
+lemma int_of_mword_simps[simp]:
+  "int_of_mword False w = uint w"
+  "int_of_mword True w = sint w"
+  "int_of_bv BC_mword False w = Some (uint w)"
+  "int_of_bv BC_mword True w = Some (sint w)"
+  by (auto simp: int_of_mword_def int_of_bv_def BC_mword_defs)
+
+lemma BC_mword_simps[simp]:
+  "unsigned_method BC_mword a = Some (uint a)"
+  "signed_method BC_mword a = Some (sint a)"
+  "length_method BC_mword (a :: ('a :: len) word) = int (LENGTH('a))"
+  by (auto simp: BC_mword_defs)
+
+lemma of_bits_mword_of_bl[simp]:
+  assumes "just_list (map bool_of_bitU bus) = Some bs"
+  shows "of_bits_method BC_mword bus = Some (of_bl bs)"
+    and "of_bits_failwith BC_mword bus = of_bl bs"
+  using assms by (auto simp: BC_mword_defs of_bits_failwith_def maybe_failwith_def)
+
+lemma nat_of_bits_aux_bl_to_bin_aux:
+  "nat_of_bools_aux acc bs = nat (bl_to_bin_aux bs (int acc))"
+  by (induction acc bs rule: nat_of_bools_aux.induct)
+     (auto simp: Bit_def intro!: arg_cong[where f = nat] arg_cong2[where f = bl_to_bin_aux] split: if_splits)
+
+lemma nat_of_bits_bl_to_bin[simp]:
+  "nat_of_bools bs = nat (bl_to_bin bs)"
+  by (auto simp: nat_of_bools_def bl_to_bin_def nat_of_bits_aux_bl_to_bin_aux)
+
+lemma unsigned_bits_of_mword[simp]:
+  "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)"
+  by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def)
+
+definition mem_bytes_of_word :: "'a::len word \<Rightarrow> bitU list list" where
+  "mem_bytes_of_word w = rev (take_chunks 8 (map bitU_of_bool (to_bl w)))"
+
+lemma mem_bytes_of_bits_mem_bytes_of_word[simp]:
+  assumes "8 dvd LENGTH('a)"
+  shows "mem_bytes_of_bits BC_mword (w :: 'a::len word) = Some (mem_bytes_of_word w)"
+  using assms
+  by (auto simp: mem_bytes_of_bits_def bytes_of_bits_def BC_mword_defs byte_chunks_take_chunks_8 mem_bytes_of_word_def)
+
+lemma bits_of_bitU_list[simp]:
+  "bits_of_method BC_bitU_list v = v"
+  "of_bits_method BC_bitU_list v = Some v"
+  by (auto simp: BC_bitU_list_def)
+
+lemma subrange_list_inc_drop_take:
+  "subrange_list_inc xs i j = drop (nat i) (take (nat (j + 1)) xs)"
+  by (auto simp: subrange_list_inc_def split_at_def)
+
+lemma subrange_list_dec_drop_take:
+  assumes "i \<ge> 0" and "j \<ge> 0"
+  shows "subrange_list_dec xs i j = drop (length xs - nat (i + 1)) (take (length xs - nat j) xs)"
+  using assms unfolding subrange_list_dec_def
+  by (auto simp: subrange_list_inc_drop_take add.commute diff_diff_add nat_minus_as_int)
+
+lemma update_subrange_list_inc_drop_take:
+  assumes "i \<ge> 0" and "j \<ge> i"
+  shows "update_subrange_list_inc xs i j xs' = take (nat i) xs @ xs' @ drop (nat (j + 1)) xs"
+  using assms unfolding update_subrange_list_inc_def
+  by (auto simp: split_at_def min_def)
+
+lemma update_subrange_list_dec_drop_take:
+  assumes "j \<ge> 0" and "i \<ge> j"
+  shows "update_subrange_list_dec xs i j xs' = take (length xs - nat (i + 1)) xs @ xs' @ drop (length xs - nat j) xs"
+  using assms unfolding update_subrange_list_dec_def update_subrange_list_inc_def
+  by (auto simp: split_at_def min_def Let_def add.commute diff_diff_add nat_minus_as_int)
+
+declare access_list_inc_def[simp]
+
+lemma access_list_dec_rev_nth:
+  assumes "0 \<le> i" and "nat i < length xs"
+  shows "access_list_dec xs i = rev xs ! (nat i)"
+  using assms
+  by (auto simp: access_list_dec_def rev_nth intro!: arg_cong2[where f = List.nth])
+
+lemma access_bv_dec_mword[simp]:
+  fixes w :: "('a::len) word"
+  assumes "0 \<le> n" and "nat n < LENGTH('a)"
+  shows "access_bv_dec BC_mword w n = bitU_of_bool (w !! (nat n))"
+  using assms unfolding access_bv_dec_def access_list_def
+  by (auto simp: access_list_dec_rev_nth BC_mword_defs rev_map test_bit_bl)
+
+lemma access_list_dec_nth[simp]:
+  assumes "0 \<le> i"
+  shows "access_list_dec xs i = xs ! (length xs - nat (i + 1))"
+  using assms
+  by (auto simp: access_list_dec_def add.commute diff_diff_add nat_minus_as_int)
+
+lemma update_list_inc_update[simp]:
+  "update_list_inc xs n x = xs[nat n := x]"
+  by (auto simp: update_list_inc_def)
+
+lemma update_list_dec_update[simp]:
+  "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]"
+  by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int)
+
+lemma update_list_dec_update_rev:
+  "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> update_list_dec xs n x = rev ((rev xs)[nat n := x])"
+  by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int rev_update)
+
+lemma access_list_dec_update_list_dec[simp]:
+  "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> access_list_dec (update_list_dec xs n x) n = x"
+  by (auto simp: access_list_dec_rev_nth update_list_dec_update_rev)
+
+lemma bools_of_nat_aux_simps[simp]:
+  "\<And>len. len \<le> 0 \<Longrightarrow> bools_of_nat_aux len x acc = acc"
+  "\<And>len. bools_of_nat_aux (int (Suc len)) x acc =
+     bools_of_nat_aux (int len) (x div 2) ((if x mod 2 = 1 then True else False) # acc)"
+  by auto
+declare bools_of_nat_aux.simps[simp del]
+
+lemma bools_of_nat_aux_bin_to_bl_aux:
+  "bools_of_nat_aux len n acc = bin_to_bl_aux (nat len) (int n) acc"
+proof (cases len)
+  case (nonneg len')
+  show ?thesis unfolding nonneg
+  proof (induction len' arbitrary: n acc)
+    case (Suc len'' n acc)
+    then show ?case
+      using zmod_int[of n 2]
+      by (auto simp del: of_nat_simps simp add: bin_rest_def bin_last_def zdiv_int)
+  qed auto
+qed auto
+
+lemma bools_of_nat_bin_to_bl[simp]:
+  "bools_of_nat len n = bin_to_bl (nat len) (int n)"
+  by (auto simp: bools_of_nat_def bools_of_nat_aux_bin_to_bl_aux)
+
+lemma add_one_bool_ignore_overflow_aux_rbl_succ[simp]:
+  "add_one_bool_ignore_overflow_aux xs = rbl_succ xs"
+  by (induction xs) auto
+
+lemma add_one_bool_ignore_overflow_rbl_succ[simp]:
+  "add_one_bool_ignore_overflow xs = rev (rbl_succ (rev xs))"
+  unfolding add_one_bool_ignore_overflow_def by auto
+
+lemma map_Not_bin_to_bl:
+  "map Not (bin_to_bl_aux len n acc) = bin_to_bl_aux len (-n - 1) (map Not acc)"
+proof (induction len arbitrary: n acc)
+  case (Suc len n acc)
+  moreover have "(- (n div 2) - 1) = ((-n - 1) div 2)" by auto
+  moreover have "(n mod 2 = 0) = ((- n - 1) mod 2 = 1)" by presburger
+  ultimately show ?case by (auto simp: bin_rest_def bin_last_def)
+qed auto
+
+lemma bools_of_int_bin_to_bl[simp]:
+  "bools_of_int len n = bin_to_bl (nat len) n"
+  by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def])
+
+end
diff --git a/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy b/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy
deleted file mode 100644
index 088ff4a8..00000000
--- a/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy
+++ /dev/null
@@ -1,494 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.\<close>
-
-theory "Sail_instr_kinds" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-
-begin 
-
-(*========================================================================*)
-(*     Sail                                                               *)
-(*                                                                        *)
-(*  Copyright (c) 2013-2017                                               *)
-(*    Kathyrn Gray                                                        *)
-(*    Shaked Flur                                                         *)
-(*    Stephen Kell                                                        *)
-(*    Gabriel Kerneis                                                     *)
-(*    Robert Norton-Wright                                                *)
-(*    Christopher Pulte                                                   *)
-(*    Peter Sewell                                                        *)
-(*    Alasdair Armstrong                                                  *)
-(*    Brian Campbell                                                      *)
-(*    Thomas Bauereiss                                                    *)
-(*    Anthony Fox                                                         *)
-(*    Jon French                                                          *)
-(*    Dominic Mulligan                                                    *)
-(*    Stephen Kell                                                        *)
-(*    Mark Wassell                                                        *)
-(*                                                                        *)
-(*  All rights reserved.                                                  *)
-(*                                                                        *)
-(*  This software was developed by the University of Cambridge Computer   *)
-(*  Laboratory as part of the Rigorous Engineering of Mainstream Systems  *)
-(*  (REMS) project, funded by EPSRC grant EP/K008528/1.                   *)
-(*                                                                        *)
-(*  Redistribution and use in source and binary forms, with or without    *)
-(*  modification, are permitted provided that the following conditions    *)
-(*  are met:                                                              *)
-(*  1. Redistributions of source code must retain the above copyright     *)
-(*     notice, this list of conditions and the following disclaimer.      *)
-(*  2. Redistributions in binary form must reproduce the above copyright  *)
-(*     notice, this list of conditions and the following disclaimer in    *)
-(*     the documentation and/or other materials provided with the         *)
-(*     distribution.                                                      *)
-(*                                                                        *)
-(*  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''    *)
-(*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     *)
-(*  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A       *)
-(*  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR   *)
-(*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,          *)
-(*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      *)
-(*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF      *)
-(*  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   *)
-(*  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,    *)
-(*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    *)
-(*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    *)
-(*  SUCH DAMAGE.                                                          *)
-(*========================================================================*)
-
-(*open import Pervasives_extra*)
-
-
-record 'a EnumerationType_class= 
-
-  toNat_method ::" 'a \<Rightarrow> nat "
-
-
-
-
-(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*)
-definition enumeration_typeCompare  :: " 'a EnumerationType_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering "  where 
-     " enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a e1 e2 = (
-  (genericCompare (op<) (op=) (
-  (toNat_method   dict_Sail_instr_kinds_EnumerationType_a) e1) ((toNat_method   dict_Sail_instr_kinds_EnumerationType_a) e2)))"
-
-
-
-definition instance_Basic_classes_Ord_var_dict  :: " 'a EnumerationType_class \<Rightarrow> 'a Ord_class "  where 
-     " instance_Basic_classes_Ord_var_dict dict_Sail_instr_kinds_EnumerationType_a = ((|
-
-  compare_method = 
-  (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a),
-
-  isLess_method = (\<lambda>  r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LT),
-
-  isLessEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) \<noteq> GT),
-
-  isGreater_method = (\<lambda>  r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GT),
-
-  isGreaterEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare 
-  dict_Sail_instr_kinds_EnumerationType_a r1 r2) \<noteq> LT)|) )"
-
-
-
-(* Data structures for building up instructions *)
-
-(* careful: changes in the read/write/barrier kinds have to be
-   reflected in deep_shallow_convert *)
-datatype read_kind =
-  (* common reads *)
-    Read_plain
-  (* Power reads *)
-  | Read_reserve
-  (* AArch64 reads *)
-  | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
-  (* RISC-V reads *)
-  | Read_RISCV_acquire  | Read_RISCV_strong_acquire
-  | Read_RISCV_reserved | Read_RISCV_reserved_acquire
-  | Read_RISCV_reserved_strong_acquire
-  (* x86 reads *)
-  | Read_X86_locked (* the read part of a lock'd instruction (rmw) *)
-
-definition instance_Show_Show_Sail_instr_kinds_read_kind_dict  :: "(read_kind)Show_class "  where 
-     " instance_Show_Show_Sail_instr_kinds_read_kind_dict = ((|
-
-  show_method = (\<lambda>x .  
-  (case  x of
-        Read_plain => (''Read_plain'')
-    | Read_reserve => (''Read_reserve'')
-    | Read_acquire => (''Read_acquire'')
-    | Read_exclusive => (''Read_exclusive'')
-    | Read_exclusive_acquire => (''Read_exclusive_acquire'')
-    | Read_stream => (''Read_stream'')
-    | Read_RISCV_acquire => (''Read_RISCV_acquire'')
-    | Read_RISCV_strong_acquire => (''Read_RISCV_strong_acquire'')
-    | Read_RISCV_reserved => (''Read_RISCV_reserved'')
-    | Read_RISCV_reserved_acquire => (''Read_RISCV_reserved_acquire'')
-    | Read_RISCV_reserved_strong_acquire => (''Read_RISCV_reserved_strong_acquire'')
-    | Read_X86_locked => (''Read_X86_locked'')
-  ))|) )"
-
-
-datatype write_kind =
-  (* common writes *)
-    Write_plain
-  (* Power writes *)
-  | Write_conditional
-  (* AArch64 writes *)
-  | Write_release | Write_exclusive | Write_exclusive_release
-  (* RISC-V *)
-  | Write_RISCV_release     | Write_RISCV_strong_release
-  | Write_RISCV_conditional | Write_RISCV_conditional_release
-  | Write_RISCV_conditional_strong_release
-  (* x86 writes *)
-  | Write_X86_locked (* the write part of a lock'd instruction (rmw) *)
-
-definition instance_Show_Show_Sail_instr_kinds_write_kind_dict  :: "(write_kind)Show_class "  where 
-     " instance_Show_Show_Sail_instr_kinds_write_kind_dict = ((|
-
-  show_method = (\<lambda>x .  
-  (case  x of
-        Write_plain => (''Write_plain'')
-    | Write_conditional => (''Write_conditional'')
-    | Write_release => (''Write_release'')
-    | Write_exclusive => (''Write_exclusive'')
-    | Write_exclusive_release => (''Write_exclusive_release'')
-    | Write_RISCV_release => (''Write_RISCV_release'')
-    | Write_RISCV_strong_release => (''Write_RISCV_strong_release'')
-    | Write_RISCV_conditional => (''Write_RISCV_conditional'')
-    | Write_RISCV_conditional_release => (''Write_RISCV_conditional_release'')
-    | Write_RISCV_conditional_strong_release => (''Write_RISCV_conditional_strong_release'')
-    | Write_X86_locked => (''Write_X86_locked'')
-  ))|) )"
-
-
-datatype barrier_kind =
-  (* Power barriers *)
-  Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
-  (* AArch64 barriers *)
-  | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
-  | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
-  | Barrier_TM_COMMIT
-  (* MIPS barriers *)
-  | Barrier_MIPS_SYNC
-  (* RISC-V barriers *)
-  | Barrier_RISCV_rw_rw
-  | Barrier_RISCV_r_rw
-  | Barrier_RISCV_r_r
-  | Barrier_RISCV_rw_w
-  | Barrier_RISCV_w_w
-  | Barrier_RISCV_i
-  (* X86 *)
-  | Barrier_x86_MFENCE
-
-
-definition instance_Show_Show_Sail_instr_kinds_barrier_kind_dict  :: "(barrier_kind)Show_class "  where 
-     " instance_Show_Show_Sail_instr_kinds_barrier_kind_dict = ((|
-
-  show_method = (\<lambda>x .  
-  (case  x of
-        Barrier_Sync => (''Barrier_Sync'')
-    | Barrier_LwSync => (''Barrier_LwSync'')
-    | Barrier_Eieio => (''Barrier_Eieio'')
-    | Barrier_Isync => (''Barrier_Isync'')
-    | Barrier_DMB => (''Barrier_DMB'')
-    | Barrier_DMB_ST => (''Barrier_DMB_ST'')
-    | Barrier_DMB_LD => (''Barrier_DMB_LD'')
-    | Barrier_DSB => (''Barrier_DSB'')
-    | Barrier_DSB_ST => (''Barrier_DSB_ST'')
-    | Barrier_DSB_LD => (''Barrier_DSB_LD'')
-    | Barrier_ISB => (''Barrier_ISB'')
-    | Barrier_TM_COMMIT => (''Barrier_TM_COMMIT'')
-    | Barrier_MIPS_SYNC => (''Barrier_MIPS_SYNC'')
-    | Barrier_RISCV_rw_rw => (''Barrier_RISCV_rw_rw'')
-    | Barrier_RISCV_r_rw => (''Barrier_RISCV_r_rw'')
-    | Barrier_RISCV_r_r => (''Barrier_RISCV_r_r'')
-    | Barrier_RISCV_rw_w => (''Barrier_RISCV_rw_w'')
-    | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'')
-    | Barrier_RISCV_i => (''Barrier_RISCV_i'')
-    | Barrier_x86_MFENCE => (''Barrier_x86_MFENCE'')
-  ))|) )"
-
-
-datatype trans_kind =
-  (* AArch64 *)
-    Transaction_start | Transaction_commit | Transaction_abort
-
-definition instance_Show_Show_Sail_instr_kinds_trans_kind_dict  :: "(trans_kind)Show_class "  where 
-     " instance_Show_Show_Sail_instr_kinds_trans_kind_dict = ((|
-
-  show_method = (\<lambda>x .  
-  (case  x of
-        Transaction_start => (''Transaction_start'')
-    | Transaction_commit => (''Transaction_commit'')
-    | Transaction_abort => (''Transaction_abort'')
-  ))|) )"
-
-
-datatype instruction_kind =
-    IK_barrier   " barrier_kind "
-  | IK_mem_read  " read_kind "
-  | IK_mem_write " write_kind "
-  | IK_mem_rmw   " (read_kind * write_kind)"
-  | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
-  indirect/computed-branch (single nia of kind NIA_indirect_address)
-  and branch/jump (single nia of kind NIA_concrete_address) *)
-  | IK_trans     " trans_kind "
-  | IK_simple
-
-
-definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict  :: "(instruction_kind)Show_class "  where 
-     " instance_Show_Show_Sail_instr_kinds_instruction_kind_dict = ((|
-
-  show_method = (\<lambda>x .  
-  (case  x of
-        IK_barrier barrier_kind => (''IK_barrier '') @
-                                     (((\<lambda>x .  (case  x of
-                                                            Barrier_Sync => 
-                                                      (''Barrier_Sync'')
-                                                        | Barrier_LwSync => 
-                                                      (''Barrier_LwSync'')
-                                                        | Barrier_Eieio => 
-                                                      (''Barrier_Eieio'')
-                                                        | Barrier_Isync => 
-                                                      (''Barrier_Isync'')
-                                                        | Barrier_DMB => 
-                                                      (''Barrier_DMB'')
-                                                        | Barrier_DMB_ST => 
-                                                      (''Barrier_DMB_ST'')
-                                                        | Barrier_DMB_LD => 
-                                                      (''Barrier_DMB_LD'')
-                                                        | Barrier_DSB => 
-                                                      (''Barrier_DSB'')
-                                                        | Barrier_DSB_ST => 
-                                                      (''Barrier_DSB_ST'')
-                                                        | Barrier_DSB_LD => 
-                                                      (''Barrier_DSB_LD'')
-                                                        | Barrier_ISB => 
-                                                      (''Barrier_ISB'')
-                                                        | Barrier_TM_COMMIT => 
-                                                      (''Barrier_TM_COMMIT'')
-                                                        | Barrier_MIPS_SYNC => 
-                                                      (''Barrier_MIPS_SYNC'')
-                                                        | Barrier_RISCV_rw_rw => 
-                                                      (''Barrier_RISCV_rw_rw'')
-                                                        | Barrier_RISCV_r_rw => 
-                                                      (''Barrier_RISCV_r_rw'')
-                                                        | Barrier_RISCV_r_r => 
-                                                      (''Barrier_RISCV_r_r'')
-                                                        | Barrier_RISCV_rw_w => 
-                                                      (''Barrier_RISCV_rw_w'')
-                                                        | Barrier_RISCV_w_w => 
-                                                      (''Barrier_RISCV_w_w'')
-                                                        | Barrier_RISCV_i => 
-                                                      (''Barrier_RISCV_i'')
-                                                        | Barrier_x86_MFENCE => 
-                                                      (''Barrier_x86_MFENCE'')
-                                                      )) barrier_kind))
-    | IK_mem_read read_kind => (''IK_mem_read '') @
-                                 (((\<lambda>x .  (case  x of
-                                                        Read_plain => 
-                                                  (''Read_plain'')
-                                                    | Read_reserve => 
-                                                  (''Read_reserve'')
-                                                    | Read_acquire => 
-                                                  (''Read_acquire'')
-                                                    | Read_exclusive => 
-                                                  (''Read_exclusive'')
-                                                    | Read_exclusive_acquire => 
-                                                  (''Read_exclusive_acquire'')
-                                                    | Read_stream => 
-                                                  (''Read_stream'')
-                                                    | Read_RISCV_acquire => 
-                                                  (''Read_RISCV_acquire'')
-                                                    | Read_RISCV_strong_acquire => 
-                                                  (''Read_RISCV_strong_acquire'')
-                                                    | Read_RISCV_reserved => 
-                                                  (''Read_RISCV_reserved'')
-                                                    | Read_RISCV_reserved_acquire => 
-                                                  (''Read_RISCV_reserved_acquire'')
-                                                    | Read_RISCV_reserved_strong_acquire => 
-                                                  (''Read_RISCV_reserved_strong_acquire'')
-                                                    | Read_X86_locked => 
-                                                  (''Read_X86_locked'')
-                                                  )) read_kind))
-    | IK_mem_write write_kind => (''IK_mem_write '') @
-                                   (((\<lambda>x .  (case  x of
-                                                          Write_plain => 
-                                                    (''Write_plain'')
-                                                      | Write_conditional => 
-                                                    (''Write_conditional'')
-                                                      | Write_release => 
-                                                    (''Write_release'')
-                                                      | Write_exclusive => 
-                                                    (''Write_exclusive'')
-                                                      | Write_exclusive_release => 
-                                                    (''Write_exclusive_release'')
-                                                      | Write_RISCV_release => 
-                                                    (''Write_RISCV_release'')
-                                                      | Write_RISCV_strong_release => 
-                                                    (''Write_RISCV_strong_release'')
-                                                      | Write_RISCV_conditional => 
-                                                    (''Write_RISCV_conditional'')
-                                                      | Write_RISCV_conditional_release => 
-                                                    (''Write_RISCV_conditional_release'')
-                                                      | Write_RISCV_conditional_strong_release => 
-                                                    (''Write_RISCV_conditional_strong_release'')
-                                                      | Write_X86_locked => 
-                                                    (''Write_X86_locked'')
-                                                    )) write_kind))
-    | IK_mem_rmw (r, w) => (''IK_mem_rmw '') @
-                             ((((\<lambda>x .  (case  x of
-                                                     Read_plain => (''Read_plain'')
-                                                 | Read_reserve => (''Read_reserve'')
-                                                 | Read_acquire => (''Read_acquire'')
-                                                 | Read_exclusive => 
-                                               (''Read_exclusive'')
-                                                 | Read_exclusive_acquire => 
-                                               (''Read_exclusive_acquire'')
-                                                 | Read_stream => (''Read_stream'')
-                                                 | Read_RISCV_acquire => 
-                                               (''Read_RISCV_acquire'')
-                                                 | Read_RISCV_strong_acquire => 
-                                               (''Read_RISCV_strong_acquire'')
-                                                 | Read_RISCV_reserved => 
-                                               (''Read_RISCV_reserved'')
-                                                 | Read_RISCV_reserved_acquire => 
-                                               (''Read_RISCV_reserved_acquire'')
-                                                 | Read_RISCV_reserved_strong_acquire => 
-                                               (''Read_RISCV_reserved_strong_acquire'')
-                                                 | Read_X86_locked => 
-                                               (''Read_X86_locked'')
-                                               )) r)) @
-                                (('' '') @
-                                   (((\<lambda>x .  (case  x of
-                                                          Write_plain => 
-                                                    (''Write_plain'')
-                                                      | Write_conditional => 
-                                                    (''Write_conditional'')
-                                                      | Write_release => 
-                                                    (''Write_release'')
-                                                      | Write_exclusive => 
-                                                    (''Write_exclusive'')
-                                                      | Write_exclusive_release => 
-                                                    (''Write_exclusive_release'')
-                                                      | Write_RISCV_release => 
-                                                    (''Write_RISCV_release'')
-                                                      | Write_RISCV_strong_release => 
-                                                    (''Write_RISCV_strong_release'')
-                                                      | Write_RISCV_conditional => 
-                                                    (''Write_RISCV_conditional'')
-                                                      | Write_RISCV_conditional_release => 
-                                                    (''Write_RISCV_conditional_release'')
-                                                      | Write_RISCV_conditional_strong_release => 
-                                                    (''Write_RISCV_conditional_strong_release'')
-                                                      | Write_X86_locked => 
-                                                    (''Write_X86_locked'')
-                                                    )) w))))
-    | IK_branch => (''IK_branch'')
-    | IK_trans trans_kind => (''IK_trans '') @
-                               (((\<lambda>x .  (case  x of
-                                                      Transaction_start => 
-                                                (''Transaction_start'')
-                                                  | Transaction_commit => 
-                                                (''Transaction_commit'')
-                                                  | Transaction_abort => 
-                                                (''Transaction_abort'')
-                                                )) trans_kind))
-    | IK_simple => (''IK_simple'')
-  ))|) )"
-
-
-
-definition read_is_exclusive  :: " read_kind \<Rightarrow> bool "  where 
-     " read_is_exclusive = ( \<lambda>x .  
-  (case  x of
-        Read_plain => False
-    | Read_reserve => True
-    | Read_acquire => False
-    | Read_exclusive => True
-    | Read_exclusive_acquire => True
-    | Read_stream => False
-    | Read_RISCV_acquire => False
-    | Read_RISCV_strong_acquire => False
-    | Read_RISCV_reserved => True
-    | Read_RISCV_reserved_acquire => True
-    | Read_RISCV_reserved_strong_acquire => True
-    | Read_X86_locked => True
-  ) )"
-
-
-
-
-definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict  :: "(read_kind)EnumerationType_class "  where 
-     " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict = ((|
-
-  toNat_method = (\<lambda>x .  
-  (case  x of
-        Read_plain =>( 0 :: nat)
-    | Read_reserve =>( 1 :: nat)
-    | Read_acquire =>( 2 :: nat)
-    | Read_exclusive =>( 3 :: nat)
-    | Read_exclusive_acquire =>( 4 :: nat)
-    | Read_stream =>( 5 :: nat)
-    | Read_RISCV_acquire =>( 6 :: nat)
-    | Read_RISCV_strong_acquire =>( 7 :: nat)
-    | Read_RISCV_reserved =>( 8 :: nat)
-    | Read_RISCV_reserved_acquire =>( 9 :: nat)
-    | Read_RISCV_reserved_strong_acquire =>( 10 :: nat)
-    | Read_X86_locked =>( 11 :: nat)
-  ))|) )"
-
-
-definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict  :: "(write_kind)EnumerationType_class "  where 
-     " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict = ((|
-
-  toNat_method = (\<lambda>x .  
-  (case  x of
-        Write_plain =>( 0 :: nat)
-    | Write_conditional =>( 1 :: nat)
-    | Write_release =>( 2 :: nat)
-    | Write_exclusive =>( 3 :: nat)
-    | Write_exclusive_release =>( 4 :: nat)
-    | Write_RISCV_release =>( 5 :: nat)
-    | Write_RISCV_strong_release =>( 6 :: nat)
-    | Write_RISCV_conditional =>( 7 :: nat)
-    | Write_RISCV_conditional_release =>( 8 :: nat)
-    | Write_RISCV_conditional_strong_release =>( 9 :: nat)
-    | Write_X86_locked =>( 10 :: nat)
-  ))|) )"
-
-
-definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict  :: "(barrier_kind)EnumerationType_class "  where 
-     " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict = ((|
-
-  toNat_method = (\<lambda>x .  
-  (case  x of
-        Barrier_Sync =>( 0 :: nat)
-    | Barrier_LwSync =>( 1 :: nat)
-    | Barrier_Eieio =>( 2 :: nat)
-    | Barrier_Isync =>( 3 :: nat)
-    | Barrier_DMB =>( 4 :: nat)
-    | Barrier_DMB_ST =>( 5 :: nat)
-    | Barrier_DMB_LD =>( 6 :: nat)
-    | Barrier_DSB =>( 7 :: nat)
-    | Barrier_DSB_ST =>( 8 :: nat)
-    | Barrier_DSB_LD =>( 9 :: nat)
-    | Barrier_ISB =>( 10 :: nat)
-    | Barrier_TM_COMMIT =>( 11 :: nat)
-    | Barrier_MIPS_SYNC =>( 12 :: nat)
-    | Barrier_RISCV_rw_rw =>( 13 :: nat)
-    | Barrier_RISCV_r_rw =>( 14 :: nat)
-    | Barrier_RISCV_r_r =>( 15 :: nat)
-    | Barrier_RISCV_rw_w =>( 16 :: nat)
-    | Barrier_RISCV_w_w =>( 17 :: nat)
-    | Barrier_RISCV_i =>( 18 :: nat)
-    | Barrier_x86_MFENCE =>( 19 :: nat)
-  ))|) )"
-
-end
diff --git a/snapshots/isabelle/lib/sail/Sail_operators.thy b/snapshots/isabelle/lib/sail/Sail_operators.thy
deleted file mode 100644
index 00b32a85..00000000
--- a/snapshots/isabelle/lib/sail/Sail_operators.thy
+++ /dev/null
@@ -1,326 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators.lem.\<close>
-
-theory "Sail_operators" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Lem_machine_word" 
-	 "Sail_values" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_values*)
-
-(*** Bit vector operations *)
-
-(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*)
-definition concat_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow>(bitU)list "  where 
-     " concat_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r = ( (
-  (bits_of_method   dict_Sail_values_Bitvector_a) l @(bits_of_method   dict_Sail_values_Bitvector_b) r))"
-
-
-(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*)
-definition cons_bv  :: " 'a Bitvector_class \<Rightarrow> bitU \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
-     " cons_bv dict_Sail_values_Bitvector_a b v = ( b # 
-  (bits_of_method   dict_Sail_values_Bitvector_a) v )"
-
-
-(*val cast_unit_bv : bitU -> list bitU*)
-definition cast_unit_bv  :: " bitU \<Rightarrow>(bitU)list "  where 
-     " cast_unit_bv b = ( [b])"
-
-
-(*val bv_of_bit : integer -> bitU -> list bitU*)
-definition bv_of_bit  :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " bv_of_bit len b = ( extz_bits len [b])"
-
-
-definition most_significant  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU "  where 
-     " most_significant dict_Sail_values_Bitvector_a v = ( (case  
-  (bits_of_method   dict_Sail_values_Bitvector_a) v of
-    b # _ => b
-  | _ => B0 (* Treat empty bitvector as all zeros *)
-  ))"
-
-
-definition get_max_representable_in  :: " bool \<Rightarrow> int \<Rightarrow> int "  where 
-     " get_max_representable_in sign (n :: int) = (
-  if (n =( 64 :: int)) then (case  sign of   True => max_64 | False => max_64u )
-  else if (n=( 32 :: int)) then (case  sign of   True => max_32 | False => max_32u )
-  else if (n=( 8 :: int)) then max_8
-  else if (n=( 5 :: int)) then max_5
-  else (case  sign of   True => (( 2 :: int))^ ((nat (abs ( n))) -( 1 :: nat))
-                       | False => (( 2 :: int))^ (nat (abs ( n)))
-       ))"
-
-
-definition get_min_representable_in  :: " 'a \<Rightarrow> int \<Rightarrow> int "  where 
-     " get_min_representable_in _ (n :: int) = (
-  if n =( 64 :: int) then min_64
-  else if n =( 32 :: int) then min_32
-  else if n =( 8 :: int) then min_8
-  else if n =( 5 :: int) then min_5
-  else( 0 :: int) - ((( 2 :: int))^ (nat (abs ( n)))))"
-
-
-(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
-definition arith_op_bv_int  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'a "  where 
-     " arith_op_bv_int dict_Sail_values_Bitvector_a op1 sign l r = (
-  (let r' = ((of_int_method   dict_Sail_values_Bitvector_a) ((length_method   dict_Sail_values_Bitvector_a) l) r) in (arith_op_bv_method   dict_Sail_values_Bitvector_a) op1 sign l r'))"
-
-
-(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
-definition arith_op_int_bv  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a "  where 
-     " arith_op_int_bv dict_Sail_values_Bitvector_a op1 sign l r = (
-  (let l' = ((of_int_method   dict_Sail_values_Bitvector_a) ((length_method   dict_Sail_values_Bitvector_a) r) l) in (arith_op_bv_method   dict_Sail_values_Bitvector_a) op1 sign l' r))"
-
-
-definition arith_op_bv_bool  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
-     " arith_op_bv_bool dict_Sail_values_Bitvector_a op1 sign l r = ( arith_op_bv_int 
-  dict_Sail_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))"
-
-definition arith_op_bv_bit  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
-     " arith_op_bv_bit dict_Sail_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a op1 sign l) (bool_of_bitU r))"
-
-
-(* TODO (or just omit and define it per spec if needed)
-val arith_op_overflow_bv : forall 'a. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU)
-let arith_op_overflow_bv op sign size l r =
-  let len = length l in
-  let act_size = len * size in
-  match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with
-    | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) ->
-       let n = op l_sign r_sign in
-       let n_unsign = op l_unsign r_unsign in
-       let correct_size = of_int act_size n in
-       let one_more_size_u = bits_of_int (act_size + 1) n_unsign in
-       let overflow =
-         if n <= get_max_representable_in sign len &&
-              n >= get_min_representable_in sign len
-         then B0 else B1 in
-       let c_out = most_significant one_more_size_u in
-       (correct_size,overflow,c_out)
-    | (_, _, _, _) ->
-       (repeat [BU] act_size, BU, BU)
-  end
-
-let add_overflow_bv = arith_op_overflow_bv integerAdd false 1
-let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1
-let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1
-let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1
-let mult_overflow_bv = arith_op_overflow_bv integerMult false 2
-let mults_overflow_bv = arith_op_overflow_bv integerMult true 2
-
-val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU)
-let arith_op_overflow_bv_bit op sign size l r_bit =
-  let act_size = length l * size in
-  match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with
-    | (Just l', Just l_u, false) ->
-       let (n, nu, changed) = match r_bit with
-         | B1 -> (op l' 1, op l_u 1, true)
-         | B0 -> (l', l_u, false)
-         | BU -> (* unreachable due to check above *)
-            failwith arith_op_overflow_bv_bit applied to undefined bit
-         end in
-       let correct_size = of_int act_size n in
-       let one_larger = bits_of_int (act_size + 1) nu in
-       let overflow =
-         if changed
-         then
-           if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
-           then B0 else B1
-         else B0 in
-       (correct_size, overflow, most_significant one_larger)
-    | (_, _, _) ->
-       (repeat [BU] act_size, BU, BU)
-  end
-
-let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1
-let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1
-let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1
-let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*)
-
-datatype shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot
-
-definition invert_shift  :: " shift \<Rightarrow> shift "  where 
-     " invert_shift = ( \<lambda>x .  
-  (case  x of
-        LL_shift => RR_shift
-    | RR_shift => LL_shift
-    | RR_shift_arith => LL_shift
-    | LL_rot => RR_rot
-    | RR_rot => LL_rot
-  ) )"
-
-
-(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*)
-definition shift_op_bv  :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " shift_op_bv dict_Sail_values_Bitvector_a op1 v n = (
-  (let v = ((bits_of_method   dict_Sail_values_Bitvector_a) v) in
-  if n =( 0 :: int) then v else
-  (let (op1, n) = (if n >( 0 :: int) then (op1, n) else (invert_shift op1, - n)) in
-  (case  op1 of
-    LL_shift =>
-     subrange_list True v n (int (List.length v) -( 1 :: int)) @ repeat [B0] n
-  | RR_shift =>
-     repeat [B0] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int))
-  | RR_shift_arith =>
-     repeat [most_significant 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int))
-  | LL_rot =>
-     subrange_list True v n (int (List.length v) -( 1 :: int)) @ subrange_list True v(( 0 :: int)) (n -( 1 :: int))
-  | RR_rot =>
-     subrange_list False v(( 0 :: int)) (n -( 1 :: int)) @ subrange_list False v n (int (List.length v) -( 1 :: int))
-  ))))"
-
-
-definition shiftl_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " shiftl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv 
-  dict_Sail_values_Bitvector_a LL_shift )"
- (*<<*)
-definition shiftr_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv 
-  dict_Sail_values_Bitvector_a RR_shift )"
- (*>>*)
-definition arith_shiftr_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " arith_shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv 
-  dict_Sail_values_Bitvector_a RR_shift_arith )"
-
-definition rotl_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " rotl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv 
-  dict_Sail_values_Bitvector_a LL_rot )"
- (*<<<*)
-definition rotr_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " rotr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv 
-  dict_Sail_values_Bitvector_a LL_rot )"
- (*>>>*)
-
-definition shiftl_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " shiftl_mword w n = ( w << (nat_of_int n))"
-
-definition shiftr_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " shiftr_mword w n = ( w >> (nat_of_int n))"
-
-definition arith_shiftr_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " arith_shiftr_mword w n = ( w >>> (nat_of_int n))"
-
-definition rotl_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " rotl_mword w n = ( Word.word_rotl (nat_of_int n) w )"
-
-definition rotr_mword  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " rotr_mword w n = ( Word.word_rotr (nat_of_int n) w )"
-
-
-fun  arith_op_no0  :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)option "  where 
-     " arith_op_no0 (op1 :: int \<Rightarrow> int \<Rightarrow> int) l r = (
-  if r =( 0 :: int)
-  then None
-  else Some (op1 l r))"
-
-
-(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
-  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*)
-definition arith_op_bv_no0  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'b option "  where 
-     " arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = (
-  Option.bind (int_of_bv 
-  dict_Sail_values_Bitvector_a sign l) (\<lambda> l' . 
-  Option.bind (int_of_bv 
-  dict_Sail_values_Bitvector_a sign r) (\<lambda> r' . 
-  if r' =( 0 :: int) then None else Some (
-  (of_int_method   dict_Sail_values_Bitvector_b) ((length_method   dict_Sail_values_Bitvector_a) l * size1) (op1 l' r')))))"
-
-
-definition mod_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option "  where 
-     " mod_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))"
-
-definition quot_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option "  where 
-     " quot_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))"
-
-definition quots_bv  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option "  where 
-     " quots_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot True(( 1 :: int)))"
-
-
-definition mod_mword  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " mod_mword = ( (op mod))"
-
-definition quot_mword  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " quot_mword = ( (op div))"
-
-definition quots_mword  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " quots_mword = ( Lem_machine_word.signedDivide )"
-
-
-definition arith_op_bv_int_no0  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b option "  where 
-     " arith_op_bv_int_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = (
-  arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l ((of_int_method   dict_Sail_values_Bitvector_a) ((length_method   dict_Sail_values_Bitvector_a) l) r))"
-
-
-definition quot_bv_int  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option "  where 
-     " quot_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))"
-
-definition mod_bv_int  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option "  where 
-     " mod_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 
-  dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))"
-
-
-definition mod_mword_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " mod_mword_int l r = ( l mod (Word.word_of_int r))"
-
-definition quot_mword_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " quot_mword_int l r = ( l div (Word.word_of_int r))"
-
-definition quots_mword_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " quots_mword_int l r = ( Lem_machine_word.signedDivide l (Word.word_of_int r))"
-
-
-definition replicate_bits_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " replicate_bits_bv dict_Sail_values_Bitvector_a v count1 = ( repeat (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) count1 )"
-
-definition duplicate_bit_bv  :: " 'a BitU_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " duplicate_bit_bv dict_Sail_values_BitU_a bit len = ( replicate_bits_bv 
-  (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len )"
-
-
-(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
-definition eq_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool "  where 
-     " eq_bv dict_Sail_values_Bitvector_a l r = ( (
-  (bits_of_method   dict_Sail_values_Bitvector_a) l =(bits_of_method   dict_Sail_values_Bitvector_a) r))"
-
-
-(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
-definition neq_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool "  where 
-     " neq_bv dict_Sail_values_Bitvector_a l r = ( \<not> (eq_bv 
-  dict_Sail_values_Bitvector_a l r))"
-
-
-(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
-definition get_slice_int_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a "  where 
-     " get_slice_int_bv dict_Sail_values_Bitvector_a len n lo = (
-  (let hi = ((lo + len) -( 1 :: int)) in
-  (let bs = (bools_of_int (hi +( 1 :: int)) n) in 
-  (of_bools_method   dict_Sail_values_Bitvector_a) (subrange_list False bs hi lo))))"
-
-
-(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*)
-definition set_slice_int_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int "  where 
-     " set_slice_int_bv dict_Sail_values_Bitvector_a len n lo v = (
-  (let hi = ((lo + len) -( 1 :: int)) in
-  (let bs = (bits_of_int (hi +( 1 :: int)) n) in
-  maybe_failwith (signed_of_bits (update_subrange_list False bs hi lo (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v))))))"
-
-end
diff --git a/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy b/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy
deleted file mode 100644
index d3d886ed..00000000
--- a/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy
+++ /dev/null
@@ -1,773 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.\<close>
-
-theory "Sail_operators_bitlists" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Lem_machine_word" 
-	 "Sail_values" 
-	 "Sail_operators" 
-	 "Prompt_monad" 
-	 "Prompt" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_values*)
-(*open import Sail_operators*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-
-(* Specialisation of operators to bit lists *)
-
-(*val uint_maybe : list bitU -> maybe integer*)
-definition uint_maybe  :: "(bitU)list \<Rightarrow>(int)option "  where 
-     " uint_maybe v = ( unsigned_of_bits (List.map (\<lambda> b. b) v))"
-
-definition uint_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad "  where 
-     " uint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''uint'') (
-  (unsigned_method   dict_Sail_values_Bitvector_a) v))"
-
-definition uint_oracle  :: "(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
-     " uint_oracle v = (
-  bools_of_bits_oracle v \<bind> (\<lambda> bs . 
-  return (int_of_bools False bs)))"
-
-definition uint  :: "(bitU)list \<Rightarrow> int "  where 
-     " uint v = ( maybe_failwith (uint_maybe v))"
-
-
-(*val sint_maybe : list bitU -> maybe integer*)
-definition sint_maybe  :: "(bitU)list \<Rightarrow>(int)option "  where 
-     " sint_maybe v = ( signed_of_bits (List.map (\<lambda> b. b) v))"
-
-definition sint_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad "  where 
-     " sint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''sint'') (
-  (signed_method   dict_Sail_values_Bitvector_a) v))"
-
-definition sint_oracle  :: "(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
-     " sint_oracle v = (
-  bools_of_bits_oracle v \<bind> (\<lambda> bs . 
-  return (int_of_bools True bs)))"
-
-definition sint  :: "(bitU)list \<Rightarrow> int "  where 
-     " sint v = ( maybe_failwith (sint_maybe v))"
-
-
-(*val extz_vec : integer -> list bitU -> list bitU*)
-definition extz_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " extz_vec = ( 
-  extz_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val exts_vec : integer -> list bitU -> list bitU*)
-definition exts_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " exts_vec = ( 
-  exts_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val zero_extend : list bitU -> integer -> list bitU*)
-definition zero_extend  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " zero_extend bits len = ( extz_bits len bits )"
-
-
-(*val sign_extend : list bitU -> integer -> list bitU*)
-definition sign_extend  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " sign_extend bits len = ( exts_bits len bits )"
-
-
-(*val zeros : integer -> list bitU*)
-definition zeros  :: " int \<Rightarrow>(bitU)list "  where 
-     " zeros len = ( repeat [B0] len )"
-
-
-(*val vector_truncate : list bitU -> integer -> list bitU*)
-definition vector_truncate  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " vector_truncate bs len = ( extz_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) len bs )"
-
-
-(*val vec_of_bits_maybe    : list bitU -> maybe (list bitU)*)
-(*val vec_of_bits_fail     : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
-(*val vec_of_bits_oracle   : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
-(*val vec_of_bits_failwith : list bitU -> list bitU*)
-(*val vec_of_bits          : list bitU -> list bitU*)
-
-(*val access_vec_inc : list bitU -> integer -> bitU*)
-definition access_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_vec_inc = ( 
-  access_bv_inc
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val access_vec_dec : list bitU -> integer -> bitU*)
-definition access_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_vec_dec = ( 
-  access_bv_dec
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*)
-definition update_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " update_vec_inc = ( 
-  update_bv_inc
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition update_vec_inc_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option "  where 
-     " update_vec_inc_maybe v i b = ( Some (update_vec_inc v i b))"
-
-definition update_vec_inc_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " update_vec_inc_fail v i b = ( return (update_vec_inc v i b))"
-
-definition update_vec_inc_oracle  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " update_vec_inc_oracle v i b = ( return (update_vec_inc v i b))"
-
-
-(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*)
-definition update_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " update_vec_dec = ( 
-  update_bv_dec
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition update_vec_dec_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option "  where 
-     " update_vec_dec_maybe v i b = ( Some (update_vec_dec v i b))"
-
-definition update_vec_dec_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " update_vec_dec_fail v i b = ( return (update_vec_dec v i b))"
-
-definition update_vec_dec_oracle  :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " update_vec_dec_oracle v i b = ( return (update_vec_dec v i b))"
-
-
-(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*)
-definition subrange_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " subrange_vec_inc = ( 
-  subrange_bv_inc
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*)
-definition subrange_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " subrange_vec_dec = ( 
-  subrange_bv_dec
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*)
-definition update_subrange_vec_inc  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " update_subrange_vec_inc = ( 
-  update_subrange_bv_inc
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict)
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*)
-definition update_subrange_vec_dec  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " update_subrange_vec_dec = ( 
-  update_subrange_bv_dec
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict)
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val concat_vec : list bitU -> list bitU -> list bitU*)
-definition concat_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " concat_vec = ( 
-  concat_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict)
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val cons_vec : bitU -> list bitU -> list bitU*)
-definition cons_vec  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " cons_vec = ( 
-  cons_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition cons_vec_maybe  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
-     " cons_vec_maybe b v = ( Some (cons_vec b v))"
-
-definition cons_vec_fail  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " cons_vec_fail b v = ( return (cons_vec b v))"
-
-definition cons_vec_oracle  :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " cons_vec_oracle b v = ( return (cons_vec b v))"
-
-
-(*val cast_unit_vec : bitU -> list bitU*)
-definition cast_unit_vec  :: " bitU \<Rightarrow>(bitU)list "  where 
-     " cast_unit_vec = ( cast_unit_bv )"
-
-definition cast_unit_vec_maybe  :: " bitU \<Rightarrow>((bitU)list)option "  where 
-     " cast_unit_vec_maybe b = ( Some (cast_unit_vec b))"
-
-definition cast_unit_vec_fail  :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " cast_unit_vec_fail b = ( return (cast_unit_vec b))"
-
-definition cast_unit_vec_oracle  :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " cast_unit_vec_oracle b = ( return (cast_unit_vec b))"
-
-
-(*val vec_of_bit : integer -> bitU -> list bitU*)
-definition vec_of_bit  :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " vec_of_bit = ( bv_of_bit )"
-
-definition vec_of_bit_maybe  :: " int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option "  where 
-     " vec_of_bit_maybe len b = ( Some (vec_of_bit len b))"
-
-definition vec_of_bit_fail  :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " vec_of_bit_fail len b = ( return (vec_of_bit len b))"
-
-definition vec_of_bit_oracle  :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " vec_of_bit_oracle len b = ( return (vec_of_bit len b))"
-
-
-(*val msb : list bitU -> bitU*)
-definition msb  :: "(bitU)list \<Rightarrow> bitU "  where 
-     " msb = ( 
-  most_significant
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*)
-definition int_of_vec_maybe  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option "  where 
-     " int_of_vec_maybe = ( 
-  int_of_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition int_of_vec_fail  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
-     " int_of_vec_fail sign v = ( maybe_fail (''int_of_vec'') (int_of_vec_maybe sign v))"
-
-definition int_of_vec_oracle  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad "  where 
-     " int_of_vec_oracle sign v = ( bools_of_bits_oracle v \<bind> (\<lambda> v .  return (int_of_bools sign v)))"
-
-definition int_of_vec  :: " bool \<Rightarrow>(bitU)list \<Rightarrow> int "  where 
-     " int_of_vec sign v = ( maybe_failwith (int_of_vec_maybe sign v))"
-
-
-(*val string_of_vec : list bitU -> string*)
-definition string_of_vec  :: "(bitU)list \<Rightarrow> string "  where 
-     " string_of_vec = ( 
-  string_of_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val and_vec : list bitU -> list bitU -> list bitU*)
-(*val or_vec  : list bitU -> list bitU -> list bitU*)
-(*val xor_vec : list bitU -> list bitU -> list bitU*)
-(*val not_vec : list bitU -> list bitU*)
-definition and_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " and_vec = ( binop_list and_bit )"
-
-definition or_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
-     " or_vec  = ( binop_list or_bit )"
-
-definition xor_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " xor_vec = ( binop_list xor_bit )"
-
-definition not_vec  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
-     " not_vec = ( List.map not_bit )"
-
-
-(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a =>
-  (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*)
-definition arith_op_double_bl  :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
-     " arith_op_double_bl dict_Sail_values_Bitvector_a op1 sign l r = (
-  (let len =(( 2 :: int) *
-  (length_method   dict_Sail_values_Bitvector_a) l) in
-  (let l' = (if sign then exts_bv 
-  dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in
-  (let r' = (if sign then exts_bv 
-  dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in
-  List.map (\<lambda> b. b) (arith_op_bits op1 sign (List.map (\<lambda> b. b) l') (List.map (\<lambda> b. b) r'))))))"
-
-
-(*val add_vec   : list bitU -> list bitU -> list bitU*)
-(*val adds_vec  : list bitU -> list bitU -> list bitU*)
-(*val sub_vec   : list bitU -> list bitU -> list bitU*)
-(*val subs_vec  : list bitU -> list bitU -> list bitU*)
-(*val mult_vec  : list bitU -> list bitU -> list bitU*)
-(*val mults_vec : list bitU -> list bitU -> list bitU*)
-definition add_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "    where 
-     " add_vec   = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op+) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
-
-definition adds_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
-     " adds_vec  = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op+) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
-
-definition sub_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "    where 
-     " sub_vec   = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op-) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
-
-definition subs_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
-     " subs_vec  = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op-) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
-
-definition mult_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "   where 
-     " mult_vec  = ( arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False )"
-
-definition mults_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " mults_vec = ( arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True )"
-
-
-(*val add_vec_int       : list bitU -> integer -> list bitU*)
-(*val adds_vec_int      : list bitU -> integer -> list bitU*)
-(*val sub_vec_int       : list bitU -> integer -> list bitU*)
-(*val subs_vec_int      : list bitU -> integer -> list bitU*)
-(*val mult_vec_int      : list bitU -> integer -> list bitU*)
-(*val mults_vec_int     : list bitU -> integer -> list bitU*)
-definition add_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " add_vec_int   l r = ( arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )"
-
-definition adds_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " adds_vec_int  l r = ( arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )"
-
-definition sub_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " sub_vec_int   l r = ( arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )"
-
-definition subs_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " subs_vec_int  l r = ( arith_op_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )"
-
-definition mult_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " mult_vec_int  l r = ( arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))"
-
-definition mults_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " mults_vec_int l r = ( arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))"
-
-
-(*val add_int_vec       : integer -> list bitU -> list bitU*)
-(*val adds_int_vec      : integer -> list bitU -> list bitU*)
-(*val sub_int_vec       : integer -> list bitU -> list bitU*)
-(*val subs_int_vec      : integer -> list bitU -> list bitU*)
-(*val mult_int_vec      : integer -> list bitU -> list bitU*)
-(*val mults_int_vec     : integer -> list bitU -> list bitU*)
-definition add_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " add_int_vec   l r = ( arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )"
-
-definition adds_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " adds_int_vec  l r = ( arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )"
-
-definition sub_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " sub_int_vec   l r = ( arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )"
-
-definition subs_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " subs_int_vec  l r = ( arith_op_int_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )"
-
-definition mult_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " mult_int_vec  l r = ( arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )"
-
-definition mults_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " mults_int_vec l r = ( arith_op_double_bl 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )"
-
-
-(*val add_vec_bit      : list bitU -> bitU -> list bitU*)
-(*val adds_vec_bit     : list bitU -> bitU -> list bitU*)
-(*val sub_vec_bit      : list bitU -> bitU -> list bitU*)
-(*val subs_vec_bit     : list bitU -> bitU -> list bitU*)
-
-definition add_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
-     " add_vec_bool dict_Sail_values_Bitvector_a       l r = ( arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (op+) False l r )"
-
-definition add_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
-     " add_vec_bit_maybe dict_Sail_values_Bitvector_a  l r = ( arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (op+) False l r )"
-
-definition add_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " add_vec_bit_fail dict_Sail_values_Bitvector_a   l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe 
-  dict_Sail_values_Bitvector_a l r))"
-
-definition add_vec_bit_oracle  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " add_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (add_vec_bool 
-  dict_Sail_values_Bitvector_a l r)))"
-
-definition add_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " add_vec_bit        l r = ( case_option (repeat [BU] (int (List.length l))) id (add_vec_bit_maybe 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-
-definition adds_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
-     " adds_vec_bool dict_Sail_values_Bitvector_a       l r = ( arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (op+) True l r )"
-
-definition adds_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
-     " adds_vec_bit_maybe dict_Sail_values_Bitvector_a  l r = ( arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (op+) True l r )"
-
-definition adds_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " adds_vec_bit_fail dict_Sail_values_Bitvector_a   l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe 
-  dict_Sail_values_Bitvector_a l r))"
-
-definition adds_vec_bit_oracle  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " adds_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (adds_vec_bool 
-  dict_Sail_values_Bitvector_a l r)))"
-
-definition adds_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " adds_vec_bit        l r = ( case_option (repeat [BU] (int (List.length l))) id (adds_vec_bit_maybe 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-
-definition sub_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
-     " sub_vec_bool dict_Sail_values_Bitvector_a        l r = ( arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (op-) False l r )"
-
-definition sub_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
-     " sub_vec_bit_maybe dict_Sail_values_Bitvector_a   l r = ( arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (op-) False l r )"
-
-definition sub_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " sub_vec_bit_fail dict_Sail_values_Bitvector_a    l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe 
-  dict_Sail_values_Bitvector_a l r))"
-
-definition sub_vec_bit_oracle  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " sub_vec_bit_oracle dict_Sail_values_Bitvector_a  l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (sub_vec_bool 
-  dict_Sail_values_Bitvector_a l r)))"
-
-definition sub_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " sub_vec_bit         l r = ( case_option (repeat [BU] (int (List.length l))) id (sub_vec_bit_maybe 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-
-definition subs_vec_bool  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a "  where 
-     " subs_vec_bool dict_Sail_values_Bitvector_a       l r = ( arith_op_bv_bool 
-  dict_Sail_values_Bitvector_a (op-) True l r )"
-
-definition subs_vec_bit_maybe  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option "  where 
-     " subs_vec_bit_maybe dict_Sail_values_Bitvector_a  l r = ( arith_op_bv_bit 
-  dict_Sail_values_Bitvector_a (op-) True l r )"
-
-definition subs_vec_bit_fail  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " subs_vec_bit_fail dict_Sail_values_Bitvector_a   l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe 
-  dict_Sail_values_Bitvector_a l r))"
-
-definition subs_vec_bit_oracle  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad "  where 
-     " subs_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (subs_vec_bool 
-  dict_Sail_values_Bitvector_a l r)))"
-
-definition subs_vec_bit  :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " subs_vec_bit        l r = ( case_option (repeat [BU] (int (List.length l))) id (subs_vec_bit_maybe 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-
-(*val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val add_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val mult_overflow_vec        : list bitU -> list bitU -> (list bitU * bitU * bitU)
-val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
-let add_overflow_vec         = add_overflow_bv
-let add_overflow_vec_signed  = add_overflow_bv_signed
-let sub_overflow_vec         = sub_overflow_bv
-let sub_overflow_vec_signed  = sub_overflow_bv_signed
-let mult_overflow_vec        = mult_overflow_bv
-let mult_overflow_vec_signed = mult_overflow_bv_signed
-
-val add_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
-val add_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
-val sub_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
-let add_overflow_vec_bit         = add_overflow_bv_bit
-let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
-let sub_overflow_vec_bit         = sub_overflow_bv_bit
-let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
-
-(*val shiftl       : list bitU -> integer -> list bitU*)
-(*val shiftr       : list bitU -> integer -> list bitU*)
-(*val arith_shiftr : list bitU -> integer -> list bitU*)
-(*val rotl         : list bitU -> integer -> list bitU*)
-(*val rotr         : list bitU -> integer -> list bitU*)
-definition shiftl  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "        where 
-     " shiftl       = ( 
-  shiftl_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition shiftr  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "        where 
-     " shiftr       = ( 
-  shiftr_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition arith_shiftr  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " arith_shiftr = ( 
-  arith_shiftr_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition rotl  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "          where 
-     " rotl         = ( 
-  rotl_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition rotr  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "          where 
-     " rotr         = ( 
-  rotr_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val mod_vec        : list bitU -> list bitU -> list bitU*)
-(*val mod_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
-(*val mod_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-definition mod_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " mod_vec        l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition mod_vec_maybe  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
-     " mod_vec_maybe  l r = ( mod_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r )"
-
-definition mod_vec_fail  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " mod_vec_fail   l r = ( maybe_fail (''mod_vec'') (mod_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition mod_vec_oracle  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " mod_vec_oracle l r = ( of_bits_oracle 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec l r))"
-
-
-(*val quot_vec        : list bitU -> list bitU -> list bitU*)
-(*val quot_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
-(*val quot_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-definition quot_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " quot_vec        l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition quot_vec_maybe  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
-     " quot_vec_maybe  l r = ( quot_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r )"
-
-definition quot_vec_fail  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " quot_vec_fail   l r = ( maybe_fail (''quot_vec'') (quot_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition quot_vec_oracle  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " quot_vec_oracle l r = ( of_bits_oracle 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec l r))"
-
-
-(*val quots_vec        : list bitU -> list bitU -> list bitU*)
-(*val quots_vec_maybe  : list bitU -> list bitU -> maybe (list bitU)*)
-(*val quots_vec_fail   : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
-definition quots_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " quots_vec        l r = ( case_option (repeat [BU] (int (List.length l))) id (quots_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition quots_vec_maybe  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option "  where 
-     " quots_vec_maybe  l r = ( quots_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r )"
-
-definition quots_vec_fail  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " quots_vec_fail   l r = ( maybe_fail (''quots_vec'') (quots_bv 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition quots_vec_oracle  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " quots_vec_oracle l r = ( of_bits_oracle 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec l r))"
-
-
-(*val mod_vec_int        : list bitU -> integer -> list bitU*)
-(*val mod_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
-(*val mod_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-definition mod_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " mod_vec_int        l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition mod_vec_int_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option "  where 
-     " mod_vec_int_maybe  l r = ( mod_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r )"
-
-definition mod_vec_int_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " mod_vec_int_fail   l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition mod_vec_int_oracle  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " mod_vec_int_oracle l r = ( of_bits_oracle 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int l r))"
-
-
-(*val quot_vec_int        : list bitU -> integer -> list bitU*)
-(*val quot_vec_int_maybe  : list bitU -> integer -> maybe (list bitU)*)
-(*val quot_vec_int_fail   : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
-definition quot_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " quot_vec_int        l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition quot_vec_int_maybe  :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option "  where 
-     " quot_vec_int_maybe  l r = ( quot_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r )"
-
-definition quot_vec_int_fail  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " quot_vec_int_fail   l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict
-   instance_Sail_values_BitU_Sail_values_bitU_dict) l r))"
-
-definition quot_vec_int_oracle  :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad "  where 
-     " quot_vec_int_oracle l r = ( of_bits_oracle 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int l r))"
-
-
-(*val replicate_bits : list bitU -> integer -> list bitU*)
-definition replicate_bits  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " replicate_bits = ( 
-  replicate_bits_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val duplicate : bitU -> integer -> list bitU*)
-definition duplicate  :: " bitU \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " duplicate = ( 
-  duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict )"
-
-definition duplicate_maybe  :: " bitU \<Rightarrow> int \<Rightarrow>((bitU)list)option "  where 
-     " duplicate_maybe b n = ( Some (duplicate b n))"
-
-definition duplicate_fail  :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " duplicate_fail b n = ( return (duplicate b n))"
-
-definition duplicate_oracle  :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad "  where 
-     " duplicate_oracle b n = (
-  bool_of_bitU_oracle b \<bind> (\<lambda> b . 
-  return (duplicate (bitU_of_bool b) n)))"
-
-
-(*val reverse_endianness : list bitU -> list bitU*)
-definition reverse_endianness  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
-     " reverse_endianness v = ( reverse_endianness_list v )"
-
-
-(*val get_slice_int : integer -> integer -> integer -> list bitU*)
-definition get_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " get_slice_int = ( 
-  get_slice_int_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*)
-definition set_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int "  where 
-     " set_slice_int = ( 
-  set_slice_int_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-
-(*val slice : list bitU -> integer -> integer -> list bitU*)
-definition slice  :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " slice v lo len = (
-  subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
-
-
-(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*)
-definition set_slice  :: " int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = (
-  update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
-
-
-(*val eq_vec    : list bitU -> list bitU -> bool*)
-(*val neq_vec   : list bitU -> list bitU -> bool*)
-definition eq_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool "     where 
-     " eq_vec    = ( 
-  eq_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-definition neq_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool "    where 
-     " neq_vec   = ( 
-  neq_bv
-    (instance_Sail_values_Bitvector_list_dict
-       instance_Sail_values_BitU_Sail_values_bitU_dict) )"
-
-end
diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy
deleted file mode 100644
index edaec4e3..00000000
--- a/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy
+++ /dev/null
@@ -1,638 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.\<close>
-
-theory "Sail_operators_mwords" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Lem_machine_word" 
-	 "Sail_values" 
-	 "Sail_operators" 
-	 "Prompt_monad" 
-	 "Prompt" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_values*)
-(*open import Sail_operators*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-definition uint_maybe  :: "('a::len)Word.word \<Rightarrow>(int)option "  where 
-     " uint_maybe v = ( Some (Word.uint v))"
-
-definition uint_fail  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
-     " uint_fail v = ( return (Word.uint v))"
-
-definition uint_oracle  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
-     " uint_oracle v = ( return (Word.uint v))"
-
-definition sint_maybe  :: "('a::len)Word.word \<Rightarrow>(int)option "  where 
-     " sint_maybe v = ( Some (Word.sint v))"
-
-definition sint_fail  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
-     " sint_fail v = ( return (Word.sint v))"
-
-definition sint_oracle  :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
-     " sint_oracle v = ( return (Word.sint v))"
-
-
-(*val vec_of_bits_maybe    : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*)
-(*val vec_of_bits_fail     : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
-(*val vec_of_bits_oracle   : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
-(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*)
-(*val vec_of_bits          : forall 'a. Size 'a => list bitU -> mword 'a*)
-definition vec_of_bits_maybe  :: "(bitU)list \<Rightarrow>(('a::len)Word.word)option "  where 
-     " vec_of_bits_maybe bits = ( map_option Word.of_bl (just_list (List.map bool_of_bitU bits)))"
-
-definition vec_of_bits_fail  :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " vec_of_bits_fail bits = ( of_bits_fail 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits )"
-
-definition vec_of_bits_oracle  :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " vec_of_bits_oracle bits = ( of_bits_oracle 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits )"
-
-definition vec_of_bits_failwith  :: "(bitU)list \<Rightarrow>('a::len)Word.word "  where 
-     " vec_of_bits_failwith bits = ( of_bits_failwith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits )"
-
-definition vec_of_bits  :: "(bitU)list \<Rightarrow>('a::len)Word.word "  where 
-     " vec_of_bits bits = ( of_bits_failwith 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict bits )"
-
-
-(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
-definition access_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_vec_inc = ( 
-  access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict )"
-
-
-(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
-definition access_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_vec_dec = ( 
-  access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict )"
-
-
-definition update_vec_dec_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " update_vec_dec_maybe w i b = ( update_mword_dec w i b )"
-
-definition update_vec_dec_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " update_vec_dec_fail w i b = (
-  bool_of_bitU_fail b \<bind> (\<lambda> b . 
-  return (update_mword_bool_dec w i b)))"
-
-definition update_vec_dec_oracle  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " update_vec_dec_oracle w i b = (
-  bool_of_bitU_oracle b \<bind> (\<lambda> b . 
-  return (update_mword_bool_dec w i b)))"
-
-definition update_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " update_vec_dec w i b = ( maybe_failwith (update_vec_dec_maybe w i b))"
-
-
-definition update_vec_inc_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " update_vec_inc_maybe w i b = ( update_mword_inc w i b )"
-
-definition update_vec_inc_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " update_vec_inc_fail w i b = (
-  bool_of_bitU_fail b \<bind> (\<lambda> b . 
-  return (update_mword_bool_inc w i b)))"
-
-definition update_vec_inc_oracle  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " update_vec_inc_oracle w i b = (
-  bool_of_bitU_oracle b \<bind> (\<lambda> b . 
-  return (update_mword_bool_inc w i b)))"
-
-definition update_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " update_vec_inc w i b = ( maybe_failwith (update_vec_inc_maybe w i b))"
-
-
-(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-definition subrange_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " subrange_vec_dec w i j = ( Word.slice (nat_of_int j) w )"
-
-
-(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-definition subrange_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " subrange_vec_inc w i j = ( subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j))"
-
-
-(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-definition update_subrange_vec_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " update_subrange_vec_dec w i j w' = ( Lem.word_update w (nat_of_int j) (nat_of_int i) w' )"
-
-
-(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-definition update_subrange_vec_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " update_subrange_vec_inc w i j w' = ( update_subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j) w' )"
-
-
-(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-definition extz_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " extz_vec _ w = ( Word.ucast w )"
-
-
-(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-definition exts_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " exts_vec _ w = ( Word.scast w )"
-
-
-(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-definition zero_extend  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " zero_extend w _ = ( Word.ucast w )"
-
-
-(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-definition sign_extend  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " sign_extend w _ = ( Word.scast w )"
-
-
-(*val zeros : forall 'a. Size 'a => integer -> mword 'a*)
-definition zeros  :: " int \<Rightarrow>('a::len)Word.word "  where 
-     " zeros _ = ( Word.word_of_int (int(( 0 :: nat))))"
-
-
-(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-definition vector_truncate  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " vector_truncate w _ = ( Word.ucast w )"
-
-
-(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
-definition concat_vec  :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('c::len)Word.word "  where 
-     " concat_vec = ( Word.word_cat )"
-
-
-(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*)
-definition cons_vec_bool  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " cons_vec_bool b w = ( Word.of_bl (b # Word.to_bl w))"
-
-definition cons_vec_maybe  :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>(('b::len)Word.word)option "  where 
-     " cons_vec_maybe b w = ( map_option (\<lambda> b .  cons_vec_bool b w) (bool_of_bitU b))"
-
-definition cons_vec_fail  :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad "  where 
-     " cons_vec_fail b w = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (cons_vec_bool b w)))"
-
-definition cons_vec_oracle  :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad "  where 
-     " cons_vec_oracle b w = ( bool_of_bitU_oracle b \<bind> (\<lambda> b .  return (cons_vec_bool b w)))"
-
-definition cons_vec  :: " bitU \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " cons_vec b w = ( maybe_failwith (cons_vec_maybe b w))"
-
-
-(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*)
-definition vec_of_bool  :: " int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " vec_of_bool _ b = ( Word.of_bl [b])"
-
-definition vec_of_bit_maybe  :: " int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " vec_of_bit_maybe len b = ( map_option (vec_of_bool len) (bool_of_bitU b))"
-
-definition vec_of_bit_fail  :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " vec_of_bit_fail len b = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (vec_of_bool len b)))"
-
-definition vec_of_bit_oracle  :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " vec_of_bit_oracle len b = ( bool_of_bitU_oracle b \<bind> (\<lambda> b .  return (vec_of_bool len b)))"
-
-definition vec_of_bit  :: " int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " vec_of_bit len b = ( maybe_failwith (vec_of_bit_maybe len b))"
-
-
-(*val cast_bool_vec : bool -> mword ty1*)
-definition cast_bool_vec  :: " bool \<Rightarrow>(1)Word.word "  where 
-     " cast_bool_vec b = ( vec_of_bool(( 1 :: int)) b )"
-
-definition cast_unit_vec_maybe  :: " bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " cast_unit_vec_maybe b = ( vec_of_bit_maybe(( 1 :: int)) b )"
-
-definition cast_unit_vec_fail  :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad "  where 
-     " cast_unit_vec_fail b = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (cast_bool_vec b)))"
-
-definition cast_unit_vec_oracle  :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad "  where 
-     " cast_unit_vec_oracle b = ( bool_of_bitU_oracle b \<bind> (\<lambda> b .  return (cast_bool_vec b)))"
-
-definition cast_unit_vec  :: " bitU \<Rightarrow>('a::len)Word.word "  where 
-     " cast_unit_vec b = ( maybe_failwith (cast_unit_vec_maybe b))"
-
-
-(*val msb : forall 'a. Size 'a => mword 'a -> bitU*)
-definition msb  :: "('a::len)Word.word \<Rightarrow> bitU "  where 
-     " msb = ( 
-  most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict )"
-
-
-(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*)
-definition int_of_vec  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
-     " int_of_vec sign w = (
-  if sign
-  then Word.sint w
-  else Word.uint w )"
-
-definition int_of_vec_maybe  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>(int)option "  where 
-     " int_of_vec_maybe sign w = ( Some (int_of_vec sign w))"
-
-definition int_of_vec_fail  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('c,(int),'b)monad "  where 
-     " int_of_vec_fail sign w = ( return (int_of_vec sign w))"
-
-
-(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*)
-definition string_of_vec  :: "('a::len)Word.word \<Rightarrow> string "  where 
-     " string_of_vec = ( 
-  string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )"
-
-
-(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val or_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
-definition and_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " and_vec = ( Bits.bitAND )"
-
-definition or_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "   where 
-     " or_vec  = ( Bits.bitOR )"
-
-definition xor_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " xor_vec = ( Bits.bitXOR )"
-
-definition not_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " not_vec = ( Bits.bitNOT )"
-
-
-(*val add_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val adds_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val sub_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val subs_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val mult_vec  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
-(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
-definition add_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " add_vec   l r = ( Word.word_of_int ((int_of_mword False l) + (int_of_mword False r)))"
-
-definition adds_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " adds_vec  l r = ( Word.word_of_int ((int_of_mword True l) + (int_of_mword True r)))"
-
-definition sub_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " sub_vec   l r = ( Word.word_of_int ((int_of_mword False l) - (int_of_mword False r)))"
-
-definition subs_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " subs_vec  l r = ( Word.word_of_int ((int_of_mword True l) - (int_of_mword True r)))"
-
-definition mult_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " mult_vec  l r = ( Word.word_of_int ((int_of_mword False (Word.ucast l :: ( 'b::len)Word.word)) * (int_of_mword False (Word.ucast r :: ( 'b::len)Word.word))))"
-
-definition mults_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))"
-
-
-(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val adds_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val subs_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-definition add_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " add_vec_int   l r = ( arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op+)   False l r )"
-
-definition adds_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " adds_vec_int  l r = ( arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op+)   True  l r )"
-
-definition sub_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " sub_vec_int   l r = ( arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )"
-
-definition subs_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " subs_vec_int  l r = ( arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
-
-definition mult_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " mult_vec_int  l r = ( arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op*)  False (Word.ucast l :: ( 'b::len)Word.word) r )"
-
-definition mults_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " mults_vec_int l r = ( arith_op_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op*)  True  (Word.scast l :: ( 'b::len)Word.word) r )"
-
-
-(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val adds_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val subs_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-definition add_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " add_int_vec   l r = ( arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op+)   False l r )"
-
-definition adds_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " adds_int_vec  l r = ( arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op+)   True  l r )"
-
-definition sub_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " sub_int_vec   l r = ( arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )"
-
-definition subs_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " subs_int_vec  l r = ( arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
-
-definition mult_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " mult_int_vec  l r = ( arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op*)  False l (Word.ucast r :: ( 'b::len)Word.word))"
-
-definition mults_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " mults_int_vec l r = ( arith_op_int_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op*)  True  l (Word.scast r :: ( 'b::len)Word.word))"
-
-
-(*val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-(*val sub_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
-
-definition add_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " add_vec_bool        l r = ( arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )"
-
-definition add_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " add_vec_bit_maybe   l r = ( map_option (add_vec_bool l) (bool_of_bitU r))"
-
-definition add_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " add_vec_bit_fail    l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (add_vec_bool l r)))"
-
-definition add_vec_bit_oracle  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " add_vec_bit_oracle  l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (add_vec_bool l r)))"
-
-definition add_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " add_vec_bit         l r = ( maybe_failwith (add_vec_bit_maybe  l r))"
-
-
-definition adds_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " adds_vec_bool       l r = ( arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True  l r )"
-
-definition adds_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " adds_vec_bit_maybe  l r = ( map_option (adds_vec_bool l) (bool_of_bitU r))"
-
-definition adds_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " adds_vec_bit_fail   l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (adds_vec_bool l r)))"
-
-definition adds_vec_bit_oracle  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " adds_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (adds_vec_bool l r)))"
-
-definition adds_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " adds_vec_bit        l r = ( maybe_failwith (adds_vec_bit_maybe l r))"
-
-
-definition sub_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " sub_vec_bool        l r = ( arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )"
-
-definition sub_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " sub_vec_bit_maybe   l r = ( map_option (sub_vec_bool l) (bool_of_bitU r))"
-
-definition sub_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " sub_vec_bit_fail    l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (sub_vec_bool l r)))"
-
-definition sub_vec_bit_oracle  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " sub_vec_bit_oracle  l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (sub_vec_bool l r)))"
-
-definition sub_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " sub_vec_bit         l r = ( maybe_failwith (sub_vec_bit_maybe  l r))"
-
-
-definition subs_vec_bool  :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " subs_vec_bool       l r = ( arith_op_bv_bool 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
-
-definition subs_vec_bit_maybe  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " subs_vec_bit_maybe  l r = ( map_option (subs_vec_bool l) (bool_of_bitU r))"
-
-definition subs_vec_bit_fail  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " subs_vec_bit_fail   l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r .  return (subs_vec_bool l r)))"
-
-definition subs_vec_bit_oracle  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " subs_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r .  return (subs_vec_bool l r)))"
-
-definition subs_vec_bit  :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word "  where 
-     " subs_vec_bit        l r = ( maybe_failwith (subs_vec_bit_maybe  l r))"
-
-
-(* TODO
-val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU)
-let maybe_mword_of_bits_overflow (bits, overflow, carry) =
-  Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits)
-
-val add_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val adds_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val sub_overflow_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val subs_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val mult_overflow_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
-let add_overflow_vec   l r = maybe_mword_of_bits_overflow (add_overflow_bv l r)
-let adds_overflow_vec  l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r)
-let sub_overflow_vec   l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r)
-let subs_overflow_vec  l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r)
-let mult_overflow_vec  l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r)
-let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r)
-
-val add_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-val add_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-val sub_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-val sub_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
-let add_overflow_vec_bit         = add_overflow_bv_bit
-let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
-let sub_overflow_vec_bit         = sub_overflow_bv_bit
-let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed*)
-
-(*val shiftl       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val shiftr       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val rotl         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val rotr         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-definition shiftl  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "        where 
-     " shiftl       = ( shiftl_mword )"
-
-definition shiftr  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "        where 
-     " shiftr       = ( shiftr_mword )"
-
-definition arith_shiftr  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " arith_shiftr = ( arith_shiftr_mword )"
-
-definition rotl  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "          where 
-     " rotl         = ( rotl_mword )"
-
-definition rotr  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "          where 
-     " rotr         = ( rotr_mword )"
-
-
-(*val mod_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val mod_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
-(*val mod_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-definition mod_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " mod_vec        l r = ( mod_mword l r )"
-
-definition mod_vec_maybe  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option "  where 
-     " mod_vec_maybe  l r = ( mod_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )"
-
-definition mod_vec_fail  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " mod_vec_fail   l r = ( maybe_fail (''mod_vec'') (mod_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))"
-
-definition mod_vec_oracle  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " mod_vec_oracle l r = (
-  (case  (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      Some w => return w
-    | None => mword_oracle () 
-  ))"
-
-
-(*val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val quot_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
-(*val quot_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-definition quot_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " quot_vec        l r = ( quot_mword l r )"
-
-definition quot_vec_maybe  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option "  where 
-     " quot_vec_maybe  l r = ( quot_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )"
-
-definition quot_vec_fail  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " quot_vec_fail   l r = ( maybe_fail (''quot_vec'') (quot_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))"
-
-definition quot_vec_oracle  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " quot_vec_oracle l r = (
-  (case  (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      Some w => return w
-    | None => mword_oracle () 
-  ))"
-
-
-(*val quots_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
-(*val quots_vec_maybe  : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
-(*val quots_vec_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
-definition quots_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " quots_vec        l r = ( quots_mword l r )"
-
-definition quots_vec_maybe  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option "  where 
-     " quots_vec_maybe  l r = ( quots_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )"
-
-definition quots_vec_fail  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " quots_vec_fail   l r = ( maybe_fail (''quots_vec'') (quots_bv 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))"
-
-definition quots_vec_oracle  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " quots_vec_oracle l r = (
-  (case  (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      Some w => return w
-    | None => mword_oracle () 
-  ))"
-
-
-(*val mod_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mod_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
-(*val mod_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-definition mod_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " mod_vec_int        l r = ( mod_mword_int l r )"
-
-definition mod_vec_int_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option "  where 
-     " mod_vec_int_maybe  l r = ( mod_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )"
-
-definition mod_vec_int_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " mod_vec_int_fail   l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))"
-
-definition mod_vec_int_oracle  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " mod_vec_int_oracle l r = (
-  (case  (mod_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      Some w => return w
-    | None => mword_oracle () 
-  ))"
-
-
-(*val quot_vec_int        : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val quot_vec_int_maybe  : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
-(*val quot_vec_int_fail   : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
-definition quot_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " quot_vec_int        l r = ( quot_mword_int l r )"
-
-definition quot_vec_int_maybe  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option "  where 
-     " quot_vec_int_maybe  l r = ( quot_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )"
-
-definition quot_vec_int_fail  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " quot_vec_int_fail   l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))"
-
-definition quot_vec_int_oracle  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad "  where 
-     " quot_vec_int_oracle l r = (
-  (case  (quot_bv_int 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of
-      Some w => return w
-    | None => mword_oracle () 
-  ))"
-
-
-(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-definition replicate_bits  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " replicate_bits v count1 = ( Word.of_bl (repeat (Word.to_bl v) count1))"
-
-
-(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*)
-definition duplicate_bool  :: " bool \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " duplicate_bool   b n = ( Word.of_bl (repeat [b] n))"
-
-definition duplicate_maybe  :: " bitU \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option "  where 
-     " duplicate_maybe  b n = ( map_option (\<lambda> b .  duplicate_bool b n) (bool_of_bitU b))"
-
-definition duplicate_fail  :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " duplicate_fail   b n = ( bool_of_bitU_fail b \<bind> (\<lambda> b .  return (duplicate_bool b n)))"
-
-definition duplicate_oracle  :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad "  where 
-     " duplicate_oracle b n = ( bool_of_bitU_oracle b \<bind> (\<lambda> b .  return (duplicate_bool b n)))"
-
-definition duplicate  :: " bitU \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " duplicate        b n = ( maybe_failwith (duplicate_maybe b n))"
-
-
-(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*)
-definition reverse_endianness  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " reverse_endianness v = ( Word.of_bl (reverse_endianness_list (Word.to_bl v)))"
-
-
-(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*)
-definition get_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " get_slice_int = ( 
-  get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )"
-
-
-(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*)
-definition set_slice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
-     " set_slice_int = ( 
-  set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )"
-
-
-(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-definition slice  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " slice v lo len = (
-  subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
-
-
-(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*)
-definition set_slice  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = (
-  update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
-
-
-(*val eq_vec    : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
-(*val neq_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
-end
diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy
deleted file mode 100644
index 22c35e1f..00000000
--- a/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy
+++ /dev/null
@@ -1,112 +0,0 @@
-theory "Sail_operators_mwords_lemmas"
-  imports Sail_operators_mwords
-begin
-
-lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_oracle_def
-lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_oracle_def
-
-lemma bools_of_bits_oracle_just_list[simp]:
-  assumes "just_list (map bool_of_bitU bus) = Some bs"
-  shows "bools_of_bits_oracle bus = return bs"
-proof -
-  have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_oracle b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)"
-    if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools
-  proof (use that in \<open>induction bus arbitrary: bs bools\<close>)
-    case (Cons bu bus bs)
-    obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b"
-      using Cons.prems by (cases bu) (auto split: option.splits)
-    then show ?case
-      using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"]
-      by (cases bu) (auto simp: bool_of_bitU_oracle_def split: option.splits)
-  qed auto
-  then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_oracle_def
-    by auto
-qed
-
-lemma of_bits_mword_return_of_bl[simp]:
-  assumes "just_list (map bool_of_bitU bus) = Some bs"
-  shows "of_bits_oracle BC_mword bus = return (of_bl bs)"
-    and "of_bits_fail BC_mword bus = return (of_bl bs)"
-  by (auto simp: of_bits_oracle_def of_bits_fail_def maybe_fail_def assms BC_mword_defs)
-
-lemma vec_of_bits_of_bl[simp]:
-  assumes "just_list (map bool_of_bitU bus) = Some bs"
-  shows "vec_of_bits_maybe bus = Some (of_bl bs)"
-    and "vec_of_bits_fail bus = return (of_bl bs)"
-    and "vec_of_bits_oracle bus = return (of_bl bs)"
-    and "vec_of_bits_failwith bus = of_bl bs"
-    and "vec_of_bits bus = of_bl bs"
-  unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_oracle_def
-            vec_of_bits_failwith_def vec_of_bits_def
-  by (auto simp: assms)
-
-lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def]
-
-lemma access_vec_inc_test_bit[simp]:
-  fixes w :: "('a::len) word"
-  assumes "n \<ge> 0" and "nat n < LENGTH('a)"
-  shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))"
-  using assms
-  by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl)
-
-lemma bool_of_bitU_monadic_simps[simp]:
-  "bool_of_bitU_fail B0 = return False"
-  "bool_of_bitU_fail B1 = return True"
-  "bool_of_bitU_fail BU = Fail ''bool_of_bitU''"
-  "bool_of_bitU_oracle B0 = return False"
-  "bool_of_bitU_oracle B1 = return True"
-  "bool_of_bitU_oracle BU = undefined_bool ()"
-  unfolding bool_of_bitU_fail_def bool_of_bitU_oracle_def
-  by auto
-
-lemma update_vec_dec_simps[simp]:
-  "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)"
-  "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)"
-  "update_vec_dec_maybe w i BU = None"
-  "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)"
-  "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)"
-  "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''"
-  "update_vec_dec_oracle w i B0 = return (set_bit w (nat i) False)"
-  "update_vec_dec_oracle w i B1 = return (set_bit w (nat i) True)"
-  "update_vec_dec_oracle w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))"
-  "update_vec_dec w i B0 = set_bit w (nat i) False"
-  "update_vec_dec w i B1 = set_bit w (nat i) True"
-  unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_oracle_def update_vec_dec_def
-  by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def)
-
-lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]:
-  "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)"
-  by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq)
-
-declare extz_vec_def[simp]
-declare exts_vec_def[simp]
-declare concat_vec_def[simp]
-
-lemma msb_Bits_msb[simp]:
-  "msb w = bitU_of_bool (Bits.msb w)"
-  by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits)
-
-declare and_vec_def[simp]
-declare or_vec_def[simp]
-declare xor_vec_def[simp]
-declare not_vec_def[simp]
-
-lemma arith_vec_simps[simp]:
-  "add_vec l r = l + r"
-  "sub_vec l r = l - r"
-  "mult_vec l r = (ucast l) * (ucast r)"
-  unfolding add_vec_def sub_vec_def mult_vec_def
-  by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def)
-
-declare adds_vec_def[simp]
-declare subs_vec_def[simp]
-declare mults_vec_def[simp]
-
-lemma arith_vec_int_simps[simp]:
-  "add_vec_int l r = l + (word_of_int r)"
-  "sub_vec_int l r = l - (word_of_int r)"
-  "mult_vec_int l r = (ucast l) * (word_of_int r)"
-  unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
-  by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
-
-end
diff --git a/snapshots/isabelle/lib/sail/Sail_values.thy b/snapshots/isabelle/lib/sail/Sail_values.thy
deleted file mode 100644
index 7338ac40..00000000
--- a/snapshots/isabelle/lib/sail/Sail_values.thy
+++ /dev/null
@@ -1,1215 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/sail_values.lem.\<close>
-
-theory "Sail_values" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Lem_machine_word" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Machine_word*)
-(*open import Sail_impl_base*)
-
-
-type_synonym ii =" int "
-type_synonym nn =" nat "
-
-(*val nat_of_int : integer -> nat*)
-definition nat_of_int  :: " int \<Rightarrow> nat "  where 
-     " nat_of_int i = ( if i <( 0 :: int) then( 0 :: nat) else nat (abs ( i)))"
-
-
-(*val pow : integer -> integer -> integer*)
-definition pow  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " pow m n = ( m ^ (nat_of_int n))"
-
-
-definition pow2  :: " int \<Rightarrow> int "  where 
-     " pow2 n = ( pow(( 2 :: int)) n )"
-
-
-(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
-
-(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
-
-(*let add_int l r = integerAdd l r
-let add_signed l r = integerAdd l r
-let sub_int l r = integerMinus l r
-let mult_int l r = integerMult l r
-let div_int l r = integerDiv l r
-let div_nat l r = natDiv l r
-let power_int_nat l r = integerPow l r
-let power_int_int l r = integerPow l (nat_of_int r)
-let negate_int i = integerNegate i
-let min_int l r = integerMin l r
-let max_int l r = integerMax l r
-
-let add_real l r = realAdd l r
-let sub_real l r = realMinus l r
-let mult_real l r = realMult l r
-let div_real l r = realDiv l r
-let negate_real r = realNegate r
-let abs_real r = realAbs r
-let power_real b e = realPowInteger b e*)
-
-(*val prerr_endline : string -> unit*)
-definition prerr_endline  :: " string \<Rightarrow> unit "  where 
-     " prerr_endline _ = ( ()  )"
-
-
-(*val print_int : string -> integer -> unit*)
-definition print_int  :: " string \<Rightarrow> int \<Rightarrow> unit "  where 
-     " print_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))"
-
-
-(*val putchar : integer -> unit*)
-definition putchar  :: " int \<Rightarrow> unit "  where 
-     " putchar _ = ( ()  )"
-
-
-(*val shr_int : ii -> ii -> ii*)
-function (sequential,domintros)  shr_int  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " shr_int x s = ( if s >( 0 :: int) then shr_int (x div( 2 :: int)) (s -( 1 :: int)) else x )" 
-by pat_completeness auto
-
-
-(*val shl_int : integer -> integer -> integer*)
-function (sequential,domintros)  shl_int  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " shl_int i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int i (shift -( 1 :: int)) else i )" 
-by pat_completeness auto
-
-definition take_list  :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " take_list n xs = ( List.take (nat_of_int n) xs )"
-
-definition drop_list  :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " drop_list n xs = ( List.drop (nat_of_int n) xs )"
-
-
-(*val repeat : forall 'a. list 'a -> integer -> list 'a*)
-fun  repeat  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a list "  where 
-     " repeat xs n = (
-  if n \<le>( 0 :: int) then []
-  else xs @ repeat xs (n-( 1 :: int)))"
-
-
-definition duplicate_to_list  :: " 'a \<Rightarrow> int \<Rightarrow> 'a list "  where 
-     " duplicate_to_list bit length1 = ( repeat [bit] length1 )"
-
-
-fun  replace  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
-     " replace ([]) (n :: int) b' = ( [])"
-|" replace (b # bs) (n :: int) b' = (
-     if n =( 0 :: int) then b' # bs
-              else b # replace bs (n -( 1 :: int)) b' )"
-
-
-definition upper  :: " 'a \<Rightarrow> 'a "  where 
-     " upper n = ( n )"
-
-
-(* Modulus operation corresponding to quot below -- result
-   has sign of dividend. *)
-definition hardware_mod  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " hardware_mod (a:: int) (b::int) = (
-  (let m = ((abs a) mod (abs b)) in
-  if a <( 0 :: int) then - m else m))"
-
-
-(* There are different possible answers for integer divide regarding
-rounding behaviour on negative operands. Positive operands always
-round down so derive the one we want (trucation towards zero) from
-that *)
-definition hardware_quot  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " hardware_quot (a::int) (b::int) = (
-  (let q = ((abs a) div (abs b)) in
-  if ((a<( 0 :: int)) \<longleftrightarrow> (b<( 0 :: int))) then
-    q  (* same sign -- result positive *)
-  else
-    - q))"
- (* different sign -- result negative *)
-
-definition max_64u  :: " int "  where 
-     " max_64u = ( ((( 2 :: int))^(( 64 :: nat))) -( 1 :: int))"
-
-definition max_64  :: " int "   where 
-     " max_64  = ( ((( 2 :: int))^(( 63 :: nat))) -( 1 :: int))"
-
-definition min_64  :: " int "   where 
-     " min_64  = (( 0 :: int) - ((( 2 :: int))^(( 63 :: nat))))"
-
-definition max_32u  :: " int "  where 
-     " max_32u = ( (( 4294967295 :: int) :: int))"
-
-definition max_32  :: " int "   where 
-     " max_32  = ( (( 2147483647 :: int) :: int))"
-
-definition min_32  :: " int "   where 
-     " min_32  = ( (( 0 :: int) -( 2147483648 :: int) :: int))"
-
-definition max_8  :: " int "    where 
-     " max_8   = ( (( 127 :: int) :: int))"
-
-definition min_8  :: " int "    where 
-     " min_8   = ( (( 0 :: int) -( 128 :: int) :: int))"
-
-definition max_5  :: " int "    where 
-     " max_5   = ( (( 31 :: int) :: int))"
-
-definition min_5  :: " int "    where 
-     " min_5   = ( (( 0 :: int) -( 32 :: int) :: int))"
-
-
-(* just_list takes a list of maybes and returns Just xs if all elements have
-   a value, and Nothing if one of the elements is Nothing. *)
-(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*)
-fun  just_list  :: "('a option)list \<Rightarrow>('a list)option "  where 
-     " just_list ([]) = ( Some [])"
-|" just_list (x # xs) = (
-    (case  (x, just_list xs) of
-        (Some x, Some xs) => Some (x # xs)
-      | (_, _) => None
-    ))"
-
-
-(*val maybe_failwith : forall 'a. maybe 'a -> 'a*)
-definition maybe_failwith  :: " 'a option \<Rightarrow> 'a "  where 
-     " maybe_failwith = ( \<lambda>x .  
-  (case  x of   Some a => a | None => failwith (''maybe_failwith'') ) )"
-
-
-(*** Bits *)
-datatype bitU = B0 | B1 | BU
-
-definition showBitU  :: " bitU \<Rightarrow> string "  where 
-     " showBitU = ( \<lambda>x .  
-  (case  x of   B0 => (''O'') | B1 => (''I'') | BU => (''U'') ) )"
-
-
-definition bitU_char  :: " bitU \<Rightarrow> char "  where 
-     " bitU_char = ( \<lambda>x .  
-  (case  x of   B0 => (CHR ''0'') | B1 => (CHR ''1'') | BU => (CHR ''?'') ) )"
-
-
-definition instance_Show_Show_Sail_values_bitU_dict  :: "(bitU)Show_class "  where 
-     " instance_Show_Show_Sail_values_bitU_dict = ((|
-
-  show_method = showBitU |) )"
-
-
-(*val compare_bitU : bitU -> bitU -> ordering*)
-fun compare_bitU  :: " bitU \<Rightarrow> bitU \<Rightarrow> ordering "  where 
-     " compare_bitU BU BU = ( EQ )"
-|" compare_bitU B0 B0 = ( EQ )"
-|" compare_bitU B1 B1 = ( EQ )"
-|" compare_bitU BU _ = ( LT )"
-|" compare_bitU _ BU = ( GT )"
-|" compare_bitU B0 _ = ( LT )"
-|" compare_bitU _ _ = ( GT )"
-
-
-definition instance_Basic_classes_Ord_Sail_values_bitU_dict  :: "(bitU)Ord_class "  where 
-     " instance_Basic_classes_Ord_Sail_values_bitU_dict = ((|
-
-  compare_method = compare_bitU,
-
-  isLess_method = (\<lambda>  l r. (compare_bitU l r) = LT),
-
-  isLessEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> GT),
-
-  isGreater_method = (\<lambda>  l r. (compare_bitU l r) = GT),
-
-  isGreaterEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> LT)|) )"
-
-
-record 'a BitU_class=
-
-  to_bitU_method ::" 'a \<Rightarrow> bitU " 
-
-  of_bitU_method ::" bitU \<Rightarrow> 'a "
-
-
-
-definition instance_Sail_values_BitU_Sail_values_bitU_dict  :: "(bitU)BitU_class "  where 
-     " instance_Sail_values_BitU_Sail_values_bitU_dict = ((|
-
-  to_bitU_method = (\<lambda> b. b),
-
-  of_bitU_method = (\<lambda> b. b)|) )"
-
-
-definition bool_of_bitU  :: " bitU \<Rightarrow>(bool)option "  where 
-     " bool_of_bitU = ( \<lambda>x .  
-  (case  x of   B0 => Some False | B1 => Some True | BU => None ) )"
-
-
-definition bitU_of_bool  :: " bool \<Rightarrow> bitU "  where 
-     " bitU_of_bool b = ( if b then B1 else B0 )"
-
-
-(*instance (BitU bool)
-  let to_bitU = bitU_of_bool
-  let of_bitU = bool_of_bitU
-end*)
-
-definition cast_bit_bool  :: " bitU \<Rightarrow>(bool)option "  where 
-     " cast_bit_bool = ( bool_of_bitU )"
-
-
-definition not_bit  :: " bitU \<Rightarrow> bitU "  where 
-     " not_bit = ( \<lambda>x .  
-  (case  x of   B1 => B0 | B0 => B1 | BU => BU ) )"
-
-
-(*val is_one : integer -> bitU*)
-definition is_one  :: " int \<Rightarrow> bitU "  where 
-     " is_one i = (
-  if i =( 1 :: int) then B1 else B0 )"
-
-
-(*val and_bit : bitU -> bitU -> bitU*)
-fun and_bit  :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU "  where 
-     " and_bit B0 _ = ( B0 )"
-|" and_bit _ B0 = ( B0 )"
-|" and_bit B1 B1 = ( B1 )"
-|" and_bit _ _ = ( BU )"
-
-
-(*val or_bit : bitU -> bitU -> bitU*)
-fun or_bit  :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU "  where 
-     " or_bit B1 _ = ( B1 )"
-|" or_bit _ B1 = ( B1 )"
-|" or_bit B0 B0 = ( B0 )"
-|" or_bit _ _ = ( BU )"
-
-
-(*val xor_bit : bitU -> bitU -> bitU*)
-fun xor_bit  :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU "  where 
-     " xor_bit B0 B0 = ( B0 )"
-|" xor_bit B0 B1 = ( B1 )"
-|" xor_bit B1 B0 = ( B1 )"
-|" xor_bit B1 B1 = ( B0 )"
-|" xor_bit _ _ = ( BU )"
-
-
-(*val &. : bitU -> bitU -> bitU*)
-
-(*val |. : bitU -> bitU -> bitU*)
-
-(*val +. : bitU -> bitU -> bitU*)
-
-
-(*** Bool lists ***)
-
-(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
-fun  bools_of_nat_aux  :: " int \<Rightarrow> nat \<Rightarrow>(bool)list \<Rightarrow>(bool)list "  where 
-     " bools_of_nat_aux len x acc1 = (
-  if len \<le>( 0 :: int) then acc1
-  else bools_of_nat_aux (len -( 1 :: int)) (x div( 2 :: nat)) ((if (x mod( 2 :: nat)) =( 1 :: nat) then True else False) # acc1))"
-
-definition bools_of_nat  :: " int \<Rightarrow> nat \<Rightarrow>(bool)list "  where 
-     " bools_of_nat len n = ( bools_of_nat_aux len n [])"
- (*List.reverse (bools_of_nat_aux n)*)
-
-(*val nat_of_bools_aux : natural -> list bool -> natural*)
-fun  nat_of_bools_aux  :: " nat \<Rightarrow>(bool)list \<Rightarrow> nat "  where 
-     " nat_of_bools_aux acc1 ([]) = ( acc1 )"
-|" nat_of_bools_aux acc1 (True # bs) = ( nat_of_bools_aux ((( 2 :: nat) * acc1) +( 1 :: nat)) bs )"
-|" nat_of_bools_aux acc1 (False # bs) = ( nat_of_bools_aux (( 2 :: nat) * acc1) bs )"
-
-definition nat_of_bools  :: "(bool)list \<Rightarrow> nat "  where 
-     " nat_of_bools bs = ( nat_of_bools_aux(( 0 :: nat)) bs )"
-
-
-(*val unsigned_of_bools : list bool -> integer*)
-definition unsigned_of_bools  :: "(bool)list \<Rightarrow> int "  where 
-     " unsigned_of_bools bs = ( int (nat_of_bools bs))"
-
-
-(*val signed_of_bools : list bool -> integer*)
-definition signed_of_bools  :: "(bool)list \<Rightarrow> int "  where 
-     " signed_of_bools bs = (
-  (case  bs of
-      True # _  =>( 0 :: int) - (( 1 :: int) + (unsigned_of_bools (List.map (\<lambda> x. \<not> x) bs)))
-    | False # _ => unsigned_of_bools bs
-    | [] =>( 0 :: int) (* Treat empty list as all zeros *)
-  ))"
-
-
-(*val int_of_bools : bool -> list bool -> integer*)
-definition int_of_bools  :: " bool \<Rightarrow>(bool)list \<Rightarrow> int "  where 
-     " int_of_bools sign bs = ( if sign then signed_of_bools bs else unsigned_of_bools bs )"
-
-
-(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
-fun  pad_list  :: " 'a \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a list "  where 
-     " pad_list x xs n = (
-  if n \<le>( 0 :: int) then xs else pad_list x (x # xs) (n -( 1 :: int)))"
-
-
-definition ext_list  :: " 'a \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " ext_list pad len xs = (
-  (let longer = (len - (int (List.length xs))) in
-  if longer <( 0 :: int) then List.drop (nat_of_int (abs (longer))) xs
-  else pad_list pad xs longer))"
-
-
-definition extz_bools  :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list "  where 
-     " extz_bools len bs = ( ext_list False len bs )"
-
-definition exts_bools  :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list "  where 
-     " exts_bools len bs = (
-  (case  bs of
-      True # _ => ext_list True len bs
-    | _ => ext_list False len bs
-  ))"
-
-
-fun  add_one_bool_ignore_overflow_aux  :: "(bool)list \<Rightarrow>(bool)list "  where 
-     " add_one_bool_ignore_overflow_aux ([]) = ( [])"
-|" add_one_bool_ignore_overflow_aux (False # bits) = ( True # bits )"
-|" add_one_bool_ignore_overflow_aux (True # bits) = ( False # add_one_bool_ignore_overflow_aux bits )"
-
-
-definition add_one_bool_ignore_overflow  :: "(bool)list \<Rightarrow>(bool)list "  where 
-     " add_one_bool_ignore_overflow bits = (
-  List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)))"
-
-
-(*let bool_list_of_int n =
-  let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
-  if n >= (0 : integer) then bs_abs
-  else add_one_bool_ignore_overflow (List.map not bs_abs)
-let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
-definition bools_of_int  :: " int \<Rightarrow> int \<Rightarrow>(bool)list "  where 
-     " bools_of_int len n = (
-  (let bs_abs = (bools_of_nat len (nat (abs (abs n)))) in
-  if n \<ge> (( 0 :: int) :: int) then bs_abs
-  else add_one_bool_ignore_overflow (List.map (\<lambda> x. \<not> x) bs_abs)))"
-
-
-(*** Bit lists ***)
-
-(*val has_undefined_bits : list bitU -> bool*)
-definition has_undefined_bits  :: "(bitU)list \<Rightarrow> bool "  where 
-     " has_undefined_bits bs = ( ((\<exists> x \<in> (set bs).  (\<lambda>x .  
-  (case  x of BU => True | _ => False )) x)))"
-
-
-definition bits_of_nat  :: " int \<Rightarrow> nat \<Rightarrow>(bitU)list "  where 
-     " bits_of_nat len n = ( List.map bitU_of_bool (bools_of_nat len n))"
-
-
-definition nat_of_bits  :: "(bitU)list \<Rightarrow>(nat)option "  where 
-     " nat_of_bits bits = (
-  (case  (just_list (List.map bool_of_bitU bits)) of
-      Some bs => Some (nat_of_bools bs)
-    | None => None
-  ))"
-
-
-definition not_bits  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
-     " not_bits = ( List.map not_bit )"
-
-
-(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*)
-definition binop_list  :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " binop_list op1 xs ys = (
-  List.foldr ( \<lambda>x .  
-  (case  x of (x, y) => \<lambda> acc1 .  op1 x y # acc1 )) (List.zip xs ys) [])"
-
-
-definition unsigned_of_bits  :: "(bitU)list \<Rightarrow>(int)option "  where 
-     " unsigned_of_bits bits = (
-  (case  (just_list (List.map bool_of_bitU bits)) of
-      Some bs => Some (unsigned_of_bools bs)
-    | None => None
-  ))"
-
-
-definition signed_of_bits  :: "(bitU)list \<Rightarrow>(int)option "  where 
-     " signed_of_bits bits = (
-  (case  (just_list (List.map bool_of_bitU bits)) of
-      Some bs => Some (signed_of_bools bs)
-    | None => None
-  ))"
-
-
-(*val int_of_bits : bool -> list bitU -> maybe integer*)
-definition int_of_bits  :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option "  where 
-     " int_of_bits sign bs = ( if sign then signed_of_bits bs else unsigned_of_bits bs )"
-
-
-definition extz_bits  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " extz_bits len bits = ( ext_list B0 len bits )"
-
-definition exts_bits  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " exts_bits len bits = (
-  (case  bits of
-    BU # _ => ext_list BU len bits
-  | B1 # _ => ext_list B1 len bits
-  | _ => ext_list B0 len bits
-  ))"
-
-
-fun  add_one_bit_ignore_overflow_aux  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
-     " add_one_bit_ignore_overflow_aux ([]) = ( [])"
-|" add_one_bit_ignore_overflow_aux (B0 # bits) = ( B1 # bits )"
-|" add_one_bit_ignore_overflow_aux (B1 # bits) = ( B0 # add_one_bit_ignore_overflow_aux bits )"
-|" add_one_bit_ignore_overflow_aux (BU # bits) = ( BU # List.map ( \<lambda>x .  
-  (case  x of _ => BU )) bits )"
-
-
-definition add_one_bit_ignore_overflow  :: "(bitU)list \<Rightarrow>(bitU)list "  where 
-     " add_one_bit_ignore_overflow bits = (
-  List.rev (add_one_bit_ignore_overflow_aux (List.rev bits)))"
-
-
-(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n)
-let bits_of_int len n = exts_bits len (bit_list_of_int n)*)
-definition bits_of_int  :: " int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " bits_of_int len n = ( List.map bitU_of_bool (bools_of_int len n))"
-
-
-(*val arith_op_bits :
-  (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
-definition arith_op_bits  :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " arith_op_bits op1 sign l r = (
-  (case  (int_of_bits sign l, int_of_bits sign r) of
-      (Some li, Some ri) => bits_of_int (int (List.length l)) (op1 li ri)
-    | (_, _) => repeat [BU] (int (List.length l))
-  ))"
-
-
-definition char_of_nibble  :: " bitU*bitU*bitU*bitU \<Rightarrow>(char)option "  where 
-     " char_of_nibble = ( \<lambda>x .  
-  (case  x of
-        (B0, B0, B0, B0) => Some (CHR ''0'')
-    | (B0, B0, B0, B1) => Some (CHR ''1'')
-    | (B0, B0, B1, B0) => Some (CHR ''2'')
-    | (B0, B0, B1, B1) => Some (CHR ''3'')
-    | (B0, B1, B0, B0) => Some (CHR ''4'')
-    | (B0, B1, B0, B1) => Some (CHR ''5'')
-    | (B0, B1, B1, B0) => Some (CHR ''6'')
-    | (B0, B1, B1, B1) => Some (CHR ''7'')
-    | (B1, B0, B0, B0) => Some (CHR ''8'')
-    | (B1, B0, B0, B1) => Some (CHR ''9'')
-    | (B1, B0, B1, B0) => Some (CHR ''A'')
-    | (B1, B0, B1, B1) => Some (CHR ''B'')
-    | (B1, B1, B0, B0) => Some (CHR ''C'')
-    | (B1, B1, B0, B1) => Some (CHR ''D'')
-    | (B1, B1, B1, B0) => Some (CHR ''E'')
-    | (B1, B1, B1, B1) => Some (CHR ''F'')
-    | _ => None
-  ) )"
-
-
-fun  hexstring_of_bits  :: "(bitU)list \<Rightarrow>((char)list)option "  where 
-     " hexstring_of_bits (b1 # b2 # b3 # b4 # bs) = (
-     (let n = (char_of_nibble (b1, b2, b3, b4)) in
-     (let s = (hexstring_of_bits bs) in
-     (case  (n, s) of
-       (Some n, Some s) => Some (n # s)
-     | _ => None
-     ))))"
-|" hexstring_of_bits ([]) = ( Some [])"
-|" hexstring_of_bits _ = ( None )"
-
-
-definition show_bitlist  :: "(bitU)list \<Rightarrow> string "  where 
-     " show_bitlist bs = (
-  (case  hexstring_of_bits bs of
-    Some s => ((CHR ''0'') # ((CHR ''x'') # s))
-  | None => ((CHR ''0'') # ((CHR ''b'') # List.map bitU_char bs))
-  ))"
-
-
-(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*)
-definition subrange_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list "  where 
-     " subrange_list_inc xs i j = (
-  (let (toJ,suffix0) = (split_at (nat_of_int (j +( 1 :: int))) xs) in
-  (let (prefix0,fromItoJ) = (split_at (nat_of_int i) toJ) in
-  fromItoJ)))"
-
-
-(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*)
-definition subrange_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list "  where 
-     " subrange_list_dec xs i j = (
-  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
-  subrange_list_inc xs (top1 - i) (top1 - j)))"
-
-
-(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*)
-definition subrange_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list "  where 
-     " subrange_list is_inc xs i j = ( if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j )"
-
-
-(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
-definition update_subrange_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " update_subrange_list_inc xs i j xs' = (
-  (let (toJ,suffix) = (split_at (nat_of_int (j +( 1 :: int))) xs) in
-  (let (prefix,fromItoJ0) = (split_at (nat_of_int i) toJ) in
-  (prefix @ xs') @ suffix)))"
-
-
-(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
-definition update_subrange_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " update_subrange_list_dec xs i j xs' = (
-  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
-  update_subrange_list_inc xs (top1 - i) (top1 - j) xs'))"
-
-
-(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*)
-definition update_subrange_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list "  where 
-     " update_subrange_list is_inc xs i j xs' = (
-  if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs' )"
-
-
-(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*)
-definition access_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a "  where 
-     " access_list_inc xs n = ( List.nth xs (nat_of_int n))"
-
-
-(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*)
-definition access_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a "  where 
-     " access_list_dec xs n = (
-  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
-  access_list_inc xs (top1 - n)))"
-
-
-(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*)
-definition access_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a "  where 
-     " access_list is_inc xs n = (
-  if is_inc then access_list_inc xs n else access_list_dec xs n )"
-
-
-(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*)
-definition update_list_inc  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
-     " update_list_inc xs n x = ( List.list_update xs (nat_of_int n) x )"
-
-
-(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*)
-definition update_list_dec  :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
-     " update_list_dec xs n x = (
-  (let top1 = ((int (List.length xs)) -( 1 :: int)) in
-  update_list_inc xs (top1 - n) x))"
-
-
-(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*)
-definition update_list  :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list "  where 
-     " update_list is_inc xs n x = (
-  if is_inc then update_list_inc xs n x else update_list_dec xs n x )"
-
-
-definition extract_only_bit  :: "(bitU)list \<Rightarrow> bitU "  where 
-     " extract_only_bit = ( \<lambda>x .  
-  (case  x of   [] => BU | [e] => e | _ => BU ) )"
-
-
-(*** Machine words *)
-
-(*val length_mword : forall 'a. mword 'a -> integer*)
-
-(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
-definition slice_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " slice_mword_dec w i j = ( Word.slice (nat_of_int i) w )"
-
-
-(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
-definition slice_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " slice_mword_inc w i j = (
-  (let top1 = ((int (size w)) -( 1 :: int)) in
-  slice_mword_dec w (top1 - i) (top1 - j)))"
-
-
-(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*)
-definition slice_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " slice_mword is_inc w i j = ( if is_inc then slice_mword_inc w i j else slice_mword_dec w i j )"
-
-
-(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-definition update_slice_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " update_slice_mword_dec w i j w' = ( Lem.word_update w (nat_of_int i) (nat_of_int j) w' )"
-
-
-(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-definition update_slice_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " update_slice_mword_inc w i j w' = (
-  (let top1 = ((int (size w)) -( 1 :: int)) in
-  update_slice_mword_dec w (top1 - i) (top1 - j) w'))"
-
-
-(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
-definition update_slice_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " update_slice_mword is_inc w i j w' = (
-  if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w' )"
-
-
-(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*)
-definition access_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_mword_dec w n = ( bitU_of_bool (Bits.test_bit w (nat_of_int n)))"
-
-
-(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*)
-definition access_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_mword_inc w n = (
-  (let top1 = ((int (size w)) -( 1 :: int)) in
-  access_mword_dec w (top1 - n)))"
-
-
-(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*)
-definition access_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_mword is_inc w n = (
-  if is_inc then access_mword_inc w n else access_mword_dec w n )"
-
-
-(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
-definition update_mword_bool_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " update_mword_bool_dec w n b = ( Bits.set_bit w (nat_of_int n) b )"
-
-definition update_mword_dec  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " update_mword_dec w n b = ( map_option (update_mword_bool_dec w n) (bool_of_bitU b))"
-
-
-(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
-definition update_mword_bool_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word "  where 
-     " update_mword_bool_inc w n b = (
-  (let top1 = ((int (size w)) -( 1 :: int)) in
-  update_mword_bool_dec w (top1 - n) b))"
-
-definition update_mword_inc  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option "  where 
-     " update_mword_inc w n b = ( map_option (update_mword_bool_inc w n) (bool_of_bitU b))"
-
-
-(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
-definition int_of_mword  :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
-     " int_of_mword sign w = (
-  if sign then Word.sint w else Word.uint w )"
-
-
-(* Translating between a type level number (itself 'n) and an integer *)
-
-definition size_itself_int  :: "('a::len)itself \<Rightarrow> int "  where 
-     " size_itself_int x = ( int (size_itself x))"
-
-
-(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n),
-   the actual integer is ignored. *)
-
-(*val make_the_value : forall 'n. integer -> itself 'n*)
-definition make_the_value  :: " int \<Rightarrow>('n::len)itself "  where 
-     " make_the_value _ = ( TYPE(_) )"
-
-
-(*** Bitvectors *)
-
-record 'a Bitvector_class=
-
-  bits_of_method ::" 'a \<Rightarrow> bitU list " 
-
-  (* We allow of_bits to be partial, as not all bitvector representations
-     support undefined bits *)
-  of_bits_method ::" bitU list \<Rightarrow>  'a option " 
-
-  of_bools_method ::" bool list \<Rightarrow> 'a " 
-
-  length_method ::" 'a \<Rightarrow> int " 
-
-  (* of_int: the first parameter specifies the desired length of the bitvector *)
-  of_int_method ::" int \<Rightarrow> int \<Rightarrow> 'a " 
-
-  (* Conversion to integers is undefined if any bit is undefined *)
-  unsigned_method ::" 'a \<Rightarrow>  int option " 
-
-  signed_method ::" 'a \<Rightarrow>  int option " 
-
-  (* Lifting of integer operations to bitvectors:  The boolean flag indicates
-     whether to treat the bitvectors as signed (true) or not (false). *)
-  arith_op_bv_method ::" (int \<Rightarrow> int \<Rightarrow> int) \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a "
-
-
-
-(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*)
-definition of_bits_failwith  :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'a "  where 
-     " of_bits_failwith dict_Sail_values_Bitvector_a bits = ( maybe_failwith (
-  (of_bits_method   dict_Sail_values_Bitvector_a) bits))"
-
-
-definition int_of_bv  :: " 'a Bitvector_class \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow>(int)option "  where 
-     " int_of_bv dict_Sail_values_Bitvector_a sign = ( if sign then 
-  (signed_method   dict_Sail_values_Bitvector_a) else (unsigned_method   dict_Sail_values_Bitvector_a) )"
-
-
-definition instance_Sail_values_Bitvector_list_dict  :: " 'a BitU_class \<Rightarrow>('a list)Bitvector_class "  where 
-     " instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a = ((|
-
-  bits_of_method = (\<lambda> v. List.map 
-  (to_bitU_method   dict_Sail_values_BitU_a) v),
-
-  of_bits_method = (\<lambda> v. Some (List.map 
-  (of_bitU_method   dict_Sail_values_BitU_a) v)),
-
-  of_bools_method = (\<lambda> v. List.map 
-  (of_bitU_method   dict_Sail_values_BitU_a) (List.map bitU_of_bool v)),
-
-  length_method = (\<lambda> xs. int (List.length xs)),
-
-  of_int_method = (\<lambda> len n. List.map 
-  (of_bitU_method   dict_Sail_values_BitU_a) (bits_of_int len n)),
-
-  unsigned_method = (\<lambda> v. unsigned_of_bits (List.map 
-  (to_bitU_method   dict_Sail_values_BitU_a) v)),
-
-  signed_method = (\<lambda> v. signed_of_bits (List.map 
-  (to_bitU_method   dict_Sail_values_BitU_a) v)),
-
-  arith_op_bv_method = (\<lambda> op1 sign l r. List.map 
-  (of_bitU_method   dict_Sail_values_BitU_a) (arith_op_bits op1 sign (List.map 
-  (to_bitU_method   dict_Sail_values_BitU_a) l) (List.map (to_bitU_method   dict_Sail_values_BitU_a) r)))|) )"
-
-
-definition instance_Sail_values_Bitvector_Machine_word_mword_dict  :: "(('a::len)Word.word)Bitvector_class "  where 
-     " instance_Sail_values_Bitvector_Machine_word_mword_dict = ((|
-
-  bits_of_method = (\<lambda> v. List.map bitU_of_bool (Word.to_bl v)),
-
-  of_bits_method = (\<lambda> v. map_option Word.of_bl (just_list (List.map bool_of_bitU v))),
-
-  of_bools_method = (\<lambda> v. Word.of_bl v),
-
-  length_method = (\<lambda> v. int (size v)),
-
-  of_int_method = ( \<lambda>x .  
-  (case  x of _ => \<lambda> n .  Word.word_of_int n )),
-
-  unsigned_method = (\<lambda> v. Some (Word.uint v)),
-
-  signed_method = (\<lambda> v. Some (Word.sint v)),
-
-  arith_op_bv_method = (\<lambda> op1 sign l r. Word.word_of_int (op1 (int_of_mword sign l) (int_of_mword sign r)))|) )"
-
-
-definition access_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_bv_inc dict_Sail_values_Bitvector_a v n = ( access_list True  (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) n )"
-
-definition access_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU "  where 
-     " access_bv_dec dict_Sail_values_Bitvector_a v n = ( access_list False (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) n )"
-
-
-definition update_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " update_bv_inc dict_Sail_values_Bitvector_a v n b = ( update_list True  (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) n b )"
-
-definition update_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list "  where 
-     " update_bv_dec dict_Sail_values_Bitvector_a v n b = ( update_list False (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) n b )"
-
-
-definition subrange_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " subrange_bv_inc dict_Sail_values_Bitvector_a v i j = ( subrange_list True  (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) i j )"
-
-definition subrange_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " subrange_bv_dec dict_Sail_values_Bitvector_a v i j = ( subrange_list False (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v) i j )"
-
-
-definition update_subrange_bv_inc  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
-     " update_subrange_bv_inc dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list True  (
-  (bits_of_method   dict_Sail_values_Bitvector_b) v) i j ((bits_of_method   dict_Sail_values_Bitvector_a) v'))"
-
-definition update_subrange_bv_dec  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
-     " update_subrange_bv_dec dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list False (
-  (bits_of_method   dict_Sail_values_Bitvector_b) v) i j ((bits_of_method   dict_Sail_values_Bitvector_a) v'))"
-
-
-(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
-definition extz_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
-     " extz_bv dict_Sail_values_Bitvector_a n v = ( extz_bits n (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v))"
-
-
-(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
-definition exts_bv  :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list "  where 
-     " exts_bv dict_Sail_values_Bitvector_a n v = ( exts_bits n (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v))"
-
-
-(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*)
-definition string_of_bv  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string "  where 
-     " string_of_bv dict_Sail_values_Bitvector_a v = ( show_bitlist (
-  (bits_of_method   dict_Sail_values_Bitvector_a) v))"
-
-
-(*** Bytes and addresses *)
-
-type_synonym memory_byte =" bitU list "
-
-(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*)
-fun  byte_chunks  :: " 'a list \<Rightarrow>(('a list)list)option "  where 
-     " byte_chunks ([]) = ( Some [])"
-|" byte_chunks (a # b # c # d # e # f # g # h # rest) = (
-     Option.bind (byte_chunks rest) (\<lambda> rest .  Some ([a,b,c,d,e,f,g,h] # rest)))"
-|" byte_chunks _ = ( None )"
-
-
-(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*)
-definition bytes_of_bits  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option "  where 
-     " bytes_of_bits dict_Sail_values_Bitvector_a bs = ( byte_chunks (
-  (bits_of_method   dict_Sail_values_Bitvector_a) bs))"
-
-
-(*val bits_of_bytes : list memory_byte -> list bitU*)
-definition bits_of_bytes  :: "((bitU)list)list \<Rightarrow>(bitU)list "  where 
-     " bits_of_bytes bs = ( List.concat (List.map (\<lambda> v. List.map (\<lambda> b. b) v) bs))"
-
-
-definition mem_bytes_of_bits  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option "  where 
-     " mem_bytes_of_bits dict_Sail_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits 
-  dict_Sail_values_Bitvector_a bs))"
-
-definition bits_of_mem_bytes  :: "((bitU)list)list \<Rightarrow>(bitU)list "  where 
-     " bits_of_mem_bytes bs = ( bits_of_bytes (List.rev bs))"
-
-
-(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
-let bitv_of_byte_lifteds v =
-  foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v
-
-val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
-let bitv_of_bytes v =
-  foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v
-
-val byte_lifteds_of_bitv : list bitU -> list byte_lifted
-let byte_lifteds_of_bitv bits =
-  let bits = List.map bit_lifted_of_bitU bits in
-  byte_lifteds_of_bit_lifteds bits
-
-val bytes_of_bitv : list bitU -> list byte
-let bytes_of_bitv bits =
-  let bits = List.map bit_of_bitU bits in
-  bytes_of_bits bits
-
-val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
-let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits
-
-val bit_lifteds_of_bitv : list bitU -> list bit_lifted
-let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v
-
-
-val address_lifted_of_bitv : list bitU -> address_lifted
-let address_lifted_of_bitv v =
-  let byte_lifteds = byte_lifteds_of_bitv v in
-  let maybe_address_integer =
-    match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
-    | Just bs -> Just (integer_of_byte_list bs)
-    | _ -> Nothing
-    end in
-  Address_lifted byte_lifteds maybe_address_integer
-
-val bitv_of_address_lifted : address_lifted -> list bitU
-let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs
-
-val address_of_bitv : list bitU -> address
-let address_of_bitv v =
-  let bytes = bytes_of_bitv v in
-  address_of_byte_list bytes*)
-
-function (sequential,domintros)  reverse_endianness_list  :: " 'a list \<Rightarrow> 'a list "  where 
-     " reverse_endianness_list bits = (
-  if List.length bits \<le>( 8 :: nat) then bits else
-    reverse_endianness_list (drop_list(( 8 :: int)) bits) @ take_list(( 8 :: int)) bits )" 
-by pat_completeness auto
-
-
-
-(*** Registers *)
-
-(*type register_field = string
-type register_field_index = string * (integer * integer) (* name, start and end *)
-
-type register =
-  | Register of string * (* name *)
-                integer * (* length *)
-                integer * (* start index *)
-                bool * (* is increasing *)
-                  list register_field_index
-  | UndefinedRegister of integer (* length *)
-  | RegisterPair of register * register*)
-
-record( 'regstate, 'regval, 'a) register_ref =
-  
- name ::" string " 
-
-     (*is_inc : bool;*)
-     read_from ::" 'regstate \<Rightarrow> 'a " 
-
-     write_to ::" 'a \<Rightarrow> 'regstate \<Rightarrow> 'regstate " 
-
-     of_regval ::" 'regval \<Rightarrow>  'a option " 
-
-     regval_of ::" 'a \<Rightarrow> 'regval " 
-
-
-(* Register accessors: pair of functions for reading and writing register values *)
-type_synonym( 'regstate, 'regval) register_accessors ="
-  ((string \<Rightarrow> 'regstate \<Rightarrow>  'regval option) *
-   (string \<Rightarrow> 'regval \<Rightarrow> 'regstate \<Rightarrow>  'regstate option))"
-
-record( 'regtype, 'a) field_ref =
-  
- field_name ::" string " 
-
-     field_start ::" int " 
-
-     field_is_inc ::" bool " 
-
-     get_field ::" 'regtype \<Rightarrow> 'a " 
-
-     set_field ::" 'regtype \<Rightarrow> 'a \<Rightarrow> 'regtype " 
-
-
-(*let name_of_reg = function
-  | Register name _ _ _ _ -> name
-  | UndefinedRegister _ -> failwith name_of_reg UndefinedRegister
-  | RegisterPair _ _ -> failwith name_of_reg RegisterPair
-end
-
-let size_of_reg = function
-  | Register _ size _ _ _ -> size
-  | UndefinedRegister size -> size
-  | RegisterPair _ _ -> failwith size_of_reg RegisterPair
-end
-
-let start_of_reg = function
-  | Register _ _ start _ _ -> start
-  | UndefinedRegister _ -> failwith start_of_reg UndefinedRegister
-  | RegisterPair _ _ -> failwith start_of_reg RegisterPair
-end
-
-let is_inc_of_reg = function
-  | Register _ _ _ is_inc _ -> is_inc
-  | UndefinedRegister _ -> failwith is_inc_of_reg UndefinedRegister
-  | RegisterPair _ _ -> failwith in_inc_of_reg RegisterPair
-end
-
-let dir_of_reg = function
-  | Register _ _ _ is_inc _ -> dir_of_bool is_inc
-  | UndefinedRegister _ -> failwith dir_of_reg UndefinedRegister
-  | RegisterPair _ _ -> failwith dir_of_reg RegisterPair
-end
-
-let size_of_reg_nat reg = natFromInteger (size_of_reg reg)
-let start_of_reg_nat reg = natFromInteger (start_of_reg reg)
-
-val register_field_indices_aux : register -> register_field -> maybe (integer * integer)
-let rec register_field_indices_aux register rfield =
-  match register with
-  | Register _ _ _ _ rfields -> List.lookup rfield rfields
-  | RegisterPair r1 r2 ->
-      let m_indices = register_field_indices_aux r1 rfield in
-      if isJust m_indices then m_indices else register_field_indices_aux r2 rfield
-  | UndefinedRegister _ -> Nothing
-  end
-
-val register_field_indices : register -> register_field -> integer * integer
-let register_field_indices register rfield =
-  match register_field_indices_aux register rfield with
-  | Just indices -> indices
-  | Nothing -> failwith Invalid register/register-field combination
-  end
-
-let register_field_indices_nat reg regfield=
-  let (i,j) = register_field_indices reg regfield in
-  (natFromInteger i,natFromInteger j)*)
-
-(*let rec external_reg_value reg_name v =
-  let (internal_start, external_start, direction) =
-    match reg_name with
-     | Reg _ start size dir ->
-        (start, (if dir = D_increasing then start else (start - (size +1))), dir)
-     | Reg_slice _ reg_start dir (slice_start, _) ->
-        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
-         slice_start, dir)
-     | Reg_field _ reg_start dir _ (slice_start, _) ->
-        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
-         slice_start, dir)
-     | Reg_f_slice _ reg_start dir _ _ (slice_start, _) ->
-        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
-         slice_start, dir)
-     end in
-  let bits = bit_lifteds_of_bitv v in
-  <| rv_bits           = bits;
-     rv_dir            = direction;
-     rv_start          = external_start;
-     rv_start_internal = internal_start |>
-
-val internal_reg_value : register_value -> list bitU
-let internal_reg_value v =
-  List.map bitU_of_bit_lifted v.rv_bits
-         (*(integerFromNat v.rv_start_internal)
-         (v.rv_dir = D_increasing)*)
-
-
-let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) =
-  match d with
-  (*This is the case the thread/concurrecny model expects, so no change needed*)
-  | D_increasing -> (i,j)
-  | D_decreasing -> let slice_i = start - i in
-                    let slice_j = (i - j) + slice_i in
-                    (slice_i,slice_j)
-  end *)
-
-(* TODO
-let external_reg_whole r =
-  Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc)
-
-let external_reg_slice r (i,j) =
-  let start = natFromInteger r.start in
-  let dir = dir_of_bool r.is_inc in
-  Reg_slice (r.name) start dir (external_slice dir start (i,j))
-
-let external_reg_field_whole reg rfield =
-  let (m,n) = register_field_indices_nat reg rfield in
-  let start = start_of_reg_nat reg in
-  let dir = dir_of_reg reg in
-  Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
-
-let external_reg_field_slice reg rfield (i,j) =
-  let (m,n) = register_field_indices_nat reg rfield in
-  let start = start_of_reg_nat reg in
-  let dir = dir_of_reg reg in
-  Reg_f_slice (name_of_reg reg) start dir rfield
-              (external_slice dir start (m,n))
-              (external_slice dir start (i,j))*)
-
-(*val external_mem_value : list bitU -> memory_value
-let external_mem_value v =
-  byte_lifteds_of_bitv v $> List.reverse
-
-val internal_mem_value : memory_value -> list bitU
-let internal_mem_value bytes =
-  List.reverse bytes $> bitv_of_byte_lifteds*)
-
-
-(*val foreach : forall 'a 'vars.
-  (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*)
-fun  foreach  :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'vars)\<Rightarrow> 'vars "  where 
-     " foreach ([]) vars body = ( vars )"
-|" foreach (x # xs) vars body = ( foreach xs (body x vars) body )"
-
-
-(*val index_list : integer -> integer -> integer -> list integer*)
-function (sequential,domintros)  index_list  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)list "  where 
-     " index_list from1 to1 step = (
-  if ((step >( 0 :: int)) \<and> (from1 \<le> to1)) \<or> ((step <( 0 :: int)) \<and> (to1 \<le> from1)) then
-    from1 # index_list (from1 + step) to1 step
-  else [])" 
-by pat_completeness auto
-
-
-(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
-function (sequential,domintros)  while  :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars "  where 
-     " while vars cond body = (
-  if cond vars then while (body vars) cond body else vars )" 
-by pat_completeness auto
-
-
-(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
-function (sequential,domintros)  until  :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars "  where 
-     " until vars cond body = (
-  (let vars = (body vars) in
-  if cond vars then vars else until (body vars) cond body))" 
-by pat_completeness auto
-
-
-
-(* convert numbers unsafely to naturals *)
-
-record 'a ToNatural_class=
- toNatural_method ::" 'a \<Rightarrow> nat " 
-
-(* eta-expanded for Isabelle output, otherwise it breaks *)
-definition instance_Sail_values_ToNatural_Num_integer_dict  :: "(int)ToNatural_class "  where 
-     " instance_Sail_values_ToNatural_Num_integer_dict = ((|
-
-  toNatural_method = (\<lambda> n .  nat (abs n))|) )"
-
-definition instance_Sail_values_ToNatural_Num_int_dict  :: "(int)ToNatural_class "  where 
-     " instance_Sail_values_ToNatural_Num_int_dict = ((|
-
-  toNatural_method = (\<lambda> n .   (nat (abs n)))|) )"
-
-definition instance_Sail_values_ToNatural_nat_dict  :: "(nat)ToNatural_class "  where 
-     " instance_Sail_values_ToNatural_nat_dict = ((|
-
-  toNatural_method = (\<lambda> n .   n)|) )"
-
-definition instance_Sail_values_ToNatural_Num_natural_dict  :: "(nat)ToNatural_class "  where 
-     " instance_Sail_values_ToNatural_Num_natural_dict = ((|
-
-  toNatural_method = (\<lambda> n .  n)|) )"
-
-
-fun toNaturalFiveTup  :: " 'a ToNatural_class \<Rightarrow> 'b ToNatural_class \<Rightarrow> 'c ToNatural_class \<Rightarrow> 'd ToNatural_class \<Rightarrow> 'e ToNatural_class \<Rightarrow> 'd*'c*'b*'a*'e \<Rightarrow> nat*nat*nat*nat*nat "  where 
-     " toNaturalFiveTup dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5) = (
-  ((toNatural_method   dict_Sail_values_ToNatural_d) n1,(toNatural_method   dict_Sail_values_ToNatural_c) n2,(toNatural_method   dict_Sail_values_ToNatural_b) n3,(toNatural_method   dict_Sail_values_ToNatural_a) n4,(toNatural_method   dict_Sail_values_ToNatural_e) n5))"
-
-
-(* Let the following types be generated by Sail per spec, using either bitlists
-   or machine words as bitvector representation *)
-(*type regfp =
-  | RFull of (string)
-  | RSlice of (string * integer * integer)
-  | RSliceBit of (string * integer)
-  | RField of (string * string)
-
-type niafp =
-  | NIAFP_successor
-  | NIAFP_concrete_address of vector bitU
-  | NIAFP_indirect_address
-
-(* only for MIPS *)
-type diafp =
-  | DIAFP_none
-  | DIAFP_concrete of vector bitU
-  | DIAFP_reg of regfp
-
-let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function
-  | RFull name ->
-     let (start,length,direction,_) = reg_info name Nothing in
-     Reg name start length direction
-  | RSlice (name,i,j) ->
-     let i = natFromInteger i in
-     let j = natFromInteger j in
-     let (start,length,direction,_) = reg_info name Nothing in
-     let slice = external_slice direction start (i,j) in
-     Reg_slice name start direction slice
-  | RSliceBit (name,i) ->
-     let i = natFromInteger i in
-     let (start,length,direction,_) = reg_info name Nothing in
-     let slice = external_slice direction start (i,i) in
-     Reg_slice name start direction slice
-  | RField (name,field_name) ->
-     let (start,length,direction,span) = reg_info name (Just field_name) in
-     let slice = external_slice direction start span in
-     Reg_field name start direction field_name slice
-end
-
-let niafp_to_nia reginfo = function
-  | NIAFP_successor -> NIA_successor
-  | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v)
-  | NIAFP_indirect_address -> NIA_indirect_address
-end
-
-let diafp_to_dia reginfo = function
-  | DIAFP_none -> DIA_none
-  | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v)
-  | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r)
-end
-*)
-end
diff --git a/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy
deleted file mode 100644
index dd008695..00000000
--- a/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy
+++ /dev/null
@@ -1,206 +0,0 @@
-theory Sail_values_lemmas
-  imports Sail_values
-begin
-
-lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def)
-
-termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def)
-
-termination index_list
-  by (relation "measure (\<lambda>(i, j, step). nat ((j - i + step) * sgn step))") auto
-
-lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto
-
-lemma just_list_None_iff[simp]: "just_list xs = None \<longleftrightarrow> None \<in> set xs"
-  by (induction xs) (auto split: option.splits)
-
-lemma just_list_Some_iff[simp]: "just_list xs = Some ys \<longleftrightarrow> xs = map Some ys"
-  by (induction xs arbitrary: ys) (auto split: option.splits)
-
-lemma just_list_cases:
-  assumes "just_list xs = y"
-  obtains (None) "None \<in> set xs" and "y = None"
-        | (Some) ys where "xs = map Some ys" and "y = Some ys"
-  using assms by (cases y) auto
-
-lemma repeat_singleton_replicate[simp]:
-  "repeat [x] n = replicate (nat n) x"
-proof (induction n)
-  case (nonneg n)
-  have "nat (1 + int m) = Suc m" for m by auto
-  then show ?case by (induction n) auto
-next
-  case (neg n)
-  then show ?case by auto
-qed
-
-lemma bool_of_bitU_simps[simp]:
-  "bool_of_bitU B0 = Some False"
-  "bool_of_bitU B1 = Some True"
-  "bool_of_bitU BU = None"
-  by (auto simp: bool_of_bitU_def)
-
-lemma bitops_bitU_of_bool[simp]:
-  "and_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<and> y)"
-  "or_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<or> y)"
-  "xor_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool ((x \<or> y) \<and> \<not>(x \<and> y))"
-  "not_bit (bitU_of_bool x) = bitU_of_bool (\<not>x)"
-  "not_bit \<circ> bitU_of_bool = bitU_of_bool \<circ> Not"
-  by (auto simp: bitU_of_bool_def not_bit_def)
-
-lemma image_bitU_of_bool_B0_B1: "bitU_of_bool ` bs \<subseteq> {B0, B1}"
-  by (auto simp: bitU_of_bool_def split: if_splits)
-
-lemma bool_of_bitU_bitU_of_bool[simp]:
-  "bool_of_bitU \<circ> bitU_of_bool = Some"
-  "bool_of_bitU \<circ> (bitU_of_bool \<circ> f) = Some \<circ> f"
-  "bool_of_bitU (bitU_of_bool x) = Some x"
-  by (intro ext, auto simp: bool_of_bitU_def bitU_of_bool_def)+
-
-abbreviation "BC_bitU_list \<equiv> instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict"
-lemmas BC_bitU_list_def = instance_Sail_values_Bitvector_list_dict_def instance_Sail_values_BitU_Sail_values_bitU_dict_def
-abbreviation "BC_mword \<equiv> instance_Sail_values_Bitvector_Machine_word_mword_dict"
-lemmas BC_mword_defs = instance_Sail_values_Bitvector_Machine_word_mword_dict_def
-  access_mword_def access_mword_inc_def access_mword_dec_def
-  (*update_mword_def update_mword_inc_def update_mword_dec_def*)
-  subrange_list_def subrange_list_inc_def subrange_list_dec_def
-  update_subrange_list_def update_subrange_list_inc_def update_subrange_list_dec_def
-
-declare size_itself_int_def[simp]
-declare size_itself_def[simp]
-declare word_size[simp]
-
-lemma int_of_mword_simps[simp]:
-  "int_of_mword False w = uint w"
-  "int_of_mword True w = sint w"
-  "int_of_bv BC_mword False w = Some (uint w)"
-  "int_of_bv BC_mword True w = Some (sint w)"
-  by (auto simp: int_of_mword_def int_of_bv_def BC_mword_defs)
-
-lemma BC_mword_simps[simp]:
-  "unsigned_method BC_mword a = Some (uint a)"
-  "signed_method BC_mword a = Some (sint a)"
-  "length_method BC_mword (a :: ('a :: len) word) = int (LENGTH('a))"
-  by (auto simp: BC_mword_defs)
-
-lemma of_bits_mword_of_bl[simp]:
-  assumes "just_list (map bool_of_bitU bus) = Some bs"
-  shows "of_bits_method BC_mword bus = Some (of_bl bs)"
-    and "of_bits_failwith BC_mword bus = of_bl bs"
-  using assms by (auto simp: BC_mword_defs of_bits_failwith_def maybe_failwith_def)
-
-lemma nat_of_bits_aux_bl_to_bin_aux:
-  "nat_of_bools_aux acc bs = nat (bl_to_bin_aux bs (int acc))"
-  by (induction acc bs rule: nat_of_bools_aux.induct)
-     (auto simp: Bit_def intro!: arg_cong[where f = nat] arg_cong2[where f = bl_to_bin_aux] split: if_splits)
-
-lemma nat_of_bits_bl_to_bin[simp]:
-  "nat_of_bools bs = nat (bl_to_bin bs)"
-  by (auto simp: nat_of_bools_def bl_to_bin_def nat_of_bits_aux_bl_to_bin_aux)
-
-lemma unsigned_bits_of_mword[simp]:
-  "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)"
-  by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def)
-
-lemma bits_of_bitU_list[simp]:
-  "bits_of_method BC_bitU_list v = v"
-  "of_bits_method BC_bitU_list v = Some v"
-  by (auto simp: BC_bitU_list_def)
-
-lemma subrange_list_inc_drop_take:
-  "subrange_list_inc xs i j = drop (nat i) (take (nat (j + 1)) xs)"
-  by (auto simp: subrange_list_inc_def split_at_def)
-
-lemma subrange_list_dec_drop_take:
-  assumes "i \<ge> 0" and "j \<ge> 0"
-  shows "subrange_list_dec xs i j = drop (length xs - nat (i + 1)) (take (length xs - nat j) xs)"
-  using assms unfolding subrange_list_dec_def
-  by (auto simp: subrange_list_inc_drop_take add.commute diff_diff_add nat_minus_as_int)
-
-lemma update_subrange_list_inc_drop_take:
-  assumes "i \<ge> 0" and "j \<ge> i"
-  shows "update_subrange_list_inc xs i j xs' = take (nat i) xs @ xs' @ drop (nat (j + 1)) xs"
-  using assms unfolding update_subrange_list_inc_def
-  by (auto simp: split_at_def min_def)
-
-lemma update_subrange_list_dec_drop_take:
-  assumes "j \<ge> 0" and "i \<ge> j"
-  shows "update_subrange_list_dec xs i j xs' = take (length xs - nat (i + 1)) xs @ xs' @ drop (length xs - nat j) xs"
-  using assms unfolding update_subrange_list_dec_def update_subrange_list_inc_def
-  by (auto simp: split_at_def min_def Let_def add.commute diff_diff_add nat_minus_as_int)
-
-declare access_list_inc_def[simp]
-
-lemma access_list_dec_rev_nth:
-  assumes "0 \<le> i" and "nat i < length xs"
-  shows "access_list_dec xs i = rev xs ! (nat i)"
-  using assms
-  by (auto simp: access_list_dec_def rev_nth intro!: arg_cong2[where f = List.nth])
-
-lemma access_bv_dec_mword[simp]:
-  fixes w :: "('a::len) word"
-  assumes "0 \<le> n" and "nat n < LENGTH('a)"
-  shows "access_bv_dec BC_mword w n = bitU_of_bool (w !! (nat n))"
-  using assms unfolding access_bv_dec_def access_list_def
-  by (auto simp: access_list_dec_rev_nth BC_mword_defs rev_map test_bit_bl)
-
-lemma access_list_dec_nth[simp]:
-  assumes "0 \<le> i"
-  shows "access_list_dec xs i = xs ! (length xs - nat (i + 1))"
-  using assms
-  by (auto simp: access_list_dec_def add.commute diff_diff_add nat_minus_as_int)
-
-lemma update_list_inc_update[simp]:
-  "update_list_inc xs n x = xs[nat n := x]"
-  by (auto simp: update_list_inc_def)
-
-lemma update_list_dec_update[simp]:
-  "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]"
-  by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int)
-
-lemma bools_of_nat_aux_simps[simp]:
-  "\<And>len. len \<le> 0 \<Longrightarrow> bools_of_nat_aux len x acc = acc"
-  "\<And>len. bools_of_nat_aux (int (Suc len)) x acc =
-     bools_of_nat_aux (int len) (x div 2) ((if x mod 2 = 1 then True else False) # acc)"
-  by auto
-declare bools_of_nat_aux.simps[simp del]
-
-lemma bools_of_nat_aux_bin_to_bl_aux:
-  "bools_of_nat_aux len n acc = bin_to_bl_aux (nat len) (int n) acc"
-proof (cases len)
-  case (nonneg len')
-  show ?thesis unfolding nonneg
-  proof (induction len' arbitrary: n acc)
-    case (Suc len'' n acc)
-    then show ?case
-      using zmod_int[of n 2]
-      by (auto simp del: of_nat_simps simp add: bin_rest_def bin_last_def zdiv_int)
-  qed auto
-qed auto
-
-lemma bools_of_nat_bin_to_bl[simp]:
-  "bools_of_nat len n = bin_to_bl (nat len) (int n)"
-  by (auto simp: bools_of_nat_def bools_of_nat_aux_bin_to_bl_aux)
-
-lemma add_one_bool_ignore_overflow_aux_rbl_succ[simp]:
-  "add_one_bool_ignore_overflow_aux xs = rbl_succ xs"
-  by (induction xs) auto
-
-lemma add_one_bool_ignore_overflow_rbl_succ[simp]:
-  "add_one_bool_ignore_overflow xs = rev (rbl_succ (rev xs))"
-  unfolding add_one_bool_ignore_overflow_def by auto
-
-lemma map_Not_bin_to_bl:
-  "map Not (bin_to_bl_aux len n acc) = bin_to_bl_aux len (-n - 1) (map Not acc)"
-proof (induction len arbitrary: n acc)
-  case (Suc len n acc)
-  moreover have "(- (n div 2) - 1) = ((-n - 1) div 2)" by auto
-  moreover have "(n mod 2 = 0) = ((- n - 1) mod 2 = 1)" by presburger
-  ultimately show ?case by (auto simp: bin_rest_def bin_last_def)
-qed auto
-
-lemma bools_of_int_bin_to_bl[simp]:
-  "bools_of_int (int len) n = bin_to_bl len n"
-  by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def])
-
-end
diff --git a/snapshots/isabelle/lib/sail/State.thy b/snapshots/isabelle/lib/sail/State.thy
deleted file mode 100644
index 9d460e8e..00000000
--- a/snapshots/isabelle/lib/sail/State.thy
+++ /dev/null
@@ -1,102 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/state.lem.\<close>
-
-theory "State" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Sail_values" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State_monad" 
-	 "State_monad_lemmas" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Sail_impl_base*)
-(*open import Sail_values*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State_monad*)
-(*open import {isabelle} `State_monad_lemmas`*)
-
-(* State monad wrapper around prompt monad *)
-
-(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*)
-function (sequential,domintros)  liftState  :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval,'a,'e)monad \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " liftState ra (Done a) = ( returnS a )"
-|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) rk a sz) (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Read_tag t k) = ( bindS (read_tagS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) t)             (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Write_memv a k) = ( bindS (write_mem_bytesS a)      (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Write_tag a t k) = ( bindS (write_tagS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) a t)          (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r)       (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Excl_res k) = ( bindS (excl_resultS () )         (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Undefined k) = ( bindS (undefined_boolS () )      (\<lambda> v .  liftState ra (k v)))"
-|" liftState ra (Write_ea wk a sz k) = ( seqS (write_mem_eaS 
-  (instance_Sail_values_Bitvector_list_dict
-     instance_Sail_values_BitU_Sail_values_bitU_dict) wk a sz)    (liftState ra k))"
-|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v)     (liftState ra k))"
-|" liftState ra (Footprint k) = ( liftState ra k )"
-|" liftState ra (Barrier _ k) = ( liftState ra k )"
-|" liftState ra (Print _ k) = ( liftState ra k )"
-|" liftState ra (Fail descr) = ( failS descr )"
-|" liftState ra (Exception e) = ( throwS e )" 
-by pat_completeness auto
-
-
-
-(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
-fun  iterS_aux  :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monadS "  where 
-     " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))"
-|" iterS_aux i f ([]) = ( returnS ()  )"
-
-
-(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
-definition iteriS  :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monadS)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set "  where 
-     " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )"
-
-
-(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
-definition iterS  :: "('a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set "  where 
-     " iterS f xs = ( iteriS ( \<lambda>x .  
-  (case  x of _ => \<lambda> x .  f x )) xs )"
-
-
-(*val foreachS : forall 'a 'rv 'vars 'e.
-  list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
-fun  foreachS  :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set "  where 
-     " foreachS ([]) vars body = ( returnS vars )"
-|" foreachS (x # xs) vars body = ( bindS
-     (body x vars) (\<lambda> vars . 
-     foreachS xs vars body))"
-
-
-
-(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
-                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
-function (sequential,domintros)  whileS  :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set "  where 
-     " whileS vars cond body s = (
-  ( bindS(cond vars) (\<lambda> cond_val s' . 
-  if cond_val then
-    ( bindS(body vars) (\<lambda> vars s'' .  whileS vars cond body s'')) s'
-  else returnS vars s')) s )" 
-by pat_completeness auto
-
-
-(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
-                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
-function (sequential,domintros)  untilS  :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set "  where 
-     " untilS vars cond body s = (
-  ( bindS(body vars) (\<lambda> vars s' . 
-  ( bindS(cond vars) (\<lambda> cond_val s'' . 
-  if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )" 
-by pat_completeness auto
-
-end
diff --git a/snapshots/isabelle/lib/sail/State_lemmas.thy b/snapshots/isabelle/lib/sail/State_lemmas.thy
deleted file mode 100644
index 84b08e6c..00000000
--- a/snapshots/isabelle/lib/sail/State_lemmas.thy
+++ /dev/null
@@ -1,202 +0,0 @@
-theory State_lemmas
-  imports State
-begin
-
-lemma All_liftState_dom: "liftState_dom (r, m)"
-  by (induction m) (auto intro: liftState.domintros)
-termination liftState using All_liftState_dom by auto
-
-lemma liftState_bind[simp]:
-  "liftState r (bind m f) = bindS (liftState r m) (liftState r \<circ> f)"
-  by (induction m f rule: bind.induct) auto
-
-lemma liftState_return[simp]: "liftState r (return a) = returnS a" by (auto simp: return_def)
-
-lemma Value_liftState_Run:
-  assumes "(Value a, s') \<in> liftState r m s"
-  obtains t where "Run m t a"
-  by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>;
-      auto simp add: failS_def throwS_def returnS_def simp del: read_regvalS.simps;
-      blast elim: Value_bindS_elim)
-
-lemmas liftState_if_distrib[simp] = if_distrib[where f = "liftState ra" for ra]
-
-lemma liftState_throw[simp]: "liftState r (throw e) = throwS e" by (auto simp: throw_def)
-lemma liftState_assert[simp]: "liftState r (assert_exp c msg) = assert_expS c msg" by (auto simp: assert_exp_def assert_expS_def)
-lemma liftState_exit[simp]: "liftState r (exit0 ()) = exitS ()" by (auto simp: exit0_def exitS_def)
-lemma liftState_exclResult[simp]: "liftState r (excl_result ()) = excl_resultS ()" by (auto simp: excl_result_def)
-lemma liftState_barrier[simp]: "liftState r (barrier bk) = returnS ()" by (auto simp: barrier_def)
-lemma liftState_footprint[simp]: "liftState r (footprint ()) = returnS ()" by (auto simp: footprint_def)
-lemma liftState_undefined[simp]: "liftState r (undefined_bool ()) = undefined_boolS ()" by (auto simp: undefined_bool_def)
-lemma liftState_maybe_fail[simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x"
-  by (auto simp: maybe_fail_def maybe_failS_def split: option.splits)
-
-lemma liftState_try_catch[simp]:
-  "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \<circ> h)"
-  by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw)
-
-lemma liftState_early_return[simp]:
-  "liftState r (early_return r) = early_returnS r"
-  by (auto simp: early_return_def early_returnS_def)
-
-lemma liftState_catch_early_return[simp]:
-  "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)"
-  by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib cong: sum.case_cong)
-
-lemma liftState_liftR[simp]:
-  "liftState r (liftR m) = liftSR (liftState r m)"
-  by (auto simp: liftR_def liftSR_def)
-
-lemma liftState_try_catchR[simp]:
-  "liftState r (try_catchR m h) = try_catchSR (liftState r m) (liftState r \<circ> h)"
-  by (auto simp: try_catchR_def try_catchSR_def sum.case_distrib cong: sum.case_cong)
-
-lemma liftState_read_mem_BC:
-  assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a"
-  shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz"
-  using assms
-  by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def split: option.splits)
-
-lemma liftState_read_mem[simp]:
-  "\<And>a. liftState r (read_mem BC_mword BC_mword rk a sz) = read_memS BC_mword BC_mword rk a sz"
-  "\<And>a. liftState r (read_mem BC_bitU_list BC_bitU_list rk a sz) = read_memS BC_bitU_list BC_bitU_list rk a sz"
-  by (auto simp: liftState_read_mem_BC)
-
-lemma liftState_write_mem_ea_BC:
-  assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a"
-  shows "liftState r (write_mem_ea BCa rk a sz) = write_mem_eaS BCa rk a (nat sz)"
-  using assms by (auto simp: write_mem_ea_def write_mem_eaS_def)
-
-lemma liftState_write_mem_ea[simp]:
-  "\<And>a. liftState r (write_mem_ea BC_mword rk a sz) = write_mem_eaS BC_mword rk a (nat sz)"
-  "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)"
-  by (auto simp: liftState_write_mem_ea_BC)
-
-lemma liftState_write_mem_val:
-  "liftState r (write_mem_val BC v) = write_mem_valS BC v"
-  by (auto simp: write_mem_val_def write_mem_valS_def split: option.splits)
-
-lemma liftState_read_reg_readS:
-  assumes "\<And>s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)"
-  shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \<circ> regstate)"
-proof
-  fix s :: "'a sequential_state"
-  obtain rv v where "get_regval' (name reg) (regstate s) = Some rv"
-    and "of_regval reg rv \<equiv> Some v" and "read_from reg (regstate s) = v"
-    using assms unfolding bind_eq_Some_conv by blast
-  then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \<circ> regstate) s"
-    by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def)
-qed
-
-lemma liftState_write_reg_updateS:
-  assumes "\<And>s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)"
-  shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))"
-  using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS)
-
-lemma liftState_iter_aux[simp]:
-  shows "liftState r (iter_aux i f xs) = iterS_aux i (\<lambda>i x. liftState r (f i x)) xs"
-  by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct) (auto cong: bindS_cong)
-
-lemma liftState_iteri[simp]:
-  "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs"
-  by (auto simp: iteri_def iteriS_def)
-
-lemma liftState_iter[simp]:
-  "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs"
-  by (auto simp: iter_def iterS_def)
-
-lemma liftState_foreachM[simp]:
-  "liftState r (foreachM xs vars body) = foreachS xs vars (\<lambda>x vars. liftState r (body x vars))"
-  by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct)
-     (auto cong: bindS_cong)
-
-lemma whileS_dom_step:
-  assumes "whileS_dom (vars, cond, body, s)"
-    and "(Value True, s') \<in> cond vars s"
-    and "(Value vars', s'') \<in> body vars s'"
-  shows "whileS_dom (vars', cond, body, s'')"
-  by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>)
-     (auto intro: whileS.domintros)
-
-lemma whileM_dom_step:
-  assumes "whileM_dom (vars, cond, body)"
-    and "Run (cond vars) t True"
-    and "Run (body vars) t' vars'"
-  shows "whileM_dom (vars', cond, body)"
-  by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>)
-     (auto intro: whileM.domintros)
-
-lemma whileM_dom_ex_step:
-  assumes "whileM_dom (vars, cond, body)"
-    and "\<exists>t. Run (cond vars) t True"
-    and "\<exists>t'. Run (body vars) t' vars'"
-  shows "whileM_dom (vars', cond, body)"
-  using assms by (blast intro: whileM_dom_step)
-
-lemmas whileS_pinduct = whileS.pinduct[case_names Step]
-
-lemma liftState_whileM:
-  assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
-    and "whileM_dom (vars, cond, body)"
-  shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
-proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>)
-  case Step: (1 vars s)
-  note domS = Step(1) and IH = Step(2) and domM = Step(3)
-  show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind
-  proof (intro bindS_ext_cong, goal_cases cond while)
-    case (while a s')
-    have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' =
-          bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'"
-      if "a"
-    proof (intro bindS_ext_cong, goal_cases body while')
-      case (while' vars' s'')
-      have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM])
-        show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run)
-        show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run)
-      qed
-      then show ?case using while while' that IH by auto
-    qed auto
-    then show ?case by auto
-  qed auto
-qed
-
-
-lemma untilM_dom_step:
-  assumes "untilM_dom (vars, cond, body)"
-    and "Run (body vars) t vars'"
-    and "Run (cond vars') t' False"
-  shows "untilM_dom (vars', cond, body)"
-  by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>)
-     (auto intro: untilM.domintros)
-
-lemma untilM_dom_ex_step:
-  assumes "untilM_dom (vars, cond, body)"
-    and "\<exists>t. Run (body vars) t vars'"
-    and "\<exists>t'. Run (cond vars') t' False"
-  shows "untilM_dom (vars', cond, body)"
-  using assms by (blast intro: untilM_dom_step)
-
-lemma liftState_untilM:
-  assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
-    and "untilM_dom (vars, cond, body)"
-  shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
-proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>)
-  case Step: (1 vars s)
-  note domS = Step(1) and IH = Step(2) and domM = Step(3)
-  show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind
-  proof (intro bindS_ext_cong, goal_cases body k)
-    case (k vars' s')
-    show ?case unfolding comp_def liftState_bind
-    proof (intro bindS_ext_cong, goal_cases cond until)
-      case (until a s'')
-      have "untilM_dom (vars', cond, body)" if "\<not>a"
-      proof (rule untilM_dom_ex_step[OF domM])
-        show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run)
-        show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run)
-      qed
-      then show ?case using k until IH by (auto simp: comp_def)
-    qed auto
-  qed auto
-qed
-
-end
diff --git a/snapshots/isabelle/lib/sail/State_monad.thy b/snapshots/isabelle/lib/sail/State_monad.thy
deleted file mode 100644
index 8e19f0b6..00000000
--- a/snapshots/isabelle/lib/sail/State_monad.thy
+++ /dev/null
@@ -1,375 +0,0 @@
-chapter \<open>Generated by Lem from ../../src/gen_lib/state_monad.lem.\<close>
-
-theory "State_monad" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-
-begin 
-
-(*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-
-(* 'a is result type *)
-
-type_synonym memstate =" (int, memory_byte) Map.map "
-type_synonym tagstate =" (int, bitU) Map.map "
-(* type regstate = map string (vector bitU) *)
-
-record 'regs sequential_state =
-  
- regstate ::" 'regs " 
-
-     memstate ::" memstate " 
-
-     tagstate ::" tagstate " 
-
-     write_ea ::"  (write_kind * int * int)option " 
-
-     last_exclusive_operation_was_load ::" bool " 
-
-     (* Random bool generator for use as an undefined bit oracle *)
-     next_bool ::" nat \<Rightarrow> (bool * nat)" 
-
-     seed ::" nat " 
-
-
-(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*)
-definition init_state  :: " 'regs \<Rightarrow>(nat \<Rightarrow> bool*nat)\<Rightarrow> nat \<Rightarrow> 'regs sequential_state "  where 
-     " init_state regs o1 s = (
-  (| regstate = regs,
-     memstate = Map.empty,
-     tagstate = Map.empty,
-     write_ea = None,
-     last_exclusive_operation_was_load = False,
-     next_bool = o1,
-     seed = s |) )"
-
-
-datatype 'e ex =
-    Failure " string "
-  | Throw " 'e "
-
-datatype( 'a, 'e) result =
-    Value " 'a "
-  | Ex " ( 'e ex)"
-
-(* State, nondeterminism and exception monad with result value type 'a
-   and exception type 'e. *)
-type_synonym( 'regs, 'a, 'e) monadS =" 'regs sequential_state \<Rightarrow> ( ('a, 'e)result * 'regs sequential_state) set "
-
-(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*)
-definition returnS  :: " 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " returnS a s = ( {(Value a,s)})"
-
-
-(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*)
-definition bindS  :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow>('a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set "  where 
-     " bindS m f (s :: 'regs sequential_state) = (
-  \<Union> (Set.image (\<lambda>x .  
-  (case  x of   (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s)))"
-
-
-(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*)
-definition seqS  :: "('regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set)\<Rightarrow>('regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set "  where 
-     " seqS m n = ( bindS m ( \<lambda>x .  
-  (case  x of (_ :: unit) => n )))"
-
-
-(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*)
-definition chooseS  :: " 'a set \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " chooseS xs s = ( Set.image (\<lambda> x .  (Value x, s)) xs )"
-
-
-(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*)
-definition readS  :: "('regs sequential_state \<Rightarrow> 'a)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " readS f = ( (\<lambda> s .  returnS (f s) s))"
-
-
-(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*)
-definition updateS  :: "('regs sequential_state \<Rightarrow> 'regs sequential_state)\<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set "  where 
-     " updateS f = ( (\<lambda> s .  returnS ()  (f s)))"
-
-
-(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*)
-definition failS  :: " string \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " failS msg s = ( {(Ex (Failure msg), s)})"
-
-
-(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*)
-definition undefined_boolS  :: " unit \<Rightarrow>('regs,(bool),'e)monadS "  where 
-     " undefined_boolS _ = ( bindS
-  (readS (\<lambda> s . (next_bool   s) ((seed   s)))) ( \<lambda>x .  
-  (case  x of
-      (b, seed1) => seqS (updateS (\<lambda> s .  ( s (| seed := seed1 |))))
-                      (returnS b)
-  )))"
-
-
-(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*)
-definition exitS  :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " exitS _ = ( failS (''exit''))"
-
-
-(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*)
-definition throwS  :: " 'e \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " throwS e s = ( {(Ex (Throw e), s)})"
-
-
-(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) ->  monadS 'regs 'a 'e2*)
-definition try_catchS  :: "('regs sequential_state \<Rightarrow>(('a,'e1)result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set "  where 
-     " try_catchS m h s = (
-  \<Union> (Set.image (\<lambda>x .  
-  (case  x of
-        (Value a, s') => returnS a s'
-    | (Ex (Throw e), s') => h e s'
-    | (Ex (Failure msg), s') => {(Ex (Failure msg), s')}
-  )) (m s)))"
-
-
-(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*)
-definition assert_expS  :: " bool \<Rightarrow> string \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set "  where 
-     " assert_expS exp msg = ( if exp then returnS ()  else failS msg )"
-
-
-(* For early return, we abuse exceptions by throwing and catching
-   the return value. The exception type is either 'r 'e, where Right e
-   represents a proper exception and Left r an early return of value r. *)
-type_synonym( 'regs, 'a, 'r, 'e) monadSR =" ('regs, 'a, ( ('r, 'e)sum)) monadS "
-
-(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e*)
-definition early_returnS  :: " 'r \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set "  where 
-     " early_returnS r = ( throwS (Inl r))"
-
-
-(*val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e*)
-definition catch_early_returnS  :: "('regs sequential_state \<Rightarrow>(('a,(('a,'e)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " catch_early_returnS m = (
-  try_catchS m
-    (\<lambda>x .  (case  x of   Inl a => returnS a | Inr e => throwS e )))"
-
-
-(* Lift to monad with early return by wrapping exceptions *)
-(*val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e*)
-definition liftSR  :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set "  where 
-     " liftSR m = ( try_catchS m (\<lambda> e .  throwS (Inr e)))"
-
-
-(* Catch exceptions in the presence of early returns *)
-(*val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) ->  monadSR 'regs 'a 'r 'e2*)
-definition try_catchSR  :: "('regs sequential_state \<Rightarrow>(('a,(('r,'e1)sum))result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set "  where 
-     " try_catchSR m h = (
-  try_catchS m
-    (\<lambda>x .  (case  x of   Inl r => throwS (Inl r) | Inr e => h e )))"
-
-
-(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*)
-definition maybe_failS  :: " string \<Rightarrow> 'a option \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " maybe_failS msg = ( \<lambda>x .  
-  (case  x of   Some a => returnS a | None => failS msg ) )"
-
-
-(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*)
-definition read_tagS  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regs,(bitU),'e)monadS "  where 
-     " read_tagS dict_Sail_values_Bitvector_a addr = ( bindS
-  (maybe_failS (''unsigned'') (
-  (unsigned_method   dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . 
-  readS (\<lambda> s .  case_option B0 id ((tagstate   s) addr))))"
-
-
-(* Read bytes from memory and return in little endian order *)
-(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*)
-definition read_mem_bytesS  :: " 'a Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(((bitU)list)list),'e)monadS "  where 
-     " read_mem_bytesS dict_Sail_values_Bitvector_a read_kind addr sz = ( bindS
-  (maybe_failS (''unsigned'') (
-  (unsigned_method   dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . 
-  (let sz = (int sz) in
-  (let addrs = (index_list addr ((addr+sz)-( 1 :: int))(( 1 :: int))) in  
-  (let read_byte = (\<lambda> s addr .  (memstate   s) addr) in
-  bindS (readS (\<lambda> s .  just_list (List.map (read_byte s) addrs)))
-    (\<lambda>x .  (case  x of
-                         Some mem_val => seqS
-                                           (updateS
-                                              (\<lambda> s . 
-                                               if read_is_exclusive read_kind
-                                               then
-                                                 ( s (| last_exclusive_operation_was_load := True |))
-                                               else s)) (returnS mem_val)
-                     | None => failS (''read_memS'')
-                   )))))))"
-
-
-(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*)
-definition read_memS  :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regs,'b,'e)monadS "  where 
-     " read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz = ( bindS
-  (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\<lambda> bytes . 
-  maybe_failS (''bits_of_mem_bytes'') (
-  (of_bits_method   dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))"
-
-
-(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*)
-definition excl_resultS  :: " unit \<Rightarrow>('regs,(bool),'e)monadS "  where 
-     " excl_resultS _ = ( bindS
-  (readS (\<lambda> s . (last_exclusive_operation_was_load   s))) (\<lambda> excl_load .  seqS
-  (updateS (\<lambda> s .  ( s (| last_exclusive_operation_was_load := False |))))
-  (chooseS (if excl_load then {False, True} else {False}))))"
-
-
-(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*)
-definition write_mem_eaS  :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(unit),'e)monadS "  where 
-     " write_mem_eaS dict_Sail_values_Bitvector_a write_kind addr sz = ( bindS
-  (maybe_failS (''unsigned'') (
-  (unsigned_method   dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . 
-  (let sz = (int sz) in
-  updateS (\<lambda> s .  ( s (| write_ea := (Some (write_kind, addr, sz)) |))))))"
-
-
-(* Write little-endian list of bytes to previously announced address *)
-(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*)
-definition write_mem_bytesS  :: "((bitU)list)list \<Rightarrow>('regs,(bool),'e)monadS "  where 
-     " write_mem_bytesS v = ( bindS
-  (readS (\<lambda> s . (write_ea   s))) (\<lambda>x .  
-  (case  x of
-        None => failS (''write ea has not been announced yet'')
-    | Some (_, addr, sz) =>
-  (let addrs = (index_list addr ((addr + sz) - ( 1 :: int)) (( 1 :: int))) in
-  (*let v = external_mem_value (bits_of v) in*)
-  (let a_v = (List.zip addrs v) in
-  (let write_byte = (\<lambda>mem p .  (case  (mem ,p ) of
-                                           ( mem , (addr, v) ) => map_update
-                                                                    addr 
-                                                                  v mem
-                                       )) in
-  seqS
-    (updateS
-       (\<lambda> s . 
-        ( s (| memstate := (List.foldl write_byte (memstate   s) a_v) |))))
-    (returnS True))))
-  )))"
-
-
-(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*)
-definition write_mem_valS  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set "  where 
-     " write_mem_valS dict_Sail_values_Bitvector_a v = ( (case  mem_bytes_of_bits 
-  dict_Sail_values_Bitvector_a v of
-    Some v => write_mem_bytesS v
-  | None => failS (''write_mem_val'')
-))"
-
-
-(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*)
-definition write_tagS  :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('regs,(bool),'e)monadS "  where 
-     " write_tagS dict_Sail_values_Bitvector_a addr t = ( bindS
-   (maybe_failS (''unsigned'') (
-  (unsigned_method   dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr .  seqS
-   (updateS (\<lambda> s .  ( s (| tagstate := (map_update addr t(tagstate   s)) |))))
-   (returnS True)))"
-
-
-(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*)
-definition read_regS  :: "('regs,'rv,'a)register_ref \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set "  where 
-     " read_regS reg = ( readS (\<lambda> s . (read_from   reg)(regstate   s)))"
-
-
-(* TODO
-let read_reg_range reg i j state =
-  let v = slice (get_reg state (name_of_reg reg)) i j in
-  [(Value (vec_to_bvec v),state)]
-let read_reg_bit reg i state =
-  let v = access (get_reg state (name_of_reg reg)) i in
-  [(Value v,state)]
-let read_reg_field reg regfield =
-  let (i,j) = register_field_indices reg regfield in
-  read_reg_range reg i j
-let read_reg_bitfield reg regfield =
-  let (i,_) = register_field_indices reg regfield in
-  read_reg_bit reg i *)
-
-(*val read_regvalS : forall 'regs 'rv 'e.
-  register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*)
-fun read_regvalS  :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow>('regs,'rv,'e)monadS "  where 
-     " read_regvalS (read, _) reg = ( bindS
-  (readS (\<lambda> s .  read reg(regstate   s))) (\<lambda>x .  
-  (case  x of
-        Some v => returnS v
-    | None => failS ((''read_regvalS '') @ reg)
-  )))"
-
-
-(*val write_regvalS : forall 'regs 'rv 'e.
-  register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*)
-fun write_regvalS  :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow> 'rv \<Rightarrow>('regs,(unit),'e)monadS "  where 
-     " write_regvalS (_, write1) reg v = ( bindS
-  (readS (\<lambda> s .  write1 reg v(regstate   s))) (\<lambda>x .  
-  (case  x of
-        Some rs' => updateS (\<lambda> s .  ( s (| regstate := rs' |)))
-    | None => failS ((''write_regvalS '') @ reg)
-  )))"
-
-
-(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*)
-definition write_regS  :: "('regs,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set "  where 
-     " write_regS reg v = (
-  updateS (\<lambda> s .  ( s (| regstate := ((write_to   reg) v(regstate   s)) |))))"
-
-
-(* TODO
-val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
-let update_reg reg f v state =
-  let current_value = get_reg state reg in
-  let new_value = f current_value v in
-  [(Value (), set_reg state reg new_value)]
-
-let write_reg_field reg regfield = update_reg reg regfield.set_field
-
-val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
-let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
-let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
-
-let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
-let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
-
-let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
-let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
-
-let update_reg_field_range regfield i j reg_val new_val =
-  let current_field_value = regfield.get_field reg_val in
-  let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
-  regfield.set_field reg_val new_field_value
-let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
-
-let update_reg_field_pos regfield i reg_val x =
-  let current_field_value = regfield.get_field reg_val in
-  let new_field_value = update_list regfield.field_is_inc current_field_value i x in
-  regfield.set_field reg_val new_field_value
-let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
-
-let update_reg_field_bit regfield i reg_val bit =
-  let current_field_value = regfield.get_field reg_val in
-  let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
-  regfield.set_field reg_val new_field_value
-let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
-
-(* TODO Add Show typeclass for value and exception type *)
-(*val show_result : forall 'a 'e. result 'a 'e -> string*)
-definition show_result  :: "('a,'e)result \<Rightarrow> string "  where 
-     " show_result = ( \<lambda>x .  
-  (case  x of
-        Value _ => (''Value ()'')
-    | Ex (Failure msg) => (''Failure '') @ msg
-    | Ex (Throw _) => (''Throw'')
-  ) )"
-
-
-(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*)
-definition prerr_results  :: "(('a,'e)result*'s)set \<Rightarrow> unit "  where 
-     " prerr_results rs = (
-  (let _ = (Set.image ( \<lambda>x .  
-  (case  x of (r, _) => (let _ = (prerr_endline (show_result r)) in () ) )) rs) in
-  () ))"
-
-end
diff --git a/snapshots/isabelle/lib/sail/State_monad_lemmas.thy b/snapshots/isabelle/lib/sail/State_monad_lemmas.thy
deleted file mode 100644
index e0d684ba..00000000
--- a/snapshots/isabelle/lib/sail/State_monad_lemmas.thy
+++ /dev/null
@@ -1,232 +0,0 @@
-theory State_monad_lemmas
-  imports
-    State_monad
-    Sail_values_lemmas
-begin
-
-(*context
-  notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp]
-begin*)
-
-lemma bindS_ext_cong[fundef_cong]:
-  assumes m: "m1 s = m2 s"
-    and f: "\<And>a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
-  shows "bindS m1 f1 s = bindS m2 f2 s"
-  using assms unfolding bindS_def by (auto split: result.splits)
-
-lemma bindS_cong[fundef_cong]:
-  assumes m: "m1 = m2"
-    and f: "\<And>s a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
-  shows "bindS m1 f1 = bindS m2 f2"
-  using assms by (intro ext bindS_ext_cong; blast)
-
-lemma bindS_returnS_left[simp]: "bindS (returnS x) f = f x"
-  by (auto simp add: bindS_def returnS_def)
-
-lemma bindS_returnS_right[simp]: "bindS m returnS = (m :: ('regs, 'a, 'e) monadS)"
-  by (intro ext) (auto simp: bindS_def returnS_def split: result.splits)
-
-lemma bindS_readS: "bindS (readS f) m = (\<lambda>s. m (f s) s)"
-  by (auto simp: bindS_def readS_def returnS_def)
-
-lemma bindS_updateS: "bindS (updateS f) m = (\<lambda>s. m () (f s))"
-  by (auto simp: bindS_def updateS_def returnS_def)
-
-lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()"
-  by (auto simp: assert_expS_def)
-
-
-lemma result_cases:
-  fixes r :: "('a, 'e) result"
-  obtains (Value) a where "r = Value a"
-  | (Throw) e where "r = Ex (Throw e)"
-  | (Failure) msg where "r = Ex (Failure msg)"
-proof (cases r)
-  case (Ex ex) then show ?thesis by (cases ex; auto intro: that)
-qed
-
-lemma result_state_cases:
-  fixes rs :: "('a, 'e) result \<times> 's"
-  obtains (Value) a s where "rs = (Value a, s)"
-  | (Throw) e s where "rs = (Ex (Throw e), s)"
-  | (Failure) msg s where "rs = (Ex (Failure msg), s)"
-proof -
-  obtain r s where rs: "rs = (r, s)" by (cases rs)
-  then show thesis by (cases r rule: result_cases) (auto intro: that)
-qed
-
-lemma monadS_ext_eqI:
-  fixes m m' :: "('regs, 'a, 'e) monadS"
-  assumes "\<And>a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
-    and "\<And>e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
-    and "\<And>msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
-  shows "m s = m' s"
-proof (intro set_eqI)
-  fix x
-  show "x \<in> m s \<longleftrightarrow> x \<in> m' s" using assms by (cases x rule: result_state_cases) auto
-qed
-
-lemma monadS_eqI:
-  fixes m m' :: "('regs, 'a, 'e) monadS"
-  assumes "\<And>s a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
-    and "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
-    and "\<And>s msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
-  shows "m = m'"
-  using assms by (intro ext monadS_ext_eqI)
-
-lemma bindS_cases:
-  assumes "(r, s') \<in> bindS m f s"
-  obtains (Value) a a' s'' where "r = Value a" and "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''"
-  | (Ex_Left) e where "r = Ex e" and "(Ex e, s') \<in> m s"
-  | (Ex_Right) e a s'' where "r = Ex e" and "(Value a, s'') \<in> m s" and "(Ex e, s') \<in> f a s''"
-  using assms by (cases r; auto simp: bindS_def split: result.splits)
-
-lemma bindS_intros:
-  "\<And>m f s a s' a' s''. (Value a', s'') \<in> m s \<Longrightarrow> (Value a, s') \<in> f a' s'' \<Longrightarrow> (Value a, s') \<in> bindS m f s"
-  "\<And>m f s e s'. (Ex e, s') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s"
-  "\<And>m f s e s' a s''. (Ex e, s') \<in> f a s'' \<Longrightarrow> (Value a, s'') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s"
-  by (auto simp: bindS_def intro: bexI[rotated])
-
-lemma bindS_assoc[simp]: "bindS (bindS m f) g = bindS m (\<lambda>x. bindS (f x) g)"
-  by (auto elim!: bindS_cases intro: bindS_intros monadS_eqI)
-
-lemma bindS_failS[simp]: "bindS (failS msg) f = failS msg" by (auto simp: bindS_def failS_def)
-lemma bindS_throwS[simp]: "bindS (throwS e) f = throwS e" by (auto simp: bindS_def throwS_def)
-declare seqS_def[simp]
-
-lemma Value_bindS_elim:
-  assumes "(Value a, s') \<in> bindS m f s"
-  obtains s'' a' where "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''"
-  using assms by (auto elim: bindS_cases)
-
-lemma Ex_bindS_elim:
-  assumes "(Ex e, s') \<in> bindS m f s"
-  obtains (Left) "(Ex e, s') \<in> m s"
-  | (Right) s'' a' where "(Value a', s'') \<in> m s" and "(Ex e, s') \<in> f a' s''"
-  using assms by (auto elim: bindS_cases)
-
-lemma try_catchS_returnS[simp]: "try_catchS (returnS a) h = returnS a"
-  and try_catchS_failS[simp]: "try_catchS (failS msg) h = failS msg"
-  and try_catchS_throwS[simp]: "try_catchS (throwS e) h = h e"
-  by (auto simp: try_catchS_def returnS_def failS_def throwS_def)
-
-lemma try_catchS_cong[cong]:
-  assumes "\<And>s. m1 s = m2 s" and "\<And>e s. h1 e s = h2 e s"
-  shows "try_catchS m1 h1 = try_catchS m2 h2"
-  using assms by (intro arg_cong2[where f = try_catchS] ext) auto
-
-lemma try_catchS_cases:
-  assumes "(r, s') \<in> try_catchS m h s"
-  obtains (Value) a where "r = Value a" and "(Value a, s') \<in> m s"
-  | (Fail) msg where "r = Ex (Failure msg)" and "(Ex (Failure msg), s') \<in> m s"
-  | (h) e s'' where "(Ex (Throw e), s'') \<in> m s" and "(r, s') \<in> h e s''"
-  using assms
-  by (cases r rule: result_cases) (auto simp: try_catchS_def returnS_def split: result.splits ex.splits)
-
-lemma try_catchS_intros:
-  "\<And>m h s a s'. (Value a, s') \<in> m s \<Longrightarrow> (Value a, s') \<in> try_catchS m h s"
-  "\<And>m h s msg s'. (Ex (Failure msg), s') \<in> m s \<Longrightarrow> (Ex (Failure msg), s') \<in> try_catchS m h s"
-  "\<And>m h s e s'' r s'. (Ex (Throw e), s'') \<in> m s \<Longrightarrow> (r, s') \<in> h e s'' \<Longrightarrow> (r, s') \<in> try_catchS m h s"
-  by (auto simp: try_catchS_def returnS_def intro: bexI[rotated])
-
-lemma no_Ex_basic_builtins[simp]:
-  "\<And>s e s' a. (Ex e, s') \<in> returnS a s \<longleftrightarrow> False"
-  "\<And>s e s' f. (Ex e, s') \<in> readS f s \<longleftrightarrow> False"
-  "\<And>s e s' f. (Ex e, s') \<in> updateS f s \<longleftrightarrow> False"
-  "\<And>s e s' xs. (Ex e, s') \<in> chooseS xs s \<longleftrightarrow> False"
-  by (auto simp: readS_def updateS_def returnS_def chooseS_def)
-
-fun ignore_throw_aux :: "(('a, 'e1) result \<times> 's) \<Rightarrow> (('a, 'e2) result \<times> 's) set" where
-  "ignore_throw_aux (Value a, s') = {(Value a, s')}"
-| "ignore_throw_aux (Ex (Throw e), s') = {}"
-| "ignore_throw_aux (Ex (Failure msg), s') = {(Ex (Failure msg), s')}"
-definition "ignore_throw m s \<equiv> \<Union>(ignore_throw_aux ` m s)"
-
-lemma ignore_throw_cong:
-  assumes "\<And>s. m1 s = m2 s"
-  shows "ignore_throw m1 = ignore_throw m2"
-  using assms by (auto simp: ignore_throw_def)
-
-lemma ignore_throw_aux_member_simps[simp]:
-  "(Value a, s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Value a, s')"
-  "(Ex (Throw e), s') \<in> ignore_throw_aux ms \<longleftrightarrow> False"
-  "(Ex (Failure msg), s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Ex (Failure msg), s')"
-  by (cases ms rule: result_state_cases; auto)+
-
-lemma ignore_throw_member_simps[simp]:
-  "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s"
-  "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s"
-  "(Ex (Throw e), s') \<in> ignore_throw m s \<longleftrightarrow> False"
-  "(Ex (Failure msg), s') \<in> ignore_throw m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m s"
-  by (auto simp: ignore_throw_def)
-
-lemma ignore_throw_cases:
-  assumes no_throw: "ignore_throw m s = m s"
-    and r: "(r, s') \<in> m s"
-  obtains (Value) a where "r = Value a"
-  | (Failure) msg where "r = Ex (Failure msg)"
-  using r unfolding no_throw[symmetric]
-  by (cases r rule: result_cases) (auto simp: ignore_throw_def)
-
-lemma ignore_throw_bindS[simp]:
-  "ignore_throw (bindS m f) = bindS (ignore_throw m) (ignore_throw \<circ> f)"
-  by (intro monadS_eqI) (auto simp: ignore_throw_def elim!: bindS_cases intro: bindS_intros)
-
-lemma try_catchS_bindS_no_throw:
-  fixes m1 :: "('r, 'a, 'e1) monadS" and m2 :: "('r, 'a, 'e2) monadS"
-  assumes m1: "\<And>s. ignore_throw m1 s = m1 s"
-    and m2: "\<And>s. ignore_throw m1 s = m2 s"
-  shows "try_catchS (bindS m1 f) h = bindS m2 (\<lambda>a. try_catchS (f a) h)"
-proof
-  fix s
-  have "try_catchS (bindS m1 f) h s = bindS (ignore_throw m1) (\<lambda>a. try_catchS (f a) h) s"
-    by (intro monadS_ext_eqI;
-        auto elim!: bindS_cases try_catchS_cases elim: ignore_throw_cases[OF m1];
-        auto simp: ignore_throw_def intro: bindS_intros try_catchS_intros)
-  also have "\<dots> = bindS m2 (\<lambda>a. try_catchS (f a) h) s" using m2 by (intro bindS_ext_cong) auto
-  finally show "try_catchS (bindS m1 f) h s = bindS m2 (\<lambda>a. try_catchS (f a) h) s" .
-qed
-
-lemma no_throw_basic_builtins[simp]:
-  "ignore_throw (returnS a) = returnS a"
-  "\<And>f. ignore_throw (readS f) = readS f"
-  "\<And>f. ignore_throw (updateS f) = updateS f"
-  "ignore_throw (chooseS xs) = chooseS xs"
-  "ignore_throw (failS msg) = failS msg"
-  "ignore_throw (maybe_failS msg x) = maybe_failS msg x"
-  unfolding ignore_throw_def returnS_def chooseS_def maybe_failS_def failS_def readS_def updateS_def
-  by (intro ext; auto split: option.splits)+
-
-lemmas ignore_throw_option_case_distrib =
-  option.case_distrib[where h = "\<lambda>c. ignore_throw c s" and option = "c s" for c s]
-
-lemma no_throw_mem_builtins:
-  "\<And>BC rk a sz s. ignore_throw (read_mem_bytesS BC rk a sz) s = read_mem_bytesS BC rk a sz s"
-  "\<And>BC a s. ignore_throw (read_tagS BC a) s = read_tagS BC a s"
-  "\<And>BC wk a sz s. ignore_throw (write_mem_eaS BC wk a sz) s = write_mem_eaS BC wk a sz s"
-  "\<And>v s. ignore_throw (write_mem_bytesS v) s = write_mem_bytesS v s"
-  "\<And>BC v s. ignore_throw (write_mem_valS BC v) s = write_mem_valS BC v s"
-  "\<And>BC a t s. ignore_throw (write_tagS BC a t) s = write_tagS BC a t s"
-  "\<And>s. ignore_throw (excl_resultS ()) s = excl_resultS () s"
-  "\<And>s. ignore_throw (undefined_boolS ()) s = undefined_boolS () s"
-  unfolding read_mem_bytesS_def read_memS_def read_tagS_def write_mem_eaS_def
-  unfolding write_mem_valS_def write_mem_bytesS_def write_tagS_def
-  unfolding excl_resultS_def undefined_boolS_def
-  by (auto cong: bindS_cong bindS_ext_cong ignore_throw_cong option.case_cong
-           simp: option.case_distrib prod.case_distrib ignore_throw_option_case_distrib comp_def)
-
-lemma no_throw_read_memS: "ignore_throw (read_memS BCa BCb rk a sz) s = read_memS BCa BCb rk a sz s"
-  by (auto simp: read_memS_def no_throw_mem_builtins cong: bindS_ext_cong)
-
-lemma no_throw_read_regvalS: "ignore_throw (read_regvalS r reg_name) s = read_regvalS r reg_name s"
-  by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong)
-
-lemma no_throw_write_regvalS: "ignore_throw (write_regvalS r reg_name v) s = write_regvalS r reg_name v s"
-  by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong)
-
-lemmas no_throw_builtins[simp] =
-  no_throw_mem_builtins no_throw_read_regvalS no_throw_write_regvalS no_throw_read_memS
-
-(* end *)
-
-end
diff --git a/snapshots/isabelle/riscv/Riscv.thy b/snapshots/isabelle/riscv/Riscv.thy
index 71873cec..754caaf5 100644
--- a/snapshots/isabelle/riscv/Riscv.thy
+++ b/snapshots/isabelle/riscv/Riscv.thy
@@ -5,12 +5,12 @@ theory "Riscv"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+	 "Sail2_string" 
 	 "Riscv_types" 
 	 "Riscv_extras" 
 
@@ -18,15 +18,51 @@ begin
 
 (*Generated by Sail from riscv.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 (*open import Riscv_types*)
 (*open import Riscv_extras*)
 
+(*val spc_forwards : unit -> string*)
+
+definition spc_forwards  :: " unit \<Rightarrow> string "  where 
+     " spc_forwards _ = ( ('' ''))"
+
+
+(*val spc_backwards : string -> unit*)
+
+definition spc_backwards  :: " string \<Rightarrow> unit "  where 
+     " spc_backwards s = ( ()  )"
+
+
+(*val opt_spc_forwards : unit -> string*)
+
+definition opt_spc_forwards  :: " unit \<Rightarrow> string "  where 
+     " opt_spc_forwards _ = ( (''''))"
+
+
+(*val opt_spc_backwards : string -> unit*)
+
+definition opt_spc_backwards  :: " string \<Rightarrow> unit "  where 
+     " opt_spc_backwards s = ( ()  )"
+
+
+(*val def_spc_forwards : unit -> string*)
+
+definition def_spc_forwards  :: " unit \<Rightarrow> string "  where 
+     " def_spc_forwards _ = ( ('' ''))"
+
+
+(*val def_spc_backwards : string -> unit*)
+
+definition def_spc_backwards  :: " string \<Rightarrow> unit "  where 
+     " def_spc_backwards s = ( ()  )"
+
+
 
 
 
@@ -48,7 +84,7 @@ begin
 (*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*)
 
 definition GetSlice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
-     " GetSlice_int n m o1 = ( (get_slice_int0 n m o1  :: ( 'n::len)Word.word))"
+     " GetSlice_int n m o1 = ( (get_slice_int n m o1  :: ( 'n::len)Word.word))"
 
 
 (*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*)
@@ -80,17 +116,59 @@ definition RISCV_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_
 
 (*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*)
 
-(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*)
+(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (maybe (mword 'int8_times_n))*)
 
-definition RISCV_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(exception))monad "  where 
-     " RISCV_read addr width = (
-   (read_ram (( 64 :: int)::ii) width
-      (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-        ::  64 Word.word) addr
-     :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . 
-   return (Some w__0)))"
+fun RISCV_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(exception))monad "  where 
+     " RISCV_read addr width False False False = (
+      (MEMr (( 64 :: int)::ii) width
+         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+           ::  64 Word.word) addr
+        :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . 
+      return (Some w__0)))"
+|" RISCV_read addr width True False False = (
+      (MEMr_acquire (( 64 :: int)::ii) width
+         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+           ::  64 Word.word) addr
+        :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'int8_times_n::len)Word.word) . 
+      return (Some w__1)))"
+|" RISCV_read addr width True True False = (
+      (MEMr_strong_acquire (( 64 :: int)::ii) width
+         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+           ::  64 Word.word) addr
+        :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'int8_times_n::len)Word.word) . 
+      return (Some w__2)))"
+|" RISCV_read addr width False False True = (
+      (MEMr_reserved (( 64 :: int)::ii) width
+         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+           ::  64 Word.word) addr
+        :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'int8_times_n::len)Word.word) . 
+      return (Some w__3)))"
+|" RISCV_read addr width True False True = (
+      (MEMr_reserved_acquire (( 64 :: int)::ii) width
+         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+           ::  64 Word.word) addr
+        :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__4 :: ( 'int8_times_n::len)Word.word) . 
+      return (Some w__4)))"
+|" RISCV_read addr width True True True = (
+      (MEMr_reserved_strong_acquire (( 64 :: int)::ii) width
+         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+           ::  64 Word.word) addr
+        :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'int8_times_n::len)Word.word) . 
+      return (Some w__5)))"
+|" RISCV_read addr width False True False = ( return None )"
+|" RISCV_read addr width False True True = ( return None )"
 
 
 (*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*)
@@ -171,13 +249,13 @@ fun bit_to_bool  :: " bitU \<Rightarrow> bool "  where
 (*val vector64 : ii -> mword ty64*)
 
 definition vector64  :: " int \<Rightarrow>(64)Word.word "  where 
-     " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii)  ::  64 Word.word))"
+     " vector64 n = ( (get_slice_int (( 64 :: int)::ii) n (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
 (*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*)
 
 definition to_bits  :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word "  where 
-     " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii)  :: ( 'l::len)Word.word))"
+     " to_bits l n = ( (get_slice_int l n (( 0 :: int)::ii)  :: ( 'l::len)Word.word))"
 
 
 (*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*)
@@ -241,29 +319,89 @@ definition sp  :: "(5)Word.word "  where
 (*val rX : integer -> M (mword ty64)*)
 
 definition rX  :: " int \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
-     " rX l__81 = (
-   if (((l__81 = (( 0 :: int)::ii)))) then
+     " rX r = (
+   (let p00 = r in
+   if (((p00 = (( 0 :: int)::ii)))) then
      return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
               ::  64 Word.word)
-   else
-     read_reg Xs_ref \<bind> (\<lambda> (w__0 :: xlenbits list) . 
-     return ((access_list_dec w__0 l__81  ::  64 Word.word))))"
+   else if (((p00 = (( 1 :: int)::ii)))) then (read_reg x1_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 2 :: int)::ii)))) then (read_reg x2_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 3 :: int)::ii)))) then (read_reg x3_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 4 :: int)::ii)))) then (read_reg x4_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 5 :: int)::ii)))) then (read_reg x5_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 6 :: int)::ii)))) then (read_reg x6_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 7 :: int)::ii)))) then (read_reg x7_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 8 :: int)::ii)))) then (read_reg x8_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 9 :: int)::ii)))) then (read_reg x9_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 10 :: int)::ii)))) then (read_reg x10_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 11 :: int)::ii)))) then (read_reg x11_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 12 :: int)::ii)))) then (read_reg x12_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 13 :: int)::ii)))) then (read_reg x13_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 14 :: int)::ii)))) then (read_reg x14_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 15 :: int)::ii)))) then (read_reg x15_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 16 :: int)::ii)))) then (read_reg x16_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 17 :: int)::ii)))) then (read_reg x17_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 18 :: int)::ii)))) then (read_reg x18_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 19 :: int)::ii)))) then (read_reg x19_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 20 :: int)::ii)))) then (read_reg x20_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 21 :: int)::ii)))) then (read_reg x21_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 22 :: int)::ii)))) then (read_reg x22_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 23 :: int)::ii)))) then (read_reg x23_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 24 :: int)::ii)))) then (read_reg x24_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 25 :: int)::ii)))) then (read_reg x25_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 26 :: int)::ii)))) then (read_reg x26_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 27 :: int)::ii)))) then (read_reg x27_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 28 :: int)::ii)))) then (read_reg x28_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 29 :: int)::ii)))) then (read_reg x29_ref  :: ( 64 Word.word) M)
+   else if (((p00 = (( 30 :: int)::ii)))) then (read_reg x30_ref  :: ( 64 Word.word) M)
+   else (read_reg x31_ref  :: ( 64 Word.word) M)))"
 
 
 (*val wX : integer -> mword ty64 -> M unit*)
 
 definition wX  :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " wX r v = (
-   if (((r \<noteq> (( 0 :: int)::ii)))) then
-     read_reg Xs_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . 
-     write_reg Xs_ref ((update_list_dec w__0 r v  :: ( 64 Word.word) list)) \<then>
-     return ((prerr_endline
-                (((op@) (''x'')
-                    (((op@) ((stringFromInteger r))
-                        (((op@) ('' <- '') ((string_of_vec v)))))))))))
-   else return ()  )"
+   (let p00 = r in
+   (if (((p00 = (( 0 :: int)::ii)))) then return () 
+    else if (((p00 = (( 1 :: int)::ii)))) then write_reg x1_ref v
+    else if (((p00 = (( 2 :: int)::ii)))) then write_reg x2_ref v
+    else if (((p00 = (( 3 :: int)::ii)))) then write_reg x3_ref v
+    else if (((p00 = (( 4 :: int)::ii)))) then write_reg x4_ref v
+    else if (((p00 = (( 5 :: int)::ii)))) then write_reg x5_ref v
+    else if (((p00 = (( 6 :: int)::ii)))) then write_reg x6_ref v
+    else if (((p00 = (( 7 :: int)::ii)))) then write_reg x7_ref v
+    else if (((p00 = (( 8 :: int)::ii)))) then write_reg x8_ref v
+    else if (((p00 = (( 9 :: int)::ii)))) then write_reg x9_ref v
+    else if (((p00 = (( 10 :: int)::ii)))) then write_reg x10_ref v
+    else if (((p00 = (( 11 :: int)::ii)))) then write_reg x11_ref v
+    else if (((p00 = (( 12 :: int)::ii)))) then write_reg x12_ref v
+    else if (((p00 = (( 13 :: int)::ii)))) then write_reg x13_ref v
+    else if (((p00 = (( 14 :: int)::ii)))) then write_reg x14_ref v
+    else if (((p00 = (( 15 :: int)::ii)))) then write_reg x15_ref v
+    else if (((p00 = (( 16 :: int)::ii)))) then write_reg x16_ref v
+    else if (((p00 = (( 17 :: int)::ii)))) then write_reg x17_ref v
+    else if (((p00 = (( 18 :: int)::ii)))) then write_reg x18_ref v
+    else if (((p00 = (( 19 :: int)::ii)))) then write_reg x19_ref v
+    else if (((p00 = (( 20 :: int)::ii)))) then write_reg x20_ref v
+    else if (((p00 = (( 21 :: int)::ii)))) then write_reg x21_ref v
+    else if (((p00 = (( 22 :: int)::ii)))) then write_reg x22_ref v
+    else if (((p00 = (( 23 :: int)::ii)))) then write_reg x23_ref v
+    else if (((p00 = (( 24 :: int)::ii)))) then write_reg x24_ref v
+    else if (((p00 = (( 25 :: int)::ii)))) then write_reg x25_ref v
+    else if (((p00 = (( 26 :: int)::ii)))) then write_reg x26_ref v
+    else if (((p00 = (( 27 :: int)::ii)))) then write_reg x27_ref v
+    else if (((p00 = (( 28 :: int)::ii)))) then write_reg x28_ref v
+    else if (((p00 = (( 29 :: int)::ii)))) then write_reg x29_ref v
+    else if (((p00 = (( 30 :: int)::ii)))) then write_reg x30_ref v
+    else write_reg x31_ref v) \<then>
+   return (if (((r \<noteq> (( 0 :: int)::ii)))) then
+             print_endline
+               (((op@) (''x'')
+                   (((op@) ((stringFromInteger r))
+                       (((op@) ('' <- '') ((string_of_bits v))))))))
+           else () )))"
 
 
 (*val reg_name_abi : mword ty5 -> string*)
@@ -340,9 +478,9 @@ definition reg_name_abi  :: "(5)Word.word \<Rightarrow> string "  where
 
 definition Architecture_of_num  :: " int \<Rightarrow> Architecture "  where 
      " Architecture_of_num arg0 = (
-   (let l__79 = arg0 in
-   if (((l__79 = (( 0 :: int)::ii)))) then RV32
-   else if (((l__79 = (( 1 :: int)::ii)))) then RV64
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RV32
+   else if (((p00 = (( 1 :: int)::ii)))) then RV64
    else RV128))"
 
 
@@ -377,9 +515,9 @@ fun arch_to_bits  :: " Architecture \<Rightarrow>(2)Word.word "  where
 
 definition Privilege_of_num  :: " int \<Rightarrow> Privilege "  where 
      " Privilege_of_num arg0 = (
-   (let l__77 = arg0 in
-   if (((l__77 = (( 0 :: int)::ii)))) then User
-   else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then User
+   else if (((p00 = (( 1 :: int)::ii)))) then Supervisor
    else Machine))"
 
 
@@ -421,10 +559,10 @@ fun privLevel_to_str  :: " Privilege \<Rightarrow> string "  where
 
 definition AccessType_of_num  :: " int \<Rightarrow> AccessType "  where 
      " AccessType_of_num arg0 = (
-   (let l__74 = arg0 in
-   if (((l__74 = (( 0 :: int)::ii)))) then Read
-   else if (((l__74 = (( 1 :: int)::ii)))) then Write
-   else if (((l__74 = (( 2 :: int)::ii)))) then ReadWrite
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Read
+   else if (((p00 = (( 1 :: int)::ii)))) then Write
+   else if (((p00 = (( 2 :: int)::ii)))) then ReadWrite
    else Execute))"
 
 
@@ -437,12 +575,21 @@ fun num_of_AccessType  :: " AccessType \<Rightarrow> int "  where
 |" num_of_AccessType Execute = ( (( 3 :: int)::ii))"
 
 
+(*val accessType_to_str : AccessType -> string*)
+
+fun accessType_to_str  :: " AccessType \<Rightarrow> string "  where 
+     " accessType_to_str Read = ( (''R''))"
+|" accessType_to_str Write = ( (''W''))"
+|" accessType_to_str ReadWrite = ( (''RW''))"
+|" accessType_to_str Execute = ( (''X''))"
+
+
 (*val ReadType_of_num : integer -> ReadType*)
 
 definition ReadType_of_num  :: " int \<Rightarrow> ReadType "  where 
      " ReadType_of_num arg0 = (
-   (let l__73 = arg0 in
-   if (((l__73 = (( 0 :: int)::ii)))) then Instruction
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Instruction
    else Data))"
 
 
@@ -453,26 +600,33 @@ fun num_of_ReadType  :: " ReadType \<Rightarrow> int "  where
 |" num_of_ReadType Data = ( (( 1 :: int)::ii))"
 
 
+(*val readType_to_str : ReadType -> string*)
+
+fun readType_to_str  :: " ReadType \<Rightarrow> string "  where 
+     " readType_to_str Instruction = ( (''I''))"
+|" readType_to_str Data = ( (''D''))"
+
+
 (*val ExceptionType_of_num : integer -> ExceptionType*)
 
 definition ExceptionType_of_num  :: " int \<Rightarrow> ExceptionType "  where 
      " ExceptionType_of_num arg0 = (
-   (let l__58 = arg0 in
-   if (((l__58 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align
-   else if (((l__58 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault
-   else if (((l__58 = (( 2 :: int)::ii)))) then E_Illegal_Instr
-   else if (((l__58 = (( 3 :: int)::ii)))) then E_Breakpoint
-   else if (((l__58 = (( 4 :: int)::ii)))) then E_Load_Addr_Align
-   else if (((l__58 = (( 5 :: int)::ii)))) then E_Load_Access_Fault
-   else if (((l__58 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align
-   else if (((l__58 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault
-   else if (((l__58 = (( 8 :: int)::ii)))) then E_U_EnvCall
-   else if (((l__58 = (( 9 :: int)::ii)))) then E_S_EnvCall
-   else if (((l__58 = (( 10 :: int)::ii)))) then E_Reserved_10
-   else if (((l__58 = (( 11 :: int)::ii)))) then E_M_EnvCall
-   else if (((l__58 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault
-   else if (((l__58 = (( 13 :: int)::ii)))) then E_Load_Page_Fault
-   else if (((l__58 = (( 14 :: int)::ii)))) then E_Reserved_14
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align
+   else if (((p00 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault
+   else if (((p00 = (( 2 :: int)::ii)))) then E_Illegal_Instr
+   else if (((p00 = (( 3 :: int)::ii)))) then E_Breakpoint
+   else if (((p00 = (( 4 :: int)::ii)))) then E_Load_Addr_Align
+   else if (((p00 = (( 5 :: int)::ii)))) then E_Load_Access_Fault
+   else if (((p00 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align
+   else if (((p00 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault
+   else if (((p00 = (( 8 :: int)::ii)))) then E_U_EnvCall
+   else if (((p00 = (( 9 :: int)::ii)))) then E_S_EnvCall
+   else if (((p00 = (( 10 :: int)::ii)))) then E_Reserved_10
+   else if (((p00 = (( 11 :: int)::ii)))) then E_M_EnvCall
+   else if (((p00 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault
+   else if (((p00 = (( 13 :: int)::ii)))) then E_Load_Page_Fault
+   else if (((p00 = (( 14 :: int)::ii)))) then E_Reserved_14
    else E_SAMO_Page_Fault))"
 
 
@@ -521,7 +675,7 @@ fun exceptionType_to_bits  :: " ExceptionType \<Rightarrow>(4)Word.word "  where
 (*val exceptionType_to_str : ExceptionType -> string*)
 
 fun exceptionType_to_str  :: " ExceptionType \<Rightarrow> string "  where 
-     " exceptionType_to_str E_Fetch_Addr_Align = ( (''fisaligned-fetch''))"
+     " exceptionType_to_str E_Fetch_Addr_Align = ( (''misaligned-fetch''))"
 |" exceptionType_to_str E_Fetch_Access_Fault = ( (''fetch-access-fault''))"
 |" exceptionType_to_str E_Illegal_Instr = ( (''illegal-instruction''))"
 |" exceptionType_to_str E_Breakpoint = ( (''breakpoint''))"
@@ -543,15 +697,15 @@ fun exceptionType_to_str  :: " ExceptionType \<Rightarrow> string "  where
 
 definition InterruptType_of_num  :: " int \<Rightarrow> InterruptType "  where 
      " InterruptType_of_num arg0 = (
-   (let l__50 = arg0 in
-   if (((l__50 = (( 0 :: int)::ii)))) then I_U_Software
-   else if (((l__50 = (( 1 :: int)::ii)))) then I_S_Software
-   else if (((l__50 = (( 2 :: int)::ii)))) then I_M_Software
-   else if (((l__50 = (( 3 :: int)::ii)))) then I_U_Timer
-   else if (((l__50 = (( 4 :: int)::ii)))) then I_S_Timer
-   else if (((l__50 = (( 5 :: int)::ii)))) then I_M_Timer
-   else if (((l__50 = (( 6 :: int)::ii)))) then I_U_External
-   else if (((l__50 = (( 7 :: int)::ii)))) then I_S_External
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then I_U_Software
+   else if (((p00 = (( 1 :: int)::ii)))) then I_S_Software
+   else if (((p00 = (( 2 :: int)::ii)))) then I_M_Software
+   else if (((p00 = (( 3 :: int)::ii)))) then I_U_Timer
+   else if (((p00 = (( 4 :: int)::ii)))) then I_S_Timer
+   else if (((p00 = (( 5 :: int)::ii)))) then I_M_Timer
+   else if (((p00 = (( 6 :: int)::ii)))) then I_U_External
+   else if (((p00 = (( 7 :: int)::ii)))) then I_S_External
    else I_M_External))"
 
 
@@ -587,9 +741,9 @@ fun interruptType_to_bits  :: " InterruptType \<Rightarrow>(4)Word.word "  where
 
 definition TrapVectorMode_of_num  :: " int \<Rightarrow> TrapVectorMode "  where 
      " TrapVectorMode_of_num arg0 = (
-   (let l__48 = arg0 in
-   if (((l__48 = (( 0 :: int)::ii)))) then TV_Direct
-   else if (((l__48 = (( 1 :: int)::ii)))) then TV_Vector
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then TV_Direct
+   else if (((p00 = (( 1 :: int)::ii)))) then TV_Vector
    else TV_Reserved))"
 
 
@@ -627,10 +781,10 @@ definition internal_error  :: " string \<Rightarrow>((register_value),'a,(except
 
 definition ExtStatus_of_num  :: " int \<Rightarrow> ExtStatus "  where 
      " ExtStatus_of_num arg0 = (
-   (let l__45 = arg0 in
-   if (((l__45 = (( 0 :: int)::ii)))) then Off
-   else if (((l__45 = (( 1 :: int)::ii)))) then Initial
-   else if (((l__45 = (( 2 :: int)::ii)))) then Clean
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Off
+   else if (((p00 = (( 1 :: int)::ii)))) then Initial
+   else if (((p00 = (( 2 :: int)::ii)))) then Clean
    else Dirty))"
 
 
@@ -667,9 +821,9 @@ definition extStatus_of_bits  :: "(2)Word.word \<Rightarrow> ExtStatus "  where
 
 definition SATPMode_of_num  :: " int \<Rightarrow> SATPMode "  where 
      " SATPMode_of_num arg0 = (
-   (let l__43 = arg0 in
-   if (((l__43 = (( 0 :: int)::ii)))) then Sbare
-   else if (((l__43 = (( 1 :: int)::ii)))) then Sv32
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Sbare
+   else if (((p00 = (( 1 :: int)::ii)))) then Sv32
    else Sv39))"
 
 
@@ -684,15 +838,26 @@ fun num_of_SATPMode  :: " SATPMode \<Rightarrow> int "  where
 (*val satpMode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*)
 
 definition satpMode_of_bits  :: " Architecture \<Rightarrow>(4)Word.word \<Rightarrow>(SATPMode)option "  where 
-     " satpMode_of_bits (g__113 :: Architecture) (b__0 :: satp_mode) = ( Some Sbare )"
+     " satpMode_of_bits (g__33 :: Architecture) (b__0 :: satp_mode) = (
+      if (((b__0 = (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)))) then Some Sbare
+      else
+        (case  (g__33, b__0) of
+          (RV32, b__1) =>
+           if (((b__1 = (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word)))) then Some Sv32
+           else (case  (RV32, b__1) of   (g__34, g__35) => None )
+        | (RV64, b__2) =>
+           if (((b__2 = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) then Some Sv39
+           else (case  (RV64, b__2) of   (g__34, g__35) => None )
+        | (g__34, g__35) => None
+        ))"
 
 
 (*val uop_of_num : integer -> uop*)
 
 definition uop_of_num  :: " int \<Rightarrow> uop "  where 
      " uop_of_num arg0 = (
-   (let l__42 = arg0 in
-   if (((l__42 = (( 0 :: int)::ii)))) then RISCV_LUI
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RISCV_LUI
    else RISCV_AUIPC))"
 
 
@@ -707,12 +872,12 @@ fun num_of_uop  :: " uop \<Rightarrow> int "  where
 
 definition bop_of_num  :: " int \<Rightarrow> bop "  where 
      " bop_of_num arg0 = (
-   (let l__37 = arg0 in
-   if (((l__37 = (( 0 :: int)::ii)))) then RISCV_BEQ
-   else if (((l__37 = (( 1 :: int)::ii)))) then RISCV_BNE
-   else if (((l__37 = (( 2 :: int)::ii)))) then RISCV_BLT
-   else if (((l__37 = (( 3 :: int)::ii)))) then RISCV_BGE
-   else if (((l__37 = (( 4 :: int)::ii)))) then RISCV_BLTU
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RISCV_BEQ
+   else if (((p00 = (( 1 :: int)::ii)))) then RISCV_BNE
+   else if (((p00 = (( 2 :: int)::ii)))) then RISCV_BLT
+   else if (((p00 = (( 3 :: int)::ii)))) then RISCV_BGE
+   else if (((p00 = (( 4 :: int)::ii)))) then RISCV_BLTU
    else RISCV_BGEU))"
 
 
@@ -731,12 +896,12 @@ fun num_of_bop  :: " bop \<Rightarrow> int "  where
 
 definition iop_of_num  :: " int \<Rightarrow> iop "  where 
      " iop_of_num arg0 = (
-   (let l__32 = arg0 in
-   if (((l__32 = (( 0 :: int)::ii)))) then RISCV_ADDI
-   else if (((l__32 = (( 1 :: int)::ii)))) then RISCV_SLTI
-   else if (((l__32 = (( 2 :: int)::ii)))) then RISCV_SLTIU
-   else if (((l__32 = (( 3 :: int)::ii)))) then RISCV_XORI
-   else if (((l__32 = (( 4 :: int)::ii)))) then RISCV_ORI
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDI
+   else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SLTI
+   else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLTIU
+   else if (((p00 = (( 3 :: int)::ii)))) then RISCV_XORI
+   else if (((p00 = (( 4 :: int)::ii)))) then RISCV_ORI
    else RISCV_ANDI))"
 
 
@@ -755,9 +920,9 @@ fun num_of_iop  :: " iop \<Rightarrow> int "  where
 
 definition sop_of_num  :: " int \<Rightarrow> sop "  where 
      " sop_of_num arg0 = (
-   (let l__30 = arg0 in
-   if (((l__30 = (( 0 :: int)::ii)))) then RISCV_SLLI
-   else if (((l__30 = (( 1 :: int)::ii)))) then RISCV_SRLI
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RISCV_SLLI
+   else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SRLI
    else RISCV_SRAI))"
 
 
@@ -773,16 +938,16 @@ fun num_of_sop  :: " sop \<Rightarrow> int "  where
 
 definition rop_of_num  :: " int \<Rightarrow> rop "  where 
      " rop_of_num arg0 = (
-   (let l__21 = arg0 in
-   if (((l__21 = (( 0 :: int)::ii)))) then RISCV_ADD
-   else if (((l__21 = (( 1 :: int)::ii)))) then RISCV_SUB
-   else if (((l__21 = (( 2 :: int)::ii)))) then RISCV_SLL
-   else if (((l__21 = (( 3 :: int)::ii)))) then RISCV_SLT
-   else if (((l__21 = (( 4 :: int)::ii)))) then RISCV_SLTU
-   else if (((l__21 = (( 5 :: int)::ii)))) then RISCV_XOR
-   else if (((l__21 = (( 6 :: int)::ii)))) then RISCV_SRL
-   else if (((l__21 = (( 7 :: int)::ii)))) then RISCV_SRA
-   else if (((l__21 = (( 8 :: int)::ii)))) then RISCV_OR
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADD
+   else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUB
+   else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLL
+   else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SLT
+   else if (((p00 = (( 4 :: int)::ii)))) then RISCV_SLTU
+   else if (((p00 = (( 5 :: int)::ii)))) then RISCV_XOR
+   else if (((p00 = (( 6 :: int)::ii)))) then RISCV_SRL
+   else if (((p00 = (( 7 :: int)::ii)))) then RISCV_SRA
+   else if (((p00 = (( 8 :: int)::ii)))) then RISCV_OR
    else RISCV_AND))"
 
 
@@ -805,11 +970,11 @@ fun num_of_rop  :: " rop \<Rightarrow> int "  where
 
 definition ropw_of_num  :: " int \<Rightarrow> ropw "  where 
      " ropw_of_num arg0 = (
-   (let l__17 = arg0 in
-   if (((l__17 = (( 0 :: int)::ii)))) then RISCV_ADDW
-   else if (((l__17 = (( 1 :: int)::ii)))) then RISCV_SUBW
-   else if (((l__17 = (( 2 :: int)::ii)))) then RISCV_SLLW
-   else if (((l__17 = (( 3 :: int)::ii)))) then RISCV_SRLW
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDW
+   else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUBW
+   else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLLW
+   else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SRLW
    else RISCV_SRAW))"
 
 
@@ -827,15 +992,15 @@ fun num_of_ropw  :: " ropw \<Rightarrow> int "  where
 
 definition amoop_of_num  :: " int \<Rightarrow> amoop "  where 
      " amoop_of_num arg0 = (
-   (let l__9 = arg0 in
-   if (((l__9 = (( 0 :: int)::ii)))) then AMOSWAP
-   else if (((l__9 = (( 1 :: int)::ii)))) then AMOADD
-   else if (((l__9 = (( 2 :: int)::ii)))) then AMOXOR
-   else if (((l__9 = (( 3 :: int)::ii)))) then AMOAND
-   else if (((l__9 = (( 4 :: int)::ii)))) then AMOOR
-   else if (((l__9 = (( 5 :: int)::ii)))) then AMOMIN
-   else if (((l__9 = (( 6 :: int)::ii)))) then AMOMAX
-   else if (((l__9 = (( 7 :: int)::ii)))) then AMOMINU
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then AMOSWAP
+   else if (((p00 = (( 1 :: int)::ii)))) then AMOADD
+   else if (((p00 = (( 2 :: int)::ii)))) then AMOXOR
+   else if (((p00 = (( 3 :: int)::ii)))) then AMOAND
+   else if (((p00 = (( 4 :: int)::ii)))) then AMOOR
+   else if (((p00 = (( 5 :: int)::ii)))) then AMOMIN
+   else if (((p00 = (( 6 :: int)::ii)))) then AMOMAX
+   else if (((p00 = (( 7 :: int)::ii)))) then AMOMINU
    else AMOMAXU))"
 
 
@@ -857,9 +1022,9 @@ fun num_of_amoop  :: " amoop \<Rightarrow> int "  where
 
 definition csrop_of_num  :: " int \<Rightarrow> csrop "  where 
      " csrop_of_num arg0 = (
-   (let l__7 = arg0 in
-   if (((l__7 = (( 0 :: int)::ii)))) then CSRRW
-   else if (((l__7 = (( 1 :: int)::ii)))) then CSRRS
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then CSRRW
+   else if (((p00 = (( 1 :: int)::ii)))) then CSRRS
    else CSRRC))"
 
 
@@ -875,10 +1040,10 @@ fun num_of_csrop  :: " csrop \<Rightarrow> int "  where
 
 definition word_width_of_num  :: " int \<Rightarrow> word_width "  where 
      " word_width_of_num arg0 = (
-   (let l__4 = arg0 in
-   if (((l__4 = (( 0 :: int)::ii)))) then BYTE
-   else if (((l__4 = (( 1 :: int)::ii)))) then HALF
-   else if (((l__4 = (( 2 :: int)::ii)))) then WORD
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then BYTE
+   else if (((p00 = (( 1 :: int)::ii)))) then HALF
+   else if (((p00 = (( 2 :: int)::ii)))) then WORD
    else DOUBLE))"
 
 
@@ -891,282 +1056,1141 @@ fun num_of_word_width  :: " word_width \<Rightarrow> int "  where
 |" num_of_word_width DOUBLE = ( (( 3 :: int)::ii))"
 
 
-(*val is_aligned_addr : mword ty64 -> integer -> bool*)
-
-definition is_aligned_addr  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
-     " is_aligned_addr (addr :: xlenbits) (width :: int) = (
-   (((ex_int ((hardware_mod ((Word.uint addr)) width)))) = (( 0 :: int)::ii)))"
-
+(*val reg_name_forwards : mword ty5 -> string*)
 
-(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+definition reg_name_forwards  :: "(5)Word.word \<Rightarrow> string "  where 
+     " reg_name_forwards arg0 = (
+   (let p00 = arg0 in
+   if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))
+   then
+     (''zero'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))))) then
+     (''ra'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))))) then
+     (''sp'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))))) then
+     (''gp'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     (''tp'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B1]  ::  5 Word.word)))))) then
+     (''t0'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B0]  ::  5 Word.word)))))) then
+     (''t1'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B1]  ::  5 Word.word)))))) then
+     (''t2'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     (''fp'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B1]  ::  5 Word.word)))))) then
+     (''s1'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B0]  ::  5 Word.word)))))) then
+     (''a0'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B1]  ::  5 Word.word)))))) then
+     (''a1'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     (''a2'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B1]  ::  5 Word.word)))))) then
+     (''a3'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B0]  ::  5 Word.word)))))) then
+     (''a4'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B1]  ::  5 Word.word)))))) then
+     (''a5'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))))) then
+     (''a6'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B1]  ::  5 Word.word)))))) then
+     (''a7'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B0]  ::  5 Word.word)))))) then
+     (''s2'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B1]  ::  5 Word.word)))))) then
+     (''s3'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     (''s4'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B1]  ::  5 Word.word)))))) then
+     (''s5'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B0]  ::  5 Word.word)))))) then
+     (''s6'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B1]  ::  5 Word.word)))))) then
+     (''s7'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     (''s8'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B1]  ::  5 Word.word)))))) then
+     (''s9'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B0]  ::  5 Word.word)))))) then
+     (''s10'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B1]  ::  5 Word.word)))))) then
+     (''s11'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     (''t3'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B1]  ::  5 Word.word)))))) then
+     (''t4'')
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word)))))) then
+     (''t5'')
+   else (''t6'')))"
 
-definition checked_mem_read  :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " checked_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) = (
-   (RISCV_read addr width  :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 ::
-      (( 'int8_times_n::len)Word.word)option) . 
-   return ((case  (t, w__0) of
-     (Instruction, None) => MemException E_Fetch_Access_Fault
-   | (Data, None) => MemException E_Load_Access_Fault
-   | (_, Some (v)) => MemValue v
-   ))))"
 
+(*val reg_name_backwards : string -> mword ty5*)
+
+definition reg_name_backwards  :: " string \<Rightarrow>(5)Word.word "  where 
+     " reg_name_backwards arg0 = ( 
+  if(arg0 = (''zero'')) then ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))
+  else
+    (
+    if(arg0 = (''ra'')) then ((vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))
+    else
+      (
+      if(arg0 = (''sp'')) then
+        ((vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)) else
+        (
+        if(arg0 = (''gp'')) then
+          ((vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)) else
+          (
+          if(arg0 = (''tp'')) then
+            ((vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)) else
+            (
+            if(arg0 = (''t0'')) then
+              ((vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)) else
+              (
+              if(arg0 = (''t1'')) then
+                ((vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)) else
+                (
+                if(arg0 = (''t2'')) then
+                  ((vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)) else
+                  (
+                  if(arg0 = (''fp'')) then
+                    ((vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)) else
+                    (
+                    if(arg0 = (''s1'')) then
+                      ((vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)) else
+                      (
+                      if(arg0 = (''a0'')) then
+                        ((vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)) else
+                        (
+                        if(arg0 = (''a1'')) then
+                          ((vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word))
+                        else
+                          (
+                          if(arg0 = (''a2'')) then
+                            ((vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))
+                          else
+                            (
+                            if(arg0 = (''a3'')) then
+                              ((vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word))
+                            else
+                              (
+                              if(arg0 = (''a4'')) then
+                                ((vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word))
+                              else
+                                (
+                                if(arg0 = (''a5'')) then
+                                  ((vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word))
+                                else
+                                  (
+                                  if(arg0 = (''a6'')) then
+                                    ((vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))
+                                  else
+                                    (
+                                    if(arg0 = (''a7'')) then
+                                      ((vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word))
+                                    else
+                                      (
+                                      if(arg0 = (''s2'')) then
+                                        ((vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word))
+                                      else
+                                        (
+                                        if(arg0 = (''s3'')) then
+                                          ((vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word))
+                                        else
+                                          (
+                                          if(arg0 = (''s4'')) then
+                                            ((vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word))
+                                          else
+                                            (
+                                            if(arg0 = (''s5'')) then
+                                              ((vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word))
+                                            else
+                                              (
+                                              if(arg0 = (''s6'')) then
+                                                ((vec_of_bits
+                                                    [B1,B0,B1,B1,B0] :: 5 Word.word))
+                                              else
+                                                (
+                                                if(arg0 = (''s7'')) then
+                                                  ((vec_of_bits
+                                                      [B1,B0,B1,B1,B1] :: 5 Word.word))
+                                                else
+                                                  (
+                                                  if(arg0 = (''s8'')) then
+                                                    ((vec_of_bits
+                                                        [B1,B1,B0,B0,B0] :: 5 Word.word))
+                                                  else
+                                                    (
+                                                    if(arg0 = (''s9'')) then
+                                                      ((vec_of_bits
+                                                          [B1,B1,B0,B0,B1] :: 5 Word.word))
+                                                    else
+                                                      (
+                                                      if(arg0 = (''s10'')) then
+                                                        ((vec_of_bits
+                                                            [B1,B1,B0,B1,B0] :: 5 Word.word))
+                                                      else
+                                                        (
+                                                        if(arg0 = (''s11'')) then
+                                                          ((vec_of_bits
+                                                              [B1,B1,B0,B1,B1] :: 5 Word.word))
+                                                        else
+                                                          (
+                                                          if(arg0 = (''t3'')) then
+                                                            ((vec_of_bits
+                                                                [B1,B1,B1,B0,B0] :: 5 Word.word))
+                                                          else
+                                                            (
+                                                            if(arg0 =
+                                                                 (''t4'')) then
+                                                              ((vec_of_bits
+                                                                  [B1,B1,B1,B0,B1] :: 5 Word.word))
+                                                            else
+                                                              (
+                                                              if(arg0 =
+                                                                   (''t5'')) then
+                                                                ((vec_of_bits
+                                                                    [B1,B1,B1,B1,B0] :: 5 Word.word))
+                                                              else
+                                                                (
+                                                                if(arg0 =
+                                                                    (''t6'')) then
+                                                                  ((vec_of_bits
+                                                                    [B1,B1,B1,B1,B1] :: 5 Word.word))
+                                                                else
+                                                                  undefined))))))))))))))))))))))))))))))) )"
+
+
+(*val reg_name_forwards_matches : mword ty5 -> bool*)
+
+definition reg_name_forwards_matches  :: "(5)Word.word \<Rightarrow> bool "  where 
+     " reg_name_forwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))
+   then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B1]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B1]  ::  5 Word.word)))))) then
+     True
+   else False))"
 
-(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val reg_name_backwards_matches : string -> bool*)
+
+definition reg_name_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " reg_name_backwards_matches arg0 = ( 
+  if(arg0 = (''zero'')) then True else
+    (
+    if(arg0 = (''ra'')) then True else
+      (
+      if(arg0 = (''sp'')) then True else
+        (
+        if(arg0 = (''gp'')) then True else
+          (
+          if(arg0 = (''tp'')) then True else
+            (
+            if(arg0 = (''t0'')) then True else
+              (
+              if(arg0 = (''t1'')) then True else
+                (
+                if(arg0 = (''t2'')) then True else
+                  (
+                  if(arg0 = (''fp'')) then True else
+                    (
+                    if(arg0 = (''s1'')) then True else
+                      (
+                      if(arg0 = (''a0'')) then True else
+                        (
+                        if(arg0 = (''a1'')) then True else
+                          (
+                          if(arg0 = (''a2'')) then True else
+                            (
+                            if(arg0 = (''a3'')) then True else
+                              (
+                              if(arg0 = (''a4'')) then True else
+                                (
+                                if(arg0 = (''a5'')) then True else
+                                  (
+                                  if(arg0 = (''a6'')) then True else
+                                    (
+                                    if(arg0 = (''a7'')) then True else
+                                      (
+                                      if(arg0 = (''s2'')) then True else
+                                        (
+                                        if(arg0 = (''s3'')) then True else
+                                          (
+                                          if(arg0 = (''s4'')) then True else
+                                            (
+                                            if(arg0 = (''s5'')) then 
+                                            True else
+                                              (
+                                              if(arg0 = (''s6'')) then 
+                                              True else
+                                                (
+                                                if(arg0 = (''s7'')) then 
+                                                True else
+                                                  (
+                                                  if(arg0 = (''s8'')) then
+                                                    True else
+                                                    (
+                                                    if(arg0 = (''s9'')) then
+                                                      True else
+                                                      (
+                                                      if(arg0 = (''s10'')) then
+                                                        True else
+                                                        (
+                                                        if(arg0 = (''s11'')) then
+                                                          True else
+                                                          (
+                                                          if(arg0 = (''t3'')) then
+                                                            True else
+                                                            (
+                                                            if(arg0 =
+                                                                 (''t4'')) then
+                                                              True else
+                                                              (
+                                                              if(arg0 =
+                                                                   (''t5'')) then
+                                                                True else
+                                                                (
+                                                                if(arg0 =
+                                                                    (''t6'')) then
+                                                                  True else
+                                                                  False))))))))))))))))))))))))))))))) )"
+
+
+(*val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))*)
+
+definition reg_name_matches_prefix  :: " string \<Rightarrow>((5)Word.word*int)option "  where 
+     " reg_name_matches_prefix arg0 = (
+   (let stringappend_18140 = arg0 in
+   if (((((string_startswith stringappend_18140 (''zero''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''zero''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''zero''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''ra''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''ra''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''ra''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''sp''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''sp''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''sp''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''gp''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''gp''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''gp''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''tp''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''tp''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''tp''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t0''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t0''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t0''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t1''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t1''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t1''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t2''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t2''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t2''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''fp''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''fp''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''fp''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s1''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s1''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s1''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B0,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a0''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a0''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a0''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B0,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a1''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a1''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a1''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B0,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a2''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a2''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a2''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a3''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a3''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a3''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a4''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a4''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a4''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a5''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a5''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a5''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a6''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a6''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a6''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''a7''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''a7''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''a7''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B0,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s2''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s2''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s2''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B0,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s3''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s3''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s3''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B0,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s4''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s4''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s4''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s5''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s5''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s5''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s6''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s6''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s6''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s7''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s7''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s7''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s8''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s8''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s8''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s9''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s9''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s9''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s10''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s10''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s10''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''s11''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''s11''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''s11''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t3''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t3''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t3''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t4''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t4''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t4''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B0,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t5''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t5''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t5''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B1,B0]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_18140 (''t6''))) \<and> (
+  (case  ((string_drop stringappend_18140 ((string_length (''t6''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_18140 ((string_length (''t6''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B1,B1]  ::  5 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
 
-(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val sep_forwards : unit -> string*)
+
+definition sep_forwards  :: " unit \<Rightarrow> string "  where 
+     " sep_forwards _ = (
+      string_append ((opt_spc_forwards () ))
+        ((string_append ('','') ((string_append ((def_spc_forwards () )) (''''))))))"
+
+
+(*val sep_backwards : string -> unit*)
+
+definition sep_backwards  :: " string \<Rightarrow> unit "  where 
+     " sep_backwards arg0 = (
+   (let stringappend_18070 = arg0 in  
+  (case 
+  (case  ((opt_spc_matches_prefix stringappend_18070)) of
+        Some (stringappend_18080,stringappend_18090) => (stringappend_18080, stringappend_18090)
+  ) of
+      (_, stringappend_18090) =>
+  (let stringappend_18100 = (string_drop stringappend_18070
+                               stringappend_18090) in
+  (let stringappend_18110 = (string_drop stringappend_18100
+                               ((string_length ('','')))) in
+  (case 
+  (case  ((opt_spc_matches_prefix stringappend_18110)) of
+        Some (stringappend_18120,stringappend_18130) => (stringappend_18120, stringappend_18130)
+  ) of
+      (_, stringappend_18130) =>
+  if(((string_drop stringappend_18110 stringappend_18130)) = ('''')) then 
+  ()  else undefined
+  )))
+  )))"
+
+
+(*val sep_forwards_matches : unit -> bool*)
+
+definition sep_forwards_matches  :: " unit \<Rightarrow> bool "  where 
+     " sep_forwards_matches _ = ( True )"
+
+
+(*val sep_backwards_matches : string -> bool*)
+
+definition sep_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " sep_backwards_matches arg0 = (
+   (let stringappend_18000 = arg0 in
+   if ((case  ((opt_spc_matches_prefix stringappend_18000)) of
+       Some (stringappend_18010,stringappend_18020) =>
+        (let stringappend_18030 = (string_drop stringappend_18000 stringappend_18020) in
+        if (((((string_startswith stringappend_18030 ('',''))) \<and> ((let stringappend_18040 = (string_drop stringappend_18030 ((string_length ('','')))) in
+               if ((case  ((opt_spc_matches_prefix stringappend_18040)) of
+                   Some (stringappend_18050,stringappend_18060) => 
+  if(((string_drop stringappend_18040 stringappend_18060)) = ('''')) then
+    True else False
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+          True
+        else False)
+     | None => False
+     )) then  (case 
+ (case  ((opt_spc_matches_prefix stringappend_18000)) of
+       Some (stringappend_18010,stringappend_18020) =>
+ (stringappend_18010, stringappend_18020)
+ ) of
+     (_, stringappend_18020) =>
+ (let stringappend_18030 = (string_drop stringappend_18000 stringappend_18020) in
+ (let stringappend_18040 = (string_drop stringappend_18030
+                              ((string_length ('','')))) in
+ (case 
+ (case  ((opt_spc_matches_prefix stringappend_18040)) of
+       Some (stringappend_18050,stringappend_18060) =>
+ (stringappend_18050, stringappend_18060)
+ ) of
+     (_, stringappend_18060) =>
+ if(((string_drop stringappend_18040 stringappend_18060)) = ('''')) then 
+ True else undefined
+ )))
+ )
+   else False))"
 
-(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+(*val sep_matches_prefix : string -> maybe ((unit * ii))*)
+
+definition sep_matches_prefix  :: " string \<Rightarrow>(unit*int)option "  where 
+     " sep_matches_prefix arg0 = (
+   (let stringappend_17930 = arg0 in
+   if ((case  ((opt_spc_matches_prefix stringappend_17930)) of
+       Some (stringappend_17940,stringappend_17950) =>
+        (let stringappend_17960 = (string_drop stringappend_17930 stringappend_17950) in
+        if (((((string_startswith stringappend_17960 ('',''))) \<and> ((let stringappend_17970 = (string_drop stringappend_17960 ((string_length ('','')))) in
+               if ((case  ((opt_spc_matches_prefix stringappend_17970)) of
+                   Some (stringappend_17980,stringappend_17990) => 
+  (case  ((string_drop stringappend_17970 stringappend_17990)) of
+        s0 => True
+  )
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+          True
+        else False)
+     | None => False
+     )) then  (case 
+ (case  ((opt_spc_matches_prefix stringappend_17930)) of
+       Some (stringappend_17940,stringappend_17950) =>
+ (stringappend_17940, stringappend_17950)
+ ) of
+     (_, stringappend_17950) =>
+ (let stringappend_17960 = (string_drop stringappend_17930 stringappend_17950) in
+ (let stringappend_17970 = (string_drop stringappend_17960
+                              ((string_length ('','')))) in
+ (case 
+ (case  ((opt_spc_matches_prefix stringappend_17970)) of
+       Some (stringappend_17980,stringappend_17990) =>
+ (stringappend_17980, stringappend_17990)
+ ) of
+     (_, stringappend_17990) =>
+ (case  ((string_drop stringappend_17970 stringappend_17990)) of
+       s0 => Some (() , ((string_length arg0)) - ((string_length s0)))
+ )
+ )))
+ )
+   else None))"
 
-definition MEMr  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " MEMr addr width = ( (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
+(*val bool_bits_forwards : bool -> mword ty1*)
 
-definition MEMr_acquire  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " MEMr_acquire addr width = (
-   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
+fun bool_bits_forwards  :: " bool \<Rightarrow>(1)Word.word "  where 
+     " bool_bits_forwards True = ( (vec_of_bits [B1]  ::  1 Word.word))"
+|" bool_bits_forwards False = ( (vec_of_bits [B0]  ::  1 Word.word))"
 
 
-definition MEMr_strong_acquire  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " MEMr_strong_acquire addr width = (
-   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
+(*val bool_bits_backwards : mword ty1 -> bool*)
 
+definition bool_bits_backwards  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bool_bits_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else False))"
 
-definition MEMr_reserved  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " MEMr_reserved addr width = (
-   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
+(*val bool_bits_forwards_matches : bool -> bool*)
 
-definition MEMr_reserved_acquire  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " MEMr_reserved_acquire addr width = (
-   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
+fun bool_bits_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " bool_bits_forwards_matches True = ( True )"
+|" bool_bits_forwards_matches False = ( True )"
 
 
-definition MEMr_reserved_strong_acquire  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " MEMr_reserved_strong_acquire addr width = (
-   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
+(*val bool_bits_backwards_matches : mword ty1 -> bool*)
 
+definition bool_bits_backwards_matches  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bool_bits_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else False))"
 
-(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-definition mem_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
-     " mem_read addr width aq rl res = (
-   if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
-     return (MemException E_Load_Addr_Align)
-   else
-     (case  (aq, rl, res) of
-       (False, False, False) => (MEMr addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
-     | (True, False, False) => (MEMr_acquire addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
-     | (False, False, True) =>
-        (MEMr_reserved addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
-     | (True, False, True) =>
-        (MEMr_reserved_acquire addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
-     | (False, True, False) => throw (Error_not_implemented (''load.rl''))
-     | (True, True, False) =>
-        (MEMr_strong_acquire addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
-     | (False, True, True) => throw (Error_not_implemented (''lr.rl''))
-     | (True, True, True) =>
-        (MEMr_reserved_strong_acquire addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
-     ))"
+(*val bool_not_bits_forwards : bool -> mword ty1*)
 
+fun bool_not_bits_forwards  :: " bool \<Rightarrow>(1)Word.word "  where 
+     " bool_not_bits_forwards True = ( (vec_of_bits [B0]  ::  1 Word.word))"
+|" bool_not_bits_forwards False = ( (vec_of_bits [B1]  ::  1 Word.word))"
 
-(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
 
-definition mem_write_ea  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " mem_write_ea addr width aq rl con = (
-   if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
-     return (MemException E_SAMO_Addr_Align)
-   else
-     (case  (aq, rl, con) of
-       (False, False, False) => MEMea addr width \<then> return (MemValue () )
-     | (False, True, False) => MEMea_release addr width \<then> return (MemValue () )
-     | (False, False, True) => MEMea_conditional addr width \<then> return (MemValue () )
-     | (False, True, True) => MEMea_conditional_release addr width \<then> return (MemValue () )
-     | (True, False, False) => throw (Error_not_implemented (''store.aq''))
-     | (True, True, False) => MEMea_strong_release addr width \<then> return (MemValue () )
-     | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
-     | (True, True, True) => MEMea_conditional_strong_release addr width \<then> return (MemValue () )
-     ))"
+(*val bool_not_bits_backwards : mword ty1 -> bool*)
 
+definition bool_not_bits_backwards  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bool_not_bits_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else False))"
 
-(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-definition checked_mem_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " checked_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = (
-   RISCV_write addr width data \<bind> (\<lambda> (w__0 :: bool) . 
-   return (if w__0 then MemValue () 
-           else MemException E_SAMO_Access_Fault)))"
+(*val bool_not_bits_forwards_matches : bool -> bool*)
 
+fun bool_not_bits_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " bool_not_bits_forwards_matches True = ( True )"
+|" bool_not_bits_forwards_matches False = ( True )"
 
-(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+(*val bool_not_bits_backwards_matches : mword ty1 -> bool*)
 
-(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+definition bool_not_bits_backwards_matches  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bool_not_bits_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else False))"
 
-(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+(*val size_bits_forwards : word_width -> mword ty2*)
 
-(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+fun size_bits_forwards  :: " word_width \<Rightarrow>(2)Word.word "  where 
+     " size_bits_forwards BYTE = ( (vec_of_bits [B0,B0]  ::  2 Word.word))"
+|" size_bits_forwards HALF = ( (vec_of_bits [B0,B1]  ::  2 Word.word))"
+|" size_bits_forwards WORD = ( (vec_of_bits [B1,B0]  ::  2 Word.word))"
+|" size_bits_forwards DOUBLE = ( (vec_of_bits [B1,B1]  ::  2 Word.word))"
 
-definition MEMval  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " MEMval addr width data = ( checked_mem_write addr width data )"
 
+(*val size_bits_backwards : mword ty2 -> word_width*)
 
-definition MEMval_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " MEMval_release addr width data = ( checked_mem_write addr width data )"
+definition size_bits_backwards  :: "(2)Word.word \<Rightarrow> word_width "  where 
+     " size_bits_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then BYTE
+   else if (((p00 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then HALF
+   else if (((p00 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then WORD
+   else DOUBLE))"
 
 
-definition MEMval_strong_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " MEMval_strong_release addr width data = ( checked_mem_write addr width data )"
+(*val size_bits_forwards_matches : word_width -> bool*)
 
+fun size_bits_forwards_matches  :: " word_width \<Rightarrow> bool "  where 
+     " size_bits_forwards_matches BYTE = ( True )"
+|" size_bits_forwards_matches HALF = ( True )"
+|" size_bits_forwards_matches WORD = ( True )"
+|" size_bits_forwards_matches DOUBLE = ( True )"
 
-definition MEMval_conditional  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " MEMval_conditional addr width data = ( checked_mem_write addr width data )"
 
+(*val size_bits_backwards_matches : mword ty2 -> bool*)
 
-definition MEMval_conditional_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " MEMval_conditional_release addr width data = ( checked_mem_write addr width data )"
+definition size_bits_backwards_matches  :: "(2)Word.word \<Rightarrow> bool "  where 
+     " size_bits_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0]  ::  2 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B1]  ::  2 Word.word)))) then True
+   else False))"
 
 
-definition MEMval_conditional_strong_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " MEMval_conditional_strong_release addr width data = ( checked_mem_write addr width data )"
+(*val size_mnemonic_forwards : word_width -> string*)
+
+fun size_mnemonic_forwards  :: " word_width \<Rightarrow> string "  where 
+     " size_mnemonic_forwards BYTE = ( (''b''))"
+|" size_mnemonic_forwards HALF = ( (''h''))"
+|" size_mnemonic_forwards WORD = ( (''w''))"
+|" size_mnemonic_forwards DOUBLE = ( (''d''))"
+
+
+(*val size_mnemonic_backwards : string -> word_width*)
+
+definition size_mnemonic_backwards  :: " string \<Rightarrow> word_width "  where 
+     " size_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''b'')) then BYTE else
+    (
+    if(arg0 = (''h'')) then HALF else
+      (
+      if(arg0 = (''w'')) then WORD else
+        (if(arg0 = (''d'')) then DOUBLE else undefined))) )"
+
+
+(*val size_mnemonic_forwards_matches : word_width -> bool*)
+
+fun size_mnemonic_forwards_matches  :: " word_width \<Rightarrow> bool "  where 
+     " size_mnemonic_forwards_matches BYTE = ( True )"
+|" size_mnemonic_forwards_matches HALF = ( True )"
+|" size_mnemonic_forwards_matches WORD = ( True )"
+|" size_mnemonic_forwards_matches DOUBLE = ( True )"
+
+
+(*val size_mnemonic_backwards_matches : string -> bool*)
+
+definition size_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " size_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''b'')) then True else
+    (
+    if(arg0 = (''h'')) then True else
+      (
+      if(arg0 = (''w'')) then True else
+        (if(arg0 = (''d'')) then True else False))) )"
+
+
+(*val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))*)
+
+definition size_mnemonic_matches_prefix  :: " string \<Rightarrow>(word_width*int)option "  where 
+     " size_mnemonic_matches_prefix arg0 = (
+   (let stringappend_17890 = arg0 in
+   if (((((string_startswith stringappend_17890 (''b''))) \<and> (
+  (case  ((string_drop stringappend_17890 ((string_length (''b''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17890 ((string_length (''b''))))) of
+       s0 => Some (BYTE, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17890 (''h''))) \<and> (
+  (case  ((string_drop stringappend_17890 ((string_length (''h''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17890 ((string_length (''h''))))) of
+       s0 => Some (HALF, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17890 (''w''))) \<and> (
+  (case  ((string_drop stringappend_17890 ((string_length (''w''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17890 ((string_length (''w''))))) of
+       s0 => Some (WORD, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17890 (''d''))) \<and> (
+  (case  ((string_drop stringappend_17890 ((string_length (''d''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17890 ((string_length (''d''))))) of
+       s0 => Some (DOUBLE, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
 
 
-(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+(*val Mk_Misa : mword ty64 -> Misa*)
 
-definition mem_write_value  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
-     " mem_write_value addr width value1 aq rl con = (
-   if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
-     return (MemException E_SAMO_Addr_Align)
-   else
-     (case  (aq, rl, con) of
-       (False, False, False) => MEMval addr width value1
-     | (False, True, False) => MEMval_release addr width value1
-     | (False, False, True) => MEMval_conditional addr width value1
-     | (False, True, True) => MEMval_conditional_release addr width value1
-     | (True, False, False) => throw (Error_not_implemented (''store.aq''))
-     | (True, True, False) => MEMval_strong_release addr width value1
-     | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
-     | (True, True, True) => MEMval_conditional_strong_release addr width value1
-     ))"
+definition Mk_Misa  :: "(64)Word.word \<Rightarrow> Misa "  where 
+     " Mk_Misa v = ( (| Misa_Misa_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
 
-(*val _get_Misa : Misa -> mword ty64*)
+(*val _get_Misa_bits : Misa -> mword ty64*)
 
-fun get_Misa  :: " Misa \<Rightarrow>(64)Word.word "  where 
-     " get_Misa (Mk_Misa (v)) = ( v )"
+definition get_Misa_bits  :: " Misa \<Rightarrow>(64)Word.word "  where 
+     " get_Misa_bits v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*)
+(*val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty64 -> M unit*)
 
-definition set_Misa  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Misa r_ref v = (
+definition set_Misa_bits  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Misa_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Misa v) in
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-(*val _get_SV39_PTE : SV39_PTE -> mword ty64*)
+(*val _update_Misa_bits : Misa -> mword ty64 -> Misa*)
+
+definition update_Misa_bits  :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_bits v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
 
-(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*)
+
+(*val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE*)
+
+(*val _get_SV39_PTE_bits : SV39_PTE -> mword ty64*)
+
+(*val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*)
 
 (*val _get_Misa_MXL : Misa -> mword ty2*)
 
-fun get_Misa_MXL  :: " Misa \<Rightarrow>(2)Word.word "  where 
-     " get_Misa_MXL (Mk_Misa (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii)  ::  2 Word.word))"
+definition get_Misa_MXL  :: " Misa \<Rightarrow>(2)Word.word "  where 
+     " get_Misa_MXL v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 63 :: int)::ii) (( 62 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*)
 
 definition set_Misa_MXL  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_MXL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 63 :: int)::ii) (( 62 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*)
 
-fun update_Misa_MXL  :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_MXL (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_MXL  :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_MXL v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 63 :: int)::ii) (( 62 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_Z : Misa -> mword ty1*)
 
-fun get_Misa_Z  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_Z (Mk_Misa (v)) = ( (subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_Z  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_Z v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_Z  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_Z r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 25 :: int)::ii) (( 25 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 25 :: int)::ii) (( 25 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_Z : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_Z  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_Z (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_Z  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_Z v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 25 :: int)::ii) (( 25 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_Y : Misa -> mword ty1*)
 
-fun get_Misa_Y  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_Y (Mk_Misa (v)) = ( (subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_Y  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_Y v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 24 :: int)::ii) (( 24 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_Y  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_Y r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 24 :: int)::ii) (( 24 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 24 :: int)::ii) (( 24 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_Y : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_Y  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_Y (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_Y  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_Y v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 24 :: int)::ii) (( 24 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_X : Misa -> mword ty1*)
 
-fun get_Misa_X  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_X (Mk_Misa (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_X  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_X v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 23 :: int)::ii) (( 23 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_X  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_X r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 23 :: int)::ii) (( 23 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_X : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_X  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_X (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_X  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_X v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 23 :: int)::ii) (( 23 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1177,25 +2201,33 @@ fun update_Misa_X  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_W : Misa -> mword ty1*)
 
-fun get_Misa_W  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_W (Mk_Misa (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_W  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_W v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_W  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_W r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_W : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_W  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_W (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_W  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_W v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1206,25 +2238,33 @@ fun update_Misa_W  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_V : Misa -> mword ty1*)
 
-fun get_Misa_V  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_V (Mk_Misa (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_V  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_V v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 21 :: int)::ii) (( 21 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_V  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_V r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 21 :: int)::ii) (( 21 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_V : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_V  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_V (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_V  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_V v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 21 :: int)::ii) (( 21 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1235,25 +2275,33 @@ fun update_Misa_V  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_U : Misa -> mword ty1*)
 
-fun get_Misa_U  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_U (Mk_Misa (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_U  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_U v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 20 :: int)::ii) (( 20 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_U  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_U r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 20 :: int)::ii) (( 20 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_U : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_U  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_U (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_U  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_U v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 20 :: int)::ii) (( 20 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1264,71 +2312,95 @@ fun update_Misa_U  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_T : Misa -> mword ty1*)
 
-fun get_Misa_T  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_T (Mk_Misa (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_T  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_T v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 19 :: int)::ii) (( 19 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_T  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_T r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_T : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_T  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_T (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_T  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_T v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_S : Misa -> mword ty1*)
 
-fun get_Misa_S  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_S (Mk_Misa (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_S  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_S v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 18 :: int)::ii) (( 18 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_S  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_S r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_S : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_S  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_S (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_S  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_S v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_R : Misa -> mword ty1*)
 
-fun get_Misa_R  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_R (Mk_Misa (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_R  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_R v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 17 :: int)::ii) (( 17 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_R  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_R r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 17 :: int)::ii) (( 17 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_R : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_R  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_R (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_R  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_R v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 17 :: int)::ii) (( 17 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1339,255 +2411,343 @@ fun update_Misa_R  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_Q : Misa -> mword ty1*)
 
-fun get_Misa_Q  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_Q (Mk_Misa (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_Q  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_Q v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 16 :: int)::ii) (( 16 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_Q  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_Q r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 16 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 16 :: int)::ii) (( 16 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_Q : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_Q  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_Q (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_Q  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_Q v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 16 :: int)::ii) (( 16 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_P : Misa -> mword ty1*)
 
-fun get_Misa_P  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_P (Mk_Misa (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_P  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_P v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 15 :: int)::ii) (( 15 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_P  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_P r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 15 :: int)::ii) (( 15 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_P : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_P  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_P (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_P  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_P v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 15 :: int)::ii) (( 15 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_O : Misa -> mword ty1*)
 
-fun get_Misa_O  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_O (Mk_Misa (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_O  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_O v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_O  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_O r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 14 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 14 :: int)::ii) (( 14 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_O : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_O  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_O (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_O  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_O v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 14 :: int)::ii) (( 14 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_N : Misa -> mword ty1*)
 
-fun get_Misa_N  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_N (Mk_Misa (v)) = ( (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_N  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_N v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 13 :: int)::ii) (( 13 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_N  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_N r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 13 :: int)::ii) (( 13 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_N : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_N  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_N (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_N  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_N v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 13 :: int)::ii) (( 13 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_M : Misa -> mword ty1*)
 
-fun get_Misa_M  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_M (Mk_Misa (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_M  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_M v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_M  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_M r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 12 :: int)::ii) (( 12 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_M : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_M  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_M (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_M  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_M v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 12 :: int)::ii) (( 12 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_L : Misa -> mword ty1*)
 
-fun get_Misa_L  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_L (Mk_Misa (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_L  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_L v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_L  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_L r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 11 :: int)::ii) (( 11 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_L : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_L  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_L (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_L  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_L v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 11 :: int)::ii) (( 11 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_K : Misa -> mword ty1*)
 
-fun get_Misa_K  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_K (Mk_Misa (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_K  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_K v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 10 :: int)::ii) (( 10 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_K  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_K r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 10 :: int)::ii) (( 10 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_K : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_K  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_K (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_K  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_K v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 10 :: int)::ii) (( 10 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_J : Misa -> mword ty1*)
 
-fun get_Misa_J  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_J (Mk_Misa (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_J  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_J v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_J  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_J r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_J : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_J  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_J (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_J  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_J v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_I : Misa -> mword ty1*)
 
-fun get_Misa_I  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_I (Mk_Misa (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_I  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_I v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_I  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_I r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_I : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_I  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_I (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_I  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_I v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_H : Misa -> mword ty1*)
 
-fun get_Misa_H  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_H (Mk_Misa (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_H  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_H v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_H  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_H r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_H : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_H  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_H (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_H  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_H v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_G : Misa -> mword ty1*)
 
-fun get_Misa_G  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_G (Mk_Misa (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_G  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_G v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_G  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_G r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_G : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_G  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_G (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_G  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_G v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1598,71 +2758,95 @@ fun update_Misa_G  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_F : Misa -> mword ty1*)
 
-fun get_Misa_F  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_F (Mk_Misa (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_F  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_F v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_F  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_F r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_F : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_F  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_F (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_F  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_F v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_E : Misa -> mword ty1*)
 
-fun get_Misa_E  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_E (Mk_Misa (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_E  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_E v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_E  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_E r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_E : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_E  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_E (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_E  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_E v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_D : Misa -> mword ty1*)
 
-fun get_Misa_D  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_D (Mk_Misa (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_D  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_D v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_D  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_D r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_D : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_D  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_D (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_D  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_D v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1673,71 +2857,95 @@ fun update_Misa_D  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _get_Misa_C : Misa -> mword ty1*)
 
-fun get_Misa_C  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_C (Mk_Misa (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_C  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_C v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_C  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_C r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_C : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_C  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_C (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_C  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_C v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_B : Misa -> mword ty1*)
 
-fun get_Misa_B  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_B (Mk_Misa (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_B  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_B v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_B  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_B r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_B : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_B  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_B (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_B  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_B v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Misa_A : Misa -> mword ty1*)
 
-fun get_Misa_A  :: " Misa \<Rightarrow>(1)Word.word "  where 
-     " get_Misa_A (Mk_Misa (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Misa_A  :: " Misa \<Rightarrow>(1)Word.word "  where 
+     " get_Misa_A v = ( (subrange_vec_dec(Misa_Misa_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
 
 definition set_Misa_A  :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Misa_A r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . 
-   (let r = ((get_Misa w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Misa r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Misa_Misa_chunk_0 :=
+         ((update_subrange_vec_dec(Misa_Misa_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Misa_A : Misa -> mword ty1 -> Misa*)
 
-fun update_Misa_A  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
-     " update_Misa_A (Mk_Misa (v)) x = (
-   Mk_Misa ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Misa_A  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  where 
+     " update_Misa_A v x = (
+   (v (|
+     Misa_Misa_chunk_0 :=
+       ((update_subrange_vec_dec(Misa_Misa_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*)
@@ -1746,48 +2954,85 @@ fun update_Misa_A  :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa "  whe
 
 (*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
 
-(*val legalize_misa : Misa -> mword ty64 -> Misa*)
+(*val legalize_misa : Misa -> mword ty64 -> M Misa*)
+
+definition legalize_misa  :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Misa),(exception))monad "  where 
+     " legalize_misa (m :: Misa) (v :: xlenbits) = (
+   (let v = (Mk_Misa v) in
+   and_boolM (return (((((get_Misa_C v  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))))
+     ((read_reg nextPC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . 
+      return (((((cast_unit_vec0 ((access_vec_dec w__0 (( 1 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))) \<bind> (\<lambda> (w__1 :: bool) . 
+   return (if w__1 then m
+           else update_Misa_C m ((get_Misa_C v  ::  1 Word.word))))))"
+
+
+(*val Mk_Mstatus : mword ty64 -> Mstatus*)
 
-definition legalize_misa  :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow> Misa "  where 
-     " legalize_misa (m :: Misa) (v :: xlenbits) = ( m )"
+definition Mk_Mstatus  :: "(64)Word.word \<Rightarrow> Mstatus "  where 
+     " Mk_Mstatus v = (
+   (| Mstatus_Mstatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
 
-(*val _get_Mstatus : Mstatus -> mword ty64*)
+(*val _get_Mstatus_bits : Mstatus -> mword ty64*)
 
-fun get_Mstatus  :: " Mstatus \<Rightarrow>(64)Word.word "  where 
-     " get_Mstatus (Mk_Mstatus (v)) = ( v )"
+definition get_Mstatus_bits  :: " Mstatus \<Rightarrow>(64)Word.word "  where 
+     " get_Mstatus_bits v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*)
+(*val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*)
 
-definition set_Mstatus  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Mstatus r_ref v = (
+definition set_Mstatus_bits  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Mstatus_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Mstatus v) in
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_Mstatus_bits : Mstatus -> mword ty64 -> Mstatus*)
+
+definition update_Mstatus_bits  :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_bits v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_Mstatus_SD : Mstatus -> mword ty1*)
 
-fun get_Mstatus_SD  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_SD (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_SD  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_SD v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_SD  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_SD r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_SD  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_SD (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_SD  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_SD v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*)
@@ -1798,48 +3043,64 @@ fun update_Mstatus_SD  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Msta
 
 (*val _get_Mstatus_SXL : Mstatus -> mword ty2*)
 
-fun get_Mstatus_SXL  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Mstatus_SXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii)  ::  2 Word.word))"
+definition get_Mstatus_SXL  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Mstatus_SXL v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 35 :: int)::ii) (( 34 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 definition set_Mstatus_SXL  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_SXL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 34 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 35 :: int)::ii) (( 34 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*)
 
-fun update_Mstatus_SXL  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_SXL (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_SXL  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_SXL v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 35 :: int)::ii) (( 34 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_UXL : Mstatus -> mword ty2*)
 
-fun get_Mstatus_UXL  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Mstatus_UXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii)  ::  2 Word.word))"
+definition get_Mstatus_UXL  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Mstatus_UXL v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 33 :: int)::ii) (( 32 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 definition set_Mstatus_UXL  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_UXL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 33 :: int)::ii) (( 32 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*)
 
-fun update_Mstatus_UXL  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_UXL (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_UXL  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_UXL v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 33 :: int)::ii) (( 32 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*)
@@ -1850,94 +3111,126 @@ fun update_Mstatus_UXL  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mst
 
 (*val _get_Mstatus_TSR : Mstatus -> mword ty1*)
 
-fun get_Mstatus_TSR  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_TSR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_TSR  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_TSR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_TSR  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_TSR r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_TSR  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_TSR (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_TSR  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_TSR v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_TW : Mstatus -> mword ty1*)
 
-fun get_Mstatus_TW  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_TW (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_TW  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_TW v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 21 :: int)::ii) (( 21 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_TW  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_TW r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 21 :: int)::ii) (( 21 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_TW  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_TW (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_TW  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_TW v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 21 :: int)::ii) (( 21 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_TVM : Mstatus -> mword ty1*)
 
-fun get_Mstatus_TVM  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_TVM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_TVM  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_TVM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 20 :: int)::ii) (( 20 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_TVM  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_TVM r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 20 :: int)::ii) (( 20 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_TVM  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_TVM (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_TVM  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_TVM v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 20 :: int)::ii) (( 20 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_MXR : Mstatus -> mword ty1*)
 
-fun get_Mstatus_MXR  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_MXR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_MXR  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_MXR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 19 :: int)::ii) (( 19 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_MXR  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_MXR r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_MXR  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_MXR (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_MXR  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_MXR v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*)
@@ -1948,25 +3241,33 @@ fun update_Mstatus_MXR  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst
 
 (*val _get_Mstatus_SUM : Mstatus -> mword ty1*)
 
-fun get_Mstatus_SUM  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_SUM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_SUM  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_SUM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 18 :: int)::ii) (( 18 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_SUM  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_SUM r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_SUM  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_SUM (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_SUM  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_SUM v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*)
@@ -1977,48 +3278,64 @@ fun update_Mstatus_SUM  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst
 
 (*val _get_Mstatus_MPRV : Mstatus -> mword ty1*)
 
-fun get_Mstatus_MPRV  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_MPRV (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_MPRV  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_MPRV v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 17 :: int)::ii) (( 17 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_MPRV  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_MPRV r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 17 :: int)::ii) (( 17 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_MPRV  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_MPRV (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_MPRV  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_MPRV v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 17 :: int)::ii) (( 17 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_XS : Mstatus -> mword ty2*)
 
-fun get_Mstatus_XS  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Mstatus_XS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii)  ::  2 Word.word))"
+definition get_Mstatus_XS  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Mstatus_XS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 16 :: int)::ii) (( 15 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 definition set_Mstatus_XS  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_XS r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 16 :: int)::ii) (( 15 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*)
 
-fun update_Mstatus_XS  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_XS (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_XS  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_XS v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 16 :: int)::ii) (( 15 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*)
@@ -2029,25 +3346,33 @@ fun update_Mstatus_XS  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Msta
 
 (*val _get_Mstatus_FS : Mstatus -> mword ty2*)
 
-fun get_Mstatus_FS  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Mstatus_FS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word))"
+definition get_Mstatus_FS  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Mstatus_FS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 definition set_Mstatus_FS  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_FS r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 14 :: int)::ii) (( 13 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*)
 
-fun update_Mstatus_FS  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_FS (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_FS  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_FS v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 14 :: int)::ii) (( 13 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*)
@@ -2058,48 +3383,64 @@ fun update_Mstatus_FS  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Msta
 
 (*val _get_Mstatus_MPP : Mstatus -> mword ty2*)
 
-fun get_Mstatus_MPP  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Mstatus_MPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii)  ::  2 Word.word))"
+definition get_Mstatus_MPP  :: " Mstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Mstatus_MPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 12 :: int)::ii) (( 11 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
 
 definition set_Mstatus_MPP  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_MPP r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 11 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 12 :: int)::ii) (( 11 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*)
 
-fun update_Mstatus_MPP  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_MPP (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_MPP  :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_MPP v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 12 :: int)::ii) (( 11 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_SPP : Mstatus -> mword ty1*)
 
-fun get_Mstatus_SPP  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_SPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_SPP  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_SPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_SPP  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_SPP r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
-
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
+
 
 (*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_SPP  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_SPP (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_SPP  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_SPP v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*)
@@ -2110,48 +3451,64 @@ fun update_Mstatus_SPP  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst
 
 (*val _get_Mstatus_MPIE : Mstatus -> mword ty1*)
 
-fun get_Mstatus_MPIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_MPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_MPIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_MPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_MPIE  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_MPIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_MPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_MPIE (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_MPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_MPIE v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_SPIE : Mstatus -> mword ty1*)
 
-fun get_Mstatus_SPIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_SPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_SPIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_SPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_SPIE  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_SPIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_SPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_SPIE (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_SPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_SPIE v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2162,25 +3519,33 @@ fun update_Mstatus_SPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Ms
 
 (*val _get_Mstatus_UPIE : Mstatus -> mword ty1*)
 
-fun get_Mstatus_UPIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_UPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_UPIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_UPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_UPIE  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_UPIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_UPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_UPIE (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_UPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_UPIE v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2191,48 +3556,64 @@ fun update_Mstatus_UPIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Ms
 
 (*val _get_Mstatus_MIE : Mstatus -> mword ty1*)
 
-fun get_Mstatus_MIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_MIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_MIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_MIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_MIE  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_MIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_MIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_MIE (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_MIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_MIE v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mstatus_SIE : Mstatus -> mword ty1*)
 
-fun get_Mstatus_SIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_SIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_SIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_SIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_SIE  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_SIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_SIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_SIE (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_SIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_SIE v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2243,25 +3624,33 @@ fun update_Mstatus_SIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst
 
 (*val _get_Mstatus_UIE : Mstatus -> mword ty1*)
 
-fun get_Mstatus_UIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Mstatus_UIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Mstatus_UIE  :: " Mstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Mstatus_UIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
 
 definition set_Mstatus_UIE  :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mstatus_UIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-   (let r = ((get_Mstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mstatus_Mstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*)
 
-fun update_Mstatus_UIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
-     " update_Mstatus_UIE (Mk_Mstatus (v)) x = (
-   Mk_Mstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mstatus_UIE  :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus "  where 
+     " update_Mstatus_UIE v x = (
+   (v (|
+     Mstatus_Mstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*)
@@ -2349,65 +3738,122 @@ definition haveFP  :: " unit \<Rightarrow>((register_value),(bool),(exception))m
       return (((((get_Misa_D w__1  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))))"
 
 
-(*val _get_Minterrupts : Minterrupts -> mword ty64*)
+(*val pc_alignment_mask : unit -> M (mword ty64)*)
+
+definition pc_alignment_mask  :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
+     " pc_alignment_mask _ = (
+   read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) . 
+   return ((not_vec
+              ((EXTZ (( 64 :: int)::ii)
+                  (if (((((get_Misa_C w__0  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))
+                   then
+                     (vec_of_bits [B0,B0]  ::  2 Word.word)
+                   else (vec_of_bits [B1,B0]  ::  2 Word.word))
+                 ::  64 Word.word))
+             ::  64 Word.word))))"
+
+
+(*val Mk_Minterrupts : mword ty64 -> Minterrupts*)
+
+definition Mk_Minterrupts  :: "(64)Word.word \<Rightarrow> Minterrupts "  where 
+     " Mk_Minterrupts v = (
+   (| Minterrupts_Minterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
+
+
+(*val _get_Minterrupts_bits : Minterrupts -> mword ty64*)
 
-fun get_Minterrupts  :: " Minterrupts \<Rightarrow>(64)Word.word "  where 
-     " get_Minterrupts (Mk_Minterrupts (v)) = ( v )"
+definition get_Minterrupts_bits  :: " Minterrupts \<Rightarrow>(64)Word.word "  where 
+     " get_Minterrupts_bits v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*)
+(*val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*)
 
-definition set_Minterrupts  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Minterrupts r_ref v = (
+definition set_Minterrupts_bits  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Minterrupts_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Minterrupts v) in
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_Minterrupts_bits : Minterrupts -> mword ty64 -> Minterrupts*)
+
+definition update_Minterrupts_bits  :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_bits v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_MEI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_MEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_MEI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_MEI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_MEI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_MEI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 11 :: int)::ii) (( 11 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_MEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_MEI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_MEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_MEI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 11 :: int)::ii) (( 11 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_SEI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_SEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_SEI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_SEI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_SEI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_SEI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_SEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_SEI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_SEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_SEI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2418,25 +3864,34 @@ fun update_Minterrupts_SEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar
 
 (*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_UEI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_UEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_UEI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_UEI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_UEI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_UEI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_UEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_UEI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_UEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_UEI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2447,48 +3902,66 @@ fun update_Minterrupts_UEI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar
 
 (*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_MTI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_MTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_MTI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_MTI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_MTI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_MTI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_MTI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_MTI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_MTI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_MTI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Minterrupts_STI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_STI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_STI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_STI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_STI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_STI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_STI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_STI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_STI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_STI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_STI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2499,25 +3972,34 @@ fun update_Minterrupts_STI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar
 
 (*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_UTI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_UTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_UTI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_UTI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_UTI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_UTI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_UTI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_UTI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_UTI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_UTI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2528,48 +4010,66 @@ fun update_Minterrupts_UTI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar
 
 (*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_MSI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_MSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_MSI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_MSI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_MSI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_MSI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_MSI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_MSI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_MSI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_MSI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_SSI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_SSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_SSI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_SSI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_SSI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_SSI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_SSI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_SSI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_SSI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_SSI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2580,25 +4080,34 @@ fun update_Minterrupts_SSI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar
 
 (*val _get_Minterrupts_USI : Minterrupts -> mword ty1*)
 
-fun get_Minterrupts_USI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Minterrupts_USI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Minterrupts_USI  :: " Minterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Minterrupts_USI v = (
+   (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
 
 definition set_Minterrupts_USI  :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Minterrupts_USI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   (let r = ((get_Minterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Minterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Minterrupts_Minterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*)
 
-fun update_Minterrupts_USI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
-     " update_Minterrupts_USI (Mk_Minterrupts (v)) x = (
-   Mk_Minterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Minterrupts_USI  :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts "  where 
+     " update_Minterrupts_USI v x = (
+   (v (|
+     Minterrupts_Minterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*)
@@ -2640,160 +4149,234 @@ definition legalize_mideleg  :: " Minterrupts \<Rightarrow>(64)Word.word \<Right
    update_Minterrupts_MSI m ((bool_to_bits False  ::  1 Word.word))))))"
 
 
-(*val _get_Medeleg : Medeleg -> mword ty64*)
+(*val Mk_Medeleg : mword ty64 -> Medeleg*)
+
+definition Mk_Medeleg  :: "(64)Word.word \<Rightarrow> Medeleg "  where 
+     " Mk_Medeleg v = (
+   (| Medeleg_Medeleg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
+
+
+(*val _get_Medeleg_bits : Medeleg -> mword ty64*)
 
-fun get_Medeleg  :: " Medeleg \<Rightarrow>(64)Word.word "  where 
-     " get_Medeleg (Mk_Medeleg (v)) = ( v )"
+definition get_Medeleg_bits  :: " Medeleg \<Rightarrow>(64)Word.word "  where 
+     " get_Medeleg_bits v = ( (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*)
+(*val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*)
 
-definition set_Medeleg  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Medeleg r_ref v = (
+definition set_Medeleg_bits  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Medeleg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Medeleg v) in
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_Medeleg_bits : Medeleg -> mword ty64 -> Medeleg*)
+
+definition update_Medeleg_bits  :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_bits v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*)
 
-fun get_Medeleg_SAMO_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) = (
-   (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_SAMO_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_SAMO_Page_Fault v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 15 :: int)::ii) (( 15 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_SAMO_Page_Fault  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_SAMO_Page_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 15 :: int)::ii) (( 15 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_SAMO_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_SAMO_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_SAMO_Page_Fault v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 15 :: int)::ii) (( 15 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Load_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) = (
-   (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Load_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Load_Page_Fault v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 13 :: int)::ii) (( 13 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Load_Page_Fault  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Load_Page_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 13 :: int)::ii) (( 13 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Load_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Load_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Load_Page_Fault v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 13 :: int)::ii) (( 13 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Fetch_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) = (
-   (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Fetch_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Fetch_Page_Fault v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Fetch_Page_Fault  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Fetch_Page_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 12 :: int)::ii) (( 12 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Fetch_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Fetch_Page_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Fetch_Page_Fault v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 12 :: int)::ii) (( 12 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*)
 
-fun get_Medeleg_MEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_MEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_MEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_MEnvCall v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 10 :: int)::ii) (( 10 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_MEnvCall  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_MEnvCall r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 10 :: int)::ii) (( 10 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_MEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_MEnvCall (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_MEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_MEnvCall v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 10 :: int)::ii) (( 10 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*)
 
-fun get_Medeleg_SEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_SEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_SEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_SEnvCall v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_SEnvCall  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_SEnvCall r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_SEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_SEnvCall (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_SEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_SEnvCall v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*)
 
-fun get_Medeleg_UEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_UEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_UEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_UEnvCall v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_UEnvCall  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_UEnvCall r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_UEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_UEnvCall (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_UEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_UEnvCall v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2804,26 +4387,34 @@ fun update_Medeleg_UEnvCall  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow
 
 (*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*)
 
-fun get_Medeleg_SAMO_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) = (
-   (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_SAMO_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_SAMO_Access_Fault v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_SAMO_Access_Fault  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_SAMO_Access_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_SAMO_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_SAMO_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_SAMO_Access_Fault v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2834,25 +4425,34 @@ fun update_Medeleg_SAMO_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<R
 
 (*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*)
 
-fun get_Medeleg_SAMO_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_SAMO_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_SAMO_Addr_Align v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_SAMO_Addr_Align  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_SAMO_Addr_Align r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_SAMO_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_SAMO_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_SAMO_Addr_Align v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2863,26 +4463,34 @@ fun update_Medeleg_SAMO_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rig
 
 (*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Load_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) = (
-   (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Load_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Load_Access_Fault v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Load_Access_Fault  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Load_Access_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Load_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Load_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Load_Access_Fault v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2893,25 +4501,34 @@ fun update_Medeleg_Load_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<R
 
 (*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Load_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Load_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Load_Addr_Align v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Load_Addr_Align  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Load_Addr_Align r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Load_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Load_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Load_Addr_Align v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2922,25 +4539,34 @@ fun update_Medeleg_Load_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rig
 
 (*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Breakpoint  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Breakpoint (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Breakpoint  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Breakpoint v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Breakpoint  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Breakpoint r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Breakpoint  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Breakpoint (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Breakpoint  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Breakpoint v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2951,25 +4577,34 @@ fun update_Medeleg_Breakpoint  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarr
 
 (*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Illegal_Instr  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Illegal_Instr (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Illegal_Instr  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Illegal_Instr v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Illegal_Instr  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Illegal_Instr r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Illegal_Instr  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Illegal_Instr (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Illegal_Instr  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Illegal_Instr v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -2980,26 +4615,34 @@ fun update_Medeleg_Illegal_Instr  :: " Medeleg \<Rightarrow>(1)Word.word \<Right
 
 (*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Fetch_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) = (
-   (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Fetch_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Fetch_Access_Fault v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Fetch_Access_Fault  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Fetch_Access_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Fetch_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Fetch_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Fetch_Access_Fault v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -3010,25 +4653,34 @@ fun update_Medeleg_Fetch_Access_Fault  :: " Medeleg \<Rightarrow>(1)Word.word \<
 
 (*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*)
 
-fun get_Medeleg_Fetch_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Medeleg_Fetch_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Medeleg_Fetch_Addr_Align v = (
+   (subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
 
 definition set_Medeleg_Fetch_Addr_Align  :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Medeleg_Fetch_Addr_Align r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let r = ((get_Medeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Medeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Medeleg_Medeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
 
-fun update_Medeleg_Fetch_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
-     " update_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) x = (
-   Mk_Medeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Medeleg_Fetch_Addr_Align  :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg "  where 
+     " update_Medeleg_Fetch_Addr_Align v x = (
+   (v (|
+     Medeleg_Medeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
@@ -3045,65 +4697,103 @@ definition legalize_medeleg  :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarro
    update_Medeleg_MEnvCall m ((bool_to_bits False  ::  1 Word.word))))"
 
 
-(*val _get_Mtvec : Mtvec -> mword ty64*)
+(*val Mk_Mtvec : mword ty64 -> Mtvec*)
+
+definition Mk_Mtvec  :: "(64)Word.word \<Rightarrow> Mtvec "  where 
+     " Mk_Mtvec v = ( (| Mtvec_Mtvec_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-fun get_Mtvec  :: " Mtvec \<Rightarrow>(64)Word.word "  where 
-     " get_Mtvec (Mk_Mtvec (v)) = ( v )"
 
+(*val _get_Mtvec_bits : Mtvec -> mword ty64*)
 
-(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*)
+definition get_Mtvec_bits  :: " Mtvec \<Rightarrow>(64)Word.word "  where 
+     " get_Mtvec_bits v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-definition set_Mtvec  :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Mtvec r_ref v = (
+
+(*val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*)
+
+definition set_Mtvec_bits  :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Mtvec_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Mtvec v) in
+   (let r =
+     ((r (|
+       Mtvec_Mtvec_chunk_0 :=
+         ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_Mtvec_bits : Mtvec -> mword ty64 -> Mtvec*)
+
+definition update_Mtvec_bits  :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mtvec "  where 
+     " update_Mtvec_bits v x = (
+   (v (|
+     Mtvec_Mtvec_chunk_0 :=
+       ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_Mtvec_Base : Mtvec -> mword ty62*)
 
-fun get_Mtvec_Base  :: " Mtvec \<Rightarrow>(62)Word.word "  where 
-     " get_Mtvec_Base (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii)  ::  62 Word.word))"
+definition get_Mtvec_Base  :: " Mtvec \<Rightarrow>(62)Word.word "  where 
+     " get_Mtvec_Base v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0   v) (( 63 :: int)::ii) (( 2 :: int)::ii)  ::  62 Word.word))"
 
 
 (*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*)
 
 definition set_Mtvec_Base  :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(62)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mtvec_Base r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mtvec) . 
-   (let r = ((get_Mtvec w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 2 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mtvec r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mtvec_Mtvec_chunk_0 :=
+         ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0   r) (( 63 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 61 :: int)::ii) (( 0 :: int)::ii)  ::  62 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*)
 
-fun update_Mtvec_Base  :: " Mtvec \<Rightarrow>(62)Word.word \<Rightarrow> Mtvec "  where 
-     " update_Mtvec_Base (Mk_Mtvec (v)) x = (
-   Mk_Mtvec ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mtvec_Base  :: " Mtvec \<Rightarrow>(62)Word.word \<Rightarrow> Mtvec "  where 
+     " update_Mtvec_Base v x = (
+   (v (|
+     Mtvec_Mtvec_chunk_0 :=
+       ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0   v) (( 63 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 61 :: int)::ii) (( 0 :: int)::ii)  ::  62 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mtvec_Mode : Mtvec -> mword ty2*)
 
-fun get_Mtvec_Mode  :: " Mtvec \<Rightarrow>(2)Word.word "  where 
-     " get_Mtvec_Mode (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))"
+definition get_Mtvec_Mode  :: " Mtvec \<Rightarrow>(2)Word.word "  where 
+     " get_Mtvec_Mode v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0   v) (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))"
 
 
 (*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*)
 
 definition set_Mtvec_Mode  :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mtvec_Mode r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mtvec) . 
-   (let r = ((get_Mtvec w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mtvec r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mtvec_Mtvec_chunk_0 :=
+         ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0   r) (( 1 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*)
 
-fun update_Mtvec_Mode  :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec "  where 
-     " update_Mtvec_Mode (Mk_Mtvec (v)) x = (
-   Mk_Mtvec ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mtvec_Mode  :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec "  where 
+     " update_Mtvec_Mode v x = (
+   (v (|
+     Mtvec_Mtvec_chunk_0 :=
+       ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0   v) (( 1 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*)
@@ -3124,65 +4814,104 @@ definition legalize_tvec  :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mt
    )))"
 
 
-(*val _get_Mcause : Mcause -> mword ty64*)
+(*val Mk_Mcause : mword ty64 -> Mcause*)
+
+definition Mk_Mcause  :: "(64)Word.word \<Rightarrow> Mcause "  where 
+     " Mk_Mcause v = ( (| Mcause_Mcause_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
+
+
+(*val _get_Mcause_bits : Mcause -> mword ty64*)
 
-fun get_Mcause  :: " Mcause \<Rightarrow>(64)Word.word "  where 
-     " get_Mcause (Mk_Mcause (v)) = ( v )"
+definition get_Mcause_bits  :: " Mcause \<Rightarrow>(64)Word.word "  where 
+     " get_Mcause_bits v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*)
+(*val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty64 -> M unit*)
 
-definition set_Mcause  :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Mcause r_ref v = (
+definition set_Mcause_bits  :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Mcause_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Mcause v) in
+   (let r =
+     ((r (|
+       Mcause_Mcause_chunk_0 :=
+         ((update_subrange_vec_dec(Mcause_Mcause_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
+(*val _update_Mcause_bits : Mcause -> mword ty64 -> Mcause*)
+
+definition update_Mcause_bits  :: " Mcause \<Rightarrow>(64)Word.word \<Rightarrow> Mcause "  where 
+     " update_Mcause_bits v x = (
+   (v (|
+     Mcause_Mcause_chunk_0 :=
+       ((update_subrange_vec_dec(Mcause_Mcause_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
 (*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*)
 
-fun get_Mcause_IsInterrupt  :: " Mcause \<Rightarrow>(1)Word.word "  where 
-     " get_Mcause_IsInterrupt (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
+definition get_Mcause_IsInterrupt  :: " Mcause \<Rightarrow>(1)Word.word "  where 
+     " get_Mcause_IsInterrupt v = (
+   (subrange_vec_dec(Mcause_Mcause_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
 
 
 (*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*)
 
 definition set_Mcause_IsInterrupt  :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mcause_IsInterrupt r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mcause) . 
-   (let r = ((get_Mcause w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mcause r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mcause_Mcause_chunk_0 :=
+         ((update_subrange_vec_dec(Mcause_Mcause_chunk_0   r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*)
 
-fun update_Mcause_IsInterrupt  :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause "  where 
-     " update_Mcause_IsInterrupt (Mk_Mcause (v)) x = (
-   Mk_Mcause ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mcause_IsInterrupt  :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause "  where 
+     " update_Mcause_IsInterrupt v x = (
+   (v (|
+     Mcause_Mcause_chunk_0 :=
+       ((update_subrange_vec_dec(Mcause_Mcause_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Mcause_Cause : Mcause -> mword ty63*)
 
-fun get_Mcause_Cause  :: " Mcause \<Rightarrow>(63)Word.word "  where 
-     " get_Mcause_Cause (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii)  ::  63 Word.word))"
+definition get_Mcause_Cause  :: " Mcause \<Rightarrow>(63)Word.word "  where 
+     " get_Mcause_Cause v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0   v) (( 62 :: int)::ii) (( 0 :: int)::ii)  ::  63 Word.word))"
 
 
 (*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*)
 
 definition set_Mcause_Cause  :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(63)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Mcause_Cause r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mcause) . 
-   (let r = ((get_Mcause w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Mcause r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Mcause_Mcause_chunk_0 :=
+         ((update_subrange_vec_dec(Mcause_Mcause_chunk_0   r) (( 62 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii)  ::  63 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*)
 
-fun update_Mcause_Cause  :: " Mcause \<Rightarrow>(63)Word.word \<Rightarrow> Mcause "  where 
-     " update_Mcause_Cause (Mk_Mcause (v)) x = (
-   Mk_Mcause ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Mcause_Cause  :: " Mcause \<Rightarrow>(63)Word.word \<Rightarrow> Mcause "  where 
+     " update_Mcause_Cause v x = (
+   (v (|
+     Mcause_Mcause_chunk_0 :=
+       ((update_subrange_vec_dec(Mcause_Mcause_chunk_0   v) (( 62 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 62 :: int)::ii) (( 0 :: int)::ii)  ::  63 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*)
@@ -3221,206 +4950,514 @@ definition legalize_xepc  :: "(64)Word.word \<Rightarrow>((register_value),((64)
              ::  64 Word.word))))"
 
 
-(*val _get_Sstatus : Sstatus -> mword ty64*)
+(*val Mk_Counteren : mword ty32 -> Counteren*)
+
+definition Mk_Counteren  :: "(32)Word.word \<Rightarrow> Counteren "  where 
+     " Mk_Counteren v = (
+   (| Counteren_Counteren_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) |) )"
+
+
+(*val _get_Counteren_bits : Counteren -> mword ty32*)
+
+definition get_Counteren_bits  :: " Counteren \<Rightarrow>(32)Word.word "  where 
+     " get_Counteren_bits v = (
+   (subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))"
+
+
+(*val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit*)
+
+definition set_Counteren_bits  :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Counteren_bits r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren*)
+
+definition update_Counteren_bits  :: " Counteren \<Rightarrow>(32)Word.word \<Rightarrow> Counteren "  where 
+     " update_Counteren_bits v x = (
+   (v (|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
+          ::  32 Word.word))|)))"
+
+
+(*val _get_Counteren_HPM : Counteren -> mword ty29*)
+
+definition get_Counteren_HPM  :: " Counteren \<Rightarrow>(29)Word.word "  where 
+     " get_Counteren_HPM v = (
+   (subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 31 :: int)::ii) (( 3 :: int)::ii)  ::  29 Word.word))"
+
+
+(*val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit*)
+
+definition set_Counteren_HPM  :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(29)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Counteren_HPM r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   r) (( 31 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 28 :: int)::ii) (( 0 :: int)::ii)  ::  29 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren*)
+
+definition update_Counteren_HPM  :: " Counteren \<Rightarrow>(29)Word.word \<Rightarrow> Counteren "  where 
+     " update_Counteren_HPM v x = (
+   (v (|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 31 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 28 :: int)::ii) (( 0 :: int)::ii)  ::  29 Word.word))
+          ::  32 Word.word))|)))"
+
+
+(*val _get_Counteren_IR : Counteren -> mword ty1*)
+
+definition get_Counteren_IR  :: " Counteren \<Rightarrow>(1)Word.word "  where 
+     " get_Counteren_IR v = (
+   (subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+
+
+(*val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+definition set_Counteren_IR  :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Counteren_IR r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren*)
+
+definition update_Counteren_IR  :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren "  where 
+     " update_Counteren_IR v x = (
+   (v (|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
+
+
+(*val _get_Counteren_TM : Counteren -> mword ty1*)
+
+definition get_Counteren_TM  :: " Counteren \<Rightarrow>(1)Word.word "  where 
+     " get_Counteren_TM v = (
+   (subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+
+
+(*val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+definition set_Counteren_TM  :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Counteren_TM r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren*)
+
+definition update_Counteren_TM  :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren "  where 
+     " update_Counteren_TM v x = (
+   (v (|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
+
+
+(*val _get_Counteren_CY : Counteren -> mword ty1*)
+
+definition get_Counteren_CY  :: " Counteren \<Rightarrow>(1)Word.word "  where 
+     " get_Counteren_CY v = (
+   (subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+
+
+(*val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+definition set_Counteren_CY  :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Counteren_CY r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Counteren_Counteren_chunk_0 :=
+         ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  32 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren*)
+
+definition update_Counteren_CY  :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren "  where 
+     " update_Counteren_CY v x = (
+   (v (|
+     Counteren_Counteren_chunk_0 :=
+       ((update_subrange_vec_dec(Counteren_Counteren_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  32 Word.word))|)))"
+
+
+(*val legalize_mcounteren : Counteren -> mword ty64 -> Counteren*)
+
+definition legalize_mcounteren  :: " Counteren \<Rightarrow>(64)Word.word \<Rightarrow> Counteren "  where 
+     " legalize_mcounteren (c :: Counteren) (v :: xlenbits) = (
+   (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii)))  ::  1 Word.word))) in
+   (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii)))  ::  1 Word.word))) in
+   update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii)))  ::  1 Word.word)))))"
+
+
+(*val legalize_scounteren : Counteren -> mword ty64 -> Counteren*)
 
-fun get_Sstatus  :: " Sstatus \<Rightarrow>(64)Word.word "  where 
-     " get_Sstatus (Mk_Sstatus (v)) = ( v )"
+definition legalize_scounteren  :: " Counteren \<Rightarrow>(64)Word.word \<Rightarrow> Counteren "  where 
+     " legalize_scounteren (c :: Counteren) (v :: xlenbits) = (
+   (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii)))  ::  1 Word.word))) in
+   (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii)))  ::  1 Word.word))) in
+   update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii)))  ::  1 Word.word)))))"
 
 
-(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*)
+(*val retire_instruction : unit -> M unit*)
 
-definition set_Sstatus  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Sstatus r_ref v = (
+definition retire_instruction  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " retire_instruction _ = (
+   read_reg minstret_written_ref \<bind> (\<lambda> (w__0 :: bool) . 
+   if (((((bool_to_bits w__0  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) then
+     write_reg minstret_written_ref False
+   else
+     (read_reg minstret_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
+     write_reg minstret_ref ((add_vec_int w__1 (( 1 :: int)::ii)  ::  64 Word.word)))))"
+
+
+(*val Mk_Sstatus : mword ty64 -> Sstatus*)
+
+definition Mk_Sstatus  :: "(64)Word.word \<Rightarrow> Sstatus "  where 
+     " Mk_Sstatus v = (
+   (| Sstatus_Sstatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
+
+
+(*val _get_Sstatus_bits : Sstatus -> mword ty64*)
+
+definition get_Sstatus_bits  :: " Sstatus \<Rightarrow>(64)Word.word "  where 
+     " get_Sstatus_bits v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
+
+
+(*val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*)
+
+definition set_Sstatus_bits  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Sstatus_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Sstatus v) in
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-fun get_Sstatus_SD  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_SD (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
+(*val _update_Sstatus_bits : Sstatus -> mword ty64 -> Sstatus*)
+
+definition update_Sstatus_bits  :: " Sstatus \<Rightarrow>(64)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_bits v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
+definition get_Sstatus_SD  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_SD v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_SD  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_SD r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_SD  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_SD (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_SD  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_SD v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_UXL  :: " Sstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Sstatus_UXL (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii)  ::  2 Word.word))"
+definition get_Sstatus_UXL  :: " Sstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Sstatus_UXL v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 33 :: int)::ii) (( 32 :: int)::ii)  ::  2 Word.word))"
 
 
 definition set_Sstatus_UXL  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_UXL r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 33 :: int)::ii) (( 32 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_UXL  :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_UXL (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_UXL  :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_UXL v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 33 :: int)::ii) (( 32 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_MXR  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_MXR (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_MXR  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_MXR v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 19 :: int)::ii) (( 19 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_MXR  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_MXR r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_MXR  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_MXR (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_MXR  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_MXR v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_SUM  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_SUM (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_SUM  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_SUM v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 18 :: int)::ii) (( 18 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_SUM  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_SUM r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_SUM  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_SUM (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_SUM  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_SUM v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_XS  :: " Sstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Sstatus_XS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii)  ::  2 Word.word))"
+definition get_Sstatus_XS  :: " Sstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Sstatus_XS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 16 :: int)::ii) (( 15 :: int)::ii)  ::  2 Word.word))"
 
 
 definition set_Sstatus_XS  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_XS r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 16 :: int)::ii) (( 15 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_XS  :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_XS (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_XS  :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_XS v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 16 :: int)::ii) (( 15 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_FS  :: " Sstatus \<Rightarrow>(2)Word.word "  where 
-     " get_Sstatus_FS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word))"
+definition get_Sstatus_FS  :: " Sstatus \<Rightarrow>(2)Word.word "  where 
+     " get_Sstatus_FS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word))"
 
 
 definition set_Sstatus_FS  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_FS r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 14 :: int)::ii) (( 13 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_FS  :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_FS (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_FS  :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_FS v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 14 :: int)::ii) (( 13 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_SPP  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_SPP (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_SPP  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_SPP v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_SPP  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_SPP r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_SPP  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_SPP (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_SPP  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_SPP v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_SPIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_SPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_SPIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_SPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_SPIE  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_SPIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_SPIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_SPIE (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_SPIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_SPIE v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_UPIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_UPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_UPIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_UPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_UPIE  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_UPIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_UPIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_UPIE (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_UPIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_UPIE v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_SIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_SIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_SIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_SIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_SIE  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_SIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_SIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_SIE (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_SIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_SIE v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sstatus_UIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
-     " get_Sstatus_UIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Sstatus_UIE  :: " Sstatus \<Rightarrow>(1)Word.word "  where 
+     " get_Sstatus_UIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sstatus_UIE  :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sstatus_UIE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . 
-   (let r = ((get_Sstatus w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sstatus r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sstatus_Sstatus_chunk_0 :=
+         ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sstatus_UIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
-     " update_Sstatus_UIE (Mk_Sstatus (v)) x = (
-   Mk_Sstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sstatus_UIE  :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus "  where 
+     " update_Sstatus_UIE v x = (
+   (v (|
+     Sstatus_Sstatus_chunk_0 :=
+       ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val lower_mstatus : Mstatus -> Sstatus*)
@@ -3446,7 +5483,6 @@ definition lower_mstatus  :: " Mstatus \<Rightarrow> Sstatus "  where
 definition lift_sstatus  :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow> Mstatus "  where 
      " lift_sstatus (m :: Mstatus) (s :: Sstatus) = (
    (let m = (update_Mstatus_SD m ((get_Sstatus_SD s  ::  1 Word.word))) in
-   (let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s  ::  2 Word.word))) in
    (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s  ::  1 Word.word))) in
    (let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s  ::  1 Word.word))) in
    (let m = (update_Mstatus_XS m ((get_Sstatus_XS s  ::  2 Word.word))) in
@@ -3455,184 +5491,285 @@ definition lift_sstatus  :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow> Mstatu
    (let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s  ::  1 Word.word))) in
    (let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s  ::  1 Word.word))) in
    (let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s  ::  1 Word.word))) in
-   update_Mstatus_UIE m ((get_Sstatus_UIE s  ::  1 Word.word)))))))))))))"
+   update_Mstatus_UIE m ((get_Sstatus_UIE s  ::  1 Word.word))))))))))))"
 
 
 (*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*)
 
 definition legalize_sstatus  :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus "  where 
-     " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m (Mk_Sstatus v))"
+     " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m ((Mk_Sstatus v)))"
+
 
+(*val Mk_Sedeleg : mword ty64 -> Sedeleg*)
 
-(*val _get_Sedeleg : Sedeleg -> mword ty64*)
+definition Mk_Sedeleg  :: "(64)Word.word \<Rightarrow> Sedeleg "  where 
+     " Mk_Sedeleg v = (
+   (| Sedeleg_Sedeleg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-fun get_Sedeleg  :: " Sedeleg \<Rightarrow>(64)Word.word "  where 
-     " get_Sedeleg (Mk_Sedeleg (v)) = ( v )"
 
+(*val _get_Sedeleg_bits : Sedeleg -> mword ty64*)
 
-(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*)
+definition get_Sedeleg_bits  :: " Sedeleg \<Rightarrow>(64)Word.word "  where 
+     " get_Sedeleg_bits v = ( (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-definition set_Sedeleg  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Sedeleg r_ref v = (
+
+(*val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*)
+
+definition set_Sedeleg_bits  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Sedeleg_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Sedeleg v) in
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-fun get_Sedeleg_UEnvCall  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_UEnvCall (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+(*val _update_Sedeleg_bits : Sedeleg -> mword ty64 -> Sedeleg*)
+
+definition update_Sedeleg_bits  :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_bits v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
+definition get_Sedeleg_UEnvCall  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_UEnvCall v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_UEnvCall  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_UEnvCall r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_UEnvCall  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_UEnvCall (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_UEnvCall  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_UEnvCall v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_SAMO_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) = (
-   (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_SAMO_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_SAMO_Access_Fault v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_SAMO_Access_Fault  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_SAMO_Access_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_SAMO_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_SAMO_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_SAMO_Access_Fault v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_SAMO_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_SAMO_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_SAMO_Addr_Align v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_SAMO_Addr_Align  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_SAMO_Addr_Align r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_SAMO_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_SAMO_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_SAMO_Addr_Align v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_Load_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) = (
-   (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_Load_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_Load_Access_Fault v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_Load_Access_Fault  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_Load_Access_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_Load_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_Load_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_Load_Access_Fault v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_Load_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_Load_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_Load_Addr_Align v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_Load_Addr_Align  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_Load_Addr_Align r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_Load_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_Load_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_Load_Addr_Align v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_Breakpoint  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_Breakpoint (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_Breakpoint  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_Breakpoint v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_Breakpoint  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_Breakpoint r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_Breakpoint  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_Breakpoint (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_Breakpoint  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_Breakpoint v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_Illegal_Instr  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_Illegal_Instr  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_Illegal_Instr v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_Illegal_Instr  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_Illegal_Instr r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_Illegal_Instr  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_Illegal_Instr  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_Illegal_Instr v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_Fetch_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) = (
-   (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_Fetch_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_Fetch_Access_Fault v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_Fetch_Access_Fault  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_Fetch_Access_Fault r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_Fetch_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_Fetch_Access_Fault  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_Fetch_Access_Fault v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sedeleg_Fetch_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
-     " get_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Sedeleg_Fetch_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word "  where 
+     " get_Sedeleg_Fetch_Addr_Align v = (
+   (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sedeleg_Fetch_Addr_Align  :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sedeleg_Fetch_Addr_Align r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . 
-   (let r = ((get_Sedeleg w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sedeleg r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sedeleg_Sedeleg_chunk_0 :=
+         ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sedeleg_Fetch_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
-     " update_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) x = (
-   Mk_Sedeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sedeleg_Fetch_Addr_Align  :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg "  where 
+     " update_Sedeleg_Fetch_Addr_Align v x = (
+   (v (|
+     Sedeleg_Sedeleg_chunk_0 :=
+       ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*)
@@ -3642,121 +5779,199 @@ definition legalize_sedeleg  :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarro
    Mk_Sedeleg ((EXTZ (( 64 :: int)::ii) ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii)  ::  9 Word.word))  ::  64 Word.word)))"
 
 
-(*val _get_Sinterrupts : Sinterrupts -> mword ty64*)
+(*val Mk_Sinterrupts : mword ty64 -> Sinterrupts*)
+
+definition Mk_Sinterrupts  :: "(64)Word.word \<Rightarrow> Sinterrupts "  where 
+     " Mk_Sinterrupts v = (
+   (| Sinterrupts_Sinterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-fun get_Sinterrupts  :: " Sinterrupts \<Rightarrow>(64)Word.word "  where 
-     " get_Sinterrupts (Mk_Sinterrupts (v)) = ( v )"
 
+(*val _get_Sinterrupts_bits : Sinterrupts -> mword ty64*)
 
-(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*)
+definition get_Sinterrupts_bits  :: " Sinterrupts \<Rightarrow>(64)Word.word "  where 
+     " get_Sinterrupts_bits v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-definition set_Sinterrupts  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Sinterrupts r_ref v = (
+
+(*val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*)
+
+definition set_Sinterrupts_bits  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Sinterrupts_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Sinterrupts v) in
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-fun get_Sinterrupts_SEI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Sinterrupts_SEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
+(*val _update_Sinterrupts_bits : Sinterrupts -> mword ty64 -> Sinterrupts*)
+
+definition update_Sinterrupts_bits  :: " Sinterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_bits v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
+definition get_Sinterrupts_SEI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Sinterrupts_SEI v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sinterrupts_SEI  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sinterrupts_SEI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . 
-   (let r = ((get_Sinterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sinterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sinterrupts_SEI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
-     " update_Sinterrupts_SEI (Mk_Sinterrupts (v)) x = (
-   Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sinterrupts_SEI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_SEI v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sinterrupts_UEI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Sinterrupts_UEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
+definition get_Sinterrupts_UEI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Sinterrupts_UEI v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sinterrupts_UEI  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sinterrupts_UEI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . 
-   (let r = ((get_Sinterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sinterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sinterrupts_UEI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
-     " update_Sinterrupts_UEI (Mk_Sinterrupts (v)) x = (
-   Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sinterrupts_UEI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_UEI v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sinterrupts_STI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Sinterrupts_STI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+definition get_Sinterrupts_STI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Sinterrupts_STI v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sinterrupts_STI  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sinterrupts_STI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . 
-   (let r = ((get_Sinterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sinterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sinterrupts_STI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
-     " update_Sinterrupts_STI (Mk_Sinterrupts (v)) x = (
-   Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sinterrupts_STI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_STI v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sinterrupts_UTI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Sinterrupts_UTI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+definition get_Sinterrupts_UTI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Sinterrupts_UTI v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sinterrupts_UTI  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sinterrupts_UTI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . 
-   (let r = ((get_Sinterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sinterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sinterrupts_UTI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
-     " update_Sinterrupts_UTI (Mk_Sinterrupts (v)) x = (
-   Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sinterrupts_UTI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_UTI v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sinterrupts_SSI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Sinterrupts_SSI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+definition get_Sinterrupts_SSI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Sinterrupts_SSI v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sinterrupts_SSI  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sinterrupts_SSI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . 
-   (let r = ((get_Sinterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sinterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sinterrupts_SSI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
-     " update_Sinterrupts_SSI (Mk_Sinterrupts (v)) x = (
-   Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sinterrupts_SSI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_SSI v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_Sinterrupts_USI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
-     " get_Sinterrupts_USI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+definition get_Sinterrupts_USI  :: " Sinterrupts \<Rightarrow>(1)Word.word "  where 
+     " get_Sinterrupts_USI v = (
+   (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
 
 definition set_Sinterrupts_USI  :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Sinterrupts_USI r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . 
-   (let r = ((get_Sinterrupts w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Sinterrupts r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Sinterrupts_Sinterrupts_chunk_0 :=
+         ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Sinterrupts_USI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
-     " update_Sinterrupts_USI (Mk_Sinterrupts (v)) x = (
-   Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Sinterrupts_USI  :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts "  where 
+     " update_Sinterrupts_USI v x = (
+   (v (|
+     Sinterrupts_Sinterrupts_chunk_0 :=
+       ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*)
@@ -3843,7 +6058,7 @@ definition lift_sip  :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Si
 
 definition legalize_sip  :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts "  where 
      " legalize_sip (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = (
-   lift_sip m d (Mk_Sinterrupts v))"
+   lift_sip m d ((Mk_Sinterrupts v)))"
 
 
 (*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*)
@@ -3880,85 +6095,131 @@ definition lift_sie  :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Si
 
 definition legalize_sie  :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts "  where 
      " legalize_sie (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = (
-   lift_sie m d (Mk_Sinterrupts v))"
+   lift_sie m d ((Mk_Sinterrupts v)))"
+
+
+(*val Mk_Satp64 : mword ty64 -> Satp64*)
+
+definition Mk_Satp64  :: "(64)Word.word \<Rightarrow> Satp64 "  where 
+     " Mk_Satp64 v = ( (| Satp64_Satp64_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
 
-(*val _get_Satp64 : Satp64 -> mword ty64*)
+(*val _get_Satp64_bits : Satp64 -> mword ty64*)
 
-fun get_Satp64  :: " Satp64 \<Rightarrow>(64)Word.word "  where 
-     " get_Satp64 (Mk_Satp64 (v)) = ( v )"
+definition get_Satp64_bits  :: " Satp64 \<Rightarrow>(64)Word.word "  where 
+     " get_Satp64_bits v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
 
-(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*)
+(*val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*)
 
-definition set_Satp64  :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_Satp64 r_ref v = (
+definition set_Satp64_bits  :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_Satp64_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_Satp64 v) in
+   (let r =
+     ((r (|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-fun get_Satp64_Mode  :: " Satp64 \<Rightarrow>(4)Word.word "  where 
-     " get_Satp64_Mode (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii)  ::  4 Word.word))"
+(*val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64*)
+
+definition update_Satp64_bits  :: " Satp64 \<Rightarrow>(64)Word.word \<Rightarrow> Satp64 "  where 
+     " update_Satp64_bits v x = (
+   (v (|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
+definition get_Satp64_Mode  :: " Satp64 \<Rightarrow>(4)Word.word "  where 
+     " get_Satp64_Mode v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 63 :: int)::ii) (( 60 :: int)::ii)  ::  4 Word.word))"
 
 
 definition set_Satp64_Mode  :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Satp64_Mode r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . 
-   (let r = ((get_Satp64 w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 60 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Satp64 r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   r) (( 63 :: int)::ii) (( 60 :: int)::ii)
+             ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii)  ::  4 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun update_Satp64_Mode  :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 "  where 
-     " update_Satp64_Mode (Mk_Satp64 (v)) x = (
-   Mk_Satp64 ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Satp64_Mode  :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 "  where 
+     " update_Satp64_Mode v x = (
+   (v (|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 63 :: int)::ii) (( 60 :: int)::ii)
+           ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii)  ::  4 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Satp64_Asid : Satp64 -> mword ty16*)
 
-fun get_Satp64_Asid  :: " Satp64 \<Rightarrow>(16)Word.word "  where 
-     " get_Satp64_Asid (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii)  ::  16 Word.word))"
+definition get_Satp64_Asid  :: " Satp64 \<Rightarrow>(16)Word.word "  where 
+     " get_Satp64_Asid v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 59 :: int)::ii) (( 44 :: int)::ii)  ::  16 Word.word))"
 
 
 (*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*)
 
 definition set_Satp64_Asid  :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Satp64_Asid r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . 
-   (let r = ((get_Satp64 w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 44 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Satp64 r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   r) (( 59 :: int)::ii) (( 44 :: int)::ii)
+             ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*)
 
-fun update_Satp64_Asid  :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 "  where 
-     " update_Satp64_Asid (Mk_Satp64 (v)) x = (
-   Mk_Satp64 ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Satp64_Asid  :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 "  where 
+     " update_Satp64_Asid v x = (
+   (v (|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 59 :: int)::ii) (( 44 :: int)::ii)
+           ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val _get_Satp64_PPN : Satp64 -> mword ty44*)
 
-fun get_Satp64_PPN  :: " Satp64 \<Rightarrow>(44)Word.word "  where 
-     " get_Satp64_PPN (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))"
+definition get_Satp64_PPN  :: " Satp64 \<Rightarrow>(44)Word.word "  where 
+     " get_Satp64_PPN v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))"
 
 
 (*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*)
 
 definition set_Satp64_PPN  :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " set_Satp64_PPN r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . 
-   (let r = ((get_Satp64 w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 43 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_Satp64 r)))))"
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       Satp64_Satp64_chunk_0 :=
+         ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   r) (( 43 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
 (*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*)
 
-fun update_Satp64_PPN  :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 "  where 
-     " update_Satp64_PPN (Mk_Satp64 (v)) x = (
-   Mk_Satp64 ((update_subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
+definition update_Satp64_PPN  :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 "  where 
+     " update_Satp64_PPN v x = (
+   (v (|
+     Satp64_Satp64_chunk_0 :=
+       ((update_subrange_vec_dec(Satp64_Satp64_chunk_0   v) (( 43 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))
+          ::  64 Word.word))|)))"
 
 
 (*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*)
@@ -3969,7 +6230,7 @@ definition legalize_satp  :: " Architecture \<Rightarrow>(64)Word.word \<Rightar
    (case  ((satpMode_of_bits a ((get_Satp64_Mode s  ::  4 Word.word)))) of
      None => o1
    | Some (Sv32) => o1
-   | Some (_) => (get_Satp64 s  ::  64 Word.word)
+   | Some (_) => (get_Satp64_bits s  ::  64 Word.word)
    )))"
 
 
@@ -4058,6 +6319,10 @@ definition csr_name  :: "(12)Word.word \<Rightarrow> string "  where
      (''mtval'')
    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
      (''mip'')
+   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''pmpcfg0'')
+   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''pmpaddr0'')
    else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
      (''mcycle'')
    else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
@@ -4071,13 +6336,1881 @@ definition csr_name  :: "(12)Word.word \<Rightarrow> string "  where
    else (''UNKNOWN'')))"
 
 
-(*val csrAccess : mword ty12 -> mword ty2*)
-
-definition csrAccess  :: "(12)Word.word \<Rightarrow>(2)Word.word "  where 
-     " csrAccess csr = ( (subrange_vec_dec csr (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word))"
-
-
-(*val csrPriv : mword ty12 -> mword ty2*)
+(*val csr_name_map_forwards : mword ty12 -> string*)
+
+definition csr_name_map_forwards  :: "(12)Word.word \<Rightarrow> string "  where 
+     " csr_name_map_forwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''ustatus'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''uie'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     (''utvec'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''uscratch'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''uepc'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''ucause'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''utval'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''uip'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''fflags'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''frm'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''fcsr'')
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''cycle'')
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''time'')
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''instret'')
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''cycleh'')
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''timeh'')
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''instreth'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''sstatus'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''sedeleg'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''sideleg'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''sie'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     (''stvec'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+     (''scounteren'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''sscratch'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''sepc'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''scause'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''stval'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''sip'')
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''satp'')
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''mvendorid'')
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''marchid'')
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''mimpid'')
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''mhartid'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''mstatus'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''misa'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''medeleg'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''mideleg'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''mie'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     (''mtvec'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+     (''mcounteren'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''mscratch'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''mepc'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''mcause'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''mtval'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''mip'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''pmpcfg0'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''pmpcfg1'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''pmpcfg2'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''pmpcfg3'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''pmpaddr0'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''pmpaddr1'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''pmpaddr2'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     (''pmpaddr3'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     (''pmpaddr4'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     (''pmpaddr5'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0]  ::  12 Word.word)))) then
+     (''pmpaddr6'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1]  ::  12 Word.word)))) then
+     (''pmpaddr7'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0]  ::  12 Word.word)))) then
+     (''pmpaddr8'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1]  ::  12 Word.word)))) then
+     (''pmpaddr9'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0]  ::  12 Word.word)))) then
+     (''pmpaddr10'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1]  ::  12 Word.word)))) then
+     (''pmpaddr11'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0]  ::  12 Word.word)))) then
+     (''pmpaddr12'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1]  ::  12 Word.word)))) then
+     (''pmpaddr13'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0]  ::  12 Word.word)))) then
+     (''pmpaddr14'')
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1]  ::  12 Word.word)))) then
+     (''pmpaddr15'')
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''mcycle'')
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''minstret'')
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''mcycleh'')
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''minstreth'')
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (''tselect'')
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     (''tdata1'')
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     (''tdata2'')
+   else (''tdata3'')))"
+
+
+(*val csr_name_map_backwards : string -> mword ty12*)
+
+definition csr_name_map_backwards  :: " string \<Rightarrow>(12)Word.word "  where 
+     " csr_name_map_backwards arg0 = ( 
+  if(arg0 = (''ustatus'')) then
+    ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+  else
+    (
+    if(arg0 = (''uie'')) then
+      ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word))
+    else
+      (
+      if(arg0 = (''utvec'')) then
+        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word))
+      else
+        (
+        if(arg0 = (''uscratch'')) then
+          ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+        else
+          (
+          if(arg0 = (''uepc'')) then
+            ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+          else
+            (
+            if(arg0 = (''ucause'')) then
+              ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+            else
+              (
+              if(arg0 = (''utval'')) then
+                ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word))
+              else
+                (
+                if(arg0 = (''uip'')) then
+                  ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word))
+                else
+                  (
+                  if(arg0 = (''fflags'')) then
+                    ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+                  else
+                    (
+                    if(arg0 = (''frm'')) then
+                      ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                    else
+                      (
+                      if(arg0 = (''fcsr'')) then
+                        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word))
+                      else
+                        (
+                        if(arg0 = (''cycle'')) then
+                          ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                        else
+                          (
+                          if(arg0 = (''time'')) then
+                            ((vec_of_bits
+                                [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+                          else
+                            (
+                            if(arg0 = (''instret'')) then
+                              ((vec_of_bits
+                                  [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                            else
+                              (
+                              if(arg0 = (''cycleh'')) then
+                                ((vec_of_bits
+                                    [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                              else
+                                (
+                                if(arg0 = (''timeh'')) then
+                                  ((vec_of_bits
+                                      [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+                                else
+                                  (
+                                  if(arg0 = (''instreth'')) then
+                                    ((vec_of_bits
+                                        [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                  else
+                                    (
+                                    if(arg0 = (''sstatus'')) then
+                                      ((vec_of_bits
+                                          [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                    else
+                                      (
+                                      if(arg0 = (''sedeleg'')) then
+                                        ((vec_of_bits
+                                            [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                      else
+                                        (
+                                        if(arg0 = (''sideleg'')) then
+                                          ((vec_of_bits
+                                              [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word))
+                                        else
+                                          (
+                                          if(arg0 = (''sie'')) then
+                                            ((vec_of_bits
+                                                [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word))
+                                          else
+                                            (
+                                            if(arg0 = (''stvec'')) then
+                                              ((vec_of_bits
+                                                  [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word))
+                                            else
+                                              (
+                                              if(arg0 = (''scounteren'')) then
+                                                ((vec_of_bits
+                                                    [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word))
+                                              else
+                                                (
+                                                if(arg0 = (''sscratch'')) then
+                                                  ((vec_of_bits
+                                                      [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                else
+                                                  (
+                                                  if(arg0 = (''sepc'')) then
+                                                    ((vec_of_bits
+                                                        [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+                                                  else
+                                                    (
+                                                    if(arg0 = (''scause'')) then
+                                                      ((vec_of_bits
+                                                          [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                    else
+                                                      (
+                                                      if(arg0 = (''stval'')) then
+                                                        ((vec_of_bits
+                                                            [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word))
+                                                      else
+                                                        (
+                                                        if(arg0 = (''sip'')) then
+                                                          ((vec_of_bits
+                                                              [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word))
+                                                        else
+                                                          (
+                                                          if(arg0 =
+                                                               (''satp'')) then
+                                                            ((vec_of_bits
+                                                                [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                          else
+                                                            (
+                                                            if(arg0 =
+                                                                 (''mvendorid'')) then
+                                                              ((vec_of_bits
+                                                                  [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word))
+                                                            else
+                                                              (
+                                                              if(arg0 =
+                                                                   (''marchid'')) then
+                                                                ((vec_of_bits
+                                                                    [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word))
+                                                              else
+                                                                (
+                                                                if(arg0 =
+                                                                    (''mimpid'')) then
+                                                                  ((vec_of_bits
+                                                                    [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word))
+                                                                else
+                                                                  (
+                                                                  if(
+                                                                    arg0 =
+                                                                    (''mhartid'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word))
+                                                                  else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mstatus'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''misa'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''medeleg'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mideleg'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mie'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mtvec'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcounteren'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mscratch'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mepc'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcause'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mtval'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mip'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg0'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg1'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg2'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg3'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr0'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr1'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr2'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr3'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr4'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr5'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr6'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr7'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr8'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr9'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr10'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr11'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr12'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr13'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr14'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr15'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcycle'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''minstret'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcycleh'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''minstreth'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tselect'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tdata1'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tdata2'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word))
+                                                                    else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tdata3'')) then
+                                                                    (
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word))
+                                                                    else
+                                                                    undefined)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) )"
+
+
+(*val csr_name_map_forwards_matches : mword ty12 -> bool*)
+
+definition csr_name_map_forwards_matches  :: "(12)Word.word \<Rightarrow> bool "  where 
+     " csr_name_map_forwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+     True
+   else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+     True
+   else False))"
+
+
+(*val csr_name_map_backwards_matches : string -> bool*)
+
+definition csr_name_map_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " csr_name_map_backwards_matches arg0 = ( 
+  if(arg0 = (''ustatus'')) then True else
+    (
+    if(arg0 = (''uie'')) then True else
+      (
+      if(arg0 = (''utvec'')) then True else
+        (
+        if(arg0 = (''uscratch'')) then True else
+          (
+          if(arg0 = (''uepc'')) then True else
+            (
+            if(arg0 = (''ucause'')) then True else
+              (
+              if(arg0 = (''utval'')) then True else
+                (
+                if(arg0 = (''uip'')) then True else
+                  (
+                  if(arg0 = (''fflags'')) then True else
+                    (
+                    if(arg0 = (''frm'')) then True else
+                      (
+                      if(arg0 = (''fcsr'')) then True else
+                        (
+                        if(arg0 = (''cycle'')) then True else
+                          (
+                          if(arg0 = (''time'')) then True else
+                            (
+                            if(arg0 = (''instret'')) then True else
+                              (
+                              if(arg0 = (''cycleh'')) then True else
+                                (
+                                if(arg0 = (''timeh'')) then True else
+                                  (
+                                  if(arg0 = (''instreth'')) then True else
+                                    (
+                                    if(arg0 = (''sstatus'')) then True else
+                                      (
+                                      if(arg0 = (''sedeleg'')) then True else
+                                        (
+                                        if(arg0 = (''sideleg'')) then 
+                                        True else
+                                          (
+                                          if(arg0 = (''sie'')) then True else
+                                            (
+                                            if(arg0 = (''stvec'')) then 
+                                            True else
+                                              (
+                                              if(arg0 = (''scounteren'')) then
+                                                True else
+                                                (
+                                                if(arg0 = (''sscratch'')) then
+                                                  True else
+                                                  (
+                                                  if(arg0 = (''sepc'')) then
+                                                    True else
+                                                    (
+                                                    if(arg0 = (''scause'')) then
+                                                      True else
+                                                      (
+                                                      if(arg0 = (''stval'')) then
+                                                        True else
+                                                        (
+                                                        if(arg0 = (''sip'')) then
+                                                          True else
+                                                          (
+                                                          if(arg0 =
+                                                               (''satp'')) then
+                                                            True else
+                                                            (
+                                                            if(arg0 =
+                                                                 (''mvendorid'')) then
+                                                              True else
+                                                              (
+                                                              if(arg0 =
+                                                                   (''marchid'')) then
+                                                                True else
+                                                                (
+                                                                if(arg0 =
+                                                                    (''mimpid'')) then
+                                                                  True else
+                                                                  (
+                                                                  if(
+                                                                    arg0 =
+                                                                    (''mhartid'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mstatus'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''misa'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''medeleg'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mideleg'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mie'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mtvec'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcounteren'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mscratch'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mepc'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcause'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mtval'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mip'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg0'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg1'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg2'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpcfg3'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr0'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr1'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr2'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr3'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr4'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr5'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr6'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr7'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr8'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr9'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr10'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr11'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr12'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr13'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr14'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''pmpaddr15'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcycle'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''minstret'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''mcycleh'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''minstreth'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tselect'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tdata1'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tdata2'')) then
+                                                                    True else
+                                                                    (
+                                                                    if
+                                                                    (
+                                                                    arg0 =
+                                                                    (''tdata3'')) then
+                                                                    True else
+                                                                    False)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) )"
+
+
+(*val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))*)
+
+definition csr_name_map_matches_prefix  :: " string \<Rightarrow>((12)Word.word*int)option "  where 
+     " csr_name_map_matches_prefix arg0 = (
+   (let stringappend_17160 = arg0 in
+   if (((((string_startswith stringappend_17160 (''ustatus''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''ustatus''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''ustatus''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''uie''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''uie''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''uie''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''utvec''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''utvec''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''utvec''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''uscratch''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''uscratch''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''uscratch''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''uepc''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''uepc''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''uepc''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''ucause''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''ucause''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''ucause''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''utval''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''utval''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''utval''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''uip''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''uip''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''uip''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''fflags''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''fflags''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''fflags''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''frm''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''frm''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''frm''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''fcsr''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''fcsr''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''fcsr''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''cycle''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''cycle''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''cycle''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''time''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''time''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''time''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''instret''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''instret''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''instret''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''cycleh''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''cycleh''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''cycleh''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''timeh''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''timeh''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''timeh''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''instreth''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''instreth''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''instreth''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sstatus''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sstatus''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sstatus''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sedeleg''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sedeleg''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sedeleg''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sideleg''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sideleg''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sideleg''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sie''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sie''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sie''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''stvec''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''stvec''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''stvec''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''scounteren''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''scounteren''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''scounteren''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sscratch''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sscratch''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sscratch''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sepc''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sepc''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sepc''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''scause''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''scause''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''scause''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''stval''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''stval''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''stval''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''sip''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''sip''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''sip''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''satp''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''satp''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''satp''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mvendorid''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mvendorid''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mvendorid''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''marchid''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''marchid''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''marchid''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mimpid''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mimpid''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mimpid''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mhartid''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mhartid''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mhartid''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mstatus''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mstatus''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mstatus''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''misa''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''misa''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''misa''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''medeleg''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''medeleg''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''medeleg''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mideleg''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mideleg''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mideleg''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mie''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mie''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mie''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mtvec''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mtvec''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mtvec''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mcounteren''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mcounteren''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mcounteren''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mscratch''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mscratch''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mscratch''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mepc''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mepc''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mepc''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mcause''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mcause''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mcause''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mtval''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mtval''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mtval''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mip''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mip''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mip''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpcfg0''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg0''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg0''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpcfg1''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg1''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg1''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpcfg2''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg2''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg2''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpcfg3''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg3''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpcfg3''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr0''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr0''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr0''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr1''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr1''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr1''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr2''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr2''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr2''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr3''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr3''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr3''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr4''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr4''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr4''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr5''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr5''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr5''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr6''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr6''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr6''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr7''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr7''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr7''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr8''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr8''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr8''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr9''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr9''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr9''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr10''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr10''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr10''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr11''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr11''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr11''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr12''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr12''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr12''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr13''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr13''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr13''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr14''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr14''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr14''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''pmpaddr15''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr15''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''pmpaddr15''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mcycle''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mcycle''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mcycle''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''minstret''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''minstret''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''minstret''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''mcycleh''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''mcycleh''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''mcycleh''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''minstreth''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''minstreth''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''minstreth''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''tselect''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''tselect''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''tselect''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''tdata1''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''tdata1''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''tdata1''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''tdata2''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''tdata2''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''tdata2''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17160 (''tdata3''))) \<and> (
+  (case  ((string_drop stringappend_17160 ((string_length (''tdata3''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17160 ((string_length (''tdata3''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1]  ::  12 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val csrAccess : mword ty12 -> mword ty2*)
+
+definition csrAccess  :: "(12)Word.word \<Rightarrow>(2)Word.word "  where 
+     " csrAccess csr = ( (subrange_vec_dec csr (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word))"
+
+
+(*val csrPriv : mword ty12 -> mword ty2*)
 
 definition csrPriv  :: "(12)Word.word \<Rightarrow>(2)Word.word "  where 
      " csrPriv csr = ( (subrange_vec_dec csr (( 9 :: int)::ii) (( 8 :: int)::ii)  ::  2 Word.word))"
@@ -4120,6 +8253,10 @@ definition is_CSR_defined  :: "(12)Word.word \<Rightarrow> Privilege \<Rightarro
      (((privLevel_to_bits p  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word)))
    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
      (((privLevel_to_bits p  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word)))
+   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     (((privLevel_to_bits p  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word)))
+   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word)))) then
+     False
    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
      ((((((privLevel_to_bits p  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word))))) \<or> (((((privLevel_to_bits p  ::  2 Word.word)) = ((privLevel_to_bits Supervisor  ::  2 Word.word))))))
    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
@@ -4170,6 +8307,58 @@ definition check_TVM_SATP  :: "(12)Word.word \<Rightarrow> Privilege \<Rightarro
    return ((\<not> w__2))))"
 
 
+(*val check_Counteren : mword ty12 -> Privilege -> M bool*)
+
+definition check_Counteren  :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " check_Counteren (csr :: csreg) (p :: Privilege) = (
+   (case  (csr, p) of
+     (b__0, Supervisor) =>
+      if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+        read_reg mcounteren_ref \<bind> (\<lambda> (w__0 :: Counteren) . 
+        return (((((get_Counteren_CY w__0  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+      else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+        read_reg mcounteren_ref \<bind> (\<lambda> (w__1 :: Counteren) . 
+        return (((((get_Counteren_TM w__1  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+      else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+        read_reg mcounteren_ref \<bind> (\<lambda> (w__2 :: Counteren) . 
+        return (((((get_Counteren_IR w__2  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+      else
+        return ((case  (b__0, Supervisor) of
+          (g__31, g__32) =>
+           if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)
+                      csr)) \<and> ((zopz0zIzJ_u csr
+                      (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1]  ::  12 Word.word)))))) then
+             False
+           else True
+        ))
+   | (b__3, User) =>
+      if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+        read_reg scounteren_ref \<bind> (\<lambda> (w__6 :: Counteren) . 
+        return (((((get_Counteren_CY w__6  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+      else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+        read_reg scounteren_ref \<bind> (\<lambda> (w__7 :: Counteren) . 
+        return (((((get_Counteren_TM w__7  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+      else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+        read_reg scounteren_ref \<bind> (\<lambda> (w__8 :: Counteren) . 
+        return (((((get_Counteren_IR w__8  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+      else
+        return ((case  (b__3, User) of
+          (g__31, g__32) =>
+           if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)
+                      csr)) \<and> ((zopz0zIzJ_u csr
+                      (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1]  ::  12 Word.word)))))) then
+             False
+           else True
+        ))
+   | (g__31, g__32) =>
+      return (if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)
+                         csr)) \<and> ((zopz0zIzJ_u csr
+                         (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1]  ::  12 Word.word)))))) then
+                False
+              else True)
+   ))"
+
+
 (*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*)
 
 definition check_CSR  :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
@@ -4177,7 +8366,7 @@ definition check_CSR  :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bo
    and_boolM (return ((is_CSR_defined csr p)))
      (and_boolM
         (return ((check_CSR_access ((csrAccess csr  ::  2 Word.word)) ((csrPriv csr  ::  2 Word.word)) p
-                    isWrite))) ((check_TVM_SATP csr p))))"
+                    isWrite))) (and_boolM ((check_TVM_SATP csr p)) ((check_Counteren csr p)))))"
 
 
 (*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*)
@@ -4186,9 +8375,9 @@ definition exception_delegatee  :: " ExceptionType \<Rightarrow> Privilege \<Rig
      " exception_delegatee (e :: ExceptionType) (p :: Privilege) = (
    (let idx = (num_of_ExceptionType e) in
    read_reg medeleg_ref \<bind> (\<lambda> (w__0 :: Medeleg) . 
-   (let super = (access_vec_dec ((get_Medeleg w__0  ::  64 Word.word)) idx) in
+   (let super = (access_vec_dec ((get_Medeleg_bits w__0  ::  64 Word.word)) idx) in
    read_reg sedeleg_ref \<bind> (\<lambda> (w__1 :: Sedeleg) . 
-   (let user = (access_vec_dec ((get_Sedeleg w__1  ::  64 Word.word)) idx) in
+   (let user = (access_vec_dec ((get_Sedeleg_bits w__1  ::  64 Word.word)) idx) in
    and_boolM
      (read_reg misa_ref \<bind> (\<lambda> (w__2 :: Misa) . 
       return (((((get_Misa_S w__2  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))
@@ -4234,51 +8423,98 @@ definition findPendingInterrupt  :: "(64)Word.word \<Rightarrow>(InterruptType)o
    else None))"
 
 
-(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*)
+(*val curInterrupt : Privilege -> Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*)
 
-definition curInterrupt  :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad "  where 
-     " curInterrupt (pend :: Minterrupts) (enbl :: Minterrupts) (delg :: Minterrupts) = (
+definition curInterrupt  :: " Privilege \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad "  where 
+     " curInterrupt (priv :: Privilege) (pend :: Minterrupts) (enbl :: Minterrupts) (delg :: Minterrupts) = (
    (let (en_mip :: xlenbits) =
-     ((and_vec ((get_Minterrupts pend  ::  64 Word.word)) ((get_Minterrupts enbl  ::  64 Word.word))
+     ((and_vec ((get_Minterrupts_bits pend  ::  64 Word.word))
+        ((get_Minterrupts_bits enbl  ::  64 Word.word))
        ::  64 Word.word)) in
    if (((en_mip = ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))))) then
      return None
    else
+     or_boolM
+       (return (((((privLevel_to_bits priv  ::  2 Word.word)) \<noteq> ((privLevel_to_bits Machine  ::  2 Word.word))))))
+       (and_boolM
+          (return (((((privLevel_to_bits priv  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word))))))
+          (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
+           return (((((get_Mstatus_MIE w__0  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))) \<bind> (\<lambda> eff_mie . 
+     or_boolM
+       (return (((((privLevel_to_bits priv  ::  2 Word.word)) = ((privLevel_to_bits User  ::  2 Word.word))))))
+       (and_boolM
+          (return (((((privLevel_to_bits priv  ::  2 Word.word)) = ((privLevel_to_bits Supervisor  ::  2 Word.word))))))
+          (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . 
+           return (((((get_Mstatus_SIE w__2  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))) \<bind> (\<lambda> eff_sie . 
      (let eff_mip =
-       ((and_vec en_mip ((not_vec ((get_Minterrupts delg  ::  64 Word.word))  ::  64 Word.word))
+       ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg  ::  64 Word.word))  ::  64 Word.word))
          ::  64 Word.word)) in
-     (let eff_sip = ((and_vec en_mip ((get_Minterrupts delg  ::  64 Word.word))  ::  64 Word.word)) in
-     and_boolM
-       (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
-        return (((((get_Mstatus_MIE w__0  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))
-       (return (((eff_mip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)))))) \<bind> (\<lambda> (w__1 ::
-       bool) . 
-     if w__1 then
-       return ((case  ((findPendingInterrupt eff_mip)) of
+     (let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg  ::  64 Word.word))  ::  64 Word.word)) in
+     if (((eff_mie \<and> (((eff_mip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)))))))) then
+       (case  ((findPendingInterrupt eff_mip)) of
          Some (i) =>
           (let r = (i, Machine) in
-          Some r)
-       | None => None
-       ))
+          return (Some r))
+       | None =>
+          internal_error
+            (((op@) (''non-zero eff_mip='')
+                (((op@) ((string_of_bits eff_mip)) ('', but nothing pending'')))))
+       )
+     else if (((eff_sie \<and> (((eff_sip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))))))))
+     then
+       (case  ((findPendingInterrupt eff_sip)) of
+         Some (i) =>
+          (let r = (i, Supervisor) in
+          return (Some r))
+       | None =>
+          internal_error
+            (((op@) (''non-zero eff_sip='')
+                (((op@) ((string_of_bits eff_sip)) ('', but nothing pending'')))))
+       )
      else
-       and_boolM
-         (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . 
-          return (((((get_Mstatus_SIE w__2  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))
-         (and_boolM
-            (return (((eff_sip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))))))
-            (or_boolM
-               (read_reg cur_privilege_ref \<bind> (\<lambda> (w__3 :: Privilege) . 
-                return (((((privLevel_to_bits w__3  ::  2 Word.word)) = ((privLevel_to_bits Supervisor  ::  2 Word.word)))))))
-               (read_reg cur_privilege_ref \<bind> (\<lambda> (w__4 :: Privilege) . 
-                return (((((privLevel_to_bits w__4  ::  2 Word.word)) = ((privLevel_to_bits User  ::  2 Word.word))))))))) \<bind> (\<lambda> (w__7 :: bool) . 
-       return (if w__7 then
-                 (case  ((findPendingInterrupt eff_sip)) of
-                   Some (i) =>
-                    (let r = (i, Supervisor) in
-                    Some r)
-                 | None => None
-                 )
-               else None)))))))"
+       (let p =
+         (if (((((get_Minterrupts_MTI pend  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))
+         then
+           (''1'')
+         else (''0'')) in
+       (let e =
+         (if (((((get_Minterrupts_MTI enbl  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))
+         then
+           (''1'')
+         else (''0'')) in
+       (let d =
+         (if (((((get_Minterrupts_MTI delg  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))
+         then
+           (''1'')
+         else (''0'')) in
+       (let (_ :: unit) =
+         (print_endline
+           (((op@) ('' MTI: pend='')
+               (((op@) p
+                   (((op@) ('' enbl='') (((op@) e (((op@) ('' delg='') d))))))))))) in
+       (let eff_mip =
+         ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg  ::  64 Word.word))  ::  64 Word.word))
+           ::  64 Word.word)) in
+       (let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg  ::  64 Word.word))  ::  64 Word.word)) in
+       read_reg mstatus_ref \<bind> (\<lambda> (w__8 :: Mstatus) . 
+       read_reg mstatus_ref \<bind> (\<lambda> (w__9 :: Mstatus) . 
+       read_reg mstatus_ref \<bind> (\<lambda> (w__10 :: Mstatus) . 
+       (let (_ :: unit) =
+         (print_endline
+           (((op@) (''mstatus='')
+               (((op@) ((string_of_bits ((get_Mstatus_bits w__8  ::  64 Word.word))))
+                   (((op@) ('' mie,sie='')
+                       (((op@) ((string_of_bits ((get_Mstatus_MIE w__9  ::  1 Word.word))))
+                           (((op@) ('','')
+                               (((op@)
+                                   ((string_of_bits ((get_Mstatus_SIE w__10  ::  1 Word.word))))
+                                   (((op@) ('' en_mip='')
+                                       (((op@) ((string_of_bits en_mip))
+                                           (((op@) ('' eff_mip='')
+                                               (((op@) ((string_of_bits eff_mip))
+                                                   (((op@) ('' eff_sip='')
+                                                       ((string_of_bits eff_sip))))))))))))))))))))))))) in
+       return None))))))))))))))))"
 
 
 (*val tval : maybe (mword ty64) -> mword ty64*)
@@ -4294,14 +8530,14 @@ definition handle_trap  :: " Privilege \<Rightarrow> bool \<Rightarrow>(4)Word.w
      " handle_trap (del_priv :: Privilege) (intr :: bool) (c :: exc_code) (pc :: xlenbits) (info ::
    xlenbits option) = (
    (let (_ :: unit) =
-     (prerr_endline
+     (print_endline
        (((op@) (''handling '')
            (((op@) (if intr then (''int#'') else (''exc#''))
-               (((op@) ((string_of_vec c))
+               (((op@) ((string_of_bits c))
                    (((op@) ('' at priv '')
                        (((op@) ((privLevel_to_str del_priv))
                            (((op@) ('' with tval '')
-                               ((string_of_vec ((tval info  ::  64 Word.word))))))))))))))))) in
+                               ((string_of_bits ((tval info  ::  64 Word.word))))))))))))))))) in
    (case  del_priv of
      Machine =>
       ((set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr  ::  1 Word.word)) \<then>
@@ -4314,34 +8550,53 @@ definition handle_trap  :: " Privilege \<Rightarrow> bool \<Rightarrow>(4)Word.w
       write_reg mtval_ref ((tval info  ::  64 Word.word))) \<then>
       write_reg mepc_ref pc) \<then>
       write_reg cur_privilege_ref del_priv) \<then>
-      read_reg mtvec_ref) \<bind> (\<lambda> (w__2 :: Mtvec) . 
-      read_reg mcause_ref \<bind> (\<lambda> (w__3 :: Mcause) . 
-      (case  ((tvec_addr w__2 w__3  ::  ( 64 Word.word)option)) of
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . 
+      read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) . 
+      (let (_ :: unit) =
+        (print_endline
+          (((op@) (''CSR mstatus <- '')
+              (((op@) ((string_of_bits ((get_Mstatus_bits w__2  ::  64 Word.word))))
+                  (((op@) ('' (input: '')
+                      (((op@) ((string_of_bits ((get_Mstatus_bits w__3  ::  64 Word.word)))) ('')'')))))))))) in
+      (let (_ :: unit) = (cancel_reservation () ) in
+      read_reg mtvec_ref \<bind> (\<lambda> (w__4 :: Mtvec) . 
+      read_reg mcause_ref \<bind> (\<lambda> (w__5 :: Mcause) . 
+      (case  ((tvec_addr w__4 w__5  ::  ( 64 Word.word)option)) of
         Some (epc) => return epc
       | None => (internal_error (''Invalid mtvec mode'')  :: ( 64 Word.word) M)
-      )))))
+      )))))))))
    | Supervisor =>
       ((set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr  ::  1 Word.word)) \<then>
       set_Mcause_Cause scause_ref ((EXTZ (( 63 :: int)::ii) c  ::  63 Word.word))) \<then>
-      read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) . 
-      ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6  ::  1 Word.word)) \<then>
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__8 :: Mstatus) . 
+      ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__8  ::  1 Word.word)) \<then>
       set_Mstatus_SIE mstatus_ref ((bool_to_bits False  ::  1 Word.word))) \<then>
-      read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) . 
-      (case  w__7 of
+      read_reg cur_privilege_ref) \<bind> (\<lambda> (w__9 :: Privilege) . 
+      (case  w__9 of
         User => return ((bool_to_bits False  ::  1 Word.word))
       | Supervisor => return ((bool_to_bits True  ::  1 Word.word))
       | Machine => (internal_error (''invalid privilege for s-mode trap'')  :: ( 1 Word.word) M)
-      ) \<bind> (\<lambda> (w__9 ::  1 Word.word) . 
-      ((((set_Mstatus_SPP mstatus_ref w__9 \<then>
+      ) \<bind> (\<lambda> (w__11 ::  1 Word.word) . 
+      ((((set_Mstatus_SPP mstatus_ref w__11 \<then>
       write_reg stval_ref ((tval info  ::  64 Word.word))) \<then>
       write_reg sepc_ref pc) \<then>
       write_reg cur_privilege_ref del_priv) \<then>
-      read_reg stvec_ref) \<bind> (\<lambda> (w__10 :: Mtvec) . 
-      read_reg scause_ref \<bind> (\<lambda> (w__11 :: Mcause) . 
-      (case  ((tvec_addr w__10 w__11  ::  ( 64 Word.word)option)) of
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__12 :: Mstatus) . 
+      read_reg mstatus_ref \<bind> (\<lambda> (w__13 :: Mstatus) . 
+      (let (_ :: unit) =
+        (print_endline
+          (((op@) (''CSR mstatus <- '')
+              (((op@) ((string_of_bits ((get_Mstatus_bits w__12  ::  64 Word.word))))
+                  (((op@) ('' (input: '')
+                      (((op@) ((string_of_bits ((get_Mstatus_bits w__13  ::  64 Word.word))))
+                          ('')'')))))))))) in
+      (let (_ :: unit) = (cancel_reservation () ) in
+      read_reg stvec_ref \<bind> (\<lambda> (w__14 :: Mtvec) . 
+      read_reg scause_ref \<bind> (\<lambda> (w__15 :: Mcause) . 
+      (case  ((tvec_addr w__14 w__15  ::  ( 64 Word.word)option)) of
         Some (epc) => return epc
       | None => (internal_error (''Invalid stvec mode'')  :: ( 64 Word.word) M)
-      ))))))
+      ))))))))))
    | User => (internal_error (''the N extension is currently unsupported'')  :: ( 64 Word.word) M)
    )))"
 
@@ -4354,7 +8609,7 @@ definition handle_exception  :: " Privilege \<Rightarrow> ctl_result \<Rightarro
      (_, CTL_TRAP (e)) =>
       exception_delegatee(sync_exception_trap   e) cur_priv \<bind> (\<lambda> del_priv . 
       (let (_ :: unit) =
-        (prerr_endline
+        (print_endline
           (((op@) (''trapping from '')
               (((op@) ((privLevel_to_str cur_priv))
                   (((op@) ('' to '')
@@ -4372,33 +8627,56 @@ definition handle_exception  :: " Privilege \<Rightarrow> ctl_result \<Rightarro
       read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . 
       ((write_reg cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2  ::  2 Word.word)))) \<then>
       set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User  ::  2 Word.word))) \<then>
-      read_reg cur_privilege_ref) \<bind> (\<lambda> (w__3 :: Privilege) . 
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__3 :: Mstatus) . 
+      read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) . 
       (let (_ :: unit) =
-        (prerr_endline
+        (print_endline
+          (((op@) (''CSR mstatus <- '')
+              (((op@) ((string_of_bits ((get_Mstatus_bits w__3  ::  64 Word.word))))
+                  (((op@) ('' (input: '')
+                      (((op@) ((string_of_bits ((get_Mstatus_bits w__4  ::  64 Word.word)))) ('')'')))))))))) in
+      read_reg cur_privilege_ref \<bind> (\<lambda> (w__5 :: Privilege) . 
+      (let (_ :: unit) =
+        (print_endline
           (((op@) (''ret-ing from '')
               (((op@) ((privLevel_to_str prev_priv))
-                  (((op@) ('' to '') ((privLevel_to_str w__3))))))))) in
-      (read_reg mepc_ref  :: ( 64 Word.word) M))))))
+                  (((op@) ('' to '') ((privLevel_to_str w__5))))))))) in
+      (let (_ :: unit) = (cancel_reservation () ) in
+      (read_reg mepc_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 ::  64 Word.word) . 
+      (pc_alignment_mask ()   :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 ::  64 Word.word) . 
+      return ((and_vec w__6 w__7  ::  64 Word.word)))))))))))))
    | (_, CTL_SRET (_)) =>
       read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv . 
-      read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) . 
-      ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5  ::  1 Word.word)) \<then>
+      read_reg mstatus_ref \<bind> (\<lambda> (w__8 :: Mstatus) . 
+      ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__8  ::  1 Word.word)) \<then>
       set_Mstatus_SPIE mstatus_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
-      read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) . 
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__9 :: Mstatus) . 
       ((write_reg
         cur_privilege_ref
-        (if (((((get_Mstatus_SPP w__6  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))
+        (if (((((get_Mstatus_SPP w__9  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))
          then
            Supervisor
          else User) \<then>
       set_Mstatus_SPP mstatus_ref ((bool_to_bits False  ::  1 Word.word))) \<then>
-      read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) . 
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__10 :: Mstatus) . 
+      read_reg mstatus_ref \<bind> (\<lambda> (w__11 :: Mstatus) . 
       (let (_ :: unit) =
-        (prerr_endline
+        (print_endline
+          (((op@) (''CSR mstatus <- '')
+              (((op@) ((string_of_bits ((get_Mstatus_bits w__10  ::  64 Word.word))))
+                  (((op@) ('' (input: '')
+                      (((op@) ((string_of_bits ((get_Mstatus_bits w__11  ::  64 Word.word))))
+                          ('')'')))))))))) in
+      read_reg cur_privilege_ref \<bind> (\<lambda> (w__12 :: Privilege) . 
+      (let (_ :: unit) =
+        (print_endline
           (((op@) (''ret-ing from '')
               (((op@) ((privLevel_to_str prev_priv))
-                  (((op@) ('' to '') ((privLevel_to_str w__7))))))))) in
-      (read_reg sepc_ref  :: ( 64 Word.word) M))))))
+                  (((op@) ('' to '') ((privLevel_to_str w__12))))))))) in
+      (let (_ :: unit) = (cancel_reservation () ) in
+      (read_reg sepc_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 ::  64 Word.word) . 
+      (pc_alignment_mask ()   :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 ::  64 Word.word) . 
+      return ((and_vec w__13 w__14  ::  64 Word.word)))))))))))))
    ))"
 
 
@@ -4453,17 +8731,211 @@ definition handle_illegal  :: " unit \<Rightarrow>((register_value),(unit),(exce
 
 definition init_sys  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " init_sys _ = (
-   (((((write_reg cur_privilege_ref Machine \<then>
+   (((((((((write_reg cur_privilege_ref Machine \<then>
+   write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
    set_Misa_MXL misa_ref ((arch_to_bits RV64  ::  2 Word.word))) \<then>
+   set_Misa_A misa_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
    set_Misa_C misa_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
+   set_Misa_I misa_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
+   set_Misa_M misa_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
    set_Misa_U misa_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
    set_Misa_S misa_ref ((bool_to_bits True  ::  1 Word.word))) \<then>
    read_reg misa_ref) \<bind> (\<lambda> (w__0 :: Misa) . 
    (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0  ::  2 Word.word)) \<then>
    read_reg misa_ref) \<bind> (\<lambda> (w__1 :: Misa) . 
-   (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1  ::  2 Word.word)) \<then>
+   ((((((((((((((((set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1  ::  2 Word.word)) \<then>
    set_Mstatus_SD mstatus_ref ((bool_to_bits False  ::  1 Word.word))) \<then>
-   write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)))))"
+   set_Minterrupts_bits mip_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   set_Minterrupts_bits mie_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   set_Minterrupts_bits mideleg_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   set_Medeleg_bits medeleg_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   set_Mtvec_bits mtvec_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   set_Mcause_bits mcause_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   write_reg mepc_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   write_reg mtval_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   write_reg mscratch_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   write_reg mcycle_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   write_reg mtime_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   set_Counteren_bits mcounteren_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  32 Word.word))) \<then>
+   write_reg minstret_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))) \<then>
+   write_reg minstret_written_ref False) \<then>
+   read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . 
+   return ((print_endline
+              (((op@) (''CSR mstatus <- '')
+                  (((op@) ((string_of_bits ((get_Mstatus_bits w__2  ::  64 Word.word))))
+                      (((op@) ('' (input: '')
+                          (((op@)
+                              ((string_of_bits
+                                  ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word))))
+                              ('')'')))))))))))))))"
+
+
+(*val phys_mem_segments : unit -> list ((mword ty64 * mword ty64))*)
+
+definition phys_mem_segments  :: " unit \<Rightarrow>((64)Word.word*(64)Word.word)list "  where 
+     " phys_mem_segments _ = (
+   ((plat_rom_base ()   ::  64 Word.word), (plat_rom_size ()   ::  64 Word.word)) #
+     (((plat_ram_base ()   ::  64 Word.word), (plat_ram_size ()   ::  64 Word.word)) # []))"
+
+
+(*val within_phys_mem : mword ty64 -> integer -> bool*)
+
+definition within_phys_mem  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " within_phys_mem (addr :: xlenbits) (width :: int) = (
+   if (((((zopz0zIzJ_u ((plat_ram_base ()   ::  64 Word.word)) addr)) \<and> ((zopz0zIzJ_u ((add_vec_int addr width  ::  64 Word.word))
+              ((add_vec ((plat_ram_base ()   ::  64 Word.word)) ((plat_ram_size ()   ::  64 Word.word))
+                 ::  64 Word.word))))))) then
+     True
+   else if (((((zopz0zIzJ_u ((plat_rom_base ()   ::  64 Word.word)) addr)) \<and> ((zopz0zIzJ_u ((add_vec_int addr width  ::  64 Word.word))
+                   ((add_vec ((plat_rom_base ()   ::  64 Word.word)) ((plat_rom_size ()   ::  64 Word.word))
+                      ::  64 Word.word))))))) then
+     True
+   else False )"
+
+
+(*val within_clint : mword ty64 -> integer -> bool*)
+
+definition within_clint  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " within_clint (addr :: xlenbits) (width :: int) = (
+   (((zopz0zIzJ_u ((plat_clint_base ()   ::  64 Word.word)) addr)) \<and> ((zopz0zIzJ_u ((add_vec_int addr width  ::  64 Word.word))
+         ((add_vec ((plat_clint_base ()   ::  64 Word.word)) ((plat_clint_size ()   ::  64 Word.word))
+            ::  64 Word.word))))))"
+
+
+(*val within_htif_writable : mword ty64 -> integer -> bool*)
+
+definition within_htif_writable  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " within_htif_writable (addr :: xlenbits) (width :: int) = (
+   (((plat_htif_tohost ()   ::  64 Word.word)) = addr))"
+
+
+(*val within_htif_readable : mword ty64 -> integer -> bool*)
+
+definition within_htif_readable  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " within_htif_readable (addr :: xlenbits) (width :: int) = (
+   (((plat_htif_tohost ()   ::  64 Word.word)) = addr))"
+
+
+definition MSIP_BASE  :: "(64)Word.word "  where 
+     " MSIP_BASE = (
+  (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                B0,B0,B0,B0,B0,B0,B0,B0]
+    ::  64 Word.word))"
+
+
+definition MTIMECMP_BASE  :: "(64)Word.word "  where 
+     " MTIMECMP_BASE = (
+  (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,
+                B0,B0,B0,B0,B0,B0,B0,B0]
+    ::  64 Word.word))"
+
+
+definition MTIME_BASE  :: "(64)Word.word "  where 
+     " MTIME_BASE = (
+  (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,
+                B1,B1,B1,B1,B1,B0,B0,B0]
+    ::  64 Word.word))"
+
+
+(*val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+definition clint_load  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " clint_load addr width = (
+   (let addr = ((sub_vec addr ((plat_clint_base ()   ::  64 Word.word))  ::  64 Word.word)) in
+   if ((((((addr = MSIP_BASE))) \<and> ((((((width = (( 8 :: int)::ii)))) \<or> (((width = (( 4 :: int)::ii))))))))))
+   then
+     read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['')
+             (((op@) ((string_of_bits addr))
+                 (((op@) (''] -> '')
+                     ((string_of_bits ((get_Minterrupts_MSI w__0  ::  1 Word.word))))))))))) in
+     read_reg mip_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . 
+     return (MemValue ((zero_extend ((get_Minterrupts_MSI w__1  ::  1 Word.word))
+                          (((( 8 :: int)::ii) * width))
+                         :: ( 'int8_times_n::len)Word.word))))))
+   else if ((((((addr = MTIMECMP_BASE))) \<and> (((width = (( 8 :: int)::ii))))))) then
+     (read_reg mtimecmp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: xlenbits) . 
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['')
+             (((op@) ((string_of_bits addr)) (((op@) (''] -> '') ((string_of_bits w__2))))))))) in
+     (read_reg mtimecmp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . 
+     return (MemValue ((zero_extend w__3 (( 64 :: int)::ii)  :: ( 'int8_times_n::len)Word.word))))))
+   else if ((((((addr = MTIME_BASE))) \<and> (((width = (( 8 :: int)::ii))))))) then
+     (read_reg mtime_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: xlenbits) . 
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['')
+             (((op@) ((string_of_bits addr)) (((op@) (''] -> '') ((string_of_bits w__4))))))))) in
+     (read_reg mtime_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: xlenbits) . 
+     return (MemValue ((zero_extend w__5 (( 64 :: int)::ii)  :: ( 'int8_times_n::len)Word.word))))))
+   else
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['') (((op@) ((string_of_bits addr)) (''] -> <not-mapped>'')))))) in
+     return (MemException E_Load_Access_Fault))))"
+
+
+(*val clint_dispatch : unit -> M unit*)
+
+definition clint_dispatch  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " clint_dispatch _ = (
+   (read_reg mtime_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . 
+   (let (_ :: unit) = (print_endline (((op@) (''clint::tick mtime <- '') ((string_of_bits w__0))))) in
+   (set_Minterrupts_MTI mip_ref ((bool_to_bits False  ::  1 Word.word)) \<then>
+   (read_reg mtimecmp_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: xlenbits) . 
+   (read_reg mtime_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
+   if ((zopz0zIzJ_u w__1 w__2)) then
+     (read_reg mtime_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . 
+     (let (_ :: unit) =
+       (print_endline (((op@) ('' clint timer pending at mtime '') ((string_of_bits w__3))))) in
+     set_Minterrupts_MTI mip_ref ((bool_to_bits True  ::  1 Word.word))))
+   else return () )))))"
+
+
+(*val clint_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
+
+definition clint_store  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " clint_store addr width data = (
+   (let addr = ((sub_vec addr ((plat_clint_base ()   ::  64 Word.word))  ::  64 Word.word)) in
+   if ((((((addr = MSIP_BASE))) \<and> ((((((width = (( 8 :: int)::ii)))) \<or> (((width = (( 4 :: int)::ii))))))))))
+   then
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['')
+             (((op@) ((string_of_bits addr))
+                 (((op@) (''] <- '')
+                     (((op@) ((string_of_bits data))
+                         (((op@) ('' (mip.MSI <- '')
+                             (((op@)
+                                 ((string_of_bits
+                                     ((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii)))  ::  1 Word.word))))
+                                 ('')'')))))))))))))) in
+     (set_Minterrupts_MSI mip_ref
+       ((bool_to_bits
+           (((((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii)))  ::  1 Word.word)) = (vec_of_bits [B1]  ::  1 Word.word))))
+          ::  1 Word.word)) \<then>
+     clint_dispatch () ) \<then> return (MemValue () ))
+   else if ((((((addr = MTIMECMP_BASE))) \<and> (((width = (( 8 :: int)::ii))))))) then
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['')
+             (((op@) ((string_of_bits addr))
+                 (((op@) (''] <- '') (((op@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))) in
+     (write_reg mtimecmp_ref ((zero_extend data (( 64 :: int)::ii)  ::  64 Word.word)) \<then>
+     clint_dispatch () ) \<then> return (MemValue () ))
+   else
+     (let (_ :: unit) =
+       (print_endline
+         (((op@) (''clint['')
+             (((op@) ((string_of_bits addr))
+                 (((op@) (''] <- '') (((op@) ((string_of_bits data)) ('' (<unmapped>)'')))))))))) in
+     return (MemException E_SAMO_Access_Fault))))"
 
 
 (*val tick_clock : unit -> M unit*)
@@ -4471,683 +8943,1394 @@ definition init_sys  :: " unit \<Rightarrow>((register_value),(unit),(exception)
 definition tick_clock  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
      " tick_clock _ = (
    (read_reg mcycle_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii)  ::  64 Word.word))))"
+   (write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii)  ::  64 Word.word)) \<then>
+   (read_reg mtime_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
+   write_reg mtime_ref ((add_vec_int w__1 (( 1 :: int)::ii)  ::  64 Word.word)) \<then> clint_dispatch () )))"
 
 
-definition PAGESIZE_BITS  :: " int "  where 
-     " PAGESIZE_BITS = ( (( 12 :: int)::ii))"
+(*val Mk_htif_cmd : mword ty64 -> htif_cmd*)
 
+definition Mk_htif_cmd  :: "(64)Word.word \<Rightarrow> htif_cmd "  where 
+     " Mk_htif_cmd v = (
+   (| htif_cmd_htif_cmd_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
 
-(*val _get_PTE_Bits : PTE_Bits -> mword ty8*)
 
-fun get_PTE_Bits  :: " PTE_Bits \<Rightarrow>(8)Word.word "  where 
-     " get_PTE_Bits (Mk_PTE_Bits (v)) = ( v )"
+(*val _get_htif_cmd_bits : htif_cmd -> mword ty64*)
 
+definition get_htif_cmd_bits  :: " htif_cmd \<Rightarrow>(64)Word.word "  where 
+     " get_htif_cmd_bits v = (
+   (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
 
-(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*)
 
-definition set_PTE_Bits  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits r_ref v = (
+(*val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit*)
+
+definition set_htif_cmd_bits  :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_htif_cmd_bits r_ref v = (
    reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_PTE_Bits v) in
+   (let r =
+     ((r (|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
    write_reg r_ref r)))"
 
 
-fun get_PTE_Bits_D  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_D (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
+(*val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd*)
 
+definition update_htif_cmd_bits  :: " htif_cmd \<Rightarrow>(64)Word.word \<Rightarrow> htif_cmd "  where 
+     " update_htif_cmd_bits v x = (
+   (v (|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
 
-definition set_PTE_Bits_D  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_D r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val _get_htif_cmd_device : htif_cmd -> mword ty8*)
 
-fun update_PTE_Bits_D  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_D (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x  ::  8 Word.word)))"
+definition get_htif_cmd_device  :: " htif_cmd \<Rightarrow>(8)Word.word "  where 
+     " get_htif_cmd_device v = (
+   (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 63 :: int)::ii) (( 56 :: int)::ii)  ::  8 Word.word))"
 
 
-fun get_PTE_Bits_A  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_A (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
+(*val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
 
+definition set_htif_cmd_device  :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_htif_cmd_device r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   r) (( 63 :: int)::ii) (( 56 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
-definition set_PTE_Bits_A  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_A r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd*)
 
-fun update_PTE_Bits_A  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_A (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x  ::  8 Word.word)))"
+definition update_htif_cmd_device  :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd "  where 
+     " update_htif_cmd_device v x = (
+   (v (|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 63 :: int)::ii) (( 56 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_PTE_Bits_G  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_G (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
+(*val _get_htif_cmd_cmd : htif_cmd -> mword ty8*)
 
+definition get_htif_cmd_cmd  :: " htif_cmd \<Rightarrow>(8)Word.word "  where 
+     " get_htif_cmd_cmd v = (
+   (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 55 :: int)::ii) (( 48 :: int)::ii)  ::  8 Word.word))"
 
-definition set_PTE_Bits_G  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_G r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
 
-fun update_PTE_Bits_G  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_G (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x  ::  8 Word.word)))"
+definition set_htif_cmd_cmd  :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_htif_cmd_cmd r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   r) (( 55 :: int)::ii) (( 48 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun get_PTE_Bits_U  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_U (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
+(*val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd*)
 
+definition update_htif_cmd_cmd  :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd "  where 
+     " update_htif_cmd_cmd v x = (
+   (v (|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 55 :: int)::ii) (( 48 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  64 Word.word))|)))"
 
-definition set_PTE_Bits_U  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_U r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val _get_htif_cmd_payload : htif_cmd -> mword ty48*)
 
-fun update_PTE_Bits_U  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_U (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x  ::  8 Word.word)))"
+definition get_htif_cmd_payload  :: " htif_cmd \<Rightarrow>(48)Word.word "  where 
+     " get_htif_cmd_payload v = (
+   (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 47 :: int)::ii) (( 0 :: int)::ii)  ::  48 Word.word))"
 
 
-fun get_PTE_Bits_X  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_X (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
+(*val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit*)
 
+definition set_htif_cmd_payload  :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_htif_cmd_payload r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       htif_cmd_htif_cmd_chunk_0 :=
+         ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   r) (( 47 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii)  ::  48 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
 
-definition set_PTE_Bits_X  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_X r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd*)
 
-fun update_PTE_Bits_X  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_X (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x  ::  8 Word.word)))"
+definition update_htif_cmd_payload  :: " htif_cmd \<Rightarrow>(48)Word.word \<Rightarrow> htif_cmd "  where 
+     " update_htif_cmd_payload v x = (
+   (v (|
+     htif_cmd_htif_cmd_chunk_0 :=
+       ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0   v) (( 47 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 47 :: int)::ii) (( 0 :: int)::ii)  ::  48 Word.word))
+          ::  64 Word.word))|)))"
 
 
-fun get_PTE_Bits_W  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_W (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
+(*val htif_load : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
+definition htif_load  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " htif_load addr width = (
+   (read_reg htif_tohost_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . 
+   (let (_ :: unit) =
+     (print_endline
+       (((op@) (''htif['')
+           (((op@) ((string_of_bits addr)) (((op@) (''] -> '') ((string_of_bits w__0))))))))) in
+   if (((width = (( 8 :: int)::ii)))) then
+     (read_reg htif_tohost_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: xlenbits) . 
+     return (MemValue ((zero_extend w__1 (( 64 :: int)::ii)  :: ( 'int8_times_n::len)Word.word))))
+   else return (MemException E_Load_Access_Fault))))"
 
-definition set_PTE_Bits_W  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_W r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val htif_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-fun update_PTE_Bits_W  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_W (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x  ::  8 Word.word)))"
+definition htif_store  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " htif_store addr width data = (
+   (let (_ :: unit) =
+     (print_endline
+       (((op@) (''htif['')
+           (((op@) ((string_of_bits addr)) (((op@) (''] <- '') ((string_of_bits data))))))))) in
+   (let (cbits :: xlenbits) = ((EXTZ (( 64 :: int)::ii) data  ::  64 Word.word)) in
+   write_reg htif_tohost_ref cbits \<then>
+   ((let cmd = (Mk_htif_cmd cbits) in
+   (let b__0 = ((get_htif_cmd_device cmd  ::  8 Word.word)) in
+   (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word)))) then
+      (let (_ :: unit) =
+        (print_endline
+          (((op@) (''htif-syscall-proxy cmd: '')
+              ((string_of_bits ((get_htif_cmd_payload cmd  ::  48 Word.word))))))) in
+      if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd  ::  48 Word.word)) (( 0 :: int)::ii)))
+                ::  1 Word.word)) = (vec_of_bits [B1]  ::  1 Word.word)))) then
+        write_reg htif_done_ref True \<then>
+        write_reg
+          htif_exit_code_ref
+          ((shift_bits_right
+              ((zero_extend ((get_htif_cmd_payload cmd  ::  48 Word.word)) xlen  ::  64 Word.word))
+              (vec_of_bits [B0,B1]  ::  2 Word.word)
+             ::  64 Word.word))
+      else return () )
+    else
+      return (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1]  ::  8 Word.word)))) then
+                (let (_ :: unit) =
+                  (print_endline
+                    (((op@) (''htif-term cmd: '')
+                        ((string_of_bits ((get_htif_cmd_payload cmd  ::  48 Word.word))))))) in
+                (let b__2 = ((get_htif_cmd_cmd cmd  ::  8 Word.word)) in
+                if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word)))) then () 
+                else if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1]  ::  8 Word.word)))) then
+                  plat_term_write
+                    ((subrange_vec_dec ((get_htif_cmd_payload cmd  ::  48 Word.word)) (( 7 :: int)::ii) (( 0 :: int)::ii)
+                       ::  8 Word.word))
+                else print_endline (((op@) (''Unknown term cmd: '') ((string_of_bits b__2))))))
+              else print_endline (((op@) (''htif-???? cmd: '') ((string_of_bits data)))))) \<then>
+   return (MemValue () )))))))"
 
 
-fun get_PTE_Bits_R  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_R (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
+(*val htif_tick : unit -> M unit*)
 
+definition htif_tick  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " htif_tick _ = (
+   (read_reg htif_tohost_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . 
+   (let (_ :: unit) = (print_endline (((op@) (''htif::tick '') ((string_of_bits w__0))))) in
+   write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)))))"
 
-definition set_PTE_Bits_R  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_R r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val within_mmio_readable : mword ty64 -> integer -> bool*)
 
-fun update_PTE_Bits_R  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_R (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x  ::  8 Word.word)))"
+definition within_mmio_readable  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " within_mmio_readable (addr :: xlenbits) (width :: int) = (
+   (((within_clint addr width)) \<or> (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> width)))))))"
 
 
-fun get_PTE_Bits_V  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
-     " get_PTE_Bits_V (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
+(*val within_mmio_writable : mword ty64 -> integer -> bool*)
 
+definition within_mmio_writable  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " within_mmio_writable (addr :: xlenbits) (width :: int) = (
+   (((within_clint addr width)) \<or> (((((within_htif_writable addr width)) \<and> ((width \<le> (( 8 :: int)::ii))))))))"
 
-definition set_PTE_Bits_V  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_PTE_Bits_V r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . 
-   (let r = ((get_PTE_Bits w__0  ::  8 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v  ::  8 Word.word)) in
-   write_reg r_ref (Mk_PTE_Bits r)))))"
 
+(*val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-fun update_PTE_Bits_V  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
-     " update_PTE_Bits_V (Mk_PTE_Bits (v)) x = (
-   Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x  ::  8 Word.word)))"
+definition mmio_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " mmio_read (addr :: xlenbits) (width :: int) = (
+   if ((within_clint addr width)) then
+     (clint_load addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+   else if (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> width))))) then
+     (htif_load addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+   else return (MemException E_Load_Access_Fault))"
 
 
-(*val isPTEPtr : mword ty8 -> bool*)
+(*val mmio_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-definition isPTEPtr  :: "(8)Word.word \<Rightarrow> bool "  where 
-     " isPTEPtr p = (
-   (let a = (Mk_PTE_Bits p) in
-   ((((((get_PTE_Bits_R a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_W a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_X a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word)))))))))))"
+definition mmio_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " mmio_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = (
+   if ((within_clint addr width)) then clint_store addr width data
+   else if (((((within_htif_writable addr width)) \<and> ((width \<le> (( 8 :: int)::ii)))))) then
+     htif_store addr width data
+   else return (MemException E_SAMO_Access_Fault))"
 
 
-(*val isInvalidPTE : mword ty8 -> bool*)
+(*val init_platform : unit -> M unit*)
 
-definition isInvalidPTE  :: "(8)Word.word \<Rightarrow> bool "  where 
-     " isInvalidPTE p = (
-   (let a = (Mk_PTE_Bits p) in
-   ((((((get_PTE_Bits_V a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_W a  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_R a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word)))))))))))"
+definition init_platform  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " init_platform _ = (
+   (write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)) \<then>
+   write_reg htif_done_ref False) \<then>
+   write_reg htif_exit_code_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)))"
 
 
-(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*)
+(*val tick_platform : unit -> M unit*)
 
-fun checkPTEPermission  :: " AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> PTE_Bits \<Rightarrow>((register_value),(bool),(exception))monad "  where 
-     " checkPTEPermission (Read :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr))))))))))"
-|" checkPTEPermission (Write :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
-|" checkPTEPermission (ReadWrite :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr)))))))))))))"
-|" checkPTEPermission (Execute :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
-|" checkPTEPermission (Read :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return (((((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr))))))))))"
-|" checkPTEPermission (Write :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return (((((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> do_sum))) \<and> (((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
-|" checkPTEPermission (ReadWrite :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return (((((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr)))))))))))))"
-|" checkPTEPermission (Execute :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = (
-      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
-|" checkPTEPermission (_ :: AccessType) (Machine :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
-  PTE_Bits) = ( internal_error (''m-mode mem perm check''))"
+definition tick_platform  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " tick_platform _ = (
+   (let (_ :: unit) = (cancel_reservation () ) in
+   htif_tick () ))"
 
 
-(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*)
+(*val is_aligned_addr : mword ty64 -> integer -> bool*)
 
-definition update_PTE_Bits  :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow>(PTE_Bits)option "  where 
-     " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = (
-   (let update_d =
-     (((((((a = Write))) \<or> (((a = ReadWrite)))))) \<and> (((((get_PTE_Bits_D p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word)))))) in
-   (let update_a = (((get_PTE_Bits_A p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))) in
-   if (((update_d \<or> update_a))) then
-     (let np = (update_PTE_Bits_A p ((bool_to_bits True  ::  1 Word.word))) in
-     (let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits True  ::  1 Word.word)) else np) in
-     Some np))
-   else None)))"
+definition is_aligned_addr  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool "  where 
+     " is_aligned_addr (addr :: xlenbits) (width :: int) = (
+   (((ex_int ((hardware_mod ((Word.uint addr)) width)))) = (( 0 :: int)::ii)))"
 
 
-(*val PTW_Error_of_num : integer -> PTW_Error*)
+(*val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-definition PTW_Error_of_num  :: " int \<Rightarrow> PTW_Error "  where 
-     " PTW_Error_of_num arg0 = (
-   (let l__0 = arg0 in
-   if (((l__0 = (( 0 :: int)::ii)))) then PTW_Access
-   else if (((l__0 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE
-   else if (((l__0 = (( 2 :: int)::ii)))) then PTW_No_Permission
-   else if (((l__0 = (( 3 :: int)::ii)))) then PTW_Misaligned
-   else PTW_PTE_Update))"
+definition phys_mem_read  :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " phys_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+  bool) = (
+   (RISCV_read addr width aq rl res  :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 ::
+      (( 'int8_times_n::len)Word.word)option) . 
+   return ((case  (t, w__0) of
+     (Instruction, None) => MemException E_Fetch_Access_Fault
+   | (Data, None) => MemException E_Load_Access_Fault
+   | (_, Some (v)) =>
+      (let (_ :: unit) =
+        (print_endline
+          (((op@) (''mem['')
+              (((op@) ((readType_to_str t))
+                  (((op@) ('','')
+                      (((op@) ((string_of_bits addr))
+                          (((op@) (''] -> '') ((string_of_bits v))))))))))))) in
+      MemValue v)
+   ))))"
 
 
-(*val num_of_PTW_Error : PTW_Error -> integer*)
+(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-fun num_of_PTW_Error  :: " PTW_Error \<Rightarrow> int "  where 
-     " num_of_PTW_Error PTW_Access = ( (( 0 :: int)::ii))"
-|" num_of_PTW_Error PTW_Invalid_PTE = ( (( 1 :: int)::ii))"
-|" num_of_PTW_Error PTW_No_Permission = ( (( 2 :: int)::ii))"
-|" num_of_PTW_Error PTW_Misaligned = ( (( 3 :: int)::ii))"
-|" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))"
+definition checked_mem_read  :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " checked_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) = (
+   if ((((((((readType_to_str t)) = ((readType_to_str Data))))) \<and> ((within_mmio_readable addr width))))) then
+     (mmio_read addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+   else if ((within_phys_mem addr width)) then
+     (phys_mem_read t addr width False False False  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+   else return (MemException E_Load_Access_Fault))"
 
 
-(*val translationException : AccessType -> PTW_Error -> ExceptionType*)
+(*val MEMr : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-fun translationException  :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType "  where 
-     " translationException (Read :: AccessType) (PTW_Access :: PTW_Error) = ( E_Load_Access_Fault )"
-|" translationException (Read :: AccessType) (_ :: PTW_Error) = ( E_Load_Page_Fault )"
-|" translationException (Write :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )"
-|" translationException (Write :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )"
-|" translationException (Fetch :: AccessType) (PTW_Access :: PTW_Error) = ( E_Fetch_Access_Fault )"
-|" translationException (Fetch :: AccessType) (_ :: PTW_Error) = ( E_Fetch_Page_Fault )"
+(*val MEMr_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
+(*val MEMr_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-definition SV39_LEVEL_BITS  :: " int "  where 
-     " SV39_LEVEL_BITS = ( (( 9 :: int)::ii))"
+(*val MEMr_reserved : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
+(*val MEMr_reserved_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
-definition SV39_LEVELS  :: " int "  where 
-     " SV39_LEVELS = ( (( 3 :: int)::ii))"
+(*val MEMr_reserved_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
 
+definition MEMr0  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " MEMr0 addr width = ( (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
-definition PTE39_LOG_SIZE  :: " int "  where 
-     " PTE39_LOG_SIZE = ( (( 3 :: int)::ii))"
 
+definition MEMr_acquire0  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " MEMr_acquire0 addr width = (
+   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
-definition PTE39_SIZE  :: " int "  where 
-     " PTE39_SIZE = ( (( 8 :: int)::ii))"
 
+definition MEMr_strong_acquire0  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " MEMr_strong_acquire0 addr width = (
+   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
-(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*)
 
-fun get_SV39_Vaddr  :: " SV39_Vaddr \<Rightarrow>(39)Word.word "  where 
-     " get_SV39_Vaddr (Mk_SV39_Vaddr (v)) = ( v )"
+definition MEMr_reserved0  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " MEMr_reserved0 addr width = (
+   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
 
-(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*)
+definition MEMr_reserved_acquire0  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " MEMr_reserved_acquire0 addr width = (
+   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
-definition set_SV39_Vaddr  :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_Vaddr r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_SV39_Vaddr v) in
-   write_reg r_ref r)))"
 
+definition MEMr_reserved_strong_acquire0  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " MEMr_reserved_strong_acquire0 addr width = (
+   (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))"
 
-(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*)
 
-fun get_SV39_Vaddr_VPNi  :: " SV39_Vaddr \<Rightarrow>(27)Word.word "  where 
-     " get_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii)  ::  27 Word.word))"
+(*val mem_read : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
 
+definition mem_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad "  where 
+     " mem_read addr width aq rl res = (
+   if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+     return (MemException E_Load_Addr_Align)
+   else
+     (case  (aq, rl, res) of
+       (False, False, False) =>
+        (checked_mem_read Data addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+     | (True, False, False) => (MEMr_acquire0 addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+     | (False, False, True) =>
+        (MEMr_reserved0 addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+     | (True, False, True) =>
+        (MEMr_reserved_acquire0 addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+     | (False, True, False) => throw (Error_not_implemented (''load.rl''))
+     | (True, True, False) =>
+        (MEMr_strong_acquire0 addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+     | (False, True, True) => throw (Error_not_implemented (''lr.rl''))
+     | (True, True, True) =>
+        (MEMr_reserved_strong_acquire0 addr width  :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M)
+     ))"
 
-(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*)
 
-definition set_SV39_Vaddr_VPNi  :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_Vaddr_VPNi r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Vaddr) . 
-   (let r = ((get_SV39_Vaddr w__0  ::  39 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 38 :: int)::ii) (( 12 :: int)::ii) v  ::  39 Word.word)) in
-   write_reg r_ref (Mk_SV39_Vaddr r)))))"
+(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
 
+definition mem_write_ea  :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " mem_write_ea addr width aq rl con = (
+   if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+     return (MemException E_SAMO_Addr_Align)
+   else
+     (case  (aq, rl, con) of
+       (False, False, False) => MEMea addr width \<then> return (MemValue () )
+     | (False, True, False) => MEMea_release addr width \<then> return (MemValue () )
+     | (False, False, True) => MEMea_conditional addr width \<then> return (MemValue () )
+     | (False, True, True) => MEMea_conditional_release addr width \<then> return (MemValue () )
+     | (True, False, False) => throw (Error_not_implemented (''store.aq''))
+     | (True, True, False) => MEMea_strong_release addr width \<then> return (MemValue () )
+     | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
+     | (True, True, True) => MEMea_conditional_strong_release addr width \<then> return (MemValue () )
+     ))"
 
-(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*)
 
-fun update_SV39_Vaddr_VPNi  :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr "  where 
-     " update_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) x = (
-   Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) x  ::  39 Word.word)))"
+(*val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
+definition phys_mem_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " phys_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = (
+   (let (_ :: unit) =
+     (print_endline
+       (((op@) (''mem['')
+           (((op@) ((string_of_bits addr)) (((op@) (''] <- '') ((string_of_bits data))))))))) in
+   RISCV_write addr width data \<bind> (\<lambda> (w__0 :: bool) . 
+   return (if w__0 then MemValue () 
+           else MemException E_SAMO_Access_Fault))))"
 
-(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*)
 
-fun get_SV39_Vaddr_PgOfs  :: " SV39_Vaddr \<Rightarrow>(12)Word.word "  where 
-     " get_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))"
+(*val checked_mem_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
+definition checked_mem_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " checked_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = (
+   if ((within_mmio_writable addr width)) then mmio_write addr width data
+   else if ((within_phys_mem addr width)) then phys_mem_write addr width data
+   else return (MemException E_SAMO_Access_Fault))"
 
-(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*)
 
-definition set_SV39_Vaddr_PgOfs  :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_Vaddr_PgOfs r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Vaddr) . 
-   (let r = ((get_SV39_Vaddr w__0  ::  39 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v  ::  39 Word.word)) in
-   write_reg r_ref (Mk_SV39_Vaddr r)))))"
+(*val MEMval : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
+(*val MEMval_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*)
+(*val MEMval_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-fun update_SV39_Vaddr_PgOfs  :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr "  where 
-     " update_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) x = (
-   Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x  ::  39 Word.word)))"
+(*val MEMval_conditional : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
+(*val MEMval_conditional_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*)
+(*val MEMval_conditional_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*)
 
-(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*)
+definition MEMval  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " MEMval addr width data = ( checked_mem_write addr width data )"
 
-(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*)
 
-(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*)
+definition MEMval_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " MEMval_release addr width data = ( checked_mem_write addr width data )"
 
-fun get_SV39_Paddr  :: " SV39_Paddr \<Rightarrow>(56)Word.word "  where 
-     " get_SV39_Paddr (Mk_SV39_Paddr (v)) = ( v )"
 
+definition MEMval_strong_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " MEMval_strong_release addr width data = ( checked_mem_write addr width data )"
 
-(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*)
 
-definition set_SV39_Paddr  :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_Paddr r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_SV39_Paddr v) in
-   write_reg r_ref r)))"
+definition MEMval_conditional  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " MEMval_conditional addr width data = ( checked_mem_write addr width data )"
 
 
-(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*)
+definition MEMval_conditional_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " MEMval_conditional_release addr width data = ( checked_mem_write addr width data )"
 
-fun get_SV39_Paddr_PPNi  :: " SV39_Paddr \<Rightarrow>(44)Word.word "  where 
-     " get_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii)  ::  44 Word.word))"
 
+definition MEMval_conditional_strong_release  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " MEMval_conditional_strong_release addr width data = ( checked_mem_write addr width data )"
 
-(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*)
 
-definition set_SV39_Paddr_PPNi  :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_Paddr_PPNi r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Paddr) . 
-   (let r = ((get_SV39_Paddr w__0  ::  56 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 55 :: int)::ii) (( 12 :: int)::ii) v  ::  56 Word.word)) in
-   write_reg r_ref (Mk_SV39_Paddr r)))))"
+(*val mem_write_value : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
 
+definition mem_write_value  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad "  where 
+     " mem_write_value addr width value1 aq rl con = (
+   if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+     return (MemException E_SAMO_Addr_Align)
+   else
+     (case  (aq, rl, con) of
+       (False, False, False) => checked_mem_write addr width value1
+     | (False, True, False) => MEMval_release addr width value1
+     | (False, False, True) => MEMval_conditional addr width value1
+     | (False, True, True) => MEMval_conditional_release addr width value1
+     | (True, False, False) => throw (Error_not_implemented (''store.aq''))
+     | (True, True, False) => MEMval_strong_release addr width value1
+     | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
+     | (True, True, True) => MEMval_conditional_strong_release addr width value1
+     ))"
 
-(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*)
 
-fun update_SV39_Paddr_PPNi  :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr "  where 
-     " update_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) x = (
-   Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) x  ::  56 Word.word)))"
+definition PAGESIZE_BITS  :: " int "  where 
+     " PAGESIZE_BITS = ( (( 12 :: int)::ii))"
 
 
-(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*)
+(*val Mk_PTE_Bits : mword ty8 -> PTE_Bits*)
 
-(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*)
+definition Mk_PTE_Bits  :: "(8)Word.word \<Rightarrow> PTE_Bits "  where 
+     " Mk_PTE_Bits v = (
+   (| PTE_Bits_PTE_Bits_chunk_0 = ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word)) |) )"
 
-(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*)
 
-fun get_SV39_Paddr_PgOfs  :: " SV39_Paddr \<Rightarrow>(12)Word.word "  where 
-     " get_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))"
+(*val _get_PTE_Bits_bits : PTE_Bits -> mword ty8*)
 
+definition get_PTE_Bits_bits  :: " PTE_Bits \<Rightarrow>(8)Word.word "  where 
+     " get_PTE_Bits_bits v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
 
-definition set_SV39_Paddr_PgOfs  :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_Paddr_PgOfs r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Paddr) . 
-   (let r = ((get_SV39_Paddr w__0  ::  56 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v  ::  56 Word.word)) in
-   write_reg r_ref (Mk_SV39_Paddr r)))))"
 
+(*val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*)
 
-fun update_SV39_Paddr_PgOfs  :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr "  where 
-     " update_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) x = (
-   Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x  ::  56 Word.word)))"
+definition set_PTE_Bits_bits  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_bits r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-fun get_SV39_PTE  :: " SV39_PTE \<Rightarrow>(64)Word.word "  where 
-     " get_SV39_PTE (Mk_SV39_PTE (v)) = ( v )"
+(*val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits*)
 
+definition update_PTE_Bits_bits  :: " PTE_Bits \<Rightarrow>(8)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_bits v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  8 Word.word))|)))"
 
-definition set_SV39_PTE  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_PTE r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> r . 
-   (let r = (Mk_SV39_PTE v) in
-   write_reg r_ref r)))"
 
+definition get_PTE_Bits_D  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_D v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word))"
 
-fun get_SV39_PTE_PPNi  :: " SV39_PTE \<Rightarrow>(44)Word.word "  where 
-     " get_SV39_PTE_PPNi (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii)  ::  44 Word.word))"
 
+definition set_PTE_Bits_D  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_D r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
-definition set_SV39_PTE_PPNi  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_PTE_PPNi r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . 
-   (let r = ((get_SV39_PTE w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 53 :: int)::ii) (( 10 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_SV39_PTE r)))))"
 
+definition update_PTE_Bits_D  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_D v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
-fun update_SV39_PTE_PPNi  :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE "  where 
-     " update_SV39_PTE_PPNi (Mk_SV39_PTE (v)) x = (
-   Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) x  ::  64 Word.word)))"
 
+definition get_PTE_Bits_A  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_A v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word))"
 
-(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*)
 
-fun get_SV39_PTE_RSW  :: " SV39_PTE \<Rightarrow>(2)Word.word "  where 
-     " get_SV39_PTE_RSW (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii)  ::  2 Word.word))"
+definition set_PTE_Bits_A  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_A r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*)
+definition update_PTE_Bits_A  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_A v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
-definition set_SV39_PTE_RSW  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_PTE_RSW r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . 
-   (let r = ((get_SV39_PTE w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 8 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_SV39_PTE r)))))"
 
+definition get_PTE_Bits_G  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_G v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word))"
 
-(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*)
 
-fun update_SV39_PTE_RSW  :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE "  where 
-     " update_SV39_PTE_RSW (Mk_SV39_PTE (v)) x = (
-   Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) x  ::  64 Word.word)))"
+definition set_PTE_Bits_G  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_G r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*)
+definition update_PTE_Bits_G  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_G v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
-fun get_SV39_PTE_BITS  :: " SV39_PTE \<Rightarrow>(8)Word.word "  where 
-     " get_SV39_PTE_BITS (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
 
+definition get_PTE_Bits_U  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_U v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)  ::  1 Word.word))"
 
-(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*)
 
-definition set_SV39_PTE_BITS  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " set_SV39_PTE_BITS r_ref v = (
-   reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . 
-   (let r = ((get_SV39_PTE w__0  ::  64 Word.word)) in
-   (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v  ::  64 Word.word)) in
-   write_reg r_ref (Mk_SV39_PTE r)))))"
+definition set_PTE_Bits_U  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_U r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*)
+definition update_PTE_Bits_U  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_U v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
-fun update_SV39_PTE_BITS  :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE "  where 
-     " update_SV39_PTE_BITS (Mk_SV39_PTE (v)) x = (
-   Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x  ::  64 Word.word)))"
 
+definition get_PTE_Bits_X  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_X v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word))"
 
-(*val curAsid64 : unit -> M (mword ty16)*)
 
-definition curAsid64  :: " unit \<Rightarrow>((register_value),((16)Word.word),(exception))monad "  where 
-     " curAsid64 _ = (
-   (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (let satp64 = (Mk_Satp64 w__0) in
-   return ((get_Satp64_Asid satp64  ::  16 Word.word)))))"
+definition set_PTE_Bits_X  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_X r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-(*val curPTB39 : unit -> M (mword ty56)*)
+definition update_PTE_Bits_X  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_X v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
-definition curPTB39  :: " unit \<Rightarrow>((register_value),((56)Word.word),(exception))monad "  where 
-     " curPTB39 _ = (
-   (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (let satp64 = (Mk_Satp64 w__0) in
-   return ((EXTZ (( 56 :: int)::ii)
-              ((shiftl ((get_Satp64_PPN satp64  ::  44 Word.word)) PAGESIZE_BITS  ::  44 Word.word))
-             ::  56 Word.word)))))"
 
+definition get_PTE_Bits_W  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_W v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word))"
 
-(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*)
 
-function (sequential,domintros)  walk39  :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(PTW_Result),(exception))monad "  where 
-     " walk39 vaddr ac priv mxr do_sum ptb level global1 = (
-   (let va = (Mk_SV39_Vaddr vaddr) in
-   (let (pt_ofs :: paddr39) =
-     ((shiftl
-        ((EXTZ (( 56 :: int)::ii)
-            ((subrange_vec_dec
-                ((shiftr ((get_SV39_Vaddr_VPNi va  ::  27 Word.word))
-                    ((level * SV39_LEVEL_BITS))
-                   ::  27 Word.word)) ((SV39_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii)
-               ::  9 Word.word))
-           ::  56 Word.word)) PTE39_LOG_SIZE
-       ::  56 Word.word)) in
-   (let pte_addr = ((add_vec ptb pt_ofs  ::  56 Word.word)) in
-   (checked_mem_read Data ((EXTZ (( 64 :: int)::ii) pte_addr  ::  64 Word.word)) (( 8 :: int)::ii)
-     :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 64 Word.word) MemoryOpResult) . 
-   (case  w__0 of
-     MemException (_) => return (PTW_Failure PTW_Access)
-   | MemValue (v) =>
-      (let pte = (Mk_SV39_PTE v) in
-      (let pbits = ((get_SV39_PTE_BITS pte  ::  8 Word.word)) in
-      (let pattr = (Mk_PTE_Bits pbits) in
-      (let is_global =
-        (global1 \<or> (((((get_PTE_Bits_G pattr  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))) in
-      if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE)
-      else if ((isPTEPtr pbits)) then
-        if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE)
-        else
-          walk39 vaddr ac priv mxr do_sum
-            ((EXTZ (( 56 :: int)::ii)
-                ((shiftl ((get_SV39_PTE_PPNi pte  ::  44 Word.word)) PAGESIZE_BITS  ::  44 Word.word))
-               ::  56 Word.word)) ((level - (( 1 :: int)::ii))) is_global
-      else
-        checkPTEPermission ac priv mxr do_sum pattr \<bind> (\<lambda> (w__3 :: bool) . 
-        return (if ((\<not> w__3)) then PTW_Failure PTW_No_Permission
-                else if ((level > (( 0 :: int)::ii))) then
-                  (let mask1 =
-                    ((sub_vec_int
-                       ((shiftl
-                           ((xor_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
-                               ((xor_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
-                                   ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  44 Word.word))
-                                  ::  44 Word.word))
-                              ::  44 Word.word)) ((level * SV39_LEVEL_BITS))
-                          ::  44 Word.word)) (( 1 :: int)::ii)
-                      ::  44 Word.word)) in
-                  if (((((and_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word)) mask1  ::  44 Word.word)) \<noteq> ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  44 Word.word))))) then
-                    PTW_Failure PTW_Misaligned
-                  else
-                    (let ppn =
-                      ((or_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
-                         ((and_vec
-                             ((EXTZ (( 44 :: int)::ii) ((get_SV39_Vaddr_VPNi va  ::  27 Word.word))  ::  44 Word.word))
-                             mask1
-                            ::  44 Word.word))
-                        ::  44 Word.word)) in
-                    PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va  ::  12 Word.word))
-                                   ::  56 Word.word),pte,pte_addr,level,is_global)))
-                else
-                  PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
-                                  ((get_SV39_Vaddr_PgOfs va  ::  12 Word.word))
-                                 ::  56 Word.word),pte,pte_addr,level,is_global)))))))
-   ))))))" 
-by pat_completeness auto
+definition set_PTE_Bits_W  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_W r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
 
-(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*)
+definition update_PTE_Bits_W  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_W v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
-definition make_TLB39_Entry  :: "(16)Word.word \<Rightarrow> bool \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow> int \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(TLB39_Entry),(exception))monad "  where 
-     " make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr = (
-   (let (shift :: ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in
-   (let (vAddrMask :: vaddr39) =
-     ((sub_vec_int
-        ((shiftl
-            ((xor_vec vAddr
-                ((xor_vec vAddr ((EXTZ (( 39 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  39 Word.word))
-                   ::  39 Word.word))
-               ::  39 Word.word)) shift
-           ::  39 Word.word)) (( 1 :: int)::ii)
-       ::  39 Word.word)) in
-   (let (vMatchMask :: vaddr39) = ((not_vec vAddrMask  ::  39 Word.word)) in
-   (read_reg mcycle_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . 
-   return ((| TLB39_Entry_asid = asid, 
-              TLB39_Entry_global = global1, 
-              TLB39_Entry_vAddr = ((and_vec vAddr vMatchMask  ::  39 Word.word)), 
-              TLB39_Entry_pAddr =
-                ((shiftl ((shiftr pAddr shift  ::  56 Word.word)) shift  ::  56 Word.word)), 
-              TLB39_Entry_vMatchMask = vMatchMask, 
-              TLB39_Entry_vAddrMask = vAddrMask, 
-              TLB39_Entry_pte = pte, 
-              TLB39_Entry_pteAddr = pteAddr, 
-              TLB39_Entry_age = w__0  |)))))))"
 
+definition get_PTE_Bits_R  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_R v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word))"
 
-definition TLBEntries  :: " int "  where 
-     " TLBEntries = ( (( 32 :: int)::ii))"
 
+definition set_PTE_Bits_R  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_R r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
-(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*)
 
-definition lookupTLB39  :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),((int*TLB39_Entry)option),(exception))monad "  where 
-     " lookupTLB39 asid vaddr = (
-   read_reg tlb39_ref \<bind> (\<lambda> (w__0 ::  TLB39_Entry option) . 
-   return ((case  w__0 of
-     None => None
-   | Some (e) =>
-      if (((((((TLB39_Entry_global   e) \<or> ((((TLB39_Entry_asid   e) = asid)))))) \<and> ((((TLB39_Entry_vAddr   e) = ((and_vec(TLB39_Entry_vMatchMask   e) vaddr  ::  39 Word.word))))))))
-      then
-        Some ((( 0 :: int)::ii), e)
-      else None
-   ))))"
+definition update_PTE_Bits_R  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_R v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
 
-(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*)
+definition get_PTE_Bits_V  :: " PTE_Bits \<Rightarrow>(1)Word.word "  where 
+     " get_PTE_Bits_V v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))"
 
-definition addToTLB39  :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " addToTLB39 asid vAddr pAddr pte pteAddr level global1 = (
-   make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr \<bind> (\<lambda> ent . 
-   write_reg tlb39_ref (Some ent)))"
 
+definition set_PTE_Bits_V  :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_PTE_Bits_V r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       PTE_Bits_PTE_Bits_chunk_0 :=
+         ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+            ::  8 Word.word))|))) in
+   write_reg r_ref r)))"
 
-(*val writeTLB39 : ii -> TLB39_Entry -> M unit*)
 
-definition writeTLB39  :: " int \<Rightarrow> TLB39_Entry \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " writeTLB39 (idx :: ii) (ent :: TLB39_Entry) = ( write_reg tlb39_ref (Some ent))"
+definition update_PTE_Bits_V  :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits "  where 
+     " update_PTE_Bits_V v x = (
+   (v (|
+     PTE_Bits_PTE_Bits_chunk_0 :=
+       ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0   v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word))
+          ::  8 Word.word))|)))"
 
 
-(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*)
+(*val isPTEPtr : mword ty8 -> bool*)
 
-definition flushTLB  :: "((16)Word.word)option \<Rightarrow>((39)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " flushTLB asid addr = (
-   read_reg tlb39_ref \<bind> (\<lambda> (w__0 ::  TLB39_Entry option) . 
-   (let (ent ::  TLB39_Entry option) =
-     ((case  (w__0, asid, addr) of
-       (None, _, _) => None
-     | (Some (e), None, None) => None
-     | (Some (e), None, Some (a)) =>
-        if ((((TLB39_Entry_vAddr   e) = ((and_vec(TLB39_Entry_vMatchMask   e) a  ::  39 Word.word))))) then
-          None
-        else Some e
-     | (Some (e), Some (i), None) =>
-        if (((((((TLB39_Entry_asid   e) = i))) \<and> ((\<not>(TLB39_Entry_global   e)))))) then None
-        else Some e
-     | (Some (e), Some (i), Some (a)) =>
-        if (((((((TLB39_Entry_asid   e) = i))) \<and> (((((((TLB39_Entry_vAddr   e) = ((and_vec a(TLB39_Entry_vMatchMask   e)  ::  39 Word.word))))) \<and> ((\<not>(TLB39_Entry_global   e))))))))) then
-          None
-        else Some e
-     )) in
-   write_reg tlb39_ref ent)))"
+definition isPTEPtr  :: "(8)Word.word \<Rightarrow> bool "  where 
+     " isPTEPtr p = (
+   (let a = (Mk_PTE_Bits p) in
+   ((((((get_PTE_Bits_R a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_W a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_X a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word)))))))))))"
 
 
-definition enable_dirty_update  :: " bool "  where 
-     " enable_dirty_update = ( False )"
+(*val isInvalidPTE : mword ty8 -> bool*)
 
+definition isInvalidPTE  :: "(8)Word.word \<Rightarrow> bool "  where 
+     " isInvalidPTE p = (
+   (let a = (Mk_PTE_Bits p) in
+   ((((((get_PTE_Bits_V a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_W a  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_R a  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word)))))))))))"
 
-(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*)
 
-definition translate39  :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),(TR39_Result),(exception))monad "  where 
-     " translate39 vAddr ac priv mxr do_sum level = (
-   (curAsid64 ()   :: ( 16 Word.word) M) \<bind> (\<lambda> asid . 
-   lookupTLB39 asid vAddr \<bind> (\<lambda> (w__0 ::  ((ii * TLB39_Entry))option) . 
-   (case  w__0 of
-     Some (idx,ent) =>
-      (let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS(TLB39_Entry_pte   ent)  ::  8 Word.word))) in
-      checkPTEPermission ac priv mxr do_sum pteBits \<bind> (\<lambda> (w__1 :: bool) . 
-      if ((\<not> w__1)) then return (TR39_Failure PTW_No_Permission)
-      else
-        (case  ((update_PTE_Bits pteBits ac)) of
-          None =>
-           return (TR39_Address ((or_vec(TLB39_Entry_pAddr   ent)
-                                    ((EXTZ (( 56 :: int)::ii)
-                                        ((and_vec vAddr(TLB39_Entry_vAddrMask   ent)  ::  39 Word.word))
-                                       ::  56 Word.word))
+(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*)
+
+fun checkPTEPermission  :: " AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> PTE_Bits \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " checkPTEPermission (Read :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr))))))))))"
+|" checkPTEPermission (Write :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
+|" checkPTEPermission (ReadWrite :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr)))))))))))))"
+|" checkPTEPermission (Execute :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
+|" checkPTEPermission (Read :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return (((((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr))))))))))"
+|" checkPTEPermission (Write :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return (((((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> do_sum))) \<and> (((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
+|" checkPTEPermission (ReadWrite :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return (((((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_W p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<and> mxr)))))))))))))"
+|" checkPTEPermission (Execute :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = (
+      return ((((((((get_PTE_Bits_U p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) \<and> (((((get_PTE_Bits_X p  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))"
+|" checkPTEPermission (_ :: AccessType) (Machine :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+  PTE_Bits) = ( internal_error (''m-mode mem perm check''))"
+
+
+(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*)
+
+definition update_PTE_Bits  :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow>(PTE_Bits)option "  where 
+     " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = (
+   (let update_d =
+     (((((((((accessType_to_str a)) = ((accessType_to_str Write))))) \<or> (((((accessType_to_str a)) = ((accessType_to_str ReadWrite)))))))) \<and> (((((get_PTE_Bits_D p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word)))))) in
+   (let update_a = (((get_PTE_Bits_A p  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))) in
+   if (((update_d \<or> update_a))) then
+     (let np = (update_PTE_Bits_A p ((bool_to_bits True  ::  1 Word.word))) in
+     (let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits True  ::  1 Word.word)) else np) in
+     Some np))
+   else None)))"
+
+
+(*val PTW_Error_of_num : integer -> PTW_Error*)
+
+definition PTW_Error_of_num  :: " int \<Rightarrow> PTW_Error "  where 
+     " PTW_Error_of_num arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then PTW_Access
+   else if (((p00 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE
+   else if (((p00 = (( 2 :: int)::ii)))) then PTW_No_Permission
+   else if (((p00 = (( 3 :: int)::ii)))) then PTW_Misaligned
+   else PTW_PTE_Update))"
+
+
+(*val num_of_PTW_Error : PTW_Error -> integer*)
+
+fun num_of_PTW_Error  :: " PTW_Error \<Rightarrow> int "  where 
+     " num_of_PTW_Error PTW_Access = ( (( 0 :: int)::ii))"
+|" num_of_PTW_Error PTW_Invalid_PTE = ( (( 1 :: int)::ii))"
+|" num_of_PTW_Error PTW_No_Permission = ( (( 2 :: int)::ii))"
+|" num_of_PTW_Error PTW_Misaligned = ( (( 3 :: int)::ii))"
+|" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))"
+
+
+(*val ptw_error_to_str : PTW_Error -> string*)
+
+fun ptw_error_to_str  :: " PTW_Error \<Rightarrow> string "  where 
+     " ptw_error_to_str PTW_Access = ( (''mem-access-error''))"
+|" ptw_error_to_str PTW_Invalid_PTE = ( (''invalid-pte''))"
+|" ptw_error_to_str PTW_No_Permission = ( (''no-permission''))"
+|" ptw_error_to_str PTW_Misaligned = ( (''misaligned-superpage''))"
+|" ptw_error_to_str PTW_PTE_Update = ( (''pte-update-needed''))"
+
+
+(*val translationException : AccessType -> PTW_Error -> ExceptionType*)
+
+definition translationException  :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType "  where 
+     " translationException (a :: AccessType) (f :: PTW_Error) = (
+   (let (e :: ExceptionType) =
+     ((case  (a, f) of
+       (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+     | (ReadWrite, _) => E_SAMO_Page_Fault
+     | (Read, PTW_Access) => E_Load_Access_Fault
+     | (Read, _) => E_Load_Page_Fault
+     | (Write, PTW_Access) => E_SAMO_Access_Fault
+     | (Write, _) => E_SAMO_Page_Fault
+     | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+     | (Fetch, _) => E_Fetch_Page_Fault
+     )) in
+   (let (_ :: unit) =
+     (print_endline
+       (((op@) (''translationException('')
+           (((op@) ((accessType_to_str a))
+               (((op@) ('', '')
+                   (((op@) ((ptw_error_to_str f))
+                       (((op@) ('') -> '') ((exceptionType_to_str e))))))))))))) in
+   e)))"
+
+
+definition SV39_LEVEL_BITS  :: " int "  where 
+     " SV39_LEVEL_BITS = ( (( 9 :: int)::ii))"
+
+
+definition SV39_LEVELS  :: " int "  where 
+     " SV39_LEVELS = ( (( 3 :: int)::ii))"
+
+
+definition PTE39_LOG_SIZE  :: " int "  where 
+     " PTE39_LOG_SIZE = ( (( 3 :: int)::ii))"
+
+
+definition PTE39_SIZE  :: " int "  where 
+     " PTE39_SIZE = ( (( 8 :: int)::ii))"
+
+
+(*val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr*)
+
+definition Mk_SV39_Vaddr  :: "(39)Word.word \<Rightarrow> SV39_Vaddr "  where 
+     " Mk_SV39_Vaddr v = (
+   (| SV39_Vaddr_SV39_Vaddr_chunk_0 = ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii)  ::  39 Word.word)) |) )"
+
+
+(*val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39*)
+
+definition get_SV39_Vaddr_bits  :: " SV39_Vaddr \<Rightarrow>(39)Word.word "  where 
+     " get_SV39_Vaddr_bits v = (
+   (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   v) (( 38 :: int)::ii) (( 0 :: int)::ii)  ::  39 Word.word))"
+
+
+(*val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*)
+
+definition set_SV39_Vaddr_bits  :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_Vaddr_bits r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   r) (( 38 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii)  ::  39 Word.word))
+            ::  39 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr*)
+
+definition update_SV39_Vaddr_bits  :: " SV39_Vaddr \<Rightarrow>(39)Word.word \<Rightarrow> SV39_Vaddr "  where 
+     " update_SV39_Vaddr_bits v x = (
+   (v (|
+     SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   v) (( 38 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 38 :: int)::ii) (( 0 :: int)::ii)  ::  39 Word.word))
+          ::  39 Word.word))|)))"
+
+
+(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*)
+
+definition get_SV39_Vaddr_VPNi  :: " SV39_Vaddr \<Rightarrow>(27)Word.word "  where 
+     " get_SV39_Vaddr_VPNi v = (
+   (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   v) (( 38 :: int)::ii) (( 12 :: int)::ii)  ::  27 Word.word))"
+
+
+(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*)
+
+definition set_SV39_Vaddr_VPNi  :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_Vaddr_VPNi r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   r) (( 38 :: int)::ii) (( 12 :: int)::ii)
+             ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+            ::  39 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*)
+
+definition update_SV39_Vaddr_VPNi  :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr "  where 
+     " update_SV39_Vaddr_VPNi v x = (
+   (v (|
+     SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   v) (( 38 :: int)::ii) (( 12 :: int)::ii)
+           ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii)  ::  27 Word.word))
+          ::  39 Word.word))|)))"
+
+
+(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*)
+
+definition get_SV39_Vaddr_PgOfs  :: " SV39_Vaddr \<Rightarrow>(12)Word.word "  where 
+     " get_SV39_Vaddr_PgOfs v = (
+   (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   v) (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))"
+
+
+(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*)
+
+definition set_SV39_Vaddr_PgOfs  :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_Vaddr_PgOfs r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))
+            ::  39 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*)
+
+definition update_SV39_Vaddr_PgOfs  :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr "  where 
+     " update_SV39_Vaddr_PgOfs v x = (
+   (v (|
+     SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0   v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))
+          ::  39 Word.word))|)))"
+
+
+(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*)
+
+(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*)
+
+(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*)
+
+(*val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr*)
+
+definition Mk_SV39_Paddr  :: "(56)Word.word \<Rightarrow> SV39_Paddr "  where 
+     " Mk_SV39_Paddr v = (
+   (| SV39_Paddr_SV39_Paddr_chunk_0 = ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii)  ::  56 Word.word)) |) )"
+
+
+(*val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56*)
+
+definition get_SV39_Paddr_bits  :: " SV39_Paddr \<Rightarrow>(56)Word.word "  where 
+     " get_SV39_Paddr_bits v = (
+   (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   v) (( 55 :: int)::ii) (( 0 :: int)::ii)  ::  56 Word.word))"
+
+
+(*val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*)
+
+definition set_SV39_Paddr_bits  :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_Paddr_bits r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_Paddr_SV39_Paddr_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   r) (( 55 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii)  ::  56 Word.word))
+            ::  56 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr*)
+
+definition update_SV39_Paddr_bits  :: " SV39_Paddr \<Rightarrow>(56)Word.word \<Rightarrow> SV39_Paddr "  where 
+     " update_SV39_Paddr_bits v x = (
+   (v (|
+     SV39_Paddr_SV39_Paddr_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   v) (( 55 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 55 :: int)::ii) (( 0 :: int)::ii)  ::  56 Word.word))
+          ::  56 Word.word))|)))"
+
+
+(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*)
+
+definition get_SV39_Paddr_PPNi  :: " SV39_Paddr \<Rightarrow>(44)Word.word "  where 
+     " get_SV39_Paddr_PPNi v = (
+   (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   v) (( 55 :: int)::ii) (( 12 :: int)::ii)  ::  44 Word.word))"
+
+
+(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*)
+
+definition set_SV39_Paddr_PPNi  :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_Paddr_PPNi r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_Paddr_SV39_Paddr_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   r) (( 55 :: int)::ii) (( 12 :: int)::ii)
+             ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))
+            ::  56 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*)
+
+definition update_SV39_Paddr_PPNi  :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr "  where 
+     " update_SV39_Paddr_PPNi v x = (
+   (v (|
+     SV39_Paddr_SV39_Paddr_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   v) (( 55 :: int)::ii) (( 12 :: int)::ii)
+           ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))
+          ::  56 Word.word))|)))"
+
+
+(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*)
+
+(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*)
+
+(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*)
+
+definition get_SV39_Paddr_PgOfs  :: " SV39_Paddr \<Rightarrow>(12)Word.word "  where 
+     " get_SV39_Paddr_PgOfs v = (
+   (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   v) (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))"
+
+
+definition set_SV39_Paddr_PgOfs  :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_Paddr_PgOfs r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_Paddr_SV39_Paddr_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))
+            ::  56 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+definition update_SV39_Paddr_PgOfs  :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr "  where 
+     " update_SV39_Paddr_PgOfs v x = (
+   (v (|
+     SV39_Paddr_SV39_Paddr_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0   v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii)  ::  12 Word.word))
+          ::  56 Word.word))|)))"
+
+
+(*val Mk_SV39_PTE : mword ty64 -> SV39_PTE*)
+
+definition Mk_SV39_PTE  :: "(64)Word.word \<Rightarrow> SV39_PTE "  where 
+     " Mk_SV39_PTE v = (
+   (| SV39_PTE_SV39_PTE_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) |) )"
+
+
+definition get_SV39_PTE_bits  :: " SV39_PTE \<Rightarrow>(64)Word.word "  where 
+     " get_SV39_PTE_bits v = (
+   (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))"
+
+
+definition set_SV39_PTE_bits  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_PTE_bits r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+definition update_SV39_PTE_bits  :: " SV39_PTE \<Rightarrow>(64)Word.word \<Rightarrow> SV39_PTE "  where 
+     " update_SV39_PTE_bits v x = (
+   (v (|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word))
+          ::  64 Word.word))|)))"
+
+
+definition get_SV39_PTE_PPNi  :: " SV39_PTE \<Rightarrow>(44)Word.word "  where 
+     " get_SV39_PTE_PPNi v = (
+   (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 53 :: int)::ii) (( 10 :: int)::ii)  ::  44 Word.word))"
+
+
+definition set_SV39_PTE_PPNi  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_PTE_PPNi r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   r) (( 53 :: int)::ii) (( 10 :: int)::ii)
+             ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+definition update_SV39_PTE_PPNi  :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE "  where 
+     " update_SV39_PTE_PPNi v x = (
+   (v (|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 53 :: int)::ii) (( 10 :: int)::ii)
+           ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii)  ::  44 Word.word))
+          ::  64 Word.word))|)))"
+
+
+(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*)
+
+definition get_SV39_PTE_RSW  :: " SV39_PTE \<Rightarrow>(2)Word.word "  where 
+     " get_SV39_PTE_RSW v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 9 :: int)::ii) (( 8 :: int)::ii)  ::  2 Word.word))"
+
+
+(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*)
+
+definition set_SV39_PTE_RSW  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_PTE_RSW r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+             ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*)
+
+definition update_SV39_PTE_RSW  :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE "  where 
+     " update_SV39_PTE_RSW v x = (
+   (v (|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+           ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word))
+          ::  64 Word.word))|)))"
+
+
+(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*)
+
+definition get_SV39_PTE_BITS  :: " SV39_PTE \<Rightarrow>(8)Word.word "  where 
+     " get_SV39_PTE_BITS v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))"
+
+
+(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*)
+
+definition set_SV39_PTE_BITS  :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " set_SV39_PTE_BITS r_ref v = (
+   reg_deref r_ref \<bind> (\<lambda> r . 
+   (let r =
+     ((r (|
+       SV39_PTE_SV39_PTE_chunk_0 :=
+         ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+             ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+            ::  64 Word.word))|))) in
+   write_reg r_ref r)))"
+
+
+(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*)
+
+definition update_SV39_PTE_BITS  :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE "  where 
+     " update_SV39_PTE_BITS v x = (
+   (v (|
+     SV39_PTE_SV39_PTE_chunk_0 :=
+       ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0   v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+           ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
+          ::  64 Word.word))|)))"
+
+
+(*val curAsid64 : unit -> M (mword ty16)*)
+
+definition curAsid64  :: " unit \<Rightarrow>((register_value),((16)Word.word),(exception))monad "  where 
+     " curAsid64 _ = (
+   (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   (let satp64 = (Mk_Satp64 w__0) in
+   return ((get_Satp64_Asid satp64  ::  16 Word.word)))))"
+
+
+(*val curPTB39 : unit -> M (mword ty56)*)
+
+definition curPTB39  :: " unit \<Rightarrow>((register_value),((56)Word.word),(exception))monad "  where 
+     " curPTB39 _ = (
+   (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   (let satp64 = (Mk_Satp64 w__0) in
+   return ((EXTZ (( 56 :: int)::ii)
+              ((shiftl ((get_Satp64_PPN satp64  ::  44 Word.word)) PAGESIZE_BITS  ::  44 Word.word))
+             ::  56 Word.word)))))"
+
+
+(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*)
+
+function (sequential,domintros)  walk39  :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(PTW_Result),(exception))monad "  where 
+     " walk39 vaddr ac priv mxr do_sum ptb level global1 = (
+   (let va = (Mk_SV39_Vaddr vaddr) in
+   (let (pt_ofs :: paddr39) =
+     ((shiftl
+        ((EXTZ (( 56 :: int)::ii)
+            ((subrange_vec_dec
+                ((shiftr ((get_SV39_Vaddr_VPNi va  ::  27 Word.word))
+                    ((level * SV39_LEVEL_BITS))
+                   ::  27 Word.word)) ((SV39_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii)
+               ::  9 Word.word))
+           ::  56 Word.word)) PTE39_LOG_SIZE
+       ::  56 Word.word)) in
+   (let pte_addr = ((add_vec ptb pt_ofs  ::  56 Word.word)) in
+   (phys_mem_read Data ((EXTZ (( 64 :: int)::ii) pte_addr  ::  64 Word.word)) (( 8 :: int)::ii) False False False
+     :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 64 Word.word) MemoryOpResult) . 
+   (case  w__0 of
+     MemException (_) =>
+      (let (_ :: unit) =
+        (print_endline
+          (((op@) (''walk39(vaddr='')
+              (((op@) ((string_of_bits vaddr))
+                  (((op@) ('' level='')
+                      (((op@) ((stringFromInteger level))
+                          (((op@) ('' pt_base='')
+                              (((op@) ((string_of_bits ptb))
+                                  (((op@) ('' pt_ofs='')
+                                      (((op@) ((string_of_bits pt_ofs))
+                                          (((op@) ('' pte_addr='')
+                                              (((op@) ((string_of_bits pte_addr))
+                                                  ('': invalid pte address'')))))))))))))))))))))) in
+      return (PTW_Failure PTW_Access))
+   | MemValue (v) =>
+      (let pte = (Mk_SV39_PTE v) in
+      (let pbits = ((get_SV39_PTE_BITS pte  ::  8 Word.word)) in
+      (let pattr = (Mk_PTE_Bits pbits) in
+      (let is_global =
+        (global1 \<or> (((((get_PTE_Bits_G pattr  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))) in
+      if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE)
+      else if ((isPTEPtr pbits)) then
+        if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE)
+        else
+          walk39 vaddr ac priv mxr do_sum
+            ((EXTZ (( 56 :: int)::ii)
+                ((shiftl ((get_SV39_PTE_PPNi pte  ::  44 Word.word)) PAGESIZE_BITS  ::  44 Word.word))
+               ::  56 Word.word)) ((level - (( 1 :: int)::ii))) is_global
+      else
+        checkPTEPermission ac priv mxr do_sum pattr \<bind> (\<lambda> (w__3 :: bool) . 
+        return (if ((\<not> w__3)) then PTW_Failure PTW_No_Permission
+                else if ((level > (( 0 :: int)::ii))) then
+                  (let mask1 =
+                    ((sub_vec_int
+                       ((shiftl
+                           ((xor_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
+                               ((xor_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
+                                   ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  44 Word.word))
+                                  ::  44 Word.word))
+                              ::  44 Word.word)) ((level * SV39_LEVEL_BITS))
+                          ::  44 Word.word)) (( 1 :: int)::ii)
+                      ::  44 Word.word)) in
+                  if (((((and_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word)) mask1  ::  44 Word.word)) \<noteq> ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  44 Word.word))))) then
+                    PTW_Failure PTW_Misaligned
+                  else
+                    (let ppn =
+                      ((or_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
+                         ((and_vec
+                             ((EXTZ (( 44 :: int)::ii) ((get_SV39_Vaddr_VPNi va  ::  27 Word.word))  ::  44 Word.word))
+                             mask1
+                            ::  44 Word.word))
+                        ::  44 Word.word)) in
+                    PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va  ::  12 Word.word))
+                                   ::  56 Word.word),pte,pte_addr,level,is_global)))
+                else
+                  PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte  ::  44 Word.word))
+                                  ((get_SV39_Vaddr_PgOfs va  ::  12 Word.word))
+                                 ::  56 Word.word),pte,pte_addr,level,is_global)))))))
+   ))))))" 
+by pat_completeness auto
+
+
+(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*)
+
+definition make_TLB39_Entry  :: "(16)Word.word \<Rightarrow> bool \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow> int \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(TLB39_Entry),(exception))monad "  where 
+     " make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr = (
+   (let (shift :: ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in
+   (let (vAddrMask :: vaddr39) =
+     ((sub_vec_int
+        ((shiftl
+            ((xor_vec vAddr
+                ((xor_vec vAddr ((EXTZ (( 39 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  39 Word.word))
+                   ::  39 Word.word))
+               ::  39 Word.word)) shift
+           ::  39 Word.word)) (( 1 :: int)::ii)
+       ::  39 Word.word)) in
+   (let (vMatchMask :: vaddr39) = ((not_vec vAddrMask  ::  39 Word.word)) in
+   (read_reg mcycle_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . 
+   return ((| TLB39_Entry_asid = asid, 
+              TLB39_Entry_global = global1, 
+              TLB39_Entry_vAddr = ((and_vec vAddr vMatchMask  ::  39 Word.word)), 
+              TLB39_Entry_pAddr =
+                ((shiftl ((shiftr pAddr shift  ::  56 Word.word)) shift  ::  56 Word.word)), 
+              TLB39_Entry_vMatchMask = vMatchMask, 
+              TLB39_Entry_vAddrMask = vAddrMask, 
+              TLB39_Entry_pte = pte, 
+              TLB39_Entry_pteAddr = pteAddr, 
+              TLB39_Entry_age = w__0  |)))))))"
+
+
+definition TLBEntries  :: " int "  where 
+     " TLBEntries = ( (( 32 :: int)::ii))"
+
+
+(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*)
+
+definition lookupTLB39  :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),((int*TLB39_Entry)option),(exception))monad "  where 
+     " lookupTLB39 asid vaddr = (
+   read_reg tlb39_ref \<bind> (\<lambda> (w__0 ::  TLB39_Entry option) . 
+   return ((case  w__0 of
+     None => None
+   | Some (e) =>
+      if (((((((TLB39_Entry_global   e) \<or> ((((TLB39_Entry_asid   e) = asid)))))) \<and> ((((TLB39_Entry_vAddr   e) = ((and_vec(TLB39_Entry_vMatchMask   e) vaddr  ::  39 Word.word))))))))
+      then
+        Some ((( 0 :: int)::ii), e)
+      else None
+   ))))"
+
+
+(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*)
+
+definition addToTLB39  :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " addToTLB39 asid vAddr pAddr pte pteAddr level global1 = (
+   make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr \<bind> (\<lambda> ent . 
+   write_reg tlb39_ref (Some ent)))"
+
+
+(*val writeTLB39 : ii -> TLB39_Entry -> M unit*)
+
+definition writeTLB39  :: " int \<Rightarrow> TLB39_Entry \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " writeTLB39 (idx :: ii) (ent :: TLB39_Entry) = ( write_reg tlb39_ref (Some ent))"
+
+
+(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*)
+
+definition flushTLB  :: "((16)Word.word)option \<Rightarrow>((39)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " flushTLB asid addr = (
+   read_reg tlb39_ref \<bind> (\<lambda> (w__0 ::  TLB39_Entry option) . 
+   (let (ent ::  TLB39_Entry option) =
+     ((case  (w__0, asid, addr) of
+       (None, _, _) => None
+     | (Some (e), None, None) => None
+     | (Some (e), None, Some (a)) =>
+        if ((((TLB39_Entry_vAddr   e) = ((and_vec(TLB39_Entry_vMatchMask   e) a  ::  39 Word.word))))) then
+          None
+        else Some e
+     | (Some (e), Some (i), None) =>
+        if (((((((TLB39_Entry_asid   e) = i))) \<and> ((\<not>(TLB39_Entry_global   e)))))) then None
+        else Some e
+     | (Some (e), Some (i), Some (a)) =>
+        if (((((((TLB39_Entry_asid   e) = i))) \<and> (((((((TLB39_Entry_vAddr   e) = ((and_vec a(TLB39_Entry_vMatchMask   e)  ::  39 Word.word))))) \<and> ((\<not>(TLB39_Entry_global   e))))))))) then
+          None
+        else Some e
+     )) in
+   write_reg tlb39_ref ent)))"
+
+
+(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*)
+
+definition translate39  :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),(TR39_Result),(exception))monad "  where 
+     " translate39 vAddr ac priv mxr do_sum level = (
+   (curAsid64 ()   :: ( 16 Word.word) M) \<bind> (\<lambda> asid . 
+   lookupTLB39 asid vAddr \<bind> (\<lambda> (w__0 ::  ((ii * TLB39_Entry))option) . 
+   (case  w__0 of
+     Some (idx,ent) =>
+      (let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS(TLB39_Entry_pte   ent)  ::  8 Word.word))) in
+      checkPTEPermission ac priv mxr do_sum pteBits \<bind> (\<lambda> (w__1 :: bool) . 
+      if ((\<not> w__1)) then return (TR39_Failure PTW_No_Permission)
+      else
+        (case  ((update_PTE_Bits pteBits ac)) of
+          None =>
+           return (TR39_Address ((or_vec(TLB39_Entry_pAddr   ent)
+                                    ((EXTZ (( 56 :: int)::ii)
+                                        ((and_vec vAddr(TLB39_Entry_vAddrMask   ent)  ::  39 Word.word))
+                                       ::  56 Word.word))
                                    ::  56 Word.word)))
         | Some (pbits) =>
-           if ((\<not> enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update)
+           if ((\<not> ((plat_enable_dirty_update () )))) then return (TR39_Failure PTW_PTE_Update)
            else
              (let (n_ent :: TLB39_Entry) = ent in
              (let n_ent =
                ((n_ent (|
                  TLB39_Entry_pte :=
-                   ((update_SV39_PTE_BITS(TLB39_Entry_pte   ent) ((get_PTE_Bits pbits  ::  8 Word.word))))|))) in
+                   ((update_SV39_PTE_BITS(TLB39_Entry_pte   ent)
+                       ((get_PTE_Bits_bits pbits  ::  8 Word.word))))|))) in
              (writeTLB39 idx n_ent \<then>
              checked_mem_write ((EXTZ (( 64 :: int)::ii)(TLB39_Entry_pteAddr   ent)  ::  64 Word.word)) (( 8 :: int)::ii)
-               ((get_SV39_PTE(TLB39_Entry_pte   ent)  ::  64 Word.word))) \<bind> (\<lambda> (w__2 :: unit
+               ((get_SV39_PTE_bits(TLB39_Entry_pte   ent)  ::  64 Word.word))) \<bind> (\<lambda> (w__2 :: unit
                MemoryOpResult) . 
              (case  w__2 of
                MemValue (_) => return () 
@@ -5165,16 +10348,16 @@ definition translate39  :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow>
       (case  w__7 of
         PTW_Failure (f) => return (TR39_Failure f)
       | PTW_Success (pAddr,pte,pteAddr,level,global1) =>
-         (case  ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte  ::  8 Word.word))) ac)) of
+         (case  ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV39_PTE_BITS pte  ::  8 Word.word)))) ac)) of
            None =>
             addToTLB39 asid vAddr pAddr pte pteAddr level global1 \<then> return (TR39_Address pAddr)
          | Some (pbits) =>
-            if ((\<not> enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update)
+            if ((\<not> ((plat_enable_dirty_update () )))) then return (TR39_Failure PTW_PTE_Update)
             else
               (let (w_pte :: SV39_PTE) =
-                (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits  ::  8 Word.word))) in
+                (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits  ::  8 Word.word))) in
               checked_mem_write ((EXTZ (( 64 :: int)::ii) pteAddr  ::  64 Word.word)) (( 8 :: int)::ii)
-                ((get_SV39_PTE w_pte  ::  64 Word.word)) \<bind> (\<lambda> (w__8 :: unit MemoryOpResult) . 
+                ((get_SV39_PTE_bits w_pte  ::  64 Word.word)) \<bind> (\<lambda> (w__8 :: unit MemoryOpResult) . 
               (case  w__8 of
                 MemValue (_) =>
                  addToTLB39 asid vAddr pAddr w_pte pteAddr level global1 \<then>
@@ -5199,7 +10382,7 @@ definition translationMode  :: " Privilege \<Rightarrow>((register_value),(SATPM
      (case  arch of
        Some (RV64) =>
         (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
-        (let (mbits :: satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1)  ::  4 Word.word)) in
+        (let (mbits :: satp_mode) = ((get_Satp64_Mode ((Mk_Satp64 w__1))  ::  4 Word.word)) in
         (case  ((satpMode_of_bits RV64 mbits)) of
           Some (m) => return m
         | None => internal_error (''invalid RV64 translation mode in satp'')
@@ -5208,49 +10391,698 @@ definition translationMode  :: " Privilege \<Rightarrow>((register_value),(SATPM
      ))))"
 
 
-(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*)
+(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*)
+
+definition translateAddr  :: "(64)Word.word \<Rightarrow> AccessType \<Rightarrow> ReadType \<Rightarrow>((register_value),(TR_Result),(exception))monad "  where 
+     " translateAddr vAddr ac rt = (
+   (case  rt of
+     Instruction => read_reg cur_privilege_ref
+   | Data =>
+      read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . 
+      if (((((get_Mstatus_MPRV w__1  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) then
+        read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . 
+        return ((privLevel_of_bits ((get_Mstatus_MPP w__2  ::  2 Word.word)))))
+      else read_reg cur_privilege_ref)
+   ) \<bind> (\<lambda> (effPriv :: Privilege) . 
+   read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) . 
+   (let (mxr :: bool) =
+     (((get_Mstatus_MXR w__5  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))) in
+   read_reg mstatus_ref \<bind> (\<lambda> (w__6 :: Mstatus) . 
+   (let (do_sum :: bool) =
+     (((get_Mstatus_SUM w__6  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))) in
+   translationMode effPriv \<bind> (\<lambda> (mode :: SATPMode) .  
+  (case  mode of
+        Sbare => return (TR_Address vAddr)
+    | SV39 =>
+  translate39
+    ((subrange_vec_dec vAddr (( 38 :: int):: ii) (( 0 :: int):: ii) :: 39 Word.word))
+    ac effPriv mxr do_sum ((SV39_LEVELS - (( 1 :: int):: ii))) \<bind>
+    (\<lambda> (w__7 :: TR39_Result) . 
+     return
+       ((case  w__7 of
+              TR39_Address (pa) => TR_Address
+                                     ((EXTZ (( 64 :: int):: ii) pa :: 64 Word.word))
+          | TR39_Failure (f) => TR_Failure ((translationException ac f))
+        )))
+  ))))))))"
+
+
+(*val decode : mword ty32 -> maybe ast*)
+
+(*val decodeCompressed : mword ty16 -> maybe ast*)
+
+(*val execute : ast -> M bool*)
+
+(*val print_insn : ast -> string*)
+
+(*val encdec_uop_forwards : uop -> mword ty7*)
+
+fun encdec_uop_forwards  :: " uop \<Rightarrow>(7)Word.word "  where 
+     " encdec_uop_forwards RISCV_LUI = ( (vec_of_bits [B0,B1,B1,B0,B1,B1,B1]  ::  7 Word.word))"
+|" encdec_uop_forwards RISCV_AUIPC = ( (vec_of_bits [B0,B0,B1,B0,B1,B1,B1]  ::  7 Word.word))"
+
+
+(*val encdec_uop_backwards : mword ty7 -> uop*)
+
+definition encdec_uop_backwards  :: "(7)Word.word \<Rightarrow> uop "  where 
+     " encdec_uop_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1]  ::  7 Word.word)))) then RISCV_LUI
+   else RISCV_AUIPC))"
+
+
+(*val encdec_uop_forwards_matches : uop -> bool*)
+
+fun encdec_uop_forwards_matches  :: " uop \<Rightarrow> bool "  where 
+     " encdec_uop_forwards_matches RISCV_LUI = ( True )"
+|" encdec_uop_forwards_matches RISCV_AUIPC = ( True )"
+
+
+(*val encdec_uop_backwards_matches : mword ty7 -> bool*)
+
+definition encdec_uop_backwards_matches  :: "(7)Word.word \<Rightarrow> bool "  where 
+     " encdec_uop_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1]  ::  7 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1]  ::  7 Word.word)))) then True
+   else False))"
+
+
+(*val utype_mnemonic_forwards : uop -> string*)
+
+fun utype_mnemonic_forwards  :: " uop \<Rightarrow> string "  where 
+     " utype_mnemonic_forwards RISCV_LUI = ( (''lui''))"
+|" utype_mnemonic_forwards RISCV_AUIPC = ( (''auipc''))"
+
+
+(*val utype_mnemonic_backwards : string -> uop*)
+
+definition utype_mnemonic_backwards  :: " string \<Rightarrow> uop "  where 
+     " utype_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''lui'')) then RISCV_LUI else
+    (if(arg0 = (''auipc'')) then RISCV_AUIPC else undefined) )"
+
+
+(*val utype_mnemonic_forwards_matches : uop -> bool*)
+
+fun utype_mnemonic_forwards_matches  :: " uop \<Rightarrow> bool "  where 
+     " utype_mnemonic_forwards_matches RISCV_LUI = ( True )"
+|" utype_mnemonic_forwards_matches RISCV_AUIPC = ( True )"
+
+
+(*val utype_mnemonic_backwards_matches : string -> bool*)
+
+definition utype_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " utype_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''lui'')) then True else
+    (if(arg0 = (''auipc'')) then True else False) )"
+
+
+(*val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))*)
+
+definition utype_mnemonic_matches_prefix  :: " string \<Rightarrow>(uop*int)option "  where 
+     " utype_mnemonic_matches_prefix arg0 = (
+   (let stringappend_17140 = arg0 in
+   if (((((string_startswith stringappend_17140 (''lui''))) \<and> (
+  (case  ((string_drop stringappend_17140 ((string_length (''lui''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17140 ((string_length (''lui''))))) of
+       s0 => Some (RISCV_LUI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17140 (''auipc''))) \<and> (
+  (case  ((string_drop stringappend_17140 ((string_length (''auipc''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17140 ((string_length (''auipc''))))) of
+       s0 => Some (RISCV_AUIPC, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val encdec_bop_forwards : bop -> mword ty3*)
+
+fun encdec_bop_forwards  :: " bop \<Rightarrow>(3)Word.word "  where 
+     " encdec_bop_forwards RISCV_BEQ = ( (vec_of_bits [B0,B0,B0]  ::  3 Word.word))"
+|" encdec_bop_forwards RISCV_BNE = ( (vec_of_bits [B0,B0,B1]  ::  3 Word.word))"
+|" encdec_bop_forwards RISCV_BLT = ( (vec_of_bits [B1,B0,B0]  ::  3 Word.word))"
+|" encdec_bop_forwards RISCV_BGE = ( (vec_of_bits [B1,B0,B1]  ::  3 Word.word))"
+|" encdec_bop_forwards RISCV_BLTU = ( (vec_of_bits [B1,B1,B0]  ::  3 Word.word))"
+|" encdec_bop_forwards RISCV_BGEU = ( (vec_of_bits [B1,B1,B1]  ::  3 Word.word))"
+
+
+(*val encdec_bop_backwards : mword ty3 -> bop*)
+
+definition encdec_bop_backwards  :: "(3)Word.word \<Rightarrow> bop "  where 
+     " encdec_bop_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then RISCV_BEQ
+   else if (((p00 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) then RISCV_BNE
+   else if (((p00 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) then RISCV_BLT
+   else if (((p00 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) then RISCV_BGE
+   else if (((p00 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) then RISCV_BLTU
+   else RISCV_BGEU))"
+
+
+(*val encdec_bop_forwards_matches : bop -> bool*)
+
+fun encdec_bop_forwards_matches  :: " bop \<Rightarrow> bool "  where 
+     " encdec_bop_forwards_matches RISCV_BEQ = ( True )"
+|" encdec_bop_forwards_matches RISCV_BNE = ( True )"
+|" encdec_bop_forwards_matches RISCV_BLT = ( True )"
+|" encdec_bop_forwards_matches RISCV_BGE = ( True )"
+|" encdec_bop_forwards_matches RISCV_BLTU = ( True )"
+|" encdec_bop_forwards_matches RISCV_BGEU = ( True )"
+
+
+(*val encdec_bop_backwards_matches : mword ty3 -> bool*)
+
+definition encdec_bop_backwards_matches  :: "(3)Word.word \<Rightarrow> bool "  where 
+     " encdec_bop_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) then True
+   else False))"
+
+
+(*val btype_mnemonic_forwards : bop -> string*)
+
+fun btype_mnemonic_forwards  :: " bop \<Rightarrow> string "  where 
+     " btype_mnemonic_forwards RISCV_BEQ = ( (''beq''))"
+|" btype_mnemonic_forwards RISCV_BNE = ( (''bne''))"
+|" btype_mnemonic_forwards RISCV_BLT = ( (''blt''))"
+|" btype_mnemonic_forwards RISCV_BGE = ( (''bge''))"
+|" btype_mnemonic_forwards RISCV_BLTU = ( (''bltu''))"
+|" btype_mnemonic_forwards RISCV_BGEU = ( (''bgeu''))"
+
+
+(*val btype_mnemonic_backwards : string -> bop*)
+
+definition btype_mnemonic_backwards  :: " string \<Rightarrow> bop "  where 
+     " btype_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''beq'')) then RISCV_BEQ else
+    (
+    if(arg0 = (''bne'')) then RISCV_BNE else
+      (
+      if(arg0 = (''blt'')) then RISCV_BLT else
+        (
+        if(arg0 = (''bge'')) then RISCV_BGE else
+          (
+          if(arg0 = (''bltu'')) then RISCV_BLTU else
+            (if(arg0 = (''bgeu'')) then RISCV_BGEU else undefined))))) )"
+
+
+(*val btype_mnemonic_forwards_matches : bop -> bool*)
+
+fun btype_mnemonic_forwards_matches  :: " bop \<Rightarrow> bool "  where 
+     " btype_mnemonic_forwards_matches RISCV_BEQ = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BNE = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BLT = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BGE = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BLTU = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BGEU = ( True )"
+
+
+(*val btype_mnemonic_backwards_matches : string -> bool*)
+
+definition btype_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " btype_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''beq'')) then True else
+    (
+    if(arg0 = (''bne'')) then True else
+      (
+      if(arg0 = (''blt'')) then True else
+        (
+        if(arg0 = (''bge'')) then True else
+          (
+          if(arg0 = (''bltu'')) then True else
+            (if(arg0 = (''bgeu'')) then True else False))))) )"
+
+
+(*val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))*)
+
+definition btype_mnemonic_matches_prefix  :: " string \<Rightarrow>(bop*int)option "  where 
+     " btype_mnemonic_matches_prefix arg0 = (
+   (let stringappend_17080 = arg0 in
+   if (((((string_startswith stringappend_17080 (''beq''))) \<and> (
+  (case  ((string_drop stringappend_17080 ((string_length (''beq''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17080 ((string_length (''beq''))))) of
+       s0 => Some (RISCV_BEQ, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17080 (''bne''))) \<and> (
+  (case  ((string_drop stringappend_17080 ((string_length (''bne''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17080 ((string_length (''bne''))))) of
+       s0 => Some (RISCV_BNE, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17080 (''blt''))) \<and> (
+  (case  ((string_drop stringappend_17080 ((string_length (''blt''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17080 ((string_length (''blt''))))) of
+       s0 => Some (RISCV_BLT, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17080 (''bge''))) \<and> (
+  (case  ((string_drop stringappend_17080 ((string_length (''bge''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17080 ((string_length (''bge''))))) of
+       s0 => Some (RISCV_BGE, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17080 (''bltu''))) \<and> (
+  (case  ((string_drop stringappend_17080 ((string_length (''bltu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17080 ((string_length (''bltu''))))) of
+       s0 => Some (RISCV_BLTU, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17080 (''bgeu''))) \<and> (
+  (case  ((string_drop stringappend_17080 ((string_length (''bgeu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17080 ((string_length (''bgeu''))))) of
+       s0 => Some (RISCV_BGEU, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val encdec_iop_forwards : iop -> mword ty3*)
+
+fun encdec_iop_forwards  :: " iop \<Rightarrow>(3)Word.word "  where 
+     " encdec_iop_forwards RISCV_ADDI = ( (vec_of_bits [B0,B0,B0]  ::  3 Word.word))"
+|" encdec_iop_forwards RISCV_SLTI = ( (vec_of_bits [B0,B1,B0]  ::  3 Word.word))"
+|" encdec_iop_forwards RISCV_SLTIU = ( (vec_of_bits [B0,B1,B1]  ::  3 Word.word))"
+|" encdec_iop_forwards RISCV_XORI = ( (vec_of_bits [B1,B0,B0]  ::  3 Word.word))"
+|" encdec_iop_forwards RISCV_ORI = ( (vec_of_bits [B1,B1,B0]  ::  3 Word.word))"
+|" encdec_iop_forwards RISCV_ANDI = ( (vec_of_bits [B1,B1,B1]  ::  3 Word.word))"
+
+
+(*val encdec_iop_backwards : mword ty3 -> iop*)
+
+definition encdec_iop_backwards  :: "(3)Word.word \<Rightarrow> iop "  where 
+     " encdec_iop_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then RISCV_ADDI
+   else if (((p00 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) then RISCV_SLTI
+   else if (((p00 = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) then RISCV_SLTIU
+   else if (((p00 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) then RISCV_XORI
+   else if (((p00 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) then RISCV_ORI
+   else RISCV_ANDI))"
+
+
+(*val encdec_iop_forwards_matches : iop -> bool*)
+
+fun encdec_iop_forwards_matches  :: " iop \<Rightarrow> bool "  where 
+     " encdec_iop_forwards_matches RISCV_ADDI = ( True )"
+|" encdec_iop_forwards_matches RISCV_SLTI = ( True )"
+|" encdec_iop_forwards_matches RISCV_SLTIU = ( True )"
+|" encdec_iop_forwards_matches RISCV_XORI = ( True )"
+|" encdec_iop_forwards_matches RISCV_ORI = ( True )"
+|" encdec_iop_forwards_matches RISCV_ANDI = ( True )"
+
+
+(*val encdec_iop_backwards_matches : mword ty3 -> bool*)
+
+definition encdec_iop_backwards_matches  :: "(3)Word.word \<Rightarrow> bool "  where 
+     " encdec_iop_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) then True
+   else False))"
+
+
+(*val itype_mnemonic_forwards : iop -> string*)
+
+fun itype_mnemonic_forwards  :: " iop \<Rightarrow> string "  where 
+     " itype_mnemonic_forwards RISCV_ADDI = ( (''addi''))"
+|" itype_mnemonic_forwards RISCV_SLTI = ( (''slti''))"
+|" itype_mnemonic_forwards RISCV_SLTIU = ( (''sltiu''))"
+|" itype_mnemonic_forwards RISCV_XORI = ( (''xori''))"
+|" itype_mnemonic_forwards RISCV_ORI = ( (''ori''))"
+|" itype_mnemonic_forwards RISCV_ANDI = ( (''andi''))"
+
+
+(*val itype_mnemonic_backwards : string -> iop*)
+
+definition itype_mnemonic_backwards  :: " string \<Rightarrow> iop "  where 
+     " itype_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''addi'')) then RISCV_ADDI else
+    (
+    if(arg0 = (''slti'')) then RISCV_SLTI else
+      (
+      if(arg0 = (''sltiu'')) then RISCV_SLTIU else
+        (
+        if(arg0 = (''xori'')) then RISCV_XORI else
+          (
+          if(arg0 = (''ori'')) then RISCV_ORI else
+            (if(arg0 = (''andi'')) then RISCV_ANDI else undefined))))) )"
+
+
+(*val itype_mnemonic_forwards_matches : iop -> bool*)
+
+fun itype_mnemonic_forwards_matches  :: " iop \<Rightarrow> bool "  where 
+     " itype_mnemonic_forwards_matches RISCV_ADDI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_SLTI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_SLTIU = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_XORI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_ORI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_ANDI = ( True )"
+
+
+(*val itype_mnemonic_backwards_matches : string -> bool*)
+
+definition itype_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " itype_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''addi'')) then True else
+    (
+    if(arg0 = (''slti'')) then True else
+      (
+      if(arg0 = (''sltiu'')) then True else
+        (
+        if(arg0 = (''xori'')) then True else
+          (
+          if(arg0 = (''ori'')) then True else
+            (if(arg0 = (''andi'')) then True else False))))) )"
+
+
+(*val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))*)
+
+definition itype_mnemonic_matches_prefix  :: " string \<Rightarrow>(iop*int)option "  where 
+     " itype_mnemonic_matches_prefix arg0 = (
+   (let stringappend_17020 = arg0 in
+   if (((((string_startswith stringappend_17020 (''addi''))) \<and> (
+  (case  ((string_drop stringappend_17020 ((string_length (''addi''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17020 ((string_length (''addi''))))) of
+       s0 => Some (RISCV_ADDI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17020 (''slti''))) \<and> (
+  (case  ((string_drop stringappend_17020 ((string_length (''slti''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17020 ((string_length (''slti''))))) of
+       s0 => Some (RISCV_SLTI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17020 (''sltiu''))) \<and> (
+  (case  ((string_drop stringappend_17020 ((string_length (''sltiu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17020 ((string_length (''sltiu''))))) of
+       s0 => Some (RISCV_SLTIU, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17020 (''xori''))) \<and> (
+  (case  ((string_drop stringappend_17020 ((string_length (''xori''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17020 ((string_length (''xori''))))) of
+       s0 => Some (RISCV_XORI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17020 (''ori''))) \<and> (
+  (case  ((string_drop stringappend_17020 ((string_length (''ori''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17020 ((string_length (''ori''))))) of
+       s0 => Some (RISCV_ORI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_17020 (''andi''))) \<and> (
+  (case  ((string_drop stringappend_17020 ((string_length (''andi''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_17020 ((string_length (''andi''))))) of
+       s0 => Some (RISCV_ANDI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val encdec_sop_forwards : sop -> mword ty3*)
+
+fun encdec_sop_forwards  :: " sop \<Rightarrow>(3)Word.word "  where 
+     " encdec_sop_forwards RISCV_SLLI = ( (vec_of_bits [B0,B0,B1]  ::  3 Word.word))"
+|" encdec_sop_forwards RISCV_SRLI = ( (vec_of_bits [B1,B0,B1]  ::  3 Word.word))"
+|" encdec_sop_forwards RISCV_SRAI = ( (vec_of_bits [B1,B0,B1]  ::  3 Word.word))"
+
+
+(*val encdec_sop_backwards : mword ty3 -> sop*)
 
-definition translateAddr  :: "(64)Word.word \<Rightarrow> AccessType \<Rightarrow> ReadType \<Rightarrow>((register_value),(TR_Result),(exception))monad "  where 
-     " translateAddr vAddr ac rt = (
-   (case  rt of
-     Instruction => read_reg cur_privilege_ref
-   | Data =>
-      read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . 
-      if (((((get_Mstatus_MPRV w__1  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) then
-        read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . 
-        return ((privLevel_of_bits ((get_Mstatus_MPP w__2  ::  2 Word.word)))))
-      else read_reg cur_privilege_ref)
-   ) \<bind> (\<lambda> (effPriv :: Privilege) . 
-   read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) . 
-   (let (mxr :: bool) =
-     (((get_Mstatus_MXR w__5  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))) in
-   read_reg mstatus_ref \<bind> (\<lambda> (w__6 :: Mstatus) . 
-   (let (do_sum :: bool) =
-     (((get_Mstatus_SUM w__6  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))) in
-   translationMode effPriv \<bind> (\<lambda> (mode :: SATPMode) .  
-  (case  mode of
-        Sbare => return (TR_Address vAddr)
-    | SV39 =>
-  translate39
-    ((subrange_vec_dec vAddr (( 38 :: int):: ii) (( 0 :: int):: ii) :: 39 Word.word))
-    ac effPriv mxr do_sum ((SV39_LEVELS - (( 1 :: int):: ii))) \<bind>
-    (\<lambda> (w__7 :: TR39_Result) . 
-     return
-       ((case  w__7 of
-              TR39_Address (pa) => TR_Address
-                                     ((EXTZ (( 64 :: int):: ii) pa :: 64 Word.word))
-          | TR39_Failure (f) => TR_Failure ((translationException ac f))
-        )))
-  ))))))))"
+definition encdec_sop_backwards  :: "(3)Word.word \<Rightarrow> sop "  where 
+     " encdec_sop_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) then RISCV_SLLI
+   else if (((p00 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) then RISCV_SRLI
+   else RISCV_SRAI))"
 
 
-(*val decode : mword ty32 -> maybe ast*)
+(*val encdec_sop_forwards_matches : sop -> bool*)
 
-(*val decodeCompressed : mword ty16 -> maybe ast*)
+fun encdec_sop_forwards_matches  :: " sop \<Rightarrow> bool "  where 
+     " encdec_sop_forwards_matches RISCV_SLLI = ( True )"
+|" encdec_sop_forwards_matches RISCV_SRLI = ( True )"
+|" encdec_sop_forwards_matches RISCV_SRAI = ( True )"
 
-(*val execute : ast -> M unit*)
 
-(*val print_insn : ast -> string*)
+(*val encdec_sop_backwards_matches : mword ty3 -> bool*)
+
+definition encdec_sop_backwards_matches  :: "(3)Word.word \<Rightarrow> bool "  where 
+     " encdec_sop_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) then True
+   else False))"
+
+
+(*val shiftiop_mnemonic_forwards : sop -> string*)
+
+fun shiftiop_mnemonic_forwards  :: " sop \<Rightarrow> string "  where 
+     " shiftiop_mnemonic_forwards RISCV_SLLI = ( (''slli''))"
+|" shiftiop_mnemonic_forwards RISCV_SRLI = ( (''srli''))"
+|" shiftiop_mnemonic_forwards RISCV_SRAI = ( (''srai''))"
+
+
+(*val shiftiop_mnemonic_backwards : string -> sop*)
+
+definition shiftiop_mnemonic_backwards  :: " string \<Rightarrow> sop "  where 
+     " shiftiop_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''slli'')) then RISCV_SLLI else
+    (
+    if(arg0 = (''srli'')) then RISCV_SRLI else
+      (if(arg0 = (''srai'')) then RISCV_SRAI else undefined)) )"
+
+
+(*val shiftiop_mnemonic_forwards_matches : sop -> bool*)
+
+fun shiftiop_mnemonic_forwards_matches  :: " sop \<Rightarrow> bool "  where 
+     " shiftiop_mnemonic_forwards_matches RISCV_SLLI = ( True )"
+|" shiftiop_mnemonic_forwards_matches RISCV_SRLI = ( True )"
+|" shiftiop_mnemonic_forwards_matches RISCV_SRAI = ( True )"
+
+
+(*val shiftiop_mnemonic_backwards_matches : string -> bool*)
+
+definition shiftiop_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " shiftiop_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''slli'')) then True else
+    (
+    if(arg0 = (''srli'')) then True else
+      (if(arg0 = (''srai'')) then True else False)) )"
+
+
+(*val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+definition shiftiop_mnemonic_matches_prefix  :: " string \<Rightarrow>(sop*int)option "  where 
+     " shiftiop_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16990 = arg0 in
+   if (((((string_startswith stringappend_16990 (''slli''))) \<and> (
+  (case  ((string_drop stringappend_16990 ((string_length (''slli''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16990 ((string_length (''slli''))))) of
+       s0 => Some (RISCV_SLLI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16990 (''srli''))) \<and> (
+  (case  ((string_drop stringappend_16990 ((string_length (''srli''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16990 ((string_length (''srli''))))) of
+       s0 => Some (RISCV_SRLI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16990 (''srai''))) \<and> (
+  (case  ((string_drop stringappend_16990 ((string_length (''srai''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16990 ((string_length (''srai''))))) of
+       s0 => Some (RISCV_SRAI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val rtype_mnemonic_forwards : rop -> string*)
+
+fun rtype_mnemonic_forwards  :: " rop \<Rightarrow> string "  where 
+     " rtype_mnemonic_forwards RISCV_ADD = ( (''add''))"
+|" rtype_mnemonic_forwards RISCV_SUB = ( (''sub''))"
+|" rtype_mnemonic_forwards RISCV_SLL = ( (''sll''))"
+|" rtype_mnemonic_forwards RISCV_SLT = ( (''slt''))"
+|" rtype_mnemonic_forwards RISCV_SLTU = ( (''sltu''))"
+|" rtype_mnemonic_forwards RISCV_XOR = ( (''xor''))"
+|" rtype_mnemonic_forwards RISCV_SRL = ( (''srl''))"
+|" rtype_mnemonic_forwards RISCV_SRA = ( (''sra''))"
+|" rtype_mnemonic_forwards RISCV_OR = ( (''or''))"
+|" rtype_mnemonic_forwards RISCV_AND = ( (''and''))"
+
+
+(*val rtype_mnemonic_backwards : string -> rop*)
+
+definition rtype_mnemonic_backwards  :: " string \<Rightarrow> rop "  where 
+     " rtype_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''add'')) then RISCV_ADD else
+    (
+    if(arg0 = (''sub'')) then RISCV_SUB else
+      (
+      if(arg0 = (''sll'')) then RISCV_SLL else
+        (
+        if(arg0 = (''slt'')) then RISCV_SLT else
+          (
+          if(arg0 = (''sltu'')) then RISCV_SLTU else
+            (
+            if(arg0 = (''xor'')) then RISCV_XOR else
+              (
+              if(arg0 = (''srl'')) then RISCV_SRL else
+                (
+                if(arg0 = (''sra'')) then RISCV_SRA else
+                  (
+                  if(arg0 = (''or'')) then RISCV_OR else
+                    (if(arg0 = (''and'')) then RISCV_AND else undefined))))))))) )"
+
+
+(*val rtype_mnemonic_forwards_matches : rop -> bool*)
+
+fun rtype_mnemonic_forwards_matches  :: " rop \<Rightarrow> bool "  where 
+     " rtype_mnemonic_forwards_matches RISCV_ADD = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SUB = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLL = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLT = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLTU = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_XOR = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SRL = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SRA = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_OR = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_AND = ( True )"
+
+
+(*val rtype_mnemonic_backwards_matches : string -> bool*)
+
+definition rtype_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " rtype_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''add'')) then True else
+    (
+    if(arg0 = (''sub'')) then True else
+      (
+      if(arg0 = (''sll'')) then True else
+        (
+        if(arg0 = (''slt'')) then True else
+          (
+          if(arg0 = (''sltu'')) then True else
+            (
+            if(arg0 = (''xor'')) then True else
+              (
+              if(arg0 = (''srl'')) then True else
+                (
+                if(arg0 = (''sra'')) then True else
+                  (
+                  if(arg0 = (''or'')) then True else
+                    (if(arg0 = (''and'')) then True else False))))))))) )"
+
+
+(*val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))*)
+
+definition rtype_mnemonic_matches_prefix  :: " string \<Rightarrow>(rop*int)option "  where 
+     " rtype_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16890 = arg0 in
+   if (((((string_startswith stringappend_16890 (''add''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''add''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''add''))))) of
+       s0 => Some (RISCV_ADD, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''sub''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''sub''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''sub''))))) of
+       s0 => Some (RISCV_SUB, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''sll''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''sll''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''sll''))))) of
+       s0 => Some (RISCV_SLL, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''slt''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''slt''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''slt''))))) of
+       s0 => Some (RISCV_SLT, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''sltu''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''sltu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''sltu''))))) of
+       s0 => Some (RISCV_SLTU, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''xor''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''xor''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''xor''))))) of
+       s0 => Some (RISCV_XOR, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''srl''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''srl''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''srl''))))) of
+       s0 => Some (RISCV_SRL, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''sra''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''sra''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''sra''))))) of
+       s0 => Some (RISCV_SRA, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''or''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''or''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''or''))))) of
+       s0 => Some (RISCV_OR, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16890 (''and''))) \<and> (
+  (case  ((string_drop stringappend_16890 ((string_length (''and''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16890 ((string_length (''and''))))) of
+       s0 => Some (RISCV_AND, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
 
 (*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*)
 
@@ -5261,97 +11093,1344 @@ fun extend_value  :: " bool \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOp
 |" extend_value is_unsigned (MemException (e)) = ( MemException e )"
 
 
-(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*)
+(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*)
+
+definition process_load  :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " process_load rd addr value1 is_unsigned = (
+   (case  ((extend_value is_unsigned value1  :: ( 64 Word.word) MemoryOpResult)) of
+     MemValue (result) => wX ((regbits_to_regno rd)) result \<then> return True
+   | MemException (e) => handle_mem_exception addr e \<then> return False
+   ))"
+
+
+(*val check_misaligned : mword ty64 -> word_width -> bool*)
+
+definition check_misaligned  :: "(64)Word.word \<Rightarrow> word_width \<Rightarrow> bool "  where 
+     " check_misaligned (vaddr :: xlenbits) (width :: word_width) = (
+   if ((plat_enable_misaligned_access () )) then False
+   else
+     (case  width of
+       BYTE => False
+     | HALF =>
+        (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))
+     | WORD =>
+        ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> (((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))))
+     | DOUBLE =>
+        ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> ((((((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) \<or> (((((cast_unit_vec0 ((access_vec_dec vaddr (( 2 :: int)::ii)))  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word)))))))))
+     ))"
+
+
+(*val maybe_aq_forwards : bool -> string*)
+
+fun maybe_aq_forwards  :: " bool \<Rightarrow> string "  where 
+     " maybe_aq_forwards True = ( (''.aq''))"
+|" maybe_aq_forwards False = ( (''''))"
+
+
+(*val maybe_aq_backwards : string -> bool*)
+
+definition maybe_aq_backwards  :: " string \<Rightarrow> bool "  where 
+     " maybe_aq_backwards arg0 = ( 
+  if(arg0 = (''.aq'')) then True else
+    (if(arg0 = ('''')) then False else undefined) )"
+
+
+(*val maybe_aq_forwards_matches : bool -> bool*)
+
+fun maybe_aq_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " maybe_aq_forwards_matches True = ( True )"
+|" maybe_aq_forwards_matches False = ( True )"
+
+
+(*val maybe_aq_backwards_matches : string -> bool*)
+
+definition maybe_aq_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " maybe_aq_backwards_matches arg0 = ( 
+  if(arg0 = (''.aq'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val maybe_aq_matches_prefix : string -> maybe ((bool * ii))*)
+
+definition maybe_aq_matches_prefix  :: " string \<Rightarrow>(bool*int)option "  where 
+     " maybe_aq_matches_prefix arg0 = (
+   (let stringappend_16870 = arg0 in
+   if (((((string_startswith stringappend_16870 (''.aq''))) \<and> (
+  (case  ((string_drop stringappend_16870 ((string_length (''.aq''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16870 ((string_length (''.aq''))))) of
+       s0 => Some (True, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16870 (''''))) \<and> (
+  (case  ((string_drop stringappend_16870 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16870 ((string_length (''''))))) of
+       s0 => Some (False, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val maybe_rl_forwards : bool -> string*)
+
+fun maybe_rl_forwards  :: " bool \<Rightarrow> string "  where 
+     " maybe_rl_forwards True = ( (''.rl''))"
+|" maybe_rl_forwards False = ( (''''))"
+
+
+(*val maybe_rl_backwards : string -> bool*)
+
+definition maybe_rl_backwards  :: " string \<Rightarrow> bool "  where 
+     " maybe_rl_backwards arg0 = ( 
+  if(arg0 = (''.rl'')) then True else
+    (if(arg0 = ('''')) then False else undefined) )"
+
+
+(*val maybe_rl_forwards_matches : bool -> bool*)
+
+fun maybe_rl_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " maybe_rl_forwards_matches True = ( True )"
+|" maybe_rl_forwards_matches False = ( True )"
+
+
+(*val maybe_rl_backwards_matches : string -> bool*)
+
+definition maybe_rl_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " maybe_rl_backwards_matches arg0 = ( 
+  if(arg0 = (''.rl'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val maybe_rl_matches_prefix : string -> maybe ((bool * ii))*)
+
+definition maybe_rl_matches_prefix  :: " string \<Rightarrow>(bool*int)option "  where 
+     " maybe_rl_matches_prefix arg0 = (
+   (let stringappend_16850 = arg0 in
+   if (((((string_startswith stringappend_16850 (''.rl''))) \<and> (
+  (case  ((string_drop stringappend_16850 ((string_length (''.rl''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16850 ((string_length (''.rl''))))) of
+       s0 => Some (True, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16850 (''''))) \<and> (
+  (case  ((string_drop stringappend_16850 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16850 ((string_length (''''))))) of
+       s0 => Some (False, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val maybe_u_forwards : bool -> string*)
+
+fun maybe_u_forwards  :: " bool \<Rightarrow> string "  where 
+     " maybe_u_forwards True = ( (''u''))"
+|" maybe_u_forwards False = ( (''''))"
+
+
+(*val maybe_u_backwards : string -> bool*)
+
+definition maybe_u_backwards  :: " string \<Rightarrow> bool "  where 
+     " maybe_u_backwards arg0 = ( 
+  if(arg0 = (''u'')) then True else
+    (if(arg0 = ('''')) then False else undefined) )"
+
+
+(*val maybe_u_forwards_matches : bool -> bool*)
+
+fun maybe_u_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " maybe_u_forwards_matches True = ( True )"
+|" maybe_u_forwards_matches False = ( True )"
+
+
+(*val maybe_u_backwards_matches : string -> bool*)
+
+definition maybe_u_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " maybe_u_backwards_matches arg0 = ( 
+  if(arg0 = (''u'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val maybe_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+definition maybe_u_matches_prefix  :: " string \<Rightarrow>(bool*int)option "  where 
+     " maybe_u_matches_prefix arg0 = (
+   (let stringappend_16830 = arg0 in
+   if (((((string_startswith stringappend_16830 (''u''))) \<and> (
+  (case  ((string_drop stringappend_16830 ((string_length (''u''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16830 ((string_length (''u''))))) of
+       s0 => Some (True, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16830 (''''))) \<and> (
+  (case  ((string_drop stringappend_16830 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16830 ((string_length (''''))))) of
+       s0 => Some (False, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val shiftw_mnemonic_forwards : sop -> string*)
+
+fun shiftw_mnemonic_forwards  :: " sop \<Rightarrow> string "  where 
+     " shiftw_mnemonic_forwards RISCV_SLLI = ( (''slli''))"
+|" shiftw_mnemonic_forwards RISCV_SRLI = ( (''srli''))"
+|" shiftw_mnemonic_forwards RISCV_SRAI = ( (''srai''))"
+
+
+(*val shiftw_mnemonic_backwards : string -> sop*)
+
+definition shiftw_mnemonic_backwards  :: " string \<Rightarrow> sop "  where 
+     " shiftw_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''slli'')) then RISCV_SLLI else
+    (
+    if(arg0 = (''srli'')) then RISCV_SRLI else
+      (if(arg0 = (''srai'')) then RISCV_SRAI else undefined)) )"
+
+
+(*val shiftw_mnemonic_forwards_matches : sop -> bool*)
+
+fun shiftw_mnemonic_forwards_matches  :: " sop \<Rightarrow> bool "  where 
+     " shiftw_mnemonic_forwards_matches RISCV_SLLI = ( True )"
+|" shiftw_mnemonic_forwards_matches RISCV_SRLI = ( True )"
+|" shiftw_mnemonic_forwards_matches RISCV_SRAI = ( True )"
+
+
+(*val shiftw_mnemonic_backwards_matches : string -> bool*)
+
+definition shiftw_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " shiftw_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''slli'')) then True else
+    (
+    if(arg0 = (''srli'')) then True else
+      (if(arg0 = (''srai'')) then True else False)) )"
+
+
+(*val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+definition shiftw_mnemonic_matches_prefix  :: " string \<Rightarrow>(sop*int)option "  where 
+     " shiftw_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16800 = arg0 in
+   if (((((string_startswith stringappend_16800 (''slli''))) \<and> (
+  (case  ((string_drop stringappend_16800 ((string_length (''slli''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16800 ((string_length (''slli''))))) of
+       s0 => Some (RISCV_SLLI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16800 (''srli''))) \<and> (
+  (case  ((string_drop stringappend_16800 ((string_length (''srli''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16800 ((string_length (''srli''))))) of
+       s0 => Some (RISCV_SRLI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16800 (''srai''))) \<and> (
+  (case  ((string_drop stringappend_16800 ((string_length (''srai''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16800 ((string_length (''srai''))))) of
+       s0 => Some (RISCV_SRAI, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val rtypew_mnemonic_forwards : ropw -> string*)
+
+fun rtypew_mnemonic_forwards  :: " ropw \<Rightarrow> string "  where 
+     " rtypew_mnemonic_forwards RISCV_ADDW = ( (''addw''))"
+|" rtypew_mnemonic_forwards RISCV_SUBW = ( (''subw''))"
+|" rtypew_mnemonic_forwards RISCV_SLLW = ( (''sllw''))"
+|" rtypew_mnemonic_forwards RISCV_SRLW = ( (''srlw''))"
+|" rtypew_mnemonic_forwards RISCV_SRAW = ( (''sraw''))"
+
+
+(*val rtypew_mnemonic_backwards : string -> ropw*)
+
+definition rtypew_mnemonic_backwards  :: " string \<Rightarrow> ropw "  where 
+     " rtypew_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''addw'')) then RISCV_ADDW else
+    (
+    if(arg0 = (''subw'')) then RISCV_SUBW else
+      (
+      if(arg0 = (''sllw'')) then RISCV_SLLW else
+        (
+        if(arg0 = (''srlw'')) then RISCV_SRLW else
+          (if(arg0 = (''sraw'')) then RISCV_SRAW else undefined)))) )"
+
+
+(*val rtypew_mnemonic_forwards_matches : ropw -> bool*)
+
+fun rtypew_mnemonic_forwards_matches  :: " ropw \<Rightarrow> bool "  where 
+     " rtypew_mnemonic_forwards_matches RISCV_ADDW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SUBW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SLLW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SRLW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SRAW = ( True )"
+
+
+(*val rtypew_mnemonic_backwards_matches : string -> bool*)
+
+definition rtypew_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " rtypew_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''addw'')) then True else
+    (
+    if(arg0 = (''subw'')) then True else
+      (
+      if(arg0 = (''sllw'')) then True else
+        (
+        if(arg0 = (''srlw'')) then True else
+          (if(arg0 = (''sraw'')) then True else False)))) )"
+
+
+(*val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))*)
+
+definition rtypew_mnemonic_matches_prefix  :: " string \<Rightarrow>(ropw*int)option "  where 
+     " rtypew_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16750 = arg0 in
+   if (((((string_startswith stringappend_16750 (''addw''))) \<and> (
+  (case  ((string_drop stringappend_16750 ((string_length (''addw''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16750 ((string_length (''addw''))))) of
+       s0 => Some (RISCV_ADDW, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16750 (''subw''))) \<and> (
+  (case  ((string_drop stringappend_16750 ((string_length (''subw''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16750 ((string_length (''subw''))))) of
+       s0 => Some (RISCV_SUBW, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16750 (''sllw''))) \<and> (
+  (case  ((string_drop stringappend_16750 ((string_length (''sllw''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16750 ((string_length (''sllw''))))) of
+       s0 => Some (RISCV_SLLW, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16750 (''srlw''))) \<and> (
+  (case  ((string_drop stringappend_16750 ((string_length (''srlw''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16750 ((string_length (''srlw''))))) of
+       s0 => Some (RISCV_SRLW, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16750 (''sraw''))) \<and> (
+  (case  ((string_drop stringappend_16750 ((string_length (''sraw''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16750 ((string_length (''sraw''))))) of
+       s0 => Some (RISCV_SRAW, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val encdec_mul_op_forwards : bool -> bool -> bool -> mword ty3*)
+
+definition encdec_mul_op_forwards  :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(3)Word.word "  where 
+     " encdec_mul_op_forwards arg0 arg1 arg2 = (
+   (let arg0 = (arg0, arg1, arg2) in
+   (case  arg0 of
+     (False, True, True) => (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+   | (True, True, True) => (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+   | (True, True, False) => (vec_of_bits [B0,B1,B0]  ::  3 Word.word)
+   | (True, False, False) => (vec_of_bits [B0,B1,B1]  ::  3 Word.word)
+   )))"
+
+
+(*val encdec_mul_op_backwards : mword ty3 -> (bool * bool * bool)*)
+
+definition encdec_mul_op_backwards  :: "(3)Word.word \<Rightarrow> bool*bool*bool "  where 
+     " encdec_mul_op_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then (False, True, True)
+   else if (((p00 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) then (True, True, True)
+   else if (((p00 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) then (True, True, False)
+   else (True, False, False)))"
+
+
+(*val encdec_mul_op_forwards_matches : bool -> bool -> bool -> bool*)
+
+definition encdec_mul_op_forwards_matches  :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool "  where 
+     " encdec_mul_op_forwards_matches arg0 arg1 arg2 = (
+   (let arg0 = (arg0, arg1, arg2) in
+   (case  arg0 of
+     (False, True, True) => True
+   | (True, True, True) => True
+   | (True, True, False) => True
+   | (True, False, False) => True
+   | _ => False
+   )))"
+
+
+(*val encdec_mul_op_backwards_matches : mword ty3 -> bool*)
+
+definition encdec_mul_op_backwards_matches  :: "(3)Word.word \<Rightarrow> bool "  where 
+     " encdec_mul_op_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) then True
+   else False))"
+
+
+(*val mul_mnemonic_forwards : bool -> bool -> bool -> string*)
+
+definition mul_mnemonic_forwards  :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> string "  where 
+     " mul_mnemonic_forwards arg0 arg1 arg2 = (
+   (let arg0 = (arg0, arg1, arg2) in
+   (case  arg0 of
+     (False, True, True) => (''mul'')
+   | (True, True, True) => (''mulh'')
+   | (True, True, False) => (''mulhsu'')
+   | (True, False, False) => (''mulhu'')
+   )))"
+
+
+(*val mul_mnemonic_backwards : string -> (bool * bool * bool)*)
+
+definition mul_mnemonic_backwards  :: " string \<Rightarrow> bool*bool*bool "  where 
+     " mul_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''mul'')) then (False, True, True) else
+    (
+    if(arg0 = (''mulh'')) then (True, True, True) else
+      (
+      if(arg0 = (''mulhsu'')) then (True, True, False) else
+        (if(arg0 = (''mulhu'')) then (True, False, False) else undefined))) )"
+
+
+(*val mul_mnemonic_forwards_matches : bool -> bool -> bool -> bool*)
+
+definition mul_mnemonic_forwards_matches  :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool "  where 
+     " mul_mnemonic_forwards_matches arg0 arg1 arg2 = (
+   (let arg0 = (arg0, arg1, arg2) in
+   (case  arg0 of
+     (False, True, True) => True
+   | (True, True, True) => True
+   | (True, True, False) => True
+   | (True, False, False) => True
+   | _ => False
+   )))"
+
+
+(*val mul_mnemonic_backwards_matches : string -> bool*)
+
+definition mul_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " mul_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''mul'')) then True else
+    (
+    if(arg0 = (''mulh'')) then True else
+      (
+      if(arg0 = (''mulhsu'')) then True else
+        (if(arg0 = (''mulhu'')) then True else False))) )"
+
+
+(*val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))*)
+
+definition mul_mnemonic_matches_prefix  :: " string \<Rightarrow>((bool*bool*bool)*int)option "  where 
+     " mul_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16710 = arg0 in
+   if (((((string_startswith stringappend_16710 (''mul''))) \<and> (
+  (case  ((string_drop stringappend_16710 ((string_length (''mul''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16710 ((string_length (''mul''))))) of
+       s0 => Some ((False, True, True), ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16710 (''mulh''))) \<and> (
+  (case  ((string_drop stringappend_16710 ((string_length (''mulh''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16710 ((string_length (''mulh''))))) of
+       s0 => Some ((True, True, True), ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16710 (''mulhsu''))) \<and> (
+  (case  ((string_drop stringappend_16710 ((string_length (''mulhsu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16710 ((string_length (''mulhsu''))))) of
+       s0 => Some ((True, True, False), ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16710 (''mulhu''))) \<and> (
+  (case  ((string_drop stringappend_16710 ((string_length (''mulhu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16710 ((string_length (''mulhu''))))) of
+       s0 => Some ((True, False, False), ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val maybe_not_u_forwards : bool -> string*)
+
+fun maybe_not_u_forwards  :: " bool \<Rightarrow> string "  where 
+     " maybe_not_u_forwards False = ( (''u''))"
+|" maybe_not_u_forwards True = ( (''''))"
+
+
+(*val maybe_not_u_backwards : string -> bool*)
+
+definition maybe_not_u_backwards  :: " string \<Rightarrow> bool "  where 
+     " maybe_not_u_backwards arg0 = ( 
+  if(arg0 = (''u'')) then False else
+    (if(arg0 = ('''')) then True else undefined) )"
+
+
+(*val maybe_not_u_forwards_matches : bool -> bool*)
+
+fun maybe_not_u_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " maybe_not_u_forwards_matches False = ( True )"
+|" maybe_not_u_forwards_matches True = ( True )"
+
+
+(*val maybe_not_u_backwards_matches : string -> bool*)
+
+definition maybe_not_u_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " maybe_not_u_backwards_matches arg0 = ( 
+  if(arg0 = (''u'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+definition maybe_not_u_matches_prefix  :: " string \<Rightarrow>(bool*int)option "  where 
+     " maybe_not_u_matches_prefix arg0 = (
+   (let stringappend_16690 = arg0 in
+   if (((((string_startswith stringappend_16690 (''u''))) \<and> (
+  (case  ((string_drop stringappend_16690 ((string_length (''u''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16690 ((string_length (''u''))))) of
+       s0 => Some (False, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16690 (''''))) \<and> (
+  (case  ((string_drop stringappend_16690 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16690 ((string_length (''''))))) of
+       s0 => Some (True, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val bit_maybe_r_forwards : mword ty1 -> string*)
+
+definition bit_maybe_r_forwards  :: "(1)Word.word \<Rightarrow> string "  where 
+     " bit_maybe_r_forwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then (''r'')
+   else ('''')))"
+
+
+(*val bit_maybe_r_backwards : string -> mword ty1*)
+
+definition bit_maybe_r_backwards  :: " string \<Rightarrow>(1)Word.word "  where 
+     " bit_maybe_r_backwards arg0 = ( 
+  if(arg0 = (''r'')) then ((vec_of_bits [B1] :: 1 Word.word)) else
+    (
+    if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )"
+
+
+(*val bit_maybe_r_forwards_matches : mword ty1 -> bool*)
+
+definition bit_maybe_r_forwards_matches  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bit_maybe_r_forwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else False))"
+
+
+(*val bit_maybe_r_backwards_matches : string -> bool*)
+
+definition bit_maybe_r_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " bit_maybe_r_backwards_matches arg0 = ( 
+  if(arg0 = (''r'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+definition bit_maybe_r_matches_prefix  :: " string \<Rightarrow>((1)Word.word*int)option "  where 
+     " bit_maybe_r_matches_prefix arg0 = (
+   (let stringappend_16670 = arg0 in
+   if (((((string_startswith stringappend_16670 (''r''))) \<and> (
+  (case  ((string_drop stringappend_16670 ((string_length (''r''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16670 ((string_length (''r''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16670 (''''))) \<and> (
+  (case  ((string_drop stringappend_16670 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16670 ((string_length (''''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val bit_maybe_w_forwards : mword ty1 -> string*)
+
+definition bit_maybe_w_forwards  :: "(1)Word.word \<Rightarrow> string "  where 
+     " bit_maybe_w_forwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then (''w'')
+   else ('''')))"
+
+
+(*val bit_maybe_w_backwards : string -> mword ty1*)
+
+definition bit_maybe_w_backwards  :: " string \<Rightarrow>(1)Word.word "  where 
+     " bit_maybe_w_backwards arg0 = ( 
+  if(arg0 = (''w'')) then ((vec_of_bits [B1] :: 1 Word.word)) else
+    (
+    if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )"
+
+
+(*val bit_maybe_w_forwards_matches : mword ty1 -> bool*)
+
+definition bit_maybe_w_forwards_matches  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bit_maybe_w_forwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else False))"
+
+
+(*val bit_maybe_w_backwards_matches : string -> bool*)
+
+definition bit_maybe_w_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " bit_maybe_w_backwards_matches arg0 = ( 
+  if(arg0 = (''w'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+definition bit_maybe_w_matches_prefix  :: " string \<Rightarrow>((1)Word.word*int)option "  where 
+     " bit_maybe_w_matches_prefix arg0 = (
+   (let stringappend_16650 = arg0 in
+   if (((((string_startswith stringappend_16650 (''w''))) \<and> (
+  (case  ((string_drop stringappend_16650 ((string_length (''w''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16650 ((string_length (''w''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16650 (''''))) \<and> (
+  (case  ((string_drop stringappend_16650 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16650 ((string_length (''''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val bit_maybe_i_forwards : mword ty1 -> string*)
+
+definition bit_maybe_i_forwards  :: "(1)Word.word \<Rightarrow> string "  where 
+     " bit_maybe_i_forwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then (''i'')
+   else ('''')))"
+
+
+(*val bit_maybe_i_backwards : string -> mword ty1*)
+
+definition bit_maybe_i_backwards  :: " string \<Rightarrow>(1)Word.word "  where 
+     " bit_maybe_i_backwards arg0 = ( 
+  if(arg0 = (''i'')) then ((vec_of_bits [B1] :: 1 Word.word)) else
+    (
+    if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )"
+
+
+(*val bit_maybe_i_forwards_matches : mword ty1 -> bool*)
+
+definition bit_maybe_i_forwards_matches  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bit_maybe_i_forwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else False))"
+
+
+(*val bit_maybe_i_backwards_matches : string -> bool*)
+
+definition bit_maybe_i_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " bit_maybe_i_backwards_matches arg0 = ( 
+  if(arg0 = (''i'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+definition bit_maybe_i_matches_prefix  :: " string \<Rightarrow>((1)Word.word*int)option "  where 
+     " bit_maybe_i_matches_prefix arg0 = (
+   (let stringappend_16630 = arg0 in
+   if (((((string_startswith stringappend_16630 (''i''))) \<and> (
+  (case  ((string_drop stringappend_16630 ((string_length (''i''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16630 ((string_length (''i''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16630 (''''))) \<and> (
+  (case  ((string_drop stringappend_16630 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16630 ((string_length (''''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val bit_maybe_o_forwards : mword ty1 -> string*)
+
+definition bit_maybe_o_forwards  :: "(1)Word.word \<Rightarrow> string "  where 
+     " bit_maybe_o_forwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then (''o'')
+   else ('''')))"
+
+
+(*val bit_maybe_o_backwards : string -> mword ty1*)
+
+definition bit_maybe_o_backwards  :: " string \<Rightarrow>(1)Word.word "  where 
+     " bit_maybe_o_backwards arg0 = ( 
+  if(arg0 = (''o'')) then ((vec_of_bits [B1] :: 1 Word.word)) else
+    (
+    if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )"
+
+
+(*val bit_maybe_o_forwards_matches : mword ty1 -> bool*)
+
+definition bit_maybe_o_forwards_matches  :: "(1)Word.word \<Rightarrow> bool "  where 
+     " bit_maybe_o_forwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B1]  ::  1 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then True
+   else False))"
+
+
+(*val bit_maybe_o_backwards_matches : string -> bool*)
+
+definition bit_maybe_o_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " bit_maybe_o_backwards_matches arg0 = ( 
+  if(arg0 = (''o'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+definition bit_maybe_o_matches_prefix  :: " string \<Rightarrow>((1)Word.word*int)option "  where 
+     " bit_maybe_o_matches_prefix arg0 = (
+   (let stringappend_16610 = arg0 in
+   if (((((string_startswith stringappend_16610 (''o''))) \<and> (
+  (case  ((string_drop stringappend_16610 ((string_length (''o''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16610 ((string_length (''o''))))) of
+       s0 =>
+        Some ((vec_of_bits [B1]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16610 (''''))) \<and> (
+  (case  ((string_drop stringappend_16610 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16610 ((string_length (''''))))) of
+       s0 =>
+        Some ((vec_of_bits [B0]  ::  1 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val fence_bits_forwards : mword ty4 -> string*)
+
+definition fence_bits_forwards  :: "(4)Word.word \<Rightarrow> string "  where 
+     " fence_bits_forwards v__0 = (
+      (let (r :: 1 bits) = ((subrange_vec_dec v__0 (( 3 :: int)::ii) (( 3 :: int)::ii)  ::  1 Word.word)) in
+      (let (w :: 1 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
+      (let (i :: 1 bits) = ((subrange_vec_dec v__0 (( 1 :: int)::ii) (( 1 :: int)::ii)  ::  1 Word.word)) in
+      (let (o1 :: 1 bits) = ((subrange_vec_dec v__0 (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word)) in
+      string_append ((bit_maybe_r_forwards r))
+        ((string_append ((bit_maybe_w_forwards w))
+            ((string_append ((bit_maybe_i_forwards i))
+                ((string_append ((bit_maybe_o_forwards o1)) (''''))))))))))))"
+
+
+(*val fence_bits_backwards : string -> mword ty4*)
+
+definition fence_bits_backwards  :: " string \<Rightarrow>(4)Word.word "  where 
+     " fence_bits_backwards arg0 = (
+   (let stringappend_16490 = arg0 in
+   (let (r, stringappend_16510) =
+     ((case  ((bit_maybe_r_matches_prefix stringappend_16490  ::  (( 1 Word.word * ii))option)) of
+       Some (stringappend_16500,stringappend_16510) => (stringappend_16500, stringappend_16510)
+     )) in
+   (let stringappend_16520 = (string_drop stringappend_16490 stringappend_16510) in
+   (let (w, stringappend_16540) =
+     ((case  ((bit_maybe_w_matches_prefix stringappend_16520  ::  (( 1 Word.word * ii))option)) of
+       Some (stringappend_16530,stringappend_16540) => (stringappend_16530, stringappend_16540)
+     )) in
+   (let stringappend_16550 = (string_drop stringappend_16520 stringappend_16540) in
+   (let (i, stringappend_16570) =
+     ((case  ((bit_maybe_i_matches_prefix stringappend_16550  ::  (( 1 Word.word * ii))option)) of
+       Some (stringappend_16560,stringappend_16570) => (stringappend_16560, stringappend_16570)
+     )) in
+   (let stringappend_16580 = (string_drop stringappend_16550 stringappend_16570) in
+   (let (o1, stringappend_16600) =
+     ((case  ((bit_maybe_o_matches_prefix stringappend_16580  ::  (( 1 Word.word * ii))option)) of
+       Some (stringappend_16590,stringappend_16600) => (stringappend_16590, stringappend_16600)
+     )) in  if(((string_drop stringappend_16580 stringappend_16600)) = ('''')) then
+   ((concat_vec r
+       ((concat_vec w ((concat_vec i o1 :: 2 Word.word)) :: 3 Word.word)) :: 4 Word.word))
+ else undefined)))))))))"
+
+
+(*val fence_bits_forwards_matches : mword ty4 -> bool*)
+
+definition fence_bits_forwards_matches  :: "(4)Word.word \<Rightarrow> bool "  where 
+     " fence_bits_forwards_matches v__1 = ( True )"
+
+
+(*val fence_bits_backwards_matches : string -> bool*)
+
+definition fence_bits_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " fence_bits_backwards_matches arg0 = (
+   (let stringappend_16370 = arg0 in
+   if ((case  ((bit_maybe_r_matches_prefix stringappend_16370  ::  (( 1 Word.word * ii))option)) of
+       Some (stringappend_16380,stringappend_16390) =>
+        (let stringappend_16400 = (string_drop stringappend_16370 stringappend_16390) in
+        if ((case  ((bit_maybe_w_matches_prefix stringappend_16400  ::  (( 1 Word.word * ii))option)) of
+            Some (stringappend_16410,stringappend_16420) =>
+             (let stringappend_16430 = (string_drop stringappend_16400 stringappend_16420) in
+             if ((case  ((bit_maybe_i_matches_prefix stringappend_16430  ::  (( 1 Word.word * ii))option)) of
+                 Some (stringappend_16440,stringappend_16450) =>
+                  (let stringappend_16460 = (string_drop stringappend_16430 stringappend_16450) in
+                  if ((case  ((bit_maybe_o_matches_prefix stringappend_16460
+                               ::  (( 1 Word.word * ii))option)) of
+                      Some (stringappend_16470,stringappend_16480) => 
+  if(((string_drop stringappend_16460 stringappend_16480)) = ('''')) then
+    True else False
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (r, stringappend_16390) =
+       ((case  ((bit_maybe_r_matches_prefix stringappend_16370  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16380,stringappend_16390) =>
+          (stringappend_16380, stringappend_16390)
+       )) in
+     (let stringappend_16400 = (string_drop stringappend_16370 stringappend_16390) in
+     (let (w, stringappend_16420) =
+       ((case  ((bit_maybe_w_matches_prefix stringappend_16400  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16410,stringappend_16420) =>
+          (stringappend_16410, stringappend_16420)
+       )) in
+     (let stringappend_16430 = (string_drop stringappend_16400 stringappend_16420) in
+     (let (i, stringappend_16450) =
+       ((case  ((bit_maybe_i_matches_prefix stringappend_16430  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16440,stringappend_16450) =>
+          (stringappend_16440, stringappend_16450)
+       )) in
+     (let stringappend_16460 = (string_drop stringappend_16430 stringappend_16450) in
+     (let (o1, stringappend_16480) =
+       ((case  ((bit_maybe_o_matches_prefix stringappend_16460  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16470,stringappend_16480) =>
+          (stringappend_16470, stringappend_16480)
+       )) in  if(((string_drop stringappend_16460 stringappend_16480)) = ('''')) then 
+ True else undefined)))))))
+   else False))"
+
+
+(*val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))*)
+
+definition fence_bits_matches_prefix  :: " string \<Rightarrow>((4)Word.word*int)option "  where 
+     " fence_bits_matches_prefix arg0 = (
+   (let stringappend_16250 = arg0 in
+   if ((case  ((bit_maybe_r_matches_prefix stringappend_16250  ::  (( 1 Word.word * ii))option)) of
+       Some (stringappend_16260,stringappend_16270) =>
+        (let stringappend_16280 = (string_drop stringappend_16250 stringappend_16270) in
+        if ((case  ((bit_maybe_w_matches_prefix stringappend_16280  ::  (( 1 Word.word * ii))option)) of
+            Some (stringappend_16290,stringappend_16300) =>
+             (let stringappend_16310 = (string_drop stringappend_16280 stringappend_16300) in
+             if ((case  ((bit_maybe_i_matches_prefix stringappend_16310  ::  (( 1 Word.word * ii))option)) of
+                 Some (stringappend_16320,stringappend_16330) =>
+                  (let stringappend_16340 = (string_drop stringappend_16310 stringappend_16330) in
+                  if ((case  ((bit_maybe_o_matches_prefix stringappend_16340
+                               ::  (( 1 Word.word * ii))option)) of
+                      Some (stringappend_16350,stringappend_16360) => 
+  (case  ((string_drop stringappend_16340 stringappend_16360)) of
+        s0 => True
+  )
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (r, stringappend_16270) =
+       ((case  ((bit_maybe_r_matches_prefix stringappend_16250  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16260,stringappend_16270) =>
+          (stringappend_16260, stringappend_16270)
+       )) in
+     (let stringappend_16280 = (string_drop stringappend_16250 stringappend_16270) in
+     (let (w, stringappend_16300) =
+       ((case  ((bit_maybe_w_matches_prefix stringappend_16280  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16290,stringappend_16300) =>
+          (stringappend_16290, stringappend_16300)
+       )) in
+     (let stringappend_16310 = (string_drop stringappend_16280 stringappend_16300) in
+     (let (i, stringappend_16330) =
+       ((case  ((bit_maybe_i_matches_prefix stringappend_16310  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16320,stringappend_16330) =>
+          (stringappend_16320, stringappend_16330)
+       )) in
+     (let stringappend_16340 = (string_drop stringappend_16310 stringappend_16330) in
+     (let (o1, stringappend_16360) =
+       ((case  ((bit_maybe_o_matches_prefix stringappend_16340  ::  (( 1 Word.word * ii))option)) of
+         Some (stringappend_16350,stringappend_16360) =>
+          (stringappend_16350, stringappend_16360)
+       )) in
+     (case  ((string_drop stringappend_16340 stringappend_16360)) of
+       s0 =>
+        Some ((concat_vec r ((concat_vec w ((concat_vec i o1  ::  2 Word.word))  ::  3 Word.word))
+                ::  4 Word.word),
+              ((string_length arg0)) - ((string_length s0)))
+     ))))))))
+   else None))"
+
+
+(*val aqrl_str : bool -> bool -> string*)
+
+fun aqrl_str  :: " bool \<Rightarrow> bool \<Rightarrow> string "  where 
+     " aqrl_str (False :: bool) (False :: bool) = ( (''''))"
+|" aqrl_str (False :: bool) (True :: bool) = ( (''.rl''))"
+|" aqrl_str (True :: bool) (False :: bool) = ( (''.aq''))"
+|" aqrl_str (True :: bool) (True :: bool) = ( (''.aqrl''))"
+
+
+(*val lrsc_width_str : word_width -> string*)
+
+fun lrsc_width_str  :: " word_width \<Rightarrow> string "  where 
+     " lrsc_width_str BYTE = ( (''.b''))"
+|" lrsc_width_str HALF = ( (''.h''))"
+|" lrsc_width_str WORD = ( (''.w''))"
+|" lrsc_width_str DOUBLE = ( (''.d''))"
+
+
+(*val process_loadres : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*)
+
+definition process_loadres  :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " process_loadres rd addr value1 is_unsigned = (
+   (case  ((extend_value is_unsigned value1  :: ( 64 Word.word) MemoryOpResult)) of
+     MemValue (result) =>
+      (let (_ :: unit) = (load_reservation addr) in
+      wX ((regbits_to_regno rd)) result \<then> return True)
+   | MemException (e) => handle_mem_exception addr e \<then> return False
+   ))"
+
+
+(*val encdec_amoop_forwards : amoop -> mword ty5*)
+
+fun encdec_amoop_forwards  :: " amoop \<Rightarrow>(5)Word.word "  where 
+     " encdec_amoop_forwards AMOSWAP = ( (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOADD = ( (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOXOR = ( (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOAND = ( (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOOR = ( (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOMIN = ( (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOMAX = ( (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOMINU = ( (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word))"
+|" encdec_amoop_forwards AMOMAXU = ( (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word))"
+
+
+(*val encdec_amoop_backwards : mword ty5 -> amoop*)
+
+definition encdec_amoop_backwards  :: "(5)Word.word \<Rightarrow> amoop "  where 
+     " encdec_amoop_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word))))))
+   then
+     AMOSWAP
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) then
+     AMOADD
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     AMOXOR
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     AMOAND
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     AMOOR
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))))) then
+     AMOMIN
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     AMOMAX
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     AMOMINU
+   else AMOMAXU))"
+
+
+(*val encdec_amoop_forwards_matches : amoop -> bool*)
+
+fun encdec_amoop_forwards_matches  :: " amoop \<Rightarrow> bool "  where 
+     " encdec_amoop_forwards_matches AMOSWAP = ( True )"
+|" encdec_amoop_forwards_matches AMOADD = ( True )"
+|" encdec_amoop_forwards_matches AMOXOR = ( True )"
+|" encdec_amoop_forwards_matches AMOAND = ( True )"
+|" encdec_amoop_forwards_matches AMOOR = ( True )"
+|" encdec_amoop_forwards_matches AMOMIN = ( True )"
+|" encdec_amoop_forwards_matches AMOMAX = ( True )"
+|" encdec_amoop_forwards_matches AMOMINU = ( True )"
+|" encdec_amoop_forwards_matches AMOMAXU = ( True )"
+
+
+(*val encdec_amoop_backwards_matches : mword ty5 -> bool*)
+
+definition encdec_amoop_backwards_matches  :: "(5)Word.word \<Rightarrow> bool "  where 
+     " encdec_amoop_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word))))))
+   then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word)))))) then
+     True
+   else False))"
+
+
+(*val amo_mnemonic_forwards : amoop -> string*)
+
+fun amo_mnemonic_forwards  :: " amoop \<Rightarrow> string "  where 
+     " amo_mnemonic_forwards AMOSWAP = ( (''amoswap''))"
+|" amo_mnemonic_forwards AMOADD = ( (''amoadd''))"
+|" amo_mnemonic_forwards AMOXOR = ( (''amoxor''))"
+|" amo_mnemonic_forwards AMOAND = ( (''amoand''))"
+|" amo_mnemonic_forwards AMOOR = ( (''amoor''))"
+|" amo_mnemonic_forwards AMOMIN = ( (''amomin''))"
+|" amo_mnemonic_forwards AMOMAX = ( (''amomax''))"
+|" amo_mnemonic_forwards AMOMINU = ( (''amominu''))"
+|" amo_mnemonic_forwards AMOMAXU = ( (''amomaxu''))"
+
+
+(*val amo_mnemonic_backwards : string -> amoop*)
+
+definition amo_mnemonic_backwards  :: " string \<Rightarrow> amoop "  where 
+     " amo_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''amoswap'')) then AMOSWAP else
+    (
+    if(arg0 = (''amoadd'')) then AMOADD else
+      (
+      if(arg0 = (''amoxor'')) then AMOXOR else
+        (
+        if(arg0 = (''amoand'')) then AMOAND else
+          (
+          if(arg0 = (''amoor'')) then AMOOR else
+            (
+            if(arg0 = (''amomin'')) then AMOMIN else
+              (
+              if(arg0 = (''amomax'')) then AMOMAX else
+                (
+                if(arg0 = (''amominu'')) then AMOMINU else
+                  (if(arg0 = (''amomaxu'')) then AMOMAXU else undefined)))))))) )"
+
+
+(*val amo_mnemonic_forwards_matches : amoop -> bool*)
+
+fun amo_mnemonic_forwards_matches  :: " amoop \<Rightarrow> bool "  where 
+     " amo_mnemonic_forwards_matches AMOSWAP = ( True )"
+|" amo_mnemonic_forwards_matches AMOADD = ( True )"
+|" amo_mnemonic_forwards_matches AMOXOR = ( True )"
+|" amo_mnemonic_forwards_matches AMOAND = ( True )"
+|" amo_mnemonic_forwards_matches AMOOR = ( True )"
+|" amo_mnemonic_forwards_matches AMOMIN = ( True )"
+|" amo_mnemonic_forwards_matches AMOMAX = ( True )"
+|" amo_mnemonic_forwards_matches AMOMINU = ( True )"
+|" amo_mnemonic_forwards_matches AMOMAXU = ( True )"
+
+
+(*val amo_mnemonic_backwards_matches : string -> bool*)
+
+definition amo_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " amo_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''amoswap'')) then True else
+    (
+    if(arg0 = (''amoadd'')) then True else
+      (
+      if(arg0 = (''amoxor'')) then True else
+        (
+        if(arg0 = (''amoand'')) then True else
+          (
+          if(arg0 = (''amoor'')) then True else
+            (
+            if(arg0 = (''amomin'')) then True else
+              (
+              if(arg0 = (''amomax'')) then True else
+                (
+                if(arg0 = (''amominu'')) then True else
+                  (if(arg0 = (''amomaxu'')) then True else False)))))))) )"
+
+
+(*val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))*)
+
+definition amo_mnemonic_matches_prefix  :: " string \<Rightarrow>(amoop*int)option "  where 
+     " amo_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16160 = arg0 in
+   if (((((string_startswith stringappend_16160 (''amoswap''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amoswap''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amoswap''))))) of
+       s0 => Some (AMOSWAP, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amoadd''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amoadd''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amoadd''))))) of
+       s0 => Some (AMOADD, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amoxor''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amoxor''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amoxor''))))) of
+       s0 => Some (AMOXOR, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amoand''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amoand''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amoand''))))) of
+       s0 => Some (AMOAND, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amoor''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amoor''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amoor''))))) of
+       s0 => Some (AMOOR, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amomin''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amomin''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amomin''))))) of
+       s0 => Some (AMOMIN, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amomax''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amomax''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amomax''))))) of
+       s0 => Some (AMOMAX, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amominu''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amominu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amominu''))))) of
+       s0 => Some (AMOMINU, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16160 (''amomaxu''))) \<and> (
+  (case  ((string_drop stringappend_16160 ((string_length (''amomaxu''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16160 ((string_length (''amomaxu''))))) of
+       s0 => Some (AMOMAXU, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val encdec_csrop_forwards : csrop -> mword ty2*)
+
+fun encdec_csrop_forwards  :: " csrop \<Rightarrow>(2)Word.word "  where 
+     " encdec_csrop_forwards CSRRW = ( (vec_of_bits [B0,B1]  ::  2 Word.word))"
+|" encdec_csrop_forwards CSRRS = ( (vec_of_bits [B1,B0]  ::  2 Word.word))"
+|" encdec_csrop_forwards CSRRC = ( (vec_of_bits [B1,B1]  ::  2 Word.word))"
+
+
+(*val encdec_csrop_backwards : mword ty2 -> csrop*)
+
+definition encdec_csrop_backwards  :: "(2)Word.word \<Rightarrow> csrop "  where 
+     " encdec_csrop_backwards arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then CSRRW
+   else if (((p00 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then CSRRS
+   else CSRRC))"
+
 
-definition process_load  :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " process_load rd addr value1 is_unsigned = (
-   (case  ((extend_value is_unsigned value1  :: ( 64 Word.word) MemoryOpResult)) of
-     MemValue (result) => wX ((regbits_to_regno rd)) result
-   | MemException (e) => handle_mem_exception addr e
-   ))"
+(*val encdec_csrop_forwards_matches : csrop -> bool*)
 
+fun encdec_csrop_forwards_matches  :: " csrop \<Rightarrow> bool "  where 
+     " encdec_csrop_forwards_matches CSRRW = ( True )"
+|" encdec_csrop_forwards_matches CSRRS = ( True )"
+|" encdec_csrop_forwards_matches CSRRC = ( True )"
+
+
+(*val encdec_csrop_backwards_matches : mword ty2 -> bool*)
+
+definition encdec_csrop_backwards_matches  :: "(2)Word.word \<Rightarrow> bool "  where 
+     " encdec_csrop_backwards_matches arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (vec_of_bits [B0,B1]  ::  2 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B0]  ::  2 Word.word)))) then True
+   else if (((p00 = (vec_of_bits [B1,B1]  ::  2 Word.word)))) then True
+   else False))"
 
-(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*)
 
 (*val readCSR : mword ty12 -> M (mword ty64)*)
 
 definition readCSR  :: "(12)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad "  where 
      " readCSR csr = (
    (let b__0 = csr in
-   if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1]  ::  12 Word.word)))) then
-     (read_reg mvendorid_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0]  ::  12 Word.word)))) then
-     (read_reg marchid_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1]  ::  12 Word.word)))) then
-     (read_reg mimpid_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0]  ::  12 Word.word)))) then
-     (read_reg mhartid_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .  return ((get_Mstatus w__4  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
-     read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) .  return ((get_Misa w__5  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-     read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) .  return ((get_Medeleg w__6  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
-     read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . 
-     return ((get_Minterrupts w__7  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-     read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) .  return ((get_Minterrupts w__8  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
-     read_reg mtvec_ref \<bind> (\<lambda> (w__9 :: Mtvec) .  return ((get_Mtvec w__9  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     (read_reg mscratch_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
-     (read_reg mepc_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-     read_reg mcause_ref \<bind> (\<lambda> (w__12 :: Mcause) .  return ((get_Mcause w__12  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
-     (read_reg mtval_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-     read_reg mip_ref \<bind> (\<lambda> (w__14 :: Minterrupts) . 
-     return ((get_Minterrupts w__14  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) .  return ((get_Mstatus w__15  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-     read_reg sedeleg_ref \<bind> (\<lambda> (w__16 :: Sedeleg) .  return ((get_Sedeleg w__16  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
-     read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) . 
-     return ((get_Sinterrupts w__17  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-     read_reg mie_ref \<bind> (\<lambda> (w__18 :: Minterrupts) . 
-     read_reg mideleg_ref \<bind> (\<lambda> (w__19 :: Minterrupts) . 
-     return ((get_Sinterrupts ((lower_mie w__18 w__19))  ::  64 Word.word))))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
-     read_reg stvec_ref \<bind> (\<lambda> (w__20 :: Mtvec) .  return ((get_Mtvec w__20  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     (read_reg sscratch_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
-     (read_reg sepc_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-     read_reg scause_ref \<bind> (\<lambda> (w__23 :: Mcause) .  return ((get_Mcause w__23  ::  64 Word.word)))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
-     (read_reg stval_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-     read_reg mip_ref \<bind> (\<lambda> (w__25 :: Minterrupts) . 
-     read_reg mideleg_ref \<bind> (\<lambda> (w__26 :: Minterrupts) . 
-     return ((get_Sinterrupts ((lower_mip w__25 w__26))  ::  64 Word.word))))
-   else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     (read_reg satp_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     (read_reg mcycle_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
-     (read_reg mtime_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-     (read_reg minstret_ref  :: ( 64 Word.word) M)
-   else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-     (read_reg tselect_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__31 ::  64 Word.word) . 
-     return ((not_vec w__31  ::  64 Word.word)))
-   else
-     (let (_ :: unit) = (print_bits (''unhandled read to CSR '') csr) in
-     return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                          B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                          B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-              ::  64 Word.word))))"
+   (if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1]  ::  12 Word.word)))) then
+      (read_reg mvendorid_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      (read_reg marchid_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1]  ::  12 Word.word)))) then
+      (read_reg mimpid_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0]  ::  12 Word.word)))) then
+      (read_reg mhartid_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) . 
+      return ((get_Mstatus_bits w__4  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+      read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) .  return ((get_Misa_bits w__5  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) . 
+      return ((get_Medeleg_bits w__6  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+      read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . 
+      return ((get_Minterrupts_bits w__7  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+      read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) . 
+      return ((get_Minterrupts_bits w__8  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+      read_reg mtvec_ref \<bind> (\<lambda> (w__9 :: Mtvec) .  return ((get_Mtvec_bits w__9  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+      read_reg mcounteren_ref \<bind> (\<lambda> (w__10 :: Counteren) . 
+      return ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__10  ::  32 Word.word))  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg mscratch_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+      (read_reg mepc_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 ::  64 Word.word) . 
+      (pc_alignment_mask ()   :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 ::  64 Word.word) . 
+      return ((and_vec w__12 w__13  ::  64 Word.word))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      read_reg mcause_ref \<bind> (\<lambda> (w__14 :: Mcause) . 
+      return ((get_Mcause_bits w__14  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+      (read_reg mtval_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+      read_reg mip_ref \<bind> (\<lambda> (w__16 :: Minterrupts) . 
+      return ((get_Minterrupts_bits w__16  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg pmpcfg0_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg pmpaddr0_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      read_reg mstatus_ref \<bind> (\<lambda> (w__19 :: Mstatus) . 
+      return ((get_Sstatus_bits ((lower_mstatus w__19))  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      read_reg sedeleg_ref \<bind> (\<lambda> (w__20 :: Sedeleg) . 
+      return ((get_Sedeleg_bits w__20  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+      read_reg sideleg_ref \<bind> (\<lambda> (w__21 :: Sinterrupts) . 
+      return ((get_Sinterrupts_bits w__21  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+      read_reg mie_ref \<bind> (\<lambda> (w__22 :: Minterrupts) . 
+      read_reg mideleg_ref \<bind> (\<lambda> (w__23 :: Minterrupts) . 
+      return ((get_Sinterrupts_bits ((lower_mie w__22 w__23))  ::  64 Word.word))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
+      read_reg stvec_ref \<bind> (\<lambda> (w__24 :: Mtvec) .  return ((get_Mtvec_bits w__24  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+      read_reg scounteren_ref \<bind> (\<lambda> (w__25 :: Counteren) . 
+      return ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__25  ::  32 Word.word))  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg sscratch_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+      (read_reg sepc_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 ::  64 Word.word) . 
+      (pc_alignment_mask ()   :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 ::  64 Word.word) . 
+      return ((and_vec w__27 w__28  ::  64 Word.word))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      read_reg scause_ref \<bind> (\<lambda> (w__29 :: Mcause) . 
+      return ((get_Mcause_bits w__29  ::  64 Word.word)))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
+      (read_reg stval_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
+      read_reg mip_ref \<bind> (\<lambda> (w__31 :: Minterrupts) . 
+      read_reg mideleg_ref \<bind> (\<lambda> (w__32 :: Minterrupts) . 
+      return ((get_Sinterrupts_bits ((lower_mip w__31 w__32))  ::  64 Word.word))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg satp_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg mcycle_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+      (read_reg mtime_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      (read_reg minstret_ref  :: ( 64 Word.word) M)
+    else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (read_reg tselect_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 ::  64 Word.word) . 
+      return ((not_vec w__37  ::  64 Word.word)))
+    else
+      (let (_ :: unit) = (print_bits (''unhandled read to CSR '') csr) in
+      return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word))) \<bind> (\<lambda> (res :: xlenbits) . 
+   (let (_ :: unit) =
+     (print_endline
+       (((op@) (''CSR '')
+           (((op@) ((csr_name csr)) (((op@) ('' -> '') ((string_of_bits res))))))))) in
+   return res))))"
 
 
 (*val writeCSR : mword ty12 -> mword ty64 -> M unit*)
@@ -5363,784 +12442,330 @@ definition writeCSR  :: "(12)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(
       read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . 
       (write_reg mstatus_ref ((legalize_mstatus w__0 value1)) \<then>
       read_reg mstatus_ref) \<bind> (\<lambda> (w__1 :: Mstatus) . 
-      return (Some ((get_Mstatus w__1  ::  64 Word.word)))))
+      return (Some ((get_Mstatus_bits w__1  ::  64 Word.word)))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
+      read_reg misa_ref \<bind> (\<lambda> (w__2 :: Misa) . 
+      legalize_misa w__2 value1 \<bind> (\<lambda> (w__3 :: Misa) . 
+      (write_reg misa_ref w__3 \<then>
+      read_reg misa_ref) \<bind> (\<lambda> (w__4 :: Misa) .  return (Some ((get_Misa_bits w__4  ::  64 Word.word))))))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-      read_reg medeleg_ref \<bind> (\<lambda> (w__2 :: Medeleg) . 
-      (write_reg medeleg_ref ((legalize_medeleg w__2 value1)) \<then>
-      read_reg medeleg_ref) \<bind> (\<lambda> (w__3 :: Medeleg) . 
-      return (Some ((get_Medeleg w__3  ::  64 Word.word)))))
+      read_reg medeleg_ref \<bind> (\<lambda> (w__5 :: Medeleg) . 
+      (write_reg medeleg_ref ((legalize_medeleg w__5 value1)) \<then>
+      read_reg medeleg_ref) \<bind> (\<lambda> (w__6 :: Medeleg) . 
+      return (Some ((get_Medeleg_bits w__6  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
-      read_reg mideleg_ref \<bind> (\<lambda> (w__4 :: Minterrupts) . 
-      (write_reg mideleg_ref ((legalize_mideleg w__4 value1)) \<then>
-      read_reg mideleg_ref) \<bind> (\<lambda> (w__5 :: Minterrupts) . 
-      return (Some ((get_Minterrupts w__5  ::  64 Word.word)))))
+      read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . 
+      (write_reg mideleg_ref ((legalize_mideleg w__7 value1)) \<then>
+      read_reg mideleg_ref) \<bind> (\<lambda> (w__8 :: Minterrupts) . 
+      return (Some ((get_Minterrupts_bits w__8  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-      read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) . 
-      (write_reg mie_ref ((legalize_mie w__6 value1)) \<then>
-      read_reg mie_ref) \<bind> (\<lambda> (w__7 :: Minterrupts) . 
-      return (Some ((get_Minterrupts w__7  ::  64 Word.word)))))
+      read_reg mie_ref \<bind> (\<lambda> (w__9 :: Minterrupts) . 
+      (write_reg mie_ref ((legalize_mie w__9 value1)) \<then>
+      read_reg mie_ref) \<bind> (\<lambda> (w__10 :: Minterrupts) . 
+      return (Some ((get_Minterrupts_bits w__10  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
-      read_reg mtvec_ref \<bind> (\<lambda> (w__8 :: Mtvec) . 
-      (write_reg mtvec_ref ((legalize_tvec w__8 value1)) \<then>
-      read_reg mtvec_ref) \<bind> (\<lambda> (w__9 :: Mtvec) .  return (Some ((get_Mtvec w__9  ::  64 Word.word)))))
+      read_reg mtvec_ref \<bind> (\<lambda> (w__11 :: Mtvec) . 
+      (write_reg mtvec_ref ((legalize_tvec w__11 value1)) \<then>
+      read_reg mtvec_ref) \<bind> (\<lambda> (w__12 :: Mtvec) . 
+      return (Some ((get_Mtvec_bits w__12  ::  64 Word.word)))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+      read_reg mcounteren_ref \<bind> (\<lambda> (w__13 :: Counteren) . 
+      (write_reg mcounteren_ref ((legalize_mcounteren w__13 value1)) \<then>
+      read_reg mcounteren_ref) \<bind> (\<lambda> (w__14 :: Counteren) . 
+      return (Some ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__14  ::  32 Word.word))  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
       (write_reg mscratch_ref value1 \<then>
-      (read_reg mscratch_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__10 ::  64 Word.word) .  return (Some w__10))
+      (read_reg mscratch_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__15 ::  64 Word.word) .  return (Some w__15))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
-      (legalize_xepc value1  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: xlenbits) . 
-      (write_reg mepc_ref w__11 \<then>
-      (read_reg mepc_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__12 ::  64 Word.word) .  return (Some w__12)))
+      (legalize_xepc value1  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: xlenbits) . 
+      (write_reg mepc_ref w__16 \<then>
+      (read_reg mepc_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__17 ::  64 Word.word) .  return (Some w__17)))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-      (set_Mcause mcause_ref value1 \<then>
-      read_reg mcause_ref) \<bind> (\<lambda> (w__13 :: Mcause) . 
-      return (Some ((get_Mcause w__13  ::  64 Word.word))))
+      (set_Mcause_bits mcause_ref value1 \<then>
+      read_reg mcause_ref) \<bind> (\<lambda> (w__18 :: Mcause) . 
+      return (Some ((get_Mcause_bits w__18  ::  64 Word.word))))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
       (write_reg mtval_ref value1 \<then>
-      (read_reg mtval_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 ::  64 Word.word) .  return (Some w__14))
+      (read_reg mtval_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__19 ::  64 Word.word) .  return (Some w__19))
     else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-      read_reg mip_ref \<bind> (\<lambda> (w__15 :: Minterrupts) . 
-      (write_reg mip_ref ((legalize_mip w__15 value1)) \<then>
-      read_reg mip_ref) \<bind> (\<lambda> (w__16 :: Minterrupts) . 
-      return (Some ((get_Minterrupts w__16  ::  64 Word.word)))))
+      read_reg mip_ref \<bind> (\<lambda> (w__20 :: Minterrupts) . 
+      (write_reg mip_ref ((legalize_mip w__20 value1)) \<then>
+      read_reg mip_ref) \<bind> (\<lambda> (w__21 :: Minterrupts) . 
+      return (Some ((get_Minterrupts_bits w__21  ::  64 Word.word)))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (write_reg pmpcfg0_ref value1 \<then>
+      (read_reg pmpcfg0_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__22 ::  64 Word.word) .  return (Some w__22))
+    else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (write_reg pmpaddr0_ref value1 \<then>
+      (read_reg pmpaddr0_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__23 ::  64 Word.word) .  return (Some w__23))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-      read_reg mstatus_ref \<bind> (\<lambda> (w__17 :: Mstatus) . 
-      (write_reg mstatus_ref ((legalize_sstatus w__17 value1)) \<then>
-      read_reg mstatus_ref) \<bind> (\<lambda> (w__18 :: Mstatus) . 
-      return (Some ((get_Mstatus w__18  ::  64 Word.word)))))
+      read_reg mstatus_ref \<bind> (\<lambda> (w__24 :: Mstatus) . 
+      (write_reg mstatus_ref ((legalize_sstatus w__24 value1)) \<then>
+      read_reg mstatus_ref) \<bind> (\<lambda> (w__25 :: Mstatus) . 
+      return (Some ((get_Mstatus_bits w__25  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-      read_reg sedeleg_ref \<bind> (\<lambda> (w__19 :: Sedeleg) . 
-      (write_reg sedeleg_ref ((legalize_sedeleg w__19 value1)) \<then>
-      read_reg sedeleg_ref) \<bind> (\<lambda> (w__20 :: Sedeleg) . 
-      return (Some ((get_Sedeleg w__20  ::  64 Word.word)))))
+      read_reg sedeleg_ref \<bind> (\<lambda> (w__26 :: Sedeleg) . 
+      (write_reg sedeleg_ref ((legalize_sedeleg w__26 value1)) \<then>
+      read_reg sedeleg_ref) \<bind> (\<lambda> (w__27 :: Sedeleg) . 
+      return (Some ((get_Sedeleg_bits w__27  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
-      (set_Sinterrupts sideleg_ref value1 \<then>
-      read_reg sideleg_ref) \<bind> (\<lambda> (w__21 :: Sinterrupts) . 
-      return (Some ((get_Sinterrupts w__21  ::  64 Word.word))))
+      (set_Sinterrupts_bits sideleg_ref value1 \<then>
+      read_reg sideleg_ref) \<bind> (\<lambda> (w__28 :: Sinterrupts) . 
+      return (Some ((get_Sinterrupts_bits w__28  ::  64 Word.word))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-      read_reg mie_ref \<bind> (\<lambda> (w__22 :: Minterrupts) . 
-      read_reg mideleg_ref \<bind> (\<lambda> (w__23 :: Minterrupts) . 
-      (write_reg mie_ref ((legalize_sie w__22 w__23 value1)) \<then>
-      read_reg mie_ref) \<bind> (\<lambda> (w__24 :: Minterrupts) . 
-      return (Some ((get_Minterrupts w__24  ::  64 Word.word))))))
+      read_reg mie_ref \<bind> (\<lambda> (w__29 :: Minterrupts) . 
+      read_reg mideleg_ref \<bind> (\<lambda> (w__30 :: Minterrupts) . 
+      (write_reg mie_ref ((legalize_sie w__29 w__30 value1)) \<then>
+      read_reg mie_ref) \<bind> (\<lambda> (w__31 :: Minterrupts) . 
+      return (Some ((get_Minterrupts_bits w__31  ::  64 Word.word))))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)))) then
-      read_reg stvec_ref \<bind> (\<lambda> (w__25 :: Mtvec) . 
-      (write_reg stvec_ref ((legalize_tvec w__25 value1)) \<then>
-      read_reg stvec_ref) \<bind> (\<lambda> (w__26 :: Mtvec) .  return (Some ((get_Mtvec w__26  ::  64 Word.word)))))
+      read_reg stvec_ref \<bind> (\<lambda> (w__32 :: Mtvec) . 
+      (write_reg stvec_ref ((legalize_tvec w__32 value1)) \<then>
+      read_reg stvec_ref) \<bind> (\<lambda> (w__33 :: Mtvec) . 
+      return (Some ((get_Mtvec_bits w__33  ::  64 Word.word)))))
+    else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0]  ::  12 Word.word)))) then
+      read_reg scounteren_ref \<bind> (\<lambda> (w__34 :: Counteren) . 
+      (write_reg scounteren_ref ((legalize_scounteren w__34 value1)) \<then>
+      read_reg scounteren_ref) \<bind> (\<lambda> (w__35 :: Counteren) . 
+      return (Some ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__35  ::  32 Word.word))  ::  64 Word.word)))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
       (write_reg sscratch_ref value1 \<then>
-      (read_reg sscratch_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__27 ::  64 Word.word) .  return (Some w__27))
+      (read_reg sscratch_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__36 ::  64 Word.word) .  return (Some w__36))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)))) then
-      (legalize_xepc value1  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: xlenbits) . 
-      (write_reg sepc_ref w__28 \<then>
-      (read_reg sepc_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__29 ::  64 Word.word) .  return (Some w__29)))
+      (legalize_xepc value1  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 :: xlenbits) . 
+      (write_reg sepc_ref w__37 \<then>
+      (read_reg sepc_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 ::  64 Word.word) .  return (Some w__38)))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
-      (set_Mcause scause_ref value1 \<then>
-      read_reg scause_ref) \<bind> (\<lambda> (w__30 :: Mcause) . 
-      return (Some ((get_Mcause w__30  ::  64 Word.word))))
+      (set_Mcause_bits scause_ref value1 \<then>
+      read_reg scause_ref) \<bind> (\<lambda> (w__39 :: Mcause) . 
+      return (Some ((get_Mcause_bits w__39  ::  64 Word.word))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1]  ::  12 Word.word)))) then
       (write_reg stval_ref value1 \<then>
-      (read_reg stval_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 ::  64 Word.word) .  return (Some w__31))
+      (read_reg stval_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__40 ::  64 Word.word) .  return (Some w__40))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0]  ::  12 Word.word)))) then
-      read_reg mip_ref \<bind> (\<lambda> (w__32 :: Minterrupts) . 
-      read_reg mideleg_ref \<bind> (\<lambda> (w__33 :: Minterrupts) . 
-      (write_reg mip_ref ((legalize_sip w__32 w__33 value1)) \<then>
-      read_reg mip_ref) \<bind> (\<lambda> (w__34 :: Minterrupts) . 
-      return (Some ((get_Minterrupts w__34  ::  64 Word.word))))))
+      read_reg mip_ref \<bind> (\<lambda> (w__41 :: Minterrupts) . 
+      read_reg mideleg_ref \<bind> (\<lambda> (w__42 :: Minterrupts) . 
+      (write_reg mip_ref ((legalize_sip w__41 w__42 value1)) \<then>
+      read_reg mip_ref) \<bind> (\<lambda> (w__43 :: Minterrupts) . 
+      return (Some ((get_Minterrupts_bits w__43  ::  64 Word.word))))))
     else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
-      cur_Architecture ()  \<bind> (\<lambda> (w__35 :: Architecture) . 
-      (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__36 ::  64 Word.word) . 
-      (write_reg satp_ref ((legalize_satp w__35 w__36 value1  ::  64 Word.word)) \<then>
-      (read_reg satp_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__37 ::  64 Word.word) .  return (Some w__37))))
+      cur_Architecture ()  \<bind> (\<lambda> (w__44 :: Architecture) . 
+      (read_reg satp_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__45 ::  64 Word.word) . 
+      (write_reg satp_ref ((legalize_satp w__44 w__45 value1  ::  64 Word.word)) \<then>
+      (read_reg satp_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__46 ::  64 Word.word) .  return (Some w__46))))
     else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
       (write_reg tselect_ref value1 \<then>
-      (read_reg tselect_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 ::  64 Word.word) .  return (Some w__38))
+      (read_reg tselect_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__47 ::  64 Word.word) .  return (Some w__47))
+    else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)))) then
+      (write_reg mcycle_ref value1 \<then>
+      (read_reg mcycle_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__48 ::  64 Word.word) .  return (Some w__48))
+    else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0]  ::  12 Word.word)))) then
+      ((write_reg minstret_ref value1 \<then>
+      write_reg minstret_written_ref True) \<then>
+      (read_reg minstret_ref  :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__49 ::  64 Word.word) .  return (Some w__49))
     else return None) \<bind> (\<lambda> (res ::  xlenbits option) . 
    return ((case  res of
      Some (v) =>
-      prerr_endline
+      print_endline
         (((op@) (''CSR '')
             (((op@) ((csr_name csr))
                 (((op@) ('' <- '')
-                    (((op@) ((string_of_vec v))
-                        (((op@) ('' (input: '') (((op@) ((string_of_vec value1)) ('')'')))))))))))))
+                    (((op@) ((string_of_bits v))
+                        (((op@) ('' (input: '') (((op@) ((string_of_bits value1)) ('')'')))))))))))))
    | None => print_bits (''unhandled write to CSR '') csr
    )))))"
 
 
-definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where 
-     " decode v__0 = (
-   if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1]  ::  7 Word.word)))) then
-     (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii)  ::  20 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (UTYPE (imm,rd,RISCV_LUI))))
-   else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1]  ::  7 Word.word)))) then
-     (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii)  ::  20 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (UTYPE (imm,rd,RISCV_AUIPC))))
-   else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))) then
-     (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii)  ::  20 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word))
-                             ((concat_vec
-                                 ((cast_unit_vec0 ((access_vec_dec imm (( 8 :: int)::ii)))  ::  1 Word.word))
-                                 ((concat_vec ((subrange_vec_dec imm (( 18 :: int)::ii) (( 13 :: int)::ii)  ::  6 Word.word))
-                                     ((concat_vec
-                                         ((subrange_vec_dec imm (( 12 :: int)::ii) (( 9 :: int)::ii)  ::  4 Word.word))
-                                         (vec_of_bits [B0]  ::  1 Word.word)
-                                        ::  5 Word.word))
-                                    ::  11 Word.word))
-                                ::  12 Word.word))
-                            ::  20 Word.word))
-                        ::  21 Word.word),rd))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RISCV_JALR (imm,rs1,rd)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii)))  ::  1 Word.word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word))
-                                 (vec_of_bits [B0]  ::  1 Word.word)
-                                ::  5 Word.word))
-                            ::  11 Word.word))
-                        ::  12 Word.word))
-                    ::  13 Word.word),rs2,rs1,RISCV_BEQ))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii)))  ::  1 Word.word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word))
-                                 (vec_of_bits [B0]  ::  1 Word.word)
-                                ::  5 Word.word))
-                            ::  11 Word.word))
-                        ::  12 Word.word))
-                    ::  13 Word.word),rs2,rs1,RISCV_BNE))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii)))  ::  1 Word.word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word))
-                                 (vec_of_bits [B0]  ::  1 Word.word)
-                                ::  5 Word.word))
-                            ::  11 Word.word))
-                        ::  12 Word.word))
-                    ::  13 Word.word),rs2,rs1,RISCV_BLT))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii)))  ::  1 Word.word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word))
-                                 (vec_of_bits [B0]  ::  1 Word.word)
-                                ::  5 Word.word))
-                            ::  11 Word.word))
-                        ::  12 Word.word))
-                    ::  13 Word.word),rs2,rs1,RISCV_BGE))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii)))  ::  1 Word.word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word))
-                                 (vec_of_bits [B0]  ::  1 Word.word)
-                                ::  5 Word.word))
-                            ::  11 Word.word))
-                        ::  12 Word.word))
-                    ::  13 Word.word),rs2,rs1,RISCV_BLTU))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii)))  ::  1 Word.word))
-                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii)))  ::  1 Word.word))
-                         ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii)  ::  6 Word.word))
-                             ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word))
-                                 (vec_of_bits [B0]  ::  1 Word.word)
-                                ::  5 Word.word))
-                            ::  11 Word.word))
-                        ::  12 Word.word))
-                    ::  13 Word.word),rs2,rs1,RISCV_BGEU))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_ADDI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_SLTI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_SLTIU)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_XORI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_ORI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_ANDI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii)  ::  6 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii)  ::  6 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii)  ::  6 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_ADD)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_SUB)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_SLL)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_SLT)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_SLTU)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_XOR)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_SRL)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_SRA)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_OR)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPE (rs2,rs1,rd,RISCV_AND)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,False,BYTE,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,False,HALF,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,False,WORD,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,False,DOUBLE,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,True,BYTE,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,True,HALF,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd,True,WORD,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (STORE ((concat_vec imm7 imm5  ::  12 Word.word),rs2,rs1,BYTE,False,False))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (STORE ((concat_vec imm7 imm5  ::  12 Word.word),rs2,rs1,HALF,False,False))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (STORE ((concat_vec imm7 imm5  ::  12 Word.word),rs2,rs1,WORD,False,False))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (STORE ((concat_vec imm7 imm5  ::  12 Word.word),rs2,rs1,DOUBLE,False,False))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ADDIW (imm,rs1,rd)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (SHIFTW (shamt,rs1,rd,RISCV_SLLI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (SHIFTW (shamt,rs1,rd,RISCV_SRLI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (SHIFTW (shamt,rs1,rd,RISCV_SRAI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPEW (rs2,rs1,rd,RISCV_ADDW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPEW (rs2,rs1,rd,RISCV_SUBW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPEW (rs2,rs1,rd,RISCV_SLLW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPEW (rs2,rs1,rd,RISCV_SRLW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (RTYPEW (rs2,rs1,rd,RISCV_SRAW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (MUL (rs2,rs1,rd,False,True,True)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (MUL (rs2,rs1,rd,True,True,True)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (MUL (rs2,rs1,rd,True,True,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (MUL (rs2,rs1,rd,True,False,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (DIV (rs2,rs1,rd,True)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (DIV (rs2,rs1,rd,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (REM (rs2,rs1,rd,True)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (REM (rs2,rs1,rd,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (MULW (rs2,rs1,rd)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (DIVW (rs2,rs1,rd,True)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (DIVW (rs2,rs1,rd,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (REMW (rs2,rs1,rd,True)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))))))))) then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (REMW (rs2,rs1,rd,False)))))
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 28 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 0 :: int)::ii)  ::  20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
-                     ::  20 Word.word))))))) then
-     (let (pred :: 4 bits) = ((subrange_vec_dec v__0 (( 27 :: int)::ii) (( 24 :: int)::ii)  ::  4 Word.word)) in
-     (let (succ :: 4 bits) = ((subrange_vec_dec v__0 (( 23 :: int)::ii) (( 20 :: int)::ii)  ::  4 Word.word)) in
-     Some (FENCE (pred,succ))))
-   else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,
-                             B0,B0,B0,B0,B1,B1,B1,B1]
-                 ::  32 Word.word)))) then
-     Some (FENCEI () )
-   else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                             B0,B1,B1,B1,B0,B0,B1,B1]
-                 ::  32 Word.word)))) then
-     Some (ECALL () )
-   else if (((v__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                             B0,B1,B1,B1,B0,B0,B1,B1]
-                 ::  32 Word.word)))) then
-     Some (MRET () )
-   else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                             B0,B1,B1,B1,B0,B0,B1,B1]
-                 ::  32 Word.word)))) then
-     Some (SRET () )
-   else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                             B0,B1,B1,B1,B0,B0,B1,B1]
-                 ::  32 Word.word)))) then
-     Some (EBREAK () )
-   else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                             B0,B1,B1,B1,B0,B0,B1,B1]
-                 ::  32 Word.word)))) then
-     Some (WFI () )
-   else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1]  ::  7 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 0 :: int)::ii)  ::  15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]  ::  15 Word.word)))))))
-   then
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     Some (SFENCE_VMA (rs1,rs2))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)))))))
-   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0]  ::  5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))))))))) then
-     (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in
-     (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)))))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (CSR (csr,rs1,rd,False,CSRRW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (CSR (csr,rs1,rd,False,CSRRS)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (CSR (csr,rs1,rd,False,CSRRC)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (CSR (csr,rs1,rd,True,CSRRW)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (CSR (csr,rs1,rd,True,CSRRS)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (CSR (csr,rs1,rd,True,CSRRC)))))
-   else None )"
+(*val maybe_i_forwards : bool -> string*)
+
+fun maybe_i_forwards  :: " bool \<Rightarrow> string "  where 
+     " maybe_i_forwards True = ( (''i''))"
+|" maybe_i_forwards False = ( (''''))"
+
+
+(*val maybe_i_backwards : string -> bool*)
+
+definition maybe_i_backwards  :: " string \<Rightarrow> bool "  where 
+     " maybe_i_backwards arg0 = ( 
+  if(arg0 = (''i'')) then True else
+    (if(arg0 = ('''')) then False else undefined) )"
+
+
+(*val maybe_i_forwards_matches : bool -> bool*)
+
+fun maybe_i_forwards_matches  :: " bool \<Rightarrow> bool "  where 
+     " maybe_i_forwards_matches True = ( True )"
+|" maybe_i_forwards_matches False = ( True )"
+
+
+(*val maybe_i_backwards_matches : string -> bool*)
+
+definition maybe_i_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " maybe_i_backwards_matches arg0 = ( 
+  if(arg0 = (''i'')) then True else (if(arg0 = ('''')) then True else False) )"
+
+
+(*val maybe_i_matches_prefix : string -> maybe ((bool * ii))*)
+
+definition maybe_i_matches_prefix  :: " string \<Rightarrow>(bool*int)option "  where 
+     " maybe_i_matches_prefix arg0 = (
+   (let stringappend_16140 = arg0 in
+   if (((((string_startswith stringappend_16140 (''i''))) \<and> (
+  (case  ((string_drop stringappend_16140 ((string_length (''i''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16140 ((string_length (''i''))))) of
+       s0 => Some (True, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16140 (''''))) \<and> (
+  (case  ((string_drop stringappend_16140 ((string_length (''''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16140 ((string_length (''''))))) of
+       s0 => Some (False, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
+
+
+(*val csr_mnemonic_forwards : csrop -> string*)
+
+fun csr_mnemonic_forwards  :: " csrop \<Rightarrow> string "  where 
+     " csr_mnemonic_forwards CSRRW = ( (''csrrw''))"
+|" csr_mnemonic_forwards CSRRS = ( (''csrrs''))"
+|" csr_mnemonic_forwards CSRRC = ( (''csrrc''))"
+
+
+(*val csr_mnemonic_backwards : string -> csrop*)
+
+definition csr_mnemonic_backwards  :: " string \<Rightarrow> csrop "  where 
+     " csr_mnemonic_backwards arg0 = ( 
+  if(arg0 = (''csrrw'')) then CSRRW else
+    (
+    if(arg0 = (''csrrs'')) then CSRRS else
+      (if(arg0 = (''csrrc'')) then CSRRC else undefined)) )"
+
+
+(*val csr_mnemonic_forwards_matches : csrop -> bool*)
+
+fun csr_mnemonic_forwards_matches  :: " csrop \<Rightarrow> bool "  where 
+     " csr_mnemonic_forwards_matches CSRRW = ( True )"
+|" csr_mnemonic_forwards_matches CSRRS = ( True )"
+|" csr_mnemonic_forwards_matches CSRRC = ( True )"
+
+
+(*val csr_mnemonic_backwards_matches : string -> bool*)
+
+definition csr_mnemonic_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " csr_mnemonic_backwards_matches arg0 = ( 
+  if(arg0 = (''csrrw'')) then True else
+    (
+    if(arg0 = (''csrrs'')) then True else
+      (if(arg0 = (''csrrc'')) then True else False)) )"
+
+
+(*val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))*)
+
+definition csr_mnemonic_matches_prefix  :: " string \<Rightarrow>(csrop*int)option "  where 
+     " csr_mnemonic_matches_prefix arg0 = (
+   (let stringappend_16110 = arg0 in
+   if (((((string_startswith stringappend_16110 (''csrrw''))) \<and> (
+  (case  ((string_drop stringappend_16110 ((string_length (''csrrw''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16110 ((string_length (''csrrw''))))) of
+       s0 => Some (CSRRW, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16110 (''csrrs''))) \<and> (
+  (case  ((string_drop stringappend_16110 ((string_length (''csrrs''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16110 ((string_length (''csrrs''))))) of
+       s0 => Some (CSRRS, ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_16110 (''csrrc''))) \<and> (
+  (case  ((string_drop stringappend_16110 ((string_length (''csrrc''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_16110 ((string_length (''csrrc''))))) of
+       s0 => Some (CSRRC, ((string_length arg0)) - ((string_length s0)))
+     )
+   else None))"
 
 
 definition decodeCompressed  :: "(16)Word.word \<Rightarrow>(ast)option "  where 
-     " decodeCompressed v__418 = (
-   if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (nzi1 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (nzi0 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+     " decodeCompressed v__2 = (
+   if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)))))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (nzi1 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (nzi0 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      if ((((((nzi1 = (vec_of_bits [B0]  ::  1 Word.word)))) \<and> (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) then
        Some (NOP () )
      else None))
-   else if (((v__418 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)))) then
-     Some (ILLEGAL () )
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
-     (let (nz54 :: 2 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 11 :: int)::ii)  ::  2 Word.word)) in
-     (let (nz96 :: 4 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 7 :: int)::ii)  ::  4 Word.word)) in
-     (let (nz2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
-     (let (nz3 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
-     (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+     (let (nz54 :: 2 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 11 :: int)::ii)  ::  2 Word.word)) in
+     (let (nz96 :: 4 bits) = ((subrange_vec_dec v__2 (( 10 :: int)::ii) (( 7 :: int)::ii)  ::  4 Word.word)) in
+     (let (nz2 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
+     (let (nz3 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      (let nzimm =
        ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2  ::  2 Word.word))  ::  4 Word.word))
          ::  8 Word.word)) in
      if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word)))) then None
      else Some (C_ADDI4SPN (rd,nzimm))))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
-     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
-     (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
-     (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs1 :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (ui2 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
+     (let (ui6 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2  ::  4 Word.word))  ::  5 Word.word)) in
      Some (C_LW (uimm,rs1,rd))))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
-     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
-     (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs1 :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let (rd :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      (let uimm = ((concat_vec ui76 ui53  ::  5 Word.word)) in
      Some (C_LD (uimm,rs1,rd)))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
-     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
-     (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs1 :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (ui2 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
+     (let (ui6 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2  ::  4 Word.word))  ::  5 Word.word)) in
      Some (C_SW (uimm,rs1,rs2))))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
-     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs1 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
-     (let (rs2 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs1 :: 3 bits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let (rs2 :: 3 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      (let uimm = ((concat_vec ui76 ui53  ::  5 Word.word)) in
      Some (C_SD (uimm,rs1,rs2)))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      (let nzi = ((concat_vec nzi5 nzi40  ::  6 Word.word)) in
      if ((((((nzi = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) \<or> (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then
        None
      else Some (C_ADDI (nzi,rsd))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (imm5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (imm40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      Some (C_ADDIW ((concat_vec imm5 imm40  ::  6 Word.word),rsd)))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (imm5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (imm40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None
      else Some (C_LI ((concat_vec imm5 imm40  ::  6 Word.word),rd)))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
-     (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
-     (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word)) in
-     (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)))))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
+     (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii)  ::  1 Word.word)) in
+     (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word)) in
+     (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
      (let nzimm =
        ((concat_vec nzi9
           ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4  ::  2 Word.word))  ::  3 Word.word))
@@ -6148,65 +12773,65 @@ definition decodeCompressed  :: "(16)Word.word \<Rightarrow>(ast)option "  where
          ::  6 Word.word)) in
      if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) then None
      else Some (C_ADDI16SP nzimm)))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (imm17 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (imm17 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then
        None
      else Some (C_LUI ((concat_vec imm17 imm1612  ::  6 Word.word),rd)))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40  ::  6 Word.word)) in
      if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) then None
      else Some (C_SRLI (shamt,rsd))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40  ::  6 Word.word)) in
      if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) then None
      else Some (C_SRAI (shamt,rsd))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (i40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B0]  ::  3 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (i40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      Some (C_ANDI ((concat_vec i5 i40  ::  6 Word.word),rsd)))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      Some (C_SUB (rsd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      Some (C_XOR (rsd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      Some (C_OR (rsd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      Some (C_AND (rsd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      Some (C_SUBW (rsd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
-     (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii)  ::  6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1]  ::  6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))))))))) then
+     (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      Some (C_ADDW (rsd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (i11 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (i4 :: 1 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word)) in
-     (let (i98 :: 2 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 9 :: int)::ii)  ::  2 Word.word)) in
-     (let (i10 :: 1 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word)) in
-     (let (i6 :: 1 bits) = ((subrange_vec_dec v__418 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
-     (let (i7 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
-     (let (i31 :: 3 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
-     (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B0,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (i11 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (i4 :: 1 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word)) in
+     (let (i98 :: 2 bits) = ((subrange_vec_dec v__2 (( 10 :: int)::ii) (( 9 :: int)::ii)  ::  2 Word.word)) in
+     (let (i10 :: 1 bits) = ((subrange_vec_dec v__2 (( 8 :: int)::ii) (( 8 :: int)::ii)  ::  1 Word.word)) in
+     (let (i6 :: 1 bits) = ((subrange_vec_dec v__2 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
+     (let (i7 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii)  ::  1 Word.word)) in
+     (let (i31 :: 3 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 3 :: int)::ii)  ::  3 Word.word)) in
+     (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
      Some (C_J ((concat_vec i11
                    ((concat_vec i10
                        ((concat_vec i98
@@ -6218,108 +12843,110 @@ definition decodeCompressed  :: "(16)Word.word \<Rightarrow>(ast)option "  where
                           ::  9 Word.word))
                       ::  10 Word.word))
                   ::  11 Word.word)))))))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) in
-     (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
-     (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word)) in
-     (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (i8 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (i43 :: 2 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) in
+     (let (rs :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (i76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let (i21 :: 2 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word)) in
+     (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
      Some (C_BEQZ ((concat_vec i8
                       ((concat_vec i76
                           ((concat_vec i5 ((concat_vec i43 i21  ::  4 Word.word))  ::  5 Word.word))
                          ::  7 Word.word))
                      ::  8 Word.word),rs))))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
-     (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) in
-     (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
-     (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word)) in
-     (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+     (let (i8 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (i43 :: 2 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii)  ::  2 Word.word)) in
+     (let (rs :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (i76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let (i21 :: 2 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 3 :: int)::ii)  ::  2 Word.word)) in
+     (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii)  ::  1 Word.word)) in
      Some (C_BNEZ ((concat_vec i8
                       ((concat_vec i76
                           ((concat_vec i5 ((concat_vec i43 i21  ::  4 Word.word))  ::  5 Word.word))
                          ::  7 Word.word))
                      ::  8 Word.word),rs))))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40  ::  6 Word.word)) in
      if ((((((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)))) \<or> (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then
        None
      else Some (C_SLLI (shamt,rsd))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (ui42 :: 3 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 4 :: int)::ii)  ::  3 Word.word)) in
-     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (ui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (ui42 :: 3 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 4 :: int)::ii)  ::  3 Word.word)) in
+     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 3 :: int)::ii) (( 2 :: int)::ii)  ::  2 Word.word)) in
      (let (uimm :: 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42  ::  4 Word.word))  ::  6 Word.word)) in
      if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None
      else Some (C_LWSP (uimm,rd)))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (ui43 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
-     (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (ui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (ui43 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let (ui86 :: 3 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
      (let (uimm :: 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43  ::  3 Word.word))  ::  6 Word.word)) in
      if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None
      else Some (C_LDSP (uimm,rd)))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (ui52 :: 4 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 9 :: int)::ii)  ::  4 Word.word)) in
-     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 7 :: int)::ii)  ::  2 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (ui52 :: 4 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 9 :: int)::ii)  ::  4 Word.word)) in
+     (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 8 :: int)::ii) (( 7 :: int)::ii)  ::  2 Word.word)) in
+     (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      (let (uimm :: 6 bits) = ((concat_vec ui76 ui52  ::  6 Word.word)) in
      Some (C_SWSP (uimm,rs2))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
-     (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B1,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii)  ::  3 Word.word)) in
+     (let (ui86 :: 3 bits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii)  ::  3 Word.word)) in
+     (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      (let (uimm :: 6 bits) = ((concat_vec ui86 ui53  ::  6 Word.word)) in
      Some (C_SDSP (uimm,rs2))))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0]  ::  7 Word.word))))))) then
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0]  ::  7 Word.word))))))) then
+     (let (rs1 :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
      if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None
      else Some (C_JR rs1))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0]  ::  7 Word.word))))))) then
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0]  ::  7 Word.word))))))) then
+     (let (rs1 :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
      if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None
      else Some (C_JALR rs1))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B0]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then
        None
      else Some (C_MV (rd,rs2))))
-   else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
-     (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
+   else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii)  ::  4 Word.word)) = (vec_of_bits [B1,B0,B0,B1]  ::  4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+     (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii)  ::  5 Word.word)) in
      if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then
        None
      else Some (C_ADD (rsd,rs2))))
+   else if (((v__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  16 Word.word)))) then
+     Some (C_ILLEGAL () )
    else None )"
 
 
-(*val execute_WFI : unit -> M unit*)
+(*val execute_WFI : unit -> M bool*)
 
-fun  execute_WFI  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_WFI g__110 = (
+fun  execute_WFI  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_WFI g__26 = (
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . 
    (case  w__0 of
-     Machine => return () 
+     Machine => return True
    | Supervisor =>
       read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . 
       if (((((get_Mstatus_TW w__1  ::  1 Word.word)) = ((bool_to_bits True  ::  1 Word.word))))) then
-        handle_illegal () 
-      else return () )
-   | User => handle_illegal () 
+        handle_illegal ()  \<then> return False
+      else return True)
+   | User => handle_illegal ()  \<then> return False
    )))"
 
 
-(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*)
+(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M bool*)
 
-fun  execute_UTYPE  :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_UTYPE  :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_UTYPE imm rd op1 = (
    (let (off :: xlenbits) =
      ((EXTS (( 64 :: int)::ii)
@@ -6332,93 +12959,122 @@ fun  execute_UTYPE  :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uo
       (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
       return ((add_vec w__0 off  ::  64 Word.word)))
    ) \<bind> (\<lambda> (ret :: xlenbits) . 
-   wX ((regbits_to_regno rd)) ret)))"
+   wX ((regbits_to_regno rd)) ret \<then> return True)))"
 
 
-(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*)
+(*val execute_THREAD_START : unit -> bool*)
 
-fun  execute_STORECON  :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_THREAD_START  :: " unit \<Rightarrow> bool "  where 
+     " execute_THREAD_START g__29 = ( True )"
+
+
+(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*)
+
+fun  execute_STORECON  :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_STORECON aq rl rs2 rs1 width rd = (
-   speculate_conditional_success ()  \<bind> (\<lambda> (w__0 :: bool) . 
-   (let (status :: 1 bits) =
-     (if w__0 then (vec_of_bits [B0]  ::  1 Word.word)
-     else (vec_of_bits [B1]  ::  1 Word.word)) in
-   wX ((regbits_to_regno rd)) ((EXTZ (( 64 :: int)::ii) status  ::  64 Word.word)) \<then>
-   (if (((status = (vec_of_bits [B1]  ::  1 Word.word)))) then return () 
+   (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . 
+   (let (aligned :: bool) =
+     ((case  width of
+       BYTE => True
+     | HALF =>
+        (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii)))  ::  1 Word.word)) = (vec_of_bits [B0]  ::  1 Word.word))
+     | WORD =>
+        (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))
+     | DOUBLE =>
+        (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))
+     )) in
+   if ((\<not> aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return False
+   else
+     speculate_conditional_success vaddr \<bind> (\<lambda> (w__0 :: bool) . 
+     if (((((bool_to_bits w__0  ::  1 Word.word)) = ((bool_to_bits False  ::  1 Word.word))))) then
+       wX ((regbits_to_regno rd)) ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B1]  ::  1 Word.word)  ::  64 Word.word)) \<then>
+       return True
+     else
+       translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . 
+       (case  w__1 of
+         TR_Failure (e) => handle_mem_exception vaddr e \<then> return False
+       | TR_Address (addr) =>
+          (case  width of
+            WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl True
+          | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl True
+          | _ => internal_error (''STORECON expected word or double'')
+          ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . 
+          (case  eares of
+            MemException (e) => handle_mem_exception addr e \<then> return False
+          | MemValue (_) =>
+             (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
+             (case  width of
+               WORD =>
+                mem_write_value addr (( 4 :: int)::ii)
+                  ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) aq rl True
+             | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True
+             | _ => internal_error (''STORECON expected word or double'')
+             ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . 
+             (case  res of
+               MemValue (_) =>
+                wX ((regbits_to_regno rd))
+                  ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0]  ::  1 Word.word)  ::  64 Word.word)) \<then>
+                ((let (_ :: unit) = (cancel_reservation () ) in
+                return True))
+             | MemException (e) => handle_mem_exception addr e \<then> return False
+             )))
+          ))
+       ))))))"
+
+
+(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M bool*)
+
+fun  execute_STORE  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_STORE imm rs2 rs1 width aq rl = (
+   (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word)) in
+   if ((check_misaligned vaddr width)) then
+     handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return False
    else
-     (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . 
      translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . 
      (case  w__1 of
-       TR_Failure (e) => handle_mem_exception vaddr e
+       TR_Failure (e) => handle_mem_exception vaddr e \<then> return False
      | TR_Address (addr) =>
         (case  width of
-          WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl True
-        | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl True
-        | _ => internal_error (''STORECON expected word or double'')
+          BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False
+        | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False
+        | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False
+        | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False
         ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . 
         (case  eares of
-          MemException (e) => handle_mem_exception addr e
+          MemException (e) => handle_mem_exception addr e \<then> return False
         | MemValue (_) =>
            (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
            (case  width of
-             WORD =>
+             BYTE =>
+              mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word)) aq
+                rl False
+           | HALF =>
+              mem_write_value addr (( 2 :: int)::ii) ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))
+                aq rl False
+           | WORD =>
               mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))
-                aq rl True
-           | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True
-           | _ => internal_error (''STORECON expected word or double'')
+                aq rl False
+           | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl False
            ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . 
            (case  res of
-             MemValue (_) => return () 
-           | MemException (e) => handle_mem_exception addr e
+             MemValue (_) => return True
+           | MemException (e) => handle_mem_exception addr e \<then> return False
            )))
         ))
-     )))))))"
+     )))))"
 
 
-(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*)
+(*val execute_STOP_FETCHING : unit -> bool*)
 
-fun  execute_STORE  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_STORE imm rs2 rs1 width aq rl = (
-   (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word)) in
-   translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . 
-   (case  w__1 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) =>
-      (case  width of
-        BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False
-      | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False
-      | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False
-      | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False
-      ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . 
-      (case  eares of
-        MemException (e) => handle_mem_exception addr e
-      | MemValue (_) =>
-         (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
-         (case  width of
-           BYTE =>
-            mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii)  ::  8 Word.word)) aq
-              rl False
-         | HALF =>
-            mem_write_value addr (( 2 :: int)::ii) ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word)) aq
-              rl False
-         | WORD =>
-            mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) aq
-              rl False
-         | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl False
-         ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . 
-         (case  res of
-           MemValue (_) => return () 
-         | MemException (e) => handle_mem_exception addr e
-         )))
-      ))
-   )))))"
+fun  execute_STOP_FETCHING  :: " unit \<Rightarrow> bool "  where 
+     " execute_STOP_FETCHING g__28 = ( True )"
 
 
-(*val execute_SRET : unit -> M unit*)
+(*val execute_SRET : unit -> M bool*)
 
-fun  execute_SRET  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_SRET g__108 = (
+fun  execute_SRET  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_SRET g__24 = (
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . 
    (case  w__0 of
      User => handle_illegal () 
@@ -6436,12 +13092,13 @@ fun  execute_SRET  :: " unit \<Rightarrow>((register_value),(unit),(exception))m
       (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 ::  64 Word.word) . 
       (handle_exception w__5 (CTL_SRET () ) w__6  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: xlenbits) . 
       write_reg nextPC_ref w__7)))
-   )))"
+   ) \<then>
+   return False))"
 
 
-(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*)
+(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M bool*)
 
-fun  execute_SHIFTW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_SHIFTW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_SHIFTW shamt rs1 rd op1 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
@@ -6451,12 +13108,12 @@ fun  execute_SHIFTW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)
      | RISCV_SRLI => (shift_bits_right rs1_val shamt  ::  32 Word.word)
      | RISCV_SRAI => (shift_right_arith32 rs1_val shamt  ::  32 Word.word)
      )) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result  ::  64 Word.word))))))"
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result  ::  64 Word.word)) \<then> return True))))"
 
 
-(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*)
+(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M bool*)
 
-fun  execute_SHIFTIOP  :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_SHIFTIOP  :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_SHIFTIOP shamt rs1 rd op1 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (let (result :: xlenbits) =
@@ -6465,26 +13122,26 @@ fun  execute_SHIFTIOP  :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(
      | RISCV_SRLI => (shift_bits_right rs1_val shamt  ::  64 Word.word)
      | RISCV_SRAI => (shift_right_arith64 rs1_val shamt  ::  64 Word.word)
      )) in
-   wX ((regbits_to_regno rd)) result)))"
+   wX ((regbits_to_regno rd)) result \<then> return True)))"
 
 
-(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*)
+(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M bool*)
 
-fun  execute_SFENCE_VMA  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_SFENCE_VMA  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_SFENCE_VMA rs1 rs2 = (
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . 
    if (((((privLevel_to_bits w__0  ::  2 Word.word)) = ((privLevel_to_bits User  ::  2 Word.word)))))
    then
-     handle_illegal () 
+     handle_illegal ()  \<then> return False
    else
      read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . 
      read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . 
-     (let p__104 =
+     (let p__20 =
        (architecture ((get_Mstatus_SXL w__1  ::  2 Word.word)), (get_Mstatus_TVM w__2  ::  1 Word.word)) in
-     (case  p__104 of
+     (case  p__20 of
        (Some (RV64), v_0) =>
-        if (((v_0 = ((bool_to_bits True  ::  1 Word.word))))) then handle_illegal () 
-        else
+        if (((v_0 = ((bool_to_bits True  ::  1 Word.word))))) then handle_illegal ()  \<then> return False
+        else if (((v_0 = ((bool_to_bits False  ::  1 Word.word))))) then
           (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then return None
            else
              (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 ::  64 Word.word) . 
@@ -6495,14 +13152,18 @@ fun  execute_SFENCE_VMA  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow
              (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 ::  64 Word.word) . 
              return (Some ((subrange_vec_dec w__4 (( 15 :: int)::ii) (( 0 :: int)::ii)  ::  16 Word.word))))) \<bind> (\<lambda> (asid ::
              asid64 option) . 
-          flushTLB asid addr))
-     | (g__102, g__103) => internal_error (''unimplemented sfence architecture'')
+          flushTLB asid addr \<then> return True))
+        else
+          (case  (Some RV64, v_0) of
+            (g__18, g__19) => internal_error (''unimplemented sfence architecture'')
+          )
+     | (g__18, g__19) => internal_error (''unimplemented sfence architecture'')
      ))))))"
 
 
-(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*)
+(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M bool*)
 
-fun  execute_RTYPEW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_RTYPEW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_RTYPEW rs2 rs1 rd op1 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
@@ -6522,12 +13183,12 @@ fun  execute_RTYPEW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)
         (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word))
           ::  32 Word.word)
      )) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result  ::  64 Word.word))))))))"
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result  ::  64 Word.word)) \<then> return True))))))"
 
 
-(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*)
+(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M bool*)
 
-fun  execute_RTYPE  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_RTYPE  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_RTYPE rs2 rs1 rd op1 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
@@ -6552,12 +13213,12 @@ fun  execute_RTYPE  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)W
      | RISCV_OR => (or_vec rs1_val rs2_val  ::  64 Word.word)
      | RISCV_AND => (and_vec rs1_val rs2_val  ::  64 Word.word)
      )) in
-   wX ((regbits_to_regno rd)) result))))"
+   wX ((regbits_to_regno rd)) result \<then> return True))))"
 
 
-(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M bool*)
 
-fun  execute_RISCV_JALR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_RISCV_JALR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_RISCV_JALR imm rs1 rd = (
    (read_reg nextPC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (wX ((regbits_to_regno rd)) w__0 \<then>
@@ -6567,23 +13228,24 @@ fun  execute_RISCV_JALR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarro
      nextPC_ref
      ((concat_vec ((subrange_vec_dec newPC (( 63 :: int)::ii) (( 1 :: int)::ii)  ::  63 Word.word))
          (vec_of_bits [B0]  ::  1 Word.word)
-        ::  64 Word.word))))))"
+        ::  64 Word.word)) \<then>
+   return True))))"
 
 
-(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*)
+(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M bool*)
 
-fun  execute_RISCV_JAL  :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_RISCV_JAL  :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_RISCV_JAL imm rd = (
    (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (pc :: xlenbits) . 
    (read_reg nextPC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    wX ((regbits_to_regno rd)) w__0 \<then>
    ((let (offset :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) in
-   write_reg nextPC_ref ((add_vec pc offset  ::  64 Word.word)))))))"
+   write_reg nextPC_ref ((add_vec pc offset  ::  64 Word.word)) \<then> return True)))))"
 
 
-(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
-fun  execute_REMW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_REMW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_REMW rs2 rs1 rd s = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
@@ -6592,30 +13254,31 @@ fun  execute_REMW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo
    (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
    (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
    (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r  ::  32 Word.word))  ::  64 Word.word))))))))))"
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r  ::  32 Word.word))  ::  64 Word.word)) \<then>
+   return True))))))))"
 
 
-(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
-fun  execute_REM  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_REM  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_REM rs2 rs1 rd s = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
    (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
    (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
    (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
-   wX ((regbits_to_regno rd)) ((to_bits xlen r  ::  64 Word.word))))))))"
+   wX ((regbits_to_regno rd)) ((to_bits xlen r  ::  64 Word.word)) \<then> return True))))))"
 
 
-(*val execute_NOP : unit -> unit*)
+(*val execute_NOP : unit -> bool*)
 
-fun  execute_NOP  :: " unit \<Rightarrow> unit "  where 
-     " execute_NOP g__111 = ( ()  )"
+fun  execute_NOP  :: " unit \<Rightarrow> bool "  where 
+     " execute_NOP g__27 = ( True )"
 
 
-(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*)
+(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M bool*)
 
-fun  execute_MULW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_MULW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_MULW rs2 rs1 rd = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
@@ -6628,12 +13291,12 @@ fun  execute_MULW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo
         (( 0 :: int)::ii)
        ::  32 Word.word)) in
    (let (result :: xlenbits) = ((EXTS (( 64 :: int)::ii) result32  ::  64 Word.word)) in
-   wX ((regbits_to_regno rd)) result)))))))))"
+   wX ((regbits_to_regno rd)) result \<then> return True)))))))))"
 
 
-(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*)
+(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M bool*)
 
-fun  execute_MUL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_MUL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_MUL rs2 rs1 rd high signed1 signed2 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
@@ -6643,80 +13306,96 @@ fun  execute_MUL  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wor
    (let result =
      (if high then (subrange_vec_dec result128 (( 127 :: int)::ii) (( 64 :: int)::ii)  ::  64 Word.word)
      else (subrange_vec_dec result128 (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)) in
-   wX ((regbits_to_regno rd)) result)))))))"
+   wX ((regbits_to_regno rd)) result \<then> return True)))))))"
 
 
-(*val execute_MRET : unit -> M unit*)
+(*val execute_MRET : unit -> M bool*)
 
-fun  execute_MRET  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_MRET g__107 = (
+fun  execute_MRET  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_MRET g__23 = (
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . 
-   if (((((privLevel_to_bits w__0  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word)))))
-   then
-     read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . 
-     (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
-     (handle_exception w__1 (CTL_MRET () ) w__2  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . 
-     write_reg nextPC_ref w__3)))
-   else handle_illegal () ))"
+   (if (((((privLevel_to_bits w__0  ::  2 Word.word)) = ((privLevel_to_bits Machine  ::  2 Word.word)))))
+    then
+      read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . 
+      (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
+      (handle_exception w__1 (CTL_MRET () ) w__2  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . 
+      write_reg nextPC_ref w__3)))
+    else handle_illegal () ) \<then>
+   return False))"
 
 
-(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*)
+(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M bool*)
 
-fun  execute_LOADRES  :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_LOADRES  :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_LOADRES aq rl rs1 width rd = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . 
-   translateAddr vaddr Read Data \<bind> (\<lambda> (w__0 :: TR_Result) . 
-   (case  w__0 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) =>
-      (case  width of
-        WORD =>
-         (mem_read addr (( 4 :: int)::ii) aq rl True  :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__1 :: ( 32 Word.word)
-           MemoryOpResult) . 
-         process_load rd addr w__1 False)
-      | DOUBLE =>
-         (mem_read addr (( 8 :: int)::ii) aq rl True  :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 64 Word.word)
-           MemoryOpResult) . 
-         process_load rd addr w__2 False)
-      | _ => internal_error (''LOADRES expected WORD or DOUBLE'')
-      )
-   ))))"
+   (let (aligned :: bool) =
+     ((case  width of
+       BYTE => True
+     | HALF =>
+        (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii)))  ::  1 Word.word)) = (vec_of_bits [B0]  ::  1 Word.word))
+     | WORD =>
+        (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))
+     | DOUBLE =>
+        (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))
+     )) in
+   if ((\<not> aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return False
+   else
+     translateAddr vaddr Read Data \<bind> (\<lambda> (w__0 :: TR_Result) . 
+     (case  w__0 of
+       TR_Failure (e) => handle_mem_exception vaddr e \<then> return False
+     | TR_Address (addr) =>
+        (case  width of
+          WORD =>
+           (mem_read addr (( 4 :: int)::ii) aq rl True  :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__1 :: ( 32 Word.word)
+             MemoryOpResult) . 
+           process_loadres rd vaddr w__1 False)
+        | DOUBLE =>
+           (mem_read addr (( 8 :: int)::ii) aq rl True  :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 64 Word.word)
+             MemoryOpResult) . 
+           process_loadres rd vaddr w__3 False)
+        | _ => internal_error (''LOADRES expected WORD or DOUBLE'')
+        )
+     )))))"
 
 
-(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*)
+(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M bool*)
 
-fun  execute_LOAD  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_LOAD  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_LOAD imm rs1 rd is_unsigned width aq rl = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word)) in
-   translateAddr vaddr Read Data \<bind> (\<lambda> (w__1 :: TR_Result) . 
-   (case  w__1 of
-     TR_Failure (e) => handle_mem_exception vaddr e
-   | TR_Address (addr) =>
-      (case  width of
-        BYTE =>
-         (mem_read addr (( 1 :: int)::ii) aq rl False  :: ( ( 8 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 8 Word.word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__2 is_unsigned)
-      | HALF =>
-         (mem_read addr (( 2 :: int)::ii) aq rl False  :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 16 Word.word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__3 is_unsigned)
-      | WORD =>
-         (mem_read addr (( 4 :: int)::ii) aq rl False  :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 32 Word.word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__4 is_unsigned)
-      | DOUBLE =>
-         (mem_read addr (( 8 :: int)::ii) aq rl False  :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__5 :: ( 64 Word.word)
-           MemoryOpResult) . 
-         process_load rd vaddr w__5 is_unsigned)
-      )
-   )))))"
+   if ((check_misaligned vaddr width)) then
+     handle_mem_exception vaddr E_Load_Addr_Align \<then> return False
+   else
+     translateAddr vaddr Read Data \<bind> (\<lambda> (w__1 :: TR_Result) . 
+     (case  w__1 of
+       TR_Failure (e) => handle_mem_exception vaddr e \<then> return False
+     | TR_Address (addr) =>
+        (case  width of
+          BYTE =>
+           (mem_read addr (( 1 :: int)::ii) aq rl False  :: ( ( 8 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 8 Word.word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__2 is_unsigned)
+        | HALF =>
+           (mem_read addr (( 2 :: int)::ii) aq rl False  :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 16 Word.word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__4 is_unsigned)
+        | WORD =>
+           (mem_read addr (( 4 :: int)::ii) aq rl False  :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__6 :: ( 32 Word.word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__6 is_unsigned)
+        | DOUBLE =>
+           (mem_read addr (( 8 :: int)::ii) aq rl False  :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__8 :: ( 64 Word.word)
+             MemoryOpResult) . 
+           process_load rd vaddr w__8 is_unsigned)
+        )
+     )))))"
 
 
-(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*)
+(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M bool*)
 
-fun  execute_ITYPE  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_ITYPE  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_ITYPE imm rs1 rd op1 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (let (immext :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) in
@@ -6731,40 +13410,59 @@ fun  execute_ITYPE  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)
      | RISCV_ORI => (or_vec rs1_val immext  ::  64 Word.word)
      | RISCV_ANDI => (and_vec rs1_val immext  ::  64 Word.word)
      )) in
-   wX ((regbits_to_regno rd)) result))))"
+   wX ((regbits_to_regno rd)) result \<then> return True))))"
 
 
-(*val execute_ILLEGAL : unit -> M unit*)
+(*val execute_ILLEGAL : mword ty32 -> M bool*)
 
-fun  execute_ILLEGAL  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_ILLEGAL g__112 = ( handle_illegal ()  )"
+fun  execute_ILLEGAL  :: "(32)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_ILLEGAL s = ( handle_illegal ()  \<then> return False )"
 
 
-(*val execute_FENCEI : unit -> M unit*)
+(*val execute_FENCEI : unit -> M bool*)
 
-fun  execute_FENCEI  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_FENCEI g__105 = ( MEM_fence_i ()  )"
+fun  execute_FENCEI  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_FENCEI g__21 = ( MEM_fence_i ()  \<then> return True )"
 
 
-(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*)
+(*val execute_FENCE : mword ty4 -> mword ty4 -> M bool*)
 
-fun  execute_FENCE  :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_FENCE b__0 b__1 = (
-      if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word))))))) then
+fun  execute_FENCE  :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_FENCE pred succ = (
+   (case  (pred, succ) of
+     (v__132, v__133) =>
+      if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) then
         MEM_fence_rw_rw () 
-      else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word))))))) then
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) then
         MEM_fence_r_rw () 
-      else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B0]  ::  4 Word.word))))))) then
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
         MEM_fence_r_r () 
-      else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1]  ::  4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B0,B1]  ::  4 Word.word))))))) then
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
         MEM_fence_rw_w () 
-      else MEM_fence_w_w ()  )"
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+        MEM_fence_w_w () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) then
+        MEM_fence_w_rw () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+        MEM_fence_rw_r () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+        MEM_fence_r_w () 
+      else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+        MEM_fence_w_r () 
+      else
+        return (if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+                  () 
+                else
+                  (let (_ :: unit) = (print_endline (''FIXME: unsupported fence'')) in
+                  () ))
+   ) \<then>
+   return True )"
 
 
-(*val execute_ECALL : unit -> M unit*)
+(*val execute_ECALL : unit -> M bool*)
 
-fun  execute_ECALL  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_ECALL g__106 = (
+fun  execute_ECALL  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_ECALL g__22 = (
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . 
    (let (t :: sync_exception) =
      ((| sync_exception_trap =
@@ -6777,18 +13475,20 @@ fun  execute_ECALL  :: " unit \<Rightarrow>((register_value),(unit),(exception))
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . 
    (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 ::  64 Word.word) . 
    (handle_exception w__1 (CTL_TRAP t) w__2  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . 
-   write_reg nextPC_ref w__3))))))"
+   write_reg nextPC_ref w__3 \<then> return False))))))"
 
 
-(*val execute_EBREAK : unit -> M unit*)
+(*val execute_EBREAK : unit -> M bool*)
 
-fun  execute_EBREAK  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
-     " execute_EBREAK g__109 = ( throw (Error_EBREAK () ))"
+fun  execute_EBREAK  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_EBREAK g__25 = (
+   (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+   handle_mem_exception w__0 E_Breakpoint \<then> return False))"
 
 
-(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
-fun  execute_DIVW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_DIVW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_DIVW rs2 rs1 rd s = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) in
@@ -6801,12 +13501,13 @@ fun  execute_DIVW  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo
      (if (((s \<and> ((q > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then
        (( 0 :: int)::ii) - ((ex_int ((pow (( 2 :: int)::ii) (( 31 :: int)::ii)))))
      else q) in
-   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q'  ::  32 Word.word))  ::  64 Word.word)))))))))))"
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q'  ::  32 Word.word))  ::  64 Word.word)) \<then>
+   return True)))))))))"
 
 
-(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*)
+(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*)
 
-fun  execute_DIV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_DIV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_DIV rs2 rs1 rd s = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
@@ -6814,23 +13515,29 @@ fun  execute_DIV  :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wor
    (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
    (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in
    (let (q' :: ii) = (if (((s \<and> ((q > xlen_max_signed))))) then xlen_min_signed else q) in
-   wX ((regbits_to_regno rd)) ((to_bits xlen q'  ::  64 Word.word)))))))))"
+   wX ((regbits_to_regno rd)) ((to_bits xlen q'  ::  64 Word.word)) \<then> return True)))))))"
+
 
+(*val execute_C_ILLEGAL : unit -> M bool*)
 
-(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*)
+fun  execute_C_ILLEGAL  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
+     " execute_C_ILLEGAL g__30 = ( handle_illegal ()  \<then> return False )"
 
-fun  execute_C_ADDIW  :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+
+(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M bool*)
+
+fun  execute_C_ADDIW  :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_C_ADDIW imm rsd = (
    (let (imm :: 32 bits) = ((EXTS (( 32 :: int)::ii) imm  ::  32 Word.word)) in
    (rX ((regbits_to_regno rsd))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . 
    (let (res :: 32 bits) =
      ((add_vec ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)) imm  ::  32 Word.word)) in
-   wX ((regbits_to_regno rsd)) ((EXTS (( 64 :: int)::ii) res  ::  64 Word.word))))))"
+   wX ((regbits_to_regno rsd)) ((EXTS (( 64 :: int)::ii) res  ::  64 Word.word)) \<then> return True))))"
 
 
-(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*)
+(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M bool*)
 
-fun  execute_CSR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_CSR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_CSR csr rs1 rd is_imm op1 = (
    (if is_imm then return ((EXTZ (( 64 :: int)::ii) rs1  ::  64 Word.word))
     else (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M)) \<bind> (\<lambda> (rs1_val :: xlenbits) . 
@@ -6841,10 +13548,10 @@ fun  execute_CSR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo
      )) in
    read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . 
    check_CSR csr w__1 isWrite \<bind> (\<lambda> (w__2 :: bool) . 
-   if ((\<not> w__2)) then handle_illegal () 
+   if ((\<not> w__2)) then handle_illegal ()  \<then> return False
    else
      (readCSR csr  :: ( 64 Word.word) M) \<bind> (\<lambda> csr_val . 
-     (if isWrite then
+     ((if isWrite then
         (let (new_val :: xlenbits) =
           ((case  op1 of
             CSRRW => rs1_val
@@ -6853,12 +13560,12 @@ fun  execute_CSR  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo
           )) in
         writeCSR csr new_val)
       else return () ) \<then>
-     wX ((regbits_to_regno rd)) csr_val))))))"
+     wX ((regbits_to_regno rd)) csr_val) \<then> return True))))))"
 
 
-(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*)
+(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M bool*)
 
-fun  execute_BTYPE  :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_BTYPE  :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_BTYPE imm rs2 rs1 op1 = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
    (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . 
@@ -6871,20 +13578,21 @@ fun  execute_BTYPE  :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)
      | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
      | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
      )) in
-   if taken then
-     (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-     write_reg nextPC_ref ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word)))
-   else return () ))))"
+   (if taken then
+      (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+      write_reg nextPC_ref ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word)))
+    else return () ) \<then>
+   return True))))"
 
 
-(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*)
+(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*)
 
-fun  execute_AMO  :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_AMO  :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_AMO op1 aq rl rs2 rs1 width rd = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . 
    translateAddr vaddr ReadWrite Data \<bind> (\<lambda> (w__0 :: TR_Result) . 
    (case  w__0 of
-     TR_Failure (e) => handle_mem_exception vaddr e
+     TR_Failure (e) => handle_mem_exception vaddr e \<then> return False
    | TR_Address (addr) =>
       (case  width of
         WORD => mem_write_ea addr (( 4 :: int)::ii) (((aq \<and> rl))) rl True
@@ -6892,7 +13600,7 @@ fun  execute_AMO  :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>
       | _ => internal_error (''AMO expected WORD or DOUBLE'')
       ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . 
       (case  eares of
-        MemException (e) => handle_mem_exception addr e
+        MemException (e) => handle_mem_exception addr e \<then> return False
       | MemValue (_) =>
          (case  width of
            WORD =>
@@ -6906,7 +13614,7 @@ fun  execute_AMO  :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>
          | _ => (internal_error (''AMO expected WORD or DOUBLE'')  :: ( ( 64 Word.word)MemoryOpResult) M)
          ) \<bind> (\<lambda> (rval :: xlenbits MemoryOpResult) . 
          (case  rval of
-           MemException (e) => handle_mem_exception addr e
+           MemException (e) => handle_mem_exception addr e \<then> return False
          | MemValue (loaded) =>
             (rX ((regbits_to_regno rs2))  :: ( 64 Word.word) M) \<bind> (\<lambda> (rs2_val :: xlenbits) . 
             (let (result :: xlenbits) =
@@ -6929,25 +13637,26 @@ fun  execute_AMO  :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>
             | _ => internal_error (''AMO expected WORD or DOUBLE'')
             ) \<bind> (\<lambda> (wval :: unit MemoryOpResult) . 
             (case  wval of
-              MemValue (_) => wX ((regbits_to_regno rd)) loaded
-            | MemException (e) => handle_mem_exception addr e
+              MemValue (_) => wX ((regbits_to_regno rd)) loaded \<then> return True
+            | MemException (e) => handle_mem_exception addr e \<then> return False
             ))))
          ))
       ))
    ))))"
 
 
-(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
+(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M bool*)
 
-fun  execute_ADDIW  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+fun  execute_ADDIW  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute_ADDIW imm rs1 rd = (
    (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
    (let (result :: xlenbits) = ((add_vec ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) w__0  ::  64 Word.word)) in
    wX ((regbits_to_regno rd))
-     ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)))))"
+     ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word))  ::  64 Word.word)) \<then>
+   return True)))"
 
 
-function (sequential,domintros)  execute  :: " ast \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+function (sequential,domintros)  execute  :: " ast \<Rightarrow>((register_value),(bool),(exception))monad "  where 
      " execute (C_ADDI4SPN (rdc,nzimm)) = (
       (let (imm :: 12 bits) =
         ((concat_vec (vec_of_bits [B0,B0]  ::  2 Word.word)
@@ -7092,307 +13801,10037 @@ function (sequential,domintros)  execute  :: " ast \<Rightarrow>((register_value
 |" execute (DIVW (rs2,rs1,rd,s)) = ( execute_DIVW rs2 rs1 rd s )"
 |" execute (REMW (rs2,rs1,rd,s)) = ( execute_REMW rs2 rs1 rd s )"
 |" execute (FENCE (pred,succ)) = ( execute_FENCE pred succ )"
-|" execute (FENCEI (g__105)) = ( execute_FENCEI g__105 )"
-|" execute (ECALL (g__106)) = ( execute_ECALL g__106 )"
-|" execute (MRET (g__107)) = ( execute_MRET g__107 )"
-|" execute (SRET (g__108)) = ( execute_SRET g__108 )"
-|" execute (EBREAK (g__109)) = ( execute_EBREAK g__109 )"
-|" execute (WFI (g__110)) = ( execute_WFI g__110 )"
+|" execute (FENCEI (g__21)) = ( execute_FENCEI g__21 )"
+|" execute (ECALL (g__22)) = ( execute_ECALL g__22 )"
+|" execute (MRET (g__23)) = ( execute_MRET g__23 )"
+|" execute (SRET (g__24)) = ( execute_SRET g__24 )"
+|" execute (EBREAK (g__25)) = ( execute_EBREAK g__25 )"
+|" execute (WFI (g__26)) = ( execute_WFI g__26 )"
 |" execute (SFENCE_VMA (rs1,rs2)) = ( execute_SFENCE_VMA rs1 rs2 )"
 |" execute (LOADRES (aq,rl,rs1,width,rd)) = ( execute_LOADRES aq rl rs1 width rd )"
 |" execute (STORECON (aq,rl,rs2,rs1,width,rd)) = ( execute_STORECON aq rl rs2 rs1 width rd )"
 |" execute (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( execute_AMO op1 aq rl rs2 rs1 width rd )"
 |" execute (CSR (csr,rs1,rd,is_imm,op1)) = ( execute_CSR csr rs1 rd is_imm op1 )"
-|" execute (NOP (g__111)) = ( return ((execute_NOP g__111)))"
-|" execute (ILLEGAL (g__112)) = ( execute_ILLEGAL g__112 )"
-|" execute (C_ADDIW (imm,rsd)) = ( execute_C_ADDIW imm rsd )" 
+|" execute (NOP (g__27)) = ( return ((execute_NOP g__27)))"
+|" execute (C_ADDIW (imm,rsd)) = ( execute_C_ADDIW imm rsd )"
+|" execute (STOP_FETCHING (g__28)) = ( return ((execute_STOP_FETCHING g__28)))"
+|" execute (THREAD_START (g__29)) = ( return ((execute_THREAD_START g__29)))"
+|" execute (ILLEGAL (s)) = ( execute_ILLEGAL s )"
+|" execute (C_ILLEGAL (g__30)) = ( execute_C_ILLEGAL g__30 )" 
 by pat_completeness auto
 
 
+(*val assembly_forwards : ast -> string*)
+
+fun assembly_forwards  :: " ast \<Rightarrow> string "  where 
+     " assembly_forwards (UTYPE (imm,rd,op1)) = (
+      string_append ((utype_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) (''''))))))))))"
+|" assembly_forwards (RISCV_JAL (imm,rd)) = (
+      string_append (''jal'')
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) (''''))))))))))"
+|" assembly_forwards (RISCV_JALR (imm,rs1,rd)) = (
+      string_append (''jalr'')
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) (''''))))))))))))))"
+|" assembly_forwards (BTYPE (imm,rs2,rs1,op1)) = (
+      string_append ((btype_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rs1))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs2))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) (''''))))))))))))))"
+|" assembly_forwards (ITYPE (imm,rs1,rd,op1)) = (
+      string_append ((itype_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) (''''))))))))))))))"
+|" assembly_forwards (SHIFTIOP (shamt,rs1,rd,op1)) = (
+      string_append ((shiftiop_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((string_of_bits shamt)) (''''))))))))))))"
+|" assembly_forwards (RTYPE (rs2,rs1,rd,op1)) = (
+      string_append ((rtype_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))"
+|" assembly_forwards (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)) = (
+      string_append (''l'')
+        ((string_append ((size_mnemonic_forwards size1))
+            ((string_append ((maybe_u_forwards is_unsigned))
+                ((string_append ((maybe_aq_forwards aq))
+                    ((string_append ((maybe_rl_forwards rl))
+                        ((string_append ((spc_forwards () ))
+                            ((string_append ((reg_name_forwards rd))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs1))
+                                        ((string_append ((sep_forwards () ))
+                                            ((string_append ((string_of_bits imm)) (''''))))))))))))))))))))))"
+|" assembly_forwards (STORE (imm,rs1,rd,size1,aq,rl)) = (
+      string_append (''s'')
+        ((string_append ((size_mnemonic_forwards size1))
+            ((string_append ((maybe_aq_forwards aq))
+                ((string_append ((maybe_rl_forwards rl))
+                    ((string_append ((spc_forwards () ))
+                        ((string_append ((reg_name_forwards rd))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs1))
+                                    ((string_append ((sep_forwards () ))
+                                        ((string_append ((string_of_bits imm)) (''''))))))))))))))))))))"
+|" assembly_forwards (ADDIW (imm,rs1,rd)) = (
+      string_append (''addiw'')
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits imm)) (''''))))))))))))))"
+|" assembly_forwards (SHIFTW (shamt,rs1,rd,op1)) = (
+      string_append ((shiftw_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((string_of_bits shamt)) (''''))))))))))))))"
+|" assembly_forwards (RTYPEW (rs2,rs1,rd,op1)) = (
+      string_append ((rtypew_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))"
+|" assembly_forwards (MUL (rs2,rs1,rd,high,signed1,signed2)) = (
+      string_append ((mul_mnemonic_forwards high signed1 signed2))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))"
+|" assembly_forwards (DIV (rs2,rs1,rd,s)) = (
+      string_append (''div'')
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append ((spc_forwards () ))
+                ((string_append ((reg_name_forwards rd))
+                    ((string_append ((sep_forwards () ))
+                        ((string_append ((reg_name_forwards rs1))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))"
+|" assembly_forwards (REM (rs2,rs1,rd,s)) = (
+      string_append (''rem'')
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append ((spc_forwards () ))
+                ((string_append ((reg_name_forwards rd))
+                    ((string_append ((sep_forwards () ))
+                        ((string_append ((reg_name_forwards rs1))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))"
+|" assembly_forwards (MULW (rs2,rs1,rd)) = (
+      string_append (''mulw'')
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))"
+|" assembly_forwards (DIVW (rs2,rs1,rd,s)) = (
+      string_append (''div'')
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append (''w'')
+                ((string_append ((spc_forwards () ))
+                    ((string_append ((reg_name_forwards rd))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs1))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))"
+|" assembly_forwards (REMW (rs2,rs1,rd,s)) = (
+      string_append (''rem'')
+        ((string_append ((maybe_not_u_forwards s))
+            ((string_append (''w'')
+                ((string_append ((spc_forwards () ))
+                    ((string_append ((reg_name_forwards rd))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((reg_name_forwards rs1))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))"
+|" assembly_forwards (FENCE (pred,succ)) = (
+      string_append (''fence'')
+        ((string_append ((spc_forwards () ))
+            ((string_append ((fence_bits_forwards pred))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((fence_bits_forwards succ)) (''''))))))))))"
+|" assembly_forwards (FENCEI (_)) = ( (''fence.i''))"
+|" assembly_forwards (ECALL (_)) = ( (''ecall''))"
+|" assembly_forwards (MRET (_)) = ( (''mret''))"
+|" assembly_forwards (SRET (_)) = ( (''sret''))"
+|" assembly_forwards (EBREAK (_)) = ( (''ebreak''))"
+|" assembly_forwards (WFI (_)) = ( (''wfi''))"
+|" assembly_forwards (SFENCE_VMA (rs1,rs2)) = (
+      string_append (''sfence.vma'')
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rs1))
+                ((string_append ((sep_forwards () )) ((string_append ((reg_name_forwards rs2)) (''''))))))))))"
+|" assembly_forwards (LOADRES (aq,rl,rs1,size1,rd)) = (
+      string_append (''lr.'')
+        ((string_append ((maybe_aq_forwards aq))
+            ((string_append ((maybe_rl_forwards rl))
+                ((string_append ((size_mnemonic_forwards size1))
+                    ((string_append ((spc_forwards () ))
+                        ((string_append ((reg_name_forwards rd))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs1)) (''''))))))))))))))))"
+|" assembly_forwards (STORECON (aq,rl,rs2,rs1,size1,rd)) = (
+      string_append (''sc.'')
+        ((string_append ((maybe_aq_forwards aq))
+            ((string_append ((maybe_rl_forwards rl))
+                ((string_append ((size_mnemonic_forwards size1))
+                    ((string_append ((spc_forwards () ))
+                        ((string_append ((reg_name_forwards rd))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((reg_name_forwards rs1))
+                                    ((string_append ((sep_forwards () ))
+                                        ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))))"
+|" assembly_forwards (AMO (op1,aq,rl,rs2,rs1,width,rd)) = (
+      string_append ((amo_mnemonic_forwards op1))
+        ((string_append (''.'')
+            ((string_append ((size_mnemonic_forwards width))
+                ((string_append ((maybe_aq_forwards aq))
+                    ((string_append ((maybe_rl_forwards rl))
+                        ((string_append ((spc_forwards () ))
+                            ((string_append ((reg_name_forwards rd))
+                                ((string_append ((sep_forwards () ))
+                                    ((string_append ((reg_name_forwards rs1))
+                                        ((string_append ((sep_forwards () ))
+                                            ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))))))"
+|" assembly_forwards (CSR (csr,rs1,rd,True,op1)) = (
+      string_append ((csr_mnemonic_forwards op1))
+        ((string_append (''i'')
+            ((string_append ((spc_forwards () ))
+                ((string_append ((reg_name_forwards rd))
+                    ((string_append ((sep_forwards () ))
+                        ((string_append ((string_of_bits rs1))
+                            ((string_append ((sep_forwards () ))
+                                ((string_append ((csr_name_map_forwards csr)) (''''))))))))))))))))"
+|" assembly_forwards (CSR (csr,rs1,rd,False,op1)) = (
+      string_append ((csr_mnemonic_forwards op1))
+        ((string_append ((spc_forwards () ))
+            ((string_append ((reg_name_forwards rd))
+                ((string_append ((sep_forwards () ))
+                    ((string_append ((reg_name_forwards rs1))
+                        ((string_append ((sep_forwards () ))
+                            ((string_append ((csr_name_map_forwards csr)) (''''))))))))))))))"
+|" assembly_forwards (ILLEGAL (s)) = (
+      string_append (''illegal'')
+        ((string_append ((spc_forwards () )) ((string_append ((string_of_bits s)) (''''))))))"
+
+
+(*val assembly_backwards : string -> ast*)
+
+definition assembly_backwards  :: " string \<Rightarrow> ast "  where 
+     " assembly_backwards arg0 = (
+   (let stringappend_10760 = arg0 in
+   if ((case  ((utype_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_10770,stringappend_10780) =>
+        (let stringappend_10790 = (string_drop stringappend_10760 stringappend_10780) in
+        if ((case  ((spc_matches_prefix stringappend_10790)) of
+            Some (stringappend_10800,stringappend_10810) =>
+             (let stringappend_10820 = (string_drop stringappend_10790 stringappend_10810) in
+             if ((case  ((reg_name_matches_prefix stringappend_10820  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_10830,stringappend_10840) =>
+                  (let stringappend_10850 = (string_drop stringappend_10820 stringappend_10840) in
+                  if ((case  ((sep_matches_prefix stringappend_10850)) of
+                      Some (stringappend_10860,stringappend_10870) =>
+                       (let stringappend_10880 = (string_drop stringappend_10850 stringappend_10870) in
+                       if ((case  ((hex_bits_20_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_10880
+                                    ::  (( 20 Word.word * ii))option)) of
+                           Some (stringappend_10890,stringappend_10900) => 
+  if(((string_drop stringappend_10880 stringappend_10900)) = ('''')) then
+    True else False
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_10780) =
+       ((case  ((utype_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_10770,stringappend_10780) =>
+          (stringappend_10770, stringappend_10780)
+       )) in
+     (let stringappend_10790 = (string_drop stringappend_10760 stringappend_10780) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_10790)) of
+        Some (stringappend_10800,stringappend_10810) =>
+  (stringappend_10800, stringappend_10810)
+  ) of
+      (_, stringappend_10810) =>
+  (let stringappend_10820 = (string_drop stringappend_10790
+                               stringappend_10810) in
+  (let (rd, stringappend_10840) =
+       ((case  ((reg_name_matches_prefix stringappend_10820 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_10830,stringappend_10840) =>
+        (stringappend_10830, stringappend_10840)
+        )) in
+  (let stringappend_10850 = (string_drop stringappend_10820
+                               stringappend_10840) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_10850)) of
+        Some (stringappend_10860,stringappend_10870) =>
+  (stringappend_10860, stringappend_10870)
+  ) of
+      (_, stringappend_10870) =>
+  (let stringappend_10880 = (string_drop stringappend_10850
+                               stringappend_10870) in
+  (let (imm, stringappend_10900) =
+       ((case  ((hex_bits_20_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_10880 :: (( 20 Word.word * ii)) option)) of
+              Some (stringappend_10890,stringappend_10900) =>
+        (stringappend_10890, stringappend_10900)
+        )) in
+  if(((string_drop stringappend_10880 stringappend_10900)) = ('''')) then
+    (UTYPE (imm,rd,op1)) else undefined))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_10760 (''jal''))) \<and> ((let stringappend_10920 = (string_drop stringappend_10760 ((string_length (''jal'')))) in
+               if ((case  ((spc_matches_prefix stringappend_10920)) of
+                   Some (stringappend_10930,stringappend_10940) =>
+                    (let stringappend_10950 = (string_drop stringappend_10920 stringappend_10940) in
+                    if ((case  ((reg_name_matches_prefix stringappend_10950
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_10960,stringappend_10970) =>
+                         (let stringappend_10980 =
+                           (string_drop stringappend_10950 stringappend_10970) in
+                         if ((case  ((sep_matches_prefix stringappend_10980)) of
+                             Some (stringappend_10990,stringappend_11000) =>
+                              (let stringappend_11010 =
+                                (string_drop stringappend_10980 stringappend_11000) in
+                              if ((case  ((hex_bits_21_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11010
+                                           ::  (( 21 Word.word * ii))option)) of
+                                  Some (stringappend_11020,stringappend_11030) => 
+  if(((string_drop stringappend_11010 stringappend_11030)) = ('''')) then
+    True else False
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_10920 = (string_drop stringappend_10760 ((string_length (''jal'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_10920)) of
+        Some (stringappend_10930,stringappend_10940) =>
+  (stringappend_10930, stringappend_10940)
+  ) of
+      (_, stringappend_10940) =>
+  (let stringappend_10950 = (string_drop stringappend_10920
+                               stringappend_10940) in
+  (let (rd, stringappend_10970) =
+       ((case  ((reg_name_matches_prefix stringappend_10950 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_10960,stringappend_10970) =>
+        (stringappend_10960, stringappend_10970)
+        )) in
+  (let stringappend_10980 = (string_drop stringappend_10950
+                               stringappend_10970) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_10980)) of
+        Some (stringappend_10990,stringappend_11000) =>
+  (stringappend_10990, stringappend_11000)
+  ) of
+      (_, stringappend_11000) =>
+  (let stringappend_11010 = (string_drop stringappend_10980
+                               stringappend_11000) in
+  (let (imm, stringappend_11030) =
+       ((case  ((hex_bits_21_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_11010 :: (( 21 Word.word * ii)) option)) of
+              Some (stringappend_11020,stringappend_11030) =>
+        (stringappend_11020, stringappend_11030)
+        )) in
+  if(((string_drop stringappend_11010 stringappend_11030)) = ('''')) then
+    (RISCV_JAL (imm,rd)) else undefined))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_10760 (''jalr''))) \<and> ((let stringappend_11050 = (string_drop stringappend_10760 ((string_length (''jalr'')))) in
+               if ((case  ((spc_matches_prefix stringappend_11050)) of
+                   Some (stringappend_11060,stringappend_11070) =>
+                    (let stringappend_11080 = (string_drop stringappend_11050 stringappend_11070) in
+                    if ((case  ((reg_name_matches_prefix stringappend_11080
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_11090,stringappend_11100) =>
+                         (let stringappend_11110 =
+                           (string_drop stringappend_11080 stringappend_11100) in
+                         if ((case  ((sep_matches_prefix stringappend_11110)) of
+                             Some (stringappend_11120,stringappend_11130) =>
+                              (let stringappend_11140 =
+                                (string_drop stringappend_11110 stringappend_11130) in
+                              if ((case  ((reg_name_matches_prefix stringappend_11140
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_11150,stringappend_11160) =>
+                                   (let stringappend_11170 =
+                                     (string_drop stringappend_11140 stringappend_11160) in
+                                   if ((case  ((sep_matches_prefix stringappend_11170)) of
+                                       Some (stringappend_11180,stringappend_11190) =>
+                                        (let stringappend_11200 =
+                                          (string_drop stringappend_11170 stringappend_11190) in
+                                        if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11200
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_11210,stringappend_11220) => 
+  if(((string_drop stringappend_11200 stringappend_11220)) = ('''')) then
+    True else False
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_11050 = (string_drop stringappend_10760 ((string_length (''jalr'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_11050)) of
+        Some (stringappend_11060,stringappend_11070) =>
+  (stringappend_11060, stringappend_11070)
+  ) of
+      (_, stringappend_11070) =>
+  (let stringappend_11080 = (string_drop stringappend_11050
+                               stringappend_11070) in
+  (let (rd, stringappend_11100) =
+       ((case  ((reg_name_matches_prefix stringappend_11080 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11090,stringappend_11100) =>
+        (stringappend_11090, stringappend_11100)
+        )) in
+  (let stringappend_11110 = (string_drop stringappend_11080
+                               stringappend_11100) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11110)) of
+        Some (stringappend_11120,stringappend_11130) =>
+  (stringappend_11120, stringappend_11130)
+  ) of
+      (_, stringappend_11130) =>
+  (let stringappend_11140 = (string_drop stringappend_11110
+                               stringappend_11130) in
+  (let (rs1, stringappend_11160) =
+       ((case  ((reg_name_matches_prefix stringappend_11140 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11150,stringappend_11160) =>
+        (stringappend_11150, stringappend_11160)
+        )) in
+  (let stringappend_11170 = (string_drop stringappend_11140
+                               stringappend_11160) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11170)) of
+        Some (stringappend_11180,stringappend_11190) =>
+  (stringappend_11180, stringappend_11190)
+  ) of
+      (_, stringappend_11190) =>
+  (let stringappend_11200 = (string_drop stringappend_11170
+                               stringappend_11190) in
+  (let (imm, stringappend_11220) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_11200 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_11210,stringappend_11220) =>
+        (stringappend_11210, stringappend_11220)
+        )) in
+  if(((string_drop stringappend_11200 stringappend_11220)) = ('''')) then
+    (RISCV_JALR (imm,rs1,rd)) else undefined))
+  ))))
+  ))))
+  ))
+   else if ((case  ((btype_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_11240,stringappend_11250) =>
+        (let stringappend_11260 = (string_drop stringappend_10760 stringappend_11250) in
+        if ((case  ((spc_matches_prefix stringappend_11260)) of
+            Some (stringappend_11270,stringappend_11280) =>
+             (let stringappend_11290 = (string_drop stringappend_11260 stringappend_11280) in
+             if ((case  ((reg_name_matches_prefix stringappend_11290  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_11300,stringappend_11310) =>
+                  (let stringappend_11320 = (string_drop stringappend_11290 stringappend_11310) in
+                  if ((case  ((sep_matches_prefix stringappend_11320)) of
+                      Some (stringappend_11330,stringappend_11340) =>
+                       (let stringappend_11350 = (string_drop stringappend_11320 stringappend_11340) in
+                       if ((case  ((reg_name_matches_prefix stringappend_11350
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_11360,stringappend_11370) =>
+                            (let stringappend_11380 =
+                              (string_drop stringappend_11350 stringappend_11370) in
+                            if ((case  ((sep_matches_prefix stringappend_11380)) of
+                                Some (stringappend_11390,stringappend_11400) =>
+                                 (let stringappend_11410 =
+                                   (string_drop stringappend_11380 stringappend_11400) in
+                                 if ((case  ((hex_bits_13_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11410
+                                              ::  (( 13 Word.word * ii))option)) of
+                                     Some (stringappend_11420,stringappend_11430) => 
+  if(((string_drop stringappend_11410 stringappend_11430)) = ('''')) then
+    True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_11250) =
+       ((case  ((btype_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_11240,stringappend_11250) =>
+          (stringappend_11240, stringappend_11250)
+       )) in
+     (let stringappend_11260 = (string_drop stringappend_10760 stringappend_11250) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_11260)) of
+        Some (stringappend_11270,stringappend_11280) =>
+  (stringappend_11270, stringappend_11280)
+  ) of
+      (_, stringappend_11280) =>
+  (let stringappend_11290 = (string_drop stringappend_11260
+                               stringappend_11280) in
+  (let (rs1, stringappend_11310) =
+       ((case  ((reg_name_matches_prefix stringappend_11290 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11300,stringappend_11310) =>
+        (stringappend_11300, stringappend_11310)
+        )) in
+  (let stringappend_11320 = (string_drop stringappend_11290
+                               stringappend_11310) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11320)) of
+        Some (stringappend_11330,stringappend_11340) =>
+  (stringappend_11330, stringappend_11340)
+  ) of
+      (_, stringappend_11340) =>
+  (let stringappend_11350 = (string_drop stringappend_11320
+                               stringappend_11340) in
+  (let (rs2, stringappend_11370) =
+       ((case  ((reg_name_matches_prefix stringappend_11350 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11360,stringappend_11370) =>
+        (stringappend_11360, stringappend_11370)
+        )) in
+  (let stringappend_11380 = (string_drop stringappend_11350
+                               stringappend_11370) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11380)) of
+        Some (stringappend_11390,stringappend_11400) =>
+  (stringappend_11390, stringappend_11400)
+  ) of
+      (_, stringappend_11400) =>
+  (let stringappend_11410 = (string_drop stringappend_11380
+                               stringappend_11400) in
+  (let (imm, stringappend_11430) =
+       ((case  ((hex_bits_13_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_11410 :: (( 13 Word.word * ii)) option)) of
+              Some (stringappend_11420,stringappend_11430) =>
+        (stringappend_11420, stringappend_11430)
+        )) in
+  if(((string_drop stringappend_11410 stringappend_11430)) = ('''')) then
+    (BTYPE (imm,rs2,rs1,op1)) else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((itype_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_11450,stringappend_11460) =>
+        (let stringappend_11470 = (string_drop stringappend_10760 stringappend_11460) in
+        if ((case  ((spc_matches_prefix stringappend_11470)) of
+            Some (stringappend_11480,stringappend_11490) =>
+             (let stringappend_11500 = (string_drop stringappend_11470 stringappend_11490) in
+             if ((case  ((reg_name_matches_prefix stringappend_11500  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_11510,stringappend_11520) =>
+                  (let stringappend_11530 = (string_drop stringappend_11500 stringappend_11520) in
+                  if ((case  ((sep_matches_prefix stringappend_11530)) of
+                      Some (stringappend_11540,stringappend_11550) =>
+                       (let stringappend_11560 = (string_drop stringappend_11530 stringappend_11550) in
+                       if ((case  ((reg_name_matches_prefix stringappend_11560
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_11570,stringappend_11580) =>
+                            (let stringappend_11590 =
+                              (string_drop stringappend_11560 stringappend_11580) in
+                            if ((case  ((sep_matches_prefix stringappend_11590)) of
+                                Some (stringappend_11600,stringappend_11610) =>
+                                 (let stringappend_11620 =
+                                   (string_drop stringappend_11590 stringappend_11610) in
+                                 if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11620
+                                              ::  (( 12 Word.word * ii))option)) of
+                                     Some (stringappend_11630,stringappend_11640) => 
+  if(((string_drop stringappend_11620 stringappend_11640)) = ('''')) then
+    True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_11460) =
+       ((case  ((itype_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_11450,stringappend_11460) =>
+          (stringappend_11450, stringappend_11460)
+       )) in
+     (let stringappend_11470 = (string_drop stringappend_10760 stringappend_11460) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_11470)) of
+        Some (stringappend_11480,stringappend_11490) =>
+  (stringappend_11480, stringappend_11490)
+  ) of
+      (_, stringappend_11490) =>
+  (let stringappend_11500 = (string_drop stringappend_11470
+                               stringappend_11490) in
+  (let (rd, stringappend_11520) =
+       ((case  ((reg_name_matches_prefix stringappend_11500 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11510,stringappend_11520) =>
+        (stringappend_11510, stringappend_11520)
+        )) in
+  (let stringappend_11530 = (string_drop stringappend_11500
+                               stringappend_11520) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11530)) of
+        Some (stringappend_11540,stringappend_11550) =>
+  (stringappend_11540, stringappend_11550)
+  ) of
+      (_, stringappend_11550) =>
+  (let stringappend_11560 = (string_drop stringappend_11530
+                               stringappend_11550) in
+  (let (rs1, stringappend_11580) =
+       ((case  ((reg_name_matches_prefix stringappend_11560 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11570,stringappend_11580) =>
+        (stringappend_11570, stringappend_11580)
+        )) in
+  (let stringappend_11590 = (string_drop stringappend_11560
+                               stringappend_11580) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11590)) of
+        Some (stringappend_11600,stringappend_11610) =>
+  (stringappend_11600, stringappend_11610)
+  ) of
+      (_, stringappend_11610) =>
+  (let stringappend_11620 = (string_drop stringappend_11590
+                               stringappend_11610) in
+  (let (imm, stringappend_11640) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_11620 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_11630,stringappend_11640) =>
+        (stringappend_11630, stringappend_11640)
+        )) in
+  if(((string_drop stringappend_11620 stringappend_11640)) = ('''')) then
+    (ITYPE (imm,rs1,rd,op1)) else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((shiftiop_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_11660,stringappend_11670) =>
+        (let stringappend_11680 = (string_drop stringappend_10760 stringappend_11670) in
+        if ((case  ((spc_matches_prefix stringappend_11680)) of
+            Some (stringappend_11690,stringappend_11700) =>
+             (let stringappend_11710 = (string_drop stringappend_11680 stringappend_11700) in
+             if ((case  ((reg_name_matches_prefix stringappend_11710  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_11720,stringappend_11730) =>
+                  (let stringappend_11740 = (string_drop stringappend_11710 stringappend_11730) in
+                  if ((case  ((sep_matches_prefix stringappend_11740)) of
+                      Some (stringappend_11750,stringappend_11760) =>
+                       (let stringappend_11770 = (string_drop stringappend_11740 stringappend_11760) in
+                       if ((case  ((reg_name_matches_prefix stringappend_11770
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_11780,stringappend_11790) =>
+                            (let stringappend_11800 =
+                              (string_drop stringappend_11770 stringappend_11790) in
+                            if ((case  ((hex_bits_6_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11800
+                                         ::  (( 6 Word.word * ii))option)) of
+                                Some (stringappend_11810,stringappend_11820) => 
+  if(((string_drop stringappend_11800 stringappend_11820)) = ('''')) then
+    True else False
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_11670) =
+       ((case  ((shiftiop_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_11660,stringappend_11670) =>
+          (stringappend_11660, stringappend_11670)
+       )) in
+     (let stringappend_11680 = (string_drop stringappend_10760 stringappend_11670) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_11680)) of
+        Some (stringappend_11690,stringappend_11700) =>
+  (stringappend_11690, stringappend_11700)
+  ) of
+      (_, stringappend_11700) =>
+  (let stringappend_11710 = (string_drop stringappend_11680
+                               stringappend_11700) in
+  (let (rd, stringappend_11730) =
+       ((case  ((reg_name_matches_prefix stringappend_11710 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11720,stringappend_11730) =>
+        (stringappend_11720, stringappend_11730)
+        )) in
+  (let stringappend_11740 = (string_drop stringappend_11710
+                               stringappend_11730) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11740)) of
+        Some (stringappend_11750,stringappend_11760) =>
+  (stringappend_11750, stringappend_11760)
+  ) of
+      (_, stringappend_11760) =>
+  (let stringappend_11770 = (string_drop stringappend_11740
+                               stringappend_11760) in
+  (let (rs1, stringappend_11790) =
+       ((case  ((reg_name_matches_prefix stringappend_11770 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11780,stringappend_11790) =>
+        (stringappend_11780, stringappend_11790)
+        )) in
+  (let stringappend_11800 = (string_drop stringappend_11770
+                               stringappend_11790) in
+  (let (shamt, stringappend_11820) =
+       ((case  ((hex_bits_6_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_11800 :: (( 6 Word.word * ii)) option)) of
+              Some (stringappend_11810,stringappend_11820) =>
+        (stringappend_11810, stringappend_11820)
+        )) in
+  if(((string_drop stringappend_11800 stringappend_11820)) = ('''')) then
+    (SHIFTIOP (shamt,rs1,rd,op1)) else undefined))))
+  ))))
+  )))
+   else if ((case  ((rtype_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_11840,stringappend_11850) =>
+        (let stringappend_11860 = (string_drop stringappend_10760 stringappend_11850) in
+        if ((case  ((spc_matches_prefix stringappend_11860)) of
+            Some (stringappend_11870,stringappend_11880) =>
+             (let stringappend_11890 = (string_drop stringappend_11860 stringappend_11880) in
+             if ((case  ((reg_name_matches_prefix stringappend_11890  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_11900,stringappend_11910) =>
+                  (let stringappend_11920 = (string_drop stringappend_11890 stringappend_11910) in
+                  if ((case  ((sep_matches_prefix stringappend_11920)) of
+                      Some (stringappend_11930,stringappend_11940) =>
+                       (let stringappend_11950 = (string_drop stringappend_11920 stringappend_11940) in
+                       if ((case  ((reg_name_matches_prefix stringappend_11950
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_11960,stringappend_11970) =>
+                            (let stringappend_11980 =
+                              (string_drop stringappend_11950 stringappend_11970) in
+                            if ((case  ((sep_matches_prefix stringappend_11980)) of
+                                Some (stringappend_11990,stringappend_12000) =>
+                                 (let stringappend_12010 =
+                                   (string_drop stringappend_11980 stringappend_12000) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_12010
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_12020,stringappend_12030) => 
+  if(((string_drop stringappend_12010 stringappend_12030)) = ('''')) then
+    True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_11850) =
+       ((case  ((rtype_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_11840,stringappend_11850) =>
+          (stringappend_11840, stringappend_11850)
+       )) in
+     (let stringappend_11860 = (string_drop stringappend_10760 stringappend_11850) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_11860)) of
+        Some (stringappend_11870,stringappend_11880) =>
+  (stringappend_11870, stringappend_11880)
+  ) of
+      (_, stringappend_11880) =>
+  (let stringappend_11890 = (string_drop stringappend_11860
+                               stringappend_11880) in
+  (let (rd, stringappend_11910) =
+       ((case  ((reg_name_matches_prefix stringappend_11890 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11900,stringappend_11910) =>
+        (stringappend_11900, stringappend_11910)
+        )) in
+  (let stringappend_11920 = (string_drop stringappend_11890
+                               stringappend_11910) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11920)) of
+        Some (stringappend_11930,stringappend_11940) =>
+  (stringappend_11930, stringappend_11940)
+  ) of
+      (_, stringappend_11940) =>
+  (let stringappend_11950 = (string_drop stringappend_11920
+                               stringappend_11940) in
+  (let (rs1, stringappend_11970) =
+       ((case  ((reg_name_matches_prefix stringappend_11950 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_11960,stringappend_11970) =>
+        (stringappend_11960, stringappend_11970)
+        )) in
+  (let stringappend_11980 = (string_drop stringappend_11950
+                               stringappend_11970) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_11980)) of
+        Some (stringappend_11990,stringappend_12000) =>
+  (stringappend_11990, stringappend_12000)
+  ) of
+      (_, stringappend_12000) =>
+  (let stringappend_12010 = (string_drop stringappend_11980
+                               stringappend_12000) in
+  (let (rs2, stringappend_12030) =
+       ((case  ((reg_name_matches_prefix stringappend_12010 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12020,stringappend_12030) =>
+        (stringappend_12020, stringappend_12030)
+        )) in
+  if(((string_drop stringappend_12010 stringappend_12030)) = ('''')) then
+    (RTYPE (rs2,rs1,rd,op1)) else undefined))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_10760 (''l''))) \<and> ((let stringappend_12050 = (string_drop stringappend_10760 ((string_length (''l'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_12050)) of
+                   Some (stringappend_12060,stringappend_12070) =>
+                    (let stringappend_12080 = (string_drop stringappend_12050 stringappend_12070) in
+                    if ((case  ((maybe_u_matches_prefix stringappend_12080)) of
+                        Some (stringappend_12090,stringappend_12100) =>
+                         (let stringappend_12110 =
+                           (string_drop stringappend_12080 stringappend_12100) in
+                         if ((case  ((maybe_aq_matches_prefix stringappend_12110)) of
+                             Some (stringappend_12120,stringappend_12130) =>
+                              (let stringappend_12140 =
+                                (string_drop stringappend_12110 stringappend_12130) in
+                              if ((case  ((maybe_rl_matches_prefix stringappend_12140)) of
+                                  Some (stringappend_12150,stringappend_12160) =>
+                                   (let stringappend_12170 =
+                                     (string_drop stringappend_12140 stringappend_12160) in
+                                   if ((case  ((spc_matches_prefix stringappend_12170)) of
+                                       Some (stringappend_12180,stringappend_12190) =>
+                                        (let stringappend_12200 =
+                                          (string_drop stringappend_12170 stringappend_12190) in
+                                        if ((case  ((reg_name_matches_prefix stringappend_12200
+                                                     ::  (( 5 Word.word * ii))option)) of
+                                            Some (stringappend_12210,stringappend_12220) =>
+                                             (let stringappend_12230 =
+                                               (string_drop stringappend_12200 stringappend_12220) in
+                                             if ((case  ((sep_matches_prefix stringappend_12230)) of
+                                                 Some (stringappend_12240,stringappend_12250) =>
+                                                  (let stringappend_12260 =
+                                                    (string_drop stringappend_12230
+                                                      stringappend_12250) in
+                                                  if ((case  ((reg_name_matches_prefix
+                                                                stringappend_12260
+                                                               ::  (( 5 Word.word * ii))option)) of
+                                                      Some (stringappend_12270,stringappend_12280) =>
+                                                       (let stringappend_12290 =
+                                                         (string_drop stringappend_12260
+                                                           stringappend_12280) in
+                                                       if ((case  ((sep_matches_prefix
+                                                                     stringappend_12290)) of
+                                                           Some
+                                                           (stringappend_12300,stringappend_12310) =>
+                                                            (let stringappend_12320 =
+                                                              (string_drop stringappend_12290
+                                                                stringappend_12310) in
+                                                            if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                          stringappend_12320
+                                                                         ::  (( 12 Word.word * ii))option)) of
+                                                                Some
+                                                                (stringappend_12330,stringappend_12340) => 
+  if(((string_drop stringappend_12320 stringappend_12340)) = ('''')) then
+    True else False
+                                                              | None => False
+                                                              )) then
+                                                              True
+                                                            else False)
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_12050 = (string_drop stringappend_10760 ((string_length (''l'')))) in
+     (let (size1, stringappend_12070) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_12050)) of
+         Some (stringappend_12060,stringappend_12070) =>
+          (stringappend_12060, stringappend_12070)
+       )) in
+     (let stringappend_12080 = (string_drop stringappend_12050 stringappend_12070) in
+     (let (is_unsigned, stringappend_12100) =
+       ((case  ((maybe_u_matches_prefix stringappend_12080)) of
+         Some (stringappend_12090,stringappend_12100) =>
+          (stringappend_12090, stringappend_12100)
+       )) in
+     (let stringappend_12110 = (string_drop stringappend_12080 stringappend_12100) in
+     (let (aq, stringappend_12130) =
+       ((case  ((maybe_aq_matches_prefix stringappend_12110)) of
+         Some (stringappend_12120,stringappend_12130) =>
+          (stringappend_12120, stringappend_12130)
+       )) in
+     (let stringappend_12140 = (string_drop stringappend_12110 stringappend_12130) in
+     (let (rl, stringappend_12160) =
+       ((case  ((maybe_rl_matches_prefix stringappend_12140)) of
+         Some (stringappend_12150,stringappend_12160) =>
+          (stringappend_12150, stringappend_12160)
+       )) in
+     (let stringappend_12170 = (string_drop stringappend_12140 stringappend_12160) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_12170)) of
+        Some (stringappend_12180,stringappend_12190) =>
+  (stringappend_12180, stringappend_12190)
+  ) of
+      (_, stringappend_12190) =>
+  (let stringappend_12200 = (string_drop stringappend_12170
+                               stringappend_12190) in
+  (let (rd, stringappend_12220) =
+       ((case  ((reg_name_matches_prefix stringappend_12200 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12210,stringappend_12220) =>
+        (stringappend_12210, stringappend_12220)
+        )) in
+  (let stringappend_12230 = (string_drop stringappend_12200
+                               stringappend_12220) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12230)) of
+        Some (stringappend_12240,stringappend_12250) =>
+  (stringappend_12240, stringappend_12250)
+  ) of
+      (_, stringappend_12250) =>
+  (let stringappend_12260 = (string_drop stringappend_12230
+                               stringappend_12250) in
+  (let (rs1, stringappend_12280) =
+       ((case  ((reg_name_matches_prefix stringappend_12260 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12270,stringappend_12280) =>
+        (stringappend_12270, stringappend_12280)
+        )) in
+  (let stringappend_12290 = (string_drop stringappend_12260
+                               stringappend_12280) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12290)) of
+        Some (stringappend_12300,stringappend_12310) =>
+  (stringappend_12300, stringappend_12310)
+  ) of
+      (_, stringappend_12310) =>
+  (let stringappend_12320 = (string_drop stringappend_12290
+                               stringappend_12310) in
+  (let (imm, stringappend_12340) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_12320 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_12330,stringappend_12340) =>
+        (stringappend_12330, stringappend_12340)
+        )) in
+  if(((string_drop stringappend_12320 stringappend_12340)) = ('''')) then
+    (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)) else undefined))
+  ))))
+  ))))
+  ))))))))))
+   else if (((((string_startswith stringappend_10760 (''s''))) \<and> ((let stringappend_12360 = (string_drop stringappend_10760 ((string_length (''s'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_12360)) of
+                   Some (stringappend_12370,stringappend_12380) =>
+                    (let stringappend_12390 = (string_drop stringappend_12360 stringappend_12380) in
+                    if ((case  ((maybe_aq_matches_prefix stringappend_12390)) of
+                        Some (stringappend_12400,stringappend_12410) =>
+                         (let stringappend_12420 =
+                           (string_drop stringappend_12390 stringappend_12410) in
+                         if ((case  ((maybe_rl_matches_prefix stringappend_12420)) of
+                             Some (stringappend_12430,stringappend_12440) =>
+                              (let stringappend_12450 =
+                                (string_drop stringappend_12420 stringappend_12440) in
+                              if ((case  ((spc_matches_prefix stringappend_12450)) of
+                                  Some (stringappend_12460,stringappend_12470) =>
+                                   (let stringappend_12480 =
+                                     (string_drop stringappend_12450 stringappend_12470) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_12480
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_12490,stringappend_12500) =>
+                                        (let stringappend_12510 =
+                                          (string_drop stringappend_12480 stringappend_12500) in
+                                        if ((case  ((sep_matches_prefix stringappend_12510)) of
+                                            Some (stringappend_12520,stringappend_12530) =>
+                                             (let stringappend_12540 =
+                                               (string_drop stringappend_12510 stringappend_12530) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_12540
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_12550,stringappend_12560) =>
+                                                  (let stringappend_12570 =
+                                                    (string_drop stringappend_12540
+                                                      stringappend_12560) in
+                                                  if ((case  ((sep_matches_prefix stringappend_12570)) of
+                                                      Some (stringappend_12580,stringappend_12590) =>
+                                                       (let stringappend_12600 =
+                                                         (string_drop stringappend_12570
+                                                           stringappend_12590) in
+                                                       if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                     stringappend_12600
+                                                                    ::  (( 12 Word.word * ii))option)) of
+                                                           Some
+                                                           (stringappend_12610,stringappend_12620) => 
+  if(((string_drop stringappend_12600 stringappend_12620)) = ('''')) then
+    True else False
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_12360 = (string_drop stringappend_10760 ((string_length (''s'')))) in
+     (let (size1, stringappend_12380) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_12360)) of
+         Some (stringappend_12370,stringappend_12380) =>
+          (stringappend_12370, stringappend_12380)
+       )) in
+     (let stringappend_12390 = (string_drop stringappend_12360 stringappend_12380) in
+     (let (aq, stringappend_12410) =
+       ((case  ((maybe_aq_matches_prefix stringappend_12390)) of
+         Some (stringappend_12400,stringappend_12410) =>
+          (stringappend_12400, stringappend_12410)
+       )) in
+     (let stringappend_12420 = (string_drop stringappend_12390 stringappend_12410) in
+     (let (rl, stringappend_12440) =
+       ((case  ((maybe_rl_matches_prefix stringappend_12420)) of
+         Some (stringappend_12430,stringappend_12440) =>
+          (stringappend_12430, stringappend_12440)
+       )) in
+     (let stringappend_12450 = (string_drop stringappend_12420 stringappend_12440) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_12450)) of
+        Some (stringappend_12460,stringappend_12470) =>
+  (stringappend_12460, stringappend_12470)
+  ) of
+      (_, stringappend_12470) =>
+  (let stringappend_12480 = (string_drop stringappend_12450
+                               stringappend_12470) in
+  (let (rd, stringappend_12500) =
+       ((case  ((reg_name_matches_prefix stringappend_12480 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12490,stringappend_12500) =>
+        (stringappend_12490, stringappend_12500)
+        )) in
+  (let stringappend_12510 = (string_drop stringappend_12480
+                               stringappend_12500) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12510)) of
+        Some (stringappend_12520,stringappend_12530) =>
+  (stringappend_12520, stringappend_12530)
+  ) of
+      (_, stringappend_12530) =>
+  (let stringappend_12540 = (string_drop stringappend_12510
+                               stringappend_12530) in
+  (let (rs1, stringappend_12560) =
+       ((case  ((reg_name_matches_prefix stringappend_12540 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12550,stringappend_12560) =>
+        (stringappend_12550, stringappend_12560)
+        )) in
+  (let stringappend_12570 = (string_drop stringappend_12540
+                               stringappend_12560) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12570)) of
+        Some (stringappend_12580,stringappend_12590) =>
+  (stringappend_12580, stringappend_12590)
+  ) of
+      (_, stringappend_12590) =>
+  (let stringappend_12600 = (string_drop stringappend_12570
+                               stringappend_12590) in
+  (let (imm, stringappend_12620) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_12600 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_12610,stringappend_12620) =>
+        (stringappend_12610, stringappend_12620)
+        )) in
+  if(((string_drop stringappend_12600 stringappend_12620)) = ('''')) then
+    (STORE (imm,rs1,rd,size1,aq,rl)) else undefined))
+  ))))
+  ))))
+  ))))))))
+   else if (((((string_startswith stringappend_10760 (''addiw''))) \<and> ((let stringappend_12640 = (string_drop stringappend_10760 ((string_length (''addiw'')))) in
+               if ((case  ((spc_matches_prefix stringappend_12640)) of
+                   Some (stringappend_12650,stringappend_12660) =>
+                    (let stringappend_12670 = (string_drop stringappend_12640 stringappend_12660) in
+                    if ((case  ((reg_name_matches_prefix stringappend_12670
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_12680,stringappend_12690) =>
+                         (let stringappend_12700 =
+                           (string_drop stringappend_12670 stringappend_12690) in
+                         if ((case  ((sep_matches_prefix stringappend_12700)) of
+                             Some (stringappend_12710,stringappend_12720) =>
+                              (let stringappend_12730 =
+                                (string_drop stringappend_12700 stringappend_12720) in
+                              if ((case  ((reg_name_matches_prefix stringappend_12730
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_12740,stringappend_12750) =>
+                                   (let stringappend_12760 =
+                                     (string_drop stringappend_12730 stringappend_12750) in
+                                   if ((case  ((sep_matches_prefix stringappend_12760)) of
+                                       Some (stringappend_12770,stringappend_12780) =>
+                                        (let stringappend_12790 =
+                                          (string_drop stringappend_12760 stringappend_12780) in
+                                        if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_12790
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_12800,stringappend_12810) => 
+  if(((string_drop stringappend_12790 stringappend_12810)) = ('''')) then
+    True else False
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_12640 = (string_drop stringappend_10760 ((string_length (''addiw'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_12640)) of
+        Some (stringappend_12650,stringappend_12660) =>
+  (stringappend_12650, stringappend_12660)
+  ) of
+      (_, stringappend_12660) =>
+  (let stringappend_12670 = (string_drop stringappend_12640
+                               stringappend_12660) in
+  (let (rd, stringappend_12690) =
+       ((case  ((reg_name_matches_prefix stringappend_12670 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12680,stringappend_12690) =>
+        (stringappend_12680, stringappend_12690)
+        )) in
+  (let stringappend_12700 = (string_drop stringappend_12670
+                               stringappend_12690) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12700)) of
+        Some (stringappend_12710,stringappend_12720) =>
+  (stringappend_12710, stringappend_12720)
+  ) of
+      (_, stringappend_12720) =>
+  (let stringappend_12730 = (string_drop stringappend_12700
+                               stringappend_12720) in
+  (let (rs1, stringappend_12750) =
+       ((case  ((reg_name_matches_prefix stringappend_12730 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12740,stringappend_12750) =>
+        (stringappend_12740, stringappend_12750)
+        )) in
+  (let stringappend_12760 = (string_drop stringappend_12730
+                               stringappend_12750) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12760)) of
+        Some (stringappend_12770,stringappend_12780) =>
+  (stringappend_12770, stringappend_12780)
+  ) of
+      (_, stringappend_12780) =>
+  (let stringappend_12790 = (string_drop stringappend_12760
+                               stringappend_12780) in
+  (let (imm, stringappend_12810) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_12790 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_12800,stringappend_12810) =>
+        (stringappend_12800, stringappend_12810)
+        )) in
+  if(((string_drop stringappend_12790 stringappend_12810)) = ('''')) then
+    (ADDIW (imm,rs1,rd)) else undefined))
+  ))))
+  ))))
+  ))
+   else if ((case  ((shiftw_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_12830,stringappend_12840) =>
+        (let stringappend_12850 = (string_drop stringappend_10760 stringappend_12840) in
+        if ((case  ((spc_matches_prefix stringappend_12850)) of
+            Some (stringappend_12860,stringappend_12870) =>
+             (let stringappend_12880 = (string_drop stringappend_12850 stringappend_12870) in
+             if ((case  ((reg_name_matches_prefix stringappend_12880  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_12890,stringappend_12900) =>
+                  (let stringappend_12910 = (string_drop stringappend_12880 stringappend_12900) in
+                  if ((case  ((sep_matches_prefix stringappend_12910)) of
+                      Some (stringappend_12920,stringappend_12930) =>
+                       (let stringappend_12940 = (string_drop stringappend_12910 stringappend_12930) in
+                       if ((case  ((reg_name_matches_prefix stringappend_12940
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_12950,stringappend_12960) =>
+                            (let stringappend_12970 =
+                              (string_drop stringappend_12940 stringappend_12960) in
+                            if ((case  ((sep_matches_prefix stringappend_12970)) of
+                                Some (stringappend_12980,stringappend_12990) =>
+                                 (let stringappend_13000 =
+                                   (string_drop stringappend_12970 stringappend_12990) in
+                                 if ((case  ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_13000
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_13010,stringappend_13020) => 
+  if(((string_drop stringappend_13000 stringappend_13020)) = ('''')) then
+    True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_12840) =
+       ((case  ((shiftw_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_12830,stringappend_12840) =>
+          (stringappend_12830, stringappend_12840)
+       )) in
+     (let stringappend_12850 = (string_drop stringappend_10760 stringappend_12840) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_12850)) of
+        Some (stringappend_12860,stringappend_12870) =>
+  (stringappend_12860, stringappend_12870)
+  ) of
+      (_, stringappend_12870) =>
+  (let stringappend_12880 = (string_drop stringappend_12850
+                               stringappend_12870) in
+  (let (rd, stringappend_12900) =
+       ((case  ((reg_name_matches_prefix stringappend_12880 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12890,stringappend_12900) =>
+        (stringappend_12890, stringappend_12900)
+        )) in
+  (let stringappend_12910 = (string_drop stringappend_12880
+                               stringappend_12900) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12910)) of
+        Some (stringappend_12920,stringappend_12930) =>
+  (stringappend_12920, stringappend_12930)
+  ) of
+      (_, stringappend_12930) =>
+  (let stringappend_12940 = (string_drop stringappend_12910
+                               stringappend_12930) in
+  (let (rs1, stringappend_12960) =
+       ((case  ((reg_name_matches_prefix stringappend_12940 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_12950,stringappend_12960) =>
+        (stringappend_12950, stringappend_12960)
+        )) in
+  (let stringappend_12970 = (string_drop stringappend_12940
+                               stringappend_12960) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_12970)) of
+        Some (stringappend_12980,stringappend_12990) =>
+  (stringappend_12980, stringappend_12990)
+  ) of
+      (_, stringappend_12990) =>
+  (let stringappend_13000 = (string_drop stringappend_12970
+                               stringappend_12990) in
+  (let (shamt, stringappend_13020) =
+       ((case  ((hex_bits_5_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_13000 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13010,stringappend_13020) =>
+        (stringappend_13010, stringappend_13020)
+        )) in
+  if(((string_drop stringappend_13000 stringappend_13020)) = ('''')) then
+    (SHIFTW (shamt,rs1,rd,op1)) else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((rtypew_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_13040,stringappend_13050) =>
+        (let stringappend_13060 = (string_drop stringappend_10760 stringappend_13050) in
+        if ((case  ((spc_matches_prefix stringappend_13060)) of
+            Some (stringappend_13070,stringappend_13080) =>
+             (let stringappend_13090 = (string_drop stringappend_13060 stringappend_13080) in
+             if ((case  ((reg_name_matches_prefix stringappend_13090  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_13100,stringappend_13110) =>
+                  (let stringappend_13120 = (string_drop stringappend_13090 stringappend_13110) in
+                  if ((case  ((sep_matches_prefix stringappend_13120)) of
+                      Some (stringappend_13130,stringappend_13140) =>
+                       (let stringappend_13150 = (string_drop stringappend_13120 stringappend_13140) in
+                       if ((case  ((reg_name_matches_prefix stringappend_13150
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_13160,stringappend_13170) =>
+                            (let stringappend_13180 =
+                              (string_drop stringappend_13150 stringappend_13170) in
+                            if ((case  ((sep_matches_prefix stringappend_13180)) of
+                                Some (stringappend_13190,stringappend_13200) =>
+                                 (let stringappend_13210 =
+                                   (string_drop stringappend_13180 stringappend_13200) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_13210
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_13220,stringappend_13230) => 
+  if(((string_drop stringappend_13210 stringappend_13230)) = ('''')) then
+    True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_13050) =
+       ((case  ((rtypew_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_13040,stringappend_13050) =>
+          (stringappend_13040, stringappend_13050)
+       )) in
+     (let stringappend_13060 = (string_drop stringappend_10760 stringappend_13050) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_13060)) of
+        Some (stringappend_13070,stringappend_13080) =>
+  (stringappend_13070, stringappend_13080)
+  ) of
+      (_, stringappend_13080) =>
+  (let stringappend_13090 = (string_drop stringappend_13060
+                               stringappend_13080) in
+  (let (rd, stringappend_13110) =
+       ((case  ((reg_name_matches_prefix stringappend_13090 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13100,stringappend_13110) =>
+        (stringappend_13100, stringappend_13110)
+        )) in
+  (let stringappend_13120 = (string_drop stringappend_13090
+                               stringappend_13110) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13120)) of
+        Some (stringappend_13130,stringappend_13140) =>
+  (stringappend_13130, stringappend_13140)
+  ) of
+      (_, stringappend_13140) =>
+  (let stringappend_13150 = (string_drop stringappend_13120
+                               stringappend_13140) in
+  (let (rs1, stringappend_13170) =
+       ((case  ((reg_name_matches_prefix stringappend_13150 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13160,stringappend_13170) =>
+        (stringappend_13160, stringappend_13170)
+        )) in
+  (let stringappend_13180 = (string_drop stringappend_13150
+                               stringappend_13170) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13180)) of
+        Some (stringappend_13190,stringappend_13200) =>
+  (stringappend_13190, stringappend_13200)
+  ) of
+      (_, stringappend_13200) =>
+  (let stringappend_13210 = (string_drop stringappend_13180
+                               stringappend_13200) in
+  (let (rs2, stringappend_13230) =
+       ((case  ((reg_name_matches_prefix stringappend_13210 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13220,stringappend_13230) =>
+        (stringappend_13220, stringappend_13230)
+        )) in
+  if(((string_drop stringappend_13210 stringappend_13230)) = ('''')) then
+    (RTYPEW (rs2,rs1,rd,op1)) else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((mul_mnemonic_matches_prefix stringappend_10760)) of
+       Some (stringappend_13250,stringappend_13260) =>
+        (let stringappend_13270 = (string_drop stringappend_10760 stringappend_13260) in
+        if ((case  ((spc_matches_prefix stringappend_13270)) of
+            Some (stringappend_13280,stringappend_13290) =>
+             (let stringappend_13300 = (string_drop stringappend_13270 stringappend_13290) in
+             if ((case  ((reg_name_matches_prefix stringappend_13300  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_13310,stringappend_13320) =>
+                  (let stringappend_13330 = (string_drop stringappend_13300 stringappend_13320) in
+                  if ((case  ((sep_matches_prefix stringappend_13330)) of
+                      Some (stringappend_13340,stringappend_13350) =>
+                       (let stringappend_13360 = (string_drop stringappend_13330 stringappend_13350) in
+                       if ((case  ((reg_name_matches_prefix stringappend_13360
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_13370,stringappend_13380) =>
+                            (let stringappend_13390 =
+                              (string_drop stringappend_13360 stringappend_13380) in
+                            if ((case  ((sep_matches_prefix stringappend_13390)) of
+                                Some (stringappend_13400,stringappend_13410) =>
+                                 (let stringappend_13420 =
+                                   (string_drop stringappend_13390 stringappend_13410) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_13420
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_13430,stringappend_13440) => 
+  if(((string_drop stringappend_13420 stringappend_13440)) = ('''')) then
+    True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let ((high, signed1, signed2), stringappend_13260) =
+       ((case  ((mul_mnemonic_matches_prefix stringappend_10760)) of
+         Some (stringappend_13250,stringappend_13260) =>
+          (stringappend_13250, stringappend_13260)
+       )) in
+     (let stringappend_13270 = (string_drop stringappend_10760 stringappend_13260) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_13270)) of
+        Some (stringappend_13280,stringappend_13290) =>
+  (stringappend_13280, stringappend_13290)
+  ) of
+      (_, stringappend_13290) =>
+  (let stringappend_13300 = (string_drop stringappend_13270
+                               stringappend_13290) in
+  (let (rd, stringappend_13320) =
+       ((case  ((reg_name_matches_prefix stringappend_13300 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13310,stringappend_13320) =>
+        (stringappend_13310, stringappend_13320)
+        )) in
+  (let stringappend_13330 = (string_drop stringappend_13300
+                               stringappend_13320) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13330)) of
+        Some (stringappend_13340,stringappend_13350) =>
+  (stringappend_13340, stringappend_13350)
+  ) of
+      (_, stringappend_13350) =>
+  (let stringappend_13360 = (string_drop stringappend_13330
+                               stringappend_13350) in
+  (let (rs1, stringappend_13380) =
+       ((case  ((reg_name_matches_prefix stringappend_13360 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13370,stringappend_13380) =>
+        (stringappend_13370, stringappend_13380)
+        )) in
+  (let stringappend_13390 = (string_drop stringappend_13360
+                               stringappend_13380) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13390)) of
+        Some (stringappend_13400,stringappend_13410) =>
+  (stringappend_13400, stringappend_13410)
+  ) of
+      (_, stringappend_13410) =>
+  (let stringappend_13420 = (string_drop stringappend_13390
+                               stringappend_13410) in
+  (let (rs2, stringappend_13440) =
+       ((case  ((reg_name_matches_prefix stringappend_13420 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13430,stringappend_13440) =>
+        (stringappend_13430, stringappend_13440)
+        )) in
+  if(((string_drop stringappend_13420 stringappend_13440)) = ('''')) then
+    (MUL (rs2,rs1,rd,high,signed1,signed2)) else undefined))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_10760 (''div''))) \<and> ((let stringappend_13460 = (string_drop stringappend_10760 ((string_length (''div'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_13460)) of
+                   Some (stringappend_13470,stringappend_13480) =>
+                    (let stringappend_13490 = (string_drop stringappend_13460 stringappend_13480) in
+                    if ((case  ((spc_matches_prefix stringappend_13490)) of
+                        Some (stringappend_13500,stringappend_13510) =>
+                         (let stringappend_13520 =
+                           (string_drop stringappend_13490 stringappend_13510) in
+                         if ((case  ((reg_name_matches_prefix stringappend_13520
+                                      ::  (( 5 Word.word * ii))option)) of
+                             Some (stringappend_13530,stringappend_13540) =>
+                              (let stringappend_13550 =
+                                (string_drop stringappend_13520 stringappend_13540) in
+                              if ((case  ((sep_matches_prefix stringappend_13550)) of
+                                  Some (stringappend_13560,stringappend_13570) =>
+                                   (let stringappend_13580 =
+                                     (string_drop stringappend_13550 stringappend_13570) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_13580
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_13590,stringappend_13600) =>
+                                        (let stringappend_13610 =
+                                          (string_drop stringappend_13580 stringappend_13600) in
+                                        if ((case  ((sep_matches_prefix stringappend_13610)) of
+                                            Some (stringappend_13620,stringappend_13630) =>
+                                             (let stringappend_13640 =
+                                               (string_drop stringappend_13610 stringappend_13630) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_13640
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_13650,stringappend_13660) => 
+  if(((string_drop stringappend_13640 stringappend_13660)) = ('''')) then
+    True else False
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_13460 = (string_drop stringappend_10760 ((string_length (''div'')))) in
+     (let (s, stringappend_13480) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_13460)) of
+         Some (stringappend_13470,stringappend_13480) =>
+          (stringappend_13470, stringappend_13480)
+       )) in
+     (let stringappend_13490 = (string_drop stringappend_13460 stringappend_13480) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_13490)) of
+        Some (stringappend_13500,stringappend_13510) =>
+  (stringappend_13500, stringappend_13510)
+  ) of
+      (_, stringappend_13510) =>
+  (let stringappend_13520 = (string_drop stringappend_13490
+                               stringappend_13510) in
+  (let (rd, stringappend_13540) =
+       ((case  ((reg_name_matches_prefix stringappend_13520 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13530,stringappend_13540) =>
+        (stringappend_13530, stringappend_13540)
+        )) in
+  (let stringappend_13550 = (string_drop stringappend_13520
+                               stringappend_13540) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13550)) of
+        Some (stringappend_13560,stringappend_13570) =>
+  (stringappend_13560, stringappend_13570)
+  ) of
+      (_, stringappend_13570) =>
+  (let stringappend_13580 = (string_drop stringappend_13550
+                               stringappend_13570) in
+  (let (rs1, stringappend_13600) =
+       ((case  ((reg_name_matches_prefix stringappend_13580 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13590,stringappend_13600) =>
+        (stringappend_13590, stringappend_13600)
+        )) in
+  (let stringappend_13610 = (string_drop stringappend_13580
+                               stringappend_13600) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13610)) of
+        Some (stringappend_13620,stringappend_13630) =>
+  (stringappend_13620, stringappend_13630)
+  ) of
+      (_, stringappend_13630) =>
+  (let stringappend_13640 = (string_drop stringappend_13610
+                               stringappend_13630) in
+  (let (rs2, stringappend_13660) =
+       ((case  ((reg_name_matches_prefix stringappend_13640 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13650,stringappend_13660) =>
+        (stringappend_13650, stringappend_13660)
+        )) in
+  if(((string_drop stringappend_13640 stringappend_13660)) = ('''')) then
+    (DIV (rs2,rs1,rd,s)) else undefined))
+  ))))
+  ))))
+  ))))
+   else if (((((string_startswith stringappend_10760 (''rem''))) \<and> ((let stringappend_13680 = (string_drop stringappend_10760 ((string_length (''rem'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_13680)) of
+                   Some (stringappend_13690,stringappend_13700) =>
+                    (let stringappend_13710 = (string_drop stringappend_13680 stringappend_13700) in
+                    if ((case  ((spc_matches_prefix stringappend_13710)) of
+                        Some (stringappend_13720,stringappend_13730) =>
+                         (let stringappend_13740 =
+                           (string_drop stringappend_13710 stringappend_13730) in
+                         if ((case  ((reg_name_matches_prefix stringappend_13740
+                                      ::  (( 5 Word.word * ii))option)) of
+                             Some (stringappend_13750,stringappend_13760) =>
+                              (let stringappend_13770 =
+                                (string_drop stringappend_13740 stringappend_13760) in
+                              if ((case  ((sep_matches_prefix stringappend_13770)) of
+                                  Some (stringappend_13780,stringappend_13790) =>
+                                   (let stringappend_13800 =
+                                     (string_drop stringappend_13770 stringappend_13790) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_13800
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_13810,stringappend_13820) =>
+                                        (let stringappend_13830 =
+                                          (string_drop stringappend_13800 stringappend_13820) in
+                                        if ((case  ((sep_matches_prefix stringappend_13830)) of
+                                            Some (stringappend_13840,stringappend_13850) =>
+                                             (let stringappend_13860 =
+                                               (string_drop stringappend_13830 stringappend_13850) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_13860
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_13870,stringappend_13880) => 
+  if(((string_drop stringappend_13860 stringappend_13880)) = ('''')) then
+    True else False
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_13680 = (string_drop stringappend_10760 ((string_length (''rem'')))) in
+     (let (s, stringappend_13700) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_13680)) of
+         Some (stringappend_13690,stringappend_13700) =>
+          (stringappend_13690, stringappend_13700)
+       )) in
+     (let stringappend_13710 = (string_drop stringappend_13680 stringappend_13700) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_13710)) of
+        Some (stringappend_13720,stringappend_13730) =>
+  (stringappend_13720, stringappend_13730)
+  ) of
+      (_, stringappend_13730) =>
+  (let stringappend_13740 = (string_drop stringappend_13710
+                               stringappend_13730) in
+  (let (rd, stringappend_13760) =
+       ((case  ((reg_name_matches_prefix stringappend_13740 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13750,stringappend_13760) =>
+        (stringappend_13750, stringappend_13760)
+        )) in
+  (let stringappend_13770 = (string_drop stringappend_13740
+                               stringappend_13760) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13770)) of
+        Some (stringappend_13780,stringappend_13790) =>
+  (stringappend_13780, stringappend_13790)
+  ) of
+      (_, stringappend_13790) =>
+  (let stringappend_13800 = (string_drop stringappend_13770
+                               stringappend_13790) in
+  (let (rs1, stringappend_13820) =
+       ((case  ((reg_name_matches_prefix stringappend_13800 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13810,stringappend_13820) =>
+        (stringappend_13810, stringappend_13820)
+        )) in
+  (let stringappend_13830 = (string_drop stringappend_13800
+                               stringappend_13820) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13830)) of
+        Some (stringappend_13840,stringappend_13850) =>
+  (stringappend_13840, stringappend_13850)
+  ) of
+      (_, stringappend_13850) =>
+  (let stringappend_13860 = (string_drop stringappend_13830
+                               stringappend_13850) in
+  (let (rs2, stringappend_13880) =
+       ((case  ((reg_name_matches_prefix stringappend_13860 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13870,stringappend_13880) =>
+        (stringappend_13870, stringappend_13880)
+        )) in
+  if(((string_drop stringappend_13860 stringappend_13880)) = ('''')) then
+    (REM (rs2,rs1,rd,s)) else undefined))
+  ))))
+  ))))
+  ))))
+   else if (((((string_startswith stringappend_10760 (''mulw''))) \<and> ((let stringappend_13900 = (string_drop stringappend_10760 ((string_length (''mulw'')))) in
+               if ((case  ((spc_matches_prefix stringappend_13900)) of
+                   Some (stringappend_13910,stringappend_13920) =>
+                    (let stringappend_13930 = (string_drop stringappend_13900 stringappend_13920) in
+                    if ((case  ((reg_name_matches_prefix stringappend_13930
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_13940,stringappend_13950) =>
+                         (let stringappend_13960 =
+                           (string_drop stringappend_13930 stringappend_13950) in
+                         if ((case  ((sep_matches_prefix stringappend_13960)) of
+                             Some (stringappend_13970,stringappend_13980) =>
+                              (let stringappend_13990 =
+                                (string_drop stringappend_13960 stringappend_13980) in
+                              if ((case  ((reg_name_matches_prefix stringappend_13990
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_14000,stringappend_14010) =>
+                                   (let stringappend_14020 =
+                                     (string_drop stringappend_13990 stringappend_14010) in
+                                   if ((case  ((sep_matches_prefix stringappend_14020)) of
+                                       Some (stringappend_14030,stringappend_14040) =>
+                                        (let stringappend_14050 =
+                                          (string_drop stringappend_14020 stringappend_14040) in
+                                        if ((case  ((reg_name_matches_prefix stringappend_14050
+                                                     ::  (( 5 Word.word * ii))option)) of
+                                            Some (stringappend_14060,stringappend_14070) => 
+  if(((string_drop stringappend_14050 stringappend_14070)) = ('''')) then
+    True else False
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_13900 = (string_drop stringappend_10760 ((string_length (''mulw'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_13900)) of
+        Some (stringappend_13910,stringappend_13920) =>
+  (stringappend_13910, stringappend_13920)
+  ) of
+      (_, stringappend_13920) =>
+  (let stringappend_13930 = (string_drop stringappend_13900
+                               stringappend_13920) in
+  (let (rd, stringappend_13950) =
+       ((case  ((reg_name_matches_prefix stringappend_13930 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_13940,stringappend_13950) =>
+        (stringappend_13940, stringappend_13950)
+        )) in
+  (let stringappend_13960 = (string_drop stringappend_13930
+                               stringappend_13950) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_13960)) of
+        Some (stringappend_13970,stringappend_13980) =>
+  (stringappend_13970, stringappend_13980)
+  ) of
+      (_, stringappend_13980) =>
+  (let stringappend_13990 = (string_drop stringappend_13960
+                               stringappend_13980) in
+  (let (rs1, stringappend_14010) =
+       ((case  ((reg_name_matches_prefix stringappend_13990 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14000,stringappend_14010) =>
+        (stringappend_14000, stringappend_14010)
+        )) in
+  (let stringappend_14020 = (string_drop stringappend_13990
+                               stringappend_14010) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_14020)) of
+        Some (stringappend_14030,stringappend_14040) =>
+  (stringappend_14030, stringappend_14040)
+  ) of
+      (_, stringappend_14040) =>
+  (let stringappend_14050 = (string_drop stringappend_14020
+                               stringappend_14040) in
+  (let (rs2, stringappend_14070) =
+       ((case  ((reg_name_matches_prefix stringappend_14050 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14060,stringappend_14070) =>
+        (stringappend_14060, stringappend_14070)
+        )) in
+  if(((string_drop stringappend_14050 stringappend_14070)) = ('''')) then
+    (MULW (rs2,rs1,rd)) else undefined))
+  ))))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_10760 (''div''))) \<and> ((let stringappend_14090 = (string_drop stringappend_10760 ((string_length (''div'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_14090)) of
+                   Some (stringappend_14100,stringappend_14110) =>
+                    (let stringappend_14120 = (string_drop stringappend_14090 stringappend_14110) in
+                    if (((((string_startswith stringappend_14120 (''w''))) \<and> ((let stringappend_14130 =
+                             (string_drop stringappend_14120 ((string_length (''w'')))) in
+                           if ((case  ((spc_matches_prefix stringappend_14130)) of
+                               Some (stringappend_14140,stringappend_14150) =>
+                                (let stringappend_14160 =
+                                  (string_drop stringappend_14130 stringappend_14150) in
+                                if ((case  ((reg_name_matches_prefix stringappend_14160
+                                             ::  (( 5 Word.word * ii))option)) of
+                                    Some (stringappend_14170,stringappend_14180) =>
+                                     (let stringappend_14190 =
+                                       (string_drop stringappend_14160 stringappend_14180) in
+                                     if ((case  ((sep_matches_prefix stringappend_14190)) of
+                                         Some (stringappend_14200,stringappend_14210) =>
+                                          (let stringappend_14220 =
+                                            (string_drop stringappend_14190 stringappend_14210) in
+                                          if ((case  ((reg_name_matches_prefix stringappend_14220
+                                                       ::  (( 5 Word.word * ii))option)) of
+                                              Some (stringappend_14230,stringappend_14240) =>
+                                               (let stringappend_14250 =
+                                                 (string_drop stringappend_14220 stringappend_14240) in
+                                               if ((case  ((sep_matches_prefix stringappend_14250)) of
+                                                   Some (stringappend_14260,stringappend_14270) =>
+                                                    (let stringappend_14280 =
+                                                      (string_drop stringappend_14250
+                                                        stringappend_14270) in
+                                                    if ((case  ((reg_name_matches_prefix
+                                                                  stringappend_14280
+                                                                 ::  (( 5 Word.word * ii))option)) of
+                                                        Some
+                                                        (stringappend_14290,stringappend_14300) => 
+  if(((string_drop stringappend_14280 stringappend_14300)) = ('''')) then
+    True else False
+                                                      | None => False
+                                                      )) then
+                                                      True
+                                                    else False)
+                                                 | None => False
+                                                 )) then
+                                                 True
+                                               else False)
+                                            | None => False
+                                            )) then
+                                            True
+                                          else False)
+                                       | None => False
+                                       )) then
+                                       True
+                                     else False)
+                                  | None => False
+                                  )) then
+                                  True
+                                else False)
+                             | None => False
+                             )) then
+                             True
+                           else False))))) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_14090 = (string_drop stringappend_10760 ((string_length (''div'')))) in
+     (let (s, stringappend_14110) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_14090)) of
+         Some (stringappend_14100,stringappend_14110) =>
+          (stringappend_14100, stringappend_14110)
+       )) in
+     (let stringappend_14120 = (string_drop stringappend_14090 stringappend_14110) in
+     (let stringappend_14130 = (string_drop stringappend_14120 ((string_length (''w'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_14130)) of
+        Some (stringappend_14140,stringappend_14150) =>
+  (stringappend_14140, stringappend_14150)
+  ) of
+      (_, stringappend_14150) =>
+  (let stringappend_14160 = (string_drop stringappend_14130
+                               stringappend_14150) in
+  (let (rd, stringappend_14180) =
+       ((case  ((reg_name_matches_prefix stringappend_14160 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14170,stringappend_14180) =>
+        (stringappend_14170, stringappend_14180)
+        )) in
+  (let stringappend_14190 = (string_drop stringappend_14160
+                               stringappend_14180) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_14190)) of
+        Some (stringappend_14200,stringappend_14210) =>
+  (stringappend_14200, stringappend_14210)
+  ) of
+      (_, stringappend_14210) =>
+  (let stringappend_14220 = (string_drop stringappend_14190
+                               stringappend_14210) in
+  (let (rs1, stringappend_14240) =
+       ((case  ((reg_name_matches_prefix stringappend_14220 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14230,stringappend_14240) =>
+        (stringappend_14230, stringappend_14240)
+        )) in
+  (let stringappend_14250 = (string_drop stringappend_14220
+                               stringappend_14240) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_14250)) of
+        Some (stringappend_14260,stringappend_14270) =>
+  (stringappend_14260, stringappend_14270)
+  ) of
+      (_, stringappend_14270) =>
+  (let stringappend_14280 = (string_drop stringappend_14250
+                               stringappend_14270) in
+  (let (rs2, stringappend_14300) =
+       ((case  ((reg_name_matches_prefix stringappend_14280 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14290,stringappend_14300) =>
+        (stringappend_14290, stringappend_14300)
+        )) in
+  if(((string_drop stringappend_14280 stringappend_14300)) = ('''')) then
+    (DIVW (rs2,rs1,rd,s)) else undefined))
+  ))))
+  ))))
+  )))))
+   else if (((((string_startswith stringappend_10760 (''rem''))) \<and> ((let stringappend_14320 = (string_drop stringappend_10760 ((string_length (''rem'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_14320)) of
+                   Some (stringappend_14330,stringappend_14340) =>
+                    (let stringappend_14350 = (string_drop stringappend_14320 stringappend_14340) in
+                    if (((((string_startswith stringappend_14350 (''w''))) \<and> ((let stringappend_14360 =
+                             (string_drop stringappend_14350 ((string_length (''w'')))) in
+                           if ((case  ((spc_matches_prefix stringappend_14360)) of
+                               Some (stringappend_14370,stringappend_14380) =>
+                                (let stringappend_14390 =
+                                  (string_drop stringappend_14360 stringappend_14380) in
+                                if ((case  ((reg_name_matches_prefix stringappend_14390
+                                             ::  (( 5 Word.word * ii))option)) of
+                                    Some (stringappend_14400,stringappend_14410) =>
+                                     (let stringappend_14420 =
+                                       (string_drop stringappend_14390 stringappend_14410) in
+                                     if ((case  ((sep_matches_prefix stringappend_14420)) of
+                                         Some (stringappend_14430,stringappend_14440) =>
+                                          (let stringappend_14450 =
+                                            (string_drop stringappend_14420 stringappend_14440) in
+                                          if ((case  ((reg_name_matches_prefix stringappend_14450
+                                                       ::  (( 5 Word.word * ii))option)) of
+                                              Some (stringappend_14460,stringappend_14470) =>
+                                               (let stringappend_14480 =
+                                                 (string_drop stringappend_14450 stringappend_14470) in
+                                               if ((case  ((sep_matches_prefix stringappend_14480)) of
+                                                   Some (stringappend_14490,stringappend_14500) =>
+                                                    (let stringappend_14510 =
+                                                      (string_drop stringappend_14480
+                                                        stringappend_14500) in
+                                                    if ((case  ((reg_name_matches_prefix
+                                                                  stringappend_14510
+                                                                 ::  (( 5 Word.word * ii))option)) of
+                                                        Some
+                                                        (stringappend_14520,stringappend_14530) => 
+  if(((string_drop stringappend_14510 stringappend_14530)) = ('''')) then
+    True else False
+                                                      | None => False
+                                                      )) then
+                                                      True
+                                                    else False)
+                                                 | None => False
+                                                 )) then
+                                                 True
+                                               else False)
+                                            | None => False
+                                            )) then
+                                            True
+                                          else False)
+                                       | None => False
+                                       )) then
+                                       True
+                                     else False)
+                                  | None => False
+                                  )) then
+                                  True
+                                else False)
+                             | None => False
+                             )) then
+                             True
+                           else False))))) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_14320 = (string_drop stringappend_10760 ((string_length (''rem'')))) in
+     (let (s, stringappend_14340) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_14320)) of
+         Some (stringappend_14330,stringappend_14340) =>
+          (stringappend_14330, stringappend_14340)
+       )) in
+     (let stringappend_14350 = (string_drop stringappend_14320 stringappend_14340) in
+     (let stringappend_14360 = (string_drop stringappend_14350 ((string_length (''w'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_14360)) of
+        Some (stringappend_14370,stringappend_14380) =>
+  (stringappend_14370, stringappend_14380)
+  ) of
+      (_, stringappend_14380) =>
+  (let stringappend_14390 = (string_drop stringappend_14360
+                               stringappend_14380) in
+  (let (rd, stringappend_14410) =
+       ((case  ((reg_name_matches_prefix stringappend_14390 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14400,stringappend_14410) =>
+        (stringappend_14400, stringappend_14410)
+        )) in
+  (let stringappend_14420 = (string_drop stringappend_14390
+                               stringappend_14410) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_14420)) of
+        Some (stringappend_14430,stringappend_14440) =>
+  (stringappend_14430, stringappend_14440)
+  ) of
+      (_, stringappend_14440) =>
+  (let stringappend_14450 = (string_drop stringappend_14420
+                               stringappend_14440) in
+  (let (rs1, stringappend_14470) =
+       ((case  ((reg_name_matches_prefix stringappend_14450 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14460,stringappend_14470) =>
+        (stringappend_14460, stringappend_14470)
+        )) in
+  (let stringappend_14480 = (string_drop stringappend_14450
+                               stringappend_14470) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_14480)) of
+        Some (stringappend_14490,stringappend_14500) =>
+  (stringappend_14490, stringappend_14500)
+  ) of
+      (_, stringappend_14500) =>
+  (let stringappend_14510 = (string_drop stringappend_14480
+                               stringappend_14500) in
+  (let (rs2, stringappend_14530) =
+       ((case  ((reg_name_matches_prefix stringappend_14510 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_14520,stringappend_14530) =>
+        (stringappend_14520, stringappend_14530)
+        )) in
+  if(((string_drop stringappend_14510 stringappend_14530)) = ('''')) then
+    (REMW (rs2,rs1,rd,s)) else undefined))
+  ))))
+  ))))
+  )))))
+   else if (((((string_startswith stringappend_10760 (''fence''))) \<and> ((let stringappend_14550 = (string_drop stringappend_10760 ((string_length (''fence'')))) in
+               if ((case  ((spc_matches_prefix stringappend_14550)) of
+                   Some (stringappend_14560,stringappend_14570) =>
+                    (let stringappend_14580 = (string_drop stringappend_14550 stringappend_14570) in
+                    if ((case  ((fence_bits_matches_prefix stringappend_14580
+                                 ::  (( 4 Word.word * ii))option)) of
+                        Some (stringappend_14590,stringappend_14600) =>
+                         (let stringappend_14610 =
+                           (string_drop stringappend_14580 stringappend_14600) in
+                         if ((case  ((sep_matches_prefix stringappend_14610)) of
+                             Some (stringappend_14620,stringappend_14630) =>
+                              (let stringappend_14640 =
+                                (string_drop stringappend_14610 stringappend_14630) in
+                              if ((case  ((fence_bits_matches_prefix stringappend_14640
+                                           ::  (( 4 Word.word * ii))option)) of
+                                  Some (stringappend_14650,stringappend_14660) => 
+  if(((string_drop stringappend_14640 stringappend_14660)) = ('''')) then
+    True else False
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_14550 = (string_drop stringappend_10760 ((string_length (''fence'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_14550)) of
+        Some (stringappend_14560,stringappend_14570) =>
+  (stringappend_14560, stringappend_14570)
+  ) of
+      (_, stringappend_14570) =>
+  (let stringappend_14580 = (string_drop stringappend_14550
+                               stringappend_14570) in
+  (let (pred, stringappend_14600) =
+       ((case  ((fence_bits_matches_prefix stringappend_14580 :: (( 4 Word.word * ii)) option)) of
+              Some (stringappend_14590,stringappend_14600) =>
+        (stringappend_14590, stringappend_14600)
+        )) in
+  (let stringappend_14610 = (string_drop stringappend_14580
+                               stringappend_14600) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_14610)) of
+        Some (stringappend_14620,stringappend_14630) =>
+  (stringappend_14620, stringappend_14630)
+  ) of
+      (_, stringappend_14630) =>
+  (let stringappend_14640 = (string_drop stringappend_14610
+                               stringappend_14630) in
+  (let (succ, stringappend_14660) =
+       ((case  ((fence_bits_matches_prefix stringappend_14640 :: (( 4 Word.word * ii)) option)) of
+              Some (stringappend_14650,stringappend_14660) =>
+        (stringappend_14650, stringappend_14660)
+        )) in
+  if(((string_drop stringappend_14640 stringappend_14660)) = ('''')) then
+    (FENCE (pred,succ)) else undefined))
+  ))))
+  ))
+   else  if(stringappend_10760 = (''fence.i'')) then (FENCEI () ) else
+   (
+   if(stringappend_10760 = (''ecall'')) then (ECALL () ) else
+     (
+     if(stringappend_10760 = (''mret'')) then (MRET () ) else
+       (
+       if(stringappend_10760 = (''sret'')) then (SRET () ) else
+         (
+         if(stringappend_10760 = (''ebreak'')) then (EBREAK () ) else
+           (
+           if(stringappend_10760 = (''wfi'')) then (WFI () ) else
+             (
+             if (((((string_startswith stringappend_10760 (''sfence.vma'')))
+                     \<and>
+                     ((let stringappend_14680 =
+                           (string_drop stringappend_10760
+                              ((string_length (''sfence.vma'')))) in
+                      if ((case  ((spc_matches_prefix stringappend_14680)) of
+                                Some (stringappend_14690,stringappend_14700) =>
+                          (let stringappend_14710 = (string_drop
+                                                       stringappend_14680
+                                                       stringappend_14700) in
+                          if ((case  ((reg_name_matches_prefix
+                                         stringappend_14710
+                                      :: (( 5 Word.word * ii)) option)) of
+                                    Some (stringappend_14720,stringappend_14730) =>
+                              (let stringappend_14740 =
+                                   (string_drop stringappend_14710
+                                      stringappend_14730) in
+                              if ((case  ((sep_matches_prefix
+                                             stringappend_14740)) of
+                                        Some (stringappend_14750,stringappend_14760) =>
+                                  (let stringappend_14770 =
+                                       (string_drop stringappend_14740
+                                          stringappend_14760) in
+                                  if ((case  ((reg_name_matches_prefix
+                                                 stringappend_14770
+                                              :: (( 5 Word.word * ii)) option)) of
+                                            Some (stringappend_14780,stringappend_14790) =>
+                                      if(((string_drop stringappend_14770
+                                             stringappend_14790)) = ('''')) then
+                                        True else False
+                                        | None => False
+                                      )) then True else False)
+                                    | None => False
+                                  )) then True else False)
+                                | None => False
+                              )) then True else False)
+                            | None => False
+                          )) then True else False))))) then
+               (let stringappend_14680 = (string_drop stringappend_10760
+                                            ((string_length (''sfence.vma'')))) in
+               (case 
+               (case  ((spc_matches_prefix stringappend_14680)) of
+                     Some (stringappend_14690,stringappend_14700) =>
+               (stringappend_14690, stringappend_14700)
+               ) of
+                   (_, stringappend_14700) =>
+               (let stringappend_14710 = (string_drop stringappend_14680
+                                            stringappend_14700) in
+               (let (rs1, stringappend_14730) =
+                    ((case  ((reg_name_matches_prefix stringappend_14710 :: (( 5 Word.word * ii)) option)) of
+                           Some (stringappend_14720,stringappend_14730) =>
+                     (stringappend_14720, stringappend_14730)
+                     )) in
+               (let stringappend_14740 = (string_drop stringappend_14710
+                                            stringappend_14730) in
+               (case 
+               (case  ((sep_matches_prefix stringappend_14740)) of
+                     Some (stringappend_14750,stringappend_14760) =>
+               (stringappend_14750, stringappend_14760)
+               ) of
+                   (_, stringappend_14760) =>
+               (let stringappend_14770 = (string_drop stringappend_14740
+                                            stringappend_14760) in
+               (let (rs2, stringappend_14790) =
+                    ((case  ((reg_name_matches_prefix stringappend_14770 :: (( 5 Word.word * ii)) option)) of
+                           Some (stringappend_14780,stringappend_14790) =>
+                     (stringappend_14780, stringappend_14790)
+                     )) in
+               if(((string_drop stringappend_14770 stringappend_14790)) =
+                    ('''')) then (SFENCE_VMA (rs1,rs2)) else undefined))
+               ))))
+               )) else
+               if (((((string_startswith stringappend_10760 (''lr.'')))
+                       \<and>
+                       ((let stringappend_14810 =
+                             (string_drop stringappend_10760
+                                ((string_length (''lr.'')))) in
+                        if ((case  ((maybe_aq_matches_prefix
+                                       stringappend_14810)) of
+                                  Some (stringappend_14820,stringappend_14830) =>
+                            (let stringappend_14840 =
+                                 (string_drop stringappend_14810
+                                    stringappend_14830) in
+                            if ((case  ((maybe_rl_matches_prefix
+                                           stringappend_14840)) of
+                                      Some (stringappend_14850,stringappend_14860) =>
+                                (let stringappend_14870 =
+                                     (string_drop stringappend_14840
+                                        stringappend_14860) in
+                                if ((case  ((size_mnemonic_matches_prefix
+                                               stringappend_14870)) of
+                                          Some (stringappend_14880,stringappend_14890) =>
+                                    (let stringappend_14900 =
+                                         (string_drop stringappend_14870
+                                            stringappend_14890) in
+                                    if ((case  ((spc_matches_prefix
+                                                   stringappend_14900)) of
+                                              Some (stringappend_14910,stringappend_14920) =>
+                                        (let stringappend_14930 =
+                                             (string_drop stringappend_14900
+                                                stringappend_14920) in
+                                        if ((case  ((reg_name_matches_prefix
+                                                       stringappend_14930
+                                                    :: (( 5 Word.word * ii)) option)) of
+                                                  Some (stringappend_14940,stringappend_14950) =>
+                                            (let stringappend_14960 =
+                                                 (string_drop
+                                                    stringappend_14930
+                                                    stringappend_14950) in
+                                            if ((case  ((sep_matches_prefix
+                                                           stringappend_14960)) of
+                                                      Some (stringappend_14970,stringappend_14980) =>
+                                                (let stringappend_14990 =
+                                                     (string_drop
+                                                        stringappend_14960
+                                                        stringappend_14980) in
+                                                if ((case  ((reg_name_matches_prefix
+                                                               stringappend_14990
+                                                            :: (( 5 Word.word * ii)) option)) of
+                                                          Some (stringappend_15000,stringappend_15010) =>
+                                                    if(((string_drop
+                                                           stringappend_14990
+                                                           stringappend_15010))
+                                                         = ('''')) then 
+                                                    True else False
+                                                      | None => False
+                                                    )) then True else 
+                                                False)
+                                                  | None => False
+                                                )) then True else False)
+                                              | None => False
+                                            )) then True else False)
+                                          | None => False
+                                        )) then True else False)
+                                      | None => False
+                                    )) then True else False)
+                                  | None => False
+                                )) then True else False)
+                              | None => False
+                            )) then True else False))))) then
+                 (let stringappend_14810 = (string_drop stringappend_10760
+                                              ((string_length (''lr.'')))) in
+                 (let (aq, stringappend_14830) =
+                      ((case  ((maybe_aq_matches_prefix stringappend_14810)) of
+                             Some (stringappend_14820,stringappend_14830) =>
+                       (stringappend_14820, stringappend_14830)
+                       )) in
+                 (let stringappend_14840 = (string_drop stringappend_14810
+                                              stringappend_14830) in
+                 (let (rl, stringappend_14860) =
+                      ((case  ((maybe_rl_matches_prefix stringappend_14840)) of
+                             Some (stringappend_14850,stringappend_14860) =>
+                       (stringappend_14850, stringappend_14860)
+                       )) in
+                 (let stringappend_14870 = (string_drop stringappend_14840
+                                              stringappend_14860) in
+                 (let (size1, stringappend_14890) =
+                      ((case  ((size_mnemonic_matches_prefix
+                                  stringappend_14870)) of
+                             Some (stringappend_14880,stringappend_14890) =>
+                       (stringappend_14880, stringappend_14890)
+                       )) in
+                 (let stringappend_14900 = (string_drop stringappend_14870
+                                              stringappend_14890) in
+                 (case 
+                 (case  ((spc_matches_prefix stringappend_14900)) of
+                       Some (stringappend_14910,stringappend_14920) =>
+                 (stringappend_14910, stringappend_14920)
+                 ) of
+                     (_, stringappend_14920) =>
+                 (let stringappend_14930 = (string_drop stringappend_14900
+                                              stringappend_14920) in
+                 (let (rd, stringappend_14950) =
+                      ((case  ((reg_name_matches_prefix stringappend_14930 :: (( 5 Word.word * ii)) option)) of
+                             Some (stringappend_14940,stringappend_14950) =>
+                       (stringappend_14940, stringappend_14950)
+                       )) in
+                 (let stringappend_14960 = (string_drop stringappend_14930
+                                              stringappend_14950) in
+                 (case 
+                 (case  ((sep_matches_prefix stringappend_14960)) of
+                       Some (stringappend_14970,stringappend_14980) =>
+                 (stringappend_14970, stringappend_14980)
+                 ) of
+                     (_, stringappend_14980) =>
+                 (let stringappend_14990 = (string_drop stringappend_14960
+                                              stringappend_14980) in
+                 (let (rs1, stringappend_15010) =
+                      ((case  ((reg_name_matches_prefix stringappend_14990 :: (( 5 Word.word * ii)) option)) of
+                             Some (stringappend_15000,stringappend_15010) =>
+                       (stringappend_15000, stringappend_15010)
+                       )) in
+                 if(((string_drop stringappend_14990 stringappend_15010)) =
+                      ('''')) then (LOADRES (aq,rl,rs1,size1,rd)) else
+                   undefined))
+                 ))))
+                 )))))))) else
+                 if (((((string_startswith stringappend_10760 (''sc.'')))
+                         \<and>
+                         ((let stringappend_15030 =
+                               (string_drop stringappend_10760
+                                  ((string_length (''sc.'')))) in
+                          if ((case  ((maybe_aq_matches_prefix
+                                         stringappend_15030)) of
+                                    Some (stringappend_15040,stringappend_15050) =>
+                              (let stringappend_15060 =
+                                   (string_drop stringappend_15030
+                                      stringappend_15050) in
+                              if ((case  ((maybe_rl_matches_prefix
+                                             stringappend_15060)) of
+                                        Some (stringappend_15070,stringappend_15080) =>
+                                  (let stringappend_15090 =
+                                       (string_drop stringappend_15060
+                                          stringappend_15080) in
+                                  if ((case  ((size_mnemonic_matches_prefix
+                                                 stringappend_15090)) of
+                                            Some (stringappend_15100,stringappend_15110) =>
+                                      (let stringappend_15120 =
+                                           (string_drop stringappend_15090
+                                              stringappend_15110) in
+                                      if ((case  ((spc_matches_prefix
+                                                     stringappend_15120)) of
+                                                Some (stringappend_15130,stringappend_15140) =>
+                                          (let stringappend_15150 =
+                                               (string_drop
+                                                  stringappend_15120
+                                                  stringappend_15140) in
+                                          if ((case  ((reg_name_matches_prefix
+                                                         stringappend_15150
+                                                      :: (( 5 Word.word * ii)) option)) of
+                                                    Some (stringappend_15160,stringappend_15170) =>
+                                              (let stringappend_15180 =
+                                                   (string_drop
+                                                      stringappend_15150
+                                                      stringappend_15170) in
+                                              if ((case  ((sep_matches_prefix
+                                                             stringappend_15180)) of
+                                                        Some (stringappend_15190,stringappend_15200) =>
+                                                  (let stringappend_15210 =
+                                                       (string_drop
+                                                          stringappend_15180
+                                                          stringappend_15200) in
+                                                  if ((case  ((reg_name_matches_prefix
+                                                                 stringappend_15210
+                                                              :: (( 5 Word.word * ii)) option)) of
+                                                            Some (stringappend_15220,stringappend_15230) =>
+                                                      (let stringappend_15240 =
+                                                           (string_drop
+                                                              stringappend_15210
+                                                              stringappend_15230) in
+                                                      if ((case  ((sep_matches_prefix
+                                                                    stringappend_15240)) of
+                                                                Some
+                                                          (stringappend_15250,stringappend_15260) =>
+                                                          (let stringappend_15270 =
+                                                               (string_drop
+                                                                  stringappend_15240
+                                                                  stringappend_15260) in
+                                                          if ((case  
+                                                              ((reg_name_matches_prefix
+                                                                  stringappend_15270
+                                                               :: (( 5 Word.word * ii)) option)) of
+                                                                    Some
+                                                              (stringappend_15280,stringappend_15290) =>
+                                                              if(((string_drop
+                                                                    stringappend_15270
+                                                                    stringappend_15290))
+                                                                   = 
+                                                                 ('''')) then
+                                                                True else
+                                                                False
+                                                                | None => 
+                                                              False
+                                                              )) then 
+                                                          True else False)
+                                                            | None => 
+                                                          False
+                                                          )) then True else
+                                                        False)
+                                                        | None => False
+                                                      )) then True else 
+                                                  False)
+                                                    | None => False
+                                                  )) then True else False)
+                                                | None => False
+                                              )) then True else False)
+                                            | None => False
+                                          )) then True else False)
+                                        | None => False
+                                      )) then True else False)
+                                    | None => False
+                                  )) then True else False)
+                                | None => False
+                              )) then True else False))))) then
+                   (let stringappend_15030 = (string_drop stringappend_10760
+                                                ((string_length (''sc.'')))) in
+                   (let (aq, stringappend_15050) =
+                        ((case  ((maybe_aq_matches_prefix stringappend_15030)) of
+                               Some (stringappend_15040,stringappend_15050) =>
+                         (stringappend_15040, stringappend_15050)
+                         )) in
+                   (let stringappend_15060 = (string_drop stringappend_15030
+                                                stringappend_15050) in
+                   (let (rl, stringappend_15080) =
+                        ((case  ((maybe_rl_matches_prefix stringappend_15060)) of
+                               Some (stringappend_15070,stringappend_15080) =>
+                         (stringappend_15070, stringappend_15080)
+                         )) in
+                   (let stringappend_15090 = (string_drop stringappend_15060
+                                                stringappend_15080) in
+                   (let (size1, stringappend_15110) =
+                        ((case  ((size_mnemonic_matches_prefix
+                                    stringappend_15090)) of
+                               Some (stringappend_15100,stringappend_15110) =>
+                         (stringappend_15100, stringappend_15110)
+                         )) in
+                   (let stringappend_15120 = (string_drop stringappend_15090
+                                                stringappend_15110) in
+                   (case 
+                   (case  ((spc_matches_prefix stringappend_15120)) of
+                         Some (stringappend_15130,stringappend_15140) =>
+                   (stringappend_15130, stringappend_15140)
+                   ) of
+                       (_, stringappend_15140) =>
+                   (let stringappend_15150 = (string_drop stringappend_15120
+                                                stringappend_15140) in
+                   (let (rd, stringappend_15170) =
+                        ((case  ((reg_name_matches_prefix stringappend_15150 :: (( 5 Word.word * ii)) option)) of
+                               Some (stringappend_15160,stringappend_15170) =>
+                         (stringappend_15160, stringappend_15170)
+                         )) in
+                   (let stringappend_15180 = (string_drop stringappend_15150
+                                                stringappend_15170) in
+                   (case 
+                   (case  ((sep_matches_prefix stringappend_15180)) of
+                         Some (stringappend_15190,stringappend_15200) =>
+                   (stringappend_15190, stringappend_15200)
+                   ) of
+                       (_, stringappend_15200) =>
+                   (let stringappend_15210 = (string_drop stringappend_15180
+                                                stringappend_15200) in
+                   (let (rs1, stringappend_15230) =
+                        ((case  ((reg_name_matches_prefix stringappend_15210 :: (( 5 Word.word * ii)) option)) of
+                               Some (stringappend_15220,stringappend_15230) =>
+                         (stringappend_15220, stringappend_15230)
+                         )) in
+                   (let stringappend_15240 = (string_drop stringappend_15210
+                                                stringappend_15230) in
+                   (case 
+                   (case  ((sep_matches_prefix stringappend_15240)) of
+                         Some (stringappend_15250,stringappend_15260) =>
+                   (stringappend_15250, stringappend_15260)
+                   ) of
+                       (_, stringappend_15260) =>
+                   (let stringappend_15270 = (string_drop stringappend_15240
+                                                stringappend_15260) in
+                   (let (rs2, stringappend_15290) =
+                        ((case  ((reg_name_matches_prefix stringappend_15270 :: (( 5 Word.word * ii)) option)) of
+                               Some (stringappend_15280,stringappend_15290) =>
+                         (stringappend_15280, stringappend_15290)
+                         )) in
+                   if(((string_drop stringappend_15270 stringappend_15290)) =
+                        ('''')) then (STORECON (aq,rl,rs2,rs1,size1,rd)) else
+                     undefined))
+                   ))))
+                   ))))
+                   )))))))) else
+                   if ((case  ((amo_mnemonic_matches_prefix
+                                  stringappend_10760)) of
+                             Some (stringappend_15310,stringappend_15320) =>
+                       (let stringappend_15330 = (string_drop
+                                                    stringappend_10760
+                                                    stringappend_15320) in
+                       if (((((string_startswith stringappend_15330 (''.'')))
+                               \<and>
+                               ((let stringappend_15340 = (string_drop
+                                                             stringappend_15330
+                                                             ((string_length
+                                                                 (''.'')))) in
+                                if ((case  ((size_mnemonic_matches_prefix
+                                               stringappend_15340)) of
+                                          Some (stringappend_15350,stringappend_15360) =>
+                                    (let stringappend_15370 =
+                                         (string_drop stringappend_15340
+                                            stringappend_15360) in
+                                    if ((case  ((maybe_aq_matches_prefix
+                                                   stringappend_15370)) of
+                                              Some (stringappend_15380,stringappend_15390) =>
+                                        (let stringappend_15400 =
+                                             (string_drop stringappend_15370
+                                                stringappend_15390) in
+                                        if ((case  ((maybe_rl_matches_prefix
+                                                       stringappend_15400)) of
+                                                  Some (stringappend_15410,stringappend_15420) =>
+                                            (let stringappend_15430 =
+                                                 (string_drop
+                                                    stringappend_15400
+                                                    stringappend_15420) in
+                                            if ((case  ((spc_matches_prefix
+                                                           stringappend_15430)) of
+                                                      Some (stringappend_15440,stringappend_15450) =>
+                                                (let stringappend_15460 =
+                                                     (string_drop
+                                                        stringappend_15430
+                                                        stringappend_15450) in
+                                                if ((case  ((reg_name_matches_prefix
+                                                               stringappend_15460
+                                                            :: (( 5 Word.word * ii)) option)) of
+                                                          Some (stringappend_15470,stringappend_15480) =>
+                                                    (let stringappend_15490 =
+                                                         (string_drop
+                                                            stringappend_15460
+                                                            stringappend_15480) in
+                                                    if ((case  ((sep_matches_prefix
+                                                                   stringappend_15490)) of
+                                                              Some (stringappend_15500,stringappend_15510) =>
+                                                        (let stringappend_15520 =
+                                                             (string_drop
+                                                                stringappend_15490
+                                                                stringappend_15510) in
+                                                        if ((case  ((
+                                                                    reg_name_matches_prefix
+                                                                    stringappend_15520
+                                                                    :: (( 5 Word.word * ii)) option)) of
+                                                                  Some (stringappend_15530,stringappend_15540) =>
+                                                            (let stringappend_15550 =
+                                                                 (string_drop
+                                                                    stringappend_15520
+                                                                    stringappend_15540) in
+                                                            if ((case  
+                                                                ((sep_matches_prefix
+                                                                    stringappend_15550)) of
+                                                                      Some
+                                                                (stringappend_15560,stringappend_15570) =>
+                                                                (let 
+                                                                stringappend_15580 =
+                                                                (string_drop
+                                                                   stringappend_15550
+                                                                   stringappend_15570) in
+                                                                if ((case  
+                                                                    (
+                                                                    (
+                                                                    reg_name_matches_prefix
+                                                                    stringappend_15580
+                                                                    :: (( 5 Word.word * ii)) option)) of
+                                                                      Some
+                                                                    (stringappend_15590,stringappend_15600) =>
+                                                                    if
+                                                                    (
+                                                                    (
+                                                                    (
+                                                                    string_drop
+                                                                    stringappend_15580
+                                                                    stringappend_15600))
+                                                                    = 
+                                                                    ('''')) then
+                                                                    True else
+                                                                    False
+                                                                    | None => 
+                                                                    False
+                                                                    )) then
+                                                                  True else
+                                                                  False)
+                                                                  | None => 
+                                                                False
+                                                                )) then 
+                                                            True else 
+                                                            False)
+                                                              | None => 
+                                                            False
+                                                            )) then True else
+                                                          False)
+                                                          | None => False
+                                                        )) then True else
+                                                      False)
+                                                      | None => False
+                                                    )) then True else 
+                                                False)
+                                                  | None => False
+                                                )) then True else False)
+                                              | None => False
+                                            )) then True else False)
+                                          | None => False
+                                        )) then True else False)
+                                      | None => False
+                                    )) then True else False))))) then 
+                       True else False)
+                         | None => False
+                       )) then
+                     (let (op1, stringappend_15320) =
+                          ((case  ((amo_mnemonic_matches_prefix
+                                      stringappend_10760)) of
+                                 Some (stringappend_15310,stringappend_15320) =>
+                           (stringappend_15310, stringappend_15320)
+                           )) in
+                     (let stringappend_15330 = (string_drop
+                                                  stringappend_10760
+                                                  stringappend_15320) in
+                     (let stringappend_15340 = (string_drop
+                                                  stringappend_15330
+                                                  ((string_length (''.'')))) in
+                     (let (width, stringappend_15360) =
+                          ((case  ((size_mnemonic_matches_prefix
+                                      stringappend_15340)) of
+                                 Some (stringappend_15350,stringappend_15360) =>
+                           (stringappend_15350, stringappend_15360)
+                           )) in
+                     (let stringappend_15370 = (string_drop
+                                                  stringappend_15340
+                                                  stringappend_15360) in
+                     (let (aq, stringappend_15390) =
+                          ((case  ((maybe_aq_matches_prefix
+                                      stringappend_15370)) of
+                                 Some (stringappend_15380,stringappend_15390) =>
+                           (stringappend_15380, stringappend_15390)
+                           )) in
+                     (let stringappend_15400 = (string_drop
+                                                  stringappend_15370
+                                                  stringappend_15390) in
+                     (let (rl, stringappend_15420) =
+                          ((case  ((maybe_rl_matches_prefix
+                                      stringappend_15400)) of
+                                 Some (stringappend_15410,stringappend_15420) =>
+                           (stringappend_15410, stringappend_15420)
+                           )) in
+                     (let stringappend_15430 = (string_drop
+                                                  stringappend_15400
+                                                  stringappend_15420) in
+                     (case 
+                     (case  ((spc_matches_prefix stringappend_15430)) of
+                           Some (stringappend_15440,stringappend_15450) =>
+                     (stringappend_15440, stringappend_15450)
+                     ) of
+                         (_, stringappend_15450) =>
+                     (let stringappend_15460 = (string_drop
+                                                  stringappend_15430
+                                                  stringappend_15450) in
+                     (let (rd, stringappend_15480) =
+                          ((case  ((reg_name_matches_prefix
+                                      stringappend_15460 :: (( 5 Word.word * ii)) option)) of
+                                 Some (stringappend_15470,stringappend_15480) =>
+                           (stringappend_15470, stringappend_15480)
+                           )) in
+                     (let stringappend_15490 = (string_drop
+                                                  stringappend_15460
+                                                  stringappend_15480) in
+                     (case 
+                     (case  ((sep_matches_prefix stringappend_15490)) of
+                           Some (stringappend_15500,stringappend_15510) =>
+                     (stringappend_15500, stringappend_15510)
+                     ) of
+                         (_, stringappend_15510) =>
+                     (let stringappend_15520 = (string_drop
+                                                  stringappend_15490
+                                                  stringappend_15510) in
+                     (let (rs1, stringappend_15540) =
+                          ((case  ((reg_name_matches_prefix
+                                      stringappend_15520 :: (( 5 Word.word * ii)) option)) of
+                                 Some (stringappend_15530,stringappend_15540) =>
+                           (stringappend_15530, stringappend_15540)
+                           )) in
+                     (let stringappend_15550 = (string_drop
+                                                  stringappend_15520
+                                                  stringappend_15540) in
+                     (case 
+                     (case  ((sep_matches_prefix stringappend_15550)) of
+                           Some (stringappend_15560,stringappend_15570) =>
+                     (stringappend_15560, stringappend_15570)
+                     ) of
+                         (_, stringappend_15570) =>
+                     (let stringappend_15580 = (string_drop
+                                                  stringappend_15550
+                                                  stringappend_15570) in
+                     (let (rs2, stringappend_15600) =
+                          ((case  ((reg_name_matches_prefix
+                                      stringappend_15580 :: (( 5 Word.word * ii)) option)) of
+                                 Some (stringappend_15590,stringappend_15600) =>
+                           (stringappend_15590, stringappend_15600)
+                           )) in
+                     if(((string_drop stringappend_15580 stringappend_15600))
+                          = ('''')) then (AMO (op1,aq,rl,rs2,rs1,width,rd))
+                     else undefined))
+                     ))))
+                     ))))
+                     )))))))))) else
+                     if ((case  ((csr_mnemonic_matches_prefix
+                                    stringappend_10760)) of
+                               Some (stringappend_15620,stringappend_15630) =>
+                         (let stringappend_15640 = (string_drop
+                                                      stringappend_10760
+                                                      stringappend_15630) in
+                         if (((((string_startswith stringappend_15640 (''i'')))
+                                 \<and>
+                                 ((let stringappend_15650 = (string_drop
+                                                               stringappend_15640
+                                                               ((string_length
+                                                                   (''i'')))) in
+                                  if ((case  ((spc_matches_prefix
+                                                 stringappend_15650)) of
+                                            Some (stringappend_15660,stringappend_15670) =>
+                                      (let stringappend_15680 =
+                                           (string_drop stringappend_15650
+                                              stringappend_15670) in
+                                      if ((case  ((reg_name_matches_prefix
+                                                     stringappend_15680
+                                                  :: (( 5 Word.word * ii)) option)) of
+                                                Some (stringappend_15690,stringappend_15700) =>
+                                          (let stringappend_15710 =
+                                               (string_drop
+                                                  stringappend_15680
+                                                  stringappend_15700) in
+                                          if ((case  ((sep_matches_prefix
+                                                         stringappend_15710)) of
+                                                    Some (stringappend_15720,stringappend_15730) =>
+                                              (let stringappend_15740 =
+                                                   (string_drop
+                                                      stringappend_15710
+                                                      stringappend_15730) in
+                                              if ((case  ((hex_bits_5_matches_prefix
+                                                             instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                             stringappend_15740
+                                                          :: (( 5 Word.word * ii)) option)) of
+                                                        Some (stringappend_15750,stringappend_15760) =>
+                                                  (let stringappend_15770 =
+                                                       (string_drop
+                                                          stringappend_15740
+                                                          stringappend_15760) in
+                                                  if ((case  ((sep_matches_prefix
+                                                                 stringappend_15770)) of
+                                                            Some (stringappend_15780,stringappend_15790) =>
+                                                      (let stringappend_15800 =
+                                                           (string_drop
+                                                              stringappend_15770
+                                                              stringappend_15790) in
+                                                      if ((case  ((csr_name_map_matches_prefix
+                                                                    stringappend_15800
+                                                                  :: (( 12 Word.word * ii)) option)) of
+                                                                Some (stringappend_15810,stringappend_15820) =>
+                                                          if(((string_drop
+                                                                 stringappend_15800
+                                                                 stringappend_15820))
+                                                               = ('''')) then
+                                                            True else 
+                                                          False
+                                                            | None => 
+                                                          False
+                                                          )) then True else
+                                                        False)
+                                                        | None => False
+                                                      )) then True else 
+                                                  False)
+                                                    | None => False
+                                                  )) then True else False)
+                                                | None => False
+                                              )) then True else False)
+                                            | None => False
+                                          )) then True else False)
+                                        | None => False
+                                      )) then True else False))))) then 
+                         True else False)
+                           | None => False
+                         )) then
+                       (let (op1, stringappend_15630) =
+                            ((case  ((csr_mnemonic_matches_prefix
+                                        stringappend_10760)) of
+                                   Some (stringappend_15620,stringappend_15630) =>
+                             (stringappend_15620, stringappend_15630)
+                             )) in
+                       (let stringappend_15640 = (string_drop
+                                                    stringappend_10760
+                                                    stringappend_15630) in
+                       (let stringappend_15650 = (string_drop
+                                                    stringappend_15640
+                                                    ((string_length (''i'')))) in
+                       (case 
+                       (case  ((spc_matches_prefix stringappend_15650)) of
+                             Some (stringappend_15660,stringappend_15670) =>
+                       (stringappend_15660, stringappend_15670)
+                       ) of
+                           (_, stringappend_15670) =>
+                       (let stringappend_15680 = (string_drop
+                                                    stringappend_15650
+                                                    stringappend_15670) in
+                       (let (rd, stringappend_15700) =
+                            ((case  ((reg_name_matches_prefix
+                                        stringappend_15680 :: (( 5 Word.word * ii)) option)) of
+                                   Some (stringappend_15690,stringappend_15700) =>
+                             (stringappend_15690, stringappend_15700)
+                             )) in
+                       (let stringappend_15710 = (string_drop
+                                                    stringappend_15680
+                                                    stringappend_15700) in
+                       (case 
+                       (case  ((sep_matches_prefix stringappend_15710)) of
+                             Some (stringappend_15720,stringappend_15730) =>
+                       (stringappend_15720, stringappend_15730)
+                       ) of
+                           (_, stringappend_15730) =>
+                       (let stringappend_15740 = (string_drop
+                                                    stringappend_15710
+                                                    stringappend_15730) in
+                       (let (rs1, stringappend_15760) =
+                            ((case  ((hex_bits_5_matches_prefix
+                                        instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                        stringappend_15740 :: (( 5 Word.word * ii)) option)) of
+                                   Some (stringappend_15750,stringappend_15760) =>
+                             (stringappend_15750, stringappend_15760)
+                             )) in
+                       (let stringappend_15770 = (string_drop
+                                                    stringappend_15740
+                                                    stringappend_15760) in
+                       (case 
+                       (case  ((sep_matches_prefix stringappend_15770)) of
+                             Some (stringappend_15780,stringappend_15790) =>
+                       (stringappend_15780, stringappend_15790)
+                       ) of
+                           (_, stringappend_15790) =>
+                       (let stringappend_15800 = (string_drop
+                                                    stringappend_15770
+                                                    stringappend_15790) in
+                       (let (csr, stringappend_15820) =
+                            ((case  ((csr_name_map_matches_prefix
+                                        stringappend_15800 :: (( 12 Word.word * ii)) option)) of
+                                   Some (stringappend_15810,stringappend_15820) =>
+                             (stringappend_15810, stringappend_15820)
+                             )) in
+                       if(((string_drop stringappend_15800 stringappend_15820))
+                            = ('''')) then (CSR (csr,rs1,rd,True,op1)) else
+                         undefined))
+                       ))))
+                       ))))
+                       )))) else
+                       if ((case  ((csr_mnemonic_matches_prefix
+                                      stringappend_10760)) of
+                                 Some (stringappend_15840,stringappend_15850) =>
+                           (let stringappend_15860 = (string_drop
+                                                        stringappend_10760
+                                                        stringappend_15850) in
+                           if ((case  ((spc_matches_prefix stringappend_15860)) of
+                                     Some (stringappend_15870,stringappend_15880) =>
+                               (let stringappend_15890 = (string_drop
+                                                            stringappend_15860
+                                                            stringappend_15880) in
+                               if ((case  ((reg_name_matches_prefix
+                                              stringappend_15890
+                                           :: (( 5 Word.word * ii)) option)) of
+                                         Some (stringappend_15900,stringappend_15910) =>
+                                   (let stringappend_15920 = (string_drop
+                                                                stringappend_15890
+                                                                stringappend_15910) in
+                                   if ((case  ((sep_matches_prefix
+                                                  stringappend_15920)) of
+                                             Some (stringappend_15930,stringappend_15940) =>
+                                       (let stringappend_15950 =
+                                            (string_drop stringappend_15920
+                                               stringappend_15940) in
+                                       if ((case  ((reg_name_matches_prefix
+                                                      stringappend_15950
+                                                   :: (( 5 Word.word * ii)) option)) of
+                                                 Some (stringappend_15960,stringappend_15970) =>
+                                           (let stringappend_15980 =
+                                                (string_drop
+                                                   stringappend_15950
+                                                   stringappend_15970) in
+                                           if ((case  ((sep_matches_prefix
+                                                          stringappend_15980)) of
+                                                     Some (stringappend_15990,stringappend_16000) =>
+                                               (let stringappend_16010 =
+                                                    (string_drop
+                                                       stringappend_15980
+                                                       stringappend_16000) in
+                                               if ((case  ((csr_name_map_matches_prefix
+                                                              stringappend_16010
+                                                           :: (( 12 Word.word * ii)) option)) of
+                                                         Some (stringappend_16020,stringappend_16030) =>
+                                                   if(((string_drop
+                                                          stringappend_16010
+                                                          stringappend_16030))
+                                                        = ('''')) then 
+                                                   True else False
+                                                     | None => False
+                                                   )) then True else 
+                                               False)
+                                                 | None => False
+                                               )) then True else False)
+                                             | None => False
+                                           )) then True else False)
+                                         | None => False
+                                       )) then True else False)
+                                     | None => False
+                                   )) then True else False)
+                                 | None => False
+                               )) then True else False)
+                             | None => False
+                           )) then
+                         (let (op1, stringappend_15850) =
+                              ((case  ((csr_mnemonic_matches_prefix
+                                          stringappend_10760)) of
+                                     Some (stringappend_15840,stringappend_15850) =>
+                               (stringappend_15840, stringappend_15850)
+                               )) in
+                         (let stringappend_15860 = (string_drop
+                                                      stringappend_10760
+                                                      stringappend_15850) in
+                         (case 
+                         (case  ((spc_matches_prefix stringappend_15860)) of
+                               Some (stringappend_15870,stringappend_15880) =>
+                         (stringappend_15870, stringappend_15880)
+                         ) of
+                             (_, stringappend_15880) =>
+                         (let stringappend_15890 = (string_drop
+                                                      stringappend_15860
+                                                      stringappend_15880) in
+                         (let (rd, stringappend_15910) =
+                              ((case  ((reg_name_matches_prefix
+                                          stringappend_15890 :: (( 5 Word.word * ii)) option)) of
+                                     Some (stringappend_15900,stringappend_15910) =>
+                               (stringappend_15900, stringappend_15910)
+                               )) in
+                         (let stringappend_15920 = (string_drop
+                                                      stringappend_15890
+                                                      stringappend_15910) in
+                         (case 
+                         (case  ((sep_matches_prefix stringappend_15920)) of
+                               Some (stringappend_15930,stringappend_15940) =>
+                         (stringappend_15930, stringappend_15940)
+                         ) of
+                             (_, stringappend_15940) =>
+                         (let stringappend_15950 = (string_drop
+                                                      stringappend_15920
+                                                      stringappend_15940) in
+                         (let (rs1, stringappend_15970) =
+                              ((case  ((reg_name_matches_prefix
+                                          stringappend_15950 :: (( 5 Word.word * ii)) option)) of
+                                     Some (stringappend_15960,stringappend_15970) =>
+                               (stringappend_15960, stringappend_15970)
+                               )) in
+                         (let stringappend_15980 = (string_drop
+                                                      stringappend_15950
+                                                      stringappend_15970) in
+                         (case 
+                         (case  ((sep_matches_prefix stringappend_15980)) of
+                               Some (stringappend_15990,stringappend_16000) =>
+                         (stringappend_15990, stringappend_16000)
+                         ) of
+                             (_, stringappend_16000) =>
+                         (let stringappend_16010 = (string_drop
+                                                      stringappend_15980
+                                                      stringappend_16000) in
+                         (let (csr, stringappend_16030) =
+                              ((case  ((csr_name_map_matches_prefix
+                                          stringappend_16010 :: (( 12 Word.word * ii)) option)) of
+                                     Some (stringappend_16020,stringappend_16030) =>
+                               (stringappend_16020, stringappend_16030)
+                               )) in
+                         if(((string_drop stringappend_16010
+                                stringappend_16030)) = ('''')) then
+                           (CSR (csr,rs1,rd,False,op1)) else undefined))
+                         ))))
+                         ))))
+                         ))) else
+                         (let stringappend_16050 = (string_drop
+                                                      stringappend_10760
+                                                      ((string_length
+                                                          (''illegal'')))) in
+                         (case 
+                         (case  ((spc_matches_prefix stringappend_16050)) of
+                               Some (stringappend_16060,stringappend_16070) =>
+                         (stringappend_16060, stringappend_16070)
+                         ) of
+                             (_, stringappend_16070) =>
+                         (let stringappend_16080 = (string_drop
+                                                      stringappend_16050
+                                                      stringappend_16070) in
+                         (let (s, stringappend_16100) =
+                              ((case  ((hex_bits_32_matches_prefix
+                                          instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                          stringappend_16080 :: (( 32 Word.word * ii)) option)) of
+                                     Some (stringappend_16090,stringappend_16100) =>
+                               (stringappend_16090, stringappend_16100)
+                               )) in
+                         if(((string_drop stringappend_16080
+                                stringappend_16100)) = ('''')) then
+                           (ILLEGAL s) else undefined))
+                         ))))))))))"
+
+
+(*val assembly_forwards_matches : ast -> bool*)
+
+fun assembly_forwards_matches  :: " ast \<Rightarrow> bool "  where 
+     " assembly_forwards_matches (UTYPE (imm,rd,op1)) = ( True )"
+|" assembly_forwards_matches (RISCV_JAL (imm,rd)) = ( True )"
+|" assembly_forwards_matches (RISCV_JALR (imm,rs1,rd)) = ( True )"
+|" assembly_forwards_matches (BTYPE (imm,rs2,rs1,op1)) = ( True )"
+|" assembly_forwards_matches (ITYPE (imm,rs1,rd,op1)) = ( True )"
+|" assembly_forwards_matches (SHIFTIOP (shamt,rs1,rd,op1)) = ( True )"
+|" assembly_forwards_matches (RTYPE (rs2,rs1,rd,op1)) = ( True )"
+|" assembly_forwards_matches (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)) = ( True )"
+|" assembly_forwards_matches (STORE (imm,rs1,rd,size1,aq,rl)) = ( True )"
+|" assembly_forwards_matches (ADDIW (imm,rs1,rd)) = ( True )"
+|" assembly_forwards_matches (SHIFTW (shamt,rs1,rd,op1)) = ( True )"
+|" assembly_forwards_matches (RTYPEW (rs2,rs1,rd,op1)) = ( True )"
+|" assembly_forwards_matches (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( True )"
+|" assembly_forwards_matches (DIV (rs2,rs1,rd,s)) = ( True )"
+|" assembly_forwards_matches (REM (rs2,rs1,rd,s)) = ( True )"
+|" assembly_forwards_matches (MULW (rs2,rs1,rd)) = ( True )"
+|" assembly_forwards_matches (DIVW (rs2,rs1,rd,s)) = ( True )"
+|" assembly_forwards_matches (REMW (rs2,rs1,rd,s)) = ( True )"
+|" assembly_forwards_matches (FENCE (pred,succ)) = ( True )"
+|" assembly_forwards_matches (FENCEI (_)) = ( True )"
+|" assembly_forwards_matches (ECALL (_)) = ( True )"
+|" assembly_forwards_matches (MRET (_)) = ( True )"
+|" assembly_forwards_matches (SRET (_)) = ( True )"
+|" assembly_forwards_matches (EBREAK (_)) = ( True )"
+|" assembly_forwards_matches (WFI (_)) = ( True )"
+|" assembly_forwards_matches (SFENCE_VMA (rs1,rs2)) = ( True )"
+|" assembly_forwards_matches (LOADRES (aq,rl,rs1,size1,rd)) = ( True )"
+|" assembly_forwards_matches (STORECON (aq,rl,rs2,rs1,size1,rd)) = ( True )"
+|" assembly_forwards_matches (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( True )"
+|" assembly_forwards_matches (CSR (csr,rs1,rd,True,op1)) = ( True )"
+|" assembly_forwards_matches (CSR (csr,rs1,rd,False,op1)) = ( True )"
+|" assembly_forwards_matches (ILLEGAL (s)) = ( True )"
+|" assembly_forwards_matches _ = ( False )"
+
+
+(*val assembly_backwards_matches : string -> bool*)
+
+definition assembly_backwards_matches  :: " string \<Rightarrow> bool "  where 
+     " assembly_backwards_matches arg0 = (
+   (let stringappend_5410 = arg0 in
+   if ((case  ((utype_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_5420,stringappend_5430) =>
+        (let stringappend_5440 = (string_drop stringappend_5410 stringappend_5430) in
+        if ((case  ((spc_matches_prefix stringappend_5440)) of
+            Some (stringappend_5450,stringappend_5460) =>
+             (let stringappend_5470 = (string_drop stringappend_5440 stringappend_5460) in
+             if ((case  ((reg_name_matches_prefix stringappend_5470  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_5480,stringappend_5490) =>
+                  (let stringappend_5500 = (string_drop stringappend_5470 stringappend_5490) in
+                  if ((case  ((sep_matches_prefix stringappend_5500)) of
+                      Some (stringappend_5510,stringappend_5520) =>
+                       (let stringappend_5530 = (string_drop stringappend_5500 stringappend_5520) in
+                       if ((case  ((hex_bits_20_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5530
+                                    ::  (( 20 Word.word * ii))option)) of
+                           Some (stringappend_5540,stringappend_5550) => 
+  if(((string_drop stringappend_5530 stringappend_5550)) = ('''')) then 
+  True else False
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_5430) =
+       ((case  ((utype_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_5420,stringappend_5430) => (stringappend_5420, stringappend_5430)
+       )) in
+     (let stringappend_5440 = (string_drop stringappend_5410 stringappend_5430) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_5440)) of
+        Some (stringappend_5450,stringappend_5460) => (stringappend_5450, stringappend_5460)
+  ) of
+      (_, stringappend_5460) =>
+  (let stringappend_5470 = (string_drop stringappend_5440 stringappend_5460) in
+  (let (rd, stringappend_5490) =
+       ((case  ((reg_name_matches_prefix stringappend_5470 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5480,stringappend_5490) => (stringappend_5480, stringappend_5490)
+        )) in
+  (let stringappend_5500 = (string_drop stringappend_5470 stringappend_5490) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5500)) of
+        Some (stringappend_5510,stringappend_5520) => (stringappend_5510, stringappend_5520)
+  ) of
+      (_, stringappend_5520) =>
+  (let stringappend_5530 = (string_drop stringappend_5500 stringappend_5520) in
+  (let (imm, stringappend_5550) =
+       ((case  ((hex_bits_20_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_5530 :: (( 20 Word.word * ii)) option)) of
+              Some (stringappend_5540,stringappend_5550) => (stringappend_5540, stringappend_5550)
+        )) in
+  if(((string_drop stringappend_5530 stringappend_5550)) = ('''')) then 
+  True else undefined))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_5410 (''jal''))) \<and> ((let stringappend_5570 = (string_drop stringappend_5410 ((string_length (''jal'')))) in
+               if ((case  ((spc_matches_prefix stringappend_5570)) of
+                   Some (stringappend_5580,stringappend_5590) =>
+                    (let stringappend_5600 = (string_drop stringappend_5570 stringappend_5590) in
+                    if ((case  ((reg_name_matches_prefix stringappend_5600
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_5610,stringappend_5620) =>
+                         (let stringappend_5630 = (string_drop stringappend_5600 stringappend_5620) in
+                         if ((case  ((sep_matches_prefix stringappend_5630)) of
+                             Some (stringappend_5640,stringappend_5650) =>
+                              (let stringappend_5660 =
+                                (string_drop stringappend_5630 stringappend_5650) in
+                              if ((case  ((hex_bits_21_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5660
+                                           ::  (( 21 Word.word * ii))option)) of
+                                  Some (stringappend_5670,stringappend_5680) => 
+  if(((string_drop stringappend_5660 stringappend_5680)) = ('''')) then 
+  True else False
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_5570 = (string_drop stringappend_5410 ((string_length (''jal'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_5570)) of
+        Some (stringappend_5580,stringappend_5590) => (stringappend_5580, stringappend_5590)
+  ) of
+      (_, stringappend_5590) =>
+  (let stringappend_5600 = (string_drop stringappend_5570 stringappend_5590) in
+  (let (rd, stringappend_5620) =
+       ((case  ((reg_name_matches_prefix stringappend_5600 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5610,stringappend_5620) => (stringappend_5610, stringappend_5620)
+        )) in
+  (let stringappend_5630 = (string_drop stringappend_5600 stringappend_5620) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5630)) of
+        Some (stringappend_5640,stringappend_5650) => (stringappend_5640, stringappend_5650)
+  ) of
+      (_, stringappend_5650) =>
+  (let stringappend_5660 = (string_drop stringappend_5630 stringappend_5650) in
+  (let (imm, stringappend_5680) =
+       ((case  ((hex_bits_21_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_5660 :: (( 21 Word.word * ii)) option)) of
+              Some (stringappend_5670,stringappend_5680) => (stringappend_5670, stringappend_5680)
+        )) in
+  if(((string_drop stringappend_5660 stringappend_5680)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_5410 (''jalr''))) \<and> ((let stringappend_5700 = (string_drop stringappend_5410 ((string_length (''jalr'')))) in
+               if ((case  ((spc_matches_prefix stringappend_5700)) of
+                   Some (stringappend_5710,stringappend_5720) =>
+                    (let stringappend_5730 = (string_drop stringappend_5700 stringappend_5720) in
+                    if ((case  ((reg_name_matches_prefix stringappend_5730
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_5740,stringappend_5750) =>
+                         (let stringappend_5760 = (string_drop stringappend_5730 stringappend_5750) in
+                         if ((case  ((sep_matches_prefix stringappend_5760)) of
+                             Some (stringappend_5770,stringappend_5780) =>
+                              (let stringappend_5790 =
+                                (string_drop stringappend_5760 stringappend_5780) in
+                              if ((case  ((reg_name_matches_prefix stringappend_5790
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_5800,stringappend_5810) =>
+                                   (let stringappend_5820 =
+                                     (string_drop stringappend_5790 stringappend_5810) in
+                                   if ((case  ((sep_matches_prefix stringappend_5820)) of
+                                       Some (stringappend_5830,stringappend_5840) =>
+                                        (let stringappend_5850 =
+                                          (string_drop stringappend_5820 stringappend_5840) in
+                                        if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5850
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_5860,stringappend_5870) => 
+  if(((string_drop stringappend_5850 stringappend_5870)) = ('''')) then 
+  True else False
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_5700 = (string_drop stringappend_5410 ((string_length (''jalr'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_5700)) of
+        Some (stringappend_5710,stringappend_5720) => (stringappend_5710, stringappend_5720)
+  ) of
+      (_, stringappend_5720) =>
+  (let stringappend_5730 = (string_drop stringappend_5700 stringappend_5720) in
+  (let (rd, stringappend_5750) =
+       ((case  ((reg_name_matches_prefix stringappend_5730 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5740,stringappend_5750) => (stringappend_5740, stringappend_5750)
+        )) in
+  (let stringappend_5760 = (string_drop stringappend_5730 stringappend_5750) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5760)) of
+        Some (stringappend_5770,stringappend_5780) => (stringappend_5770, stringappend_5780)
+  ) of
+      (_, stringappend_5780) =>
+  (let stringappend_5790 = (string_drop stringappend_5760 stringappend_5780) in
+  (let (rs1, stringappend_5810) =
+       ((case  ((reg_name_matches_prefix stringappend_5790 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5800,stringappend_5810) => (stringappend_5800, stringappend_5810)
+        )) in
+  (let stringappend_5820 = (string_drop stringappend_5790 stringappend_5810) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5820)) of
+        Some (stringappend_5830,stringappend_5840) => (stringappend_5830, stringappend_5840)
+  ) of
+      (_, stringappend_5840) =>
+  (let stringappend_5850 = (string_drop stringappend_5820 stringappend_5840) in
+  (let (imm, stringappend_5870) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_5850 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_5860,stringappend_5870) => (stringappend_5860, stringappend_5870)
+        )) in
+  if(((string_drop stringappend_5850 stringappend_5870)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))
+   else if ((case  ((btype_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_5890,stringappend_5900) =>
+        (let stringappend_5910 = (string_drop stringappend_5410 stringappend_5900) in
+        if ((case  ((spc_matches_prefix stringappend_5910)) of
+            Some (stringappend_5920,stringappend_5930) =>
+             (let stringappend_5940 = (string_drop stringappend_5910 stringappend_5930) in
+             if ((case  ((reg_name_matches_prefix stringappend_5940  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_5950,stringappend_5960) =>
+                  (let stringappend_5970 = (string_drop stringappend_5940 stringappend_5960) in
+                  if ((case  ((sep_matches_prefix stringappend_5970)) of
+                      Some (stringappend_5980,stringappend_5990) =>
+                       (let stringappend_6000 = (string_drop stringappend_5970 stringappend_5990) in
+                       if ((case  ((reg_name_matches_prefix stringappend_6000
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_6010,stringappend_6020) =>
+                            (let stringappend_6030 =
+                              (string_drop stringappend_6000 stringappend_6020) in
+                            if ((case  ((sep_matches_prefix stringappend_6030)) of
+                                Some (stringappend_6040,stringappend_6050) =>
+                                 (let stringappend_6060 =
+                                   (string_drop stringappend_6030 stringappend_6050) in
+                                 if ((case  ((hex_bits_13_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_6060
+                                              ::  (( 13 Word.word * ii))option)) of
+                                     Some (stringappend_6070,stringappend_6080) => 
+  if(((string_drop stringappend_6060 stringappend_6080)) = ('''')) then 
+  True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_5900) =
+       ((case  ((btype_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_5890,stringappend_5900) => (stringappend_5890, stringappend_5900)
+       )) in
+     (let stringappend_5910 = (string_drop stringappend_5410 stringappend_5900) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_5910)) of
+        Some (stringappend_5920,stringappend_5930) => (stringappend_5920, stringappend_5930)
+  ) of
+      (_, stringappend_5930) =>
+  (let stringappend_5940 = (string_drop stringappend_5910 stringappend_5930) in
+  (let (rs1, stringappend_5960) =
+       ((case  ((reg_name_matches_prefix stringappend_5940 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5950,stringappend_5960) => (stringappend_5950, stringappend_5960)
+        )) in
+  (let stringappend_5970 = (string_drop stringappend_5940 stringappend_5960) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5970)) of
+        Some (stringappend_5980,stringappend_5990) => (stringappend_5980, stringappend_5990)
+  ) of
+      (_, stringappend_5990) =>
+  (let stringappend_6000 = (string_drop stringappend_5970 stringappend_5990) in
+  (let (rs2, stringappend_6020) =
+       ((case  ((reg_name_matches_prefix stringappend_6000 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6010,stringappend_6020) => (stringappend_6010, stringappend_6020)
+        )) in
+  (let stringappend_6030 = (string_drop stringappend_6000 stringappend_6020) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6030)) of
+        Some (stringappend_6040,stringappend_6050) => (stringappend_6040, stringappend_6050)
+  ) of
+      (_, stringappend_6050) =>
+  (let stringappend_6060 = (string_drop stringappend_6030 stringappend_6050) in
+  (let (imm, stringappend_6080) =
+       ((case  ((hex_bits_13_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_6060 :: (( 13 Word.word * ii)) option)) of
+              Some (stringappend_6070,stringappend_6080) => (stringappend_6070, stringappend_6080)
+        )) in
+  if(((string_drop stringappend_6060 stringappend_6080)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((itype_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_6100,stringappend_6110) =>
+        (let stringappend_6120 = (string_drop stringappend_5410 stringappend_6110) in
+        if ((case  ((spc_matches_prefix stringappend_6120)) of
+            Some (stringappend_6130,stringappend_6140) =>
+             (let stringappend_6150 = (string_drop stringappend_6120 stringappend_6140) in
+             if ((case  ((reg_name_matches_prefix stringappend_6150  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_6160,stringappend_6170) =>
+                  (let stringappend_6180 = (string_drop stringappend_6150 stringappend_6170) in
+                  if ((case  ((sep_matches_prefix stringappend_6180)) of
+                      Some (stringappend_6190,stringappend_6200) =>
+                       (let stringappend_6210 = (string_drop stringappend_6180 stringappend_6200) in
+                       if ((case  ((reg_name_matches_prefix stringappend_6210
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_6220,stringappend_6230) =>
+                            (let stringappend_6240 =
+                              (string_drop stringappend_6210 stringappend_6230) in
+                            if ((case  ((sep_matches_prefix stringappend_6240)) of
+                                Some (stringappend_6250,stringappend_6260) =>
+                                 (let stringappend_6270 =
+                                   (string_drop stringappend_6240 stringappend_6260) in
+                                 if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_6270
+                                              ::  (( 12 Word.word * ii))option)) of
+                                     Some (stringappend_6280,stringappend_6290) => 
+  if(((string_drop stringappend_6270 stringappend_6290)) = ('''')) then 
+  True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_6110) =
+       ((case  ((itype_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_6100,stringappend_6110) => (stringappend_6100, stringappend_6110)
+       )) in
+     (let stringappend_6120 = (string_drop stringappend_5410 stringappend_6110) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_6120)) of
+        Some (stringappend_6130,stringappend_6140) => (stringappend_6130, stringappend_6140)
+  ) of
+      (_, stringappend_6140) =>
+  (let stringappend_6150 = (string_drop stringappend_6120 stringappend_6140) in
+  (let (rd, stringappend_6170) =
+       ((case  ((reg_name_matches_prefix stringappend_6150 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6160,stringappend_6170) => (stringappend_6160, stringappend_6170)
+        )) in
+  (let stringappend_6180 = (string_drop stringappend_6150 stringappend_6170) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6180)) of
+        Some (stringappend_6190,stringappend_6200) => (stringappend_6190, stringappend_6200)
+  ) of
+      (_, stringappend_6200) =>
+  (let stringappend_6210 = (string_drop stringappend_6180 stringappend_6200) in
+  (let (rs1, stringappend_6230) =
+       ((case  ((reg_name_matches_prefix stringappend_6210 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6220,stringappend_6230) => (stringappend_6220, stringappend_6230)
+        )) in
+  (let stringappend_6240 = (string_drop stringappend_6210 stringappend_6230) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6240)) of
+        Some (stringappend_6250,stringappend_6260) => (stringappend_6250, stringappend_6260)
+  ) of
+      (_, stringappend_6260) =>
+  (let stringappend_6270 = (string_drop stringappend_6240 stringappend_6260) in
+  (let (imm, stringappend_6290) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_6270 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_6280,stringappend_6290) => (stringappend_6280, stringappend_6290)
+        )) in
+  if(((string_drop stringappend_6270 stringappend_6290)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((shiftiop_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_6310,stringappend_6320) =>
+        (let stringappend_6330 = (string_drop stringappend_5410 stringappend_6320) in
+        if ((case  ((spc_matches_prefix stringappend_6330)) of
+            Some (stringappend_6340,stringappend_6350) =>
+             (let stringappend_6360 = (string_drop stringappend_6330 stringappend_6350) in
+             if ((case  ((reg_name_matches_prefix stringappend_6360  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_6370,stringappend_6380) =>
+                  (let stringappend_6390 = (string_drop stringappend_6360 stringappend_6380) in
+                  if ((case  ((sep_matches_prefix stringappend_6390)) of
+                      Some (stringappend_6400,stringappend_6410) =>
+                       (let stringappend_6420 = (string_drop stringappend_6390 stringappend_6410) in
+                       if ((case  ((reg_name_matches_prefix stringappend_6420
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_6430,stringappend_6440) =>
+                            (let stringappend_6450 =
+                              (string_drop stringappend_6420 stringappend_6440) in
+                            if ((case  ((hex_bits_6_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_6450
+                                         ::  (( 6 Word.word * ii))option)) of
+                                Some (stringappend_6460,stringappend_6470) => 
+  if(((string_drop stringappend_6450 stringappend_6470)) = ('''')) then 
+  True else False
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_6320) =
+       ((case  ((shiftiop_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_6310,stringappend_6320) => (stringappend_6310, stringappend_6320)
+       )) in
+     (let stringappend_6330 = (string_drop stringappend_5410 stringappend_6320) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_6330)) of
+        Some (stringappend_6340,stringappend_6350) => (stringappend_6340, stringappend_6350)
+  ) of
+      (_, stringappend_6350) =>
+  (let stringappend_6360 = (string_drop stringappend_6330 stringappend_6350) in
+  (let (rd, stringappend_6380) =
+       ((case  ((reg_name_matches_prefix stringappend_6360 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6370,stringappend_6380) => (stringappend_6370, stringappend_6380)
+        )) in
+  (let stringappend_6390 = (string_drop stringappend_6360 stringappend_6380) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6390)) of
+        Some (stringappend_6400,stringappend_6410) => (stringappend_6400, stringappend_6410)
+  ) of
+      (_, stringappend_6410) =>
+  (let stringappend_6420 = (string_drop stringappend_6390 stringappend_6410) in
+  (let (rs1, stringappend_6440) =
+       ((case  ((reg_name_matches_prefix stringappend_6420 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6430,stringappend_6440) => (stringappend_6430, stringappend_6440)
+        )) in
+  (let stringappend_6450 = (string_drop stringappend_6420 stringappend_6440) in
+  (let (shamt, stringappend_6470) =
+       ((case  ((hex_bits_6_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_6450 :: (( 6 Word.word * ii)) option)) of
+              Some (stringappend_6460,stringappend_6470) => (stringappend_6460, stringappend_6470)
+        )) in
+  if(((string_drop stringappend_6450 stringappend_6470)) = ('''')) then 
+  True else undefined))))
+  ))))
+  )))
+   else if ((case  ((rtype_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_6490,stringappend_6500) =>
+        (let stringappend_6510 = (string_drop stringappend_5410 stringappend_6500) in
+        if ((case  ((spc_matches_prefix stringappend_6510)) of
+            Some (stringappend_6520,stringappend_6530) =>
+             (let stringappend_6540 = (string_drop stringappend_6510 stringappend_6530) in
+             if ((case  ((reg_name_matches_prefix stringappend_6540  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_6550,stringappend_6560) =>
+                  (let stringappend_6570 = (string_drop stringappend_6540 stringappend_6560) in
+                  if ((case  ((sep_matches_prefix stringappend_6570)) of
+                      Some (stringappend_6580,stringappend_6590) =>
+                       (let stringappend_6600 = (string_drop stringappend_6570 stringappend_6590) in
+                       if ((case  ((reg_name_matches_prefix stringappend_6600
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_6610,stringappend_6620) =>
+                            (let stringappend_6630 =
+                              (string_drop stringappend_6600 stringappend_6620) in
+                            if ((case  ((sep_matches_prefix stringappend_6630)) of
+                                Some (stringappend_6640,stringappend_6650) =>
+                                 (let stringappend_6660 =
+                                   (string_drop stringappend_6630 stringappend_6650) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_6660
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_6670,stringappend_6680) => 
+  if(((string_drop stringappend_6660 stringappend_6680)) = ('''')) then 
+  True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_6500) =
+       ((case  ((rtype_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_6490,stringappend_6500) => (stringappend_6490, stringappend_6500)
+       )) in
+     (let stringappend_6510 = (string_drop stringappend_5410 stringappend_6500) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_6510)) of
+        Some (stringappend_6520,stringappend_6530) => (stringappend_6520, stringappend_6530)
+  ) of
+      (_, stringappend_6530) =>
+  (let stringappend_6540 = (string_drop stringappend_6510 stringappend_6530) in
+  (let (rd, stringappend_6560) =
+       ((case  ((reg_name_matches_prefix stringappend_6540 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6550,stringappend_6560) => (stringappend_6550, stringappend_6560)
+        )) in
+  (let stringappend_6570 = (string_drop stringappend_6540 stringappend_6560) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6570)) of
+        Some (stringappend_6580,stringappend_6590) => (stringappend_6580, stringappend_6590)
+  ) of
+      (_, stringappend_6590) =>
+  (let stringappend_6600 = (string_drop stringappend_6570 stringappend_6590) in
+  (let (rs1, stringappend_6620) =
+       ((case  ((reg_name_matches_prefix stringappend_6600 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6610,stringappend_6620) => (stringappend_6610, stringappend_6620)
+        )) in
+  (let stringappend_6630 = (string_drop stringappend_6600 stringappend_6620) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6630)) of
+        Some (stringappend_6640,stringappend_6650) => (stringappend_6640, stringappend_6650)
+  ) of
+      (_, stringappend_6650) =>
+  (let stringappend_6660 = (string_drop stringappend_6630 stringappend_6650) in
+  (let (rs2, stringappend_6680) =
+       ((case  ((reg_name_matches_prefix stringappend_6660 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6670,stringappend_6680) => (stringappend_6670, stringappend_6680)
+        )) in
+  if(((string_drop stringappend_6660 stringappend_6680)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_5410 (''l''))) \<and> ((let stringappend_6700 = (string_drop stringappend_5410 ((string_length (''l'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_6700)) of
+                   Some (stringappend_6710,stringappend_6720) =>
+                    (let stringappend_6730 = (string_drop stringappend_6700 stringappend_6720) in
+                    if ((case  ((maybe_u_matches_prefix stringappend_6730)) of
+                        Some (stringappend_6740,stringappend_6750) =>
+                         (let stringappend_6760 = (string_drop stringappend_6730 stringappend_6750) in
+                         if ((case  ((maybe_aq_matches_prefix stringappend_6760)) of
+                             Some (stringappend_6770,stringappend_6780) =>
+                              (let stringappend_6790 =
+                                (string_drop stringappend_6760 stringappend_6780) in
+                              if ((case  ((maybe_rl_matches_prefix stringappend_6790)) of
+                                  Some (stringappend_6800,stringappend_6810) =>
+                                   (let stringappend_6820 =
+                                     (string_drop stringappend_6790 stringappend_6810) in
+                                   if ((case  ((spc_matches_prefix stringappend_6820)) of
+                                       Some (stringappend_6830,stringappend_6840) =>
+                                        (let stringappend_6850 =
+                                          (string_drop stringappend_6820 stringappend_6840) in
+                                        if ((case  ((reg_name_matches_prefix stringappend_6850
+                                                     ::  (( 5 Word.word * ii))option)) of
+                                            Some (stringappend_6860,stringappend_6870) =>
+                                             (let stringappend_6880 =
+                                               (string_drop stringappend_6850 stringappend_6870) in
+                                             if ((case  ((sep_matches_prefix stringappend_6880)) of
+                                                 Some (stringappend_6890,stringappend_6900) =>
+                                                  (let stringappend_6910 =
+                                                    (string_drop stringappend_6880
+                                                      stringappend_6900) in
+                                                  if ((case  ((reg_name_matches_prefix
+                                                                stringappend_6910
+                                                               ::  (( 5 Word.word * ii))option)) of
+                                                      Some (stringappend_6920,stringappend_6930) =>
+                                                       (let stringappend_6940 =
+                                                         (string_drop stringappend_6910
+                                                           stringappend_6930) in
+                                                       if ((case  ((sep_matches_prefix
+                                                                     stringappend_6940)) of
+                                                           Some
+                                                           (stringappend_6950,stringappend_6960) =>
+                                                            (let stringappend_6970 =
+                                                              (string_drop stringappend_6940
+                                                                stringappend_6960) in
+                                                            if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                          stringappend_6970
+                                                                         ::  (( 12 Word.word * ii))option)) of
+                                                                Some
+                                                                (stringappend_6980,stringappend_6990) => 
+  if(((string_drop stringappend_6970 stringappend_6990)) = ('''')) then 
+  True else False
+                                                              | None => False
+                                                              )) then
+                                                              True
+                                                            else False)
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_6700 = (string_drop stringappend_5410 ((string_length (''l'')))) in
+     (let (size1, stringappend_6720) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_6700)) of
+         Some (stringappend_6710,stringappend_6720) => (stringappend_6710, stringappend_6720)
+       )) in
+     (let stringappend_6730 = (string_drop stringappend_6700 stringappend_6720) in
+     (let (is_unsigned, stringappend_6750) =
+       ((case  ((maybe_u_matches_prefix stringappend_6730)) of
+         Some (stringappend_6740,stringappend_6750) => (stringappend_6740, stringappend_6750)
+       )) in
+     (let stringappend_6760 = (string_drop stringappend_6730 stringappend_6750) in
+     (let (aq, stringappend_6780) =
+       ((case  ((maybe_aq_matches_prefix stringappend_6760)) of
+         Some (stringappend_6770,stringappend_6780) => (stringappend_6770, stringappend_6780)
+       )) in
+     (let stringappend_6790 = (string_drop stringappend_6760 stringappend_6780) in
+     (let (rl, stringappend_6810) =
+       ((case  ((maybe_rl_matches_prefix stringappend_6790)) of
+         Some (stringappend_6800,stringappend_6810) => (stringappend_6800, stringappend_6810)
+       )) in
+     (let stringappend_6820 = (string_drop stringappend_6790 stringappend_6810) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_6820)) of
+        Some (stringappend_6830,stringappend_6840) => (stringappend_6830, stringappend_6840)
+  ) of
+      (_, stringappend_6840) =>
+  (let stringappend_6850 = (string_drop stringappend_6820 stringappend_6840) in
+  (let (rd, stringappend_6870) =
+       ((case  ((reg_name_matches_prefix stringappend_6850 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6860,stringappend_6870) => (stringappend_6860, stringappend_6870)
+        )) in
+  (let stringappend_6880 = (string_drop stringappend_6850 stringappend_6870) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6880)) of
+        Some (stringappend_6890,stringappend_6900) => (stringappend_6890, stringappend_6900)
+  ) of
+      (_, stringappend_6900) =>
+  (let stringappend_6910 = (string_drop stringappend_6880 stringappend_6900) in
+  (let (rs1, stringappend_6930) =
+       ((case  ((reg_name_matches_prefix stringappend_6910 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_6920,stringappend_6930) => (stringappend_6920, stringappend_6930)
+        )) in
+  (let stringappend_6940 = (string_drop stringappend_6910 stringappend_6930) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_6940)) of
+        Some (stringappend_6950,stringappend_6960) => (stringappend_6950, stringappend_6960)
+  ) of
+      (_, stringappend_6960) =>
+  (let stringappend_6970 = (string_drop stringappend_6940 stringappend_6960) in
+  (let (imm, stringappend_6990) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_6970 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_6980,stringappend_6990) => (stringappend_6980, stringappend_6990)
+        )) in
+  if(((string_drop stringappend_6970 stringappend_6990)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))))))))))
+   else if (((((string_startswith stringappend_5410 (''s''))) \<and> ((let stringappend_7010 = (string_drop stringappend_5410 ((string_length (''s'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_7010)) of
+                   Some (stringappend_7020,stringappend_7030) =>
+                    (let stringappend_7040 = (string_drop stringappend_7010 stringappend_7030) in
+                    if ((case  ((maybe_aq_matches_prefix stringappend_7040)) of
+                        Some (stringappend_7050,stringappend_7060) =>
+                         (let stringappend_7070 = (string_drop stringappend_7040 stringappend_7060) in
+                         if ((case  ((maybe_rl_matches_prefix stringappend_7070)) of
+                             Some (stringappend_7080,stringappend_7090) =>
+                              (let stringappend_7100 =
+                                (string_drop stringappend_7070 stringappend_7090) in
+                              if ((case  ((spc_matches_prefix stringappend_7100)) of
+                                  Some (stringappend_7110,stringappend_7120) =>
+                                   (let stringappend_7130 =
+                                     (string_drop stringappend_7100 stringappend_7120) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_7130
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_7140,stringappend_7150) =>
+                                        (let stringappend_7160 =
+                                          (string_drop stringappend_7130 stringappend_7150) in
+                                        if ((case  ((sep_matches_prefix stringappend_7160)) of
+                                            Some (stringappend_7170,stringappend_7180) =>
+                                             (let stringappend_7190 =
+                                               (string_drop stringappend_7160 stringappend_7180) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_7190
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_7200,stringappend_7210) =>
+                                                  (let stringappend_7220 =
+                                                    (string_drop stringappend_7190
+                                                      stringappend_7210) in
+                                                  if ((case  ((sep_matches_prefix stringappend_7220)) of
+                                                      Some (stringappend_7230,stringappend_7240) =>
+                                                       (let stringappend_7250 =
+                                                         (string_drop stringappend_7220
+                                                           stringappend_7240) in
+                                                       if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                     stringappend_7250
+                                                                    ::  (( 12 Word.word * ii))option)) of
+                                                           Some
+                                                           (stringappend_7260,stringappend_7270) => 
+  if(((string_drop stringappend_7250 stringappend_7270)) = ('''')) then 
+  True else False
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_7010 = (string_drop stringappend_5410 ((string_length (''s'')))) in
+     (let (size1, stringappend_7030) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_7010)) of
+         Some (stringappend_7020,stringappend_7030) => (stringappend_7020, stringappend_7030)
+       )) in
+     (let stringappend_7040 = (string_drop stringappend_7010 stringappend_7030) in
+     (let (aq, stringappend_7060) =
+       ((case  ((maybe_aq_matches_prefix stringappend_7040)) of
+         Some (stringappend_7050,stringappend_7060) => (stringappend_7050, stringappend_7060)
+       )) in
+     (let stringappend_7070 = (string_drop stringappend_7040 stringappend_7060) in
+     (let (rl, stringappend_7090) =
+       ((case  ((maybe_rl_matches_prefix stringappend_7070)) of
+         Some (stringappend_7080,stringappend_7090) => (stringappend_7080, stringappend_7090)
+       )) in
+     (let stringappend_7100 = (string_drop stringappend_7070 stringappend_7090) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_7100)) of
+        Some (stringappend_7110,stringappend_7120) => (stringappend_7110, stringappend_7120)
+  ) of
+      (_, stringappend_7120) =>
+  (let stringappend_7130 = (string_drop stringappend_7100 stringappend_7120) in
+  (let (rd, stringappend_7150) =
+       ((case  ((reg_name_matches_prefix stringappend_7130 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7140,stringappend_7150) => (stringappend_7140, stringappend_7150)
+        )) in
+  (let stringappend_7160 = (string_drop stringappend_7130 stringappend_7150) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7160)) of
+        Some (stringappend_7170,stringappend_7180) => (stringappend_7170, stringappend_7180)
+  ) of
+      (_, stringappend_7180) =>
+  (let stringappend_7190 = (string_drop stringappend_7160 stringappend_7180) in
+  (let (rs1, stringappend_7210) =
+       ((case  ((reg_name_matches_prefix stringappend_7190 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7200,stringappend_7210) => (stringappend_7200, stringappend_7210)
+        )) in
+  (let stringappend_7220 = (string_drop stringappend_7190 stringappend_7210) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7220)) of
+        Some (stringappend_7230,stringappend_7240) => (stringappend_7230, stringappend_7240)
+  ) of
+      (_, stringappend_7240) =>
+  (let stringappend_7250 = (string_drop stringappend_7220 stringappend_7240) in
+  (let (imm, stringappend_7270) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_7250 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_7260,stringappend_7270) => (stringappend_7260, stringappend_7270)
+        )) in
+  if(((string_drop stringappend_7250 stringappend_7270)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))))))))
+   else if (((((string_startswith stringappend_5410 (''addiw''))) \<and> ((let stringappend_7290 = (string_drop stringappend_5410 ((string_length (''addiw'')))) in
+               if ((case  ((spc_matches_prefix stringappend_7290)) of
+                   Some (stringappend_7300,stringappend_7310) =>
+                    (let stringappend_7320 = (string_drop stringappend_7290 stringappend_7310) in
+                    if ((case  ((reg_name_matches_prefix stringappend_7320
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_7330,stringappend_7340) =>
+                         (let stringappend_7350 = (string_drop stringappend_7320 stringappend_7340) in
+                         if ((case  ((sep_matches_prefix stringappend_7350)) of
+                             Some (stringappend_7360,stringappend_7370) =>
+                              (let stringappend_7380 =
+                                (string_drop stringappend_7350 stringappend_7370) in
+                              if ((case  ((reg_name_matches_prefix stringappend_7380
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_7390,stringappend_7400) =>
+                                   (let stringappend_7410 =
+                                     (string_drop stringappend_7380 stringappend_7400) in
+                                   if ((case  ((sep_matches_prefix stringappend_7410)) of
+                                       Some (stringappend_7420,stringappend_7430) =>
+                                        (let stringappend_7440 =
+                                          (string_drop stringappend_7410 stringappend_7430) in
+                                        if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_7440
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_7450,stringappend_7460) => 
+  if(((string_drop stringappend_7440 stringappend_7460)) = ('''')) then 
+  True else False
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_7290 = (string_drop stringappend_5410 ((string_length (''addiw'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_7290)) of
+        Some (stringappend_7300,stringappend_7310) => (stringappend_7300, stringappend_7310)
+  ) of
+      (_, stringappend_7310) =>
+  (let stringappend_7320 = (string_drop stringappend_7290 stringappend_7310) in
+  (let (rd, stringappend_7340) =
+       ((case  ((reg_name_matches_prefix stringappend_7320 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7330,stringappend_7340) => (stringappend_7330, stringappend_7340)
+        )) in
+  (let stringappend_7350 = (string_drop stringappend_7320 stringappend_7340) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7350)) of
+        Some (stringappend_7360,stringappend_7370) => (stringappend_7360, stringappend_7370)
+  ) of
+      (_, stringappend_7370) =>
+  (let stringappend_7380 = (string_drop stringappend_7350 stringappend_7370) in
+  (let (rs1, stringappend_7400) =
+       ((case  ((reg_name_matches_prefix stringappend_7380 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7390,stringappend_7400) => (stringappend_7390, stringappend_7400)
+        )) in
+  (let stringappend_7410 = (string_drop stringappend_7380 stringappend_7400) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7410)) of
+        Some (stringappend_7420,stringappend_7430) => (stringappend_7420, stringappend_7430)
+  ) of
+      (_, stringappend_7430) =>
+  (let stringappend_7440 = (string_drop stringappend_7410 stringappend_7430) in
+  (let (imm, stringappend_7460) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_7440 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_7450,stringappend_7460) => (stringappend_7450, stringappend_7460)
+        )) in
+  if(((string_drop stringappend_7440 stringappend_7460)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))
+   else if ((case  ((shiftw_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_7480,stringappend_7490) =>
+        (let stringappend_7500 = (string_drop stringappend_5410 stringappend_7490) in
+        if ((case  ((spc_matches_prefix stringappend_7500)) of
+            Some (stringappend_7510,stringappend_7520) =>
+             (let stringappend_7530 = (string_drop stringappend_7500 stringappend_7520) in
+             if ((case  ((reg_name_matches_prefix stringappend_7530  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_7540,stringappend_7550) =>
+                  (let stringappend_7560 = (string_drop stringappend_7530 stringappend_7550) in
+                  if ((case  ((sep_matches_prefix stringappend_7560)) of
+                      Some (stringappend_7570,stringappend_7580) =>
+                       (let stringappend_7590 = (string_drop stringappend_7560 stringappend_7580) in
+                       if ((case  ((reg_name_matches_prefix stringappend_7590
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_7600,stringappend_7610) =>
+                            (let stringappend_7620 =
+                              (string_drop stringappend_7590 stringappend_7610) in
+                            if ((case  ((sep_matches_prefix stringappend_7620)) of
+                                Some (stringappend_7630,stringappend_7640) =>
+                                 (let stringappend_7650 =
+                                   (string_drop stringappend_7620 stringappend_7640) in
+                                 if ((case  ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_7650
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_7660,stringappend_7670) => 
+  if(((string_drop stringappend_7650 stringappend_7670)) = ('''')) then 
+  True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_7490) =
+       ((case  ((shiftw_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_7480,stringappend_7490) => (stringappend_7480, stringappend_7490)
+       )) in
+     (let stringappend_7500 = (string_drop stringappend_5410 stringappend_7490) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_7500)) of
+        Some (stringappend_7510,stringappend_7520) => (stringappend_7510, stringappend_7520)
+  ) of
+      (_, stringappend_7520) =>
+  (let stringappend_7530 = (string_drop stringappend_7500 stringappend_7520) in
+  (let (rd, stringappend_7550) =
+       ((case  ((reg_name_matches_prefix stringappend_7530 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7540,stringappend_7550) => (stringappend_7540, stringappend_7550)
+        )) in
+  (let stringappend_7560 = (string_drop stringappend_7530 stringappend_7550) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7560)) of
+        Some (stringappend_7570,stringappend_7580) => (stringappend_7570, stringappend_7580)
+  ) of
+      (_, stringappend_7580) =>
+  (let stringappend_7590 = (string_drop stringappend_7560 stringappend_7580) in
+  (let (rs1, stringappend_7610) =
+       ((case  ((reg_name_matches_prefix stringappend_7590 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7600,stringappend_7610) => (stringappend_7600, stringappend_7610)
+        )) in
+  (let stringappend_7620 = (string_drop stringappend_7590 stringappend_7610) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7620)) of
+        Some (stringappend_7630,stringappend_7640) => (stringappend_7630, stringappend_7640)
+  ) of
+      (_, stringappend_7640) =>
+  (let stringappend_7650 = (string_drop stringappend_7620 stringappend_7640) in
+  (let (shamt, stringappend_7670) =
+       ((case  ((hex_bits_5_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_7650 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7660,stringappend_7670) => (stringappend_7660, stringappend_7670)
+        )) in
+  if(((string_drop stringappend_7650 stringappend_7670)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((rtypew_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_7690,stringappend_7700) =>
+        (let stringappend_7710 = (string_drop stringappend_5410 stringappend_7700) in
+        if ((case  ((spc_matches_prefix stringappend_7710)) of
+            Some (stringappend_7720,stringappend_7730) =>
+             (let stringappend_7740 = (string_drop stringappend_7710 stringappend_7730) in
+             if ((case  ((reg_name_matches_prefix stringappend_7740  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_7750,stringappend_7760) =>
+                  (let stringappend_7770 = (string_drop stringappend_7740 stringappend_7760) in
+                  if ((case  ((sep_matches_prefix stringappend_7770)) of
+                      Some (stringappend_7780,stringappend_7790) =>
+                       (let stringappend_7800 = (string_drop stringappend_7770 stringappend_7790) in
+                       if ((case  ((reg_name_matches_prefix stringappend_7800
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_7810,stringappend_7820) =>
+                            (let stringappend_7830 =
+                              (string_drop stringappend_7800 stringappend_7820) in
+                            if ((case  ((sep_matches_prefix stringappend_7830)) of
+                                Some (stringappend_7840,stringappend_7850) =>
+                                 (let stringappend_7860 =
+                                   (string_drop stringappend_7830 stringappend_7850) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_7860
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_7870,stringappend_7880) => 
+  if(((string_drop stringappend_7860 stringappend_7880)) = ('''')) then 
+  True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_7700) =
+       ((case  ((rtypew_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_7690,stringappend_7700) => (stringappend_7690, stringappend_7700)
+       )) in
+     (let stringappend_7710 = (string_drop stringappend_5410 stringappend_7700) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_7710)) of
+        Some (stringappend_7720,stringappend_7730) => (stringappend_7720, stringappend_7730)
+  ) of
+      (_, stringappend_7730) =>
+  (let stringappend_7740 = (string_drop stringappend_7710 stringappend_7730) in
+  (let (rd, stringappend_7760) =
+       ((case  ((reg_name_matches_prefix stringappend_7740 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7750,stringappend_7760) => (stringappend_7750, stringappend_7760)
+        )) in
+  (let stringappend_7770 = (string_drop stringappend_7740 stringappend_7760) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7770)) of
+        Some (stringappend_7780,stringappend_7790) => (stringappend_7780, stringappend_7790)
+  ) of
+      (_, stringappend_7790) =>
+  (let stringappend_7800 = (string_drop stringappend_7770 stringappend_7790) in
+  (let (rs1, stringappend_7820) =
+       ((case  ((reg_name_matches_prefix stringappend_7800 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7810,stringappend_7820) => (stringappend_7810, stringappend_7820)
+        )) in
+  (let stringappend_7830 = (string_drop stringappend_7800 stringappend_7820) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7830)) of
+        Some (stringappend_7840,stringappend_7850) => (stringappend_7840, stringappend_7850)
+  ) of
+      (_, stringappend_7850) =>
+  (let stringappend_7860 = (string_drop stringappend_7830 stringappend_7850) in
+  (let (rs2, stringappend_7880) =
+       ((case  ((reg_name_matches_prefix stringappend_7860 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7870,stringappend_7880) => (stringappend_7870, stringappend_7880)
+        )) in
+  if(((string_drop stringappend_7860 stringappend_7880)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))
+   else if ((case  ((mul_mnemonic_matches_prefix stringappend_5410)) of
+       Some (stringappend_7900,stringappend_7910) =>
+        (let stringappend_7920 = (string_drop stringappend_5410 stringappend_7910) in
+        if ((case  ((spc_matches_prefix stringappend_7920)) of
+            Some (stringappend_7930,stringappend_7940) =>
+             (let stringappend_7950 = (string_drop stringappend_7920 stringappend_7940) in
+             if ((case  ((reg_name_matches_prefix stringappend_7950  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_7960,stringappend_7970) =>
+                  (let stringappend_7980 = (string_drop stringappend_7950 stringappend_7970) in
+                  if ((case  ((sep_matches_prefix stringappend_7980)) of
+                      Some (stringappend_7990,stringappend_8000) =>
+                       (let stringappend_8010 = (string_drop stringappend_7980 stringappend_8000) in
+                       if ((case  ((reg_name_matches_prefix stringappend_8010
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_8020,stringappend_8030) =>
+                            (let stringappend_8040 =
+                              (string_drop stringappend_8010 stringappend_8030) in
+                            if ((case  ((sep_matches_prefix stringappend_8040)) of
+                                Some (stringappend_8050,stringappend_8060) =>
+                                 (let stringappend_8070 =
+                                   (string_drop stringappend_8040 stringappend_8060) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_8070
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_8080,stringappend_8090) => 
+  if(((string_drop stringappend_8070 stringappend_8090)) = ('''')) then 
+  True else False
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let ((high, signed1, signed2), stringappend_7910) =
+       ((case  ((mul_mnemonic_matches_prefix stringappend_5410)) of
+         Some (stringappend_7900,stringappend_7910) => (stringappend_7900, stringappend_7910)
+       )) in
+     (let stringappend_7920 = (string_drop stringappend_5410 stringappend_7910) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_7920)) of
+        Some (stringappend_7930,stringappend_7940) => (stringappend_7930, stringappend_7940)
+  ) of
+      (_, stringappend_7940) =>
+  (let stringappend_7950 = (string_drop stringappend_7920 stringappend_7940) in
+  (let (rd, stringappend_7970) =
+       ((case  ((reg_name_matches_prefix stringappend_7950 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_7960,stringappend_7970) => (stringappend_7960, stringappend_7970)
+        )) in
+  (let stringappend_7980 = (string_drop stringappend_7950 stringappend_7970) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_7980)) of
+        Some (stringappend_7990,stringappend_8000) => (stringappend_7990, stringappend_8000)
+  ) of
+      (_, stringappend_8000) =>
+  (let stringappend_8010 = (string_drop stringappend_7980 stringappend_8000) in
+  (let (rs1, stringappend_8030) =
+       ((case  ((reg_name_matches_prefix stringappend_8010 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8020,stringappend_8030) => (stringappend_8020, stringappend_8030)
+        )) in
+  (let stringappend_8040 = (string_drop stringappend_8010 stringappend_8030) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8040)) of
+        Some (stringappend_8050,stringappend_8060) => (stringappend_8050, stringappend_8060)
+  ) of
+      (_, stringappend_8060) =>
+  (let stringappend_8070 = (string_drop stringappend_8040 stringappend_8060) in
+  (let (rs2, stringappend_8090) =
+       ((case  ((reg_name_matches_prefix stringappend_8070 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8080,stringappend_8090) => (stringappend_8080, stringappend_8090)
+        )) in
+  if(((string_drop stringappend_8070 stringappend_8090)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_5410 (''div''))) \<and> ((let stringappend_8110 = (string_drop stringappend_5410 ((string_length (''div'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_8110)) of
+                   Some (stringappend_8120,stringappend_8130) =>
+                    (let stringappend_8140 = (string_drop stringappend_8110 stringappend_8130) in
+                    if ((case  ((spc_matches_prefix stringappend_8140)) of
+                        Some (stringappend_8150,stringappend_8160) =>
+                         (let stringappend_8170 = (string_drop stringappend_8140 stringappend_8160) in
+                         if ((case  ((reg_name_matches_prefix stringappend_8170
+                                      ::  (( 5 Word.word * ii))option)) of
+                             Some (stringappend_8180,stringappend_8190) =>
+                              (let stringappend_8200 =
+                                (string_drop stringappend_8170 stringappend_8190) in
+                              if ((case  ((sep_matches_prefix stringappend_8200)) of
+                                  Some (stringappend_8210,stringappend_8220) =>
+                                   (let stringappend_8230 =
+                                     (string_drop stringappend_8200 stringappend_8220) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_8230
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_8240,stringappend_8250) =>
+                                        (let stringappend_8260 =
+                                          (string_drop stringappend_8230 stringappend_8250) in
+                                        if ((case  ((sep_matches_prefix stringappend_8260)) of
+                                            Some (stringappend_8270,stringappend_8280) =>
+                                             (let stringappend_8290 =
+                                               (string_drop stringappend_8260 stringappend_8280) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_8290
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_8300,stringappend_8310) => 
+  if(((string_drop stringappend_8290 stringappend_8310)) = ('''')) then 
+  True else False
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_8110 = (string_drop stringappend_5410 ((string_length (''div'')))) in
+     (let (s, stringappend_8130) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_8110)) of
+         Some (stringappend_8120,stringappend_8130) => (stringappend_8120, stringappend_8130)
+       )) in
+     (let stringappend_8140 = (string_drop stringappend_8110 stringappend_8130) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_8140)) of
+        Some (stringappend_8150,stringappend_8160) => (stringappend_8150, stringappend_8160)
+  ) of
+      (_, stringappend_8160) =>
+  (let stringappend_8170 = (string_drop stringappend_8140 stringappend_8160) in
+  (let (rd, stringappend_8190) =
+       ((case  ((reg_name_matches_prefix stringappend_8170 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8180,stringappend_8190) => (stringappend_8180, stringappend_8190)
+        )) in
+  (let stringappend_8200 = (string_drop stringappend_8170 stringappend_8190) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8200)) of
+        Some (stringappend_8210,stringappend_8220) => (stringappend_8210, stringappend_8220)
+  ) of
+      (_, stringappend_8220) =>
+  (let stringappend_8230 = (string_drop stringappend_8200 stringappend_8220) in
+  (let (rs1, stringappend_8250) =
+       ((case  ((reg_name_matches_prefix stringappend_8230 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8240,stringappend_8250) => (stringappend_8240, stringappend_8250)
+        )) in
+  (let stringappend_8260 = (string_drop stringappend_8230 stringappend_8250) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8260)) of
+        Some (stringappend_8270,stringappend_8280) => (stringappend_8270, stringappend_8280)
+  ) of
+      (_, stringappend_8280) =>
+  (let stringappend_8290 = (string_drop stringappend_8260 stringappend_8280) in
+  (let (rs2, stringappend_8310) =
+       ((case  ((reg_name_matches_prefix stringappend_8290 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8300,stringappend_8310) => (stringappend_8300, stringappend_8310)
+        )) in
+  if(((string_drop stringappend_8290 stringappend_8310)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))))
+   else if (((((string_startswith stringappend_5410 (''rem''))) \<and> ((let stringappend_8330 = (string_drop stringappend_5410 ((string_length (''rem'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_8330)) of
+                   Some (stringappend_8340,stringappend_8350) =>
+                    (let stringappend_8360 = (string_drop stringappend_8330 stringappend_8350) in
+                    if ((case  ((spc_matches_prefix stringappend_8360)) of
+                        Some (stringappend_8370,stringappend_8380) =>
+                         (let stringappend_8390 = (string_drop stringappend_8360 stringappend_8380) in
+                         if ((case  ((reg_name_matches_prefix stringappend_8390
+                                      ::  (( 5 Word.word * ii))option)) of
+                             Some (stringappend_8400,stringappend_8410) =>
+                              (let stringappend_8420 =
+                                (string_drop stringappend_8390 stringappend_8410) in
+                              if ((case  ((sep_matches_prefix stringappend_8420)) of
+                                  Some (stringappend_8430,stringappend_8440) =>
+                                   (let stringappend_8450 =
+                                     (string_drop stringappend_8420 stringappend_8440) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_8450
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_8460,stringappend_8470) =>
+                                        (let stringappend_8480 =
+                                          (string_drop stringappend_8450 stringappend_8470) in
+                                        if ((case  ((sep_matches_prefix stringappend_8480)) of
+                                            Some (stringappend_8490,stringappend_8500) =>
+                                             (let stringappend_8510 =
+                                               (string_drop stringappend_8480 stringappend_8500) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_8510
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_8520,stringappend_8530) => 
+  if(((string_drop stringappend_8510 stringappend_8530)) = ('''')) then 
+  True else False
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_8330 = (string_drop stringappend_5410 ((string_length (''rem'')))) in
+     (let (s, stringappend_8350) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_8330)) of
+         Some (stringappend_8340,stringappend_8350) => (stringappend_8340, stringappend_8350)
+       )) in
+     (let stringappend_8360 = (string_drop stringappend_8330 stringappend_8350) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_8360)) of
+        Some (stringappend_8370,stringappend_8380) => (stringappend_8370, stringappend_8380)
+  ) of
+      (_, stringappend_8380) =>
+  (let stringappend_8390 = (string_drop stringappend_8360 stringappend_8380) in
+  (let (rd, stringappend_8410) =
+       ((case  ((reg_name_matches_prefix stringappend_8390 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8400,stringappend_8410) => (stringappend_8400, stringappend_8410)
+        )) in
+  (let stringappend_8420 = (string_drop stringappend_8390 stringappend_8410) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8420)) of
+        Some (stringappend_8430,stringappend_8440) => (stringappend_8430, stringappend_8440)
+  ) of
+      (_, stringappend_8440) =>
+  (let stringappend_8450 = (string_drop stringappend_8420 stringappend_8440) in
+  (let (rs1, stringappend_8470) =
+       ((case  ((reg_name_matches_prefix stringappend_8450 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8460,stringappend_8470) => (stringappend_8460, stringappend_8470)
+        )) in
+  (let stringappend_8480 = (string_drop stringappend_8450 stringappend_8470) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8480)) of
+        Some (stringappend_8490,stringappend_8500) => (stringappend_8490, stringappend_8500)
+  ) of
+      (_, stringappend_8500) =>
+  (let stringappend_8510 = (string_drop stringappend_8480 stringappend_8500) in
+  (let (rs2, stringappend_8530) =
+       ((case  ((reg_name_matches_prefix stringappend_8510 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8520,stringappend_8530) => (stringappend_8520, stringappend_8530)
+        )) in
+  if(((string_drop stringappend_8510 stringappend_8530)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))))
+   else if (((((string_startswith stringappend_5410 (''mulw''))) \<and> ((let stringappend_8550 = (string_drop stringappend_5410 ((string_length (''mulw'')))) in
+               if ((case  ((spc_matches_prefix stringappend_8550)) of
+                   Some (stringappend_8560,stringappend_8570) =>
+                    (let stringappend_8580 = (string_drop stringappend_8550 stringappend_8570) in
+                    if ((case  ((reg_name_matches_prefix stringappend_8580
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_8590,stringappend_8600) =>
+                         (let stringappend_8610 = (string_drop stringappend_8580 stringappend_8600) in
+                         if ((case  ((sep_matches_prefix stringappend_8610)) of
+                             Some (stringappend_8620,stringappend_8630) =>
+                              (let stringappend_8640 =
+                                (string_drop stringappend_8610 stringappend_8630) in
+                              if ((case  ((reg_name_matches_prefix stringappend_8640
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_8650,stringappend_8660) =>
+                                   (let stringappend_8670 =
+                                     (string_drop stringappend_8640 stringappend_8660) in
+                                   if ((case  ((sep_matches_prefix stringappend_8670)) of
+                                       Some (stringappend_8680,stringappend_8690) =>
+                                        (let stringappend_8700 =
+                                          (string_drop stringappend_8670 stringappend_8690) in
+                                        if ((case  ((reg_name_matches_prefix stringappend_8700
+                                                     ::  (( 5 Word.word * ii))option)) of
+                                            Some (stringappend_8710,stringappend_8720) => 
+  if(((string_drop stringappend_8700 stringappend_8720)) = ('''')) then 
+  True else False
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_8550 = (string_drop stringappend_5410 ((string_length (''mulw'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_8550)) of
+        Some (stringappend_8560,stringappend_8570) => (stringappend_8560, stringappend_8570)
+  ) of
+      (_, stringappend_8570) =>
+  (let stringappend_8580 = (string_drop stringappend_8550 stringappend_8570) in
+  (let (rd, stringappend_8600) =
+       ((case  ((reg_name_matches_prefix stringappend_8580 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8590,stringappend_8600) => (stringappend_8590, stringappend_8600)
+        )) in
+  (let stringappend_8610 = (string_drop stringappend_8580 stringappend_8600) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8610)) of
+        Some (stringappend_8620,stringappend_8630) => (stringappend_8620, stringappend_8630)
+  ) of
+      (_, stringappend_8630) =>
+  (let stringappend_8640 = (string_drop stringappend_8610 stringappend_8630) in
+  (let (rs1, stringappend_8660) =
+       ((case  ((reg_name_matches_prefix stringappend_8640 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8650,stringappend_8660) => (stringappend_8650, stringappend_8660)
+        )) in
+  (let stringappend_8670 = (string_drop stringappend_8640 stringappend_8660) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8670)) of
+        Some (stringappend_8680,stringappend_8690) => (stringappend_8680, stringappend_8690)
+  ) of
+      (_, stringappend_8690) =>
+  (let stringappend_8700 = (string_drop stringappend_8670 stringappend_8690) in
+  (let (rs2, stringappend_8720) =
+       ((case  ((reg_name_matches_prefix stringappend_8700 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8710,stringappend_8720) => (stringappend_8710, stringappend_8720)
+        )) in
+  if(((string_drop stringappend_8700 stringappend_8720)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_5410 (''div''))) \<and> ((let stringappend_8740 = (string_drop stringappend_5410 ((string_length (''div'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_8740)) of
+                   Some (stringappend_8750,stringappend_8760) =>
+                    (let stringappend_8770 = (string_drop stringappend_8740 stringappend_8760) in
+                    if (((((string_startswith stringappend_8770 (''w''))) \<and> ((let stringappend_8780 =
+                             (string_drop stringappend_8770 ((string_length (''w'')))) in
+                           if ((case  ((spc_matches_prefix stringappend_8780)) of
+                               Some (stringappend_8790,stringappend_8800) =>
+                                (let stringappend_8810 =
+                                  (string_drop stringappend_8780 stringappend_8800) in
+                                if ((case  ((reg_name_matches_prefix stringappend_8810
+                                             ::  (( 5 Word.word * ii))option)) of
+                                    Some (stringappend_8820,stringappend_8830) =>
+                                     (let stringappend_8840 =
+                                       (string_drop stringappend_8810 stringappend_8830) in
+                                     if ((case  ((sep_matches_prefix stringappend_8840)) of
+                                         Some (stringappend_8850,stringappend_8860) =>
+                                          (let stringappend_8870 =
+                                            (string_drop stringappend_8840 stringappend_8860) in
+                                          if ((case  ((reg_name_matches_prefix stringappend_8870
+                                                       ::  (( 5 Word.word * ii))option)) of
+                                              Some (stringappend_8880,stringappend_8890) =>
+                                               (let stringappend_8900 =
+                                                 (string_drop stringappend_8870 stringappend_8890) in
+                                               if ((case  ((sep_matches_prefix stringappend_8900)) of
+                                                   Some (stringappend_8910,stringappend_8920) =>
+                                                    (let stringappend_8930 =
+                                                      (string_drop stringappend_8900
+                                                        stringappend_8920) in
+                                                    if ((case  ((reg_name_matches_prefix
+                                                                  stringappend_8930
+                                                                 ::  (( 5 Word.word * ii))option)) of
+                                                        Some (stringappend_8940,stringappend_8950) => 
+  if(((string_drop stringappend_8930 stringappend_8950)) = ('''')) then 
+  True else False
+                                                      | None => False
+                                                      )) then
+                                                      True
+                                                    else False)
+                                                 | None => False
+                                                 )) then
+                                                 True
+                                               else False)
+                                            | None => False
+                                            )) then
+                                            True
+                                          else False)
+                                       | None => False
+                                       )) then
+                                       True
+                                     else False)
+                                  | None => False
+                                  )) then
+                                  True
+                                else False)
+                             | None => False
+                             )) then
+                             True
+                           else False))))) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_8740 = (string_drop stringappend_5410 ((string_length (''div'')))) in
+     (let (s, stringappend_8760) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_8740)) of
+         Some (stringappend_8750,stringappend_8760) => (stringappend_8750, stringappend_8760)
+       )) in
+     (let stringappend_8770 = (string_drop stringappend_8740 stringappend_8760) in
+     (let stringappend_8780 = (string_drop stringappend_8770 ((string_length (''w'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_8780)) of
+        Some (stringappend_8790,stringappend_8800) => (stringappend_8790, stringappend_8800)
+  ) of
+      (_, stringappend_8800) =>
+  (let stringappend_8810 = (string_drop stringappend_8780 stringappend_8800) in
+  (let (rd, stringappend_8830) =
+       ((case  ((reg_name_matches_prefix stringappend_8810 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8820,stringappend_8830) => (stringappend_8820, stringappend_8830)
+        )) in
+  (let stringappend_8840 = (string_drop stringappend_8810 stringappend_8830) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8840)) of
+        Some (stringappend_8850,stringappend_8860) => (stringappend_8850, stringappend_8860)
+  ) of
+      (_, stringappend_8860) =>
+  (let stringappend_8870 = (string_drop stringappend_8840 stringappend_8860) in
+  (let (rs1, stringappend_8890) =
+       ((case  ((reg_name_matches_prefix stringappend_8870 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8880,stringappend_8890) => (stringappend_8880, stringappend_8890)
+        )) in
+  (let stringappend_8900 = (string_drop stringappend_8870 stringappend_8890) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_8900)) of
+        Some (stringappend_8910,stringappend_8920) => (stringappend_8910, stringappend_8920)
+  ) of
+      (_, stringappend_8920) =>
+  (let stringappend_8930 = (string_drop stringappend_8900 stringappend_8920) in
+  (let (rs2, stringappend_8950) =
+       ((case  ((reg_name_matches_prefix stringappend_8930 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_8940,stringappend_8950) => (stringappend_8940, stringappend_8950)
+        )) in
+  if(((string_drop stringappend_8930 stringappend_8950)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))))
+   else if (((((string_startswith stringappend_5410 (''rem''))) \<and> ((let stringappend_8970 = (string_drop stringappend_5410 ((string_length (''rem'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_8970)) of
+                   Some (stringappend_8980,stringappend_8990) =>
+                    (let stringappend_9000 = (string_drop stringappend_8970 stringappend_8990) in
+                    if (((((string_startswith stringappend_9000 (''w''))) \<and> ((let stringappend_9010 =
+                             (string_drop stringappend_9000 ((string_length (''w'')))) in
+                           if ((case  ((spc_matches_prefix stringappend_9010)) of
+                               Some (stringappend_9020,stringappend_9030) =>
+                                (let stringappend_9040 =
+                                  (string_drop stringappend_9010 stringappend_9030) in
+                                if ((case  ((reg_name_matches_prefix stringappend_9040
+                                             ::  (( 5 Word.word * ii))option)) of
+                                    Some (stringappend_9050,stringappend_9060) =>
+                                     (let stringappend_9070 =
+                                       (string_drop stringappend_9040 stringappend_9060) in
+                                     if ((case  ((sep_matches_prefix stringappend_9070)) of
+                                         Some (stringappend_9080,stringappend_9090) =>
+                                          (let stringappend_9100 =
+                                            (string_drop stringappend_9070 stringappend_9090) in
+                                          if ((case  ((reg_name_matches_prefix stringappend_9100
+                                                       ::  (( 5 Word.word * ii))option)) of
+                                              Some (stringappend_9110,stringappend_9120) =>
+                                               (let stringappend_9130 =
+                                                 (string_drop stringappend_9100 stringappend_9120) in
+                                               if ((case  ((sep_matches_prefix stringappend_9130)) of
+                                                   Some (stringappend_9140,stringappend_9150) =>
+                                                    (let stringappend_9160 =
+                                                      (string_drop stringappend_9130
+                                                        stringappend_9150) in
+                                                    if ((case  ((reg_name_matches_prefix
+                                                                  stringappend_9160
+                                                                 ::  (( 5 Word.word * ii))option)) of
+                                                        Some (stringappend_9170,stringappend_9180) => 
+  if(((string_drop stringappend_9160 stringappend_9180)) = ('''')) then 
+  True else False
+                                                      | None => False
+                                                      )) then
+                                                      True
+                                                    else False)
+                                                 | None => False
+                                                 )) then
+                                                 True
+                                               else False)
+                                            | None => False
+                                            )) then
+                                            True
+                                          else False)
+                                       | None => False
+                                       )) then
+                                       True
+                                     else False)
+                                  | None => False
+                                  )) then
+                                  True
+                                else False)
+                             | None => False
+                             )) then
+                             True
+                           else False))))) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_8970 = (string_drop stringappend_5410 ((string_length (''rem'')))) in
+     (let (s, stringappend_8990) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_8970)) of
+         Some (stringappend_8980,stringappend_8990) => (stringappend_8980, stringappend_8990)
+       )) in
+     (let stringappend_9000 = (string_drop stringappend_8970 stringappend_8990) in
+     (let stringappend_9010 = (string_drop stringappend_9000 ((string_length (''w'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_9010)) of
+        Some (stringappend_9020,stringappend_9030) => (stringappend_9020, stringappend_9030)
+  ) of
+      (_, stringappend_9030) =>
+  (let stringappend_9040 = (string_drop stringappend_9010 stringappend_9030) in
+  (let (rd, stringappend_9060) =
+       ((case  ((reg_name_matches_prefix stringappend_9040 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_9050,stringappend_9060) => (stringappend_9050, stringappend_9060)
+        )) in
+  (let stringappend_9070 = (string_drop stringappend_9040 stringappend_9060) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_9070)) of
+        Some (stringappend_9080,stringappend_9090) => (stringappend_9080, stringappend_9090)
+  ) of
+      (_, stringappend_9090) =>
+  (let stringappend_9100 = (string_drop stringappend_9070 stringappend_9090) in
+  (let (rs1, stringappend_9120) =
+       ((case  ((reg_name_matches_prefix stringappend_9100 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_9110,stringappend_9120) => (stringappend_9110, stringappend_9120)
+        )) in
+  (let stringappend_9130 = (string_drop stringappend_9100 stringappend_9120) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_9130)) of
+        Some (stringappend_9140,stringappend_9150) => (stringappend_9140, stringappend_9150)
+  ) of
+      (_, stringappend_9150) =>
+  (let stringappend_9160 = (string_drop stringappend_9130 stringappend_9150) in
+  (let (rs2, stringappend_9180) =
+       ((case  ((reg_name_matches_prefix stringappend_9160 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_9170,stringappend_9180) => (stringappend_9170, stringappend_9180)
+        )) in
+  if(((string_drop stringappend_9160 stringappend_9180)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))))
+  )))))
+   else if (((((string_startswith stringappend_5410 (''fence''))) \<and> ((let stringappend_9200 = (string_drop stringappend_5410 ((string_length (''fence'')))) in
+               if ((case  ((spc_matches_prefix stringappend_9200)) of
+                   Some (stringappend_9210,stringappend_9220) =>
+                    (let stringappend_9230 = (string_drop stringappend_9200 stringappend_9220) in
+                    if ((case  ((fence_bits_matches_prefix stringappend_9230
+                                 ::  (( 4 Word.word * ii))option)) of
+                        Some (stringappend_9240,stringappend_9250) =>
+                         (let stringappend_9260 = (string_drop stringappend_9230 stringappend_9250) in
+                         if ((case  ((sep_matches_prefix stringappend_9260)) of
+                             Some (stringappend_9270,stringappend_9280) =>
+                              (let stringappend_9290 =
+                                (string_drop stringappend_9260 stringappend_9280) in
+                              if ((case  ((fence_bits_matches_prefix stringappend_9290
+                                           ::  (( 4 Word.word * ii))option)) of
+                                  Some (stringappend_9300,stringappend_9310) => 
+  if(((string_drop stringappend_9290 stringappend_9310)) = ('''')) then 
+  True else False
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_9200 = (string_drop stringappend_5410 ((string_length (''fence'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_9200)) of
+        Some (stringappend_9210,stringappend_9220) => (stringappend_9210, stringappend_9220)
+  ) of
+      (_, stringappend_9220) =>
+  (let stringappend_9230 = (string_drop stringappend_9200 stringappend_9220) in
+  (let (pred, stringappend_9250) =
+       ((case  ((fence_bits_matches_prefix stringappend_9230 :: (( 4 Word.word * ii)) option)) of
+              Some (stringappend_9240,stringappend_9250) => (stringappend_9240, stringappend_9250)
+        )) in
+  (let stringappend_9260 = (string_drop stringappend_9230 stringappend_9250) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_9260)) of
+        Some (stringappend_9270,stringappend_9280) => (stringappend_9270, stringappend_9280)
+  ) of
+      (_, stringappend_9280) =>
+  (let stringappend_9290 = (string_drop stringappend_9260 stringappend_9280) in
+  (let (succ, stringappend_9310) =
+       ((case  ((fence_bits_matches_prefix stringappend_9290 :: (( 4 Word.word * ii)) option)) of
+              Some (stringappend_9300,stringappend_9310) => (stringappend_9300, stringappend_9310)
+        )) in
+  if(((string_drop stringappend_9290 stringappend_9310)) = ('''')) then 
+  True else undefined))
+  ))))
+  ))
+   else  if(stringappend_5410 = (''fence.i'')) then True else
+   (
+   if(stringappend_5410 = (''ecall'')) then True else
+     (
+     if(stringappend_5410 = (''mret'')) then True else
+       (
+       if(stringappend_5410 = (''sret'')) then True else
+         (
+         if(stringappend_5410 = (''ebreak'')) then True else
+           (
+           if(stringappend_5410 = (''wfi'')) then True else
+             (
+             if (((((string_startswith stringappend_5410 (''sfence.vma'')))
+                     \<and>
+                     ((let stringappend_9330 =
+                           (string_drop stringappend_5410
+                              ((string_length (''sfence.vma'')))) in
+                      if ((case  ((spc_matches_prefix stringappend_9330)) of
+                                Some (stringappend_9340,stringappend_9350) =>
+                          (let stringappend_9360 = (string_drop
+                                                      stringappend_9330
+                                                      stringappend_9350) in
+                          if ((case  ((reg_name_matches_prefix
+                                         stringappend_9360
+                                      :: (( 5 Word.word * ii)) option)) of
+                                    Some (stringappend_9370,stringappend_9380) =>
+                              (let stringappend_9390 = (string_drop
+                                                          stringappend_9360
+                                                          stringappend_9380) in
+                              if ((case  ((sep_matches_prefix
+                                             stringappend_9390)) of
+                                        Some (stringappend_9400,stringappend_9410) =>
+                                  (let stringappend_9420 =
+                                       (string_drop stringappend_9390
+                                          stringappend_9410) in
+                                  if ((case  ((reg_name_matches_prefix
+                                                 stringappend_9420
+                                              :: (( 5 Word.word * ii)) option)) of
+                                            Some (stringappend_9430,stringappend_9440) =>
+                                      if(((string_drop stringappend_9420
+                                             stringappend_9440)) = ('''')) then
+                                        True else False
+                                        | None => False
+                                      )) then True else False)
+                                    | None => False
+                                  )) then True else False)
+                                | None => False
+                              )) then True else False)
+                            | None => False
+                          )) then True else False))))) then
+               (let stringappend_9330 = (string_drop stringappend_5410
+                                           ((string_length (''sfence.vma'')))) in
+               (case 
+               (case  ((spc_matches_prefix stringappend_9330)) of
+                     Some (stringappend_9340,stringappend_9350) =>
+               (stringappend_9340, stringappend_9350)
+               ) of
+                   (_, stringappend_9350) =>
+               (let stringappend_9360 = (string_drop stringappend_9330
+                                           stringappend_9350) in
+               (let (rs1, stringappend_9380) =
+                    ((case  ((reg_name_matches_prefix stringappend_9360 :: (( 5 Word.word * ii)) option)) of
+                           Some (stringappend_9370,stringappend_9380) =>
+                     (stringappend_9370, stringappend_9380)
+                     )) in
+               (let stringappend_9390 = (string_drop stringappend_9360
+                                           stringappend_9380) in
+               (case 
+               (case  ((sep_matches_prefix stringappend_9390)) of
+                     Some (stringappend_9400,stringappend_9410) =>
+               (stringappend_9400, stringappend_9410)
+               ) of
+                   (_, stringappend_9410) =>
+               (let stringappend_9420 = (string_drop stringappend_9390
+                                           stringappend_9410) in
+               (let (rs2, stringappend_9440) =
+                    ((case  ((reg_name_matches_prefix stringappend_9420 :: (( 5 Word.word * ii)) option)) of
+                           Some (stringappend_9430,stringappend_9440) =>
+                     (stringappend_9430, stringappend_9440)
+                     )) in
+               if(((string_drop stringappend_9420 stringappend_9440)) =
+                    ('''')) then True else undefined))
+               ))))
+               )) else
+               if (((((string_startswith stringappend_5410 (''lr.''))) \<and>
+                       ((let stringappend_9460 = (string_drop
+                                                    stringappend_5410
+                                                    ((string_length (''lr.'')))) in
+                        if ((case  ((maybe_aq_matches_prefix
+                                       stringappend_9460)) of
+                                  Some (stringappend_9470,stringappend_9480) =>
+                            (let stringappend_9490 = (string_drop
+                                                        stringappend_9460
+                                                        stringappend_9480) in
+                            if ((case  ((maybe_rl_matches_prefix
+                                           stringappend_9490)) of
+                                      Some (stringappend_9500,stringappend_9510) =>
+                                (let stringappend_9520 =
+                                     (string_drop stringappend_9490
+                                        stringappend_9510) in
+                                if ((case  ((size_mnemonic_matches_prefix
+                                               stringappend_9520)) of
+                                          Some (stringappend_9530,stringappend_9540) =>
+                                    (let stringappend_9550 =
+                                         (string_drop stringappend_9520
+                                            stringappend_9540) in
+                                    if ((case  ((spc_matches_prefix
+                                                   stringappend_9550)) of
+                                              Some (stringappend_9560,stringappend_9570) =>
+                                        (let stringappend_9580 =
+                                             (string_drop stringappend_9550
+                                                stringappend_9570) in
+                                        if ((case  ((reg_name_matches_prefix
+                                                       stringappend_9580
+                                                    :: (( 5 Word.word * ii)) option)) of
+                                                  Some (stringappend_9590,stringappend_9600) =>
+                                            (let stringappend_9610 =
+                                                 (string_drop
+                                                    stringappend_9580
+                                                    stringappend_9600) in
+                                            if ((case  ((sep_matches_prefix
+                                                           stringappend_9610)) of
+                                                      Some (stringappend_9620,stringappend_9630) =>
+                                                (let stringappend_9640 =
+                                                     (string_drop
+                                                        stringappend_9610
+                                                        stringappend_9630) in
+                                                if ((case  ((reg_name_matches_prefix
+                                                               stringappend_9640
+                                                            :: (( 5 Word.word * ii)) option)) of
+                                                          Some (stringappend_9650,stringappend_9660) =>
+                                                    if(((string_drop
+                                                           stringappend_9640
+                                                           stringappend_9660))
+                                                         = ('''')) then 
+                                                    True else False
+                                                      | None => False
+                                                    )) then True else 
+                                                False)
+                                                  | None => False
+                                                )) then True else False)
+                                              | None => False
+                                            )) then True else False)
+                                          | None => False
+                                        )) then True else False)
+                                      | None => False
+                                    )) then True else False)
+                                  | None => False
+                                )) then True else False)
+                              | None => False
+                            )) then True else False))))) then
+                 (let stringappend_9460 = (string_drop stringappend_5410
+                                             ((string_length (''lr.'')))) in
+                 (let (aq, stringappend_9480) =
+                      ((case  ((maybe_aq_matches_prefix stringappend_9460)) of
+                             Some (stringappend_9470,stringappend_9480) =>
+                       (stringappend_9470, stringappend_9480)
+                       )) in
+                 (let stringappend_9490 = (string_drop stringappend_9460
+                                             stringappend_9480) in
+                 (let (rl, stringappend_9510) =
+                      ((case  ((maybe_rl_matches_prefix stringappend_9490)) of
+                             Some (stringappend_9500,stringappend_9510) =>
+                       (stringappend_9500, stringappend_9510)
+                       )) in
+                 (let stringappend_9520 = (string_drop stringappend_9490
+                                             stringappend_9510) in
+                 (let (size1, stringappend_9540) =
+                      ((case  ((size_mnemonic_matches_prefix
+                                  stringappend_9520)) of
+                             Some (stringappend_9530,stringappend_9540) =>
+                       (stringappend_9530, stringappend_9540)
+                       )) in
+                 (let stringappend_9550 = (string_drop stringappend_9520
+                                             stringappend_9540) in
+                 (case 
+                 (case  ((spc_matches_prefix stringappend_9550)) of
+                       Some (stringappend_9560,stringappend_9570) =>
+                 (stringappend_9560, stringappend_9570)
+                 ) of
+                     (_, stringappend_9570) =>
+                 (let stringappend_9580 = (string_drop stringappend_9550
+                                             stringappend_9570) in
+                 (let (rd, stringappend_9600) =
+                      ((case  ((reg_name_matches_prefix stringappend_9580 :: (( 5 Word.word * ii)) option)) of
+                             Some (stringappend_9590,stringappend_9600) =>
+                       (stringappend_9590, stringappend_9600)
+                       )) in
+                 (let stringappend_9610 = (string_drop stringappend_9580
+                                             stringappend_9600) in
+                 (case 
+                 (case  ((sep_matches_prefix stringappend_9610)) of
+                       Some (stringappend_9620,stringappend_9630) =>
+                 (stringappend_9620, stringappend_9630)
+                 ) of
+                     (_, stringappend_9630) =>
+                 (let stringappend_9640 = (string_drop stringappend_9610
+                                             stringappend_9630) in
+                 (let (rs1, stringappend_9660) =
+                      ((case  ((reg_name_matches_prefix stringappend_9640 :: (( 5 Word.word * ii)) option)) of
+                             Some (stringappend_9650,stringappend_9660) =>
+                       (stringappend_9650, stringappend_9660)
+                       )) in
+                 if(((string_drop stringappend_9640 stringappend_9660)) =
+                      ('''')) then True else undefined))
+                 ))))
+                 )))))))) else
+                 if (((((string_startswith stringappend_5410 (''sc.'')))
+                         \<and>
+                         ((let stringappend_9680 = (string_drop
+                                                      stringappend_5410
+                                                      ((string_length
+                                                          (''sc.'')))) in
+                          if ((case  ((maybe_aq_matches_prefix
+                                         stringappend_9680)) of
+                                    Some (stringappend_9690,stringappend_9700) =>
+                              (let stringappend_9710 = (string_drop
+                                                          stringappend_9680
+                                                          stringappend_9700) in
+                              if ((case  ((maybe_rl_matches_prefix
+                                             stringappend_9710)) of
+                                        Some (stringappend_9720,stringappend_9730) =>
+                                  (let stringappend_9740 =
+                                       (string_drop stringappend_9710
+                                          stringappend_9730) in
+                                  if ((case  ((size_mnemonic_matches_prefix
+                                                 stringappend_9740)) of
+                                            Some (stringappend_9750,stringappend_9760) =>
+                                      (let stringappend_9770 =
+                                           (string_drop stringappend_9740
+                                              stringappend_9760) in
+                                      if ((case  ((spc_matches_prefix
+                                                     stringappend_9770)) of
+                                                Some (stringappend_9780,stringappend_9790) =>
+                                          (let stringappend_9800 =
+                                               (string_drop stringappend_9770
+                                                  stringappend_9790) in
+                                          if ((case  ((reg_name_matches_prefix
+                                                         stringappend_9800
+                                                      :: (( 5 Word.word * ii)) option)) of
+                                                    Some (stringappend_9810,stringappend_9820) =>
+                                              (let stringappend_9830 =
+                                                   (string_drop
+                                                      stringappend_9800
+                                                      stringappend_9820) in
+                                              if ((case  ((sep_matches_prefix
+                                                             stringappend_9830)) of
+                                                        Some (stringappend_9840,stringappend_9850) =>
+                                                  (let stringappend_9860 =
+                                                       (string_drop
+                                                          stringappend_9830
+                                                          stringappend_9850) in
+                                                  if ((case  ((reg_name_matches_prefix
+                                                                 stringappend_9860
+                                                              :: (( 5 Word.word * ii)) option)) of
+                                                            Some (stringappend_9870,stringappend_9880) =>
+                                                      (let stringappend_9890 =
+                                                           (string_drop
+                                                              stringappend_9860
+                                                              stringappend_9880) in
+                                                      if ((case  ((sep_matches_prefix
+                                                                    stringappend_9890)) of
+                                                                Some
+                                                          (stringappend_9900,stringappend_9910) =>
+                                                          (let stringappend_9920 =
+                                                               (string_drop
+                                                                  stringappend_9890
+                                                                  stringappend_9910) in
+                                                          if ((case  
+                                                              ((reg_name_matches_prefix
+                                                                  stringappend_9920
+                                                               :: (( 5 Word.word * ii)) option)) of
+                                                                    Some
+                                                              (stringappend_9930,stringappend_9940) =>
+                                                              if(((string_drop
+                                                                    stringappend_9920
+                                                                    stringappend_9940))
+                                                                   = 
+                                                                 ('''')) then
+                                                                True else
+                                                                False
+                                                                | None => 
+                                                              False
+                                                              )) then 
+                                                          True else False)
+                                                            | None => 
+                                                          False
+                                                          )) then True else
+                                                        False)
+                                                        | None => False
+                                                      )) then True else 
+                                                  False)
+                                                    | None => False
+                                                  )) then True else False)
+                                                | None => False
+                                              )) then True else False)
+                                            | None => False
+                                          )) then True else False)
+                                        | None => False
+                                      )) then True else False)
+                                    | None => False
+                                  )) then True else False)
+                                | None => False
+                              )) then True else False))))) then
+                   (let stringappend_9680 = (string_drop stringappend_5410
+                                               ((string_length (''sc.'')))) in
+                   (let (aq, stringappend_9700) =
+                        ((case  ((maybe_aq_matches_prefix stringappend_9680)) of
+                               Some (stringappend_9690,stringappend_9700) =>
+                         (stringappend_9690, stringappend_9700)
+                         )) in
+                   (let stringappend_9710 = (string_drop stringappend_9680
+                                               stringappend_9700) in
+                   (let (rl, stringappend_9730) =
+                        ((case  ((maybe_rl_matches_prefix stringappend_9710)) of
+                               Some (stringappend_9720,stringappend_9730) =>
+                         (stringappend_9720, stringappend_9730)
+                         )) in
+                   (let stringappend_9740 = (string_drop stringappend_9710
+                                               stringappend_9730) in
+                   (let (size1, stringappend_9760) =
+                        ((case  ((size_mnemonic_matches_prefix
+                                    stringappend_9740)) of
+                               Some (stringappend_9750,stringappend_9760) =>
+                         (stringappend_9750, stringappend_9760)
+                         )) in
+                   (let stringappend_9770 = (string_drop stringappend_9740
+                                               stringappend_9760) in
+                   (case 
+                   (case  ((spc_matches_prefix stringappend_9770)) of
+                         Some (stringappend_9780,stringappend_9790) =>
+                   (stringappend_9780, stringappend_9790)
+                   ) of
+                       (_, stringappend_9790) =>
+                   (let stringappend_9800 = (string_drop stringappend_9770
+                                               stringappend_9790) in
+                   (let (rd, stringappend_9820) =
+                        ((case  ((reg_name_matches_prefix stringappend_9800 :: (( 5 Word.word * ii)) option)) of
+                               Some (stringappend_9810,stringappend_9820) =>
+                         (stringappend_9810, stringappend_9820)
+                         )) in
+                   (let stringappend_9830 = (string_drop stringappend_9800
+                                               stringappend_9820) in
+                   (case 
+                   (case  ((sep_matches_prefix stringappend_9830)) of
+                         Some (stringappend_9840,stringappend_9850) =>
+                   (stringappend_9840, stringappend_9850)
+                   ) of
+                       (_, stringappend_9850) =>
+                   (let stringappend_9860 = (string_drop stringappend_9830
+                                               stringappend_9850) in
+                   (let (rs1, stringappend_9880) =
+                        ((case  ((reg_name_matches_prefix stringappend_9860 :: (( 5 Word.word * ii)) option)) of
+                               Some (stringappend_9870,stringappend_9880) =>
+                         (stringappend_9870, stringappend_9880)
+                         )) in
+                   (let stringappend_9890 = (string_drop stringappend_9860
+                                               stringappend_9880) in
+                   (case 
+                   (case  ((sep_matches_prefix stringappend_9890)) of
+                         Some (stringappend_9900,stringappend_9910) =>
+                   (stringappend_9900, stringappend_9910)
+                   ) of
+                       (_, stringappend_9910) =>
+                   (let stringappend_9920 = (string_drop stringappend_9890
+                                               stringappend_9910) in
+                   (let (rs2, stringappend_9940) =
+                        ((case  ((reg_name_matches_prefix stringappend_9920 :: (( 5 Word.word * ii)) option)) of
+                               Some (stringappend_9930,stringappend_9940) =>
+                         (stringappend_9930, stringappend_9940)
+                         )) in
+                   if(((string_drop stringappend_9920 stringappend_9940)) =
+                        ('''')) then True else undefined))
+                   ))))
+                   ))))
+                   )))))))) else
+                   if ((case  ((amo_mnemonic_matches_prefix stringappend_5410)) of
+                             Some (stringappend_9960,stringappend_9970) =>
+                       (let stringappend_9980 = (string_drop
+                                                   stringappend_5410
+                                                   stringappend_9970) in
+                       if (((((string_startswith stringappend_9980 (''.'')))
+                               \<and>
+                               ((let stringappend_9990 = (string_drop
+                                                            stringappend_9980
+                                                            ((string_length
+                                                                (''.'')))) in
+                                if ((case  ((size_mnemonic_matches_prefix
+                                               stringappend_9990)) of
+                                          Some (stringappend_10000,stringappend_10010) =>
+                                    (let stringappend_10020 =
+                                         (string_drop stringappend_9990
+                                            stringappend_10010) in
+                                    if ((case  ((maybe_aq_matches_prefix
+                                                   stringappend_10020)) of
+                                              Some (stringappend_10030,stringappend_10040) =>
+                                        (let stringappend_10050 =
+                                             (string_drop stringappend_10020
+                                                stringappend_10040) in
+                                        if ((case  ((maybe_rl_matches_prefix
+                                                       stringappend_10050)) of
+                                                  Some (stringappend_10060,stringappend_10070) =>
+                                            (let stringappend_10080 =
+                                                 (string_drop
+                                                    stringappend_10050
+                                                    stringappend_10070) in
+                                            if ((case  ((spc_matches_prefix
+                                                           stringappend_10080)) of
+                                                      Some (stringappend_10090,stringappend_10100) =>
+                                                (let stringappend_10110 =
+                                                     (string_drop
+                                                        stringappend_10080
+                                                        stringappend_10100) in
+                                                if ((case  ((reg_name_matches_prefix
+                                                               stringappend_10110
+                                                            :: (( 5 Word.word * ii)) option)) of
+                                                          Some (stringappend_10120,stringappend_10130) =>
+                                                    (let stringappend_10140 =
+                                                         (string_drop
+                                                            stringappend_10110
+                                                            stringappend_10130) in
+                                                    if ((case  ((sep_matches_prefix
+                                                                   stringappend_10140)) of
+                                                              Some (stringappend_10150,stringappend_10160) =>
+                                                        (let stringappend_10170 =
+                                                             (string_drop
+                                                                stringappend_10140
+                                                                stringappend_10160) in
+                                                        if ((case  ((
+                                                                    reg_name_matches_prefix
+                                                                    stringappend_10170
+                                                                    :: (( 5 Word.word * ii)) option)) of
+                                                                  Some (stringappend_10180,stringappend_10190) =>
+                                                            (let stringappend_10200 =
+                                                                 (string_drop
+                                                                    stringappend_10170
+                                                                    stringappend_10190) in
+                                                            if ((case  
+                                                                ((sep_matches_prefix
+                                                                    stringappend_10200)) of
+                                                                      Some
+                                                                (stringappend_10210,stringappend_10220) =>
+                                                                (let 
+                                                                stringappend_10230 =
+                                                                (string_drop
+                                                                   stringappend_10200
+                                                                   stringappend_10220) in
+                                                                if ((case  
+                                                                    (
+                                                                    (
+                                                                    reg_name_matches_prefix
+                                                                    stringappend_10230
+                                                                    :: (( 5 Word.word * ii)) option)) of
+                                                                      Some
+                                                                    (stringappend_10240,stringappend_10250) =>
+                                                                    if
+                                                                    (
+                                                                    (
+                                                                    (
+                                                                    string_drop
+                                                                    stringappend_10230
+                                                                    stringappend_10250))
+                                                                    = 
+                                                                    ('''')) then
+                                                                    True else
+                                                                    False
+                                                                    | None => 
+                                                                    False
+                                                                    )) then
+                                                                  True else
+                                                                  False)
+                                                                  | None => 
+                                                                False
+                                                                )) then 
+                                                            True else 
+                                                            False)
+                                                              | None => 
+                                                            False
+                                                            )) then True else
+                                                          False)
+                                                          | None => False
+                                                        )) then True else
+                                                      False)
+                                                      | None => False
+                                                    )) then True else 
+                                                False)
+                                                  | None => False
+                                                )) then True else False)
+                                              | None => False
+                                            )) then True else False)
+                                          | None => False
+                                        )) then True else False)
+                                      | None => False
+                                    )) then True else False))))) then 
+                       True else False)
+                         | None => False
+                       )) then
+                     (let (op1, stringappend_9970) =
+                          ((case  ((amo_mnemonic_matches_prefix
+                                      stringappend_5410)) of
+                                 Some (stringappend_9960,stringappend_9970) =>
+                           (stringappend_9960, stringappend_9970)
+                           )) in
+                     (let stringappend_9980 = (string_drop stringappend_5410
+                                                 stringappend_9970) in
+                     (let stringappend_9990 = (string_drop stringappend_9980
+                                                 ((string_length (''.'')))) in
+                     (let (width, stringappend_10010) =
+                          ((case  ((size_mnemonic_matches_prefix
+                                      stringappend_9990)) of
+                                 Some (stringappend_10000,stringappend_10010) =>
+                           (stringappend_10000, stringappend_10010)
+                           )) in
+                     (let stringappend_10020 = (string_drop stringappend_9990
+                                                  stringappend_10010) in
+                     (let (aq, stringappend_10040) =
+                          ((case  ((maybe_aq_matches_prefix
+                                      stringappend_10020)) of
+                                 Some (stringappend_10030,stringappend_10040) =>
+                           (stringappend_10030, stringappend_10040)
+                           )) in
+                     (let stringappend_10050 = (string_drop
+                                                  stringappend_10020
+                                                  stringappend_10040) in
+                     (let (rl, stringappend_10070) =
+                          ((case  ((maybe_rl_matches_prefix
+                                      stringappend_10050)) of
+                                 Some (stringappend_10060,stringappend_10070) =>
+                           (stringappend_10060, stringappend_10070)
+                           )) in
+                     (let stringappend_10080 = (string_drop
+                                                  stringappend_10050
+                                                  stringappend_10070) in
+                     (case 
+                     (case  ((spc_matches_prefix stringappend_10080)) of
+                           Some (stringappend_10090,stringappend_10100) =>
+                     (stringappend_10090, stringappend_10100)
+                     ) of
+                         (_, stringappend_10100) =>
+                     (let stringappend_10110 = (string_drop
+                                                  stringappend_10080
+                                                  stringappend_10100) in
+                     (let (rd, stringappend_10130) =
+                          ((case  ((reg_name_matches_prefix
+                                      stringappend_10110 :: (( 5 Word.word * ii)) option)) of
+                                 Some (stringappend_10120,stringappend_10130) =>
+                           (stringappend_10120, stringappend_10130)
+                           )) in
+                     (let stringappend_10140 = (string_drop
+                                                  stringappend_10110
+                                                  stringappend_10130) in
+                     (case 
+                     (case  ((sep_matches_prefix stringappend_10140)) of
+                           Some (stringappend_10150,stringappend_10160) =>
+                     (stringappend_10150, stringappend_10160)
+                     ) of
+                         (_, stringappend_10160) =>
+                     (let stringappend_10170 = (string_drop
+                                                  stringappend_10140
+                                                  stringappend_10160) in
+                     (let (rs1, stringappend_10190) =
+                          ((case  ((reg_name_matches_prefix
+                                      stringappend_10170 :: (( 5 Word.word * ii)) option)) of
+                                 Some (stringappend_10180,stringappend_10190) =>
+                           (stringappend_10180, stringappend_10190)
+                           )) in
+                     (let stringappend_10200 = (string_drop
+                                                  stringappend_10170
+                                                  stringappend_10190) in
+                     (case 
+                     (case  ((sep_matches_prefix stringappend_10200)) of
+                           Some (stringappend_10210,stringappend_10220) =>
+                     (stringappend_10210, stringappend_10220)
+                     ) of
+                         (_, stringappend_10220) =>
+                     (let stringappend_10230 = (string_drop
+                                                  stringappend_10200
+                                                  stringappend_10220) in
+                     (let (rs2, stringappend_10250) =
+                          ((case  ((reg_name_matches_prefix
+                                      stringappend_10230 :: (( 5 Word.word * ii)) option)) of
+                                 Some (stringappend_10240,stringappend_10250) =>
+                           (stringappend_10240, stringappend_10250)
+                           )) in
+                     if(((string_drop stringappend_10230 stringappend_10250))
+                          = ('''')) then True else undefined))
+                     ))))
+                     ))))
+                     )))))))))) else
+                     if ((case  ((csr_mnemonic_matches_prefix
+                                    stringappend_5410)) of
+                               Some (stringappend_10270,stringappend_10280) =>
+                         (let stringappend_10290 = (string_drop
+                                                      stringappend_5410
+                                                      stringappend_10280) in
+                         if (((((string_startswith stringappend_10290 (''i'')))
+                                 \<and>
+                                 ((let stringappend_10300 = (string_drop
+                                                               stringappend_10290
+                                                               ((string_length
+                                                                   (''i'')))) in
+                                  if ((case  ((spc_matches_prefix
+                                                 stringappend_10300)) of
+                                            Some (stringappend_10310,stringappend_10320) =>
+                                      (let stringappend_10330 =
+                                           (string_drop stringappend_10300
+                                              stringappend_10320) in
+                                      if ((case  ((reg_name_matches_prefix
+                                                     stringappend_10330
+                                                  :: (( 5 Word.word * ii)) option)) of
+                                                Some (stringappend_10340,stringappend_10350) =>
+                                          (let stringappend_10360 =
+                                               (string_drop
+                                                  stringappend_10330
+                                                  stringappend_10350) in
+                                          if ((case  ((sep_matches_prefix
+                                                         stringappend_10360)) of
+                                                    Some (stringappend_10370,stringappend_10380) =>
+                                              (let stringappend_10390 =
+                                                   (string_drop
+                                                      stringappend_10360
+                                                      stringappend_10380) in
+                                              if ((case  ((hex_bits_5_matches_prefix
+                                                             instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                             stringappend_10390
+                                                          :: (( 5 Word.word * ii)) option)) of
+                                                        Some (stringappend_10400,stringappend_10410) =>
+                                                  (let stringappend_10420 =
+                                                       (string_drop
+                                                          stringappend_10390
+                                                          stringappend_10410) in
+                                                  if ((case  ((sep_matches_prefix
+                                                                 stringappend_10420)) of
+                                                            Some (stringappend_10430,stringappend_10440) =>
+                                                      (let stringappend_10450 =
+                                                           (string_drop
+                                                              stringappend_10420
+                                                              stringappend_10440) in
+                                                      if ((case  ((csr_name_map_matches_prefix
+                                                                    stringappend_10450
+                                                                  :: (( 12 Word.word * ii)) option)) of
+                                                                Some (stringappend_10460,stringappend_10470) =>
+                                                          if(((string_drop
+                                                                 stringappend_10450
+                                                                 stringappend_10470))
+                                                               = ('''')) then
+                                                            True else 
+                                                          False
+                                                            | None => 
+                                                          False
+                                                          )) then True else
+                                                        False)
+                                                        | None => False
+                                                      )) then True else 
+                                                  False)
+                                                    | None => False
+                                                  )) then True else False)
+                                                | None => False
+                                              )) then True else False)
+                                            | None => False
+                                          )) then True else False)
+                                        | None => False
+                                      )) then True else False))))) then 
+                         True else False)
+                           | None => False
+                         )) then
+                       (let (op1, stringappend_10280) =
+                            ((case  ((csr_mnemonic_matches_prefix
+                                        stringappend_5410)) of
+                                   Some (stringappend_10270,stringappend_10280) =>
+                             (stringappend_10270, stringappend_10280)
+                             )) in
+                       (let stringappend_10290 = (string_drop
+                                                    stringappend_5410
+                                                    stringappend_10280) in
+                       (let stringappend_10300 = (string_drop
+                                                    stringappend_10290
+                                                    ((string_length (''i'')))) in
+                       (case 
+                       (case  ((spc_matches_prefix stringappend_10300)) of
+                             Some (stringappend_10310,stringappend_10320) =>
+                       (stringappend_10310, stringappend_10320)
+                       ) of
+                           (_, stringappend_10320) =>
+                       (let stringappend_10330 = (string_drop
+                                                    stringappend_10300
+                                                    stringappend_10320) in
+                       (let (rd, stringappend_10350) =
+                            ((case  ((reg_name_matches_prefix
+                                        stringappend_10330 :: (( 5 Word.word * ii)) option)) of
+                                   Some (stringappend_10340,stringappend_10350) =>
+                             (stringappend_10340, stringappend_10350)
+                             )) in
+                       (let stringappend_10360 = (string_drop
+                                                    stringappend_10330
+                                                    stringappend_10350) in
+                       (case 
+                       (case  ((sep_matches_prefix stringappend_10360)) of
+                             Some (stringappend_10370,stringappend_10380) =>
+                       (stringappend_10370, stringappend_10380)
+                       ) of
+                           (_, stringappend_10380) =>
+                       (let stringappend_10390 = (string_drop
+                                                    stringappend_10360
+                                                    stringappend_10380) in
+                       (let (rs1, stringappend_10410) =
+                            ((case  ((hex_bits_5_matches_prefix
+                                        instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                        stringappend_10390 :: (( 5 Word.word * ii)) option)) of
+                                   Some (stringappend_10400,stringappend_10410) =>
+                             (stringappend_10400, stringappend_10410)
+                             )) in
+                       (let stringappend_10420 = (string_drop
+                                                    stringappend_10390
+                                                    stringappend_10410) in
+                       (case 
+                       (case  ((sep_matches_prefix stringappend_10420)) of
+                             Some (stringappend_10430,stringappend_10440) =>
+                       (stringappend_10430, stringappend_10440)
+                       ) of
+                           (_, stringappend_10440) =>
+                       (let stringappend_10450 = (string_drop
+                                                    stringappend_10420
+                                                    stringappend_10440) in
+                       (let (csr, stringappend_10470) =
+                            ((case  ((csr_name_map_matches_prefix
+                                        stringappend_10450 :: (( 12 Word.word * ii)) option)) of
+                                   Some (stringappend_10460,stringappend_10470) =>
+                             (stringappend_10460, stringappend_10470)
+                             )) in
+                       if(((string_drop stringappend_10450 stringappend_10470))
+                            = ('''')) then True else undefined))
+                       ))))
+                       ))))
+                       )))) else
+                       if ((case  ((csr_mnemonic_matches_prefix
+                                      stringappend_5410)) of
+                                 Some (stringappend_10490,stringappend_10500) =>
+                           (let stringappend_10510 = (string_drop
+                                                        stringappend_5410
+                                                        stringappend_10500) in
+                           if ((case  ((spc_matches_prefix stringappend_10510)) of
+                                     Some (stringappend_10520,stringappend_10530) =>
+                               (let stringappend_10540 = (string_drop
+                                                            stringappend_10510
+                                                            stringappend_10530) in
+                               if ((case  ((reg_name_matches_prefix
+                                              stringappend_10540
+                                           :: (( 5 Word.word * ii)) option)) of
+                                         Some (stringappend_10550,stringappend_10560) =>
+                                   (let stringappend_10570 = (string_drop
+                                                                stringappend_10540
+                                                                stringappend_10560) in
+                                   if ((case  ((sep_matches_prefix
+                                                  stringappend_10570)) of
+                                             Some (stringappend_10580,stringappend_10590) =>
+                                       (let stringappend_10600 =
+                                            (string_drop stringappend_10570
+                                               stringappend_10590) in
+                                       if ((case  ((reg_name_matches_prefix
+                                                      stringappend_10600
+                                                   :: (( 5 Word.word * ii)) option)) of
+                                                 Some (stringappend_10610,stringappend_10620) =>
+                                           (let stringappend_10630 =
+                                                (string_drop
+                                                   stringappend_10600
+                                                   stringappend_10620) in
+                                           if ((case  ((sep_matches_prefix
+                                                          stringappend_10630)) of
+                                                     Some (stringappend_10640,stringappend_10650) =>
+                                               (let stringappend_10660 =
+                                                    (string_drop
+                                                       stringappend_10630
+                                                       stringappend_10650) in
+                                               if ((case  ((csr_name_map_matches_prefix
+                                                              stringappend_10660
+                                                           :: (( 12 Word.word * ii)) option)) of
+                                                         Some (stringappend_10670,stringappend_10680) =>
+                                                   if(((string_drop
+                                                          stringappend_10660
+                                                          stringappend_10680))
+                                                        = ('''')) then 
+                                                   True else False
+                                                     | None => False
+                                                   )) then True else 
+                                               False)
+                                                 | None => False
+                                               )) then True else False)
+                                             | None => False
+                                           )) then True else False)
+                                         | None => False
+                                       )) then True else False)
+                                     | None => False
+                                   )) then True else False)
+                                 | None => False
+                               )) then True else False)
+                             | None => False
+                           )) then
+                         (let (op1, stringappend_10500) =
+                              ((case  ((csr_mnemonic_matches_prefix
+                                          stringappend_5410)) of
+                                     Some (stringappend_10490,stringappend_10500) =>
+                               (stringappend_10490, stringappend_10500)
+                               )) in
+                         (let stringappend_10510 = (string_drop
+                                                      stringappend_5410
+                                                      stringappend_10500) in
+                         (case 
+                         (case  ((spc_matches_prefix stringappend_10510)) of
+                               Some (stringappend_10520,stringappend_10530) =>
+                         (stringappend_10520, stringappend_10530)
+                         ) of
+                             (_, stringappend_10530) =>
+                         (let stringappend_10540 = (string_drop
+                                                      stringappend_10510
+                                                      stringappend_10530) in
+                         (let (rd, stringappend_10560) =
+                              ((case  ((reg_name_matches_prefix
+                                          stringappend_10540 :: (( 5 Word.word * ii)) option)) of
+                                     Some (stringappend_10550,stringappend_10560) =>
+                               (stringappend_10550, stringappend_10560)
+                               )) in
+                         (let stringappend_10570 = (string_drop
+                                                      stringappend_10540
+                                                      stringappend_10560) in
+                         (case 
+                         (case  ((sep_matches_prefix stringappend_10570)) of
+                               Some (stringappend_10580,stringappend_10590) =>
+                         (stringappend_10580, stringappend_10590)
+                         ) of
+                             (_, stringappend_10590) =>
+                         (let stringappend_10600 = (string_drop
+                                                      stringappend_10570
+                                                      stringappend_10590) in
+                         (let (rs1, stringappend_10620) =
+                              ((case  ((reg_name_matches_prefix
+                                          stringappend_10600 :: (( 5 Word.word * ii)) option)) of
+                                     Some (stringappend_10610,stringappend_10620) =>
+                               (stringappend_10610, stringappend_10620)
+                               )) in
+                         (let stringappend_10630 = (string_drop
+                                                      stringappend_10600
+                                                      stringappend_10620) in
+                         (case 
+                         (case  ((sep_matches_prefix stringappend_10630)) of
+                               Some (stringappend_10640,stringappend_10650) =>
+                         (stringappend_10640, stringappend_10650)
+                         ) of
+                             (_, stringappend_10650) =>
+                         (let stringappend_10660 = (string_drop
+                                                      stringappend_10630
+                                                      stringappend_10650) in
+                         (let (csr, stringappend_10680) =
+                              ((case  ((csr_name_map_matches_prefix
+                                          stringappend_10660 :: (( 12 Word.word * ii)) option)) of
+                                     Some (stringappend_10670,stringappend_10680) =>
+                               (stringappend_10670, stringappend_10680)
+                               )) in
+                         if(((string_drop stringappend_10660
+                                stringappend_10680)) = ('''')) then True else
+                           undefined))
+                         ))))
+                         ))))
+                         ))) else
+                         if (((((string_startswith stringappend_5410
+                                   (''illegal''))) \<and>
+                                 ((let stringappend_10700 =
+                                       (string_drop stringappend_5410
+                                          ((string_length (''illegal'')))) in
+                                  if ((case  ((spc_matches_prefix
+                                                 stringappend_10700)) of
+                                            Some (stringappend_10710,stringappend_10720) =>
+                                      (let stringappend_10730 =
+                                           (string_drop stringappend_10700
+                                              stringappend_10720) in
+                                      if ((case  ((hex_bits_32_matches_prefix
+                                                     instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                     stringappend_10730
+                                                  :: (( 32 Word.word * ii)) option)) of
+                                                Some (stringappend_10740,stringappend_10750) =>
+                                          if(((string_drop stringappend_10730
+                                                 stringappend_10750)) =
+                                               ('''')) then True else 
+                                          False
+                                            | None => False
+                                          )) then True else False)
+                                        | None => False
+                                      )) then True else False))))) then
+                           (let stringappend_10700 = (string_drop
+                                                        stringappend_5410
+                                                        ((string_length
+                                                            (''illegal'')))) in
+                           (case 
+                           (case  ((spc_matches_prefix stringappend_10700)) of
+                                 Some (stringappend_10710,stringappend_10720) =>
+                           (stringappend_10710, stringappend_10720)
+                           ) of
+                               (_, stringappend_10720) =>
+                           (let stringappend_10730 = (string_drop
+                                                        stringappend_10700
+                                                        stringappend_10720) in
+                           (let (s, stringappend_10750) =
+                                ((case  ((hex_bits_32_matches_prefix
+                                            instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                            stringappend_10730 :: (( 32 Word.word * ii)) option)) of
+                                       Some (stringappend_10740,stringappend_10750) =>
+                                 (stringappend_10740, stringappend_10750)
+                                 )) in
+                           if(((string_drop stringappend_10730
+                                  stringappend_10750)) = ('''')) then 
+                           True else undefined))
+                           )) else False))))))))"
+
+
+(*val assembly_matches_prefix : string -> maybe ((ast * ii))*)
+
+definition assembly_matches_prefix  :: " string \<Rightarrow>(ast*int)option "  where 
+     " assembly_matches_prefix arg0 = (
+   (let stringappend_00 = arg0 in
+   if ((case  ((utype_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_10,stringappend_20) =>
+        (let stringappend_30 = (string_drop stringappend_00 stringappend_20) in
+        if ((case  ((spc_matches_prefix stringappend_30)) of
+            Some (stringappend_40,stringappend_50) =>
+             (let stringappend_60 = (string_drop stringappend_30 stringappend_50) in
+             if ((case  ((reg_name_matches_prefix stringappend_60  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_70,stringappend_80) =>
+                  (let stringappend_90 = (string_drop stringappend_60 stringappend_80) in
+                  if ((case  ((sep_matches_prefix stringappend_90)) of
+                      Some (stringappend_100,stringappend_110) =>
+                       (let stringappend_120 = (string_drop stringappend_90 stringappend_110) in
+                       if ((case  ((hex_bits_20_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_120
+                                    ::  (( 20 Word.word * ii))option)) of
+                           Some (stringappend_130,stringappend_140) => 
+  (case  ((string_drop stringappend_120 stringappend_140)) of   s0 => True )
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_20) =
+       ((case  ((utype_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_10,stringappend_20) => (stringappend_10, stringappend_20)
+       )) in
+     (let stringappend_30 = (string_drop stringappend_00 stringappend_20) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_30)) of
+        Some (stringappend_40,stringappend_50) => (stringappend_40, stringappend_50)
+  ) of
+      (_, stringappend_50) =>
+  (let stringappend_60 = (string_drop stringappend_30 stringappend_50) in
+  (let (rd, stringappend_80) =
+       ((case  ((reg_name_matches_prefix stringappend_60 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_70,stringappend_80) => (stringappend_70, stringappend_80)
+        )) in
+  (let stringappend_90 = (string_drop stringappend_60 stringappend_80) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_90)) of
+        Some (stringappend_100,stringappend_110) => (stringappend_100, stringappend_110)
+  ) of
+      (_, stringappend_110) =>
+  (let stringappend_120 = (string_drop stringappend_90 stringappend_110) in
+  (let (imm, stringappend_140) =
+       ((case  ((hex_bits_20_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_120 :: (( 20 Word.word * ii)) option)) of
+              Some (stringappend_130,stringappend_140) => (stringappend_130, stringappend_140)
+        )) in
+  (case  ((string_drop stringappend_120 stringappend_140)) of
+        s0 => Some
+                (UTYPE (imm,rd,op1), ((string_length arg0)) -
+                                       ((string_length s0)))
+  )))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_00 (''jal''))) \<and> ((let stringappend_160 = (string_drop stringappend_00 ((string_length (''jal'')))) in
+               if ((case  ((spc_matches_prefix stringappend_160)) of
+                   Some (stringappend_170,stringappend_180) =>
+                    (let stringappend_190 = (string_drop stringappend_160 stringappend_180) in
+                    if ((case  ((reg_name_matches_prefix stringappend_190
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_200,stringappend_210) =>
+                         (let stringappend_220 = (string_drop stringappend_190 stringappend_210) in
+                         if ((case  ((sep_matches_prefix stringappend_220)) of
+                             Some (stringappend_230,stringappend_240) =>
+                              (let stringappend_250 =
+                                (string_drop stringappend_220 stringappend_240) in
+                              if ((case  ((hex_bits_21_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_250
+                                           ::  (( 21 Word.word * ii))option)) of
+                                  Some (stringappend_260,stringappend_270) => 
+  (case  ((string_drop stringappend_250 stringappend_270)) of   s0 => True )
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_160 = (string_drop stringappend_00 ((string_length (''jal'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_160)) of
+        Some (stringappend_170,stringappend_180) => (stringappend_170, stringappend_180)
+  ) of
+      (_, stringappend_180) =>
+  (let stringappend_190 = (string_drop stringappend_160 stringappend_180) in
+  (let (rd, stringappend_210) =
+       ((case  ((reg_name_matches_prefix stringappend_190 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_200,stringappend_210) => (stringappend_200, stringappend_210)
+        )) in
+  (let stringappend_220 = (string_drop stringappend_190 stringappend_210) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_220)) of
+        Some (stringappend_230,stringappend_240) => (stringappend_230, stringappend_240)
+  ) of
+      (_, stringappend_240) =>
+  (let stringappend_250 = (string_drop stringappend_220 stringappend_240) in
+  (let (imm, stringappend_270) =
+       ((case  ((hex_bits_21_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_250 :: (( 21 Word.word * ii)) option)) of
+              Some (stringappend_260,stringappend_270) => (stringappend_260, stringappend_270)
+        )) in
+  (case  ((string_drop stringappend_250 stringappend_270)) of
+        s0 => Some
+                (RISCV_JAL (imm,rd), ((string_length arg0)) -
+                                       ((string_length s0)))
+  )))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_00 (''jalr''))) \<and> ((let stringappend_290 = (string_drop stringappend_00 ((string_length (''jalr'')))) in
+               if ((case  ((spc_matches_prefix stringappend_290)) of
+                   Some (stringappend_300,stringappend_310) =>
+                    (let stringappend_320 = (string_drop stringappend_290 stringappend_310) in
+                    if ((case  ((reg_name_matches_prefix stringappend_320
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_330,stringappend_340) =>
+                         (let stringappend_350 = (string_drop stringappend_320 stringappend_340) in
+                         if ((case  ((sep_matches_prefix stringappend_350)) of
+                             Some (stringappend_360,stringappend_370) =>
+                              (let stringappend_380 =
+                                (string_drop stringappend_350 stringappend_370) in
+                              if ((case  ((reg_name_matches_prefix stringappend_380
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_390,stringappend_400) =>
+                                   (let stringappend_410 =
+                                     (string_drop stringappend_380 stringappend_400) in
+                                   if ((case  ((sep_matches_prefix stringappend_410)) of
+                                       Some (stringappend_420,stringappend_430) =>
+                                        (let stringappend_440 =
+                                          (string_drop stringappend_410 stringappend_430) in
+                                        if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_440
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_450,stringappend_460) => 
+  (case  ((string_drop stringappend_440 stringappend_460)) of   s0 => True )
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_290 = (string_drop stringappend_00 ((string_length (''jalr'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_290)) of
+        Some (stringappend_300,stringappend_310) => (stringappend_300, stringappend_310)
+  ) of
+      (_, stringappend_310) =>
+  (let stringappend_320 = (string_drop stringappend_290 stringappend_310) in
+  (let (rd, stringappend_340) =
+       ((case  ((reg_name_matches_prefix stringappend_320 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_330,stringappend_340) => (stringappend_330, stringappend_340)
+        )) in
+  (let stringappend_350 = (string_drop stringappend_320 stringappend_340) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_350)) of
+        Some (stringappend_360,stringappend_370) => (stringappend_360, stringappend_370)
+  ) of
+      (_, stringappend_370) =>
+  (let stringappend_380 = (string_drop stringappend_350 stringappend_370) in
+  (let (rs1, stringappend_400) =
+       ((case  ((reg_name_matches_prefix stringappend_380 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_390,stringappend_400) => (stringappend_390, stringappend_400)
+        )) in
+  (let stringappend_410 = (string_drop stringappend_380 stringappend_400) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_410)) of
+        Some (stringappend_420,stringappend_430) => (stringappend_420, stringappend_430)
+  ) of
+      (_, stringappend_430) =>
+  (let stringappend_440 = (string_drop stringappend_410 stringappend_430) in
+  (let (imm, stringappend_460) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_440 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_450,stringappend_460) => (stringappend_450, stringappend_460)
+        )) in
+  (case  ((string_drop stringappend_440 stringappend_460)) of
+        s0 =>
+  Some
+    (RISCV_JALR (imm,rs1,rd), ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))
+   else if ((case  ((btype_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_480,stringappend_490) =>
+        (let stringappend_500 = (string_drop stringappend_00 stringappend_490) in
+        if ((case  ((spc_matches_prefix stringappend_500)) of
+            Some (stringappend_510,stringappend_520) =>
+             (let stringappend_530 = (string_drop stringappend_500 stringappend_520) in
+             if ((case  ((reg_name_matches_prefix stringappend_530  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_540,stringappend_550) =>
+                  (let stringappend_560 = (string_drop stringappend_530 stringappend_550) in
+                  if ((case  ((sep_matches_prefix stringappend_560)) of
+                      Some (stringappend_570,stringappend_580) =>
+                       (let stringappend_590 = (string_drop stringappend_560 stringappend_580) in
+                       if ((case  ((reg_name_matches_prefix stringappend_590
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_600,stringappend_610) =>
+                            (let stringappend_620 = (string_drop stringappend_590 stringappend_610) in
+                            if ((case  ((sep_matches_prefix stringappend_620)) of
+                                Some (stringappend_630,stringappend_640) =>
+                                 (let stringappend_650 =
+                                   (string_drop stringappend_620 stringappend_640) in
+                                 if ((case  ((hex_bits_13_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_650
+                                              ::  (( 13 Word.word * ii))option)) of
+                                     Some (stringappend_660,stringappend_670) => 
+  (case  ((string_drop stringappend_650 stringappend_670)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_490) =
+       ((case  ((btype_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_480,stringappend_490) => (stringappend_480, stringappend_490)
+       )) in
+     (let stringappend_500 = (string_drop stringappend_00 stringappend_490) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_500)) of
+        Some (stringappend_510,stringappend_520) => (stringappend_510, stringappend_520)
+  ) of
+      (_, stringappend_520) =>
+  (let stringappend_530 = (string_drop stringappend_500 stringappend_520) in
+  (let (rs1, stringappend_550) =
+       ((case  ((reg_name_matches_prefix stringappend_530 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_540,stringappend_550) => (stringappend_540, stringappend_550)
+        )) in
+  (let stringappend_560 = (string_drop stringappend_530 stringappend_550) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_560)) of
+        Some (stringappend_570,stringappend_580) => (stringappend_570, stringappend_580)
+  ) of
+      (_, stringappend_580) =>
+  (let stringappend_590 = (string_drop stringappend_560 stringappend_580) in
+  (let (rs2, stringappend_610) =
+       ((case  ((reg_name_matches_prefix stringappend_590 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_600,stringappend_610) => (stringappend_600, stringappend_610)
+        )) in
+  (let stringappend_620 = (string_drop stringappend_590 stringappend_610) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_620)) of
+        Some (stringappend_630,stringappend_640) => (stringappend_630, stringappend_640)
+  ) of
+      (_, stringappend_640) =>
+  (let stringappend_650 = (string_drop stringappend_620 stringappend_640) in
+  (let (imm, stringappend_670) =
+       ((case  ((hex_bits_13_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_650 :: (( 13 Word.word * ii)) option)) of
+              Some (stringappend_660,stringappend_670) => (stringappend_660, stringappend_670)
+        )) in
+  (case  ((string_drop stringappend_650 stringappend_670)) of
+        s0 => Some
+                (BTYPE (imm,rs2,rs1,op1), ((string_length arg0)) -
+                                            ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if ((case  ((itype_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_690,stringappend_700) =>
+        (let stringappend_710 = (string_drop stringappend_00 stringappend_700) in
+        if ((case  ((spc_matches_prefix stringappend_710)) of
+            Some (stringappend_720,stringappend_730) =>
+             (let stringappend_740 = (string_drop stringappend_710 stringappend_730) in
+             if ((case  ((reg_name_matches_prefix stringappend_740  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_750,stringappend_760) =>
+                  (let stringappend_770 = (string_drop stringappend_740 stringappend_760) in
+                  if ((case  ((sep_matches_prefix stringappend_770)) of
+                      Some (stringappend_780,stringappend_790) =>
+                       (let stringappend_800 = (string_drop stringappend_770 stringappend_790) in
+                       if ((case  ((reg_name_matches_prefix stringappend_800
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_810,stringappend_820) =>
+                            (let stringappend_830 = (string_drop stringappend_800 stringappend_820) in
+                            if ((case  ((sep_matches_prefix stringappend_830)) of
+                                Some (stringappend_840,stringappend_850) =>
+                                 (let stringappend_860 =
+                                   (string_drop stringappend_830 stringappend_850) in
+                                 if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_860
+                                              ::  (( 12 Word.word * ii))option)) of
+                                     Some (stringappend_870,stringappend_880) => 
+  (case  ((string_drop stringappend_860 stringappend_880)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_700) =
+       ((case  ((itype_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_690,stringappend_700) => (stringappend_690, stringappend_700)
+       )) in
+     (let stringappend_710 = (string_drop stringappend_00 stringappend_700) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_710)) of
+        Some (stringappend_720,stringappend_730) => (stringappend_720, stringappend_730)
+  ) of
+      (_, stringappend_730) =>
+  (let stringappend_740 = (string_drop stringappend_710 stringappend_730) in
+  (let (rd, stringappend_760) =
+       ((case  ((reg_name_matches_prefix stringappend_740 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_750,stringappend_760) => (stringappend_750, stringappend_760)
+        )) in
+  (let stringappend_770 = (string_drop stringappend_740 stringappend_760) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_770)) of
+        Some (stringappend_780,stringappend_790) => (stringappend_780, stringappend_790)
+  ) of
+      (_, stringappend_790) =>
+  (let stringappend_800 = (string_drop stringappend_770 stringappend_790) in
+  (let (rs1, stringappend_820) =
+       ((case  ((reg_name_matches_prefix stringappend_800 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_810,stringappend_820) => (stringappend_810, stringappend_820)
+        )) in
+  (let stringappend_830 = (string_drop stringappend_800 stringappend_820) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_830)) of
+        Some (stringappend_840,stringappend_850) => (stringappend_840, stringappend_850)
+  ) of
+      (_, stringappend_850) =>
+  (let stringappend_860 = (string_drop stringappend_830 stringappend_850) in
+  (let (imm, stringappend_880) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_860 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_870,stringappend_880) => (stringappend_870, stringappend_880)
+        )) in
+  (case  ((string_drop stringappend_860 stringappend_880)) of
+        s0 => Some
+                (ITYPE (imm,rs1,rd,op1), ((string_length arg0)) -
+                                           ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if ((case  ((shiftiop_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_900,stringappend_910) =>
+        (let stringappend_920 = (string_drop stringappend_00 stringappend_910) in
+        if ((case  ((spc_matches_prefix stringappend_920)) of
+            Some (stringappend_930,stringappend_940) =>
+             (let stringappend_950 = (string_drop stringappend_920 stringappend_940) in
+             if ((case  ((reg_name_matches_prefix stringappend_950  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_960,stringappend_970) =>
+                  (let stringappend_980 = (string_drop stringappend_950 stringappend_970) in
+                  if ((case  ((sep_matches_prefix stringappend_980)) of
+                      Some (stringappend_990,stringappend_1000) =>
+                       (let stringappend_1010 = (string_drop stringappend_980 stringappend_1000) in
+                       if ((case  ((reg_name_matches_prefix stringappend_1010
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_1020,stringappend_1030) =>
+                            (let stringappend_1040 =
+                              (string_drop stringappend_1010 stringappend_1030) in
+                            if ((case  ((hex_bits_6_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1040
+                                         ::  (( 6 Word.word * ii))option)) of
+                                Some (stringappend_1050,stringappend_1060) => 
+  (case  ((string_drop stringappend_1040 stringappend_1060)) of   s0 => True )
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_910) =
+       ((case  ((shiftiop_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_900,stringappend_910) => (stringappend_900, stringappend_910)
+       )) in
+     (let stringappend_920 = (string_drop stringappend_00 stringappend_910) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_920)) of
+        Some (stringappend_930,stringappend_940) => (stringappend_930, stringappend_940)
+  ) of
+      (_, stringappend_940) =>
+  (let stringappend_950 = (string_drop stringappend_920 stringappend_940) in
+  (let (rd, stringappend_970) =
+       ((case  ((reg_name_matches_prefix stringappend_950 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_960,stringappend_970) => (stringappend_960, stringappend_970)
+        )) in
+  (let stringappend_980 = (string_drop stringappend_950 stringappend_970) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_980)) of
+        Some (stringappend_990,stringappend_1000) => (stringappend_990, stringappend_1000)
+  ) of
+      (_, stringappend_1000) =>
+  (let stringappend_1010 = (string_drop stringappend_980 stringappend_1000) in
+  (let (rs1, stringappend_1030) =
+       ((case  ((reg_name_matches_prefix stringappend_1010 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1020,stringappend_1030) => (stringappend_1020, stringappend_1030)
+        )) in
+  (let stringappend_1040 = (string_drop stringappend_1010 stringappend_1030) in
+  (let (shamt, stringappend_1060) =
+       ((case  ((hex_bits_6_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_1040 :: (( 6 Word.word * ii)) option)) of
+              Some (stringappend_1050,stringappend_1060) => (stringappend_1050, stringappend_1060)
+        )) in
+  (case  ((string_drop stringappend_1040 stringappend_1060)) of
+        s0 =>
+  Some
+    (SHIFTIOP (shamt,rs1,rd,op1), ((string_length arg0)) -
+                                    ((string_length s0)))
+  )))))
+  ))))
+  )))
+   else if ((case  ((rtype_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_1080,stringappend_1090) =>
+        (let stringappend_1100 = (string_drop stringappend_00 stringappend_1090) in
+        if ((case  ((spc_matches_prefix stringappend_1100)) of
+            Some (stringappend_1110,stringappend_1120) =>
+             (let stringappend_1130 = (string_drop stringappend_1100 stringappend_1120) in
+             if ((case  ((reg_name_matches_prefix stringappend_1130  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_1140,stringappend_1150) =>
+                  (let stringappend_1160 = (string_drop stringappend_1130 stringappend_1150) in
+                  if ((case  ((sep_matches_prefix stringappend_1160)) of
+                      Some (stringappend_1170,stringappend_1180) =>
+                       (let stringappend_1190 = (string_drop stringappend_1160 stringappend_1180) in
+                       if ((case  ((reg_name_matches_prefix stringappend_1190
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_1200,stringappend_1210) =>
+                            (let stringappend_1220 =
+                              (string_drop stringappend_1190 stringappend_1210) in
+                            if ((case  ((sep_matches_prefix stringappend_1220)) of
+                                Some (stringappend_1230,stringappend_1240) =>
+                                 (let stringappend_1250 =
+                                   (string_drop stringappend_1220 stringappend_1240) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_1250
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_1260,stringappend_1270) => 
+  (case  ((string_drop stringappend_1250 stringappend_1270)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_1090) =
+       ((case  ((rtype_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_1080,stringappend_1090) => (stringappend_1080, stringappend_1090)
+       )) in
+     (let stringappend_1100 = (string_drop stringappend_00 stringappend_1090) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_1100)) of
+        Some (stringappend_1110,stringappend_1120) => (stringappend_1110, stringappend_1120)
+  ) of
+      (_, stringappend_1120) =>
+  (let stringappend_1130 = (string_drop stringappend_1100 stringappend_1120) in
+  (let (rd, stringappend_1150) =
+       ((case  ((reg_name_matches_prefix stringappend_1130 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1140,stringappend_1150) => (stringappend_1140, stringappend_1150)
+        )) in
+  (let stringappend_1160 = (string_drop stringappend_1130 stringappend_1150) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1160)) of
+        Some (stringappend_1170,stringappend_1180) => (stringappend_1170, stringappend_1180)
+  ) of
+      (_, stringappend_1180) =>
+  (let stringappend_1190 = (string_drop stringappend_1160 stringappend_1180) in
+  (let (rs1, stringappend_1210) =
+       ((case  ((reg_name_matches_prefix stringappend_1190 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1200,stringappend_1210) => (stringappend_1200, stringappend_1210)
+        )) in
+  (let stringappend_1220 = (string_drop stringappend_1190 stringappend_1210) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1220)) of
+        Some (stringappend_1230,stringappend_1240) => (stringappend_1230, stringappend_1240)
+  ) of
+      (_, stringappend_1240) =>
+  (let stringappend_1250 = (string_drop stringappend_1220 stringappend_1240) in
+  (let (rs2, stringappend_1270) =
+       ((case  ((reg_name_matches_prefix stringappend_1250 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1260,stringappend_1270) => (stringappend_1260, stringappend_1270)
+        )) in
+  (case  ((string_drop stringappend_1250 stringappend_1270)) of
+        s0 => Some
+                (RTYPE (rs2,rs1,rd,op1), ((string_length arg0)) -
+                                           ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_00 (''l''))) \<and> ((let stringappend_1290 = (string_drop stringappend_00 ((string_length (''l'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_1290)) of
+                   Some (stringappend_1300,stringappend_1310) =>
+                    (let stringappend_1320 = (string_drop stringappend_1290 stringappend_1310) in
+                    if ((case  ((maybe_u_matches_prefix stringappend_1320)) of
+                        Some (stringappend_1330,stringappend_1340) =>
+                         (let stringappend_1350 = (string_drop stringappend_1320 stringappend_1340) in
+                         if ((case  ((maybe_aq_matches_prefix stringappend_1350)) of
+                             Some (stringappend_1360,stringappend_1370) =>
+                              (let stringappend_1380 =
+                                (string_drop stringappend_1350 stringappend_1370) in
+                              if ((case  ((maybe_rl_matches_prefix stringappend_1380)) of
+                                  Some (stringappend_1390,stringappend_1400) =>
+                                   (let stringappend_1410 =
+                                     (string_drop stringappend_1380 stringappend_1400) in
+                                   if ((case  ((spc_matches_prefix stringappend_1410)) of
+                                       Some (stringappend_1420,stringappend_1430) =>
+                                        (let stringappend_1440 =
+                                          (string_drop stringappend_1410 stringappend_1430) in
+                                        if ((case  ((reg_name_matches_prefix stringappend_1440
+                                                     ::  (( 5 Word.word * ii))option)) of
+                                            Some (stringappend_1450,stringappend_1460) =>
+                                             (let stringappend_1470 =
+                                               (string_drop stringappend_1440 stringappend_1460) in
+                                             if ((case  ((sep_matches_prefix stringappend_1470)) of
+                                                 Some (stringappend_1480,stringappend_1490) =>
+                                                  (let stringappend_1500 =
+                                                    (string_drop stringappend_1470
+                                                      stringappend_1490) in
+                                                  if ((case  ((reg_name_matches_prefix
+                                                                stringappend_1500
+                                                               ::  (( 5 Word.word * ii))option)) of
+                                                      Some (stringappend_1510,stringappend_1520) =>
+                                                       (let stringappend_1530 =
+                                                         (string_drop stringappend_1500
+                                                           stringappend_1520) in
+                                                       if ((case  ((sep_matches_prefix
+                                                                     stringappend_1530)) of
+                                                           Some
+                                                           (stringappend_1540,stringappend_1550) =>
+                                                            (let stringappend_1560 =
+                                                              (string_drop stringappend_1530
+                                                                stringappend_1550) in
+                                                            if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                          stringappend_1560
+                                                                         ::  (( 12 Word.word * ii))option)) of
+                                                                Some
+                                                                (stringappend_1570,stringappend_1580) => 
+  (case  ((string_drop stringappend_1560 stringappend_1580)) of   s0 => True )
+                                                              | None => False
+                                                              )) then
+                                                              True
+                                                            else False)
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_1290 = (string_drop stringappend_00 ((string_length (''l'')))) in
+     (let (size1, stringappend_1310) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_1290)) of
+         Some (stringappend_1300,stringappend_1310) => (stringappend_1300, stringappend_1310)
+       )) in
+     (let stringappend_1320 = (string_drop stringappend_1290 stringappend_1310) in
+     (let (is_unsigned, stringappend_1340) =
+       ((case  ((maybe_u_matches_prefix stringappend_1320)) of
+         Some (stringappend_1330,stringappend_1340) => (stringappend_1330, stringappend_1340)
+       )) in
+     (let stringappend_1350 = (string_drop stringappend_1320 stringappend_1340) in
+     (let (aq, stringappend_1370) =
+       ((case  ((maybe_aq_matches_prefix stringappend_1350)) of
+         Some (stringappend_1360,stringappend_1370) => (stringappend_1360, stringappend_1370)
+       )) in
+     (let stringappend_1380 = (string_drop stringappend_1350 stringappend_1370) in
+     (let (rl, stringappend_1400) =
+       ((case  ((maybe_rl_matches_prefix stringappend_1380)) of
+         Some (stringappend_1390,stringappend_1400) => (stringappend_1390, stringappend_1400)
+       )) in
+     (let stringappend_1410 = (string_drop stringappend_1380 stringappend_1400) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_1410)) of
+        Some (stringappend_1420,stringappend_1430) => (stringappend_1420, stringappend_1430)
+  ) of
+      (_, stringappend_1430) =>
+  (let stringappend_1440 = (string_drop stringappend_1410 stringappend_1430) in
+  (let (rd, stringappend_1460) =
+       ((case  ((reg_name_matches_prefix stringappend_1440 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1450,stringappend_1460) => (stringappend_1450, stringappend_1460)
+        )) in
+  (let stringappend_1470 = (string_drop stringappend_1440 stringappend_1460) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1470)) of
+        Some (stringappend_1480,stringappend_1490) => (stringappend_1480, stringappend_1490)
+  ) of
+      (_, stringappend_1490) =>
+  (let stringappend_1500 = (string_drop stringappend_1470 stringappend_1490) in
+  (let (rs1, stringappend_1520) =
+       ((case  ((reg_name_matches_prefix stringappend_1500 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1510,stringappend_1520) => (stringappend_1510, stringappend_1520)
+        )) in
+  (let stringappend_1530 = (string_drop stringappend_1500 stringappend_1520) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1530)) of
+        Some (stringappend_1540,stringappend_1550) => (stringappend_1540, stringappend_1550)
+  ) of
+      (_, stringappend_1550) =>
+  (let stringappend_1560 = (string_drop stringappend_1530 stringappend_1550) in
+  (let (imm, stringappend_1580) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_1560 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_1570,stringappend_1580) => (stringappend_1570, stringappend_1580)
+        )) in
+  (case  ((string_drop stringappend_1560 stringappend_1580)) of
+        s0 =>
+  Some
+    (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl),
+    ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))))))))))
+   else if (((((string_startswith stringappend_00 (''s''))) \<and> ((let stringappend_1600 = (string_drop stringappend_00 ((string_length (''s'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_1600)) of
+                   Some (stringappend_1610,stringappend_1620) =>
+                    (let stringappend_1630 = (string_drop stringappend_1600 stringappend_1620) in
+                    if ((case  ((maybe_aq_matches_prefix stringappend_1630)) of
+                        Some (stringappend_1640,stringappend_1650) =>
+                         (let stringappend_1660 = (string_drop stringappend_1630 stringappend_1650) in
+                         if ((case  ((maybe_rl_matches_prefix stringappend_1660)) of
+                             Some (stringappend_1670,stringappend_1680) =>
+                              (let stringappend_1690 =
+                                (string_drop stringappend_1660 stringappend_1680) in
+                              if ((case  ((spc_matches_prefix stringappend_1690)) of
+                                  Some (stringappend_1700,stringappend_1710) =>
+                                   (let stringappend_1720 =
+                                     (string_drop stringappend_1690 stringappend_1710) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_1720
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_1730,stringappend_1740) =>
+                                        (let stringappend_1750 =
+                                          (string_drop stringappend_1720 stringappend_1740) in
+                                        if ((case  ((sep_matches_prefix stringappend_1750)) of
+                                            Some (stringappend_1760,stringappend_1770) =>
+                                             (let stringappend_1780 =
+                                               (string_drop stringappend_1750 stringappend_1770) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_1780
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_1790,stringappend_1800) =>
+                                                  (let stringappend_1810 =
+                                                    (string_drop stringappend_1780
+                                                      stringappend_1800) in
+                                                  if ((case  ((sep_matches_prefix stringappend_1810)) of
+                                                      Some (stringappend_1820,stringappend_1830) =>
+                                                       (let stringappend_1840 =
+                                                         (string_drop stringappend_1810
+                                                           stringappend_1830) in
+                                                       if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                                                                     stringappend_1840
+                                                                    ::  (( 12 Word.word * ii))option)) of
+                                                           Some
+                                                           (stringappend_1850,stringappend_1860) => 
+  (case  ((string_drop stringappend_1840 stringappend_1860)) of   s0 => True )
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_1600 = (string_drop stringappend_00 ((string_length (''s'')))) in
+     (let (size1, stringappend_1620) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_1600)) of
+         Some (stringappend_1610,stringappend_1620) => (stringappend_1610, stringappend_1620)
+       )) in
+     (let stringappend_1630 = (string_drop stringappend_1600 stringappend_1620) in
+     (let (aq, stringappend_1650) =
+       ((case  ((maybe_aq_matches_prefix stringappend_1630)) of
+         Some (stringappend_1640,stringappend_1650) => (stringappend_1640, stringappend_1650)
+       )) in
+     (let stringappend_1660 = (string_drop stringappend_1630 stringappend_1650) in
+     (let (rl, stringappend_1680) =
+       ((case  ((maybe_rl_matches_prefix stringappend_1660)) of
+         Some (stringappend_1670,stringappend_1680) => (stringappend_1670, stringappend_1680)
+       )) in
+     (let stringappend_1690 = (string_drop stringappend_1660 stringappend_1680) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_1690)) of
+        Some (stringappend_1700,stringappend_1710) => (stringappend_1700, stringappend_1710)
+  ) of
+      (_, stringappend_1710) =>
+  (let stringappend_1720 = (string_drop stringappend_1690 stringappend_1710) in
+  (let (rd, stringappend_1740) =
+       ((case  ((reg_name_matches_prefix stringappend_1720 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1730,stringappend_1740) => (stringappend_1730, stringappend_1740)
+        )) in
+  (let stringappend_1750 = (string_drop stringappend_1720 stringappend_1740) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1750)) of
+        Some (stringappend_1760,stringappend_1770) => (stringappend_1760, stringappend_1770)
+  ) of
+      (_, stringappend_1770) =>
+  (let stringappend_1780 = (string_drop stringappend_1750 stringappend_1770) in
+  (let (rs1, stringappend_1800) =
+       ((case  ((reg_name_matches_prefix stringappend_1780 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1790,stringappend_1800) => (stringappend_1790, stringappend_1800)
+        )) in
+  (let stringappend_1810 = (string_drop stringappend_1780 stringappend_1800) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1810)) of
+        Some (stringappend_1820,stringappend_1830) => (stringappend_1820, stringappend_1830)
+  ) of
+      (_, stringappend_1830) =>
+  (let stringappend_1840 = (string_drop stringappend_1810 stringappend_1830) in
+  (let (imm, stringappend_1860) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_1840 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_1850,stringappend_1860) => (stringappend_1850, stringappend_1860)
+        )) in
+  (case  ((string_drop stringappend_1840 stringappend_1860)) of
+        s0 =>
+  Some
+    (STORE (imm,rs1,rd,size1,aq,rl),
+    ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))))))))
+   else if (((((string_startswith stringappend_00 (''addiw''))) \<and> ((let stringappend_1880 = (string_drop stringappend_00 ((string_length (''addiw'')))) in
+               if ((case  ((spc_matches_prefix stringappend_1880)) of
+                   Some (stringappend_1890,stringappend_1900) =>
+                    (let stringappend_1910 = (string_drop stringappend_1880 stringappend_1900) in
+                    if ((case  ((reg_name_matches_prefix stringappend_1910
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_1920,stringappend_1930) =>
+                         (let stringappend_1940 = (string_drop stringappend_1910 stringappend_1930) in
+                         if ((case  ((sep_matches_prefix stringappend_1940)) of
+                             Some (stringappend_1950,stringappend_1960) =>
+                              (let stringappend_1970 =
+                                (string_drop stringappend_1940 stringappend_1960) in
+                              if ((case  ((reg_name_matches_prefix stringappend_1970
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_1980,stringappend_1990) =>
+                                   (let stringappend_2000 =
+                                     (string_drop stringappend_1970 stringappend_1990) in
+                                   if ((case  ((sep_matches_prefix stringappend_2000)) of
+                                       Some (stringappend_2010,stringappend_2020) =>
+                                        (let stringappend_2030 =
+                                          (string_drop stringappend_2000 stringappend_2020) in
+                                        if ((case  ((hex_bits_12_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_2030
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_2040,stringappend_2050) => 
+  (case  ((string_drop stringappend_2030 stringappend_2050)) of   s0 => True )
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_1880 = (string_drop stringappend_00 ((string_length (''addiw'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_1880)) of
+        Some (stringappend_1890,stringappend_1900) => (stringappend_1890, stringappend_1900)
+  ) of
+      (_, stringappend_1900) =>
+  (let stringappend_1910 = (string_drop stringappend_1880 stringappend_1900) in
+  (let (rd, stringappend_1930) =
+       ((case  ((reg_name_matches_prefix stringappend_1910 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1920,stringappend_1930) => (stringappend_1920, stringappend_1930)
+        )) in
+  (let stringappend_1940 = (string_drop stringappend_1910 stringappend_1930) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_1940)) of
+        Some (stringappend_1950,stringappend_1960) => (stringappend_1950, stringappend_1960)
+  ) of
+      (_, stringappend_1960) =>
+  (let stringappend_1970 = (string_drop stringappend_1940 stringappend_1960) in
+  (let (rs1, stringappend_1990) =
+       ((case  ((reg_name_matches_prefix stringappend_1970 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_1980,stringappend_1990) => (stringappend_1980, stringappend_1990)
+        )) in
+  (let stringappend_2000 = (string_drop stringappend_1970 stringappend_1990) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2000)) of
+        Some (stringappend_2010,stringappend_2020) => (stringappend_2010, stringappend_2020)
+  ) of
+      (_, stringappend_2020) =>
+  (let stringappend_2030 = (string_drop stringappend_2000 stringappend_2020) in
+  (let (imm, stringappend_2050) =
+       ((case  ((hex_bits_12_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_2030 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_2040,stringappend_2050) => (stringappend_2040, stringappend_2050)
+        )) in
+  (case  ((string_drop stringappend_2030 stringappend_2050)) of
+        s0 => Some
+                (ADDIW (imm,rs1,rd), ((string_length arg0)) -
+                                       ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))
+   else if ((case  ((shiftw_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_2070,stringappend_2080) =>
+        (let stringappend_2090 = (string_drop stringappend_00 stringappend_2080) in
+        if ((case  ((spc_matches_prefix stringappend_2090)) of
+            Some (stringappend_2100,stringappend_2110) =>
+             (let stringappend_2120 = (string_drop stringappend_2090 stringappend_2110) in
+             if ((case  ((reg_name_matches_prefix stringappend_2120  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_2130,stringappend_2140) =>
+                  (let stringappend_2150 = (string_drop stringappend_2120 stringappend_2140) in
+                  if ((case  ((sep_matches_prefix stringappend_2150)) of
+                      Some (stringappend_2160,stringappend_2170) =>
+                       (let stringappend_2180 = (string_drop stringappend_2150 stringappend_2170) in
+                       if ((case  ((reg_name_matches_prefix stringappend_2180
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_2190,stringappend_2200) =>
+                            (let stringappend_2210 =
+                              (string_drop stringappend_2180 stringappend_2200) in
+                            if ((case  ((sep_matches_prefix stringappend_2210)) of
+                                Some (stringappend_2220,stringappend_2230) =>
+                                 (let stringappend_2240 =
+                                   (string_drop stringappend_2210 stringappend_2230) in
+                                 if ((case  ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_2240
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_2250,stringappend_2260) => 
+  (case  ((string_drop stringappend_2240 stringappend_2260)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_2080) =
+       ((case  ((shiftw_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_2070,stringappend_2080) => (stringappend_2070, stringappend_2080)
+       )) in
+     (let stringappend_2090 = (string_drop stringappend_00 stringappend_2080) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_2090)) of
+        Some (stringappend_2100,stringappend_2110) => (stringappend_2100, stringappend_2110)
+  ) of
+      (_, stringappend_2110) =>
+  (let stringappend_2120 = (string_drop stringappend_2090 stringappend_2110) in
+  (let (rd, stringappend_2140) =
+       ((case  ((reg_name_matches_prefix stringappend_2120 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2130,stringappend_2140) => (stringappend_2130, stringappend_2140)
+        )) in
+  (let stringappend_2150 = (string_drop stringappend_2120 stringappend_2140) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2150)) of
+        Some (stringappend_2160,stringappend_2170) => (stringappend_2160, stringappend_2170)
+  ) of
+      (_, stringappend_2170) =>
+  (let stringappend_2180 = (string_drop stringappend_2150 stringappend_2170) in
+  (let (rs1, stringappend_2200) =
+       ((case  ((reg_name_matches_prefix stringappend_2180 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2190,stringappend_2200) => (stringappend_2190, stringappend_2200)
+        )) in
+  (let stringappend_2210 = (string_drop stringappend_2180 stringappend_2200) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2210)) of
+        Some (stringappend_2220,stringappend_2230) => (stringappend_2220, stringappend_2230)
+  ) of
+      (_, stringappend_2230) =>
+  (let stringappend_2240 = (string_drop stringappend_2210 stringappend_2230) in
+  (let (shamt, stringappend_2260) =
+       ((case  ((hex_bits_5_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_2240 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2250,stringappend_2260) => (stringappend_2250, stringappend_2260)
+        )) in
+  (case  ((string_drop stringappend_2240 stringappend_2260)) of
+        s0 =>
+  Some
+    (SHIFTW (shamt,rs1,rd,op1), ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if ((case  ((rtypew_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_2280,stringappend_2290) =>
+        (let stringappend_2300 = (string_drop stringappend_00 stringappend_2290) in
+        if ((case  ((spc_matches_prefix stringappend_2300)) of
+            Some (stringappend_2310,stringappend_2320) =>
+             (let stringappend_2330 = (string_drop stringappend_2300 stringappend_2320) in
+             if ((case  ((reg_name_matches_prefix stringappend_2330  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_2340,stringappend_2350) =>
+                  (let stringappend_2360 = (string_drop stringappend_2330 stringappend_2350) in
+                  if ((case  ((sep_matches_prefix stringappend_2360)) of
+                      Some (stringappend_2370,stringappend_2380) =>
+                       (let stringappend_2390 = (string_drop stringappend_2360 stringappend_2380) in
+                       if ((case  ((reg_name_matches_prefix stringappend_2390
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_2400,stringappend_2410) =>
+                            (let stringappend_2420 =
+                              (string_drop stringappend_2390 stringappend_2410) in
+                            if ((case  ((sep_matches_prefix stringappend_2420)) of
+                                Some (stringappend_2430,stringappend_2440) =>
+                                 (let stringappend_2450 =
+                                   (string_drop stringappend_2420 stringappend_2440) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_2450
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_2460,stringappend_2470) => 
+  (case  ((string_drop stringappend_2450 stringappend_2470)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_2290) =
+       ((case  ((rtypew_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_2280,stringappend_2290) => (stringappend_2280, stringappend_2290)
+       )) in
+     (let stringappend_2300 = (string_drop stringappend_00 stringappend_2290) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_2300)) of
+        Some (stringappend_2310,stringappend_2320) => (stringappend_2310, stringappend_2320)
+  ) of
+      (_, stringappend_2320) =>
+  (let stringappend_2330 = (string_drop stringappend_2300 stringappend_2320) in
+  (let (rd, stringappend_2350) =
+       ((case  ((reg_name_matches_prefix stringappend_2330 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2340,stringappend_2350) => (stringappend_2340, stringappend_2350)
+        )) in
+  (let stringappend_2360 = (string_drop stringappend_2330 stringappend_2350) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2360)) of
+        Some (stringappend_2370,stringappend_2380) => (stringappend_2370, stringappend_2380)
+  ) of
+      (_, stringappend_2380) =>
+  (let stringappend_2390 = (string_drop stringappend_2360 stringappend_2380) in
+  (let (rs1, stringappend_2410) =
+       ((case  ((reg_name_matches_prefix stringappend_2390 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2400,stringappend_2410) => (stringappend_2400, stringappend_2410)
+        )) in
+  (let stringappend_2420 = (string_drop stringappend_2390 stringappend_2410) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2420)) of
+        Some (stringappend_2430,stringappend_2440) => (stringappend_2430, stringappend_2440)
+  ) of
+      (_, stringappend_2440) =>
+  (let stringappend_2450 = (string_drop stringappend_2420 stringappend_2440) in
+  (let (rs2, stringappend_2470) =
+       ((case  ((reg_name_matches_prefix stringappend_2450 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2460,stringappend_2470) => (stringappend_2460, stringappend_2470)
+        )) in
+  (case  ((string_drop stringappend_2450 stringappend_2470)) of
+        s0 => Some
+                (RTYPEW (rs2,rs1,rd,op1), ((string_length arg0)) -
+                                            ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if ((case  ((mul_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_2490,stringappend_2500) =>
+        (let stringappend_2510 = (string_drop stringappend_00 stringappend_2500) in
+        if ((case  ((spc_matches_prefix stringappend_2510)) of
+            Some (stringappend_2520,stringappend_2530) =>
+             (let stringappend_2540 = (string_drop stringappend_2510 stringappend_2530) in
+             if ((case  ((reg_name_matches_prefix stringappend_2540  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_2550,stringappend_2560) =>
+                  (let stringappend_2570 = (string_drop stringappend_2540 stringappend_2560) in
+                  if ((case  ((sep_matches_prefix stringappend_2570)) of
+                      Some (stringappend_2580,stringappend_2590) =>
+                       (let stringappend_2600 = (string_drop stringappend_2570 stringappend_2590) in
+                       if ((case  ((reg_name_matches_prefix stringappend_2600
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_2610,stringappend_2620) =>
+                            (let stringappend_2630 =
+                              (string_drop stringappend_2600 stringappend_2620) in
+                            if ((case  ((sep_matches_prefix stringappend_2630)) of
+                                Some (stringappend_2640,stringappend_2650) =>
+                                 (let stringappend_2660 =
+                                   (string_drop stringappend_2630 stringappend_2650) in
+                                 if ((case  ((reg_name_matches_prefix stringappend_2660
+                                              ::  (( 5 Word.word * ii))option)) of
+                                     Some (stringappend_2670,stringappend_2680) => 
+  (case  ((string_drop stringappend_2660 stringappend_2680)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let ((high, signed1, signed2), stringappend_2500) =
+       ((case  ((mul_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_2490,stringappend_2500) => (stringappend_2490, stringappend_2500)
+       )) in
+     (let stringappend_2510 = (string_drop stringappend_00 stringappend_2500) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_2510)) of
+        Some (stringappend_2520,stringappend_2530) => (stringappend_2520, stringappend_2530)
+  ) of
+      (_, stringappend_2530) =>
+  (let stringappend_2540 = (string_drop stringappend_2510 stringappend_2530) in
+  (let (rd, stringappend_2560) =
+       ((case  ((reg_name_matches_prefix stringappend_2540 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2550,stringappend_2560) => (stringappend_2550, stringappend_2560)
+        )) in
+  (let stringappend_2570 = (string_drop stringappend_2540 stringappend_2560) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2570)) of
+        Some (stringappend_2580,stringappend_2590) => (stringappend_2580, stringappend_2590)
+  ) of
+      (_, stringappend_2590) =>
+  (let stringappend_2600 = (string_drop stringappend_2570 stringappend_2590) in
+  (let (rs1, stringappend_2620) =
+       ((case  ((reg_name_matches_prefix stringappend_2600 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2610,stringappend_2620) => (stringappend_2610, stringappend_2620)
+        )) in
+  (let stringappend_2630 = (string_drop stringappend_2600 stringappend_2620) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2630)) of
+        Some (stringappend_2640,stringappend_2650) => (stringappend_2640, stringappend_2650)
+  ) of
+      (_, stringappend_2650) =>
+  (let stringappend_2660 = (string_drop stringappend_2630 stringappend_2650) in
+  (let (rs2, stringappend_2680) =
+       ((case  ((reg_name_matches_prefix stringappend_2660 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2670,stringappend_2680) => (stringappend_2670, stringappend_2680)
+        )) in
+  (case  ((string_drop stringappend_2660 stringappend_2680)) of
+        s0 =>
+  Some
+    (MUL (rs2,rs1,rd,high,signed1,signed2),
+    ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_00 (''div''))) \<and> ((let stringappend_2700 = (string_drop stringappend_00 ((string_length (''div'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_2700)) of
+                   Some (stringappend_2710,stringappend_2720) =>
+                    (let stringappend_2730 = (string_drop stringappend_2700 stringappend_2720) in
+                    if ((case  ((spc_matches_prefix stringappend_2730)) of
+                        Some (stringappend_2740,stringappend_2750) =>
+                         (let stringappend_2760 = (string_drop stringappend_2730 stringappend_2750) in
+                         if ((case  ((reg_name_matches_prefix stringappend_2760
+                                      ::  (( 5 Word.word * ii))option)) of
+                             Some (stringappend_2770,stringappend_2780) =>
+                              (let stringappend_2790 =
+                                (string_drop stringappend_2760 stringappend_2780) in
+                              if ((case  ((sep_matches_prefix stringappend_2790)) of
+                                  Some (stringappend_2800,stringappend_2810) =>
+                                   (let stringappend_2820 =
+                                     (string_drop stringappend_2790 stringappend_2810) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_2820
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_2830,stringappend_2840) =>
+                                        (let stringappend_2850 =
+                                          (string_drop stringappend_2820 stringappend_2840) in
+                                        if ((case  ((sep_matches_prefix stringappend_2850)) of
+                                            Some (stringappend_2860,stringappend_2870) =>
+                                             (let stringappend_2880 =
+                                               (string_drop stringappend_2850 stringappend_2870) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_2880
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_2890,stringappend_2900) => 
+  (case  ((string_drop stringappend_2880 stringappend_2900)) of   s0 => True )
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_2700 = (string_drop stringappend_00 ((string_length (''div'')))) in
+     (let (s, stringappend_2720) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_2700)) of
+         Some (stringappend_2710,stringappend_2720) => (stringappend_2710, stringappend_2720)
+       )) in
+     (let stringappend_2730 = (string_drop stringappend_2700 stringappend_2720) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_2730)) of
+        Some (stringappend_2740,stringappend_2750) => (stringappend_2740, stringappend_2750)
+  ) of
+      (_, stringappend_2750) =>
+  (let stringappend_2760 = (string_drop stringappend_2730 stringappend_2750) in
+  (let (rd, stringappend_2780) =
+       ((case  ((reg_name_matches_prefix stringappend_2760 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2770,stringappend_2780) => (stringappend_2770, stringappend_2780)
+        )) in
+  (let stringappend_2790 = (string_drop stringappend_2760 stringappend_2780) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2790)) of
+        Some (stringappend_2800,stringappend_2810) => (stringappend_2800, stringappend_2810)
+  ) of
+      (_, stringappend_2810) =>
+  (let stringappend_2820 = (string_drop stringappend_2790 stringappend_2810) in
+  (let (rs1, stringappend_2840) =
+       ((case  ((reg_name_matches_prefix stringappend_2820 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2830,stringappend_2840) => (stringappend_2830, stringappend_2840)
+        )) in
+  (let stringappend_2850 = (string_drop stringappend_2820 stringappend_2840) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_2850)) of
+        Some (stringappend_2860,stringappend_2870) => (stringappend_2860, stringappend_2870)
+  ) of
+      (_, stringappend_2870) =>
+  (let stringappend_2880 = (string_drop stringappend_2850 stringappend_2870) in
+  (let (rs2, stringappend_2900) =
+       ((case  ((reg_name_matches_prefix stringappend_2880 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2890,stringappend_2900) => (stringappend_2890, stringappend_2900)
+        )) in
+  (case  ((string_drop stringappend_2880 stringappend_2900)) of
+        s1 => Some
+                (DIV (rs2,rs1,rd,s), ((string_length arg0)) -
+                                       ((string_length s1)))
+  )))
+  ))))
+  ))))
+  ))))
+   else if (((((string_startswith stringappend_00 (''rem''))) \<and> ((let stringappend_2920 = (string_drop stringappend_00 ((string_length (''rem'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_2920)) of
+                   Some (stringappend_2930,stringappend_2940) =>
+                    (let stringappend_2950 = (string_drop stringappend_2920 stringappend_2940) in
+                    if ((case  ((spc_matches_prefix stringappend_2950)) of
+                        Some (stringappend_2960,stringappend_2970) =>
+                         (let stringappend_2980 = (string_drop stringappend_2950 stringappend_2970) in
+                         if ((case  ((reg_name_matches_prefix stringappend_2980
+                                      ::  (( 5 Word.word * ii))option)) of
+                             Some (stringappend_2990,stringappend_3000) =>
+                              (let stringappend_3010 =
+                                (string_drop stringappend_2980 stringappend_3000) in
+                              if ((case  ((sep_matches_prefix stringappend_3010)) of
+                                  Some (stringappend_3020,stringappend_3030) =>
+                                   (let stringappend_3040 =
+                                     (string_drop stringappend_3010 stringappend_3030) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_3040
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_3050,stringappend_3060) =>
+                                        (let stringappend_3070 =
+                                          (string_drop stringappend_3040 stringappend_3060) in
+                                        if ((case  ((sep_matches_prefix stringappend_3070)) of
+                                            Some (stringappend_3080,stringappend_3090) =>
+                                             (let stringappend_3100 =
+                                               (string_drop stringappend_3070 stringappend_3090) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_3100
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_3110,stringappend_3120) => 
+  (case  ((string_drop stringappend_3100 stringappend_3120)) of   s0 => True )
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_2920 = (string_drop stringappend_00 ((string_length (''rem'')))) in
+     (let (s, stringappend_2940) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_2920)) of
+         Some (stringappend_2930,stringappend_2940) => (stringappend_2930, stringappend_2940)
+       )) in
+     (let stringappend_2950 = (string_drop stringappend_2920 stringappend_2940) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_2950)) of
+        Some (stringappend_2960,stringappend_2970) => (stringappend_2960, stringappend_2970)
+  ) of
+      (_, stringappend_2970) =>
+  (let stringappend_2980 = (string_drop stringappend_2950 stringappend_2970) in
+  (let (rd, stringappend_3000) =
+       ((case  ((reg_name_matches_prefix stringappend_2980 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_2990,stringappend_3000) => (stringappend_2990, stringappend_3000)
+        )) in
+  (let stringappend_3010 = (string_drop stringappend_2980 stringappend_3000) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3010)) of
+        Some (stringappend_3020,stringappend_3030) => (stringappend_3020, stringappend_3030)
+  ) of
+      (_, stringappend_3030) =>
+  (let stringappend_3040 = (string_drop stringappend_3010 stringappend_3030) in
+  (let (rs1, stringappend_3060) =
+       ((case  ((reg_name_matches_prefix stringappend_3040 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3050,stringappend_3060) => (stringappend_3050, stringappend_3060)
+        )) in
+  (let stringappend_3070 = (string_drop stringappend_3040 stringappend_3060) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3070)) of
+        Some (stringappend_3080,stringappend_3090) => (stringappend_3080, stringappend_3090)
+  ) of
+      (_, stringappend_3090) =>
+  (let stringappend_3100 = (string_drop stringappend_3070 stringappend_3090) in
+  (let (rs2, stringappend_3120) =
+       ((case  ((reg_name_matches_prefix stringappend_3100 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3110,stringappend_3120) => (stringappend_3110, stringappend_3120)
+        )) in
+  (case  ((string_drop stringappend_3100 stringappend_3120)) of
+        s1 => Some
+                (REM (rs2,rs1,rd,s), ((string_length arg0)) -
+                                       ((string_length s1)))
+  )))
+  ))))
+  ))))
+  ))))
+   else if (((((string_startswith stringappend_00 (''mulw''))) \<and> ((let stringappend_3140 = (string_drop stringappend_00 ((string_length (''mulw'')))) in
+               if ((case  ((spc_matches_prefix stringappend_3140)) of
+                   Some (stringappend_3150,stringappend_3160) =>
+                    (let stringappend_3170 = (string_drop stringappend_3140 stringappend_3160) in
+                    if ((case  ((reg_name_matches_prefix stringappend_3170
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_3180,stringappend_3190) =>
+                         (let stringappend_3200 = (string_drop stringappend_3170 stringappend_3190) in
+                         if ((case  ((sep_matches_prefix stringappend_3200)) of
+                             Some (stringappend_3210,stringappend_3220) =>
+                              (let stringappend_3230 =
+                                (string_drop stringappend_3200 stringappend_3220) in
+                              if ((case  ((reg_name_matches_prefix stringappend_3230
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_3240,stringappend_3250) =>
+                                   (let stringappend_3260 =
+                                     (string_drop stringappend_3230 stringappend_3250) in
+                                   if ((case  ((sep_matches_prefix stringappend_3260)) of
+                                       Some (stringappend_3270,stringappend_3280) =>
+                                        (let stringappend_3290 =
+                                          (string_drop stringappend_3260 stringappend_3280) in
+                                        if ((case  ((reg_name_matches_prefix stringappend_3290
+                                                     ::  (( 5 Word.word * ii))option)) of
+                                            Some (stringappend_3300,stringappend_3310) => 
+  (case  ((string_drop stringappend_3290 stringappend_3310)) of   s0 => True )
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_3140 = (string_drop stringappend_00 ((string_length (''mulw'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_3140)) of
+        Some (stringappend_3150,stringappend_3160) => (stringappend_3150, stringappend_3160)
+  ) of
+      (_, stringappend_3160) =>
+  (let stringappend_3170 = (string_drop stringappend_3140 stringappend_3160) in
+  (let (rd, stringappend_3190) =
+       ((case  ((reg_name_matches_prefix stringappend_3170 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3180,stringappend_3190) => (stringappend_3180, stringappend_3190)
+        )) in
+  (let stringappend_3200 = (string_drop stringappend_3170 stringappend_3190) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3200)) of
+        Some (stringappend_3210,stringappend_3220) => (stringappend_3210, stringappend_3220)
+  ) of
+      (_, stringappend_3220) =>
+  (let stringappend_3230 = (string_drop stringappend_3200 stringappend_3220) in
+  (let (rs1, stringappend_3250) =
+       ((case  ((reg_name_matches_prefix stringappend_3230 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3240,stringappend_3250) => (stringappend_3240, stringappend_3250)
+        )) in
+  (let stringappend_3260 = (string_drop stringappend_3230 stringappend_3250) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3260)) of
+        Some (stringappend_3270,stringappend_3280) => (stringappend_3270, stringappend_3280)
+  ) of
+      (_, stringappend_3280) =>
+  (let stringappend_3290 = (string_drop stringappend_3260 stringappend_3280) in
+  (let (rs2, stringappend_3310) =
+       ((case  ((reg_name_matches_prefix stringappend_3290 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3300,stringappend_3310) => (stringappend_3300, stringappend_3310)
+        )) in
+  (case  ((string_drop stringappend_3290 stringappend_3310)) of
+        s0 => Some
+                (MULW (rs2,rs1,rd), ((string_length arg0)) -
+                                      ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_00 (''div''))) \<and> ((let stringappend_3330 = (string_drop stringappend_00 ((string_length (''div'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_3330)) of
+                   Some (stringappend_3340,stringappend_3350) =>
+                    (let stringappend_3360 = (string_drop stringappend_3330 stringappend_3350) in
+                    if (((((string_startswith stringappend_3360 (''w''))) \<and> ((let stringappend_3370 =
+                             (string_drop stringappend_3360 ((string_length (''w'')))) in
+                           if ((case  ((spc_matches_prefix stringappend_3370)) of
+                               Some (stringappend_3380,stringappend_3390) =>
+                                (let stringappend_3400 =
+                                  (string_drop stringappend_3370 stringappend_3390) in
+                                if ((case  ((reg_name_matches_prefix stringappend_3400
+                                             ::  (( 5 Word.word * ii))option)) of
+                                    Some (stringappend_3410,stringappend_3420) =>
+                                     (let stringappend_3430 =
+                                       (string_drop stringappend_3400 stringappend_3420) in
+                                     if ((case  ((sep_matches_prefix stringappend_3430)) of
+                                         Some (stringappend_3440,stringappend_3450) =>
+                                          (let stringappend_3460 =
+                                            (string_drop stringappend_3430 stringappend_3450) in
+                                          if ((case  ((reg_name_matches_prefix stringappend_3460
+                                                       ::  (( 5 Word.word * ii))option)) of
+                                              Some (stringappend_3470,stringappend_3480) =>
+                                               (let stringappend_3490 =
+                                                 (string_drop stringappend_3460 stringappend_3480) in
+                                               if ((case  ((sep_matches_prefix stringappend_3490)) of
+                                                   Some (stringappend_3500,stringappend_3510) =>
+                                                    (let stringappend_3520 =
+                                                      (string_drop stringappend_3490
+                                                        stringappend_3510) in
+                                                    if ((case  ((reg_name_matches_prefix
+                                                                  stringappend_3520
+                                                                 ::  (( 5 Word.word * ii))option)) of
+                                                        Some (stringappend_3530,stringappend_3540) => 
+  (case  ((string_drop stringappend_3520 stringappend_3540)) of   s0 => True )
+                                                      | None => False
+                                                      )) then
+                                                      True
+                                                    else False)
+                                                 | None => False
+                                                 )) then
+                                                 True
+                                               else False)
+                                            | None => False
+                                            )) then
+                                            True
+                                          else False)
+                                       | None => False
+                                       )) then
+                                       True
+                                     else False)
+                                  | None => False
+                                  )) then
+                                  True
+                                else False)
+                             | None => False
+                             )) then
+                             True
+                           else False))))) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_3330 = (string_drop stringappend_00 ((string_length (''div'')))) in
+     (let (s, stringappend_3350) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_3330)) of
+         Some (stringappend_3340,stringappend_3350) => (stringappend_3340, stringappend_3350)
+       )) in
+     (let stringappend_3360 = (string_drop stringappend_3330 stringappend_3350) in
+     (let stringappend_3370 = (string_drop stringappend_3360 ((string_length (''w'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_3370)) of
+        Some (stringappend_3380,stringappend_3390) => (stringappend_3380, stringappend_3390)
+  ) of
+      (_, stringappend_3390) =>
+  (let stringappend_3400 = (string_drop stringappend_3370 stringappend_3390) in
+  (let (rd, stringappend_3420) =
+       ((case  ((reg_name_matches_prefix stringappend_3400 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3410,stringappend_3420) => (stringappend_3410, stringappend_3420)
+        )) in
+  (let stringappend_3430 = (string_drop stringappend_3400 stringappend_3420) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3430)) of
+        Some (stringappend_3440,stringappend_3450) => (stringappend_3440, stringappend_3450)
+  ) of
+      (_, stringappend_3450) =>
+  (let stringappend_3460 = (string_drop stringappend_3430 stringappend_3450) in
+  (let (rs1, stringappend_3480) =
+       ((case  ((reg_name_matches_prefix stringappend_3460 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3470,stringappend_3480) => (stringappend_3470, stringappend_3480)
+        )) in
+  (let stringappend_3490 = (string_drop stringappend_3460 stringappend_3480) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3490)) of
+        Some (stringappend_3500,stringappend_3510) => (stringappend_3500, stringappend_3510)
+  ) of
+      (_, stringappend_3510) =>
+  (let stringappend_3520 = (string_drop stringappend_3490 stringappend_3510) in
+  (let (rs2, stringappend_3540) =
+       ((case  ((reg_name_matches_prefix stringappend_3520 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3530,stringappend_3540) => (stringappend_3530, stringappend_3540)
+        )) in
+  (case  ((string_drop stringappend_3520 stringappend_3540)) of
+        s1 => Some
+                (DIVW (rs2,rs1,rd,s), ((string_length arg0)) -
+                                        ((string_length s1)))
+  )))
+  ))))
+  ))))
+  )))))
+   else if (((((string_startswith stringappend_00 (''rem''))) \<and> ((let stringappend_3560 = (string_drop stringappend_00 ((string_length (''rem'')))) in
+               if ((case  ((maybe_not_u_matches_prefix stringappend_3560)) of
+                   Some (stringappend_3570,stringappend_3580) =>
+                    (let stringappend_3590 = (string_drop stringappend_3560 stringappend_3580) in
+                    if (((((string_startswith stringappend_3590 (''w''))) \<and> ((let stringappend_3600 =
+                             (string_drop stringappend_3590 ((string_length (''w'')))) in
+                           if ((case  ((spc_matches_prefix stringappend_3600)) of
+                               Some (stringappend_3610,stringappend_3620) =>
+                                (let stringappend_3630 =
+                                  (string_drop stringappend_3600 stringappend_3620) in
+                                if ((case  ((reg_name_matches_prefix stringappend_3630
+                                             ::  (( 5 Word.word * ii))option)) of
+                                    Some (stringappend_3640,stringappend_3650) =>
+                                     (let stringappend_3660 =
+                                       (string_drop stringappend_3630 stringappend_3650) in
+                                     if ((case  ((sep_matches_prefix stringappend_3660)) of
+                                         Some (stringappend_3670,stringappend_3680) =>
+                                          (let stringappend_3690 =
+                                            (string_drop stringappend_3660 stringappend_3680) in
+                                          if ((case  ((reg_name_matches_prefix stringappend_3690
+                                                       ::  (( 5 Word.word * ii))option)) of
+                                              Some (stringappend_3700,stringappend_3710) =>
+                                               (let stringappend_3720 =
+                                                 (string_drop stringappend_3690 stringappend_3710) in
+                                               if ((case  ((sep_matches_prefix stringappend_3720)) of
+                                                   Some (stringappend_3730,stringappend_3740) =>
+                                                    (let stringappend_3750 =
+                                                      (string_drop stringappend_3720
+                                                        stringappend_3740) in
+                                                    if ((case  ((reg_name_matches_prefix
+                                                                  stringappend_3750
+                                                                 ::  (( 5 Word.word * ii))option)) of
+                                                        Some (stringappend_3760,stringappend_3770) => 
+  (case  ((string_drop stringappend_3750 stringappend_3770)) of   s0 => True )
+                                                      | None => False
+                                                      )) then
+                                                      True
+                                                    else False)
+                                                 | None => False
+                                                 )) then
+                                                 True
+                                               else False)
+                                            | None => False
+                                            )) then
+                                            True
+                                          else False)
+                                       | None => False
+                                       )) then
+                                       True
+                                     else False)
+                                  | None => False
+                                  )) then
+                                  True
+                                else False)
+                             | None => False
+                             )) then
+                             True
+                           else False))))) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_3560 = (string_drop stringappend_00 ((string_length (''rem'')))) in
+     (let (s, stringappend_3580) =
+       ((case  ((maybe_not_u_matches_prefix stringappend_3560)) of
+         Some (stringappend_3570,stringappend_3580) => (stringappend_3570, stringappend_3580)
+       )) in
+     (let stringappend_3590 = (string_drop stringappend_3560 stringappend_3580) in
+     (let stringappend_3600 = (string_drop stringappend_3590 ((string_length (''w'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_3600)) of
+        Some (stringappend_3610,stringappend_3620) => (stringappend_3610, stringappend_3620)
+  ) of
+      (_, stringappend_3620) =>
+  (let stringappend_3630 = (string_drop stringappend_3600 stringappend_3620) in
+  (let (rd, stringappend_3650) =
+       ((case  ((reg_name_matches_prefix stringappend_3630 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3640,stringappend_3650) => (stringappend_3640, stringappend_3650)
+        )) in
+  (let stringappend_3660 = (string_drop stringappend_3630 stringappend_3650) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3660)) of
+        Some (stringappend_3670,stringappend_3680) => (stringappend_3670, stringappend_3680)
+  ) of
+      (_, stringappend_3680) =>
+  (let stringappend_3690 = (string_drop stringappend_3660 stringappend_3680) in
+  (let (rs1, stringappend_3710) =
+       ((case  ((reg_name_matches_prefix stringappend_3690 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3700,stringappend_3710) => (stringappend_3700, stringappend_3710)
+        )) in
+  (let stringappend_3720 = (string_drop stringappend_3690 stringappend_3710) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3720)) of
+        Some (stringappend_3730,stringappend_3740) => (stringappend_3730, stringappend_3740)
+  ) of
+      (_, stringappend_3740) =>
+  (let stringappend_3750 = (string_drop stringappend_3720 stringappend_3740) in
+  (let (rs2, stringappend_3770) =
+       ((case  ((reg_name_matches_prefix stringappend_3750 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_3760,stringappend_3770) => (stringappend_3760, stringappend_3770)
+        )) in
+  (case  ((string_drop stringappend_3750 stringappend_3770)) of
+        s1 => Some
+                (REMW (rs2,rs1,rd,s), ((string_length arg0)) -
+                                        ((string_length s1)))
+  )))
+  ))))
+  ))))
+  )))))
+   else if (((((string_startswith stringappend_00 (''fence''))) \<and> ((let stringappend_3790 = (string_drop stringappend_00 ((string_length (''fence'')))) in
+               if ((case  ((spc_matches_prefix stringappend_3790)) of
+                   Some (stringappend_3800,stringappend_3810) =>
+                    (let stringappend_3820 = (string_drop stringappend_3790 stringappend_3810) in
+                    if ((case  ((fence_bits_matches_prefix stringappend_3820
+                                 ::  (( 4 Word.word * ii))option)) of
+                        Some (stringappend_3830,stringappend_3840) =>
+                         (let stringappend_3850 = (string_drop stringappend_3820 stringappend_3840) in
+                         if ((case  ((sep_matches_prefix stringappend_3850)) of
+                             Some (stringappend_3860,stringappend_3870) =>
+                              (let stringappend_3880 =
+                                (string_drop stringappend_3850 stringappend_3870) in
+                              if ((case  ((fence_bits_matches_prefix stringappend_3880
+                                           ::  (( 4 Word.word * ii))option)) of
+                                  Some (stringappend_3890,stringappend_3900) => 
+  (case  ((string_drop stringappend_3880 stringappend_3900)) of   s0 => True )
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_3790 = (string_drop stringappend_00 ((string_length (''fence'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_3790)) of
+        Some (stringappend_3800,stringappend_3810) => (stringappend_3800, stringappend_3810)
+  ) of
+      (_, stringappend_3810) =>
+  (let stringappend_3820 = (string_drop stringappend_3790 stringappend_3810) in
+  (let (pred, stringappend_3840) =
+       ((case  ((fence_bits_matches_prefix stringappend_3820 :: (( 4 Word.word * ii)) option)) of
+              Some (stringappend_3830,stringappend_3840) => (stringappend_3830, stringappend_3840)
+        )) in
+  (let stringappend_3850 = (string_drop stringappend_3820 stringappend_3840) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_3850)) of
+        Some (stringappend_3860,stringappend_3870) => (stringappend_3860, stringappend_3870)
+  ) of
+      (_, stringappend_3870) =>
+  (let stringappend_3880 = (string_drop stringappend_3850 stringappend_3870) in
+  (let (succ, stringappend_3900) =
+       ((case  ((fence_bits_matches_prefix stringappend_3880 :: (( 4 Word.word * ii)) option)) of
+              Some (stringappend_3890,stringappend_3900) => (stringappend_3890, stringappend_3900)
+        )) in
+  (case  ((string_drop stringappend_3880 stringappend_3900)) of
+        s0 => Some
+                (FENCE (pred,succ), ((string_length arg0)) -
+                                      ((string_length s0)))
+  )))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_00 (''fence.i''))) \<and> (
+  (case  ((string_drop stringappend_00 ((string_length (''fence.i''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_00 ((string_length (''fence.i''))))) of
+       s0 => Some (FENCEI () , ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_00 (''ecall''))) \<and> (
+  (case  ((string_drop stringappend_00 ((string_length (''ecall''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_00 ((string_length (''ecall''))))) of
+       s0 => Some (ECALL () , ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_00 (''mret''))) \<and> (
+  (case  ((string_drop stringappend_00 ((string_length (''mret''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_00 ((string_length (''mret''))))) of
+       s0 => Some (MRET () , ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_00 (''sret''))) \<and> (
+  (case  ((string_drop stringappend_00 ((string_length (''sret''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_00 ((string_length (''sret''))))) of
+       s0 => Some (SRET () , ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_00 (''ebreak''))) \<and> (
+  (case  ((string_drop stringappend_00 ((string_length (''ebreak''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_00 ((string_length (''ebreak''))))) of
+       s0 => Some (EBREAK () , ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_00 (''wfi''))) \<and> (
+  (case  ((string_drop stringappend_00 ((string_length (''wfi''))))) of
+        s0 => True
+  ))))) then
+     (case  ((string_drop stringappend_00 ((string_length (''wfi''))))) of
+       s0 => Some (WFI () , ((string_length arg0)) - ((string_length s0)))
+     )
+   else if (((((string_startswith stringappend_00 (''sfence.vma''))) \<and> ((let stringappend_3980 = (string_drop stringappend_00 ((string_length (''sfence.vma'')))) in
+               if ((case  ((spc_matches_prefix stringappend_3980)) of
+                   Some (stringappend_3990,stringappend_4000) =>
+                    (let stringappend_4010 = (string_drop stringappend_3980 stringappend_4000) in
+                    if ((case  ((reg_name_matches_prefix stringappend_4010
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_4020,stringappend_4030) =>
+                         (let stringappend_4040 = (string_drop stringappend_4010 stringappend_4030) in
+                         if ((case  ((sep_matches_prefix stringappend_4040)) of
+                             Some (stringappend_4050,stringappend_4060) =>
+                              (let stringappend_4070 =
+                                (string_drop stringappend_4040 stringappend_4060) in
+                              if ((case  ((reg_name_matches_prefix stringappend_4070
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_4080,stringappend_4090) => 
+  (case  ((string_drop stringappend_4070 stringappend_4090)) of   s0 => True )
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_3980 = (string_drop stringappend_00 ((string_length (''sfence.vma'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_3980)) of
+        Some (stringappend_3990,stringappend_4000) => (stringappend_3990, stringappend_4000)
+  ) of
+      (_, stringappend_4000) =>
+  (let stringappend_4010 = (string_drop stringappend_3980 stringappend_4000) in
+  (let (rs1, stringappend_4030) =
+       ((case  ((reg_name_matches_prefix stringappend_4010 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4020,stringappend_4030) => (stringappend_4020, stringappend_4030)
+        )) in
+  (let stringappend_4040 = (string_drop stringappend_4010 stringappend_4030) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_4040)) of
+        Some (stringappend_4050,stringappend_4060) => (stringappend_4050, stringappend_4060)
+  ) of
+      (_, stringappend_4060) =>
+  (let stringappend_4070 = (string_drop stringappend_4040 stringappend_4060) in
+  (let (rs2, stringappend_4090) =
+       ((case  ((reg_name_matches_prefix stringappend_4070 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4080,stringappend_4090) => (stringappend_4080, stringappend_4090)
+        )) in
+  (case  ((string_drop stringappend_4070 stringappend_4090)) of
+        s0 => Some
+                (SFENCE_VMA (rs1,rs2), ((string_length arg0)) -
+                                         ((string_length s0)))
+  )))
+  ))))
+  ))
+   else if (((((string_startswith stringappend_00 (''lr.''))) \<and> ((let stringappend_4110 = (string_drop stringappend_00 ((string_length (''lr.'')))) in
+               if ((case  ((maybe_aq_matches_prefix stringappend_4110)) of
+                   Some (stringappend_4120,stringappend_4130) =>
+                    (let stringappend_4140 = (string_drop stringappend_4110 stringappend_4130) in
+                    if ((case  ((maybe_rl_matches_prefix stringappend_4140)) of
+                        Some (stringappend_4150,stringappend_4160) =>
+                         (let stringappend_4170 = (string_drop stringappend_4140 stringappend_4160) in
+                         if ((case  ((size_mnemonic_matches_prefix stringappend_4170)) of
+                             Some (stringappend_4180,stringappend_4190) =>
+                              (let stringappend_4200 =
+                                (string_drop stringappend_4170 stringappend_4190) in
+                              if ((case  ((spc_matches_prefix stringappend_4200)) of
+                                  Some (stringappend_4210,stringappend_4220) =>
+                                   (let stringappend_4230 =
+                                     (string_drop stringappend_4200 stringappend_4220) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_4230
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_4240,stringappend_4250) =>
+                                        (let stringappend_4260 =
+                                          (string_drop stringappend_4230 stringappend_4250) in
+                                        if ((case  ((sep_matches_prefix stringappend_4260)) of
+                                            Some (stringappend_4270,stringappend_4280) =>
+                                             (let stringappend_4290 =
+                                               (string_drop stringappend_4260 stringappend_4280) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_4290
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_4300,stringappend_4310) => 
+  (case  ((string_drop stringappend_4290 stringappend_4310)) of   s0 => True )
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_4110 = (string_drop stringappend_00 ((string_length (''lr.'')))) in
+     (let (aq, stringappend_4130) =
+       ((case  ((maybe_aq_matches_prefix stringappend_4110)) of
+         Some (stringappend_4120,stringappend_4130) => (stringappend_4120, stringappend_4130)
+       )) in
+     (let stringappend_4140 = (string_drop stringappend_4110 stringappend_4130) in
+     (let (rl, stringappend_4160) =
+       ((case  ((maybe_rl_matches_prefix stringappend_4140)) of
+         Some (stringappend_4150,stringappend_4160) => (stringappend_4150, stringappend_4160)
+       )) in
+     (let stringappend_4170 = (string_drop stringappend_4140 stringappend_4160) in
+     (let (size1, stringappend_4190) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_4170)) of
+         Some (stringappend_4180,stringappend_4190) => (stringappend_4180, stringappend_4190)
+       )) in
+     (let stringappend_4200 = (string_drop stringappend_4170 stringappend_4190) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_4200)) of
+        Some (stringappend_4210,stringappend_4220) => (stringappend_4210, stringappend_4220)
+  ) of
+      (_, stringappend_4220) =>
+  (let stringappend_4230 = (string_drop stringappend_4200 stringappend_4220) in
+  (let (rd, stringappend_4250) =
+       ((case  ((reg_name_matches_prefix stringappend_4230 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4240,stringappend_4250) => (stringappend_4240, stringappend_4250)
+        )) in
+  (let stringappend_4260 = (string_drop stringappend_4230 stringappend_4250) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_4260)) of
+        Some (stringappend_4270,stringappend_4280) => (stringappend_4270, stringappend_4280)
+  ) of
+      (_, stringappend_4280) =>
+  (let stringappend_4290 = (string_drop stringappend_4260 stringappend_4280) in
+  (let (rs1, stringappend_4310) =
+       ((case  ((reg_name_matches_prefix stringappend_4290 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4300,stringappend_4310) => (stringappend_4300, stringappend_4310)
+        )) in
+  (case  ((string_drop stringappend_4290 stringappend_4310)) of
+        s0 =>
+  Some
+    (LOADRES (aq,rl,rs1,size1,rd), ((string_length arg0)) -
+                                     ((string_length s0)))
+  )))
+  ))))
+  ))))))))
+   else if (((((string_startswith stringappend_00 (''sc.''))) \<and> ((let stringappend_4330 = (string_drop stringappend_00 ((string_length (''sc.'')))) in
+               if ((case  ((maybe_aq_matches_prefix stringappend_4330)) of
+                   Some (stringappend_4340,stringappend_4350) =>
+                    (let stringappend_4360 = (string_drop stringappend_4330 stringappend_4350) in
+                    if ((case  ((maybe_rl_matches_prefix stringappend_4360)) of
+                        Some (stringappend_4370,stringappend_4380) =>
+                         (let stringappend_4390 = (string_drop stringappend_4360 stringappend_4380) in
+                         if ((case  ((size_mnemonic_matches_prefix stringappend_4390)) of
+                             Some (stringappend_4400,stringappend_4410) =>
+                              (let stringappend_4420 =
+                                (string_drop stringappend_4390 stringappend_4410) in
+                              if ((case  ((spc_matches_prefix stringappend_4420)) of
+                                  Some (stringappend_4430,stringappend_4440) =>
+                                   (let stringappend_4450 =
+                                     (string_drop stringappend_4420 stringappend_4440) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_4450
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_4460,stringappend_4470) =>
+                                        (let stringappend_4480 =
+                                          (string_drop stringappend_4450 stringappend_4470) in
+                                        if ((case  ((sep_matches_prefix stringappend_4480)) of
+                                            Some (stringappend_4490,stringappend_4500) =>
+                                             (let stringappend_4510 =
+                                               (string_drop stringappend_4480 stringappend_4500) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_4510
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_4520,stringappend_4530) =>
+                                                  (let stringappend_4540 =
+                                                    (string_drop stringappend_4510
+                                                      stringappend_4530) in
+                                                  if ((case  ((sep_matches_prefix stringappend_4540)) of
+                                                      Some (stringappend_4550,stringappend_4560) =>
+                                                       (let stringappend_4570 =
+                                                         (string_drop stringappend_4540
+                                                           stringappend_4560) in
+                                                       if ((case  ((reg_name_matches_prefix
+                                                                     stringappend_4570
+                                                                    ::  (( 5 Word.word * ii))option)) of
+                                                           Some
+                                                           (stringappend_4580,stringappend_4590) => 
+  (case  ((string_drop stringappend_4570 stringappend_4590)) of   s0 => True )
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_4330 = (string_drop stringappend_00 ((string_length (''sc.'')))) in
+     (let (aq, stringappend_4350) =
+       ((case  ((maybe_aq_matches_prefix stringappend_4330)) of
+         Some (stringappend_4340,stringappend_4350) => (stringappend_4340, stringappend_4350)
+       )) in
+     (let stringappend_4360 = (string_drop stringappend_4330 stringappend_4350) in
+     (let (rl, stringappend_4380) =
+       ((case  ((maybe_rl_matches_prefix stringappend_4360)) of
+         Some (stringappend_4370,stringappend_4380) => (stringappend_4370, stringappend_4380)
+       )) in
+     (let stringappend_4390 = (string_drop stringappend_4360 stringappend_4380) in
+     (let (size1, stringappend_4410) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_4390)) of
+         Some (stringappend_4400,stringappend_4410) => (stringappend_4400, stringappend_4410)
+       )) in
+     (let stringappend_4420 = (string_drop stringappend_4390 stringappend_4410) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_4420)) of
+        Some (stringappend_4430,stringappend_4440) => (stringappend_4430, stringappend_4440)
+  ) of
+      (_, stringappend_4440) =>
+  (let stringappend_4450 = (string_drop stringappend_4420 stringappend_4440) in
+  (let (rd, stringappend_4470) =
+       ((case  ((reg_name_matches_prefix stringappend_4450 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4460,stringappend_4470) => (stringappend_4460, stringappend_4470)
+        )) in
+  (let stringappend_4480 = (string_drop stringappend_4450 stringappend_4470) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_4480)) of
+        Some (stringappend_4490,stringappend_4500) => (stringappend_4490, stringappend_4500)
+  ) of
+      (_, stringappend_4500) =>
+  (let stringappend_4510 = (string_drop stringappend_4480 stringappend_4500) in
+  (let (rs1, stringappend_4530) =
+       ((case  ((reg_name_matches_prefix stringappend_4510 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4520,stringappend_4530) => (stringappend_4520, stringappend_4530)
+        )) in
+  (let stringappend_4540 = (string_drop stringappend_4510 stringappend_4530) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_4540)) of
+        Some (stringappend_4550,stringappend_4560) => (stringappend_4550, stringappend_4560)
+  ) of
+      (_, stringappend_4560) =>
+  (let stringappend_4570 = (string_drop stringappend_4540 stringappend_4560) in
+  (let (rs2, stringappend_4590) =
+       ((case  ((reg_name_matches_prefix stringappend_4570 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4580,stringappend_4590) => (stringappend_4580, stringappend_4590)
+        )) in
+  (case  ((string_drop stringappend_4570 stringappend_4590)) of
+        s0 =>
+  Some
+    (STORECON (aq,rl,rs2,rs1,size1,rd),
+    ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))))))))
+   else if ((case  ((amo_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_4610,stringappend_4620) =>
+        (let stringappend_4630 = (string_drop stringappend_00 stringappend_4620) in
+        if (((((string_startswith stringappend_4630 (''.''))) \<and> ((let stringappend_4640 = (string_drop stringappend_4630 ((string_length (''.'')))) in
+               if ((case  ((size_mnemonic_matches_prefix stringappend_4640)) of
+                   Some (stringappend_4650,stringappend_4660) =>
+                    (let stringappend_4670 = (string_drop stringappend_4640 stringappend_4660) in
+                    if ((case  ((maybe_aq_matches_prefix stringappend_4670)) of
+                        Some (stringappend_4680,stringappend_4690) =>
+                         (let stringappend_4700 = (string_drop stringappend_4670 stringappend_4690) in
+                         if ((case  ((maybe_rl_matches_prefix stringappend_4700)) of
+                             Some (stringappend_4710,stringappend_4720) =>
+                              (let stringappend_4730 =
+                                (string_drop stringappend_4700 stringappend_4720) in
+                              if ((case  ((spc_matches_prefix stringappend_4730)) of
+                                  Some (stringappend_4740,stringappend_4750) =>
+                                   (let stringappend_4760 =
+                                     (string_drop stringappend_4730 stringappend_4750) in
+                                   if ((case  ((reg_name_matches_prefix stringappend_4760
+                                                ::  (( 5 Word.word * ii))option)) of
+                                       Some (stringappend_4770,stringappend_4780) =>
+                                        (let stringappend_4790 =
+                                          (string_drop stringappend_4760 stringappend_4780) in
+                                        if ((case  ((sep_matches_prefix stringappend_4790)) of
+                                            Some (stringappend_4800,stringappend_4810) =>
+                                             (let stringappend_4820 =
+                                               (string_drop stringappend_4790 stringappend_4810) in
+                                             if ((case  ((reg_name_matches_prefix stringappend_4820
+                                                          ::  (( 5 Word.word * ii))option)) of
+                                                 Some (stringappend_4830,stringappend_4840) =>
+                                                  (let stringappend_4850 =
+                                                    (string_drop stringappend_4820
+                                                      stringappend_4840) in
+                                                  if ((case  ((sep_matches_prefix stringappend_4850)) of
+                                                      Some (stringappend_4860,stringappend_4870) =>
+                                                       (let stringappend_4880 =
+                                                         (string_drop stringappend_4850
+                                                           stringappend_4870) in
+                                                       if ((case  ((reg_name_matches_prefix
+                                                                     stringappend_4880
+                                                                    ::  (( 5 Word.word * ii))option)) of
+                                                           Some
+                                                           (stringappend_4890,stringappend_4900) => 
+  (case  ((string_drop stringappend_4880 stringappend_4900)) of   s0 => True )
+                                                         | None => False
+                                                         )) then
+                                                         True
+                                                       else False)
+                                                    | None => False
+                                                    )) then
+                                                    True
+                                                  else False)
+                                               | None => False
+                                               )) then
+                                               True
+                                             else False)
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_4620) =
+       ((case  ((amo_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_4610,stringappend_4620) => (stringappend_4610, stringappend_4620)
+       )) in
+     (let stringappend_4630 = (string_drop stringappend_00 stringappend_4620) in
+     (let stringappend_4640 = (string_drop stringappend_4630 ((string_length (''.'')))) in
+     (let (width, stringappend_4660) =
+       ((case  ((size_mnemonic_matches_prefix stringappend_4640)) of
+         Some (stringappend_4650,stringappend_4660) => (stringappend_4650, stringappend_4660)
+       )) in
+     (let stringappend_4670 = (string_drop stringappend_4640 stringappend_4660) in
+     (let (aq, stringappend_4690) =
+       ((case  ((maybe_aq_matches_prefix stringappend_4670)) of
+         Some (stringappend_4680,stringappend_4690) => (stringappend_4680, stringappend_4690)
+       )) in
+     (let stringappend_4700 = (string_drop stringappend_4670 stringappend_4690) in
+     (let (rl, stringappend_4720) =
+       ((case  ((maybe_rl_matches_prefix stringappend_4700)) of
+         Some (stringappend_4710,stringappend_4720) => (stringappend_4710, stringappend_4720)
+       )) in
+     (let stringappend_4730 = (string_drop stringappend_4700 stringappend_4720) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_4730)) of
+        Some (stringappend_4740,stringappend_4750) => (stringappend_4740, stringappend_4750)
+  ) of
+      (_, stringappend_4750) =>
+  (let stringappend_4760 = (string_drop stringappend_4730 stringappend_4750) in
+  (let (rd, stringappend_4780) =
+       ((case  ((reg_name_matches_prefix stringappend_4760 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4770,stringappend_4780) => (stringappend_4770, stringappend_4780)
+        )) in
+  (let stringappend_4790 = (string_drop stringappend_4760 stringappend_4780) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_4790)) of
+        Some (stringappend_4800,stringappend_4810) => (stringappend_4800, stringappend_4810)
+  ) of
+      (_, stringappend_4810) =>
+  (let stringappend_4820 = (string_drop stringappend_4790 stringappend_4810) in
+  (let (rs1, stringappend_4840) =
+       ((case  ((reg_name_matches_prefix stringappend_4820 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4830,stringappend_4840) => (stringappend_4830, stringappend_4840)
+        )) in
+  (let stringappend_4850 = (string_drop stringappend_4820 stringappend_4840) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_4850)) of
+        Some (stringappend_4860,stringappend_4870) => (stringappend_4860, stringappend_4870)
+  ) of
+      (_, stringappend_4870) =>
+  (let stringappend_4880 = (string_drop stringappend_4850 stringappend_4870) in
+  (let (rs2, stringappend_4900) =
+       ((case  ((reg_name_matches_prefix stringappend_4880 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4890,stringappend_4900) => (stringappend_4890, stringappend_4900)
+        )) in
+  (case  ((string_drop stringappend_4880 stringappend_4900)) of
+        s0 =>
+  Some
+    (AMO (op1,aq,rl,rs2,rs1,width,rd),
+    ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))))))))))
+   else if ((case  ((csr_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_4920,stringappend_4930) =>
+        (let stringappend_4940 = (string_drop stringappend_00 stringappend_4930) in
+        if (((((string_startswith stringappend_4940 (''i''))) \<and> ((let stringappend_4950 = (string_drop stringappend_4940 ((string_length (''i'')))) in
+               if ((case  ((spc_matches_prefix stringappend_4950)) of
+                   Some (stringappend_4960,stringappend_4970) =>
+                    (let stringappend_4980 = (string_drop stringappend_4950 stringappend_4970) in
+                    if ((case  ((reg_name_matches_prefix stringappend_4980
+                                 ::  (( 5 Word.word * ii))option)) of
+                        Some (stringappend_4990,stringappend_5000) =>
+                         (let stringappend_5010 = (string_drop stringappend_4980 stringappend_5000) in
+                         if ((case  ((sep_matches_prefix stringappend_5010)) of
+                             Some (stringappend_5020,stringappend_5030) =>
+                              (let stringappend_5040 =
+                                (string_drop stringappend_5010 stringappend_5030) in
+                              if ((case  ((hex_bits_5_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5040
+                                           ::  (( 5 Word.word * ii))option)) of
+                                  Some (stringappend_5050,stringappend_5060) =>
+                                   (let stringappend_5070 =
+                                     (string_drop stringappend_5040 stringappend_5060) in
+                                   if ((case  ((sep_matches_prefix stringappend_5070)) of
+                                       Some (stringappend_5080,stringappend_5090) =>
+                                        (let stringappend_5100 =
+                                          (string_drop stringappend_5070 stringappend_5090) in
+                                        if ((case  ((csr_name_map_matches_prefix stringappend_5100
+                                                     ::  (( 12 Word.word * ii))option)) of
+                                            Some (stringappend_5110,stringappend_5120) => 
+  (case  ((string_drop stringappend_5100 stringappend_5120)) of   s0 => True )
+                                          | None => False
+                                          )) then
+                                          True
+                                        else False)
+                                     | None => False
+                                     )) then
+                                     True
+                                   else False)
+                                | None => False
+                                )) then
+                                True
+                              else False)
+                           | None => False
+                           )) then
+                           True
+                         else False)
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_4930) =
+       ((case  ((csr_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_4920,stringappend_4930) => (stringappend_4920, stringappend_4930)
+       )) in
+     (let stringappend_4940 = (string_drop stringappend_00 stringappend_4930) in
+     (let stringappend_4950 = (string_drop stringappend_4940 ((string_length (''i'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_4950)) of
+        Some (stringappend_4960,stringappend_4970) => (stringappend_4960, stringappend_4970)
+  ) of
+      (_, stringappend_4970) =>
+  (let stringappend_4980 = (string_drop stringappend_4950 stringappend_4970) in
+  (let (rd, stringappend_5000) =
+       ((case  ((reg_name_matches_prefix stringappend_4980 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_4990,stringappend_5000) => (stringappend_4990, stringappend_5000)
+        )) in
+  (let stringappend_5010 = (string_drop stringappend_4980 stringappend_5000) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5010)) of
+        Some (stringappend_5020,stringappend_5030) => (stringappend_5020, stringappend_5030)
+  ) of
+      (_, stringappend_5030) =>
+  (let stringappend_5040 = (string_drop stringappend_5010 stringappend_5030) in
+  (let (rs1, stringappend_5060) =
+       ((case  ((hex_bits_5_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_5040 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5050,stringappend_5060) => (stringappend_5050, stringappend_5060)
+        )) in
+  (let stringappend_5070 = (string_drop stringappend_5040 stringappend_5060) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5070)) of
+        Some (stringappend_5080,stringappend_5090) => (stringappend_5080, stringappend_5090)
+  ) of
+      (_, stringappend_5090) =>
+  (let stringappend_5100 = (string_drop stringappend_5070 stringappend_5090) in
+  (let (csr, stringappend_5120) =
+       ((case  ((csr_name_map_matches_prefix stringappend_5100 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_5110,stringappend_5120) => (stringappend_5110, stringappend_5120)
+        )) in
+  (case  ((string_drop stringappend_5100 stringappend_5120)) of
+        s0 =>
+  Some
+    (CSR (csr,rs1,rd,True,op1), ((string_length arg0)) - ((string_length s0)))
+  )))
+  ))))
+  ))))
+  ))))
+   else if ((case  ((csr_mnemonic_matches_prefix stringappend_00)) of
+       Some (stringappend_5140,stringappend_5150) =>
+        (let stringappend_5160 = (string_drop stringappend_00 stringappend_5150) in
+        if ((case  ((spc_matches_prefix stringappend_5160)) of
+            Some (stringappend_5170,stringappend_5180) =>
+             (let stringappend_5190 = (string_drop stringappend_5160 stringappend_5180) in
+             if ((case  ((reg_name_matches_prefix stringappend_5190  ::  (( 5 Word.word * ii))option)) of
+                 Some (stringappend_5200,stringappend_5210) =>
+                  (let stringappend_5220 = (string_drop stringappend_5190 stringappend_5210) in
+                  if ((case  ((sep_matches_prefix stringappend_5220)) of
+                      Some (stringappend_5230,stringappend_5240) =>
+                       (let stringappend_5250 = (string_drop stringappend_5220 stringappend_5240) in
+                       if ((case  ((reg_name_matches_prefix stringappend_5250
+                                    ::  (( 5 Word.word * ii))option)) of
+                           Some (stringappend_5260,stringappend_5270) =>
+                            (let stringappend_5280 =
+                              (string_drop stringappend_5250 stringappend_5270) in
+                            if ((case  ((sep_matches_prefix stringappend_5280)) of
+                                Some (stringappend_5290,stringappend_5300) =>
+                                 (let stringappend_5310 =
+                                   (string_drop stringappend_5280 stringappend_5300) in
+                                 if ((case  ((csr_name_map_matches_prefix stringappend_5310
+                                              ::  (( 12 Word.word * ii))option)) of
+                                     Some (stringappend_5320,stringappend_5330) => 
+  (case  ((string_drop stringappend_5310 stringappend_5330)) of   s0 => True )
+                                   | None => False
+                                   )) then
+                                   True
+                                 else False)
+                              | None => False
+                              )) then
+                              True
+                            else False)
+                         | None => False
+                         )) then
+                         True
+                       else False)
+                    | None => False
+                    )) then
+                    True
+                  else False)
+               | None => False
+               )) then
+               True
+             else False)
+          | None => False
+          )) then
+          True
+        else False)
+     | None => False
+     )) then
+     (let (op1, stringappend_5150) =
+       ((case  ((csr_mnemonic_matches_prefix stringappend_00)) of
+         Some (stringappend_5140,stringappend_5150) => (stringappend_5140, stringappend_5150)
+       )) in
+     (let stringappend_5160 = (string_drop stringappend_00 stringappend_5150) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_5160)) of
+        Some (stringappend_5170,stringappend_5180) => (stringappend_5170, stringappend_5180)
+  ) of
+      (_, stringappend_5180) =>
+  (let stringappend_5190 = (string_drop stringappend_5160 stringappend_5180) in
+  (let (rd, stringappend_5210) =
+       ((case  ((reg_name_matches_prefix stringappend_5190 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5200,stringappend_5210) => (stringappend_5200, stringappend_5210)
+        )) in
+  (let stringappend_5220 = (string_drop stringappend_5190 stringappend_5210) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5220)) of
+        Some (stringappend_5230,stringappend_5240) => (stringappend_5230, stringappend_5240)
+  ) of
+      (_, stringappend_5240) =>
+  (let stringappend_5250 = (string_drop stringappend_5220 stringappend_5240) in
+  (let (rs1, stringappend_5270) =
+       ((case  ((reg_name_matches_prefix stringappend_5250 :: (( 5 Word.word * ii)) option)) of
+              Some (stringappend_5260,stringappend_5270) => (stringappend_5260, stringappend_5270)
+        )) in
+  (let stringappend_5280 = (string_drop stringappend_5250 stringappend_5270) in
+  (case 
+  (case  ((sep_matches_prefix stringappend_5280)) of
+        Some (stringappend_5290,stringappend_5300) => (stringappend_5290, stringappend_5300)
+  ) of
+      (_, stringappend_5300) =>
+  (let stringappend_5310 = (string_drop stringappend_5280 stringappend_5300) in
+  (let (csr, stringappend_5330) =
+       ((case  ((csr_name_map_matches_prefix stringappend_5310 :: (( 12 Word.word * ii)) option)) of
+              Some (stringappend_5320,stringappend_5330) => (stringappend_5320, stringappend_5330)
+        )) in
+  (case  ((string_drop stringappend_5310 stringappend_5330)) of
+        s0 =>
+  Some
+    (CSR (csr,rs1,rd,False,op1), ((string_length arg0)) -
+                                   ((string_length s0)))
+  )))
+  ))))
+  ))))
+  )))
+   else if (((((string_startswith stringappend_00 (''illegal''))) \<and> ((let stringappend_5350 = (string_drop stringappend_00 ((string_length (''illegal'')))) in
+               if ((case  ((spc_matches_prefix stringappend_5350)) of
+                   Some (stringappend_5360,stringappend_5370) =>
+                    (let stringappend_5380 = (string_drop stringappend_5350 stringappend_5370) in
+                    if ((case  ((hex_bits_32_matches_prefix 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5380
+                                 ::  (( 32 Word.word * ii))option)) of
+                        Some (stringappend_5390,stringappend_5400) => 
+  (case  ((string_drop stringappend_5380 stringappend_5400)) of   s0 => True )
+                      | None => False
+                      )) then
+                      True
+                    else False)
+                 | None => False
+                 )) then
+                 True
+               else False))))) then
+     (let stringappend_5350 = (string_drop stringappend_00 ((string_length (''illegal'')))) in  
+  (case 
+  (case  ((spc_matches_prefix stringappend_5350)) of
+        Some (stringappend_5360,stringappend_5370) => (stringappend_5360, stringappend_5370)
+  ) of
+      (_, stringappend_5370) =>
+  (let stringappend_5380 = (string_drop stringappend_5350 stringappend_5370) in
+  (let (s, stringappend_5400) =
+       ((case  ((hex_bits_32_matches_prefix
+                   instance_Sail2_values_Bitvector_Machine_word_mword_dict
+                   stringappend_5380 :: (( 32 Word.word * ii)) option)) of
+              Some (stringappend_5390,stringappend_5400) => (stringappend_5390, stringappend_5400)
+        )) in
+  (case  ((string_drop stringappend_5380 stringappend_5400)) of
+        s1 => Some (ILLEGAL s, ((string_length arg0)) - ((string_length s1)))
+  )))
+  ))
+   else None))"
+
+
+(*val encdec_forwards : ast -> mword ty32*)
+
+fun encdec_forwards  :: " ast \<Rightarrow>(32)Word.word "  where 
+     " encdec_forwards (UTYPE (imm,rd,op1)) = (
+      (concat_vec imm ((concat_vec rd ((encdec_uop_forwards op1  ::  7 Word.word))  ::  12 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RISCV_JAL (v__172,rd)) = (
+      (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__172 (( 20 :: int)::ii) (( 20 :: int)::ii)  ::  1 Word.word)) in
+      (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__172 (( 19 :: int)::ii) (( 12 :: int)::ii)  ::  8 Word.word)) in
+      (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__172 (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word)) in
+      (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__172 (( 10 :: int)::ii) (( 5 :: int)::ii)  ::  6 Word.word)) in
+      (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__172 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word)) in
+      (concat_vec imm_19
+         ((concat_vec imm_18_13
+             ((concat_vec imm_12_9
+                 ((concat_vec imm_8
+                     ((concat_vec imm_7_0
+                         ((concat_vec rd (vec_of_bits [B1,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  20 Word.word))
+                    ::  21 Word.word))
+                ::  25 Word.word))
+            ::  31 Word.word))
+        ::  32 Word.word)))))))"
+|" encdec_forwards (RISCV_JALR (imm,rs1,rd)) = (
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                 ((concat_vec rd (vec_of_bits [B1,B1,B0,B0,B1,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (BTYPE (v__173,rs2,rs1,op1)) = (
+      (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__173 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+      (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__173 (( 11 :: int)::ii) (( 11 :: int)::ii)  ::  1 Word.word)) in
+      (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__173 (( 10 :: int)::ii) (( 5 :: int)::ii)  ::  6 Word.word)) in
+      (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__173 (( 4 :: int)::ii) (( 1 :: int)::ii)  ::  4 Word.word)) in
+      (concat_vec imm7_6
+         ((concat_vec imm7_5_0
+             ((concat_vec rs2
+                 ((concat_vec rs1
+                     ((concat_vec ((encdec_bop_forwards op1  ::  3 Word.word))
+                         ((concat_vec imm5_4_1
+                             ((concat_vec imm5_0 (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word)
+                                ::  8 Word.word))
+                            ::  12 Word.word))
+                        ::  15 Word.word))
+                    ::  20 Word.word))
+                ::  25 Word.word))
+            ::  31 Word.word))
+        ::  32 Word.word))))))"
+|" encdec_forwards (ITYPE (imm,rs1,rd,op1)) = (
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec ((encdec_iop_forwards op1  ::  3 Word.word))
+                 ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  26 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  26 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) = (
+      (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0]  ::  6 Word.word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  26 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_ADD)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SUB)) = (
+      (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SLL)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SLT)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B1,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SLTU)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B1,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_XOR)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SRL)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SRA)) = (
+      (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_OR)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B1,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_AND)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B1,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (LOAD (imm,rs1,rd,is_unsigned,size1,False,False)) = (
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec ((bool_bits_forwards is_unsigned  ::  1 Word.word))
+                 ((concat_vec ((size_bits_forwards size1  ::  2 Word.word))
+                     ((concat_vec rd (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  14 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (STORE (v__174,rs2,rs1,size1,False,False)) = (
+      (let (imm7 :: 7 bits) = ((subrange_vec_dec v__174 (( 11 :: int)::ii) (( 5 :: int)::ii)  ::  7 Word.word)) in
+      (let (imm5 :: 5 bits) = ((subrange_vec_dec v__174 (( 4 :: int)::ii) (( 0 :: int)::ii)  ::  5 Word.word)) in
+      (concat_vec imm7
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                     ((concat_vec ((size_bits_forwards size1  ::  2 Word.word))
+                         ((concat_vec imm5 (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  14 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))))"
+|" encdec_forwards (ADDIW (imm,rs1,rd)) = (
+      (concat_vec imm
+         ((concat_vec rs1
+             ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                 ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) = (
+      (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec shamt
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) = (
+      (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) = (
+      (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0,B1]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (MUL (rs2,rs1,rd,high,signed1,signed2)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec ((encdec_mul_op_forwards high signed1 signed2  ::  3 Word.word))
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (DIV (rs2,rs1,rd,s)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0]  ::  2 Word.word)
+                     ((concat_vec ((bool_not_bits_forwards s  ::  1 Word.word))
+                         ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  13 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (REM (rs2,rs1,rd,s)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B1]  ::  2 Word.word)
+                     ((concat_vec ((bool_not_bits_forwards s  ::  1 Word.word))
+                         ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  13 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (MULW (rs2,rs1,rd)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (DIVW (rs2,rs1,rd,s)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B0]  ::  2 Word.word)
+                     ((concat_vec ((bool_not_bits_forwards s  ::  1 Word.word))
+                         ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  13 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (REMW (rs2,rs1,rd,s)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B1,B1]  ::  2 Word.word)
+                     ((concat_vec ((bool_not_bits_forwards s  ::  1 Word.word))
+                         ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  13 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (FENCE (pred,succ)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word)
+         ((concat_vec pred
+             ((concat_vec succ
+                 ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                     ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                             (vec_of_bits [B0,B0,B0,B1,B1,B1,B1]  ::  7 Word.word)
+                            ::  12 Word.word))
+                        ::  15 Word.word))
+                    ::  20 Word.word))
+                ::  24 Word.word))
+            ::  28 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (FENCEI (_)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+             ((concat_vec (vec_of_bits [B0,B0,B1]  ::  3 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                     (vec_of_bits [B0,B0,B0,B1,B1,B1,B1]  ::  7 Word.word)
+                    ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (ECALL (_)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+             ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                     (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                    ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (MRET (_)) = (
+      (concat_vec (vec_of_bits [B0,B0,B1,B1,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)
+             ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                         (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                        ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SRET (_)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0]  ::  7 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)
+             ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                         (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                        ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (EBREAK (_)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+             ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                     (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                    ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (WFI (_)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+             ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                     (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                    ::  12 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (SFENCE_VMA (rs1,rs2)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B1]  ::  7 Word.word)
+         ((concat_vec rs2
+             ((concat_vec rs1
+                 ((concat_vec (vec_of_bits [B0,B0,B0]  ::  3 Word.word)
+                     ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                         (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)
+                        ::  12 Word.word))
+                    ::  15 Word.word))
+                ::  20 Word.word))
+            ::  25 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (LOADRES (aq,rl,rs1,size1,rd)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word)
+         ((concat_vec ((bool_bits_forwards aq  ::  1 Word.word))
+             ((concat_vec ((bool_bits_forwards rl  ::  1 Word.word))
+                 ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word)
+                     ((concat_vec rs1
+                         ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                             ((concat_vec ((size_bits_forwards size1  ::  2 Word.word))
+                                 ((concat_vec rd (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)
+                                    ::  12 Word.word))
+                                ::  14 Word.word))
+                            ::  15 Word.word))
+                        ::  20 Word.word))
+                    ::  25 Word.word))
+                ::  26 Word.word))
+            ::  27 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (STORECON (aq,rl,rs2,rs1,size1,rd)) = (
+      (concat_vec (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)
+         ((concat_vec ((bool_bits_forwards aq  ::  1 Word.word))
+             ((concat_vec ((bool_bits_forwards rl  ::  1 Word.word))
+                 ((concat_vec rs2
+                     ((concat_vec rs1
+                         ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                             ((concat_vec ((size_bits_forwards size1  ::  2 Word.word))
+                                 ((concat_vec rd (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)
+                                    ::  12 Word.word))
+                                ::  14 Word.word))
+                            ::  15 Word.word))
+                        ::  20 Word.word))
+                    ::  25 Word.word))
+                ::  26 Word.word))
+            ::  27 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (AMO (op1,aq,rl,rs2,rs1,size1,rd)) = (
+      (concat_vec ((encdec_amoop_forwards op1  ::  5 Word.word))
+         ((concat_vec ((bool_bits_forwards aq  ::  1 Word.word))
+             ((concat_vec ((bool_bits_forwards rl  ::  1 Word.word))
+                 ((concat_vec rs2
+                     ((concat_vec rs1
+                         ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                             ((concat_vec ((size_bits_forwards size1  ::  2 Word.word))
+                                 ((concat_vec rd (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)
+                                    ::  12 Word.word))
+                                ::  14 Word.word))
+                            ::  15 Word.word))
+                        ::  20 Word.word))
+                    ::  25 Word.word))
+                ::  26 Word.word))
+            ::  27 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (CSR (csr,rs1,rd,is_imm,op1)) = (
+      (concat_vec csr
+         ((concat_vec rs1
+             ((concat_vec ((bool_bits_forwards is_imm  ::  1 Word.word))
+                 ((concat_vec ((encdec_csrop_forwards op1  ::  2 Word.word))
+                     ((concat_vec rd (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)  ::  12 Word.word))
+                    ::  14 Word.word))
+                ::  15 Word.word))
+            ::  20 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (STOP_FETCHING (_)) = (
+      (concat_vec (vec_of_bits [B1,B1,B1,B1,B1,B0,B1,B0,B1,B1,B0,B1,B1,B1,B1,B0]  ::  16 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word)
+             ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0]  ::  2 Word.word)
+                     ((concat_vec (vec_of_bits [B0,B1,B0]  ::  3 Word.word)
+                         (vec_of_bits [B1,B1]  ::  2 Word.word)
+                        ::  5 Word.word))
+                    ::  7 Word.word))
+                ::  8 Word.word))
+            ::  16 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (THREAD_START (_)) = (
+      (concat_vec (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1,B1,B1,B0]  ::  16 Word.word)
+         ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word)
+             ((concat_vec (vec_of_bits [B0]  ::  1 Word.word)
+                 ((concat_vec (vec_of_bits [B0,B0]  ::  2 Word.word)
+                     ((concat_vec (vec_of_bits [B0,B1,B0]  ::  3 Word.word)
+                         (vec_of_bits [B1,B1]  ::  2 Word.word)
+                        ::  5 Word.word))
+                    ::  7 Word.word))
+                ::  8 Word.word))
+            ::  16 Word.word))
+        ::  32 Word.word))"
+|" encdec_forwards (ILLEGAL (s)) = ( s )"
+
+
+(*val encdec_backwards : mword ty32 -> ast*)
+
+definition encdec_backwards  :: "(32)Word.word \<Rightarrow> ast "  where 
+     " encdec_backwards arg0 = (
+   (let v__175 = arg0 in
+   if ((let mappingpatterns_230 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     encdec_uop_backwards_matches mappingpatterns_230)) then
+     (let (imm ::  20 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 12 :: int)::ii)  ::  20 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_230 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (let op1 = (encdec_uop_backwards mappingpatterns_230) in
+     UTYPE (imm,rd,op1)))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (p00 = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))) then
+     (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 31 :: int)::ii)  ::  1 Word.word)) in
+     (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__175 (( 30 :: int)::ii) (( 25 :: int)::ii)  ::  6 Word.word)) in
+     (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 21 :: int)::ii)  ::  4 Word.word)) in
+     (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__175 (( 20 :: int)::ii) (( 20 :: int)::ii)  ::  1 Word.word)) in
+     (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 12 :: int)::ii)  ::  8 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RISCV_JAL ((concat_vec imm_19
+                   ((concat_vec imm_7_0
+                       ((concat_vec imm_8
+                           ((concat_vec imm_18_13
+                               ((concat_vec imm_12_9 (vec_of_bits [B0]  ::  1 Word.word)  ::  5 Word.word))
+                              ::  11 Word.word))
+                          ::  12 Word.word))
+                      ::  20 Word.word))
+                  ::  21 Word.word),rd)))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((p10 = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1]  ::  7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))))))) then
+     (let (imm ::  12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RISCV_JALR (imm,rs1,rd))))
+   else if ((let mappingpatterns_240 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((encdec_bop_backwards_matches mappingpatterns_240)) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word)))))))) then
+     (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 31 :: int)::ii)  ::  1 Word.word)) in
+     (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__175 (( 30 :: int)::ii) (( 25 :: int)::ii)  ::  6 Word.word)) in
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_240 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 8 :: int)::ii)  ::  4 Word.word)) in
+     (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__175 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
+     (let op1 = (encdec_bop_backwards mappingpatterns_240) in
+     BTYPE ((concat_vec imm7_6
+               ((concat_vec imm5_0
+                   ((concat_vec imm7_5_0
+                       ((concat_vec imm5_4_1 (vec_of_bits [B0]  ::  1 Word.word)  ::  5 Word.word))
+                      ::  11 Word.word))
+                  ::  12 Word.word))
+              ::  13 Word.word),rs2,rs1,op1)))))))))
+   else if ((let mappingpatterns_250 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((encdec_iop_backwards_matches mappingpatterns_250)) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))) then
+     (let (imm ::  12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_250 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let op1 = (encdec_iop_backwards mappingpatterns_250) in
+     ITYPE (imm,rs1,rd,op1))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word))))))))) then
+     (let (shamt ::  6 Word.word) = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 20 :: int)::ii)  ::  6 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     SHIFTIOP (shamt,rs1,rd,RISCV_SLLI))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word))))))))) then
+     (let (shamt ::  6 Word.word) = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 20 :: int)::ii)  ::  6 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     SHIFTIOP (shamt,rs1,rd,RISCV_SRLI))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0]  ::  6 Word.word))))))))) then
+     (let (shamt ::  6 Word.word) = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 20 :: int)::ii)  ::  6 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     SHIFTIOP (shamt,rs1,rd,RISCV_SRAI))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_ADD))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SUB))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SLL))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SLT))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SLTU))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_XOR))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SRL))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_SRA))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_OR))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPE (rs2,rs1,rd,RISCV_AND))))
+   else if ((let mappingpatterns_260 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_270 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_270)) \<and> ((bool_bits_backwards_matches mappingpatterns_260))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))))) then
+     (let (imm ::  12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_260 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_270 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_270) in
+     (let is_unsigned = (bool_bits_backwards mappingpatterns_260) in
+     LOAD (imm,rs1,rd,is_unsigned,size1,False,False))))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_280 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_280)) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0]  ::  1 Word.word))))))))) then
+     (let (imm7 :: 7 bits) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_280 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let (imm5 :: 5 bits) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_280) in
+     STORE ((concat_vec imm7 imm5  ::  12 Word.word),rs2,rs1,size1,False,False)))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((p10 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))))))) then
+     (let (imm ::  12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     ADDIW (imm,rs1,rd))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (shamt ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     SHIFTW (shamt,rs1,rd,RISCV_SLLI))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (shamt ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     SHIFTW (shamt,rs1,rd,RISCV_SRLI))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (shamt ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     SHIFTW (shamt,rs1,rd,RISCV_SRAI))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_ADDW))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SUBW))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SLLW))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SRLW))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     RTYPEW (rs2,rs1,rd,RISCV_SRAW))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let (mappingpatterns_290 :: 3 bits) = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((encdec_mul_op_backwards_matches mappingpatterns_290)) \<and> (((p10 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (mappingpatterns_290 :: 3 bits) = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_290) in
+     MUL (rs2,rs1,rd,high,signed1,signed2))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_300 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_300)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_300 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_300) in
+     DIV (rs2,rs1,rd,s))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_310 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_310)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_310 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_310) in
+     REM (rs2,rs1,rd,s))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     MULW (rs2,rs1,rd))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_320 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_320)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_320 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_320) in
+     DIVW (rs2,rs1,rd,s))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_330 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_330)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_330 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_330) in
+     REMW (rs2,rs1,rd,s))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 28 :: int)::ii)  ::  4 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word))))))))))) then
+     (let (pred ::  4 Word.word) = ((subrange_vec_dec v__175 (( 27 :: int)::ii) (( 24 :: int)::ii)  ::  4 Word.word)) in
+     (let (succ ::  4 Word.word) = ((subrange_vec_dec v__175 (( 23 :: int)::ii) (( 20 :: int)::ii)  ::  4 Word.word)) in
+     FENCE (pred,succ)))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word))))))))))) then
+     FENCEI () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word))))))))))) then
+     ECALL () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0]  ::  7 Word.word)))))))))))) then
+     MRET () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0]  ::  7 Word.word)))))))))))) then
+     SRET () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word))))))))))) then
+     EBREAK () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word))))))))))) then
+     WFI () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((p30 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     SFENCE_VMA (rs1,rs2)))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_340 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_350 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_360 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((((((((((size_bits_backwards_matches mappingpatterns_360)) \<and> ((bool_bits_backwards_matches mappingpatterns_350))))) \<and> ((bool_bits_backwards_matches mappingpatterns_340))))) \<and> (((p30 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word))))))))))))))) then
+     (let mappingpatterns_340 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_350 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_360 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_360) in
+     (let rl = (bool_bits_backwards mappingpatterns_350) in
+     (let aq = (bool_bits_backwards mappingpatterns_340) in
+     LOADRES (aq,rl,rs1,size1,rd)))))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_370 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_380 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_390 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_390)) \<and> ((bool_bits_backwards_matches mappingpatterns_380))))) \<and> ((bool_bits_backwards_matches mappingpatterns_370))))) \<and> (((p20 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))))))))))))) then
+     (let mappingpatterns_370 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_380 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_390 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_390) in
+     (let rl = (bool_bits_backwards mappingpatterns_380) in
+     (let aq = (bool_bits_backwards mappingpatterns_370) in
+     STORECON (aq,rl,rs2,rs1,size1,rd))))))))))
+   else if ((let mappingpatterns_400 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_410 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_420 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_430 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_430)) \<and> ((bool_bits_backwards_matches mappingpatterns_420))))) \<and> ((bool_bits_backwards_matches mappingpatterns_410))))) \<and> ((encdec_amoop_backwards_matches mappingpatterns_400))))) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))))))))))) then
+     (let mappingpatterns_400 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_410 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_420 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let (rs2 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_430 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_430) in
+     (let rl = (bool_bits_backwards mappingpatterns_420) in
+     (let aq = (bool_bits_backwards mappingpatterns_410) in
+     (let op1 = (encdec_amoop_backwards mappingpatterns_400) in
+     AMO (op1,aq,rl,rs2,rs1,size1,rd))))))))))))
+   else if ((let mappingpatterns_440 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_450 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((encdec_csrop_backwards_matches mappingpatterns_450)) \<and> ((bool_bits_backwards_matches mappingpatterns_440))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))))) then
+     (let (csr ::  12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let (rs1 ::  5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_440 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_450 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let (rd ::  5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let op1 = (encdec_csrop_backwards mappingpatterns_450) in
+     (let is_imm = (bool_bits_backwards mappingpatterns_440) in
+     CSR (csr,rs1,rd,is_imm,op1))))))))
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__175 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B1,B1,B0,B1,B0,B1,B1,B0,B1,B1,B1,B1,B0]  ::  16 Word.word))))))))))))
+   then
+     STOP_FETCHING () 
+   else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__175 (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__175 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__175 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__175 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1,B1,B1,B0]  ::  16 Word.word))))))))))))
+   then
+     THREAD_START () 
+   else ILLEGAL v__175))"
+
+
+(*val encdec_forwards_matches : ast -> bool*)
+
+fun encdec_forwards_matches  :: " ast \<Rightarrow> bool "  where 
+     " encdec_forwards_matches (UTYPE (imm,rd,op1)) = ( True )"
+|" encdec_forwards_matches (RISCV_JAL (v__224,rd)) = (
+      if ((let p00 = ((subrange_vec_dec v__224 (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word)) in
+        (p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then
+        True
+      else
+        (let g__17 = (RISCV_JAL (v__224,rd)) in
+        False))"
+|" encdec_forwards_matches (RISCV_JALR (imm,rs1,rd)) = ( True )"
+|" encdec_forwards_matches (BTYPE (v__225,rs2,rs1,op1)) = (
+      if ((let p00 = ((subrange_vec_dec v__225 (( 0 :: int)::ii) (( 0 :: int)::ii)  ::  1 Word.word)) in
+        (p00 = (vec_of_bits [B0]  ::  1 Word.word)))) then
+        True
+      else
+        (let g__17 = (BTYPE (v__225,rs2,rs1,op1)) in
+        False))"
+|" encdec_forwards_matches (ITYPE (imm,rs1,rd,op1)) = ( True )"
+|" encdec_forwards_matches (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) = ( True )"
+|" encdec_forwards_matches (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) = ( True )"
+|" encdec_forwards_matches (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_ADD)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SUB)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SLL)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SLT)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SLTU)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_XOR)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SRL)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SRA)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_OR)) = ( True )"
+|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_AND)) = ( True )"
+|" encdec_forwards_matches (LOAD (imm,rs1,rd,is_unsigned,size1,False,False)) = ( True )"
+|" encdec_forwards_matches (STORE (v__226,rs2,rs1,size1,False,False)) = ( True )"
+|" encdec_forwards_matches (ADDIW (imm,rs1,rd)) = ( True )"
+|" encdec_forwards_matches (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) = ( True )"
+|" encdec_forwards_matches (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) = ( True )"
+|" encdec_forwards_matches (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) = ( True )"
+|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) = ( True )"
+|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) = ( True )"
+|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) = ( True )"
+|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) = ( True )"
+|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) = ( True )"
+|" encdec_forwards_matches (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( True )"
+|" encdec_forwards_matches (DIV (rs2,rs1,rd,s)) = ( True )"
+|" encdec_forwards_matches (REM (rs2,rs1,rd,s)) = ( True )"
+|" encdec_forwards_matches (MULW (rs2,rs1,rd)) = ( True )"
+|" encdec_forwards_matches (DIVW (rs2,rs1,rd,s)) = ( True )"
+|" encdec_forwards_matches (REMW (rs2,rs1,rd,s)) = ( True )"
+|" encdec_forwards_matches (FENCE (pred,succ)) = ( True )"
+|" encdec_forwards_matches (FENCEI (_)) = ( True )"
+|" encdec_forwards_matches (ECALL (_)) = ( True )"
+|" encdec_forwards_matches (MRET (_)) = ( True )"
+|" encdec_forwards_matches (SRET (_)) = ( True )"
+|" encdec_forwards_matches (EBREAK (_)) = ( True )"
+|" encdec_forwards_matches (WFI (_)) = ( True )"
+|" encdec_forwards_matches (SFENCE_VMA (rs1,rs2)) = ( True )"
+|" encdec_forwards_matches (LOADRES (aq,rl,rs1,size1,rd)) = ( True )"
+|" encdec_forwards_matches (STORECON (aq,rl,rs2,rs1,size1,rd)) = ( True )"
+|" encdec_forwards_matches (AMO (op1,aq,rl,rs2,rs1,size1,rd)) = ( True )"
+|" encdec_forwards_matches (CSR (csr,rs1,rd,is_imm,op1)) = ( True )"
+|" encdec_forwards_matches (STOP_FETCHING (_)) = ( True )"
+|" encdec_forwards_matches (THREAD_START (_)) = ( True )"
+|" encdec_forwards_matches (ILLEGAL (s)) = ( True )"
+|" encdec_forwards_matches g__17 = ( False )"
+
+
+(*val encdec_backwards_matches : mword ty32 -> bool*)
+
+definition encdec_backwards_matches  :: "(32)Word.word \<Rightarrow> bool "  where 
+     " encdec_backwards_matches arg0 = (
+   (let v__227 = arg0 in
+   if ((let mappingpatterns_00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     encdec_uop_backwards_matches mappingpatterns_00)) then
+     (let mappingpatterns_00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (let op1 = (encdec_uop_backwards mappingpatterns_00) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (p00 = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1]  ::  7 Word.word)))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((p10 = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1]  ::  7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))))))) then
+     True
+   else if ((let mappingpatterns_10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((encdec_bop_backwards_matches mappingpatterns_10)) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1]  ::  7 Word.word)))))))) then
+     (let mappingpatterns_10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let op1 = (encdec_bop_backwards mappingpatterns_10) in
+     True))
+   else if ((let mappingpatterns_20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((encdec_iop_backwards_matches mappingpatterns_20)) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))))))) then
+     (let mappingpatterns_20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let op1 = (encdec_iop_backwards mappingpatterns_20) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0]  ::  6 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 26 :: int)::ii)  ::  6 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0]  ::  6 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let mappingpatterns_30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_40 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_40)) \<and> ((bool_bits_backwards_matches mappingpatterns_30))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))))) then
+     (let mappingpatterns_30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_40 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_40) in
+     (let is_unsigned = (bool_bits_backwards mappingpatterns_30) in
+     True))))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_50 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((size_bits_backwards_matches mappingpatterns_50)) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0]  ::  1 Word.word))))))))) then
+     (let mappingpatterns_50 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_50) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((p10 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let (mappingpatterns_60 :: 3 bits) = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((encdec_mul_op_backwards_matches mappingpatterns_60)) \<and> (((p10 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word))))))))) then
+     (let (mappingpatterns_60 :: 3 bits) = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_60) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_70 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_70)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let mappingpatterns_70 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_70) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_80 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_80)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let mappingpatterns_80 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_80) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_90 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_90)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let mappingpatterns_90 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_90) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii)  ::  2 Word.word)) in
+     (let mappingpatterns_100 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((bool_not_bits_backwards_matches mappingpatterns_100)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     (let mappingpatterns_100 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii)  ::  1 Word.word)) in
+     (let s = (bool_not_bits_backwards mappingpatterns_100) in
+     True))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 28 :: int)::ii)  ::  4 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0]  ::  4 Word.word))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B1]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]  ::  12 Word.word))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0]  ::  7 Word.word)))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0]  ::  7 Word.word)))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1]  ::  12 Word.word))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1]  ::  12 Word.word))))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii)  ::  7 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((p30 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word)))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0]  ::  3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1]  ::  7 Word.word)))))))))) then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_110 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_120 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 24 :: int)::ii) (( 20 :: int)::ii)  ::  5 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_130 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((((((((((((((size_bits_backwards_matches mappingpatterns_130)) \<and> ((bool_bits_backwards_matches mappingpatterns_120))))) \<and> ((bool_bits_backwards_matches mappingpatterns_110))))) \<and> (((p30 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0]  ::  5 Word.word))))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0]  ::  5 Word.word))))))))))))))) then
+     (let mappingpatterns_110 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_120 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_130 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_130) in
+     (let rl = (bool_bits_backwards mappingpatterns_120) in
+     (let aq = (bool_bits_backwards mappingpatterns_110) in
+     True))))))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_140 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_150 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_160 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_160)) \<and> ((bool_bits_backwards_matches mappingpatterns_150))))) \<and> ((bool_bits_backwards_matches mappingpatterns_140))))) \<and> (((p20 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1]  ::  5 Word.word)))))))))))))) then
+     (let mappingpatterns_140 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_150 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_160 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_160) in
+     (let rl = (bool_bits_backwards mappingpatterns_150) in
+     (let aq = (bool_bits_backwards mappingpatterns_140) in
+     True))))))
+   else if ((let mappingpatterns_170 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_180 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_190 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_200 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     (((((((((((((((size_bits_backwards_matches mappingpatterns_200)) \<and> ((bool_bits_backwards_matches mappingpatterns_190))))) \<and> ((bool_bits_backwards_matches mappingpatterns_180))))) \<and> ((encdec_amoop_backwards_matches mappingpatterns_170))))) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1]  ::  7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0]  ::  1 Word.word)))))))))))) then
+     (let mappingpatterns_170 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii)  ::  5 Word.word)) in
+     (let mappingpatterns_180 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_190 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_200 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let size1 = (size_bits_backwards mappingpatterns_200) in
+     (let rl = (bool_bits_backwards mappingpatterns_190) in
+     (let aq = (bool_bits_backwards mappingpatterns_180) in
+     (let op1 = (encdec_amoop_backwards mappingpatterns_170) in
+     True))))))))
+   else if ((let mappingpatterns_210 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_220 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) in
+     ((((((encdec_csrop_backwards_matches mappingpatterns_220)) \<and> ((bool_bits_backwards_matches mappingpatterns_210))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1]  ::  7 Word.word))))))))) then
+     (let mappingpatterns_210 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii)  ::  1 Word.word)) in
+     (let mappingpatterns_220 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii)  ::  2 Word.word)) in
+     (let op1 = (encdec_csrop_backwards mappingpatterns_220) in
+     (let is_imm = (bool_bits_backwards mappingpatterns_210) in
+     True))))
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__227 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B1,B1,B0,B1,B0,B1,B1,B0,B1,B1,B1,B1,B0]  ::  16 Word.word))))))))))))
+   then
+     True
+   else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 16 :: int)::ii)  ::  16 Word.word)) in
+     (let p10 = ((subrange_vec_dec v__227 (( 15 :: int)::ii) (( 8 :: int)::ii)  ::  8 Word.word)) in
+     (let p20 = ((subrange_vec_dec v__227 (( 7 :: int)::ii) (( 7 :: int)::ii)  ::  1 Word.word)) in
+     (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 5 :: int)::ii)  ::  2 Word.word)) in
+     (let p40 = ((subrange_vec_dec v__227 (( 4 :: int)::ii) (( 2 :: int)::ii)  ::  3 Word.word)) in
+     (let p50 = ((subrange_vec_dec v__227 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) in
+     ((((((((((((((((p50 = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0]  ::  3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0]  ::  1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0]  ::  8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1,B1,B1,B0]  ::  16 Word.word))))))))))))
+   then
+     True
+   else True))"
+
+
 fun print_insn  :: " ast \<Rightarrow> string "  where 
-     " print_insn (UTYPE (imm,rd,op1)) = (
-      (case  op1 of
-        RISCV_LUI =>
-         (op@) (''lui   '')
-           (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm))))))
-      | RISCV_AUIPC =>
-         (op@) (''auipc '')
-           (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm))))))
-      ))"
-|" print_insn (RISCV_JAL (imm,rd)) = (
-      (op@) (''jal   '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))"
-|" print_insn (RISCV_JALR (imm,rs1,rd)) = (
-      (op@) (''jalr  '')
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))"
-|" print_insn (BTYPE (imm,rs2,rs1,op1)) = (
-      (let (insn :: string) =
-        ((case  op1 of
-          RISCV_BEQ => (''beq   '')
-        | RISCV_BNE => (''bne   '')
-        | RISCV_BLT => (''blt   '')
-        | RISCV_BGE => (''bge   '')
-        | RISCV_BLTU => (''bltu  '')
-        | RISCV_BGEU => (''bgeu  '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rs1))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs2)) (((op@) ('', '') ((string_of_vec imm))))))))))))"
-|" print_insn (ITYPE (imm,rs1,rd,op1)) = (
-      (let (insn :: string) =
-        ((case  op1 of
-          RISCV_ADDI => (''addi  '')
-        | RISCV_SLTI => (''slti  '')
-        | RISCV_SLTIU => (''sltiu '')
-        | RISCV_XORI => (''xori  '')
-        | RISCV_ORI => (''ori   '')
-        | RISCV_ANDI => (''andi  '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))"
-|" print_insn (SHIFTIOP (shamt,rs1,rd,op1)) = (
-      (let (insn :: string) =
-        ((case  op1 of   RISCV_SLLI => (''slli  '') | RISCV_SRLI => (''srli  '') | RISCV_SRAI => (''srai  '') )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))"
-|" print_insn (RTYPE (rs2,rs1,rd,op1)) = (
-      (let (insn :: string) =
-        ((case  op1 of
-          RISCV_ADD => (''add   '')
-        | RISCV_SUB => (''sub   '')
-        | RISCV_SLL => (''sll   '')
-        | RISCV_SLT => (''slt   '')
-        | RISCV_SLTU => (''sltu  '')
-        | RISCV_XOR => (''xor   '')
-        | RISCV_SRL => (''srl   '')
-        | RISCV_SRA => (''sra   '')
-        | RISCV_OR => (''or    '')
-        | RISCV_AND => (''and   '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (LOAD (imm,rs1,rd,is_unsigned,width,aq,rl)) = (
-      (let (insn :: string) =
-        ((case  (width, is_unsigned) of
-          (BYTE, False) => (''lb    '')
-        | (BYTE, True) => (''lbu   '')
-        | (HALF, False) => (''lh    '')
-        | (HALF, True) => (''lhu   '')
-        | (WORD, False) => (''lw    '')
-        | (WORD, True) => (''lwu   '')
-        | (DOUBLE, False) => (''ld    '')
-        | (DOUBLE, True) => (''ldu   '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))"
-|" print_insn (STORE (imm,rs2,rs1,width,aq,rl)) = (
-      (let (insn :: string) =
-        ((case  width of
-          BYTE => (''sb    '')
-        | HALF => (''sh    '')
-        | WORD => (''sw    '')
-        | DOUBLE => (''sd    '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rs2))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))"
-|" print_insn (ADDIW (imm,rs1,rd)) = (
-      (op@) (''addiw '')
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))"
-|" print_insn (SHIFTW (shamt,rs1,rd,op1)) = (
-      (let (insn :: string) =
-        ((case  op1 of   RISCV_SLLI => (''slli  '') | RISCV_SRLI => (''srli  '') | RISCV_SRAI => (''srai  '') )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))"
-|" print_insn (RTYPEW (rs2,rs1,rd,op1)) = (
-      (let (insn :: string) =
-        ((case  op1 of
-          RISCV_ADDW => (''addw  '')
-        | RISCV_SUBW => (''subw  '')
-        | RISCV_SLLW => (''sllw  '')
-        | RISCV_SRLW => (''srlw  '')
-        | RISCV_SRAW => (''sraw  '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (MUL (rs2,rs1,rd,high,signed1,signed2)) = (
-      (let (insn :: string) =
-        ((case  (high, signed1, signed2) of
-          (False, True, True) => (''mul   '')
-        | (True, True, True) => (''mulh  '')
-        | (True, True, False) => (''mulhsu '')
-        | (True, False, False) => (''mulhu'')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (DIV (rs2,rs1,rd,s)) = (
-      (let (insn :: string) = (if s then (''div   '') else (''divu  '')) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (REM (rs2,rs1,rd,s)) = (
-      (let (insn :: string) = (if s then (''rem   '') else (''remu  '')) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (MULW (rs2,rs1,rd)) = (
-      (op@) (''mulw  '')
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))))))"
-|" print_insn (DIVW (rs2,rs1,rd,s)) = (
-      (let (insn :: string) = (if s then (''divw  '') else (''divuw '')) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (REMW (rs2,rs1,rd,s)) = (
-      (let (insn :: string) = (if s then (''remw  '') else (''remuw '')) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (FENCE (pred,succ)) = ( (''fence''))"
-|" print_insn (FENCEI (g__93)) = ( (''fence.i''))"
-|" print_insn (ECALL (g__94)) = ( (''ecall''))"
-|" print_insn (MRET (g__95)) = ( (''mret''))"
-|" print_insn (SRET (g__96)) = ( (''sret''))"
-|" print_insn (EBREAK (g__97)) = ( (''ebreak''))"
-|" print_insn (WFI (g__98)) = ( (''wfi''))"
-|" print_insn (SFENCE_VMA (rs1,rs2)) = (
-      (op@) (''sfence.vma '')
-        (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))"
-|" print_insn (LOADRES (aq,rl,rs1,width,rd)) = (
-      (let (insn :: string) =
-        ((case  width of   WORD => (''lr.w  '') | DOUBLE => (''lr.d  '') | _ => (''lr.bad '') )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((reg_name_abi rs1))))))))"
-|" print_insn (STORECON (aq,rl,rs2,rs1,width,rd)) = (
-      (let (insn :: string) =
-        ((case  width of   WORD => (''sc.w  '') | DOUBLE => (''sc.d  '') | _ => (''sc.bad '') )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (AMO (op1,aq,rl,rs2,rs1,width,rd)) = (
-      (let (insn :: string) =
-        ((case  (op1, width) of
-          (AMOSWAP, WORD) => (''amoswap.w '')
-        | (AMOADD, WORD) => (''amoadd.w  '')
-        | (AMOXOR, WORD) => (''amoxor.w  '')
-        | (AMOAND, WORD) => (''amoand.w  '')
-        | (AMOOR, WORD) => (''amoor.w   '')
-        | (AMOMIN, WORD) => (''amomin.w  '')
-        | (AMOMAX, WORD) => (''amomax.w  '')
-        | (AMOMINU, WORD) => (''amominu.w '')
-        | (AMOMAXU, WORD) => (''amomaxu.w '')
-        | (AMOSWAP, DOUBLE) => (''amoswap.d '')
-        | (AMOADD, DOUBLE) => (''amoadd.d  '')
-        | (AMOXOR, DOUBLE) => (''amoxor.d  '')
-        | (AMOAND, DOUBLE) => (''amoand.d  '')
-        | (AMOOR, DOUBLE) => (''amoor.d   '')
-        | (AMOMIN, DOUBLE) => (''amomin.d  '')
-        | (AMOMAX, DOUBLE) => (''amomax.d  '')
-        | (AMOMINU, DOUBLE) => (''amominu.d '')
-        | (AMOMAXU, DOUBLE) => (''amomaxu.d '')
-        | (_, _) => (''amo.bad '')
-        )) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '')
-                (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))"
-|" print_insn (CSR (csr,rs1,rd,is_imm,op1)) = (
-      (let (insn :: string) =
-        ((case  (op1, is_imm) of
-          (CSRRW, True) => (''csrrwi '')
-        | (CSRRW, False) => (''csrrw  '')
-        | (CSRRS, True) => (''csrrsi '')
-        | (CSRRS, False) => (''csrrs  '')
-        | (CSRRC, True) => (''csrrci '')
-        | (CSRRC, False) => (''csrrc  '')
-        )) in
-      (let (rs1_str :: string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in
-      (op@) insn
-        (((op@) ((reg_name_abi rd))
-            (((op@) ('', '') (((op@) rs1_str (((op@) ('', '') ((csr_name csr)))))))))))))"
-|" print_insn (NOP (g__99)) = ( (''nop''))"
-|" print_insn (ILLEGAL (g__100)) = ( (''illegal''))"
+     " print_insn (NOP (g__13)) = ( (''nop''))"
 |" print_insn (C_ADDI4SPN (rdc,nzimm)) = (
       (op@) (''c.addi4spn '')
         (((op@) ((reg_name_abi ((creg2reg_bits rdc  ::  5 Word.word))))
-            (((op@) ('', '') ((string_of_vec nzimm)))))))"
+            (((op@) ('', '') ((string_of_bits nzimm)))))))"
 |" print_insn (C_LW (uimm,rsc,rdc)) = (
       (op@) (''c.lw   '')
         (((op@) ((reg_name_abi ((creg2reg_bits rdc  ::  5 Word.word))))
             (((op@) ('', '')
                 (((op@) ((reg_name_abi ((creg2reg_bits rsc  ::  5 Word.word))))
-                    (((op@) ('', '') ((string_of_vec uimm)))))))))))"
+                    (((op@) ('', '') ((string_of_bits uimm)))))))))))"
 |" print_insn (C_LD (uimm,rsc,rdc)) = (
       (op@) (''c.ld   '')
         (((op@) ((reg_name_abi ((creg2reg_bits rdc  ::  5 Word.word))))
             (((op@) ('', '')
                 (((op@) ((reg_name_abi ((creg2reg_bits rsc  ::  5 Word.word))))
-                    (((op@) ('', '') ((string_of_vec uimm)))))))))))"
+                    (((op@) ('', '') ((string_of_bits uimm)))))))))))"
 |" print_insn (C_SW (uimm,rsc1,rsc2)) = (
       (op@) (''c.sw   '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsc1  ::  5 Word.word))))
             (((op@) ('', '')
                 (((op@) ((reg_name_abi ((creg2reg_bits rsc2  ::  5 Word.word))))
-                    (((op@) ('', '') ((string_of_vec uimm)))))))))))"
+                    (((op@) ('', '') ((string_of_bits uimm)))))))))))"
 |" print_insn (C_SD (uimm,rsc1,rsc2)) = (
       (op@) (''c.sd   '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsc1  ::  5 Word.word))))
             (((op@) ('', '')
                 (((op@) ((reg_name_abi ((creg2reg_bits rsc2  ::  5 Word.word))))
-                    (((op@) ('', '') ((string_of_vec uimm)))))))))))"
+                    (((op@) ('', '') ((string_of_bits uimm)))))))))))"
 |" print_insn (C_ADDI (nzi,rsd)) = (
       (op@) (''c.addi   '')
-        (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec nzi)))))))"
-|" print_insn (C_JAL (imm)) = ( (op@) (''c.jal   '') ((string_of_vec imm)))"
+        (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_bits nzi)))))))"
+|" print_insn (C_JAL (imm)) = ( (op@) (''c.jal   '') ((string_of_bits imm)))"
 |" print_insn (C_ADDIW (imm,rsd)) = (
       (op@) (''c.addiw '')
-        (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec imm)))))))"
+        (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_bits imm)))))))"
 |" print_insn (C_LI (imm,rd)) = (
       (op@) (''c.li  '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))"
-|" print_insn (C_ADDI16SP (imm)) = ( (op@) (''c.addi16sp  '') ((string_of_vec imm)))"
+        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits imm)))))))"
+|" print_insn (C_ADDI16SP (imm)) = ( (op@) (''c.addi16sp  '') ((string_of_bits imm)))"
 |" print_insn (C_LUI (imm,rd)) = (
       (op@) (''c.lui  '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))"
+        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits imm)))))))"
 |" print_insn (C_SRLI (shamt,rsd)) = (
       (op@) (''c.srli  '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsd  ::  5 Word.word))))
-            (((op@) ('', '') ((string_of_vec shamt)))))))"
+            (((op@) ('', '') ((string_of_bits shamt)))))))"
 |" print_insn (C_SRAI (shamt,rsd)) = (
       (op@) (''c.srai  '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsd  ::  5 Word.word))))
-            (((op@) ('', '') ((string_of_vec shamt)))))))"
+            (((op@) ('', '') ((string_of_bits shamt)))))))"
 |" print_insn (C_ANDI (imm,rsd)) = (
       (op@) (''c.andi  '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsd  ::  5 Word.word))))
-            (((op@) ('', '') ((string_of_vec imm)))))))"
+            (((op@) ('', '') ((string_of_bits imm)))))))"
 |" print_insn (C_SUB (rsd,rs2)) = (
       (op@) (''c.sub  '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsd  ::  5 Word.word))))
@@ -7417,30 +23856,30 @@ fun print_insn  :: " ast \<Rightarrow> string "  where
       (op@) (''c.addw '')
         (((op@) ((reg_name_abi ((creg2reg_bits rsd  ::  5 Word.word))))
             (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2  ::  5 Word.word)))))))))"
-|" print_insn (C_J (imm)) = ( (op@) (''c.j    '') ((string_of_vec imm)))"
+|" print_insn (C_J (imm)) = ( (op@) (''c.j    '') ((string_of_bits imm)))"
 |" print_insn (C_BEQZ (imm,rs)) = (
       (op@) (''c.beqz '')
         (((op@) ((reg_name_abi ((creg2reg_bits rs  ::  5 Word.word))))
-            (((op@) ('', '') ((string_of_vec imm)))))))"
+            (((op@) ('', '') ((string_of_bits imm)))))))"
 |" print_insn (C_BNEZ (imm,rs)) = (
       (op@) (''c.bnez '')
         (((op@) ((reg_name_abi ((creg2reg_bits rs  ::  5 Word.word))))
-            (((op@) ('', '') ((string_of_vec imm)))))))"
+            (((op@) ('', '') ((string_of_bits imm)))))))"
 |" print_insn (C_SLLI (shamt,rsd)) = (
       (op@) (''c.slli '')
-        (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec shamt)))))))"
+        (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_bits shamt)))))))"
 |" print_insn (C_LWSP (uimm,rd)) = (
       (op@) (''c.lwsp '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))"
+        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))"
 |" print_insn (C_LDSP (uimm,rd)) = (
       (op@) (''c.ldsp '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))"
+        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))"
 |" print_insn (C_SWSP (uimm,rd)) = (
       (op@) (''c.swsp '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))"
+        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))"
 |" print_insn (C_SDSP (uimm,rd)) = (
       (op@) (''c.sdsp '')
-        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))"
+        (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))"
 |" print_insn (C_JR (rs1)) = ( (op@) (''c.jr  '') ((reg_name_abi rs1)))"
 |" print_insn (C_JALR (rs1)) = ( (op@) (''c.jalr  '') ((reg_name_abi rs1)))"
 |" print_insn (C_MV (rd,rs2)) = (
@@ -7449,6 +23888,15 @@ fun print_insn  :: " ast \<Rightarrow> string "  where
 |" print_insn (C_ADD (rsd,rs2)) = (
       (op@) (''c.add  '')
         (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((reg_name_abi rs2)))))))"
+|" print_insn (STOP_FETCHING (g__14)) = ( (''stop_fetching''))"
+|" print_insn (THREAD_START (g__15)) = ( (''thread_start''))"
+|" print_insn (ILLEGAL (s)) = ( (op@) (''illegal '') ((string_of_bits s)))"
+|" print_insn (C_ILLEGAL (g__16)) = ( (''c.illegal''))"
+|" print_insn insn = ( assembly_forwards insn )"
+
+
+definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where 
+     " decode bv = ( Some ((encdec_backwards bv)))"
 
 
 (*val isRVC : mword ty16 -> bool*)
@@ -7505,77 +23953,554 @@ definition fetch  :: " unit \<Rightarrow>((register_value),(FetchResult),(except
      )))))"
 
 
-(*val step : unit -> M bool*)
+(*val step : ii -> M (bool * bool)*)
 
-definition step  :: " unit \<Rightarrow>((register_value),(bool),(exception))monad "  where 
-     " step _ = (
-   read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . 
-   read_reg mie_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . 
-   read_reg mideleg_ref \<bind> (\<lambda> (w__2 :: Minterrupts) . 
-   curInterrupt w__0 w__1 w__2 \<bind> (\<lambda> (w__3 ::  ((InterruptType * Privilege))option) . 
-   (case  w__3 of
+definition step  :: " int \<Rightarrow>((register_value),(bool*bool),(exception))monad "  where 
+     " step step_no = (
+   read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . 
+   read_reg mip_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . 
+   read_reg mie_ref \<bind> (\<lambda> (w__2 :: Minterrupts) . 
+   read_reg mideleg_ref \<bind> (\<lambda> (w__3 :: Minterrupts) . 
+   curInterrupt w__0 w__1 w__2 w__3 \<bind> (\<lambda> (w__4 ::  ((InterruptType * Privilege))option) . 
+   (case  w__4 of
      Some (intr,priv) =>
       (let (_ :: unit) = (print_bits (''Handling interrupt: '') ((interruptType_to_bits intr  ::  4 Word.word))) in
-      handle_interrupt intr priv \<then> return False)
+      handle_interrupt intr priv \<then> return (False, False))
    | None =>
-      fetch ()  \<bind> (\<lambda> (w__4 :: FetchResult) . 
-      (case  w__4 of
-        F_Error (e,addr) => handle_mem_exception addr e \<then> return False
+      fetch ()  \<bind> (\<lambda> (w__5 :: FetchResult) . 
+      (case  w__5 of
+        F_Error (e,addr) => handle_mem_exception addr e \<then> return (False, False)
       | F_RVC (h) =>
          (case  ((decodeCompressed h)) of
            None =>
-            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: xlenbits) . 
+            read_reg cur_privilege_ref \<bind> (\<lambda> (w__6 :: Privilege) . 
+            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: xlenbits) . 
             (let (_ :: unit) =
-              (prerr_endline
-                (((op@) (''PC: '')
-                    (((op@) ((string_of_vec w__5))
-                        (((op@) ('' instr: '')
-                            (((op@) ((string_of_vec h)) ('' :  <no-decode>'')))))))))) in
-            handle_decode_exception ((EXTZ (( 64 :: int)::ii) h  ::  64 Word.word)) \<then> return False))
+              (print_endline
+                (((op@) (''['')
+                    (((op@) ((stringFromInteger step_no))
+                        (((op@) (''] ['')
+                            (((op@) ((privLevel_to_str w__6))
+                                (((op@) ('']: '')
+                                    (((op@) ((string_of_bits w__7))
+                                        (((op@) ('' ('')
+                                            (((op@) ((string_of_bits h)) ('') <no-decode>'')))))))))))))))))) in
+            handle_decode_exception ((EXTZ (( 64 :: int)::ii) h  ::  64 Word.word)) \<then> return (False, True))))
          | Some (ast) =>
-            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: xlenbits) . 
+            read_reg cur_privilege_ref \<bind> (\<lambda> (w__8 :: Privilege) . 
+            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: xlenbits) . 
             (let (_ :: unit) =
-              (prerr_endline
-                (((op@) (''PC: '')
-                    (((op@) ((string_of_vec w__6))
-                        (((op@) ('' instr: '')
-                            (((op@) ((string_of_vec h))
-                                (((op@) ('' :  '') ((print_insn ast))))))))))))) in
-            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 ::  64 Word.word) . 
-            (write_reg nextPC_ref ((add_vec_int w__7 (( 2 :: int)::ii)  ::  64 Word.word)) \<then>
-            execute ast) \<then> return True)))
+              (print_endline
+                (((op@) (''['')
+                    (((op@) ((stringFromInteger step_no))
+                        (((op@) (''] ['')
+                            (((op@) ((privLevel_to_str w__8))
+                                (((op@) ('']: '')
+                                    (((op@) ((string_of_bits w__9))
+                                        (((op@) ('' ('')
+                                            (((op@) ((string_of_bits h))
+                                                (((op@) ('') '') ((print_insn ast))))))))))))))))))))) in
+            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 ::  64 Word.word) . 
+            (write_reg nextPC_ref ((add_vec_int w__10 (( 2 :: int)::ii)  ::  64 Word.word)) \<then>
+            execute ast) \<bind> (\<lambda> (w__11 :: bool) .  return (w__11, True))))))
          )
       | F_Base (w) =>
          (case  ((decode w)) of
            None =>
-            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: xlenbits) . 
+            read_reg cur_privilege_ref \<bind> (\<lambda> (w__13 :: Privilege) . 
+            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: xlenbits) . 
             (let (_ :: unit) =
-              (prerr_endline
-                (((op@) (''PC: '')
-                    (((op@) ((string_of_vec w__9))
-                        (((op@) ('' instr: '')
-                            (((op@) ((string_of_vec w)) ('' :  <no-decode>'')))))))))) in
-            handle_decode_exception ((EXTZ (( 64 :: int)::ii) w  ::  64 Word.word)) \<then> return False))
+              (print_endline
+                (((op@) (''['')
+                    (((op@) ((stringFromInteger step_no))
+                        (((op@) (''] ['')
+                            (((op@) ((privLevel_to_str w__13))
+                                (((op@) ('']: '')
+                                    (((op@) ((string_of_bits w__14))
+                                        (((op@) ('' ('')
+                                            (((op@) ((string_of_bits w)) ('') <no-decode>'')))))))))))))))))) in
+            handle_decode_exception ((EXTZ (( 64 :: int)::ii) w  ::  64 Word.word)) \<then> return (False, True))))
          | Some (ast) =>
-            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: xlenbits) . 
+            read_reg cur_privilege_ref \<bind> (\<lambda> (w__15 :: Privilege) . 
+            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: xlenbits) . 
             (let (_ :: unit) =
-              (prerr_endline
-                (((op@) (''PC: '')
-                    (((op@) ((string_of_vec w__10))
-                        (((op@) ('' instr: '')
-                            (((op@) ((string_of_vec w))
-                                (((op@) ('' :  '') ((print_insn ast))))))))))))) in
-            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 ::  64 Word.word) . 
-            (write_reg nextPC_ref ((add_vec_int w__11 (( 4 :: int)::ii)  ::  64 Word.word)) \<then>
-            execute ast) \<then> return True)))
+              (print_endline
+                (((op@) (''['')
+                    (((op@) ((stringFromInteger step_no))
+                        (((op@) (''] ['')
+                            (((op@) ((privLevel_to_str w__15))
+                                (((op@) ('']: '')
+                                    (((op@) ((string_of_bits w__16))
+                                        (((op@) ('' ('')
+                                            (((op@) ((string_of_bits w))
+                                                (((op@) ('') '') ((print_insn ast))))))))))))))))))))) in
+            (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 ::  64 Word.word) . 
+            (write_reg nextPC_ref ((add_vec_int w__17 (( 4 :: int)::ii)  ::  64 Word.word)) \<then>
+            execute ast) \<bind> (\<lambda> (w__18 :: bool) .  return (w__18, True))))))
          )
       ))
-   ))))))"
+   )))))))"
+
+
+(*val loop : unit -> M unit*)
+
+definition loop  :: " unit \<Rightarrow>((register_value),(unit),(exception))monad "  where 
+     " loop _ = (
+   (let insns_per_tick = (plat_insns_per_tick () ) in
+   (let (i :: ii) = ((( 0 :: int)::ii)) in
+   (let (step_no :: ii) = ((( 0 :: int)::ii)) in
+   (whileM (i, step_no)
+     (\<lambda> varstup .  (let (i, step_no) = varstup in
+       read_reg htif_done_ref \<bind> (\<lambda> (w__0 :: bool) .  return ((\<not> w__0)))))
+     (\<lambda> varstup .  (let (i, step_no) = varstup in
+       (write_reg minstret_written_ref False \<then>
+       step step_no) \<bind> (\<lambda> varstup .  (let (retired, stepped) = varstup in
+       (read_reg nextPC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: xlenbits) . 
+       (write_reg PC_ref w__1 \<then>
+       (if retired then retire_instruction () 
+        else return () )) \<then>
+       ((let (step_no :: ii) = (if stepped then ((ex_int step_no)) + (( 1 :: int)::ii) else step_no) in
+       read_reg htif_done_ref \<bind> (\<lambda> (w__2 :: bool) . 
+       (if w__2 then
+          (read_reg htif_exit_code_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . 
+          (let exit_val = (Word.uint w__3) in
+          return ((let _ =
+            (if (((exit_val = (( 0 :: int)::ii)))) then print_endline (''SUCCESS'')
+            else print_int (''FAILURE: '') exit_val) in
+          i))))
+        else
+          (let i = (((ex_int i)) + (( 1 :: int)::ii)) in
+          if (((((ex_int i)) = insns_per_tick))) then
+            (tick_clock ()  \<then> tick_platform () ) \<then> return (( 0 :: int)::ii)
+          else return i)) \<bind> (\<lambda> (i :: ii) . 
+       return (i, step_no))))))))))) \<bind> (\<lambda> varstup .  (let ((i :: ii), (step_no :: ii)) = varstup in
+   return () ))))))"
+
+
+(*val read_kind_of_num : integer -> read_kind*)
+
+definition read_kind_of_num  :: " int \<Rightarrow> read_kind "  where 
+     " read_kind_of_num arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Read_plain
+   else if (((p00 = (( 1 :: int)::ii)))) then Read_reserve
+   else if (((p00 = (( 2 :: int)::ii)))) then Read_acquire
+   else if (((p00 = (( 3 :: int)::ii)))) then Read_exclusive
+   else if (((p00 = (( 4 :: int)::ii)))) then Read_exclusive_acquire
+   else if (((p00 = (( 5 :: int)::ii)))) then Read_stream
+   else if (((p00 = (( 6 :: int)::ii)))) then Read_RISCV_acquire
+   else if (((p00 = (( 7 :: int)::ii)))) then Read_RISCV_strong_acquire
+   else if (((p00 = (( 8 :: int)::ii)))) then Read_RISCV_reserved
+   else if (((p00 = (( 9 :: int)::ii)))) then Read_RISCV_reserved_acquire
+   else if (((p00 = (( 10 :: int)::ii)))) then Read_RISCV_reserved_strong_acquire
+   else Read_X86_locked))"
+
+
+(*val num_of_read_kind : read_kind -> integer*)
+
+fun num_of_read_kind  :: " read_kind \<Rightarrow> int "  where 
+     " num_of_read_kind Read_plain = ( (( 0 :: int)::ii))"
+|" num_of_read_kind Read_reserve = ( (( 1 :: int)::ii))"
+|" num_of_read_kind Read_acquire = ( (( 2 :: int)::ii))"
+|" num_of_read_kind Read_exclusive = ( (( 3 :: int)::ii))"
+|" num_of_read_kind Read_exclusive_acquire = ( (( 4 :: int)::ii))"
+|" num_of_read_kind Read_stream = ( (( 5 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_acquire = ( (( 6 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_strong_acquire = ( (( 7 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved = ( (( 8 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved_acquire = ( (( 9 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved_strong_acquire = ( (( 10 :: int)::ii))"
+|" num_of_read_kind Read_X86_locked = ( (( 11 :: int)::ii))"
+
+
+(*val write_kind_of_num : integer -> write_kind*)
+
+definition write_kind_of_num  :: " int \<Rightarrow> write_kind "  where 
+     " write_kind_of_num arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Write_plain
+   else if (((p00 = (( 1 :: int)::ii)))) then Write_conditional
+   else if (((p00 = (( 2 :: int)::ii)))) then Write_release
+   else if (((p00 = (( 3 :: int)::ii)))) then Write_exclusive
+   else if (((p00 = (( 4 :: int)::ii)))) then Write_exclusive_release
+   else if (((p00 = (( 5 :: int)::ii)))) then Write_RISCV_release
+   else if (((p00 = (( 6 :: int)::ii)))) then Write_RISCV_strong_release
+   else if (((p00 = (( 7 :: int)::ii)))) then Write_RISCV_conditional
+   else if (((p00 = (( 8 :: int)::ii)))) then Write_RISCV_conditional_release
+   else if (((p00 = (( 9 :: int)::ii)))) then Write_RISCV_conditional_strong_release
+   else Write_X86_locked))"
+
+
+(*val num_of_write_kind : write_kind -> integer*)
+
+fun num_of_write_kind  :: " write_kind \<Rightarrow> int "  where 
+     " num_of_write_kind Write_plain = ( (( 0 :: int)::ii))"
+|" num_of_write_kind Write_conditional = ( (( 1 :: int)::ii))"
+|" num_of_write_kind Write_release = ( (( 2 :: int)::ii))"
+|" num_of_write_kind Write_exclusive = ( (( 3 :: int)::ii))"
+|" num_of_write_kind Write_exclusive_release = ( (( 4 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_release = ( (( 5 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_strong_release = ( (( 6 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional = ( (( 7 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional_release = ( (( 8 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional_strong_release = ( (( 9 :: int)::ii))"
+|" num_of_write_kind Write_X86_locked = ( (( 10 :: int)::ii))"
+
+
+(*val barrier_kind_of_num : integer -> barrier_kind*)
+
+definition barrier_kind_of_num  :: " int \<Rightarrow> barrier_kind "  where 
+     " barrier_kind_of_num arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Barrier_Sync
+   else if (((p00 = (( 1 :: int)::ii)))) then Barrier_LwSync
+   else if (((p00 = (( 2 :: int)::ii)))) then Barrier_Eieio
+   else if (((p00 = (( 3 :: int)::ii)))) then Barrier_Isync
+   else if (((p00 = (( 4 :: int)::ii)))) then Barrier_DMB
+   else if (((p00 = (( 5 :: int)::ii)))) then Barrier_DMB_ST
+   else if (((p00 = (( 6 :: int)::ii)))) then Barrier_DMB_LD
+   else if (((p00 = (( 7 :: int)::ii)))) then Barrier_DSB
+   else if (((p00 = (( 8 :: int)::ii)))) then Barrier_DSB_ST
+   else if (((p00 = (( 9 :: int)::ii)))) then Barrier_DSB_LD
+   else if (((p00 = (( 10 :: int)::ii)))) then Barrier_ISB
+   else if (((p00 = (( 11 :: int)::ii)))) then Barrier_MIPS_SYNC
+   else if (((p00 = (( 12 :: int)::ii)))) then Barrier_RISCV_rw_rw
+   else if (((p00 = (( 13 :: int)::ii)))) then Barrier_RISCV_r_rw
+   else if (((p00 = (( 14 :: int)::ii)))) then Barrier_RISCV_r_r
+   else if (((p00 = (( 15 :: int)::ii)))) then Barrier_RISCV_rw_w
+   else if (((p00 = (( 16 :: int)::ii)))) then Barrier_RISCV_w_w
+   else if (((p00 = (( 17 :: int)::ii)))) then Barrier_RISCV_w_rw
+   else if (((p00 = (( 18 :: int)::ii)))) then Barrier_RISCV_rw_r
+   else if (((p00 = (( 19 :: int)::ii)))) then Barrier_RISCV_r_w
+   else if (((p00 = (( 20 :: int)::ii)))) then Barrier_RISCV_w_r
+   else if (((p00 = (( 21 :: int)::ii)))) then Barrier_RISCV_i
+   else Barrier_x86_MFENCE))"
+
+
+(*val num_of_barrier_kind : barrier_kind -> integer*)
+
+fun num_of_barrier_kind  :: " barrier_kind \<Rightarrow> int "  where 
+     " num_of_barrier_kind Barrier_Sync = ( (( 0 :: int)::ii))"
+|" num_of_barrier_kind Barrier_LwSync = ( (( 1 :: int)::ii))"
+|" num_of_barrier_kind Barrier_Eieio = ( (( 2 :: int)::ii))"
+|" num_of_barrier_kind Barrier_Isync = ( (( 3 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB = ( (( 4 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB_ST = ( (( 5 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB_LD = ( (( 6 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB = ( (( 7 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB_ST = ( (( 8 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB_LD = ( (( 9 :: int)::ii))"
+|" num_of_barrier_kind Barrier_ISB = ( (( 10 :: int)::ii))"
+|" num_of_barrier_kind Barrier_MIPS_SYNC = ( (( 11 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_rw = ( (( 12 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_rw = ( (( 13 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_r = ( (( 14 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_w = ( (( 15 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_w = ( (( 16 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_rw = ( (( 17 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_r = ( (( 18 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_w = ( (( 19 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_r = ( (( 20 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_i = ( (( 21 :: int)::ii))"
+|" num_of_barrier_kind Barrier_x86_MFENCE = ( (( 22 :: int)::ii))"
+
+
+(*val trans_kind_of_num : integer -> trans_kind*)
+
+definition trans_kind_of_num  :: " int \<Rightarrow> trans_kind "  where 
+     " trans_kind_of_num arg0 = (
+   (let p00 = arg0 in
+   if (((p00 = (( 0 :: int)::ii)))) then Transaction_start
+   else if (((p00 = (( 1 :: int)::ii)))) then Transaction_commit
+   else Transaction_abort))"
+
+
+(*val num_of_trans_kind : trans_kind -> integer*)
+
+fun num_of_trans_kind  :: " trans_kind \<Rightarrow> int "  where 
+     " num_of_trans_kind Transaction_start = ( (( 0 :: int)::ii))"
+|" num_of_trans_kind Transaction_commit = ( (( 1 :: int)::ii))"
+|" num_of_trans_kind Transaction_abort = ( (( 2 :: int)::ii))"
+
+
+definition GPRstr  :: "(string)list "  where 
+     " GPRstr = (
+  [(''x31''),(''x30''),(''x29''),(''x28''),(''x27''),(''x26''),(''x25''),(''x24''),(''x23''),(''x22''),(''x21''),(''x20''),(''x19''),(''x18''),(''x17''),(''x16''),
+   (''x15''),(''x14''),(''x13''),(''x12''),(''x21''),(''x10''),(''x9''),(''x8''),(''x7''),(''x6''),(''x5''),(''x4''),(''x3''),(''x2''),(''x1''),(''x0'')])"
+
+
+definition CIA_fp  :: " regfp "  where 
+     " CIA_fp = ( RFull (''CIA''))"
+
+
+definition NIA_fp  :: " regfp "  where 
+     " NIA_fp = ( RFull (''NIA''))"
+
+
+(*val initial_analysis : ast -> M (list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)*)
+
+definition initial_analysis  :: " ast \<Rightarrow>((register_value),((regfp)list*(regfp)list*(regfp)list*(niafp)list*diafp*instruction_kind),(exception))monad "  where 
+     " initial_analysis instr = (
+   (let iR = ([]) in
+   (let oR = ([]) in
+   (let aR = ([]) in
+   (let ik = (IK_simple () ) in
+   (let Nias = ([NIAFP_successor () ]) in
+   (let Dia = (DIAFP_none () ) in
+   (case  instr of
+     EBREAK (_) => return (Nias, aR, iR, ik, oR)
+   | UTYPE (imm,rd,op1) =>
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR))
+   | RISCV_JAL (imm,rd) =>
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) in
+      (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
+      (let (Nias :: niafps) = ([NIAFP_concrete_address ((add_vec w__0 offset  ::  64 Word.word))]) in
+      (let (ik :: instruction_kind) = (IK_branch () ) in
+      return (Nias, aR, iR, ik, oR))))))
+   | RISCV_JALR (imm,rs,rd) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) in
+      (let (Nias :: niafps) = ([NIAFP_indirect_address () ]) in
+      (let (ik :: instruction_kind) = (IK_branch () ) in
+      return (Nias, aR, iR, ik, oR))))))
+   | BTYPE (imm,rs2,rs1,op1) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let ik = (IK_branch () ) in
+      (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) in
+      (read_reg PC_ref  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 ::  64 Word.word) . 
+      (let (Nias :: niafps) =
+        ([NIAFP_concrete_address ((add_vec w__1 offset  ::  64 Word.word)),NIAFP_successor () ]) in
+      return (Nias, aR, iR, ik, oR)))))))
+   | ITYPE (imm,rs,rd,op1) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR)))
+   | SHIFTIOP (imm,rs,rd,op1) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR)))
+   | RTYPE (rs2,rs1,rd,op1) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR))))
+   | CSR (csr,rs1,rd,is_imm,op1) =>
+      (let (isWrite :: bool) =
+        ((case  op1 of
+          CSRRW => True
+        | _ => if is_imm then (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii)) else (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii))
+        )) in
+      (let (iR :: regfps) = ((RFull ((csr_name csr))) # iR) in
+      (let (iR :: regfps) =
+        (if ((\<not> is_imm)) then (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR
+        else iR) in
+      (let (oR :: regfps) = (if isWrite then (RFull ((csr_name csr))) # oR else oR) in
+      (let (oR :: regfps) = ((RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR))))))
+   | LOAD (imm,rs,rd,unsign,width,aq,rl) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      (let aR = iR in
+      (case  (aq, rl) of
+        (False, False) => return (IK_mem_read Read_plain)
+      | (True, False) => return (IK_mem_read Read_RISCV_acquire)
+      | (True, True) => return (IK_mem_read Read_RISCV_strong_acquire)
+      | _ => internal_error (''LOAD type not implemented in initial_analysis'')
+      ) \<bind> (\<lambda> (w__3 :: instruction_kind) . 
+      (let (ik :: instruction_kind) = w__3 in
+      return (Nias, aR, iR, ik, oR))))))
+   | STORE (imm,rs2,rs1,width,aq,rl) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let (aR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then aR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # aR) in
+      (case  (aq, rl) of
+        (False, False) => return (IK_mem_write Write_plain)
+      | (False, True) => return (IK_mem_write Write_RISCV_release)
+      | (True, True) => return (IK_mem_write Write_RISCV_strong_release)
+      | _ => internal_error (''STORE type not implemented in initial_analysis'')
+      ) \<bind> (\<lambda> (w__5 :: instruction_kind) . 
+      (let (ik :: instruction_kind) = w__5 in
+      return (Nias, aR, iR, ik, oR))))))
+   | ADDIW (imm,rs,rd) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR)))
+   | SHIFTW (imm,rs,rd,op1) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR)))
+   | RTYPEW (rs2,rs1,rd,op1) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      return (Nias, aR, iR, ik, oR))))
+   | FENCE (pred,succ) =>
+      (case  (pred, succ) of
+        (v__276, v__277) =>
+         if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_rw_rw)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_r_rw)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_r_r)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_rw_w)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_w_w)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_w_rw)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_rw_r)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_r_w)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B1]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B1,B0]  ::  2 Word.word))))))) then
+           return (IK_barrier Barrier_RISCV_w_r)
+         else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii)  ::  2 Word.word)) = (vec_of_bits [B0,B0]  ::  2 Word.word))))))) then
+           return (IK_simple () )
+         else internal_error (''barrier type not implemented in initial_analysis'')
+      ) \<bind> (\<lambda> (w__17 :: instruction_kind) . 
+      (let (ik :: instruction_kind) = w__17 in
+      return (Nias, aR, iR, ik, oR)))
+   | FENCEI (_) =>
+      (let (ik :: instruction_kind) = (IK_barrier Barrier_RISCV_i) in
+      return (Nias, aR, iR, ik, oR))
+   | LOADRES (aq,rl,rs1,width,rd) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      (let aR = iR in
+      (case  (aq, rl) of
+        (False, False) => return (IK_mem_read Read_RISCV_reserved)
+      | (True, False) => return (IK_mem_read Read_RISCV_reserved_acquire)
+      | (True, True) => return (IK_mem_read Read_RISCV_reserved_strong_acquire)
+      | (False, True) => internal_error (''LOADRES type not implemented in initial_analysis'')
+      ) \<bind> (\<lambda> (w__19 :: instruction_kind) . 
+      (let (ik :: instruction_kind) = w__19 in
+      return (Nias, aR, iR, ik, oR))))))
+   | STORECON (aq,rl,rs2,rs1,width,rd) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let (aR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then aR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # aR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      (case  (aq, rl) of
+        (False, False) => return (IK_mem_write Write_RISCV_conditional)
+      | (False, True) => return (IK_mem_write Write_RISCV_conditional_release)
+      | (True, True) => return (IK_mem_write Write_RISCV_conditional_strong_release)
+      | (True, False) => internal_error (''STORECON type not implemented in initial_analysis'')
+      ) \<bind> (\<lambda> (w__21 :: instruction_kind) . 
+      (let (ik :: instruction_kind) = w__21 in
+      return (Nias, aR, iR, ik, oR)))))))
+   | AMO (op1,aq,rl,rs2,rs1,width,rd) =>
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in
+      (let (iR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in
+      (let (aR :: regfps) =
+        (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then aR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # aR) in
+      (let (oR :: regfps) =
+        (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+        else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in
+      (let (ik :: instruction_kind) =
+        ((case  (aq, rl) of
+          (False, False) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional)
+        | (False, True) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional_release)
+        | (True, False) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional)
+        | (True, True) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional_release)
+        )) in
+      return (Nias, aR, iR, ik, oR))))))
+   | _ => return (Nias, aR, iR, ik, oR)
+   ) \<bind> (\<lambda> varstup .  (let ((Nias :: niafps), (aR :: regfps), (iR :: regfps), (ik :: instruction_kind), (oR ::
+     regfps)) = varstup in
+   return (iR, oR, aR, Nias, Dia, ik))))))))))"
 
 
 definition initial_regstate  :: " regstate "  where 
      " initial_regstate = (
   (| tlb39 = None, 
+     htif_exit_code =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     htif_done = False, 
+     htif_tohost =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     mtimecmp =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
      tselect =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -7587,10 +24512,11 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
      scause =
-       (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                    ::  64 Word.word)), 
+       ((| Mcause_Mcause_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      sepc =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -7602,26 +24528,28 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
      stvec =
-       (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                   ::  64 Word.word)), 
+       ((| Mtvec_Mtvec_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      satp =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
      sideleg =
-       (Mk_Sinterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0]
-                         ::  64 Word.word)), 
+       ((| Sinterrupts_Sinterrupts_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      sedeleg =
-       (Mk_Sedeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                     ::  64 Word.word)), 
+       ((| Sedeleg_Sedeleg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      pmpcfg0 =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -7652,6 +24580,7 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
+     minstret_written = False, 
      minstret =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -7667,6 +24596,16 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
+     scounteren =
+       ((| Counteren_Counteren_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  32 Word.word)) |)), 
+     mcounteren =
+       ((| Counteren_Counteren_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  32 Word.word)) |)), 
      mscratch =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
@@ -7683,54 +24622,214 @@ definition initial_regstate  :: " regstate "  where
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
      mcause =
-       (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                    ::  64 Word.word)), 
+       ((| Mcause_Mcause_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      mtvec =
-       (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                               B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                   ::  64 Word.word)), 
+       ((| Mtvec_Mtvec_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      medeleg =
-       (Mk_Medeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                     ::  64 Word.word)), 
+       ((| Medeleg_Medeleg_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      mideleg =
-       (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0]
-                         ::  64 Word.word)), 
+       ((| Minterrupts_Minterrupts_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      mie =
-       (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0]
-                         ::  64 Word.word)), 
+       ((| Minterrupts_Minterrupts_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      mip =
-       (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                     B0]
-                         ::  64 Word.word)), 
+       ((| Minterrupts_Minterrupts_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      mstatus =
-       (Mk_Mstatus (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                                 B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                     ::  64 Word.word)), 
+       ((| Mstatus_Mstatus_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      misa =
-       (Mk_Misa (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                              B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                              B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-                  ::  64 Word.word)), 
+       ((| Misa_Misa_chunk_0 =
+             ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                           B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+               ::  64 Word.word)) |)), 
      cur_inst =
        ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                      B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
          ::  64 Word.word)), 
      cur_privilege = User, 
+     x31 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x30 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x29 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x28 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x27 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x26 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x25 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x24 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x23 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x22 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x21 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x20 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x19 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x18 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x17 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x16 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x15 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x14 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x13 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x12 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x11 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x10 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x9 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x8 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x7 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x6 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x5 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x4 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x3 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x2 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
+     x1 =
+       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
+         ::  64 Word.word)), 
      Xs =
        ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
                        B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
diff --git a/snapshots/isabelle/riscv/Riscv_duopod.thy b/snapshots/isabelle/riscv/Riscv_duopod.thy
deleted file mode 100644
index 9087ec9c..00000000
--- a/snapshots/isabelle/riscv/Riscv_duopod.thy
+++ /dev/null
@@ -1,461 +0,0 @@
-chapter \<open>Generated by Lem from riscv_duopod.lem.\<close>
-
-theory "Riscv_duopod" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
-	 "Riscv_duopod_types" 
-	 "Riscv_extras" 
-
-begin 
-
-(*Generated by Sail from riscv_duopod.*)
-(*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
-(*open import Riscv_duopod_types*)
-(*open import Riscv_extras*)
-
-
-
-
-
-
-
-
-
-(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
-
-
-
-(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*)
-
-
-
-(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*)
-
-(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*)
-
-definition GetSlice_int  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word "  where 
-     " GetSlice_int n m o1 = ( (get_slice_int0 n m o1  :: ( 'n::len)Word.word))"
-
-
-(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*)
-
-(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*)
-
-(*val cast_unit_vec : bitU -> mword ty1*)
-
-fun cast_unit_vec0  :: " bitU \<Rightarrow>(1)Word.word "  where 
-     " cast_unit_vec0 B0 = ( (vec_of_bits [B0]  ::  1 Word.word))"
-|" cast_unit_vec0 B1 = ( (vec_of_bits [B1]  ::  1 Word.word))"
-
-
-(*val DecStr : ii -> string*)
-
-(*val HexStr : ii -> string*)
-
-(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*)
-
-definition RISCV_write  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),(bool),(unit))monad "  where 
-     " RISCV_write addr width data = (
-   write_ram (( 64 :: int)::ii) width
-     (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                   B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                   B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-       ::  64 Word.word) addr data \<then>
-   return True )"
-
-
-(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*)
-
-(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*)
-
-definition RISCV_read  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(unit))monad "  where 
-     " RISCV_read addr width = (
-   (read_ram (( 64 :: int)::ii) width
-      (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                    B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-        ::  64 Word.word) addr
-     :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . 
-   return (Some w__0)))"
-
-
-(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*)
-
-(*val ex_nat : ii -> integer*)
-
-definition ex_nat  :: " int \<Rightarrow> int "  where 
-     " ex_nat n = ( n )"
-
-
-(*val ex_int : ii -> integer*)
-
-definition ex_int  :: " int \<Rightarrow> int "  where 
-     " ex_int n = ( n )"
-
-
-(*val coerce_int_nat : ii -> M ii*)
-
-definition coerce_int_nat  :: " int \<Rightarrow>((register_value),(int),(unit))monad "  where 
-     " coerce_int_nat x = ( assert_exp True ('''') \<then> return x )"
-
-
-(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
-
-(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
-
-definition EXTS  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
-     " EXTS (m__tv :: int) v = ( (sign_extend v m__tv  :: ( 'm::len)Word.word))"
-
-
-definition EXTZ  :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word "  where 
-     " EXTZ (m__tv :: int) v = ( (zero_extend v m__tv  :: ( 'm::len)Word.word))"
-
-
-(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
-
-(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
-
-(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
-
-(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
-
-(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
-
-definition zopz0zI_s  :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool "  where 
-     " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))"
-
-
-definition zopz0zKzJ_s  :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool "  where 
-     " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))"
-
-
-definition zopz0zI_u  :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool "  where 
-     " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))"
-
-
-definition zopz0zKzJ_u  :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool "  where 
-     " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))"
-
-
-definition zopz0zIzJ_u  :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool "  where 
-     " zopz0zIzJ_u x y = ( ((Word.uint x)) \<le> ((Word.uint y)))"
-
-
-(*val bool_to_bits : bool -> mword ty1*)
-
-definition bool_to_bits  :: " bool \<Rightarrow>(1)Word.word "  where 
-     " bool_to_bits x = ( if x then (vec_of_bits [B1]  ::  1 Word.word) else (vec_of_bits [B0]  ::  1 Word.word))"
-
-
-(*val bit_to_bool : bitU -> bool*)
-
-fun bit_to_bool  :: " bitU \<Rightarrow> bool "  where 
-     " bit_to_bool B1 = ( True )"
-|" bit_to_bool B0 = ( False )"
-
-
-(*val vector64 : ii -> mword ty64*)
-
-definition vector64  :: " int \<Rightarrow>(64)Word.word "  where 
-     " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii)  ::  64 Word.word))"
-
-
-(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*)
-
-definition to_bits  :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word "  where 
-     " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii)  :: ( 'l::len)Word.word))"
-
-
-(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*)
-
-definition shift_right_arith64  :: "(64)Word.word \<Rightarrow>(6)Word.word \<Rightarrow>(64)Word.word "  where 
-     " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = (
-   (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v  ::  128 Word.word)) in
-   (subrange_vec_dec ((shift_bits_right v128 shift  ::  128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii)  ::  64 Word.word)))"
-
-
-(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*)
-
-definition shift_right_arith32  :: "(32)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word.word "  where 
-     " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = (
-   (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v  ::  64 Word.word)) in
-   (subrange_vec_dec ((shift_bits_right v64 shift  ::  64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii)  ::  32 Word.word)))"
-
-
-(*val zeros : forall 'n. Size 'n => integer -> mword 'n*)
-
-definition zeros0  :: " int \<Rightarrow>('n::len)Word.word "  where 
-     " zeros0 n = ( (replicate_bits (vec_of_bits [B0]  ::  1 Word.word) n  :: ( 'n::len)Word.word))"
-
-
-(*val regbits_to_regno : mword ty5 -> integer*)
-
-definition regbits_to_regno  :: "(5)Word.word \<Rightarrow> int "  where 
-     " regbits_to_regno b = (
-   (let r = (Word.uint b) in
-   r))"
-
-
-(*val rX : integer -> M (mword ty64)*)
-
-definition rX  :: " int \<Rightarrow>((register_value),((64)Word.word),(unit))monad "  where 
-     " rX l__5 = (
-   if (((l__5 = (( 0 :: int)::ii)))) then
-     return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                          B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                          B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-              ::  64 Word.word)
-   else
-     read_reg Xs_ref \<bind> (\<lambda> (w__0 :: xlen_t list) . 
-     return ((access_list_dec w__0 l__5  ::  64 Word.word))))"
-
-
-(*val wX : integer -> mword ty64 -> M unit*)
-
-definition wX  :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(unit))monad "  where 
-     " wX r v = (
-   if (((r \<noteq> (( 0 :: int)::ii)))) then
-     read_reg Xs_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . 
-     write_reg Xs_ref ((update_list_dec w__0 r v  :: ( 64 Word.word) list)))
-   else return ()  )"
-
-
-(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (mword 'int8_times_n)*)
-
-definition MEMr  :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('int8_times_n::len)Word.word),(unit))monad "  where 
-     " MEMr addr width = (
-   (RISCV_read addr width  :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 ::
-      (( 'int8_times_n::len)Word.word)option) . 
-   return ((case  w__0 of
-     Some (v) => v
-   | None => (zeros0 (((( 8 :: int)::ii) * width))  :: ( 'int8_times_n::len)Word.word)
-   ))))"
-
-
-(*val iop_of_num : integer -> iop*)
-
-definition iop_of_num  :: " int \<Rightarrow> iop "  where 
-     " iop_of_num arg0 = (
-   (let l__0 = arg0 in
-   if (((l__0 = (( 0 :: int)::ii)))) then RISCV_ADDI
-   else if (((l__0 = (( 1 :: int)::ii)))) then RISCV_SLTI
-   else if (((l__0 = (( 2 :: int)::ii)))) then RISCV_SLTIU
-   else if (((l__0 = (( 3 :: int)::ii)))) then RISCV_XORI
-   else if (((l__0 = (( 4 :: int)::ii)))) then RISCV_ORI
-   else RISCV_ANDI))"
-
-
-(*val num_of_iop : iop -> integer*)
-
-fun num_of_iop  :: " iop \<Rightarrow> int "  where 
-     " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))"
-|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))"
-|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))"
-|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))"
-|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))"
-|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))"
-
-
-(*val decode : mword ty32 -> maybe ast*)
-
-(*val execute : ast -> M unit*)
-
-definition decode  :: "(32)Word.word \<Rightarrow>(ast)option "  where 
-     " decode v__0 = (
-   if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B0,B0]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (ITYPE (imm,rs1,rd,RISCV_ADDI)))))
-   else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii)  ::  3 Word.word)) = (vec_of_bits [B0,B1,B1]  ::  3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii)  ::  7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1]  ::  7 Word.word))))))) then
-     (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii)  ::  12 Word.word)) in
-     (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii)  ::  5 Word.word)) in
-     (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii)  ::  5 Word.word)) in
-     Some (LOAD (imm,rs1,rd)))))
-   else None )"
-
-
-(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> M unit*)
-
-definition execute_LOAD  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(unit))monad "  where 
-     " execute_LOAD imm rs1 rd = (
-   (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 ::  64 Word.word) . 
-   (let (addr :: xlen_t) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word))  ::  64 Word.word)) in
-   (MEMr addr (( 8 :: int)::ii)  :: ( 64 Word.word) M) \<bind> (\<lambda> (result :: xlen_t) . 
-   wX ((regbits_to_regno rd)) result))))"
-
-
-(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*)
-
-fun execute_ITYPE  :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(unit),(unit))monad "  where 
-     " execute_ITYPE imm rs1 rd RISCV_ADDI = (
-   (rX ((regbits_to_regno rs1))  :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . 
-   (let (imm_ext :: xlen_t) = ((EXTS (( 64 :: int)::ii) imm  ::  64 Word.word)) in
-   (let result = ((add_vec rs1_val imm_ext  ::  64 Word.word)) in
-   wX ((regbits_to_regno rd)) result))))"
-
-
-fun execute  :: " ast \<Rightarrow>((register_value),(unit),(unit))monad "  where 
-     " execute (ITYPE (imm,rs1,rd,arg3)) = ( execute_ITYPE imm rs1 rd arg3 )"
-|" execute (LOAD (imm,rs1,rd)) = ( execute_LOAD imm rs1 rd )"
-
-
-definition initial_regstate  :: " regstate "  where 
-     " initial_regstate = (
-  (| Xs =
-       ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word),
-         (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                       B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-           ::  64 Word.word)]), 
-     nextPC =
-       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-         ::  64 Word.word)), 
-     PC =
-       ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
-                     B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
-         ::  64 Word.word)) |) )"
-
-
-
-end
diff --git a/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy b/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy
deleted file mode 100644
index d6ca4d7d..00000000
--- a/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy
+++ /dev/null
@@ -1,48 +0,0 @@
-theory Riscv_duopod_lemmas
-  imports
-    Sail.Sail_values_lemmas
-    Sail.State_lemmas
-    Riscv_duopod
-begin
-
-abbreviation "liftS \<equiv> liftState (get_regval, set_regval)"
-
-lemmas register_defs = get_regval_def set_regval_def Xs_ref_def nextPC_ref_def PC_ref_def
-
-lemma regval_vector_64_dec_bit[simp]:
-  "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v"
-  by (auto simp: regval_of_vector_64_dec_bit_def)
-
-lemma vector_of_rv_rv_of_vector[simp]:
-  assumes "\<And>v. of_rv (rv_of v) = Some v"
-  shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v"
-proof -
-  from assms have "of_rv \<circ> rv_of = Some" by auto
-  then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def)
-qed
-
-lemma liftS_read_reg_Xs[simp]:
-  "liftS (read_reg Xs_ref) = readS (Xs \<circ> regstate)"
-  by (auto simp: liftState_read_reg_readS register_defs)
-
-lemma liftS_write_reg_Xs[simp]:
-  "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\<lambda>_. v)))"
-  by (auto simp: liftState_write_reg_updateS register_defs)
-
-lemma liftS_read_reg_nextPC[simp]:
-  "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)"
-  by (auto simp: liftState_read_reg_readS register_defs)
-
-lemma liftS_write_reg_nextPC[simp]:
-  "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
-  by (auto simp: liftState_write_reg_updateS register_defs)
-
-lemma liftS_read_reg_PC[simp]:
-  "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)"
-  by (auto simp: liftState_read_reg_readS register_defs)
-
-lemma liftS_write_reg_PC[simp]:
-  "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))"
-  by (auto simp: liftState_write_reg_updateS register_defs)
-
-end
diff --git a/snapshots/isabelle/riscv/Riscv_duopod_types.thy b/snapshots/isabelle/riscv/Riscv_duopod_types.thy
deleted file mode 100644
index 8e92ede0..00000000
--- a/snapshots/isabelle/riscv/Riscv_duopod_types.thy
+++ /dev/null
@@ -1,170 +0,0 @@
-chapter \<open>Generated by Lem from riscv_duopod_types.lem.\<close>
-
-theory "Riscv_duopod_types" 
-
-imports 
- 	 Main
-	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
-
-begin 
-
-(*Generated by Sail from riscv_duopod.*)
-(*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
-type_synonym 'n bits =" ( 'n::len)Word.word "
-
-
-
-type_synonym xlen  =" int "
-
-type_synonym xlen_t  =" 64 bits "
-
-type_synonym 'n regno  =" int "
-
-type_synonym regbits  =" 5 bits "
-
-datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI
-
-
-
-datatype ast  =
-    ITYPE " (( 12 bits * regbits * regbits * iop))" | LOAD " (( 12 bits * regbits * regbits))"
-
-
-
-datatype register_value  =
-    Regval_vector " ((ii * bool * register_value list))"
-  | Regval_list " ( register_value list)"
-  | Regval_option " ( register_value option)"
-  | Regval_vector_64_dec_bit " ( 64 Word.word)"
-
-
-
-record regstate  = 
- Xs ::" ( 64 Word.word) list " 
- nextPC ::"  64 Word.word " 
- PC ::"  64 Word.word "  
-
-
-
-
-
-(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
-
-fun vector_64_dec_bit_of_regval  :: " register_value \<Rightarrow>((64)Word.word)option "  where 
-     " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )"
-|" vector_64_dec_bit_of_regval g__6 = ( None )"
-
-
-(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
-
-definition regval_of_vector_64_dec_bit  :: "(64)Word.word \<Rightarrow> register_value "  where 
-     " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )"
-
-
-
-
-(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
-definition vector_of_regval  :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option "  where 
-     " vector_of_regval of_regval1 = ( \<lambda>x .  
-  (case  x of
-        Regval_vector (_, _, v) => just_list (List.map of_regval1 v)
-    | _ => None
-  ) )"
-
-
-(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
-definition regval_of_vector  :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value "  where 
-     " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))"
-
-
-(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
-definition list_of_regval  :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option "  where 
-     " list_of_regval of_regval1 = ( \<lambda>x .  
-  (case  x of
-        Regval_list v => just_list (List.map of_regval1 v)
-    | _ => None
-  ) )"
-
-
-(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
-definition regval_of_list  :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value "  where 
-     " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))"
-
-
-(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
-definition option_of_regval  :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option "  where 
-     " option_of_regval of_regval1 = ( \<lambda>x .  
-  (case  x of   Regval_option v => map_option of_regval1 v | _ => None ) )"
-
-
-(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
-definition regval_of_option  :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value "  where 
-     " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))"
-
-
-
-definition Xs_ref  :: "((regstate),(register_value),(((64)Word.word)list))register_ref "  where 
-     " Xs_ref = ( (|
-  name = (''Xs''),
-  read_from = (\<lambda> s . (Xs   s)),
-  write_to = (\<lambda> v s .  (( s (| Xs := v |)))),
-  of_regval = (\<lambda> v .  vector_of_regval (\<lambda> v .  vector_64_dec_bit_of_regval v) v),
-  regval_of = (\<lambda> v .  regval_of_vector (\<lambda> v .  regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )"
-
-
-definition nextPC_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
-     " nextPC_ref = ( (|
-  name = (''nextPC''),
-  read_from = (\<lambda> s . (nextPC   s)),
-  write_to = (\<lambda> v s .  (( s (| nextPC := v |)))),
-  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
-  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
-
-
-definition PC_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
-     " PC_ref = ( (|
-  name = (''PC''),
-  read_from = (\<lambda> s . (PC   s)),
-  write_to = (\<lambda> v s .  (( s (| PC := v |)))),
-  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
-  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
-
-
-(*val get_regval : string -> regstate -> maybe register_value*)
-definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option "  where 
-     " get_regval reg_name s = (
-  if reg_name = (''Xs'') then Some ((regval_of   Xs_ref) ((read_from   Xs_ref) s)) else
-  if reg_name = (''nextPC'') then Some ((regval_of   nextPC_ref) ((read_from   nextPC_ref) s)) else
-  if reg_name = (''PC'') then Some ((regval_of   PC_ref) ((read_from   PC_ref) s)) else
-  None )"
-
-
-(*val set_regval : string -> register_value -> regstate -> maybe regstate*)
-definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option "  where 
-     " set_regval reg_name v s = (
-  if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to   Xs_ref) v s) ((of_regval   Xs_ref) v) else
-  if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to   nextPC_ref) v s) ((of_regval   nextPC_ref) v) else
-  if reg_name = (''PC'') then map_option (\<lambda> v . (write_to   PC_ref) v s) ((of_regval   PC_ref) v) else
-  None )"
-
-
-definition register_accessors  :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)"  where 
-     " register_accessors = ( (get_regval, set_regval))"
-
-
-
-type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, unit) monadR "
-type_synonym 'a M =" (register_value, 'a, unit) monad "
-end
diff --git a/snapshots/isabelle/riscv/Riscv_extras.thy b/snapshots/isabelle/riscv/Riscv_extras.thy
index fc83385b..8e371170 100644
--- a/snapshots/isabelle/riscv/Riscv_extras.thy
+++ b/snapshots/isabelle/riscv/Riscv_extras.thy
@@ -6,21 +6,21 @@ imports
  	 Main
 	 "Lem_pervasives" 
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
 
 begin 
 
 (*open import Pervasives*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 
 type_synonym 'a bitvector =" ( 'a::len)Word.word "
 
@@ -39,6 +39,18 @@ definition MEM_fence_rw_w  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where
 definition MEM_fence_w_w  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where 
      " MEM_fence_w_w   _ = ( barrier Barrier_RISCV_w_w )"
 
+definition MEM_fence_w_rw  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where 
+     " MEM_fence_w_rw  _ = ( barrier Barrier_RISCV_w_rw )"
+
+definition MEM_fence_rw_r  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where 
+     " MEM_fence_rw_r  _ = ( barrier Barrier_RISCV_rw_r )"
+
+definition MEM_fence_r_w  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where 
+     " MEM_fence_r_w   _ = ( barrier Barrier_RISCV_r_w )"
+
+definition MEM_fence_w_r  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where 
+     " MEM_fence_w_r   _ = ( barrier Barrier_RISCV_w_r )"
+
 definition MEM_fence_i  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where 
      " MEM_fence_i     _ = ( barrier Barrier_RISCV_i )"
 
@@ -52,57 +64,148 @@ definition MEM_fence_i  :: " unit \<Rightarrow>('b,(unit),'a)monad "  where
 
 definition MEMea  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "                       where 
      " MEMea addr size1                      = ( write_mem_ea 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr size1 )"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addr size1 )"
 
 definition MEMea_release  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "               where 
      " MEMea_release addr size1              = ( write_mem_ea 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr size1 )"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr size1 )"
 
 definition MEMea_strong_release  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "        where 
      " MEMea_strong_release addr size1       = ( write_mem_ea 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr size1 )"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr size1 )"
 
 definition MEMea_conditional  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "           where 
      " MEMea_conditional addr size1          = ( write_mem_ea 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr size1 )"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr size1 )"
 
 definition MEMea_conditional_release  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "   where 
      " MEMea_conditional_release addr size1  = ( write_mem_ea 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr size1 )"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr size1 )"
 
 definition MEMea_conditional_strong_release  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " 
                                           where 
      " MEMea_conditional_strong_release addr size1
                                           = ( write_mem_ea 
-  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr size1 )"
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr size1 )"
+
+
+(*val MEMr                         : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_acquire                 : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_strong_acquire          : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved                : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_acquire        : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+
+definition MEMr  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "                          where 
+     " MEMr addrsize size1 hexRAM addr                         = ( read_mem 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addr size1 )"
+
+definition MEMr_acquire  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "                  where 
+     " MEMr_acquire addrsize size1 hexRAM addr                 = ( read_mem 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addr size1 )"
+
+definition MEMr_strong_acquire  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "           where 
+     " MEMr_strong_acquire addrsize size1 hexRAM addr          = ( read_mem 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addr size1 )"
+
+definition MEMr_reserved  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "                 where 
+     " MEMr_reserved addrsize size1 hexRAM addr                = ( read_mem 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addr size1 )"
+
+definition MEMr_reserved_acquire  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "         where 
+     " MEMr_reserved_acquire addrsize size1 hexRAM addr        = ( read_mem 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addr size1 )"
+
+definition MEMr_reserved_strong_acquire  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "  where 
+     " MEMr_reserved_strong_acquire addrsize size1 hexRAM addr = ( read_mem 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addr size1 )"
 
 
 (*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*)
 definition write_ram  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(unit),'e)monad "  where 
      " write_ram addrsize size1 hexRAM address value1 = (
-  (write_mem_ea instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \<then>
-  write_mem_val instance_Sail_values_Bitvector_Machine_word_mword_dict value1) \<bind>  (\<lambda>x .  (case  x of _ => return ()  )) )"
+  write_mem_val instance_Sail2_values_Bitvector_Machine_word_mword_dict value1 \<bind>  (\<lambda>x .  (case  x of _ => return ()  )) )"
 
 
 (*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
 definition read_ram  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad "  where 
      " read_ram addrsize size1 hexRAM address = (
-  read_mem instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )"
+  read_mem instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )"
+
+
+(*val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit*)
+definition load_reservation  :: "('a::len)Word.word \<Rightarrow> unit "  where 
+     " load_reservation addr = ( ()  )"
 
 
-definition speculate_conditional_success  :: " unit \<Rightarrow>('b,(bool),'a)monad "  where 
+definition speculate_conditional_success  :: " 'c \<Rightarrow>('b,(bool),'a)monad "  where 
      " speculate_conditional_success _ = ( excl_result ()  )"
 
 
-(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*)
-definition get_slice_int0  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " get_slice_int0 len n lo = (
-  (* TODO: Is this the intended behaviour? *)
-  (let hi = ((lo + len) -( 1 :: int)) in
-  (let bits = (bits_of_int (hi +( 1 :: int)) n) in
-  of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list False bits hi lo))))"
+definition cancel_reservation  :: " unit \<Rightarrow> unit "  where 
+     " cancel_reservation _ = ( ()  )"
+
+
+(*val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_ram_base  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_ram_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_ram_size  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_ram_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_rom_base  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_rom_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_rom_size  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_rom_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_clint_base  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_clint_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_clint_size  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_clint_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_enable_dirty_update : unit -> bool*)
+definition plat_enable_dirty_update  :: " unit \<Rightarrow> bool "  where 
+     " plat_enable_dirty_update _ = ( False )"
+
+
+(*val plat_enable_misaligned_access : unit -> bool*)
+definition plat_enable_misaligned_access  :: " unit \<Rightarrow> bool "  where 
+     " plat_enable_misaligned_access _ = ( False )"
+
+
+(*val plat_insns_per_tick : unit -> integer*)
+definition plat_insns_per_tick  :: " unit \<Rightarrow> int "  where 
+     " plat_insns_per_tick _ = (( 1 :: int))"
+
+
+(*val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_htif_tohost  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_htif_tohost _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+(*val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit*)
+definition plat_term_write  :: "('a::len)Word.word \<Rightarrow> unit "  where 
+     " plat_term_write _ = ( ()  )"
+
+
+(*val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a*)
+definition plat_term_read  :: " unit \<Rightarrow>('a::len)Word.word "  where 
+     " plat_term_read _ = ( Word.word_of_int(( 0 :: int)))"
 
 
 (*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
@@ -116,11 +219,21 @@ definition shift_bits_left  :: "('a::len)Word.word \<Rightarrow>('b::len)Word.wo
 
 (*val print_string : string -> string -> unit*)
 definition print_string  :: " string \<Rightarrow> string \<Rightarrow> unit "  where 
-     " print_string msg s = ( prerr_endline (msg @ s))"
+     " print_string msg s = ( ()  )"
+ (* print_endline (msg ^ s) *)
+
+(*val prerr_string : string -> string -> unit*)
+definition prerr_string  :: " string \<Rightarrow> string \<Rightarrow> unit "  where 
+     " prerr_string msg s = ( prerr_endline (msg @ s))"
+
+
+(*val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+definition prerr_bits  :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit "  where 
+     " prerr_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))"
 
 
 (*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
 definition print_bits  :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit "  where 
-     " print_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))"
-
+     " print_bits msg bs = ( ()  )"
+ (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
 end
diff --git a/snapshots/isabelle/riscv/Riscv_lemmas.thy b/snapshots/isabelle/riscv/Riscv_lemmas.thy
index 108208ca..cb159d68 100644
--- a/snapshots/isabelle/riscv/Riscv_lemmas.thy
+++ b/snapshots/isabelle/riscv/Riscv_lemmas.thy
@@ -1,19 +1,28 @@
 theory Riscv_lemmas
   imports
-    Sail.Sail_values_lemmas
-    Sail.State_lemmas
+    Sail.Sail2_values_lemmas
+    Sail.Sail2_state_lemmas
     Riscv
 begin
 
-abbreviation "liftS \<equiv> liftState (get_regval, set_regval)"
+abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)"
 
-lemmas register_defs = get_regval_def set_regval_def tlb39_ref_def tselect_ref_def stval_ref_def
+lemmas register_defs = get_regval_def set_regval_def tlb39_ref_def htif_exit_code_ref_def
+  htif_done_ref_def htif_tohost_ref_def mtimecmp_ref_def tselect_ref_def stval_ref_def
   scause_ref_def sepc_ref_def sscratch_ref_def stvec_ref_def satp_ref_def sideleg_ref_def
   sedeleg_ref_def pmpcfg0_ref_def pmpaddr0_ref_def mhartid_ref_def marchid_ref_def mimpid_ref_def
-  mvendorid_ref_def minstret_ref_def mtime_ref_def mcycle_ref_def mscratch_ref_def mtval_ref_def
-  mepc_ref_def mcause_ref_def mtvec_ref_def medeleg_ref_def mideleg_ref_def mie_ref_def mip_ref_def
-  mstatus_ref_def misa_ref_def cur_inst_ref_def cur_privilege_ref_def Xs_ref_def nextPC_ref_def
-  PC_ref_def
+  mvendorid_ref_def minstret_written_ref_def minstret_ref_def mtime_ref_def mcycle_ref_def
+  scounteren_ref_def mcounteren_ref_def mscratch_ref_def mtval_ref_def mepc_ref_def mcause_ref_def
+  mtvec_ref_def medeleg_ref_def mideleg_ref_def mie_ref_def mip_ref_def mstatus_ref_def misa_ref_def
+  cur_inst_ref_def cur_privilege_ref_def x31_ref_def x30_ref_def x29_ref_def x28_ref_def x27_ref_def
+  x26_ref_def x25_ref_def x24_ref_def x23_ref_def x22_ref_def x21_ref_def x20_ref_def x19_ref_def
+  x18_ref_def x17_ref_def x16_ref_def x15_ref_def x14_ref_def x13_ref_def x12_ref_def x11_ref_def
+  x10_ref_def x9_ref_def x8_ref_def x7_ref_def x6_ref_def x5_ref_def x4_ref_def x3_ref_def
+  x2_ref_def x1_ref_def Xs_ref_def nextPC_ref_def PC_ref_def
+
+lemma regval_Counteren[simp]:
+  "Counteren_of_regval (regval_of_Counteren v) = Some v"
+  by (auto simp: regval_of_Counteren_def)
 
 lemma regval_Mcause[simp]:
   "Mcause_of_regval (regval_of_Mcause v) = Some v"
@@ -55,6 +64,10 @@ lemma regval_TLB39_Entry[simp]:
   "TLB39_Entry_of_regval (regval_of_TLB39_Entry v) = Some v"
   by (auto simp: regval_of_TLB39_Entry_def)
 
+lemma regval_bool[simp]:
+  "bool_of_regval (regval_of_bool v) = Some v"
+  by (auto simp: regval_of_bool_def)
+
 lemma regval_vector_64_dec_bit[simp]:
   "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v"
   by (auto simp: regval_of_vector_64_dec_bit_def)
@@ -80,284 +93,588 @@ proof -
   with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def)
 qed
 
-lemma liftS_read_reg_tlb39[simp]:
-  "liftS (read_reg tlb39_ref) = readS (tlb39 \<circ> regstate)"
+lemma liftS_read_reg_tlb39[liftState_simp]:
+  "\<lbrakk>read_reg tlb39_ref\<rbrakk>\<^sub>S = readS (tlb39 \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tlb39[liftState_simp]:
+  "\<lbrakk>write_reg tlb39_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tlb39_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_exit_code[liftState_simp]:
+  "\<lbrakk>read_reg htif_exit_code_ref\<rbrakk>\<^sub>S = readS (htif_exit_code \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_exit_code[liftState_simp]:
+  "\<lbrakk>write_reg htif_exit_code_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_exit_code_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_done[liftState_simp]:
+  "\<lbrakk>read_reg htif_done_ref\<rbrakk>\<^sub>S = readS (htif_done \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_done[liftState_simp]:
+  "\<lbrakk>write_reg htif_done_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_done_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_tohost[liftState_simp]:
+  "\<lbrakk>read_reg htif_tohost_ref\<rbrakk>\<^sub>S = readS (htif_tohost \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_tohost[liftState_simp]:
+  "\<lbrakk>write_reg htif_tohost_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_tohost_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtimecmp[liftState_simp]:
+  "\<lbrakk>read_reg mtimecmp_ref\<rbrakk>\<^sub>S = readS (mtimecmp \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtimecmp[liftState_simp]:
+  "\<lbrakk>write_reg mtimecmp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtimecmp_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_tselect[liftState_simp]:
+  "\<lbrakk>read_reg tselect_ref\<rbrakk>\<^sub>S = readS (tselect \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tselect[liftState_simp]:
+  "\<lbrakk>write_reg tselect_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tselect_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_stval[liftState_simp]:
+  "\<lbrakk>read_reg stval_ref\<rbrakk>\<^sub>S = readS (stval \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_stval[liftState_simp]:
+  "\<lbrakk>write_reg stval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stval_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_scause[liftState_simp]:
+  "\<lbrakk>read_reg scause_ref\<rbrakk>\<^sub>S = readS (scause \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_scause[liftState_simp]:
+  "\<lbrakk>write_reg scause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scause_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sepc[liftState_simp]:
+  "\<lbrakk>read_reg sepc_ref\<rbrakk>\<^sub>S = readS (sepc \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sepc[liftState_simp]:
+  "\<lbrakk>write_reg sepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sepc_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sscratch[liftState_simp]:
+  "\<lbrakk>read_reg sscratch_ref\<rbrakk>\<^sub>S = readS (sscratch \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sscratch[liftState_simp]:
+  "\<lbrakk>write_reg sscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sscratch_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_stvec[liftState_simp]:
+  "\<lbrakk>read_reg stvec_ref\<rbrakk>\<^sub>S = readS (stvec \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_stvec[liftState_simp]:
+  "\<lbrakk>write_reg stvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stvec_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_satp[liftState_simp]:
+  "\<lbrakk>read_reg satp_ref\<rbrakk>\<^sub>S = readS (satp \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_satp[liftState_simp]:
+  "\<lbrakk>write_reg satp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (satp_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sideleg[liftState_simp]:
+  "\<lbrakk>read_reg sideleg_ref\<rbrakk>\<^sub>S = readS (sideleg \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sideleg[liftState_simp]:
+  "\<lbrakk>write_reg sideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sideleg_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sedeleg[liftState_simp]:
+  "\<lbrakk>read_reg sedeleg_ref\<rbrakk>\<^sub>S = readS (sedeleg \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sedeleg[liftState_simp]:
+  "\<lbrakk>write_reg sedeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpcfg0[liftState_simp]:
+  "\<lbrakk>read_reg pmpcfg0_ref\<rbrakk>\<^sub>S = readS (pmpcfg0 \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpcfg0[liftState_simp]:
+  "\<lbrakk>write_reg pmpcfg0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpcfg0_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr0[liftState_simp]:
+  "\<lbrakk>read_reg pmpaddr0_ref\<rbrakk>\<^sub>S = readS (pmpaddr0 \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr0[liftState_simp]:
+  "\<lbrakk>write_reg pmpaddr0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mhartid[liftState_simp]:
+  "\<lbrakk>read_reg mhartid_ref\<rbrakk>\<^sub>S = readS (mhartid \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mhartid[liftState_simp]:
+  "\<lbrakk>write_reg mhartid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mhartid_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_marchid[liftState_simp]:
+  "\<lbrakk>read_reg marchid_ref\<rbrakk>\<^sub>S = readS (marchid \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_marchid[liftState_simp]:
+  "\<lbrakk>write_reg marchid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (marchid_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mimpid[liftState_simp]:
+  "\<lbrakk>read_reg mimpid_ref\<rbrakk>\<^sub>S = readS (mimpid \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mimpid[liftState_simp]:
+  "\<lbrakk>write_reg mimpid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mimpid_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mvendorid[liftState_simp]:
+  "\<lbrakk>read_reg mvendorid_ref\<rbrakk>\<^sub>S = readS (mvendorid \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mvendorid[liftState_simp]:
+  "\<lbrakk>write_reg mvendorid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_minstret_written[liftState_simp]:
+  "\<lbrakk>read_reg minstret_written_ref\<rbrakk>\<^sub>S = readS (minstret_written \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_minstret_written[liftState_simp]:
+  "\<lbrakk>write_reg minstret_written_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_written_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_minstret[liftState_simp]:
+  "\<lbrakk>read_reg minstret_ref\<rbrakk>\<^sub>S = readS (minstret \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_minstret[liftState_simp]:
+  "\<lbrakk>write_reg minstret_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtime[liftState_simp]:
+  "\<lbrakk>read_reg mtime_ref\<rbrakk>\<^sub>S = readS (mtime \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtime[liftState_simp]:
+  "\<lbrakk>write_reg mtime_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtime_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcycle[liftState_simp]:
+  "\<lbrakk>read_reg mcycle_ref\<rbrakk>\<^sub>S = readS (mcycle \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcycle[liftState_simp]:
+  "\<lbrakk>write_reg mcycle_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcycle_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_scounteren[liftState_simp]:
+  "\<lbrakk>read_reg scounteren_ref\<rbrakk>\<^sub>S = readS (scounteren \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_scounteren[liftState_simp]:
+  "\<lbrakk>write_reg scounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scounteren_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcounteren[liftState_simp]:
+  "\<lbrakk>read_reg mcounteren_ref\<rbrakk>\<^sub>S = readS (mcounteren \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcounteren[liftState_simp]:
+  "\<lbrakk>write_reg mcounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcounteren_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mscratch[liftState_simp]:
+  "\<lbrakk>read_reg mscratch_ref\<rbrakk>\<^sub>S = readS (mscratch \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mscratch[liftState_simp]:
+  "\<lbrakk>write_reg mscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mscratch_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtval[liftState_simp]:
+  "\<lbrakk>read_reg mtval_ref\<rbrakk>\<^sub>S = readS (mtval \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtval[liftState_simp]:
+  "\<lbrakk>write_reg mtval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtval_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mepc[liftState_simp]:
+  "\<lbrakk>read_reg mepc_ref\<rbrakk>\<^sub>S = readS (mepc \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mepc[liftState_simp]:
+  "\<lbrakk>write_reg mepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mepc_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcause[liftState_simp]:
+  "\<lbrakk>read_reg mcause_ref\<rbrakk>\<^sub>S = readS (mcause \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcause[liftState_simp]:
+  "\<lbrakk>write_reg mcause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcause_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtvec[liftState_simp]:
+  "\<lbrakk>read_reg mtvec_ref\<rbrakk>\<^sub>S = readS (mtvec \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtvec[liftState_simp]:
+  "\<lbrakk>write_reg mtvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtvec_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_medeleg[liftState_simp]:
+  "\<lbrakk>read_reg medeleg_ref\<rbrakk>\<^sub>S = readS (medeleg \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_medeleg[liftState_simp]:
+  "\<lbrakk>write_reg medeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (medeleg_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mideleg[liftState_simp]:
+  "\<lbrakk>read_reg mideleg_ref\<rbrakk>\<^sub>S = readS (mideleg \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mideleg[liftState_simp]:
+  "\<lbrakk>write_reg mideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mideleg_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mie[liftState_simp]:
+  "\<lbrakk>read_reg mie_ref\<rbrakk>\<^sub>S = readS (mie \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mie[liftState_simp]:
+  "\<lbrakk>write_reg mie_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mie_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mip[liftState_simp]:
+  "\<lbrakk>read_reg mip_ref\<rbrakk>\<^sub>S = readS (mip \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mip[liftState_simp]:
+  "\<lbrakk>write_reg mip_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mip_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mstatus[liftState_simp]:
+  "\<lbrakk>read_reg mstatus_ref\<rbrakk>\<^sub>S = readS (mstatus \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mstatus[liftState_simp]:
+  "\<lbrakk>write_reg mstatus_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mstatus_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_misa[liftState_simp]:
+  "\<lbrakk>read_reg misa_ref\<rbrakk>\<^sub>S = readS (misa \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_misa[liftState_simp]:
+  "\<lbrakk>write_reg misa_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (misa_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_cur_inst[liftState_simp]:
+  "\<lbrakk>read_reg cur_inst_ref\<rbrakk>\<^sub>S = readS (cur_inst \<circ> regstate)"
+  by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_cur_inst[liftState_simp]:
+  "\<lbrakk>write_reg cur_inst_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))"
+  by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_cur_privilege[liftState_simp]:
+  "\<lbrakk>read_reg cur_privilege_ref\<rbrakk>\<^sub>S = readS (cur_privilege \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_tlb39[simp]:
-  "liftS (write_reg tlb39_ref v) = updateS (regstate_update (tlb39_update (\<lambda>_. v)))"
+lemma liftS_write_reg_cur_privilege[liftState_simp]:
+  "\<lbrakk>write_reg cur_privilege_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_tselect[simp]:
-  "liftS (read_reg tselect_ref) = readS (tselect \<circ> regstate)"
+lemma liftS_read_reg_x31[liftState_simp]:
+  "\<lbrakk>read_reg x31_ref\<rbrakk>\<^sub>S = readS (x31 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_tselect[simp]:
-  "liftS (write_reg tselect_ref v) = updateS (regstate_update (tselect_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x31[liftState_simp]:
+  "\<lbrakk>write_reg x31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x31_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_stval[simp]:
-  "liftS (read_reg stval_ref) = readS (stval \<circ> regstate)"
+lemma liftS_read_reg_x30[liftState_simp]:
+  "\<lbrakk>read_reg x30_ref\<rbrakk>\<^sub>S = readS (x30 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_stval[simp]:
-  "liftS (write_reg stval_ref v) = updateS (regstate_update (stval_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x30[liftState_simp]:
+  "\<lbrakk>write_reg x30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x30_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_scause[simp]:
-  "liftS (read_reg scause_ref) = readS (scause \<circ> regstate)"
+lemma liftS_read_reg_x29[liftState_simp]:
+  "\<lbrakk>read_reg x29_ref\<rbrakk>\<^sub>S = readS (x29 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_scause[simp]:
-  "liftS (write_reg scause_ref v) = updateS (regstate_update (scause_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x29[liftState_simp]:
+  "\<lbrakk>write_reg x29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x29_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_sepc[simp]:
-  "liftS (read_reg sepc_ref) = readS (sepc \<circ> regstate)"
+lemma liftS_read_reg_x28[liftState_simp]:
+  "\<lbrakk>read_reg x28_ref\<rbrakk>\<^sub>S = readS (x28 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_sepc[simp]:
-  "liftS (write_reg sepc_ref v) = updateS (regstate_update (sepc_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x28[liftState_simp]:
+  "\<lbrakk>write_reg x28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x28_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_sscratch[simp]:
-  "liftS (read_reg sscratch_ref) = readS (sscratch \<circ> regstate)"
+lemma liftS_read_reg_x27[liftState_simp]:
+  "\<lbrakk>read_reg x27_ref\<rbrakk>\<^sub>S = readS (x27 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_sscratch[simp]:
-  "liftS (write_reg sscratch_ref v) = updateS (regstate_update (sscratch_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x27[liftState_simp]:
+  "\<lbrakk>write_reg x27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x27_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_stvec[simp]:
-  "liftS (read_reg stvec_ref) = readS (stvec \<circ> regstate)"
+lemma liftS_read_reg_x26[liftState_simp]:
+  "\<lbrakk>read_reg x26_ref\<rbrakk>\<^sub>S = readS (x26 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_stvec[simp]:
-  "liftS (write_reg stvec_ref v) = updateS (regstate_update (stvec_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x26[liftState_simp]:
+  "\<lbrakk>write_reg x26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x26_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_satp[simp]:
-  "liftS (read_reg satp_ref) = readS (satp \<circ> regstate)"
+lemma liftS_read_reg_x25[liftState_simp]:
+  "\<lbrakk>read_reg x25_ref\<rbrakk>\<^sub>S = readS (x25 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_satp[simp]:
-  "liftS (write_reg satp_ref v) = updateS (regstate_update (satp_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x25[liftState_simp]:
+  "\<lbrakk>write_reg x25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x25_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_sideleg[simp]:
-  "liftS (read_reg sideleg_ref) = readS (sideleg \<circ> regstate)"
+lemma liftS_read_reg_x24[liftState_simp]:
+  "\<lbrakk>read_reg x24_ref\<rbrakk>\<^sub>S = readS (x24 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_sideleg[simp]:
-  "liftS (write_reg sideleg_ref v) = updateS (regstate_update (sideleg_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x24[liftState_simp]:
+  "\<lbrakk>write_reg x24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x24_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_sedeleg[simp]:
-  "liftS (read_reg sedeleg_ref) = readS (sedeleg \<circ> regstate)"
+lemma liftS_read_reg_x23[liftState_simp]:
+  "\<lbrakk>read_reg x23_ref\<rbrakk>\<^sub>S = readS (x23 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_sedeleg[simp]:
-  "liftS (write_reg sedeleg_ref v) = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x23[liftState_simp]:
+  "\<lbrakk>write_reg x23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x23_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_pmpcfg0[simp]:
-  "liftS (read_reg pmpcfg0_ref) = readS (pmpcfg0 \<circ> regstate)"
+lemma liftS_read_reg_x22[liftState_simp]:
+  "\<lbrakk>read_reg x22_ref\<rbrakk>\<^sub>S = readS (x22 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_pmpcfg0[simp]:
-  "liftS (write_reg pmpcfg0_ref v) = updateS (regstate_update (pmpcfg0_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x22[liftState_simp]:
+  "\<lbrakk>write_reg x22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x22_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_pmpaddr0[simp]:
-  "liftS (read_reg pmpaddr0_ref) = readS (pmpaddr0 \<circ> regstate)"
+lemma liftS_read_reg_x21[liftState_simp]:
+  "\<lbrakk>read_reg x21_ref\<rbrakk>\<^sub>S = readS (x21 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_pmpaddr0[simp]:
-  "liftS (write_reg pmpaddr0_ref v) = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x21[liftState_simp]:
+  "\<lbrakk>write_reg x21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x21_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mhartid[simp]:
-  "liftS (read_reg mhartid_ref) = readS (mhartid \<circ> regstate)"
+lemma liftS_read_reg_x20[liftState_simp]:
+  "\<lbrakk>read_reg x20_ref\<rbrakk>\<^sub>S = readS (x20 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mhartid[simp]:
-  "liftS (write_reg mhartid_ref v) = updateS (regstate_update (mhartid_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x20[liftState_simp]:
+  "\<lbrakk>write_reg x20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x20_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_marchid[simp]:
-  "liftS (read_reg marchid_ref) = readS (marchid \<circ> regstate)"
+lemma liftS_read_reg_x19[liftState_simp]:
+  "\<lbrakk>read_reg x19_ref\<rbrakk>\<^sub>S = readS (x19 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_marchid[simp]:
-  "liftS (write_reg marchid_ref v) = updateS (regstate_update (marchid_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x19[liftState_simp]:
+  "\<lbrakk>write_reg x19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x19_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mimpid[simp]:
-  "liftS (read_reg mimpid_ref) = readS (mimpid \<circ> regstate)"
+lemma liftS_read_reg_x18[liftState_simp]:
+  "\<lbrakk>read_reg x18_ref\<rbrakk>\<^sub>S = readS (x18 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mimpid[simp]:
-  "liftS (write_reg mimpid_ref v) = updateS (regstate_update (mimpid_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x18[liftState_simp]:
+  "\<lbrakk>write_reg x18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x18_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mvendorid[simp]:
-  "liftS (read_reg mvendorid_ref) = readS (mvendorid \<circ> regstate)"
+lemma liftS_read_reg_x17[liftState_simp]:
+  "\<lbrakk>read_reg x17_ref\<rbrakk>\<^sub>S = readS (x17 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mvendorid[simp]:
-  "liftS (write_reg mvendorid_ref v) = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x17[liftState_simp]:
+  "\<lbrakk>write_reg x17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x17_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_minstret[simp]:
-  "liftS (read_reg minstret_ref) = readS (minstret \<circ> regstate)"
+lemma liftS_read_reg_x16[liftState_simp]:
+  "\<lbrakk>read_reg x16_ref\<rbrakk>\<^sub>S = readS (x16 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_minstret[simp]:
-  "liftS (write_reg minstret_ref v) = updateS (regstate_update (minstret_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x16[liftState_simp]:
+  "\<lbrakk>write_reg x16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x16_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mtime[simp]:
-  "liftS (read_reg mtime_ref) = readS (mtime \<circ> regstate)"
+lemma liftS_read_reg_x15[liftState_simp]:
+  "\<lbrakk>read_reg x15_ref\<rbrakk>\<^sub>S = readS (x15 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mtime[simp]:
-  "liftS (write_reg mtime_ref v) = updateS (regstate_update (mtime_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x15[liftState_simp]:
+  "\<lbrakk>write_reg x15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x15_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mcycle[simp]:
-  "liftS (read_reg mcycle_ref) = readS (mcycle \<circ> regstate)"
+lemma liftS_read_reg_x14[liftState_simp]:
+  "\<lbrakk>read_reg x14_ref\<rbrakk>\<^sub>S = readS (x14 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mcycle[simp]:
-  "liftS (write_reg mcycle_ref v) = updateS (regstate_update (mcycle_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x14[liftState_simp]:
+  "\<lbrakk>write_reg x14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x14_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mscratch[simp]:
-  "liftS (read_reg mscratch_ref) = readS (mscratch \<circ> regstate)"
+lemma liftS_read_reg_x13[liftState_simp]:
+  "\<lbrakk>read_reg x13_ref\<rbrakk>\<^sub>S = readS (x13 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mscratch[simp]:
-  "liftS (write_reg mscratch_ref v) = updateS (regstate_update (mscratch_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x13[liftState_simp]:
+  "\<lbrakk>write_reg x13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x13_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mtval[simp]:
-  "liftS (read_reg mtval_ref) = readS (mtval \<circ> regstate)"
+lemma liftS_read_reg_x12[liftState_simp]:
+  "\<lbrakk>read_reg x12_ref\<rbrakk>\<^sub>S = readS (x12 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mtval[simp]:
-  "liftS (write_reg mtval_ref v) = updateS (regstate_update (mtval_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x12[liftState_simp]:
+  "\<lbrakk>write_reg x12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x12_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mepc[simp]:
-  "liftS (read_reg mepc_ref) = readS (mepc \<circ> regstate)"
+lemma liftS_read_reg_x11[liftState_simp]:
+  "\<lbrakk>read_reg x11_ref\<rbrakk>\<^sub>S = readS (x11 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mepc[simp]:
-  "liftS (write_reg mepc_ref v) = updateS (regstate_update (mepc_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x11[liftState_simp]:
+  "\<lbrakk>write_reg x11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x11_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mcause[simp]:
-  "liftS (read_reg mcause_ref) = readS (mcause \<circ> regstate)"
+lemma liftS_read_reg_x10[liftState_simp]:
+  "\<lbrakk>read_reg x10_ref\<rbrakk>\<^sub>S = readS (x10 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mcause[simp]:
-  "liftS (write_reg mcause_ref v) = updateS (regstate_update (mcause_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x10[liftState_simp]:
+  "\<lbrakk>write_reg x10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x10_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mtvec[simp]:
-  "liftS (read_reg mtvec_ref) = readS (mtvec \<circ> regstate)"
+lemma liftS_read_reg_x9[liftState_simp]:
+  "\<lbrakk>read_reg x9_ref\<rbrakk>\<^sub>S = readS (x9 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mtvec[simp]:
-  "liftS (write_reg mtvec_ref v) = updateS (regstate_update (mtvec_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x9[liftState_simp]:
+  "\<lbrakk>write_reg x9_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x9_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_medeleg[simp]:
-  "liftS (read_reg medeleg_ref) = readS (medeleg \<circ> regstate)"
+lemma liftS_read_reg_x8[liftState_simp]:
+  "\<lbrakk>read_reg x8_ref\<rbrakk>\<^sub>S = readS (x8 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_medeleg[simp]:
-  "liftS (write_reg medeleg_ref v) = updateS (regstate_update (medeleg_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x8[liftState_simp]:
+  "\<lbrakk>write_reg x8_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x8_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mideleg[simp]:
-  "liftS (read_reg mideleg_ref) = readS (mideleg \<circ> regstate)"
+lemma liftS_read_reg_x7[liftState_simp]:
+  "\<lbrakk>read_reg x7_ref\<rbrakk>\<^sub>S = readS (x7 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mideleg[simp]:
-  "liftS (write_reg mideleg_ref v) = updateS (regstate_update (mideleg_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x7[liftState_simp]:
+  "\<lbrakk>write_reg x7_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x7_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mie[simp]:
-  "liftS (read_reg mie_ref) = readS (mie \<circ> regstate)"
+lemma liftS_read_reg_x6[liftState_simp]:
+  "\<lbrakk>read_reg x6_ref\<rbrakk>\<^sub>S = readS (x6 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mie[simp]:
-  "liftS (write_reg mie_ref v) = updateS (regstate_update (mie_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x6[liftState_simp]:
+  "\<lbrakk>write_reg x6_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x6_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mip[simp]:
-  "liftS (read_reg mip_ref) = readS (mip \<circ> regstate)"
+lemma liftS_read_reg_x5[liftState_simp]:
+  "\<lbrakk>read_reg x5_ref\<rbrakk>\<^sub>S = readS (x5 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mip[simp]:
-  "liftS (write_reg mip_ref v) = updateS (regstate_update (mip_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x5[liftState_simp]:
+  "\<lbrakk>write_reg x5_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x5_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_mstatus[simp]:
-  "liftS (read_reg mstatus_ref) = readS (mstatus \<circ> regstate)"
+lemma liftS_read_reg_x4[liftState_simp]:
+  "\<lbrakk>read_reg x4_ref\<rbrakk>\<^sub>S = readS (x4 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_mstatus[simp]:
-  "liftS (write_reg mstatus_ref v) = updateS (regstate_update (mstatus_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x4[liftState_simp]:
+  "\<lbrakk>write_reg x4_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x4_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_misa[simp]:
-  "liftS (read_reg misa_ref) = readS (misa \<circ> regstate)"
+lemma liftS_read_reg_x3[liftState_simp]:
+  "\<lbrakk>read_reg x3_ref\<rbrakk>\<^sub>S = readS (x3 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_misa[simp]:
-  "liftS (write_reg misa_ref v) = updateS (regstate_update (misa_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x3[liftState_simp]:
+  "\<lbrakk>write_reg x3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x3_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_cur_inst[simp]:
-  "liftS (read_reg cur_inst_ref) = readS (cur_inst \<circ> regstate)"
+lemma liftS_read_reg_x2[liftState_simp]:
+  "\<lbrakk>read_reg x2_ref\<rbrakk>\<^sub>S = readS (x2 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_cur_inst[simp]:
-  "liftS (write_reg cur_inst_ref v) = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x2[liftState_simp]:
+  "\<lbrakk>write_reg x2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x2_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_cur_privilege[simp]:
-  "liftS (read_reg cur_privilege_ref) = readS (cur_privilege \<circ> regstate)"
+lemma liftS_read_reg_x1[liftState_simp]:
+  "\<lbrakk>read_reg x1_ref\<rbrakk>\<^sub>S = readS (x1 \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_cur_privilege[simp]:
-  "liftS (write_reg cur_privilege_ref v) = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))"
+lemma liftS_write_reg_x1[liftState_simp]:
+  "\<lbrakk>write_reg x1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x1_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_Xs[simp]:
-  "liftS (read_reg Xs_ref) = readS (Xs \<circ> regstate)"
+lemma liftS_read_reg_Xs[liftState_simp]:
+  "\<lbrakk>read_reg Xs_ref\<rbrakk>\<^sub>S = readS (Xs \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_Xs[simp]:
-  "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\<lambda>_. v)))"
+lemma liftS_write_reg_Xs[liftState_simp]:
+  "\<lbrakk>write_reg Xs_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Xs_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_nextPC[simp]:
-  "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)"
+lemma liftS_read_reg_nextPC[liftState_simp]:
+  "\<lbrakk>read_reg nextPC_ref\<rbrakk>\<^sub>S = readS (nextPC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_nextPC[simp]:
-  "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_nextPC[liftState_simp]:
+  "\<lbrakk>write_reg nextPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
-lemma liftS_read_reg_PC[simp]:
-  "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)"
+lemma liftS_read_reg_PC[liftState_simp]:
+  "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)"
   by (auto simp: liftState_read_reg_readS register_defs)
 
-lemma liftS_write_reg_PC[simp]:
-  "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))"
+lemma liftS_write_reg_PC[liftState_simp]:
+  "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))"
   by (auto simp: liftState_write_reg_updateS register_defs)
 
 end
diff --git a/snapshots/isabelle/riscv/Riscv_types.thy b/snapshots/isabelle/riscv/Riscv_types.thy
index 71dce180..78328442 100644
--- a/snapshots/isabelle/riscv/Riscv_types.thy
+++ b/snapshots/isabelle/riscv/Riscv_types.thy
@@ -5,23 +5,23 @@ theory "Riscv_types"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
-	 "State" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+	 "Sail2_string" 
 
 begin 
 
 (*Generated by Sail from riscv.*)
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
-(*open import State*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 type_synonym 'n bits =" ( 'n::len)Word.word "
 
 
@@ -109,8 +109,7 @@ datatype TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved
 
 
 
-datatype exception  =
-    Error_not_implemented " (string)" | Error_EBREAK " (unit)" | Error_internal_error " (unit)"
+datatype exception  =   Error_not_implemented " (string)" | Error_internal_error " (unit)"
 
 
 
@@ -174,55 +173,68 @@ datatype word_width = BYTE | HALF | WORD | DOUBLE
 
 
 
-datatype 'a MemoryOpResult =   MemValue " ('a)" | MemException " (ExceptionType)"
+record Misa  = 
+ Misa_Misa_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Misa  =   Mk_Misa " ( 64 Word.word)"
+record SV39_PTE  = 
+ SV39_PTE_SV39_PTE_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype SV39_PTE  =   Mk_SV39_PTE " ( 64 Word.word)"
+record PTE_Bits  = 
+ PTE_Bits_PTE_Bits_chunk_0 ::"  8 Word.word "  
 
 
 
-datatype PTE_Bits  =   Mk_PTE_Bits " ( 8 Word.word)"
+record Mstatus  = 
+ Mstatus_Mstatus_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Mstatus  =   Mk_Mstatus " ( 64 Word.word)"
+record Sstatus  = 
+ Sstatus_Sstatus_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Sstatus  =   Mk_Sstatus " ( 64 Word.word)"
+record Minterrupts  = 
+ Minterrupts_Minterrupts_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Minterrupts  =   Mk_Minterrupts " ( 64 Word.word)"
+record Sinterrupts  = 
+ Sinterrupts_Sinterrupts_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Sinterrupts  =   Mk_Sinterrupts " ( 64 Word.word)"
+record Medeleg  = 
+ Medeleg_Medeleg_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Medeleg  =   Mk_Medeleg " ( 64 Word.word)"
+record Sedeleg  = 
+ Sedeleg_Sedeleg_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Sedeleg  =   Mk_Sedeleg " ( 64 Word.word)"
+record Mtvec  = 
+ Mtvec_Mtvec_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Mtvec  =   Mk_Mtvec " ( 64 Word.word)"
+record Satp64  = 
+ Satp64_Satp64_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Satp64  =   Mk_Satp64 " ( 64 Word.word)"
+record Mcause  = 
+ Mcause_Mcause_chunk_0 ::"  64 Word.word "  
 
 
 
-datatype Mcause  =   Mk_Mcause " ( 64 Word.word)"
+record Counteren  = 
+ Counteren_Counteren_chunk_0 ::"  32 Word.word "  
 
 
 
@@ -237,6 +249,15 @@ datatype ctl_result  =   CTL_TRAP " (sync_exception)" | CTL_SRET " (unit)" | CTL
 
 
 
+datatype 'a MemoryOpResult =   MemValue " ('a)" | MemException " (ExceptionType)"
+
+
+
+record htif_cmd  = 
+ htif_cmd_htif_cmd_chunk_0 ::"  64 Word.word "  
+
+
+
 type_synonym pteAttribs  =" 8 bits "
 
 datatype PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update
@@ -249,11 +270,13 @@ type_synonym paddr39  =" 56 bits "
 
 type_synonym pte39  =" xlenbits "
 
-datatype SV39_Vaddr  =   Mk_SV39_Vaddr " ( 39 Word.word)"
+record SV39_Vaddr  = 
+ SV39_Vaddr_SV39_Vaddr_chunk_0 ::"  39 Word.word "  
 
 
 
-datatype SV39_Paddr  =   Mk_SV39_Paddr " ( 56 Word.word)"
+record SV39_Paddr  = 
+ SV39_Paddr_SV39_Paddr_chunk_0 ::"  56 Word.word "  
 
 
 
@@ -326,7 +349,6 @@ datatype (plugins only: size) ast  =
   | AMO " ((amoop * bool * bool * regbits * regbits * word_width * regbits))"
   | CSR " (( 12 bits * regbits * regbits * bool * csrop))"
   | NOP " (unit)"
-  | ILLEGAL " (unit)"
   | C_ADDI4SPN " ((cregbits * 8 bits))"
   | C_LW " (( 5 bits * cregbits * cregbits))"
   | C_LD " (( 5 bits * cregbits * cregbits))"
@@ -359,6 +381,10 @@ datatype (plugins only: size) ast  =
   | C_JALR " (regbits)"
   | C_MV " ((regbits * regbits))"
   | C_ADD " ((regbits * regbits))"
+  | STOP_FETCHING " (unit)"
+  | THREAD_START " (unit)"
+  | ILLEGAL " (word0)"
+  | C_ILLEGAL " (unit)"
 
 
 
@@ -366,10 +392,44 @@ datatype FetchResult  =   F_Base " (word0)" | F_RVC " (half)" | F_Error " ((Exce
 
 
 
+datatype regfp  =
+    RFull " (string)"
+  | RSlice " ((string * ii * ii))"
+  | RSliceBit " ((string * ii))"
+  | RField " ((string * string))"
+
+
+
+type_synonym regfps  =" regfp list "
+
+datatype niafp  =
+    NIAFP_successor " (unit)"
+  | NIAFP_concrete_address " ( 64 bits)"
+  | NIAFP_indirect_address " (unit)"
+
+
+
+type_synonym niafps  =" niafp list "
+
+datatype diafp  =   DIAFP_none " (unit)" | DIAFP_concrete " ( 64 bits)" | DIAFP_reg " (regfp)"
+
+
+
+
+
+
+
+
+
+
+
+
+
 datatype register_value  =
     Regval_vector " ((ii * bool * register_value list))"
   | Regval_list " ( register_value list)"
   | Regval_option " ( register_value option)"
+  | Regval_Counteren " (Counteren)"
   | Regval_Mcause " (Mcause)"
   | Regval_Medeleg " (Medeleg)"
   | Regval_Minterrupts " (Minterrupts)"
@@ -380,6 +440,7 @@ datatype register_value  =
   | Regval_Sedeleg " (Sedeleg)"
   | Regval_Sinterrupts " (Sinterrupts)"
   | Regval_TLB39_Entry " (TLB39_Entry)"
+  | Regval_bool " (bool)"
   | Regval_vector_64_dec_bit " ( 64 Word.word)"
 
 
@@ -388,6 +449,14 @@ record regstate  =
   
  tlb39 ::"  TLB39_Entry option " 
 
+     htif_exit_code ::"  64 Word.word " 
+
+     htif_done ::" bool " 
+
+     htif_tohost ::"  64 Word.word " 
+
+     mtimecmp ::"  64 Word.word " 
+
      tselect ::"  64 Word.word " 
 
      stval ::"  64 Word.word " 
@@ -418,12 +487,18 @@ record regstate  =
 
      mvendorid ::"  64 Word.word " 
 
+     minstret_written ::" bool " 
+
      minstret ::"  64 Word.word " 
 
      mtime ::"  64 Word.word " 
 
      mcycle ::"  64 Word.word " 
 
+     scounteren ::" Counteren " 
+
+     mcounteren ::" Counteren " 
+
      mscratch ::"  64 Word.word " 
 
      mtval ::"  64 Word.word " 
@@ -450,6 +525,68 @@ record regstate  =
 
      cur_privilege ::" Privilege " 
 
+     x31 ::"  64 Word.word " 
+
+     x30 ::"  64 Word.word " 
+
+     x29 ::"  64 Word.word " 
+
+     x28 ::"  64 Word.word " 
+
+     x27 ::"  64 Word.word " 
+
+     x26 ::"  64 Word.word " 
+
+     x25 ::"  64 Word.word " 
+
+     x24 ::"  64 Word.word " 
+
+     x23 ::"  64 Word.word " 
+
+     x22 ::"  64 Word.word " 
+
+     x21 ::"  64 Word.word " 
+
+     x20 ::"  64 Word.word " 
+
+     x19 ::"  64 Word.word " 
+
+     x18 ::"  64 Word.word " 
+
+     x17 ::"  64 Word.word " 
+
+     x16 ::"  64 Word.word " 
+
+     x15 ::"  64 Word.word " 
+
+     x14 ::"  64 Word.word " 
+
+     x13 ::"  64 Word.word " 
+
+     x12 ::"  64 Word.word " 
+
+     x11 ::"  64 Word.word " 
+
+     x10 ::"  64 Word.word " 
+
+     x9 ::"  64 Word.word " 
+
+     x8 ::"  64 Word.word " 
+
+     x7 ::"  64 Word.word " 
+
+     x6 ::"  64 Word.word " 
+
+     x5 ::"  64 Word.word " 
+
+     x4 ::"  64 Word.word " 
+
+     x3 ::"  64 Word.word " 
+
+     x2 ::"  64 Word.word " 
+
+     x1 ::"  64 Word.word " 
+
      Xs ::" ( 64 Word.word) list " 
 
      nextPC ::"  64 Word.word " 
@@ -460,11 +597,24 @@ record regstate  =
 
 
 
+(*val Counteren_of_regval : register_value -> maybe Counteren*)
+
+fun Counteren_of_regval  :: " register_value \<Rightarrow>(Counteren)option "  where 
+     " Counteren_of_regval (Regval_Counteren (v)) = ( Some v )"
+|" Counteren_of_regval g__12 = ( None )"
+
+
+(*val regval_of_Counteren : Counteren -> register_value*)
+
+definition regval_of_Counteren  :: " Counteren \<Rightarrow> register_value "  where 
+     " regval_of_Counteren v = ( Regval_Counteren v )"
+
+
 (*val Mcause_of_regval : register_value -> maybe Mcause*)
 
 fun Mcause_of_regval  :: " register_value \<Rightarrow>(Mcause)option "  where 
      " Mcause_of_regval (Regval_Mcause (v)) = ( Some v )"
-|" Mcause_of_regval g__92 = ( None )"
+|" Mcause_of_regval g__11 = ( None )"
 
 
 (*val regval_of_Mcause : Mcause -> register_value*)
@@ -477,7 +627,7 @@ definition regval_of_Mcause  :: " Mcause \<Rightarrow> register_value "  where
 
 fun Medeleg_of_regval  :: " register_value \<Rightarrow>(Medeleg)option "  where 
      " Medeleg_of_regval (Regval_Medeleg (v)) = ( Some v )"
-|" Medeleg_of_regval g__91 = ( None )"
+|" Medeleg_of_regval g__10 = ( None )"
 
 
 (*val regval_of_Medeleg : Medeleg -> register_value*)
@@ -490,7 +640,7 @@ definition regval_of_Medeleg  :: " Medeleg \<Rightarrow> register_value "  where
 
 fun Minterrupts_of_regval  :: " register_value \<Rightarrow>(Minterrupts)option "  where 
      " Minterrupts_of_regval (Regval_Minterrupts (v)) = ( Some v )"
-|" Minterrupts_of_regval g__90 = ( None )"
+|" Minterrupts_of_regval g__9 = ( None )"
 
 
 (*val regval_of_Minterrupts : Minterrupts -> register_value*)
@@ -503,7 +653,7 @@ definition regval_of_Minterrupts  :: " Minterrupts \<Rightarrow> register_value
 
 fun Misa_of_regval  :: " register_value \<Rightarrow>(Misa)option "  where 
      " Misa_of_regval (Regval_Misa (v)) = ( Some v )"
-|" Misa_of_regval g__89 = ( None )"
+|" Misa_of_regval g__8 = ( None )"
 
 
 (*val regval_of_Misa : Misa -> register_value*)
@@ -516,7 +666,7 @@ definition regval_of_Misa  :: " Misa \<Rightarrow> register_value "  where
 
 fun Mstatus_of_regval  :: " register_value \<Rightarrow>(Mstatus)option "  where 
      " Mstatus_of_regval (Regval_Mstatus (v)) = ( Some v )"
-|" Mstatus_of_regval g__88 = ( None )"
+|" Mstatus_of_regval g__7 = ( None )"
 
 
 (*val regval_of_Mstatus : Mstatus -> register_value*)
@@ -529,7 +679,7 @@ definition regval_of_Mstatus  :: " Mstatus \<Rightarrow> register_value "  where
 
 fun Mtvec_of_regval  :: " register_value \<Rightarrow>(Mtvec)option "  where 
      " Mtvec_of_regval (Regval_Mtvec (v)) = ( Some v )"
-|" Mtvec_of_regval g__87 = ( None )"
+|" Mtvec_of_regval g__6 = ( None )"
 
 
 (*val regval_of_Mtvec : Mtvec -> register_value*)
@@ -542,7 +692,7 @@ definition regval_of_Mtvec  :: " Mtvec \<Rightarrow> register_value "  where
 
 fun Privilege_of_regval  :: " register_value \<Rightarrow>(Privilege)option "  where 
      " Privilege_of_regval (Regval_Privilege (v)) = ( Some v )"
-|" Privilege_of_regval g__86 = ( None )"
+|" Privilege_of_regval g__5 = ( None )"
 
 
 (*val regval_of_Privilege : Privilege -> register_value*)
@@ -555,7 +705,7 @@ definition regval_of_Privilege  :: " Privilege \<Rightarrow> register_value "  w
 
 fun Sedeleg_of_regval  :: " register_value \<Rightarrow>(Sedeleg)option "  where 
      " Sedeleg_of_regval (Regval_Sedeleg (v)) = ( Some v )"
-|" Sedeleg_of_regval g__85 = ( None )"
+|" Sedeleg_of_regval g__4 = ( None )"
 
 
 (*val regval_of_Sedeleg : Sedeleg -> register_value*)
@@ -568,7 +718,7 @@ definition regval_of_Sedeleg  :: " Sedeleg \<Rightarrow> register_value "  where
 
 fun Sinterrupts_of_regval  :: " register_value \<Rightarrow>(Sinterrupts)option "  where 
      " Sinterrupts_of_regval (Regval_Sinterrupts (v)) = ( Some v )"
-|" Sinterrupts_of_regval g__84 = ( None )"
+|" Sinterrupts_of_regval g__3 = ( None )"
 
 
 (*val regval_of_Sinterrupts : Sinterrupts -> register_value*)
@@ -581,7 +731,7 @@ definition regval_of_Sinterrupts  :: " Sinterrupts \<Rightarrow> register_value
 
 fun TLB39_Entry_of_regval  :: " register_value \<Rightarrow>(TLB39_Entry)option "  where 
      " TLB39_Entry_of_regval (Regval_TLB39_Entry (v)) = ( Some v )"
-|" TLB39_Entry_of_regval g__83 = ( None )"
+|" TLB39_Entry_of_regval g__2 = ( None )"
 
 
 (*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*)
@@ -590,11 +740,24 @@ definition regval_of_TLB39_Entry  :: " TLB39_Entry \<Rightarrow> register_value
      " regval_of_TLB39_Entry v = ( Regval_TLB39_Entry v )"
 
 
+(*val bool_of_regval : register_value -> maybe bool*)
+
+fun bool_of_regval  :: " register_value \<Rightarrow>(bool)option "  where 
+     " bool_of_regval (Regval_bool (v)) = ( Some v )"
+|" bool_of_regval g__1 = ( None )"
+
+
+(*val regval_of_bool : bool -> register_value*)
+
+definition regval_of_bool  :: " bool \<Rightarrow> register_value "  where 
+     " regval_of_bool v = ( Regval_bool v )"
+
+
 (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
 
 fun vector_64_dec_bit_of_regval  :: " register_value \<Rightarrow>((64)Word.word)option "  where 
      " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )"
-|" vector_64_dec_bit_of_regval g__82 = ( None )"
+|" vector_64_dec_bit_of_regval g__0 = ( None )"
 
 
 (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
@@ -657,6 +820,42 @@ definition tlb39_ref  :: "((regstate),(register_value),((TLB39_Entry)option))reg
   regval_of = (\<lambda> v .  regval_of_option (\<lambda> v .  regval_of_TLB39_Entry v) v) |) )"
 
 
+definition htif_exit_code_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " htif_exit_code_ref = ( (|
+  name = (''htif_exit_code''),
+  read_from = (\<lambda> s . (htif_exit_code   s)),
+  write_to = (\<lambda> v s .  (( s (| htif_exit_code := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition htif_done_ref  :: "((regstate),(register_value),(bool))register_ref "  where 
+     " htif_done_ref = ( (|
+  name = (''htif_done''),
+  read_from = (\<lambda> s . (htif_done   s)),
+  write_to = (\<lambda> v s .  (( s (| htif_done := v |)))),
+  of_regval = (\<lambda> v .  bool_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_bool v) |) )"
+
+
+definition htif_tohost_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " htif_tohost_ref = ( (|
+  name = (''htif_tohost''),
+  read_from = (\<lambda> s . (htif_tohost   s)),
+  write_to = (\<lambda> v s .  (( s (| htif_tohost := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mtimecmp_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " mtimecmp_ref = ( (|
+  name = (''mtimecmp''),
+  read_from = (\<lambda> s . (mtimecmp   s)),
+  write_to = (\<lambda> v s .  (( s (| mtimecmp := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
 definition tselect_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
      " tselect_ref = ( (|
   name = (''tselect''),
@@ -792,6 +991,15 @@ definition mvendorid_ref  :: "((regstate),(register_value),((64)Word.word))regis
   regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
 
 
+definition minstret_written_ref  :: "((regstate),(register_value),(bool))register_ref "  where 
+     " minstret_written_ref = ( (|
+  name = (''minstret_written''),
+  read_from = (\<lambda> s . (minstret_written   s)),
+  write_to = (\<lambda> v s .  (( s (| minstret_written := v |)))),
+  of_regval = (\<lambda> v .  bool_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_bool v) |) )"
+
+
 definition minstret_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
      " minstret_ref = ( (|
   name = (''minstret''),
@@ -819,6 +1027,24 @@ definition mcycle_ref  :: "((regstate),(register_value),((64)Word.word))register
   regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
 
 
+definition scounteren_ref  :: "((regstate),(register_value),(Counteren))register_ref "  where 
+     " scounteren_ref = ( (|
+  name = (''scounteren''),
+  read_from = (\<lambda> s . (scounteren   s)),
+  write_to = (\<lambda> v s .  (( s (| scounteren := v |)))),
+  of_regval = (\<lambda> v .  Counteren_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_Counteren v) |) )"
+
+
+definition mcounteren_ref  :: "((regstate),(register_value),(Counteren))register_ref "  where 
+     " mcounteren_ref = ( (|
+  name = (''mcounteren''),
+  read_from = (\<lambda> s . (mcounteren   s)),
+  write_to = (\<lambda> v s .  (( s (| mcounteren := v |)))),
+  of_regval = (\<lambda> v .  Counteren_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_Counteren v) |) )"
+
+
 definition mscratch_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
      " mscratch_ref = ( (|
   name = (''mscratch''),
@@ -936,6 +1162,285 @@ definition cur_privilege_ref  :: "((regstate),(register_value),(Privilege))regis
   regval_of = (\<lambda> v .  regval_of_Privilege v) |) )"
 
 
+definition x31_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x31_ref = ( (|
+  name = (''x31''),
+  read_from = (\<lambda> s . (x31   s)),
+  write_to = (\<lambda> v s .  (( s (| x31 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x30_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x30_ref = ( (|
+  name = (''x30''),
+  read_from = (\<lambda> s . (x30   s)),
+  write_to = (\<lambda> v s .  (( s (| x30 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x29_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x29_ref = ( (|
+  name = (''x29''),
+  read_from = (\<lambda> s . (x29   s)),
+  write_to = (\<lambda> v s .  (( s (| x29 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x28_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x28_ref = ( (|
+  name = (''x28''),
+  read_from = (\<lambda> s . (x28   s)),
+  write_to = (\<lambda> v s .  (( s (| x28 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x27_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x27_ref = ( (|
+  name = (''x27''),
+  read_from = (\<lambda> s . (x27   s)),
+  write_to = (\<lambda> v s .  (( s (| x27 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x26_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x26_ref = ( (|
+  name = (''x26''),
+  read_from = (\<lambda> s . (x26   s)),
+  write_to = (\<lambda> v s .  (( s (| x26 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x25_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x25_ref = ( (|
+  name = (''x25''),
+  read_from = (\<lambda> s . (x25   s)),
+  write_to = (\<lambda> v s .  (( s (| x25 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x24_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x24_ref = ( (|
+  name = (''x24''),
+  read_from = (\<lambda> s . (x24   s)),
+  write_to = (\<lambda> v s .  (( s (| x24 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x23_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x23_ref = ( (|
+  name = (''x23''),
+  read_from = (\<lambda> s . (x23   s)),
+  write_to = (\<lambda> v s .  (( s (| x23 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x22_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x22_ref = ( (|
+  name = (''x22''),
+  read_from = (\<lambda> s . (x22   s)),
+  write_to = (\<lambda> v s .  (( s (| x22 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x21_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x21_ref = ( (|
+  name = (''x21''),
+  read_from = (\<lambda> s . (x21   s)),
+  write_to = (\<lambda> v s .  (( s (| x21 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x20_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x20_ref = ( (|
+  name = (''x20''),
+  read_from = (\<lambda> s . (x20   s)),
+  write_to = (\<lambda> v s .  (( s (| x20 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x19_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x19_ref = ( (|
+  name = (''x19''),
+  read_from = (\<lambda> s . (x19   s)),
+  write_to = (\<lambda> v s .  (( s (| x19 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x18_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x18_ref = ( (|
+  name = (''x18''),
+  read_from = (\<lambda> s . (x18   s)),
+  write_to = (\<lambda> v s .  (( s (| x18 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x17_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x17_ref = ( (|
+  name = (''x17''),
+  read_from = (\<lambda> s . (x17   s)),
+  write_to = (\<lambda> v s .  (( s (| x17 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x16_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x16_ref = ( (|
+  name = (''x16''),
+  read_from = (\<lambda> s . (x16   s)),
+  write_to = (\<lambda> v s .  (( s (| x16 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x15_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x15_ref = ( (|
+  name = (''x15''),
+  read_from = (\<lambda> s . (x15   s)),
+  write_to = (\<lambda> v s .  (( s (| x15 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x14_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x14_ref = ( (|
+  name = (''x14''),
+  read_from = (\<lambda> s . (x14   s)),
+  write_to = (\<lambda> v s .  (( s (| x14 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x13_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x13_ref = ( (|
+  name = (''x13''),
+  read_from = (\<lambda> s . (x13   s)),
+  write_to = (\<lambda> v s .  (( s (| x13 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x12_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x12_ref = ( (|
+  name = (''x12''),
+  read_from = (\<lambda> s . (x12   s)),
+  write_to = (\<lambda> v s .  (( s (| x12 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x11_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x11_ref = ( (|
+  name = (''x11''),
+  read_from = (\<lambda> s . (x11   s)),
+  write_to = (\<lambda> v s .  (( s (| x11 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x10_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x10_ref = ( (|
+  name = (''x10''),
+  read_from = (\<lambda> s . (x10   s)),
+  write_to = (\<lambda> v s .  (( s (| x10 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x9_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x9_ref = ( (|
+  name = (''x9''),
+  read_from = (\<lambda> s . (x9   s)),
+  write_to = (\<lambda> v s .  (( s (| x9 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x8_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x8_ref = ( (|
+  name = (''x8''),
+  read_from = (\<lambda> s . (x8   s)),
+  write_to = (\<lambda> v s .  (( s (| x8 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x7_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x7_ref = ( (|
+  name = (''x7''),
+  read_from = (\<lambda> s . (x7   s)),
+  write_to = (\<lambda> v s .  (( s (| x7 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x6_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x6_ref = ( (|
+  name = (''x6''),
+  read_from = (\<lambda> s . (x6   s)),
+  write_to = (\<lambda> v s .  (( s (| x6 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x5_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x5_ref = ( (|
+  name = (''x5''),
+  read_from = (\<lambda> s . (x5   s)),
+  write_to = (\<lambda> v s .  (( s (| x5 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x4_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x4_ref = ( (|
+  name = (''x4''),
+  read_from = (\<lambda> s . (x4   s)),
+  write_to = (\<lambda> v s .  (( s (| x4 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x3_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x3_ref = ( (|
+  name = (''x3''),
+  read_from = (\<lambda> s . (x3   s)),
+  write_to = (\<lambda> v s .  (( s (| x3 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x2_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x2_ref = ( (|
+  name = (''x2''),
+  read_from = (\<lambda> s . (x2   s)),
+  write_to = (\<lambda> v s .  (( s (| x2 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x1_ref  :: "((regstate),(register_value),((64)Word.word))register_ref "  where 
+     " x1_ref = ( (|
+  name = (''x1''),
+  read_from = (\<lambda> s . (x1   s)),
+  write_to = (\<lambda> v s .  (( s (| x1 := v |)))),
+  of_regval = (\<lambda> v .  vector_64_dec_bit_of_regval v),
+  regval_of = (\<lambda> v .  regval_of_vector_64_dec_bit v) |) )"
+
+
 definition Xs_ref  :: "((regstate),(register_value),(((64)Word.word)list))register_ref "  where 
      " Xs_ref = ( (|
   name = (''Xs''),
@@ -967,6 +1472,10 @@ definition PC_ref  :: "((regstate),(register_value),((64)Word.word))register_ref
 definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option "  where 
      " get_regval reg_name s = (
   if reg_name = (''tlb39'') then Some ((regval_of   tlb39_ref) ((read_from   tlb39_ref) s)) else
+  if reg_name = (''htif_exit_code'') then Some ((regval_of   htif_exit_code_ref) ((read_from   htif_exit_code_ref) s)) else
+  if reg_name = (''htif_done'') then Some ((regval_of   htif_done_ref) ((read_from   htif_done_ref) s)) else
+  if reg_name = (''htif_tohost'') then Some ((regval_of   htif_tohost_ref) ((read_from   htif_tohost_ref) s)) else
+  if reg_name = (''mtimecmp'') then Some ((regval_of   mtimecmp_ref) ((read_from   mtimecmp_ref) s)) else
   if reg_name = (''tselect'') then Some ((regval_of   tselect_ref) ((read_from   tselect_ref) s)) else
   if reg_name = (''stval'') then Some ((regval_of   stval_ref) ((read_from   stval_ref) s)) else
   if reg_name = (''scause'') then Some ((regval_of   scause_ref) ((read_from   scause_ref) s)) else
@@ -982,9 +1491,12 @@ definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register
   if reg_name = (''marchid'') then Some ((regval_of   marchid_ref) ((read_from   marchid_ref) s)) else
   if reg_name = (''mimpid'') then Some ((regval_of   mimpid_ref) ((read_from   mimpid_ref) s)) else
   if reg_name = (''mvendorid'') then Some ((regval_of   mvendorid_ref) ((read_from   mvendorid_ref) s)) else
+  if reg_name = (''minstret_written'') then Some ((regval_of   minstret_written_ref) ((read_from   minstret_written_ref) s)) else
   if reg_name = (''minstret'') then Some ((regval_of   minstret_ref) ((read_from   minstret_ref) s)) else
   if reg_name = (''mtime'') then Some ((regval_of   mtime_ref) ((read_from   mtime_ref) s)) else
   if reg_name = (''mcycle'') then Some ((regval_of   mcycle_ref) ((read_from   mcycle_ref) s)) else
+  if reg_name = (''scounteren'') then Some ((regval_of   scounteren_ref) ((read_from   scounteren_ref) s)) else
+  if reg_name = (''mcounteren'') then Some ((regval_of   mcounteren_ref) ((read_from   mcounteren_ref) s)) else
   if reg_name = (''mscratch'') then Some ((regval_of   mscratch_ref) ((read_from   mscratch_ref) s)) else
   if reg_name = (''mtval'') then Some ((regval_of   mtval_ref) ((read_from   mtval_ref) s)) else
   if reg_name = (''mepc'') then Some ((regval_of   mepc_ref) ((read_from   mepc_ref) s)) else
@@ -998,6 +1510,37 @@ definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register
   if reg_name = (''misa'') then Some ((regval_of   misa_ref) ((read_from   misa_ref) s)) else
   if reg_name = (''cur_inst'') then Some ((regval_of   cur_inst_ref) ((read_from   cur_inst_ref) s)) else
   if reg_name = (''cur_privilege'') then Some ((regval_of   cur_privilege_ref) ((read_from   cur_privilege_ref) s)) else
+  if reg_name = (''x31'') then Some ((regval_of   x31_ref) ((read_from   x31_ref) s)) else
+  if reg_name = (''x30'') then Some ((regval_of   x30_ref) ((read_from   x30_ref) s)) else
+  if reg_name = (''x29'') then Some ((regval_of   x29_ref) ((read_from   x29_ref) s)) else
+  if reg_name = (''x28'') then Some ((regval_of   x28_ref) ((read_from   x28_ref) s)) else
+  if reg_name = (''x27'') then Some ((regval_of   x27_ref) ((read_from   x27_ref) s)) else
+  if reg_name = (''x26'') then Some ((regval_of   x26_ref) ((read_from   x26_ref) s)) else
+  if reg_name = (''x25'') then Some ((regval_of   x25_ref) ((read_from   x25_ref) s)) else
+  if reg_name = (''x24'') then Some ((regval_of   x24_ref) ((read_from   x24_ref) s)) else
+  if reg_name = (''x23'') then Some ((regval_of   x23_ref) ((read_from   x23_ref) s)) else
+  if reg_name = (''x22'') then Some ((regval_of   x22_ref) ((read_from   x22_ref) s)) else
+  if reg_name = (''x21'') then Some ((regval_of   x21_ref) ((read_from   x21_ref) s)) else
+  if reg_name = (''x20'') then Some ((regval_of   x20_ref) ((read_from   x20_ref) s)) else
+  if reg_name = (''x19'') then Some ((regval_of   x19_ref) ((read_from   x19_ref) s)) else
+  if reg_name = (''x18'') then Some ((regval_of   x18_ref) ((read_from   x18_ref) s)) else
+  if reg_name = (''x17'') then Some ((regval_of   x17_ref) ((read_from   x17_ref) s)) else
+  if reg_name = (''x16'') then Some ((regval_of   x16_ref) ((read_from   x16_ref) s)) else
+  if reg_name = (''x15'') then Some ((regval_of   x15_ref) ((read_from   x15_ref) s)) else
+  if reg_name = (''x14'') then Some ((regval_of   x14_ref) ((read_from   x14_ref) s)) else
+  if reg_name = (''x13'') then Some ((regval_of   x13_ref) ((read_from   x13_ref) s)) else
+  if reg_name = (''x12'') then Some ((regval_of   x12_ref) ((read_from   x12_ref) s)) else
+  if reg_name = (''x11'') then Some ((regval_of   x11_ref) ((read_from   x11_ref) s)) else
+  if reg_name = (''x10'') then Some ((regval_of   x10_ref) ((read_from   x10_ref) s)) else
+  if reg_name = (''x9'') then Some ((regval_of   x9_ref) ((read_from   x9_ref) s)) else
+  if reg_name = (''x8'') then Some ((regval_of   x8_ref) ((read_from   x8_ref) s)) else
+  if reg_name = (''x7'') then Some ((regval_of   x7_ref) ((read_from   x7_ref) s)) else
+  if reg_name = (''x6'') then Some ((regval_of   x6_ref) ((read_from   x6_ref) s)) else
+  if reg_name = (''x5'') then Some ((regval_of   x5_ref) ((read_from   x5_ref) s)) else
+  if reg_name = (''x4'') then Some ((regval_of   x4_ref) ((read_from   x4_ref) s)) else
+  if reg_name = (''x3'') then Some ((regval_of   x3_ref) ((read_from   x3_ref) s)) else
+  if reg_name = (''x2'') then Some ((regval_of   x2_ref) ((read_from   x2_ref) s)) else
+  if reg_name = (''x1'') then Some ((regval_of   x1_ref) ((read_from   x1_ref) s)) else
   if reg_name = (''Xs'') then Some ((regval_of   Xs_ref) ((read_from   Xs_ref) s)) else
   if reg_name = (''nextPC'') then Some ((regval_of   nextPC_ref) ((read_from   nextPC_ref) s)) else
   if reg_name = (''PC'') then Some ((regval_of   PC_ref) ((read_from   PC_ref) s)) else
@@ -1008,6 +1551,10 @@ definition get_regval  :: " string \<Rightarrow> regstate \<Rightarrow>(register
 definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option "  where 
      " set_regval reg_name v s = (
   if reg_name = (''tlb39'') then map_option (\<lambda> v . (write_to   tlb39_ref) v s) ((of_regval   tlb39_ref) v) else
+  if reg_name = (''htif_exit_code'') then map_option (\<lambda> v . (write_to   htif_exit_code_ref) v s) ((of_regval   htif_exit_code_ref) v) else
+  if reg_name = (''htif_done'') then map_option (\<lambda> v . (write_to   htif_done_ref) v s) ((of_regval   htif_done_ref) v) else
+  if reg_name = (''htif_tohost'') then map_option (\<lambda> v . (write_to   htif_tohost_ref) v s) ((of_regval   htif_tohost_ref) v) else
+  if reg_name = (''mtimecmp'') then map_option (\<lambda> v . (write_to   mtimecmp_ref) v s) ((of_regval   mtimecmp_ref) v) else
   if reg_name = (''tselect'') then map_option (\<lambda> v . (write_to   tselect_ref) v s) ((of_regval   tselect_ref) v) else
   if reg_name = (''stval'') then map_option (\<lambda> v . (write_to   stval_ref) v s) ((of_regval   stval_ref) v) else
   if reg_name = (''scause'') then map_option (\<lambda> v . (write_to   scause_ref) v s) ((of_regval   scause_ref) v) else
@@ -1023,9 +1570,12 @@ definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> re
   if reg_name = (''marchid'') then map_option (\<lambda> v . (write_to   marchid_ref) v s) ((of_regval   marchid_ref) v) else
   if reg_name = (''mimpid'') then map_option (\<lambda> v . (write_to   mimpid_ref) v s) ((of_regval   mimpid_ref) v) else
   if reg_name = (''mvendorid'') then map_option (\<lambda> v . (write_to   mvendorid_ref) v s) ((of_regval   mvendorid_ref) v) else
+  if reg_name = (''minstret_written'') then map_option (\<lambda> v . (write_to   minstret_written_ref) v s) ((of_regval   minstret_written_ref) v) else
   if reg_name = (''minstret'') then map_option (\<lambda> v . (write_to   minstret_ref) v s) ((of_regval   minstret_ref) v) else
   if reg_name = (''mtime'') then map_option (\<lambda> v . (write_to   mtime_ref) v s) ((of_regval   mtime_ref) v) else
   if reg_name = (''mcycle'') then map_option (\<lambda> v . (write_to   mcycle_ref) v s) ((of_regval   mcycle_ref) v) else
+  if reg_name = (''scounteren'') then map_option (\<lambda> v . (write_to   scounteren_ref) v s) ((of_regval   scounteren_ref) v) else
+  if reg_name = (''mcounteren'') then map_option (\<lambda> v . (write_to   mcounteren_ref) v s) ((of_regval   mcounteren_ref) v) else
   if reg_name = (''mscratch'') then map_option (\<lambda> v . (write_to   mscratch_ref) v s) ((of_regval   mscratch_ref) v) else
   if reg_name = (''mtval'') then map_option (\<lambda> v . (write_to   mtval_ref) v s) ((of_regval   mtval_ref) v) else
   if reg_name = (''mepc'') then map_option (\<lambda> v . (write_to   mepc_ref) v s) ((of_regval   mepc_ref) v) else
@@ -1039,6 +1589,37 @@ definition set_regval  :: " string \<Rightarrow> register_value \<Rightarrow> re
   if reg_name = (''misa'') then map_option (\<lambda> v . (write_to   misa_ref) v s) ((of_regval   misa_ref) v) else
   if reg_name = (''cur_inst'') then map_option (\<lambda> v . (write_to   cur_inst_ref) v s) ((of_regval   cur_inst_ref) v) else
   if reg_name = (''cur_privilege'') then map_option (\<lambda> v . (write_to   cur_privilege_ref) v s) ((of_regval   cur_privilege_ref) v) else
+  if reg_name = (''x31'') then map_option (\<lambda> v . (write_to   x31_ref) v s) ((of_regval   x31_ref) v) else
+  if reg_name = (''x30'') then map_option (\<lambda> v . (write_to   x30_ref) v s) ((of_regval   x30_ref) v) else
+  if reg_name = (''x29'') then map_option (\<lambda> v . (write_to   x29_ref) v s) ((of_regval   x29_ref) v) else
+  if reg_name = (''x28'') then map_option (\<lambda> v . (write_to   x28_ref) v s) ((of_regval   x28_ref) v) else
+  if reg_name = (''x27'') then map_option (\<lambda> v . (write_to   x27_ref) v s) ((of_regval   x27_ref) v) else
+  if reg_name = (''x26'') then map_option (\<lambda> v . (write_to   x26_ref) v s) ((of_regval   x26_ref) v) else
+  if reg_name = (''x25'') then map_option (\<lambda> v . (write_to   x25_ref) v s) ((of_regval   x25_ref) v) else
+  if reg_name = (''x24'') then map_option (\<lambda> v . (write_to   x24_ref) v s) ((of_regval   x24_ref) v) else
+  if reg_name = (''x23'') then map_option (\<lambda> v . (write_to   x23_ref) v s) ((of_regval   x23_ref) v) else
+  if reg_name = (''x22'') then map_option (\<lambda> v . (write_to   x22_ref) v s) ((of_regval   x22_ref) v) else
+  if reg_name = (''x21'') then map_option (\<lambda> v . (write_to   x21_ref) v s) ((of_regval   x21_ref) v) else
+  if reg_name = (''x20'') then map_option (\<lambda> v . (write_to   x20_ref) v s) ((of_regval   x20_ref) v) else
+  if reg_name = (''x19'') then map_option (\<lambda> v . (write_to   x19_ref) v s) ((of_regval   x19_ref) v) else
+  if reg_name = (''x18'') then map_option (\<lambda> v . (write_to   x18_ref) v s) ((of_regval   x18_ref) v) else
+  if reg_name = (''x17'') then map_option (\<lambda> v . (write_to   x17_ref) v s) ((of_regval   x17_ref) v) else
+  if reg_name = (''x16'') then map_option (\<lambda> v . (write_to   x16_ref) v s) ((of_regval   x16_ref) v) else
+  if reg_name = (''x15'') then map_option (\<lambda> v . (write_to   x15_ref) v s) ((of_regval   x15_ref) v) else
+  if reg_name = (''x14'') then map_option (\<lambda> v . (write_to   x14_ref) v s) ((of_regval   x14_ref) v) else
+  if reg_name = (''x13'') then map_option (\<lambda> v . (write_to   x13_ref) v s) ((of_regval   x13_ref) v) else
+  if reg_name = (''x12'') then map_option (\<lambda> v . (write_to   x12_ref) v s) ((of_regval   x12_ref) v) else
+  if reg_name = (''x11'') then map_option (\<lambda> v . (write_to   x11_ref) v s) ((of_regval   x11_ref) v) else
+  if reg_name = (''x10'') then map_option (\<lambda> v . (write_to   x10_ref) v s) ((of_regval   x10_ref) v) else
+  if reg_name = (''x9'') then map_option (\<lambda> v . (write_to   x9_ref) v s) ((of_regval   x9_ref) v) else
+  if reg_name = (''x8'') then map_option (\<lambda> v . (write_to   x8_ref) v s) ((of_regval   x8_ref) v) else
+  if reg_name = (''x7'') then map_option (\<lambda> v . (write_to   x7_ref) v s) ((of_regval   x7_ref) v) else
+  if reg_name = (''x6'') then map_option (\<lambda> v . (write_to   x6_ref) v s) ((of_regval   x6_ref) v) else
+  if reg_name = (''x5'') then map_option (\<lambda> v . (write_to   x5_ref) v s) ((of_regval   x5_ref) v) else
+  if reg_name = (''x4'') then map_option (\<lambda> v . (write_to   x4_ref) v s) ((of_regval   x4_ref) v) else
+  if reg_name = (''x3'') then map_option (\<lambda> v . (write_to   x3_ref) v s) ((of_regval   x3_ref) v) else
+  if reg_name = (''x2'') then map_option (\<lambda> v . (write_to   x2_ref) v s) ((of_regval   x2_ref) v) else
+  if reg_name = (''x1'') then map_option (\<lambda> v . (write_to   x1_ref) v s) ((of_regval   x1_ref) v) else
   if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to   Xs_ref) v s) ((of_regval   Xs_ref) v) else
   if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to   nextPC_ref) v s) ((of_regval   nextPC_ref) v) else
   if reg_name = (''PC'') then map_option (\<lambda> v . (write_to   PC_ref) v s) ((of_regval   PC_ref) v) else
@@ -1050,6 +1631,6 @@ definition register_accessors  :: "(string \<Rightarrow> regstate \<Rightarrow>(
 
 
 
-type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR "
-type_synonym 'a M =" (register_value, 'a, exception) monad "
+type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR "
+type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad "
 end
-- 
cgit v1.2.3


From 585c1b81c8e6efd3d7a84f317e1f3e18b84cbe89 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Tue, 10 Jul 2018 16:24:22 -0700
Subject: Turn off some riscv debug tracing.

---
 riscv/riscv_vmem.sail | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index fc9e7eb5..a067e94d 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -84,7 +84,7 @@ function translationException(a : AccessType, f : PTW_Error) -> ExceptionType =
     (Fetch, PTW_Access)     => E_Fetch_Access_Fault,
     (Fetch, _)              => E_Fetch_Page_Fault
   } in {
-    print("translationException(" ^ a ^ ", " ^ f ^ ") -> " ^ e);
+/*  print("translationException(" ^ a ^ ", " ^ f ^ ") -> " ^ e); */
     e
   }
 }
@@ -146,11 +146,11 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
   /* FIXME: we assume here that walks only access memory-backed addresses. */
   match (phys_mem_read(Data, EXTZ(pte_addr), 8, false, false, false)) {
     MemException(_) => {
-      print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
+/*    print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
             ^ " pt_base=" ^ BitStr(ptb)
             ^ " pt_ofs=" ^ BitStr(pt_ofs)
             ^ " pte_addr=" ^ BitStr(pte_addr)
-            ^ ": invalid pte address");
+            ^ ": invalid pte address"); */
       PTW_Failure(PTW_Access)
     },
     MemValue(v) => {
@@ -191,10 +191,15 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
               } else {
                 /* add the appropriate bits of the VPN to the superpage PPN */
                 let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
+/*              let res = append(ppn, va.PgOfs());
+                print("walk39: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
+                      ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
                 PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global)
               }
             } else {
               /* normal leaf PTE */
+/*            let res = append(pte.PPNi(), va.PgOfs());
+              print("walk39: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
               PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global)
             }
           }
-- 
cgit v1.2.3


From a480edc06d0a803c7ec133fe462005155d163bf7 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Tue, 10 Jul 2018 16:27:03 -0700
Subject: Add an option to specify the dtc to use for the riscv platform.

---
 riscv/platform_impl.ml | 17 +++++++++++++++--
 riscv/platform_main.ml |  5 ++++-
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/riscv/platform_impl.ml b/riscv/platform_impl.ml
index 5c238a1e..e593dce9 100644
--- a/riscv/platform_impl.ml
+++ b/riscv/platform_impl.ml
@@ -113,10 +113,23 @@ let dts = spike_dts "rv64imac" cpu_hz insns_per_tick mems;;
 let bytes_to_string bytes =
   String.init (List.length bytes) (fun i -> Char.chr (List.nth bytes i))
 
+let dtc_path = ref "/usr/bin/dtc"
+
+let set_dtc path =
+  try let st = Unix.stat path in
+      if st.Unix.st_kind = Unix.S_REG && st.Unix.st_perm != 0
+      then dtc_path := path
+      else ( Printf.eprintf "%s doesn't seem like a valid executable.\n%!" path;
+             exit 1)
+  with Unix.Unix_error (e, _, _) ->
+    ( Printf.eprintf "Error accessing %s: %s\n%!" path (Unix.error_message e);
+      exit 1)
+
 let make_dtb dts = (* Call the dtc compiler, assumed to be at /usr/bin/dtc *)
   try
+    let cmd = Printf.sprintf "%s -I dts" !dtc_path in
     let (cfrom, cto, cerr) =
-      Unix.open_process_full "/usr/bin/dtc -I dts" [||]
+      Unix.open_process_full cmd [||]
     in (
       output_string cto dts;
       (* print_endline " sent dts to dtc ..."; *)
@@ -136,7 +149,7 @@ let make_dtb dts = (* Call the dtc compiler, assumed to be at /usr/bin/dtc *)
       let emsg = bytes_to_string (accum_bytes cerr []) in
       match Unix.close_process_full (cfrom, cto, cerr) with
         | Unix.WEXITED 0 -> dtb
-        | _ -> (Printf.printf "%s\n" ("Error executing dtc: " ^ emsg);
+        | _ -> (Printf.printf "%s\n%!" ("Error executing dtc: " ^ emsg);
                 exit 1)
     )
   with Unix.Unix_error (e, fn, _) ->
diff --git a/riscv/platform_main.ml b/riscv/platform_main.ml
index 4c33e24d..e204daee 100644
--- a/riscv/platform_main.ml
+++ b/riscv/platform_main.ml
@@ -72,7 +72,10 @@ let options = Arg.align ([("-dump-dts",
                            " enable dirty-bit update during page-table walks");
                           ("-enable-misaligned-access",
                            Arg.Set P.config_enable_misaligned_access,
-                           " enable misaligned accesses without M-mode traps")
+                           " enable misaligned accesses without M-mode traps");
+                          ("-with-dtc",
+                           Arg.String PI.set_dtc,
+                           " full path to dtc to use")
                          ])
 
 let usage_msg = "RISC-V platform options:"
-- 
cgit v1.2.3


From 7198c68593a4802380bd80a65a1cf199c9ba74c8 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Wed, 11 Jul 2018 11:04:38 +0100
Subject: Update HOL4 snapshot with Thomas' fixes

---
 snapshots/hol4/sail/aarch64/aarch64_monoScript.sml | 36 ++++++++-----
 snapshots/hol4/sail/cheri/cheriScript.sml          | 36 ++++++++-----
 snapshots/hol4/sail/cheri/mips_extrasScript.sml    | 11 +++-
 .../lib/hol/sail2_operators_bitlistsScript.sml     | 60 +++++-----------------
 .../sail/lib/hol/sail2_operators_mwordsScript.sml  | 54 +++++--------------
 snapshots/hol4/sail/mips/mipsScript.sml            | 36 ++++++++-----
 snapshots/hol4/sail/mips/mips_extrasScript.sml     | 11 +++-
 snapshots/hol4/sail/riscv/riscvScript.sml          | 45 ++++------------
 8 files changed, 127 insertions(+), 162 deletions(-)

diff --git a/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml b/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml
index b454337e..3c70ce1c 100644
--- a/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml
+++ b/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml
@@ -170,14 +170,17 @@ val _ = Define `
 
 val _ = Define `
  ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j=
-    (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
+    (((and_vec xs
+         ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+        :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
 
 
 (*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
 
 val _ = Define `
  ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j=
-    (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i))  :  'n words$word)) in
+    (let (m : 'n bits) =
+     ((slice_mask ((int_of_num (words$word_len xs))) j ((((j - i)) + (( 1 : int):ii)))  :  'n words$word)) in
    (((and_vec xs m  :  'n words$word)) = m)))`;
 
 
@@ -209,12 +212,15 @@ val _ = Define `
  ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j'))  :  'n words$word))  :  'n words$word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int_of_num (words$word_len xs))) j' ((((i' - j')) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j'
        :  'n words$word)) in
    (xs = ys)))`;
 
@@ -225,16 +231,18 @@ val _ = Define `
  ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j'))  :  'm words$word))  :  'm words$word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int_of_num (words$word_len ys))) j' ((((i' - j')) + (( 1 : int):ii)))  :  'm words$word))
+           :  'm words$word)) j'
        :  'm words$word)) in
    (or_vec
-      ((sub_vec_int ((shiftl ((extzv s__tv xs  :  's words$word)) i'  :  's words$word))
-          ((j' - (( 1 : int):ii)))
+      ((shiftl ((extzv s__tv xs  :  's words$word)) ((((i' - j')) + (( 1 : int):ii)))
          :  's words$word)) ((extzv s__tv ys  :  's words$word))
      :  's words$word)))`;
 
@@ -245,7 +253,9 @@ val _ = Define `
  ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
 
@@ -296,7 +306,9 @@ val _ = Define `
  ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) i
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) i
        :  'n words$word)) in
    lem$w2ui xs))`;
 
diff --git a/snapshots/hol4/sail/cheri/cheriScript.sml b/snapshots/hol4/sail/cheri/cheriScript.sml
index 5fa55723..01410ba7 100644
--- a/snapshots/hol4/sail/cheri/cheriScript.sml
+++ b/snapshots/hol4/sail/cheri/cheriScript.sml
@@ -2904,14 +2904,17 @@ val _ = Define `
 
 val _ = Define `
  ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j=
-    (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
+    (((and_vec xs
+         ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+        :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
 
 
 (*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
 
 val _ = Define `
  ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j=
-    (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i))  :  'n words$word)) in
+    (let (m : 'n bits) =
+     ((slice_mask ((int_of_num (words$word_len xs))) j ((((j - i)) + (( 1 : int):ii)))  :  'n words$word)) in
    (((and_vec xs m  :  'n words$word)) = m)))`;
 
 
@@ -2943,12 +2946,15 @@ val _ = Define `
  ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j'))  :  'n words$word))  :  'n words$word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int_of_num (words$word_len xs))) j' ((((i' - j')) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j'
        :  'n words$word)) in
    (xs = ys)))`;
 
@@ -2959,16 +2965,18 @@ val _ = Define `
  ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j'))  :  'm words$word))  :  'm words$word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int_of_num (words$word_len ys))) j' ((((i' - j')) + (( 1 : int):ii)))  :  'm words$word))
+           :  'm words$word)) j'
        :  'm words$word)) in
    (or_vec
-      ((sub_vec_int ((shiftl ((extzv s__tv xs  :  's words$word)) i'  :  's words$word))
-          ((j' - (( 1 : int):ii)))
+      ((shiftl ((extzv s__tv xs  :  's words$word)) ((((i' - j')) + (( 1 : int):ii)))
          :  's words$word)) ((extzv s__tv ys  :  's words$word))
      :  's words$word)))`;
 
@@ -2979,7 +2987,9 @@ val _ = Define `
  ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
 
@@ -3030,7 +3040,9 @@ val _ = Define `
  ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) i
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) i
        :  'n words$word)) in
    lem$w2ui xs))`;
 
diff --git a/snapshots/hol4/sail/cheri/mips_extrasScript.sml b/snapshots/hol4/sail/cheri/mips_extrasScript.sml
index aef40b53..1af18e62 100644
--- a/snapshots/hol4/sail/cheri/mips_extrasScript.sml
+++ b/snapshots/hol4/sail/cheri/mips_extrasScript.sml
@@ -225,9 +225,18 @@ val _ = Define `
 
 
 val _ = Define `
- ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bv 
+ ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (print_endline ( STRCAT msg (string_of_bv 
   dict_Sail2_values_Bitvector_a bs))))`;
 
+val _ = Define `
+ ((prerr_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bv 
+  dict_Sail2_values_Bitvector_a bs))))`;
+
+
+(*val prerr_string : string -> unit*)
+val _ = Define `
+ ((prerr_string:string -> unit) _=  () )`;
+
 
 (*val get_time_ns : unit -> integer*)
 val _ = Define `
diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
index e6b4da4f..da349336 100644
--- a/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
+++ b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
@@ -328,76 +328,40 @@ val _ = Define `
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T))`;
 
 
-(*val add_vec_int       : list bitU -> integer -> list bitU*)
-(*val adds_vec_int      : list bitU -> integer -> list bitU*)
-(*val sub_vec_int       : list bitU -> integer -> list bitU*)
-(*val subs_vec_int      : list bitU -> integer -> list bitU*)
-(*val mult_vec_int      : list bitU -> integer -> list bitU*)
-(*val mults_vec_int     : list bitU -> integer -> list bitU*)
+(*val add_vec_int      : list bitU -> integer -> list bitU*)
+(*val sub_vec_int      : list bitU -> integer -> list bitU*)
+(*val mult_vec_int     : list bitU -> integer -> list bitU*)
 val _ = Define `
- ((add_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
-  (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
-
-val _ = Define `
- ((adds_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
+ ((add_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
   (instance_Sail2_values_Bitvector_list_dict
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`;
 
 val _ = Define `
- ((sub_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
-  (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
-
-val _ = Define `
- ((subs_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
+ ((sub_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
   (instance_Sail2_values_Bitvector_list_dict
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`;
 
 val _ = Define `
- ((mult_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_double_bl 
-  (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
-
-val _ = Define `
- ((mults_vec_int0:(bitU)list -> int ->(bitU)list) l r=  (arith_op_double_bl 
+ ((mult_vec_int0:(bitU)list -> int ->(bitU)list) l r=  (arith_op_double_bl 
   (instance_Sail2_values_Bitvector_list_dict
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
 
 
-(*val add_int_vec       : integer -> list bitU -> list bitU*)
-(*val adds_int_vec      : integer -> list bitU -> list bitU*)
-(*val sub_int_vec       : integer -> list bitU -> list bitU*)
-(*val subs_int_vec      : integer -> list bitU -> list bitU*)
-(*val mult_int_vec      : integer -> list bitU -> list bitU*)
-(*val mults_int_vec     : integer -> list bitU -> list bitU*)
+(*val add_int_vec      : integer -> list bitU -> list bitU*)
+(*val sub_int_vec      : integer -> list bitU -> list bitU*)
+(*val mult_int_vec     : integer -> list bitU -> list bitU*)
 val _ = Define `
- ((add_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
-  (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
-
-val _ = Define `
- ((adds_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
+ ((add_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
   (instance_Sail2_values_Bitvector_list_dict
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`;
 
 val _ = Define `
- ((sub_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
-  (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
-
-val _ = Define `
- ((subs_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
+ ((sub_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
   (instance_Sail2_values_Bitvector_list_dict
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`;
 
 val _ = Define `
- ((mult_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_double_bl 
-  (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
-
-val _ = Define `
- ((mults_int_vec0:int ->(bitU)list ->(bitU)list) l r=  (arith_op_double_bl 
+ ((mult_int_vec0:int ->(bitU)list ->(bitU)list) l r=  (arith_op_double_bl 
   (instance_Sail2_values_Bitvector_list_dict
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
 
diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
index 603daf57..9276cfef 100644
--- a/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
+++ b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
@@ -278,65 +278,35 @@ val _ = Define `
  ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r=  (integer_word$i2w ((int_of_mword T (words$sw2sw l :  'b words$word)) * (int_of_mword T (words$sw2sw r :  'b words$word)))))`;
 
 
-(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val adds_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val subs_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
-(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+(*val add_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val sub_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
 val _ = Define `
- ((add_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
-
-val _ = Define `
- ((adds_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
+ ((add_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
   instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
 
 val _ = Define `
- ((sub_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
-
-val _ = Define `
- ((subs_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
+ ((sub_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
   instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
 
 val _ = Define `
- ((mult_vec_int:'a words$word -> int -> 'b words$word)  l r=  (arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  F (words$w2w l :  'b words$word) r))`;
-
-val _ = Define `
- ((mults_vec_int:'a words$word -> int -> 'b words$word) l r=  (arith_op_bv_int 
+ ((mult_vec_int:'a words$word -> int -> 'b words$word) l r=  (arith_op_bv_int 
   instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  T  (words$sw2sw l :  'b words$word) r))`;
 
 
-(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val adds_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val subs_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
-(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+(*val add_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val sub_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
 val _ = Define `
- ((add_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
-
-val _ = Define `
- ((adds_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
+ ((add_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
   instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
 
 val _ = Define `
- ((sub_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
-
-val _ = Define `
- ((subs_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
+ ((sub_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
   instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
 
 val _ = Define `
- ((mult_int_vec:int -> 'a words$word -> 'b words$word)  l r=  (arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  F l (words$w2w r :  'b words$word)))`;
-
-val _ = Define `
- ((mults_int_vec:int -> 'a words$word -> 'b words$word) l r=  (arith_op_int_bv 
+ ((mult_int_vec:int -> 'a words$word -> 'b words$word) l r=  (arith_op_int_bv 
   instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  T  l (words$sw2sw r :  'b words$word)))`;
 
 
diff --git a/snapshots/hol4/sail/mips/mipsScript.sml b/snapshots/hol4/sail/mips/mipsScript.sml
index 928a7276..2758a979 100644
--- a/snapshots/hol4/sail/mips/mipsScript.sml
+++ b/snapshots/hol4/sail/mips/mipsScript.sml
@@ -2728,14 +2728,17 @@ val _ = Define `
 
 val _ = Define `
  ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j=
-    (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
+    (((and_vec xs
+         ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+        :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
 
 
 (*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*)
 
 val _ = Define `
  ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j=
-    (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i))  :  'n words$word)) in
+    (let (m : 'n bits) =
+     ((slice_mask ((int_of_num (words$word_len xs))) j ((((j - i)) + (( 1 : int):ii)))  :  'n words$word)) in
    (((and_vec xs m  :  'n words$word)) = m)))`;
 
 
@@ -2767,12 +2770,15 @@ val _ = Define `
  ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j'))  :  'n words$word))  :  'n words$word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int_of_num (words$word_len xs))) j' ((((i' - j')) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j'
        :  'n words$word)) in
    (xs = ys)))`;
 
@@ -2783,16 +2789,18 @@ val _ = Define `
  ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    let ys =
      ((shiftr
-        ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j'))  :  'm words$word))  :  'm words$word))
-        j'
+        ((and_vec ys
+            ((slice_mask ((int_of_num (words$word_len ys))) j' ((((i' - j')) + (( 1 : int):ii)))  :  'm words$word))
+           :  'm words$word)) j'
        :  'm words$word)) in
    (or_vec
-      ((sub_vec_int ((shiftl ((extzv s__tv xs  :  's words$word)) i'  :  's words$word))
-          ((j' - (( 1 : int):ii)))
+      ((shiftl ((extzv s__tv xs  :  's words$word)) ((((i' - j')) + (( 1 : int):ii)))
          :  's words$word)) ((extzv s__tv ys  :  's words$word))
      :  's words$word)))`;
 
@@ -2803,7 +2811,9 @@ val _ = Define `
  ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) j
        :  'n words$word)) in
    (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
 
@@ -2854,7 +2864,9 @@ val _ = Define `
  ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j=
     (let xs =
      ((shiftr
-        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) i
+        ((and_vec xs
+            ((slice_mask ((int_of_num (words$word_len xs))) j ((((i - j)) + (( 1 : int):ii)))  :  'n words$word))
+           :  'n words$word)) i
        :  'n words$word)) in
    lem$w2ui xs))`;
 
diff --git a/snapshots/hol4/sail/mips/mips_extrasScript.sml b/snapshots/hol4/sail/mips/mips_extrasScript.sml
index f89e7b2f..5cfb5b2d 100644
--- a/snapshots/hol4/sail/mips/mips_extrasScript.sml
+++ b/snapshots/hol4/sail/mips/mips_extrasScript.sml
@@ -225,9 +225,18 @@ val _ = Define `
 
 
 val _ = Define `
- ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bv 
+ ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (print_endline ( STRCAT msg (string_of_bv 
   dict_Sail2_values_Bitvector_a bs))))`;
 
+val _ = Define `
+ ((prerr_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs=  (prerr_endline ( STRCAT msg (string_of_bv 
+  dict_Sail2_values_Bitvector_a bs))))`;
+
+
+(*val prerr_string : string -> unit*)
+val _ = Define `
+ ((prerr_string:string -> unit) _=  () )`;
+
 
 (*val get_time_ns : unit -> integer*)
 val _ = Define `
diff --git a/snapshots/hol4/sail/riscv/riscvScript.sml b/snapshots/hol4/sail/riscv/riscvScript.sml
index bd56ca74..e4eb3718 100644
--- a/snapshots/hol4/sail/riscv/riscvScript.sml
+++ b/snapshots/hol4/sail/riscv/riscvScript.sml
@@ -8887,25 +8887,16 @@ val _ = Define `
 
 val _ = Define `
  ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)=
-    (let (e : ExceptionType) =
-     ((case (a, f) of
-       (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
-     | (ReadWrite, _) => E_SAMO_Page_Fault
-     | (Read, PTW_Access) => E_Load_Access_Fault
-     | (Read, _) => E_Load_Page_Fault
-     | (Write, PTW_Access) => E_SAMO_Access_Fault
-     | (Write, _) => E_SAMO_Page_Fault
-     | (Fetch, PTW_Access) => E_Fetch_Access_Fault
-     | (Fetch, _) => E_Fetch_Page_Fault
-     )) in
-   let (_ : unit) =
-     (print_endline
-       ((STRCAT "translationException("
-           ((STRCAT ((accessType_to_str a))
-               ((STRCAT ", "
-                   ((STRCAT ((ptw_error_to_str f))
-                       ((STRCAT ") -> " ((exceptionType_to_str e))))))))))))) in
-   e))`;
+    ((case (a, f) of
+     (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+   | (ReadWrite, _) => E_SAMO_Page_Fault
+   | (Read, PTW_Access) => E_Load_Access_Fault
+   | (Read, _) => E_Load_Page_Fault
+   | (Write, PTW_Access) => E_SAMO_Access_Fault
+   | (Write, _) => E_SAMO_Page_Fault
+   | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+   | (Fetch, _) => E_Fetch_Page_Fault
+   )))`;
 
 
 val _ = Define `
@@ -9296,21 +9287,7 @@ val _ = Define `
    (phys_mem_read Data ((EXTZ (( 64 : int):ii) pte_addr  :  64 words$word)) (( 8 : int):ii) F F F
      : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) . 
    (case w__0 of
-     MemException (_) =>
-      let (_ : unit) =
-        (print_endline
-          ((STRCAT "walk39(vaddr="
-              ((STRCAT ((string_of_bits vaddr))
-                  ((STRCAT " level="
-                      ((STRCAT ((stringFromInteger level))
-                          ((STRCAT " pt_base="
-                              ((STRCAT ((string_of_bits ptb))
-                                  ((STRCAT " pt_ofs="
-                                      ((STRCAT ((string_of_bits pt_ofs))
-                                          ((STRCAT " pte_addr="
-                                              ((STRCAT ((string_of_bits pte_addr))
-                                                  ": invalid pte address"))))))))))))))))))))) in
-      sail2_state_monad$returnS (PTW_Failure PTW_Access)
+     MemException (_) => sail2_state_monad$returnS (PTW_Failure PTW_Access)
    | MemValue (v) =>
       let pte = (Mk_SV39_PTE v) in
       let pbits = ((get_SV39_PTE_BITS pte  :  8 words$word)) in
-- 
cgit v1.2.3


From 62d81f160dc9b1673c946a8bba66aff7fc835a95 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Wed, 11 Jul 2018 11:13:02 +0100
Subject: Manage expectations about processing time for HOL4 models

---
 snapshots/hol4/README.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md
index 5ce37726..140f1e0f 100644
--- a/snapshots/hol4/README.md
+++ b/snapshots/hol4/README.md
@@ -3,3 +3,6 @@
 These theories are a snapshot of the generated files for the Sail
 MIPS, CHERI, RISC-V, and Aarch64 models, translated to HOL4 via Lem.
 They only require HOL4; the necessary Lem library files are included.
+
+Note that HOL4 takes a substantial amount of time to process the definition of
+the `regstate` record.  In particular, allow over an hour for the MIPS model.
-- 
cgit v1.2.3


From c2e3f39158d800cf768664f7e61a27c9a824559c Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Wed, 11 Jul 2018 12:19:14 +0100
Subject: Fix riscv_duopod build.

---
 riscv/riscv_duopod.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/riscv_duopod.sail b/riscv/riscv_duopod.sail
index ddb4f6e5..ff1e4065 100644
--- a/riscv/riscv_duopod.sail
+++ b/riscv/riscv_duopod.sail
@@ -37,7 +37,7 @@ overload X = {rX, wX}
 
 val MEMr : forall 'n. (xlen_t, atom('n)) -> bits(8 * 'n) effect {rmem}
 function MEMr (addr, width) =
-  match __RISCV_read(addr, width) { Some(v) => v, None() => zeros(8 * width) }
+  match __RISCV_read(addr, width, false, false, false) { Some(v) => v, None() => zeros(8 * width) }
 
 /* Instruction decode and execute */
 enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, RISCV_XORI, RISCV_ORI, RISCV_ANDI} /* immediate ops */
-- 
cgit v1.2.3


From 7e79a2adde6a75e33973a1cd559f85a47551b18a Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Wed, 11 Jul 2018 12:59:59 +0100
Subject: Partially revert change to add_vec_int et al

On second thought, this change should not really make a difference; the CHERI
test suite still passes without it.  Moreover, using unsigned conversion of the
vector argument leads to more convenient lemmas for the provers.
---
 lib/isabelle/Sail2_operators_mwords_lemmas.thy |  9 ++++-----
 src/gen_lib/sail2_operators_bitlists.lem       | 26 +++++++++++++-------------
 src/gen_lib/sail2_operators_mwords.lem         | 26 +++++++++++++-------------
 3 files changed, 30 insertions(+), 31 deletions(-)

diff --git a/lib/isabelle/Sail2_operators_mwords_lemmas.thy b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
index 47bf32b2..fd54c93a 100644
--- a/lib/isabelle/Sail2_operators_mwords_lemmas.thy
+++ b/lib/isabelle/Sail2_operators_mwords_lemmas.thy
@@ -153,11 +153,10 @@ declare adds_vec_def[simp]
 declare subs_vec_def[simp]
 declare mults_vec_def[simp]
 
-lemma arith_vec_int_simps:
-  fixes l :: "'a::len word"
-  shows "add_vec_int l r = word_of_int (sint l + sint (word_of_int r :: 'a word))"
-    and "sub_vec_int l r = word_of_int (sint l - sint (word_of_int r :: 'a word))"
-    and "(mult_vec_int l r :: 'b::len word) = word_of_int (sint (scast l :: 'b word) * sint (word_of_int r :: 'b word))"
+lemma arith_vec_int_simps[simp]:
+  "add_vec_int l r = l + (word_of_int r)"
+  "sub_vec_int l r = l - (word_of_int r)"
+  "mult_vec_int l r = (ucast l) * (word_of_int r)"
   unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
   by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
 
diff --git a/src/gen_lib/sail2_operators_bitlists.lem b/src/gen_lib/sail2_operators_bitlists.lem
index b9a2fa86..186e0a09 100644
--- a/src/gen_lib/sail2_operators_bitlists.lem
+++ b/src/gen_lib/sail2_operators_bitlists.lem
@@ -145,19 +145,19 @@ let subs_vec  = arith_op_bv integerMinus true
 let mult_vec  = arith_op_double_bl integerMult false
 let mults_vec = arith_op_double_bl integerMult true
 
-val add_vec_int      : list bitU -> integer -> list bitU
-val sub_vec_int      : list bitU -> integer -> list bitU
-val mult_vec_int     : list bitU -> integer -> list bitU
-let add_vec_int  l r = arith_op_bv_int integerAdd true l r
-let sub_vec_int  l r = arith_op_bv_int integerMinus true l r
-let mult_vec_int l r = arith_op_double_bl integerMult true l (of_int (length l) r)
-
-val add_int_vec      : integer -> list bitU -> list bitU
-val sub_int_vec      : integer -> list bitU -> list bitU
-val mult_int_vec     : integer -> list bitU -> list bitU
-let add_int_vec  l r = arith_op_int_bv integerAdd true l r
-let sub_int_vec  l r = arith_op_int_bv integerMinus true l r
-let mult_int_vec l r = arith_op_double_bl integerMult true (of_int (length r) l) r
+val add_vec_int       : list bitU -> integer -> list bitU
+val sub_vec_int       : list bitU -> integer -> list bitU
+val mult_vec_int      : list bitU -> integer -> list bitU
+let add_vec_int   l r = arith_op_bv_int integerAdd false l r
+let sub_vec_int   l r = arith_op_bv_int integerMinus false l r
+let mult_vec_int  l r = arith_op_double_bl integerMult false l (of_int (length l) r)
+
+val add_int_vec       : integer -> list bitU -> list bitU
+val sub_int_vec       : integer -> list bitU -> list bitU
+val mult_int_vec      : integer -> list bitU -> list bitU
+let add_int_vec   l r = arith_op_int_bv integerAdd false l r
+let sub_int_vec   l r = arith_op_int_bv integerMinus false l r
+let mult_int_vec  l r = arith_op_double_bl integerMult false (of_int (length r) l) r
 
 val add_vec_bit      : list bitU -> bitU -> list bitU
 val adds_vec_bit     : list bitU -> bitU -> list bitU
diff --git a/src/gen_lib/sail2_operators_mwords.lem b/src/gen_lib/sail2_operators_mwords.lem
index c0b7f2d1..a7fb7c50 100644
--- a/src/gen_lib/sail2_operators_mwords.lem
+++ b/src/gen_lib/sail2_operators_mwords.lem
@@ -142,19 +142,19 @@ let subs_vec  l r = arith_op_bv integerMinus true  l r
 let mult_vec  l r = arith_op_bv integerMult  false (zeroExtend l : mword 'b) (zeroExtend r : mword 'b)
 let mults_vec l r = arith_op_bv integerMult  true  (signExtend l : mword 'b) (signExtend r : mword 'b)
 
-val add_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
-val sub_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
-val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
-let add_vec_int  l r = arith_op_bv_int integerAdd   true  l r
-let sub_vec_int  l r = arith_op_bv_int integerMinus true  l r
-let mult_vec_int l r = arith_op_bv_int integerMult  true  (signExtend l : mword 'b) r
-
-val add_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
-val sub_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
-val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
-let add_int_vec  l r = arith_op_int_bv integerAdd   true  l r
-let sub_int_vec  l r = arith_op_int_bv integerMinus true  l r
-let mult_int_vec l r = arith_op_int_bv integerMult  true  l (signExtend r : mword 'b)
+val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
+let add_vec_int   l r = arith_op_bv_int integerAdd   false l r
+let sub_vec_int   l r = arith_op_bv_int integerMinus false l r
+let mult_vec_int  l r = arith_op_bv_int integerMult  false (zeroExtend l : mword 'b) r
+
+val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+let add_int_vec   l r = arith_op_int_bv integerAdd   false l r
+let sub_int_vec   l r = arith_op_int_bv integerMinus false l r
+let mult_int_vec  l r = arith_op_int_bv integerMult  false l (zeroExtend r : mword 'b)
 
 val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a
 val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a
-- 
cgit v1.2.3


From e2289d8a86ff57881e1008b42a11409974254b69 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Wed, 11 Jul 2018 13:22:18 +0100
Subject: Update Isabelle and HOL snapshots

---
 .../lib/hol/sail2_operators_bitlistsScript.sml     | 36 +++++++++++-----------
 .../sail/lib/hol/sail2_operators_mwordsScript.sml  | 36 +++++++++++-----------
 .../isabelle/lib/sail/Sail2_operators_bitlists.thy | 36 +++++++++++-----------
 .../isabelle/lib/sail/Sail2_operators_mwords.thy   | 36 +++++++++++-----------
 .../lib/sail/Sail2_operators_mwords_lemmas.thy     |  9 +++---
 5 files changed, 76 insertions(+), 77 deletions(-)

diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
index da349336..88c06749 100644
--- a/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
+++ b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml
@@ -328,42 +328,42 @@ val _ = Define `
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T))`;
 
 
-(*val add_vec_int      : list bitU -> integer -> list bitU*)
-(*val sub_vec_int      : list bitU -> integer -> list bitU*)
-(*val mult_vec_int     : list bitU -> integer -> list bitU*)
+(*val add_vec_int       : list bitU -> integer -> list bitU*)
+(*val sub_vec_int       : list bitU -> integer -> list bitU*)
+(*val mult_vec_int      : list bitU -> integer -> list bitU*)
 val _ = Define `
- ((add_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
+ ((add_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`;
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
 
 val _ = Define `
- ((sub_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_bv_int 
+ ((sub_vec_int0:(bitU)list -> int ->(bitU)list)   l r=  (arith_op_bv_int 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`;
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
 
 val _ = Define `
- ((mult_vec_int0:(bitU)list -> int ->(bitU)list) l r=  (arith_op_double_bl 
+ ((mult_vec_int0:(bitU)list -> int ->(bitU)list)  l r=  (arith_op_double_bl 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
 
 
-(*val add_int_vec      : integer -> list bitU -> list bitU*)
-(*val sub_int_vec      : integer -> list bitU -> list bitU*)
-(*val mult_int_vec     : integer -> list bitU -> list bitU*)
+(*val add_int_vec       : integer -> list bitU -> list bitU*)
+(*val sub_int_vec       : integer -> list bitU -> list bitU*)
+(*val mult_int_vec      : integer -> list bitU -> list bitU*)
 val _ = Define `
- ((add_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
+ ((add_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`;
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
 
 val _ = Define `
- ((sub_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_int_bv 
+ ((sub_int_vec0:int ->(bitU)list ->(bitU)list)   l r=  (arith_op_int_bv 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`;
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
 
 val _ = Define `
- ((mult_int_vec0:int ->(bitU)list ->(bitU)list) l r=  (arith_op_double_bl 
+ ((mult_int_vec0:int ->(bitU)list ->(bitU)list)  l r=  (arith_op_double_bl 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
 
 
 (*val add_vec_bit      : list bitU -> bitU -> list bitU*)
diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
index 9276cfef..5b0e7723 100644
--- a/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
+++ b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml
@@ -278,36 +278,36 @@ val _ = Define `
  ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r=  (integer_word$i2w ((int_of_mword T (words$sw2sw l :  'b words$word)) * (int_of_mword T (words$sw2sw r :  'b words$word)))))`;
 
 
-(*val add_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val sub_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
 val _ = Define `
- ((add_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
+ ((add_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
 
 val _ = Define `
- ((sub_vec_int:'a words$word -> int -> 'a words$word)  l r=  (arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
+ ((sub_vec_int:'a words$word -> int -> 'a words$word)   l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
 
 val _ = Define `
- ((mult_vec_int:'a words$word -> int -> 'b words$word) l r=  (arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  T  (words$sw2sw l :  'b words$word) r))`;
+ ((mult_vec_int:'a words$word -> int -> 'b words$word)  l r=  (arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  F (words$w2w l :  'b words$word) r))`;
 
 
-(*val add_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val sub_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
 val _ = Define `
- ((add_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   T  l r))`;
+ ((add_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (+)   F l r))`;
 
 val _ = Define `
- ((sub_int_vec:int -> 'a words$word -> 'a words$word)  l r=  (arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T  l r))`;
+ ((sub_int_vec:int -> 'a words$word -> 'a words$word)   l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
 
 val _ = Define `
- ((mult_int_vec:int -> 'a words$word -> 'b words$word) l r=  (arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  T  l (words$sw2sw r :  'b words$word)))`;
+ ((mult_int_vec:int -> 'a words$word -> 'b words$word)  l r=  (arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * )  F l (words$w2w r :  'b words$word)))`;
 
 
 (*val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy b/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
index 96c38a6a..35f43769 100644
--- a/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
+++ b/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
@@ -333,42 +333,42 @@ definition mults_vec  :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)
      instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True )"
 
 
-(*val add_vec_int      : list bitU -> integer -> list bitU*)
-(*val sub_vec_int      : list bitU -> integer -> list bitU*)
-(*val mult_vec_int     : list bitU -> integer -> list bitU*)
+(*val add_vec_int       : list bitU -> integer -> list bitU*)
+(*val sub_vec_int       : list bitU -> integer -> list bitU*)
+(*val mult_vec_int      : list bitU -> integer -> list bitU*)
 definition add_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " add_vec_int  l r = ( arith_op_bv_int 
+     " add_vec_int   l r = ( arith_op_bv_int 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) True l r )"
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) False l r )"
 
 definition sub_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " sub_vec_int  l r = ( arith_op_bv_int 
+     " sub_vec_int   l r = ( arith_op_bv_int 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) True l r )"
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) False l r )"
 
 definition mult_vec_int  :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list "  where 
-     " mult_vec_int l r = ( arith_op_double_bl 
+     " mult_vec_int  l r = ( arith_op_double_bl 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))"
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) False l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))"
 
 
-(*val add_int_vec      : integer -> list bitU -> list bitU*)
-(*val sub_int_vec      : integer -> list bitU -> list bitU*)
-(*val mult_int_vec     : integer -> list bitU -> list bitU*)
+(*val add_int_vec       : integer -> list bitU -> list bitU*)
+(*val sub_int_vec       : integer -> list bitU -> list bitU*)
+(*val mult_int_vec      : integer -> list bitU -> list bitU*)
 definition add_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " add_int_vec  l r = ( arith_op_int_bv 
+     " add_int_vec   l r = ( arith_op_int_bv 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) True l r )"
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) False l r )"
 
 definition sub_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " sub_int_vec  l r = ( arith_op_int_bv 
+     " sub_int_vec   l r = ( arith_op_int_bv 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) True l r )"
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) False l r )"
 
 definition mult_int_vec  :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list "  where 
-     " mult_int_vec l r = ( arith_op_double_bl 
+     " mult_int_vec  l r = ( arith_op_double_bl 
   (instance_Sail2_values_Bitvector_list_dict
-     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )"
+     instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) False (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )"
 
 
 (*val add_vec_bit      : list bitU -> bitU -> list bitU*)
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy b/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
index c6d1a865..44d29a7f 100644
--- a/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
+++ b/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
@@ -283,36 +283,36 @@ definition mults_vec  :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<R
      " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))"
 
 
-(*val add_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val sub_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
-(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
 definition add_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " add_vec_int  l r = ( arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+)   True  l r )"
+     " add_vec_int   l r = ( arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+)   False l r )"
 
 definition sub_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " sub_vec_int  l r = ( arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
+     " sub_vec_int   l r = ( arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) False l r )"
 
 definition mult_vec_int  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " mult_vec_int l r = ( arith_op_bv_int 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*)  True  (Word.scast l :: ( 'b::len)Word.word) r )"
+     " mult_vec_int  l r = ( arith_op_bv_int 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*)  False (Word.ucast l :: ( 'b::len)Word.word) r )"
 
 
-(*val add_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val sub_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
-(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
 definition add_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " add_int_vec  l r = ( arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+)   True  l r )"
+     " add_int_vec   l r = ( arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+)   False l r )"
 
 definition sub_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " sub_int_vec  l r = ( arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True  l r )"
+     " sub_int_vec   l r = ( arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) False l r )"
 
 definition mult_int_vec  :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word "  where 
-     " mult_int_vec l r = ( arith_op_int_bv 
-  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*)  True  l (Word.scast r :: ( 'b::len)Word.word))"
+     " mult_int_vec  l r = ( arith_op_int_bv 
+  instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*)  False l (Word.ucast r :: ( 'b::len)Word.word))"
 
 
 (*val add_vec_bool  : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
index 47bf32b2..fd54c93a 100644
--- a/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
+++ b/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
@@ -153,11 +153,10 @@ declare adds_vec_def[simp]
 declare subs_vec_def[simp]
 declare mults_vec_def[simp]
 
-lemma arith_vec_int_simps:
-  fixes l :: "'a::len word"
-  shows "add_vec_int l r = word_of_int (sint l + sint (word_of_int r :: 'a word))"
-    and "sub_vec_int l r = word_of_int (sint l - sint (word_of_int r :: 'a word))"
-    and "(mult_vec_int l r :: 'b::len word) = word_of_int (sint (scast l :: 'b word) * sint (word_of_int r :: 'b word))"
+lemma arith_vec_int_simps[simp]:
+  "add_vec_int l r = l + (word_of_int r)"
+  "sub_vec_int l r = l - (word_of_int r)"
+  "mult_vec_int l r = (ucast l) * (word_of_int r)"
   unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
   by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
 
-- 
cgit v1.2.3


From 10ff48091a2bc49756fa48daff82170f907878fe Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Wed, 11 Jul 2018 13:42:01 +0100
Subject: Add ROOTS file to Isabelle snapshot

---
 snapshots/isabelle/README.md | 7 ++++---
 snapshots/isabelle/ROOTS     | 5 +++++
 2 files changed, 9 insertions(+), 3 deletions(-)
 create mode 100644 snapshots/isabelle/ROOTS

diff --git a/snapshots/isabelle/README.md b/snapshots/isabelle/README.md
index cabf4fc0..d2b4fe71 100644
--- a/snapshots/isabelle/README.md
+++ b/snapshots/isabelle/README.md
@@ -9,11 +9,12 @@ up-to-date.
 In order to open a theory of one of the specifications in Isabelle, use the `-l
 Sail` command-line flag to load the session containing the Sail library.
 Snapshots of the Sail and Lem libraries are in the [lib/sail](lib/sail/) and
-[lib/lem](lib/lem/) directories, respectively.  You can tell Isabelle where to
-find them using the `-d` flag, as in
+[lib/lem](lib/lem/) directories, respectively.  The ROOTS file in this directory
+contains pointers to them; you can tell Isabelle to use it with the `-d` flag,
+as in
 
 ```
-isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy
+isabelle jedit -l Sail -d . riscv/Riscv.thy
 ```
 
 This will open the RISC-V specification.
diff --git a/snapshots/isabelle/ROOTS b/snapshots/isabelle/ROOTS
new file mode 100644
index 00000000..40dc0aef
--- /dev/null
+++ b/snapshots/isabelle/ROOTS
@@ -0,0 +1,5 @@
+aarch64
+cheri
+lib/lem
+lib/sail
+riscv
-- 
cgit v1.2.3


From 2b9eace6110da21a915f594a0b6f664991d9cabd Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Wed, 11 Jul 2018 13:58:25 +0100
Subject: Note that a suitable HOL version is required

---
 snapshots/hol4/README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md
index 140f1e0f..8348eea0 100644
--- a/snapshots/hol4/README.md
+++ b/snapshots/hol4/README.md
@@ -4,5 +4,11 @@ These theories are a snapshot of the generated files for the Sail
 MIPS, CHERI, RISC-V, and Aarch64 models, translated to HOL4 via Lem.
 They only require HOL4; the necessary Lem library files are included.
 
+A recent checkout of HOL4 from the repository at
+<https://github.com/HOL-Theorem-Prover/HOL/> is required.  This snapshot was
+successfully built with commit `7ed3f12`, for example.  Some older versions
+will fail with a Holdep error due to a lexer bug in HOL that has now been
+fixed.
+
 Note that HOL4 takes a substantial amount of time to process the definition of
 the `regstate` record.  In particular, allow over an hour for the MIPS model.
-- 
cgit v1.2.3


From e8a7d7a75c7032778cfe44fc4fe8b7903ab11034 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Wed, 11 Jul 2018 16:35:49 +0100
Subject: Fixes to Isabelle snapshot

Remove absolute paths, update Aarch64_extras.thy
---
 snapshots/isabelle/aarch64/Aarch64.thy        |  14 ++--
 snapshots/isabelle/aarch64/Aarch64_extras.thy | 100 ++++++--------------------
 snapshots/isabelle/aarch64/Aarch64_types.thy  |  12 ++--
 3 files changed, 34 insertions(+), 92 deletions(-)

diff --git a/snapshots/isabelle/aarch64/Aarch64.thy b/snapshots/isabelle/aarch64/Aarch64.thy
index c63ed15e..55125942 100644
--- a/snapshots/isabelle/aarch64/Aarch64.thy
+++ b/snapshots/isabelle/aarch64/Aarch64.thy
@@ -5,14 +5,14 @@ theory "Aarch64"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "/tmp/sail/src/lem_interp/Sail2_instr_kinds" 
-	 "/tmp/sail/src/gen_lib/Sail2_values" 
-	 "/tmp/sail/src/gen_lib/Sail2_operators_mwords" 
-	 "/tmp/sail/src/gen_lib/Sail2_prompt_monad" 
-	 "/tmp/sail/src/gen_lib/Sail2_prompt" 
-	 "/tmp/sail/src/gen_lib/Sail2_string" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+	 "Sail2_string" 
 	 "Aarch64_types" 
-	 "/tmp/sail/aarch64/mono/Aarch64_extras" 
+	 "Aarch64_extras" 
 
 begin 
 
diff --git a/snapshots/isabelle/aarch64/Aarch64_extras.thy b/snapshots/isabelle/aarch64/Aarch64_extras.thy
index be3afd72..7555341b 100644
--- a/snapshots/isabelle/aarch64/Aarch64_extras.thy
+++ b/snapshots/isabelle/aarch64/Aarch64_extras.thy
@@ -5,81 +5,25 @@ theory "Aarch64_extras"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "Sail_instr_kinds" 
-	 "Sail_values" 
-	 "Sail_operators_mwords" 
-	 "Prompt_monad" 
-	 "Prompt" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
 
 begin 
 
 (*open import Pervasives_extra*)
-(*open import Sail_instr_kinds*)
-(*open import Sail_values*)
-(*open import Sail_operators_mwords*)
-(*open import Prompt_monad*)
-(*open import Prompt*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
 
 (*type ty512*)
 (*type ty1024*)
 (*type ty2048*)
 
-(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
-definition slice0  :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word "  where 
-     " slice0 v lo len = (
-  subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
-
-
-(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*)
-definition set_slice0  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word "  where 
-     " set_slice0 (out_len::ii) (slice_len::ii) out (n::ii) v = (
-  update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
-
-
-definition get_slice_int_bl  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bool)list "  where 
-     " get_slice_int_bl len n lo = (
-  (* TODO: Is this the intended behaviour? *)
-  (let hi = ((lo + len) -( 1 :: int)) in
-  (let bs = (bools_of_int (hi +( 1 :: int)) n) in
-  subrange_list False bs hi lo)))"
-
-
-(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*)
-definition get_slice_int0  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word "  where 
-     " get_slice_int0 len n lo = ( Word.of_bl (get_slice_int_bl len n lo))"
-
-
-(*val set_slice_int :  forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*)
-definition set_slice_int0  :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int "  where 
-     " set_slice_int0 len n lo v = (
-  (let hi = ((lo + len) -( 1 :: int)) in
-  (let bs = (bools_of_int (hi +( 1 :: int)) n) in
-  (*let len_n = max (hi + 1) (integerFromNat (List.length bs)) in
-  let ext_bs = exts_bools len_n bs in*)
-  signed_of_bools (update_subrange_list False bs hi lo (Word.to_bl v)))))"
-
-
-(*let ext_slice signed v i j =
-  let len = length v in
-  let bits = get_bits false (bits_of v) i j in
-  of_bits (if signed then exts_bits len bits else extz_bits len bits)
-val exts_slice : list bitU -> integer -> integer -> list bitU
-let exts_slice v i j = ext_slice true v i j
-val extz_slice : list bitU -> integer -> integer -> list bitU
-let extz_slice v i j = ext_slice false v i j*)
-
-(*val shr_int : ii -> ii -> ii*)
-function (sequential,domintros)  shr_int0  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " shr_int0 x s = ( if s >( 0 :: int) then shr_int0 (x div( 2 :: int)) (s -( 1 :: int)) else x )" 
-by pat_completeness auto
-
-
-(*val shl_int : integer -> integer -> integer*)
-function (sequential,domintros)  shl_int0  :: " int \<Rightarrow> int \<Rightarrow> int "  where 
-     " shl_int0 i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int0 i (shift -( 1 :: int)) else i )" 
-by pat_completeness auto
-
-
 definition hexchar_to_bool_list  :: " char \<Rightarrow>((bool)list)option "  where 
      " hexchar_to_bool_list c = (
   if c = (CHR ''0'') then      Some ([False,False,False,False])
@@ -120,20 +64,18 @@ definition hexstring_to_bools  :: " string \<Rightarrow>((bool)list)option "  wh
 (*val hex_slice : forall 'rv 'n 'e. Size 'n => string -> integer -> integer -> monad 'rv (mword 'n) 'e*)
 definition hex_slice  :: " string \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('rv,(('n::len)Word.word),'e)monad "  where 
      " hex_slice v len lo = (
-  (case  hexstring_to_bools v of
-      Some bs =>
-       (let hi = ((len + lo) -( 1 :: int)) in
-       (let bs = (ext_list False (len + lo) bs) in
-       return (Word.of_bl (subrange_list False bs hi lo))))
-    | None => Fail (''hex_slice'')
-  ))"
+  maybe_fail (''hex_slice'') (hexstring_to_bools v) \<bind> (\<lambda> bs . 
+   (let hi = ((len + lo) -( 1 :: int)) in
+   (let bs = (ext_list False (len + lo) bs) in
+   return (Word.of_bl (subrange_list False bs hi lo))))))"
 
 
-definition internal_pick  :: " 'a list \<Rightarrow>('c,'a,'b)monad "  where 
-     " internal_pick vs = ( return (List.hd vs))"
+(*val BigEndianReverse : forall 'rv 'n 'e. Size 'n => mword 'n -> monad 'rv (mword 'n) 'e*)
+definition BigEndianReverse  :: "('n::len)Word.word \<Rightarrow>('rv,(('n::len)Word.word),'e)monad "  where 
+     " BigEndianReverse w = ( return (reverse_endianness w))"
 
 
-(* Use constants for undefined values for now *)
+(* Use constants for some undefined values for now *)
 definition undefined_string  :: " unit \<Rightarrow>('b,(string),'a)monad "  where 
      " undefined_string _ = ( return (''''))"
 
@@ -175,8 +117,8 @@ definition undefined_nat  :: " unit \<Rightarrow>('b,(int),'a)monad "  where
   integer -> integer -> mword 'a -> mword 'b -> mword 'c -> monad 'rv unit 'e*)
 definition write_ram  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('c::len)Word.word \<Rightarrow>('rv,(unit),'e)monad "  where 
      " write_ram addrsize size1 hexRAM address value1 = (
-  (write_mem_ea instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \<then>
-  write_mem_val instance_Sail_values_Bitvector_Machine_word_mword_dict value1) \<bind>  (\<lambda>x .  (case  x of _ => return ()  )) )"
+  (write_mem_ea instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \<then>
+  write_mem_val instance_Sail2_values_Bitvector_Machine_word_mword_dict value1) \<bind>  (\<lambda>x .  (case  x of _ => return ()  )) )"
 
 
 (*val read_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c =>
@@ -184,7 +126,7 @@ definition write_ram  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word
 definition read_ram  :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(('c::len)Word.word),'e)monad "  where 
      " read_ram addrsize size1 hexRAM address = (
   (*let _ = prerr_endline (Reading  ^ (stringFromInteger size) ^  bytes from address  ^ (stringFromInteger (unsigned address))) in*)
-  read_mem instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )"
+  read_mem instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )"
 
 
 (*val elf_entry : unit -> integer*)
diff --git a/snapshots/isabelle/aarch64/Aarch64_types.thy b/snapshots/isabelle/aarch64/Aarch64_types.thy
index 33d9cafc..f233a3c0 100644
--- a/snapshots/isabelle/aarch64/Aarch64_types.thy
+++ b/snapshots/isabelle/aarch64/Aarch64_types.thy
@@ -5,12 +5,12 @@ theory "Aarch64_types"
 imports 
  	 Main
 	 "Lem_pervasives_extra" 
-	 "/tmp/sail/src/lem_interp/Sail2_instr_kinds" 
-	 "/tmp/sail/src/gen_lib/Sail2_values" 
-	 "/tmp/sail/src/gen_lib/Sail2_operators_mwords" 
-	 "/tmp/sail/src/gen_lib/Sail2_prompt_monad" 
-	 "/tmp/sail/src/gen_lib/Sail2_prompt" 
-	 "/tmp/sail/src/gen_lib/Sail2_string" 
+	 "Sail2_instr_kinds" 
+	 "Sail2_values" 
+	 "Sail2_operators_mwords" 
+	 "Sail2_prompt_monad" 
+	 "Sail2_prompt" 
+	 "Sail2_string" 
 
 begin 
 
-- 
cgit v1.2.3


From 7a4facfb0fffa81f1854a72bd250ac4d4972a1c1 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Wed, 11 Jul 2018 16:57:19 +0100
Subject: Add FreeBSD boot to mips test suite.

---
 .../cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2 |  Bin 0 -> 12294662 bytes
 ...d-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 |  Bin 0 -> 10633892 bytes
 test/cheri/run_tests.sh                            |   11 +
 test/cheri/sim.dtb                                 |  Bin 0 -> 1449 bytes
 test/cheri/simboot_128m.sailbin                    | 1794 ++++++++++++++++++++
 5 files changed, 1805 insertions(+)
 create mode 100644 test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2
 create mode 100644 test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2
 create mode 100644 test/cheri/sim.dtb
 create mode 100644 test/cheri/simboot_128m.sailbin

diff --git a/test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2 b/test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2
new file mode 100644
index 00000000..61954cd3
Binary files /dev/null and b/test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2 differ
diff --git a/test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 b/test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2
new file mode 100644
index 00000000..33794547
Binary files /dev/null and b/test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 differ
diff --git a/test/cheri/run_tests.sh b/test/cheri/run_tests.sh
index 4e1550f4..848a07e2 100755
--- a/test/cheri/run_tests.sh
+++ b/test/cheri/run_tests.sh
@@ -65,6 +65,17 @@ else
     red "Building MIPS_C specification" "fail"
 fi
 
+printf "Booting FreeBSD-MIPS...\n"
+
+bunzip2 freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2
+time $SAILDIR/mips/mips_c --cyclelimit 85000000 --binary 0x100000,freebsd-beri-sim-mdroot-smoketest_bootonly-kernel --binary 0x7f010000,sim.dtb  --image simboot_128m.sailbin > freebsd_out.txt
+if  grep -q 'Done booting' freebsd_out.txt;
+then
+    green "Booting FreeBSD MIPS" "ok"
+else
+    red "Booting FreeBSD MIPS" "fail"
+fi
+
 printf "Building CHERI 256 specification...\n"
 
 if make -C $SAILDIR/cheri cheri ;
diff --git a/test/cheri/sim.dtb b/test/cheri/sim.dtb
new file mode 100644
index 00000000..2561f997
Binary files /dev/null and b/test/cheri/sim.dtb differ
diff --git a/test/cheri/simboot_128m.sailbin b/test/cheri/simboot_128m.sailbin
new file mode 100644
index 00000000..bd6f5c28
--- /dev/null
+++ b/test/cheri/simboot_128m.sailbin
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-- 
cgit v1.2.3


From ae83a6c62fa0794215f78cd75c8020805f5d9c0a Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Wed, 11 Jul 2018 17:28:36 +0100
Subject: Remove copyright header from generated isabelle for anonymisation.
 Make sure to repeat this if re-generating isabelle before submission.

---
 snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy | 50 -----------------------
 1 file changed, 50 deletions(-)

diff --git a/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy b/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
index 7f9fc60b..d8f3b593 100644
--- a/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
+++ b/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
@@ -8,56 +8,6 @@ imports
 
 begin 
 
-(*========================================================================*)
-(*     Sail                                                               *)
-(*                                                                        *)
-(*  Copyright (c) 2013-2017                                               *)
-(*    Kathyrn Gray                                                        *)
-(*    Shaked Flur                                                         *)
-(*    Stephen Kell                                                        *)
-(*    Gabriel Kerneis                                                     *)
-(*    Robert Norton-Wright                                                *)
-(*    Christopher Pulte                                                   *)
-(*    Peter Sewell                                                        *)
-(*    Alasdair Armstrong                                                  *)
-(*    Brian Campbell                                                      *)
-(*    Thomas Bauereiss                                                    *)
-(*    Anthony Fox                                                         *)
-(*    Jon French                                                          *)
-(*    Dominic Mulligan                                                    *)
-(*    Stephen Kell                                                        *)
-(*    Mark Wassell                                                        *)
-(*                                                                        *)
-(*  All rights reserved.                                                  *)
-(*                                                                        *)
-(*  This software was developed by the University of Cambridge Computer   *)
-(*  Laboratory as part of the Rigorous Engineering of Mainstream Systems  *)
-(*  (REMS) project, funded by EPSRC grant EP/K008528/1.                   *)
-(*                                                                        *)
-(*  Redistribution and use in source and binary forms, with or without    *)
-(*  modification, are permitted provided that the following conditions    *)
-(*  are met:                                                              *)
-(*  1. Redistributions of source code must retain the above copyright     *)
-(*     notice, this list of conditions and the following disclaimer.      *)
-(*  2. Redistributions in binary form must reproduce the above copyright  *)
-(*     notice, this list of conditions and the following disclaimer in    *)
-(*     the documentation and/or other materials provided with the         *)
-(*     distribution.                                                      *)
-(*                                                                        *)
-(*  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''    *)
-(*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     *)
-(*  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A       *)
-(*  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR   *)
-(*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,          *)
-(*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      *)
-(*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF      *)
-(*  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   *)
-(*  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,    *)
-(*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    *)
-(*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    *)
-(*  SUCH DAMAGE.                                                          *)
-(*========================================================================*)
-
 (*open import Pervasives_extra*)
 
 
-- 
cgit v1.2.3


From 2a89faec667fdf24b93360d3da5f14eab161983b Mon Sep 17 00:00:00 2001
From: Jon French
Date: Wed, 11 Jul 2018 18:13:15 +0100
Subject: RISC-V model fixes for RMEM

---
 riscv/prelude.sail                |  5 ++---
 riscv/riscv.sail                  | 18 +++++++++++-------
 riscv/riscv_analysis.sail         |  4 ++--
 riscv/riscv_extras.lem            |  5 ++---
 riscv/riscv_extras_sequential.lem |  5 ++---
 riscv/riscv_mem.sail              | 24 ++++++++++++------------
 riscv/riscv_platform.sail         | 12 ++++++------
 src/sail_lib.ml                   |  2 +-
 8 files changed, 38 insertions(+), 37 deletions(-)

diff --git a/riscv/prelude.sail b/riscv/prelude.sail
index d99581a7..6eeda601 100644
--- a/riscv/prelude.sail
+++ b/riscv/prelude.sail
@@ -355,12 +355,11 @@ overload min = {min_nat, min_int}
 overload max = {max_nat, max_int}
 
 val __WriteRAM = "write_ram" : forall 'n 'm.
-  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmv}
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> bool effect {wmv}
 
 val __RISCV_write : forall 'n. (bits(64), atom('n), bits(8 * 'n)) -> bool effect {wmv}
 function __RISCV_write (addr, width, data) = {
-  __WriteRAM(64, width, 0x0000_0000_0000_0000, addr, data);
-  true
+  __WriteRAM(64, width, 0x0000_0000_0000_0000, addr, data)
 }
 
 val __TraceMemoryWrite : forall 'n 'm.
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 44ba8e0f..27ec8a2f 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -348,14 +348,15 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) =
           MemException(e) => { handle_mem_exception(addr, e); false },
           MemValue(_) => {
             let rs2_val = X(rs2) in
-            let res : MemoryOpResult(unit) = match width {
+            let res : MemoryOpResult(bool) = match width {
               BYTE   => mem_write_value(addr, 1, rs2_val[7..0],  aq, rl, false),
               HALF   => mem_write_value(addr, 2, rs2_val[15..0], aq, rl, false),
               WORD   => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, false),
               DOUBLE => mem_write_value(addr, 8, rs2_val,        aq, rl, false)
             } in
             match (res) {
-              MemValue(_)     => true,
+              MemValue(true)     => true,
+              MemValue(false)    => internal_error("store got false from mem_write_value"),
               MemException(e) => { handle_mem_exception(addr, e); false }
             }
           }
@@ -630,7 +631,8 @@ union clause ast = FENCEI : unit
 
 mapping clause encdec = FENCEI() <-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111
 
-function clause execute FENCEI() = { MEM_fence_i(); true }
+/* fence.i is a nop for the memory model */
+function clause execute FENCEI() = { /* MEM_fence_i(); */ true }
 
 
 mapping clause assembly = FENCEI() <-> "fence.i"
@@ -846,13 +848,14 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
             MemException(e)  => { handle_mem_exception(addr, e); false },
             MemValue(_) => {
               rs2_val = X(rs2);
-              let res : MemoryOpResult(unit) = match width {
+              let res : MemoryOpResult(bool) = match width {
                 WORD   => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, true),
                 DOUBLE => mem_write_value(addr, 8, rs2_val,        aq, rl, true),
                 _      => internal_error("STORECON expected word or double")
               };
               match (res) {
-                MemValue(_)     => { X(rd) = EXTZ(0b0); cancel_reservation(); true },
+                MemValue(true)     => { X(rd) = EXTZ(0b0); cancel_reservation(); true },
+                MemValue(false)    => { X(rd) = EXTZ(0b1); cancel_reservation(); true },
                 MemException(e) => { handle_mem_exception(addr, e); false }
               }
             }
@@ -921,13 +924,14 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
                   AMOMAXU => vector64(max(unsigned(rs2_val), unsigned(loaded)))
                 };
 
-              let wval : MemoryOpResult(unit) = match width {
+              let wval : MemoryOpResult(bool) = match width {
                 WORD   => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true),
                 DOUBLE => mem_write_value(addr, 8, result,        aq & rl, rl, true),
                 _      => internal_error("AMO expected WORD or DOUBLE")
               };
               match (wval) {
-                MemValue(_) => { X(rd) = loaded; true },
+                MemValue(true) => { X(rd) = loaded; true },
+                MemValue(false) => { internal_error("AMO got false from mem_write_value") },
                 MemException(e) => { handle_mem_exception(addr, e); false }
               }
             }
diff --git a/riscv/riscv_analysis.sail b/riscv/riscv_analysis.sail
index 84934a25..e374933a 100644
--- a/riscv/riscv_analysis.sail
+++ b/riscv/riscv_analysis.sail
@@ -2,7 +2,7 @@ $include <regfp.sail>
 
 /* in reverse order because inc vectors don't seem to work (bug) */
 let GPRstr : vector(32, dec, string) = [ "x31", "x30", "x29", "x28", "x27", "x26", "x25", "x24", "x23", "x22", "x21",
-  "x20", "x19", "x18", "x17", "x16", "x15", "x14", "x13", "x12", "x21",
+  "x20", "x19", "x18", "x17", "x16", "x15", "x14", "x13", "x12", "x11",
   "x10", "x9", "x8", "x7", "x6", "x5", "x4", "x3", "x2", "x1", "x0"
   ]
 
@@ -133,7 +133,7 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
                };
       },
      FENCEI() => {
-              ik = IK_barrier (Barrier_RISCV_i);
+              ik = IK_simple (); // for RMEM, should morally be Barrier_RISCV_i
      },
      LOADRES(aq, rl, rs1, width, rd) => {
             if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 60468a4e..a6fa1298 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -49,10 +49,9 @@ let MEMr_reserved_acquire addrsize size hexRAM addr        = read_mem Read_RISCV
 let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size
 
 val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
-  integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e
+  integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
 let write_ram addrsize size hexRAM address value =
-  write_mem_val value >>= fun _ ->
-  return ()
+  write_mem_val value
 
 val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index 60468a4e..a6fa1298 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -49,10 +49,9 @@ let MEMr_reserved_acquire addrsize size hexRAM addr        = read_mem Read_RISCV
 let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size
 
 val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
-  integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e
+  integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
 let write_ram addrsize size hexRAM address value =
-  write_mem_val value >>= fun _ ->
-  return ()
+  write_mem_val value
 
 val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
   integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail
index 2322a0ad..21a40af4 100644
--- a/riscv/riscv_mem.sail
+++ b/riscv/riscv_mem.sail
@@ -85,15 +85,15 @@ function mem_write_ea (addr, width, aq, rl, con) = {
 }
 
 // only used for actual memory regions, to avoid MMIO effects
-function phys_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n. MemoryOpResult(unit) = {
+function phys_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n. MemoryOpResult(bool) = {
   print("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
-  if   __RISCV_write(addr, width, data)
-  then MemValue(())
-  else MemException(E_SAMO_Access_Fault)
+//  if   
+  MemValue(__RISCV_write(addr, width, data))
+//  else MemException(E_SAMO_Access_Fault)
 }
 
 // dispatches to MMIO regions or physical memory regions depending on physical memory map
-function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n, 'n > 0. MemoryOpResult(unit) =
+function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n, 'n > 0. MemoryOpResult(bool) =
   if   within_mmio_writable(addr, width)
   then mmio_write(addr, width, data)
   else if within_phys_mem(addr, width)
@@ -102,12 +102,12 @@ function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)
 
 /* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */
 
-val MEMval                            : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
-val MEMval_release                    : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
-val MEMval_strong_release             : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
-val MEMval_conditional                : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
-val MEMval_conditional_release        : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
-val MEMval_conditional_strong_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wmv, rreg, wreg}
+val MEMval                            : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg}
+val MEMval_release                    : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg}
+val MEMval_strong_release             : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg}
+val MEMval_conditional                : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg}
+val MEMval_conditional_release        : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg}
+val MEMval_conditional_strong_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg}
 
 function MEMval                            (addr, width, data) = checked_mem_write(addr, width, data)
 function MEMval_release                    (addr, width, data) = checked_mem_write(addr, width, data)
@@ -117,7 +117,7 @@ function MEMval_conditional_release        (addr, width, data) = checked_mem_wri
 function MEMval_conditional_strong_release (addr, width, data) = checked_mem_write(addr, width, data)
 
 /* NOTE: The wreg effect is due to MMIO, the rreg is due to checking mtime. */
-val mem_write_value : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(unit) effect {wmv, rreg, wreg, escape}
+val mem_write_value : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool) effect {wmv, rreg, wreg, escape}
 
 function mem_write_value (addr, width, value, aq, rl, con) = {
   if (rl | con) & (~ (is_aligned_addr(addr, width)))
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail
index 6b903e70..558ca2db 100644
--- a/riscv/riscv_platform.sail
+++ b/riscv/riscv_platform.sail
@@ -118,19 +118,19 @@ function clint_dispatch() -> unit = {
 }
 
 /* The rreg effect is due to checking mtime. */
-val clint_store: forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {rreg,wreg}
+val clint_store: forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {rreg,wreg}
 function clint_store(addr, width, data) = {
   let addr = addr - plat_clint_base ();
   if addr == MSIP_BASE & ('n == 8 | 'n == 4) then {
     print("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mip.MSI <- " ^ BitStr(data[0]) ^ ")");
     mip->MSI() = data[0] == 0b1;
     clint_dispatch();
-    MemValue(())
+    MemValue(true)
   } else if addr == MTIMECMP_BASE & 'n == 8 then {
     print("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
     mtimecmp = zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */
     clint_dispatch();
-    MemValue(())
+    MemValue(true)
   } else {
     print("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (<unmapped>)");
     MemException(E_SAMO_Access_Fault)
@@ -177,7 +177,7 @@ function htif_load(addr, width) = {
 }
 
 /* The wreg effect is an artifact of using 'register' to implement device state. */
-val htif_store: forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(unit) effect {wreg}
+val htif_store: forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wreg}
 function htif_store(addr, width, data) = {
   print("htif[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
   /* Store the written value so that we can ack it later. */
@@ -205,7 +205,7 @@ function htif_store(addr, width, data) = {
     },
     d => print("htif-???? cmd: " ^ BitStr(data))
   };
-  MemValue(())
+  MemValue(true)
 }
 
 val htif_tick : unit -> unit effect {rreg, wreg}
@@ -229,7 +229,7 @@ function mmio_read(addr : xlenbits, width : atom('n)) -> forall 'n. MemoryOpResu
   then htif_load(addr, width)
   else MemException(E_Load_Access_Fault)
 
-function mmio_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n, 'n > 0. MemoryOpResult(unit) =
+function mmio_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n, 'n > 0. MemoryOpResult(bool) =
   if   within_clint(addr, width)
   then clint_store(addr, width, data)
   else if within_htif_writable(addr, width) & 'n <= 8
diff --git a/src/sail_lib.ml b/src/sail_lib.ml
index 63260c17..16b1d3cc 100644
--- a/src/sail_lib.ml
+++ b/src/sail_lib.ml
@@ -457,7 +457,7 @@ let write_ram' (data_size, addr, data) =
   end
 
 let write_ram (addr_size, data_size, hex_ram, addr, data) =
-  write_ram' (data_size, uint addr, data)
+  write_ram' (data_size, uint addr, data); true
 
 let wram addr byte =
   let bytes = Bytes.make 1 (char_of_int byte) in
-- 
cgit v1.2.3


From e3e2f7137be43771aace42694c8d5112f6849039 Mon Sep 17 00:00:00 2001
From: Alasdair
Date: Thu, 12 Jul 2018 00:37:54 +0100
Subject: Fixes for ARM Sail tests, and get_time_ns for interpreter

---
 src/value.ml          | 1 +
 test/arm/run_tests.sh | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/value.ml b/src/value.ml
index 41b52720..1d2346af 100644
--- a/src/value.ml
+++ b/src/value.ml
@@ -561,6 +561,7 @@ let primops =
       ("write_ram", value_write_ram);
       ("trace_memory_read", fun _ -> V_unit);
       ("trace_memory_write", fun _ -> V_unit);
+      ("get_time_ns", fun _ -> V_int (Sail_lib.get_time_ns()));
       ("load_raw", value_load_raw);
       ("to_real", value_to_real);
       ("eq_real", value_eq_real);
diff --git a/test/arm/run_tests.sh b/test/arm/run_tests.sh
index f758d634..30f955b0 100755
--- a/test/arm/run_tests.sh
+++ b/test/arm/run_tests.sh
@@ -51,7 +51,7 @@ cd $SAILDIR/aarch64
 
 printf "Compiling specification...\n"
 
-if $SAILDIR/sail -no_lexp_bounds_check -o aarch64_test -ocaml prelude.sail no_vector/spec.sail decode_start.sail no_vector/decode.sail decode_end.sail main.sail 1> /dev/null 2> /dev/null;
+if $SAILDIR/sail -no_lexp_bounds_check -o aarch64_test -ocaml no_vector.sail 1> /dev/null 2> /dev/null;
 then
     green "compiled no_vector specification" "ok";
     mv aarch64_test $DIR/;
@@ -83,7 +83,7 @@ printf "\nLoading specification into interpreter...\n"
 
 cd $SAILDIR/aarch64
 
-if $SAILDIR/sail -no_lexp_bounds_check -is $DIR/test.isail prelude.sail no_vector/spec.sail decode_start.sail no_vector/decode.sail decode_end.sail main.sail 1> /dev/null 2> /dev/null;
+if $SAILDIR/sail -no_lexp_bounds_check -is $DIR/test.isail no_vector.sail 1> /dev/null 2> /dev/null;
 then
     green "loaded no_vector specification" "ok";
 
-- 
cgit v1.2.3


From 374de34cbb22da437f856ac39154aabe72a651bb Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Wed, 11 Jul 2018 15:34:37 -0700
Subject: Update the exception code for riscv LR after clarification on
 isa-dev.

---
 riscv/riscv.sail | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 27ec8a2f..ca30f4b4 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -790,8 +790,11 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) =
       WORD   => vaddr[1..0] == 0b00,
       DOUBLE => vaddr[2..0] == 0b000
     } in
+    /* "LR faults like a normal load, even though it's in the AMO major opcode space."
+       - Andrew Waterman, isa-dev, 10 Jul 2018.
+     */
   if (~ (aligned))
-  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false }
+  then { handle_mem_exception(vaddr, E_Load_Addr_Align); false }
   else match translateAddr(vaddr, Read, Data) {
          TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
          TR_Address(addr) =>
-- 
cgit v1.2.3


From 8d95266216f3249e40c01977065600a4363ea42e Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Wed, 11 Jul 2018 21:04:34 -0700
Subject: Add fixme note about riscv jalr.

---
 riscv/riscv.sail | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index ca30f4b4..548091e2 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -84,6 +84,14 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
     /* write rd before anything else to prevent unintended strength */
     X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
     let newPC : xlenbits = X(rs1) + EXTS(imm);
+/*  RMEM FIXME: For the sequential model, the above definition doesn't work directly
+    if rs1 = rd.  We would effectively have to keep a regfile for reads and another for
+    writes, and swap on instruction fetch.  This could perhaps be optimized in
+    some manner, but for now, we just reorder the previous two lines to improve simulator
+    performance in the sequential model, as below:
+    let newPC : xlenbits = X(rs1) + EXTS(imm);
+    X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR
+*/
     nextPC = newPC[63..1] @ 0b0;
     true
 }
-- 
cgit v1.2.3


From 0b7273789c94cc1de640158d4bb3a6ac4e0e7a25 Mon Sep 17 00:00:00 2001
From: Shaked Flur
Date: Thu, 12 Jul 2018 08:44:42 +0100
Subject: Fixed a nested comment issue

---
 riscv/riscv.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 548091e2..497c5e7a 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -90,7 +90,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
     some manner, but for now, we just reorder the previous two lines to improve simulator
     performance in the sequential model, as below:
     let newPC : xlenbits = X(rs1) + EXTS(imm);
-    X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR
+    X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
 */
     nextPC = newPC[63..1] @ 0b0;
     true
-- 
cgit v1.2.3


From d4c2a2d51e16cf483c67dfc4d589ded9a2e29417 Mon Sep 17 00:00:00 2001
From: Shaked Flur
Date: Thu, 12 Jul 2018 09:19:01 +0100
Subject: Minor fix to support OCaml 4.02.3

---
 src/gen_lib/sail2_string.lem | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gen_lib/sail2_string.lem b/src/gen_lib/sail2_string.lem
index d0e40ad4..ba3a2d51 100644
--- a/src/gen_lib/sail2_string.lem
+++ b/src/gen_lib/sail2_string.lem
@@ -31,7 +31,7 @@ let string_append = stringAppend
 
 val maybeIntegerOfString : string -> maybe integer
 let maybeIntegerOfString _ = Nothing (* TODO FIXME *)
-declare ocaml target_rep function maybeIntegerOfString = `(fun s -> match int_of_string_opt s with None -> None | Some i -> Some (Nat_big_num.of_int i))`
+declare ocaml target_rep function maybeIntegerOfString = `(fun s -> match int_of_string s with i -> Some (Nat_big_num.of_int i) | exception Failure _ -> None )`
 
 (***********************************************
  * end stuff that should be in Lem Num_extra   *
-- 
cgit v1.2.3


From f81027f53801b8619afe71cb82dbbe4e4651ff13 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Thu, 12 Jul 2018 12:30:42 +0100
Subject: Further anonymise manual

---
 doc/introduction.tex | 8 ++++----
 doc/manual.tex       | 2 ++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/doc/introduction.tex b/doc/introduction.tex
index 9e268de5..1bca5e12 100644
--- a/doc/introduction.tex
+++ b/doc/introduction.tex
@@ -27,11 +27,11 @@ rigorous models for the allowed architectural envelope of concurrent
 code, for x86, IBM Power, \riscv, and ARM, that have been reasonably
 well validated by experimental testing and by discussion with the
 vendors and
-others~\cite{x86popl,tphols09,cacm,CAV2010,Alglave:2011:LRT:1987389.1987395,pldi105,pldi2012,micro2015,FGP16,mixed17}.
+others\anonymiseomit{~\cite{x86popl,tphols09,cacm,CAV2010,Alglave:2011:LRT:1987389.1987395,pldi105,pldi2012,micro2015,FGP16,mixed17}}.
 In the course of this, we have identified a number of subtle issues
 relating to the interface between the intra-instruction semantics and
 the inter-instruction concurrency
-semantics~\cite{pldi105,pldi2012,micro2015,FGP16,mixed17}. For
+semantics\anonymiseomit{~\cite{pldi105,pldi2012,micro2015,FGP16,mixed17}}. For
 example, the concurrency models, rather than treating each instruction
 execution as an atomic unit, require exposed register and memory
 events, knowledge of the potential register and memory footprints of
@@ -77,7 +77,7 @@ and generate:
 \item An internal representation of the fully type-annotated
   definition (a deep embedding of the definition) in a form that can
   be executed by the Sail interpreter.  These are both expressed in
-  Lem~\cite{Lem-icfp2014,Lemcode}, a language of type, function, and
+  Lem\anonymiseomit{~\cite{Lem-icfp2014,Lemcode}}, a language of type, function, and
   relation definitions that can be compiled into OCaml and various
   theorem provers. The Sail interpreter can also be used to analyse
   instruction definitions (or partially executed instructions) to
@@ -118,7 +118,7 @@ specification document~\cite{armarmv8,FGP16}, principally by \anonymise{Flur}.
 
 The Power model is based on an automatic extraction of pseudocode and
 decoding data from an XML export of the Framemaker document source of
-the IBM Power manual~\cite{Power2.06,micro2015}, with manual patching
+the IBM Power manual\anonymiseomit{~\cite{Power2.06,micro2015}}, with manual patching
 as necessary, principally by \anonymise{Kerneis and Gray}.
 
 The ARMv8 (ASL) model is based on an automatic translation of ARM's
diff --git a/doc/manual.tex b/doc/manual.tex
index d28719a4..d731ecd3 100644
--- a/doc/manual.tex
+++ b/doc/manual.tex
@@ -67,11 +67,13 @@
 \ifdefined\ANON
 \author{Anonymous}
 \newcommand\anonymise[1]{\emph{redacted}}
+\newcommand\anonymiseomit[1]{}
 \else
 \author{Alasdair Armstrong \and Thomas Bauereiss \and Brian Campbell \and
   Shaked Flur \and Kathryn E. Gray \and Robert Norton-Wright \and Christopher Pulte \and
   Peter Sewell}
 \newcommand\anonymise[1]{#1}
+\newcommand\anonymiseomit[1]{#1}
 \fi
 
 \maketitle
-- 
cgit v1.2.3


From 870f918d3f6e3e9ed8c8367ce19d1991a8bf40b7 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Wed, 11 Jul 2018 20:32:22 +0100
Subject: Fix bug for large integers in OCaml compilation

---
 src/c_backend.ml     |  3 ++-
 src/ocaml_backend.ml | 15 +++++++++++----
 src/rewrites.ml      |  1 +
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/c_backend.ml b/src/c_backend.ml
index e4bbd393..cb732e2d 100644
--- a/src/c_backend.ml
+++ b/src/c_backend.ml
@@ -2655,7 +2655,8 @@ let instrument_tracing ctx =
   let module StringSet = Set.Make(String) in
   let traceable = StringSet.of_list ["mach_bits"; "sail_string"; "sail_bits"; "sail_int"; "unit"; "bool"] in
   let rec instrument = function
-    | (I_aux (I_funcall (clexp, _, id, args, ctyp), _) as instr) :: instrs ->
+    | (I_aux (I_funcall (clexp, _, id, args, ctyp), _) as instr) :: instrs when not (Env.is_extern id ctx.tc_env "c") ->
+
        let trace_start =
          iraw (Printf.sprintf "trace_start(\"%s\");" (String.escaped (string_of_id id)))
        in
diff --git a/src/ocaml_backend.ml b/src/ocaml_backend.ml
index 5ffb1647..236c4222 100644
--- a/src/ocaml_backend.ml
+++ b/src/ocaml_backend.ml
@@ -167,10 +167,13 @@ let ocaml_lit (L_aux (lit_aux, _)) =
   | L_one -> string "B1"
   | L_true -> string "true"
   | L_false -> string "false"
-  | L_num n -> if Big_int.equal n Big_int.zero
-               then string "Big_int.zero"
-               else parens (string "Big_int.of_int" ^^ space
-                            ^^ string "(" ^^ string (Big_int.to_string n) ^^ string ")")
+  | L_num n ->
+     if Big_int.equal n Big_int.zero then
+       string "Big_int.zero"
+     else if Big_int.less_equal (Big_int.of_int min_int) n && Big_int.less_equal n (Big_int.of_int max_int) then
+       parens (string "Big_int.of_int" ^^ space ^^ parens (string (Big_int.to_string n)))
+     else
+       parens (string "Big_int.of_string" ^^ space ^^ dquotes (string (Big_int.to_string n)))
   | L_undef -> failwith "undefined should have been re-written prior to ocaml backend"
   | L_string str -> string_lit str
   | L_real str -> parens (string "real_of_string" ^^ space ^^ dquotes (string (String.escaped str)))
@@ -389,6 +392,10 @@ let ocaml_dec_spec ctx (DEC_aux (reg, _)) =
      separate space [string "let"; zencode ctx id; colon;
                      parens (ocaml_typ ctx typ); string "ref"; equals;
                      string "ref"; parens (ocaml_exp ctx (initial_value_for id ctx.register_inits))]
+  | DEC_config (id, typ, exp) ->
+     separate space [string "let"; zencode ctx id; colon;
+                     parens (ocaml_typ ctx typ); string "ref"; equals;
+                     string "ref"; parens (ocaml_exp ctx exp)]
   | _ -> failwith "Unsupported register declaration"
 
 let first_function = ref true
diff --git a/src/rewrites.ml b/src/rewrites.ml
index fad1f4d2..8fe30d6b 100644
--- a/src/rewrites.ml
+++ b/src/rewrites.ml
@@ -2304,6 +2304,7 @@ let rewrite_type_def_typs rw_typ rw_typquant rw_typschm (TD_aux (td, annot)) =
 let rewrite_dec_spec_typs rw_typ (DEC_aux (ds, annot)) =
   match ds with
   | DEC_reg (typ, id) -> DEC_aux (DEC_reg (rw_typ typ, id), annot)
+  | DEC_config (id, typ, exp) -> DEC_aux (DEC_config (id, rw_typ typ, exp), annot)
   | _ -> assert false
 
 (* Remove overload definitions and cast val specs from the
-- 
cgit v1.2.3


From fb33182ec89cfc4307ce5f04aa5e46d1c3c2716d Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 12 Jul 2018 12:35:48 +0100
Subject: Coq: more accurate autocast insertion

---
 src/pretty_print_coq.ml | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index efcf3851..e57238f6 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -991,10 +991,21 @@ let doc_exp_lem, doc_let_lem =
               | _, _ -> arg_pp
             in
             let epp = hang 2 (flow (break 1) (call :: List.map2 doc_arg args arg_typs)) in
-            (* Unpack existential result *)
-            let inst = instantiation_of full_exp in
-            let inst = KBindings.fold (fun k u m -> KBindings.add (orig_kid k) u m) inst KBindings.empty in
-            let ret_typ_inst = subst_unifiers inst ret_typ in
+            (* Decide whether to unpack an existential result, pack one, or cast.
+               To do this we compare the expected type stored in the checked expression
+               with the inferred type. *)
+            let ret_typ_inst =
+              match infer_exp (env_of full_exp) (strip_exp full_exp) with
+              | typed_exp -> typ_of typed_exp
+              (* Not all function applications can be inferred, so try falling back to the
+                 type inferred when we know the target type.
+                 TODO: there are probably some edge cases where this won't pick up a need
+                 to cast. *)
+              | exception _ ->
+                 let inst = instantiation_of full_exp in
+                 let inst = KBindings.fold (fun k u m -> KBindings.add (orig_kid k) u m) inst KBindings.empty in
+                 subst_unifiers inst ret_typ
+            in
             let unpack,build_ex,autocast =
               let ann_typ = Env.expand_synonyms env (typ_of_annot (l,annot)) in
               let ann_typ = expand_range_type ann_typ in
-- 
cgit v1.2.3


From 8195ac7e4d851e9901bfaae92997ea51914c09b2 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Thu, 12 Jul 2018 12:38:32 +0100
Subject: Temporarily remove some paragraphs from the manual for anonymisation

---
 doc/introduction.tex | 65 ++++++++++++++++++++++++++--------------------------
 1 file changed, 33 insertions(+), 32 deletions(-)

diff --git a/doc/introduction.tex b/doc/introduction.tex
index 1bca5e12..1f9d9dba 100644
--- a/doc/introduction.tex
+++ b/doc/introduction.tex
@@ -21,27 +21,27 @@ pseudocode, which has recently become machine-processed~\cite{Reid16}.
 For MIPS~\cite{MIPS64-II,MIPS64-III} there is also reasonably detailed
 pseudocode.
 
-The behaviour of concurrent code is often described less well.  In a
-line of research from 2007--2018 we have developed mathematically
-rigorous models for the allowed architectural envelope of concurrent
-code, for x86, IBM Power, \riscv, and ARM, that have been reasonably
-well validated by experimental testing and by discussion with the
-vendors and
-others\anonymiseomit{~\cite{x86popl,tphols09,cacm,CAV2010,Alglave:2011:LRT:1987389.1987395,pldi105,pldi2012,micro2015,FGP16,mixed17}}.
-In the course of this, we have identified a number of subtle issues
-relating to the interface between the intra-instruction semantics and
-the inter-instruction concurrency
-semantics\anonymiseomit{~\cite{pldi105,pldi2012,micro2015,FGP16,mixed17}}. For
-example, the concurrency models, rather than treating each instruction
-execution as an atomic unit, require exposed register and memory
-events, knowledge of the potential register and memory footprints of
-instructions, and knowledge of changes to those during execution.  Our
-early work in this area had hand-coded instruction semantics for quite
-small fragments of the instruction sets, just enough for concurrency
-litmus tests and expressed in various ad hoc ways. As our models have
-matured, we have switched to modelling the intra-instruction semantics
-more completely and in a style closer to the vendor-documentation
-pseudocode, and Sail was developed for this.
+%% The behaviour of concurrent code is often described less well.  In a
+%% line of research from 2007--2018 we have developed mathematically
+%% rigorous models for the allowed architectural envelope of concurrent
+%% code, for x86, IBM Power, \riscv, and ARM, that have been reasonably
+%% well validated by experimental testing and by discussion with the
+%% vendors and
+%% others\anonymiseomit{~\cite{x86popl,tphols09,cacm,CAV2010,Alglave:2011:LRT:1987389.1987395,pldi105,pldi2012,micro2015,FGP16,mixed17}}.
+%% In the course of this, we have identified a number of subtle issues
+%% relating to the interface between the intra-instruction semantics and
+%% the inter-instruction concurrency
+%% semantics\anonymiseomit{~\cite{pldi105,pldi2012,micro2015,FGP16,mixed17}}. For
+%% example, the concurrency models, rather than treating each instruction
+%% execution as an atomic unit, require exposed register and memory
+%% events, knowledge of the potential register and memory footprints of
+%% instructions, and knowledge of changes to those during execution.  Our
+%% early work in this area had hand-coded instruction semantics for quite
+%% small fragments of the instruction sets, just enough for concurrency
+%% litmus tests and expressed in various ad hoc ways. As our models have
+%% matured, we have switched to modelling the intra-instruction semantics
+%% more completely and in a style closer to the vendor-documentation
+%% pseudocode, and Sail was developed for this.
 
 
 Sail is intended:
@@ -101,25 +101,26 @@ binary descriptions, although this is something we plan to add.
 Sail has been used to develop models of parts of several architectures:
 \begin{center}
 \begin{tabular}{|l|l|} \hline
-ARMv8 (hand) & hand-written \\ \hline
+% ARMv8 (hand) & hand-written \\ \hline
 ARMv8 (ASL)  & generated from ARM's v8.3 public ASL spec \\ \hline
-IBM Power    & extracted/patched from IBM Framemaker XML \\ \hline
+% IBM Power    & extracted/patched from IBM Framemaker XML \\ \hline
 MIPS         & hand-written \\ \hline
 CHERI        & hand-written \\ \hline
 \riscv       & hand-written \\ \hline
 \end{tabular}
 \end{center}
-The ARMv8 (hand) and IBM Power models cover all user-mode instructions
-except vector, float, and load-multiple instructions, without
-exceptions; for ARMv8 this is for the A64 fragment.
+%% The ARMv8 (hand) and IBM Power models cover all user-mode instructions
+%% except vector, float, and load-multiple instructions, without
+%% exceptions; for ARMv8 this is for the A64 fragment.
 
-The ARMv8 (hand) model is hand-written based on the ARMv8-A
-specification document~\cite{armarmv8,FGP16}, principally by \anonymise{Flur}.
+%% The ARMv8 (hand) model is hand-written based on the ARMv8-A
+%% specification document\anonymiseomit{~\cite{armarmv8,FGP16}},
+%% principally by \anonymise{Flur}.
 
-The Power model is based on an automatic extraction of pseudocode and
-decoding data from an XML export of the Framemaker document source of
-the IBM Power manual\anonymiseomit{~\cite{Power2.06,micro2015}}, with manual patching
-as necessary, principally by \anonymise{Kerneis and Gray}.
+%% The Power model is based on an automatic extraction of pseudocode and
+%% decoding data from an XML export of the Framemaker document source of
+%% the IBM Power manual\anonymiseomit{~\cite{Power2.06,micro2015}}, with manual patching
+%% as necessary, principally by \anonymise{Kerneis and Gray}.
 
 The ARMv8 (ASL) model is based on an automatic translation of ARM's
 machine-readable public v8.3 ASL specification\footnote{ARM v8-A
-- 
cgit v1.2.3


From d3c75495194f810a89d10fede3ea377074af6f53 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 12 Jul 2018 13:20:41 +0100
Subject: Coq: remove unnecessary constraint on foreach loops

---
 lib/coq/Sail2_prompt.v | 8 ++++----
 lib/coq/Sail2_values.v | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/lib/coq/Sail2_prompt.v b/lib/coq/Sail2_prompt.v
index 6448e81b..c98e2926 100644
--- a/lib/coq/Sail2_prompt.v
+++ b/lib/coq/Sail2_prompt.v
@@ -30,7 +30,7 @@ match l with
   foreachM xs vars body
 end.
 
-Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
   if sumbool_of_bool (from + off <=? to) then
     match n with
     | O => returnm vars
@@ -38,7 +38,7 @@ Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)}
     end
   else returnm vars.
 
-Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
   if sumbool_of_bool (to <=? from + off) then
     match n with
     | O => returnm vars
@@ -46,9 +46,9 @@ Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from
     end
   else returnm vars.
 
-Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (0 < step)} :=
     foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
-Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (0 < step)} :=
     foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
 
 (*declare {isabelle} termination_argument foreachM = automatic*)
diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index d18b17bb..13352f4b 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -1330,7 +1330,7 @@ Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Var
 Definition foreach_Z {Vars} from to step vars body :=
   foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body.
 
-Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars :=
+Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars :=
   if sumbool_of_bool (from + off <=? to) then
     match n with
     | O => vars
@@ -1338,7 +1338,7 @@ Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{Ari
     end
   else vars.
 
-Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars :=
+Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars :=
   if sumbool_of_bool (to <=? from + off) then
     match n with
     | O => vars
@@ -1346,9 +1346,9 @@ Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{A
     end
   else vars.
 
-Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (0 < step)} :=
     foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
-Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (0 < step)} :=
     foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
 
 (*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
-- 
cgit v1.2.3


From 4f939658df5f45026d42491b8bf78aaa44f76e7b Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 12 Jul 2018 13:41:07 +0100
Subject: Coq: tuple matching in loops

---
 src/pretty_print_coq.ml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index e57238f6..6cb97d5b 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -879,7 +879,7 @@ let doc_exp_lem, doc_let_lem =
                      when not (IdSet.mem (mk_id "varstup") used_vars_body)->
                       separate space [string "fun"; doc_id loopvar; string "_"; string "varstup"; bigarrow]
                       ^^ break 1 ^^
-                      separate space [string "let"; expY vartuple; string ":= varstup in"]
+                      separate space [string "let"; squote ^^ expY vartuple; string ":= varstup in"]
                    | E_aux (E_lit (L_aux (L_unit, _)), _)
                      when not (IdSet.mem (mk_id "unit_var") used_vars_body) ->
                       separate space [string "fun"; doc_id loopvar; string "_"; string "unit_var"; bigarrow]
@@ -918,7 +918,7 @@ let doc_exp_lem, doc_let_lem =
                    | E_aux (E_tuple _, _)
                      when not (IdSet.mem (mk_id "varstup") used_vars_body)->
                       separate space [string "fun varstup"; bigarrow] ^^ break 1 ^^
-                      separate space [string "let"; expY varstuple; string ":= varstup in"]
+                      separate space [string "let"; squote ^^ expY varstuple; string ":= varstup in"]
                    | E_aux (E_lit (L_aux (L_unit, _)), _)
                      when not (IdSet.mem (mk_id "unit_var") used_vars_body) ->
                       separate space [string "fun unit_var"; bigarrow]
-- 
cgit v1.2.3


From f3d480d3fee8c28c1dd1975117149ddcd47d989f Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 12 Jul 2018 14:45:34 +0100
Subject: Coq: more autocast insertion

---
 src/pretty_print_coq.ml | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 6cb97d5b..8c345cd6 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -711,12 +711,11 @@ let rec nexp_const_eval (Nexp_aux (n,l) as nexp) =
 
 (* Decide whether two nexps used in a vector size are similar; if not
    a cast will be inserted *)
-let similar_nexps n1 n2 =
+let similar_nexps env n1 n2 =
   let rec same_nexp_shape (Nexp_aux (n1,_)) (Nexp_aux (n2,_)) =
     match n1, n2 with
-    | Nexp_id _, Nexp_id _
-    | Nexp_var _, Nexp_var _
-      -> true
+    | Nexp_id _, Nexp_id _ -> true
+    | Nexp_var k1, Nexp_var k2 -> prove env (nc_eq (nvar k1) (nvar k2))
     | Nexp_constant c1, Nexp_constant c2 -> Nat_big_num.equal c1 c2
     | Nexp_app (f1,args1), Nexp_app (f2,args2) ->
        Id.compare f1 f2 == 0 && List.for_all2 same_nexp_shape args1 args2
@@ -995,7 +994,7 @@ let doc_exp_lem, doc_let_lem =
                To do this we compare the expected type stored in the checked expression
                with the inferred type. *)
             let ret_typ_inst =
-              match infer_exp (env_of full_exp) (strip_exp full_exp) with
+              match infer_exp env (strip_exp full_exp) with
               | typed_exp -> typ_of typed_exp
               (* Not all function applications can be inferred, so try falling back to the
                  type inferred when we know the target type.
@@ -1026,7 +1025,7 @@ let doc_exp_lem, doc_let_lem =
                 match in_typ, out_typ with
                 | Typ_aux (Typ_app (_,[Typ_arg_aux (Typ_arg_nexp n1,_);_;_]),_),
                   Typ_aux (Typ_app (_,[Typ_arg_aux (Typ_arg_nexp n2,_);_;_]),_) ->
-                   not (similar_nexps n1 n2)
+                   not (similar_nexps env n1 n2)
                 | _ -> false
               in unpack,build_ex,autocast
             in
-- 
cgit v1.2.3


From 3e8afd335d1648b700fa04c80312326aec49c9c0 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 12 Jul 2018 15:36:33 +0100
Subject: Coq: handle all bool conjunctions/disjunctions

---
 lib/coq/Sail2_values.v  | 10 +++++++++-
 lib/flow.sail           |  2 +-
 src/pretty_print_coq.ml | 17 ++++++++++-------
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 13352f4b..ab557ff4 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -928,12 +928,17 @@ Ltac unbool_comparisons :=
   | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H
   | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H
   | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H
-  | H:context [andb _ _ = true] |- _ => apply andb_prop in H
+  | H:context [orb _ _ = false] |- _ => rewrite Bool.orb_false_iff in H
+  | H:context [andb _ _ = true] |- _ => rewrite Bool.andb_true_iff in H
+  | H:context [andb _ _ = false] |- _ => rewrite Bool.andb_false_iff in H
+  | H:context [negb _ = true] |- _ => rewrite Bool.negb_true_iff in H
+  | H:context [negb _ = false] |- _ => rewrite Bool.negb_false_iff in H
   | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H
   | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H
   | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H
   | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H
   end.
+
 (* Split up dependent pairs to get at proofs of properties *)
 Ltac extract_properties :=
   repeat match goal with H := (projT1 ?X) |- _ =>
@@ -987,6 +992,9 @@ Hint Extern 0 (ArithFact _) => solve_arithfact : typeclass_instances.
 
 Hint Unfold length_mword : sail.
 
+Definition neq_atom (x : Z) (y : Z) : bool := negb (Z.eqb x y).
+Hint Unfold neq_atom : sail.
+
 Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a.
 constructor.
 destruct a.
diff --git a/lib/flow.sail b/lib/flow.sail
index 304f14bc..b4440eaa 100644
--- a/lib/flow.sail
+++ b/lib/flow.sail
@@ -9,7 +9,7 @@ val or_bool = {coq: "orb", _: "or_bool"} : (bool, bool) -> bool
 
 val eq_atom = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : forall 'n 'm. (atom('n), atom('m)) -> bool
 
-val neq_atom = {lem: "neq"} : forall 'n 'm. (atom('n), atom('m)) -> bool
+val neq_atom = {lem: "neq", coq: "neq_atom"} : forall 'n 'm. (atom('n), atom('m)) -> bool
 
 function neq_atom (x, y) = not_bool(eq_atom(x, y))
 
diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 8c345cd6..28289241 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -152,10 +152,12 @@ let rec fix_id remove_tick name = match name with
        ("v" ^ name ^ "'")
      else name
 
-let doc_id (Id_aux(i,_)) =
+let string_id (Id_aux(i,_)) =
   match i with
-  | Id i -> string (fix_id false i)
-  | DeIid x -> string (Util.zencode_string ("op " ^ x))
+  | Id i -> fix_id false i
+  | DeIid x -> Util.zencode_string ("op " ^ x)
+
+let doc_id id = string (string_id id)
 
 let doc_id_type (Id_aux(i,_)) =
   match i with
@@ -729,7 +731,7 @@ let similar_nexps env n1 n2 =
     | _ -> false
   in if same_nexp_shape (nexp_const_eval n1) (nexp_const_eval n2) then true else false
 
-let constraint_fns = ["Z.leb"; "Z.geb"; "Z.ltb"; "Z.gtb"; "Z.eqb"]
+let constraint_fns = ["Z.leb"; "Z.geb"; "Z.ltb"; "Z.gtb"; "Z.eqb"; "neq_atom"]
 
 let condition_produces_constraint exp =
   (* Cheat a little - this isn't quite the right environment for subexpressions
@@ -739,9 +741,10 @@ let condition_produces_constraint exp =
     { (Rewriter.pure_exp_alg false (||)) with
       Rewriter.e_app = fun (f,bs) ->
         List.exists (fun x -> x) bs ||
-        (Env.is_extern f env "coq" &&
-           let f' = Env.get_extern f env "coq" in
-           List.exists (fun id -> String.compare f' id == 0) constraint_fns)
+        (let name = if Env.is_extern f env "coq"
+          then Env.get_extern f env "coq"
+          else string_id f in
+         List.exists (fun id -> String.compare name id == 0) constraint_fns)
     } exp
 
 let prefix_recordtype = true
-- 
cgit v1.2.3


From 06c20157840425fb367feb186f009858a3a00448 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Thu, 12 Jul 2018 15:52:40 +0100
Subject: Coq: get rid of syntax error on exception handling

---
 src/pretty_print_coq.ml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 28289241..52ecc715 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1179,7 +1179,8 @@ let doc_exp_lem, doc_let_lem =
        if effectful (effect_of e) then
          let try_catch = if ctxt.early_ret then "try_catchR" else "try_catch" in
          let epp =
-           group ((separate space [string try_catch; expY e; string "(function "]) ^/^
+           (* TODO capture avoidance for __catch_val *)
+           group ((separate space [string try_catch; expY e; string "(fun __catch_val => match __catch_val with "]) ^/^
                     (separate_map (break 1) (doc_case ctxt exc_typ) pexps) ^/^
                       (string "end)")) in
          if aexp_needed then parens (align epp) else align epp
-- 
cgit v1.2.3


From 79ecf8b83b06a6bd1330e1f243826cbe951a9e7d Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 12 Jul 2018 15:54:11 +0100
Subject: update arm and mips models for new type of write_ram builtin. Also
 fix c and interpreter implementations of same.

---
 aarch64/no_devices.sail | 4 ++--
 lib/rts.c               | 4 ++--
 lib/rts.h               | 2 +-
 mips/prelude.sail       | 4 ++--
 src/value.ml            | 4 ++--
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/aarch64/no_devices.sail b/aarch64/no_devices.sail
index 882aa6b3..57dad4e2 100644
--- a/aarch64/no_devices.sail
+++ b/aarch64/no_devices.sail
@@ -1,6 +1,6 @@
 
 val ___WriteRAM = "write_ram" : forall 'n 'm.
-  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> bool effect {wmem}
 
 val __InitRAM : forall 'm. (atom('m), int, bits('m), bits(8)) -> unit
 
@@ -25,7 +25,7 @@ val __WriteRAM : forall 'n 'm.
 
 function __WriteRAM(addr_length, bytes, hex_ram, addr, data) =
 {
-  ___WriteRAM(addr_length, bytes, hex_ram, addr, data)
+  let _ = ___WriteRAM(addr_length, bytes, hex_ram, addr, data) in ()
 }
 
 function __TraceMemoryWrite(bytes, addr, data) = ()
diff --git a/lib/rts.c b/lib/rts.c
index 84ff4916..97aad8a4 100644
--- a/lib/rts.c
+++ b/lib/rts.c
@@ -208,7 +208,7 @@ void kill_mem()
 
 // ***** Memory builtins *****
 
-unit write_ram(const mpz_t addr_size,     // Either 32 or 64
+bool write_ram(const mpz_t addr_size,     // Either 32 or 64
 	       const mpz_t data_size_mpz, // Number of bytes
 	       const sail_bits  hex_ram,       // Currently unused
 	       const sail_bits  addr_bv,
@@ -231,7 +231,7 @@ unit write_ram(const mpz_t addr_size,     // Either 32 or 64
   }
 
   mpz_clear(buf);
-  return UNIT;
+  return true;
 }
 
 void read_ram(sail_bits *data,
diff --git a/lib/rts.h b/lib/rts.h
index cedb555e..98bbd078 100644
--- a/lib/rts.h
+++ b/lib/rts.h
@@ -53,7 +53,7 @@ uint64_t read_mem(uint64_t);
 // These memory builtins are intended to match the semantics for the
 // __ReadRAM and __WriteRAM functions in ASL.
 
-unit write_ram(const mpz_t addr_size,     // Either 32 or 64
+bool write_ram(const mpz_t addr_size,     // Either 32 or 64
 	       const mpz_t data_size_mpz, // Number of bytes
 	       const sail_bits hex_ram,       // Currently unused
 	       const sail_bits addr_bv,
diff --git a/mips/prelude.sail b/mips/prelude.sail
index 037819bc..85060dda 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -125,10 +125,10 @@ overload min = {min_atom, min_nat, min_int}
 overload max = {max_atom, max_nat, max_int}
 
 val __WriteRAM = "write_ram" : forall 'n 'm.
-  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmv}
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> bool effect {wmv}
 
 val __MIPS_write : forall 'n. (bits(64), atom('n), bits(8 * 'n)) -> unit effect {wmv}
-function __MIPS_write (addr, width, data) = __WriteRAM(64, width, 0x0000_0000_0000_0000, addr, data)
+function __MIPS_write (addr, width, data) = let _ = __WriteRAM(64, width, 0x0000_0000_0000_0000, addr, data) in ()
 
 val __ReadRAM = "read_ram" : forall 'n 'm, 'n >= 0.
   (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
diff --git a/src/value.ml b/src/value.ml
index 1d2346af..dccb216e 100644
--- a/src/value.ml
+++ b/src/value.ml
@@ -406,8 +406,8 @@ let value_read_ram = function
 
 let value_write_ram = function
   | [v1; v2; v3; v4; v5] ->
-     Sail_lib.write_ram (coerce_int v1, coerce_int v2, coerce_bv v3, coerce_bv v4, coerce_bv v5);
-     V_unit
+     let b = Sail_lib.write_ram (coerce_int v1, coerce_int v2, coerce_bv v3, coerce_bv v4, coerce_bv v5) in
+     V_bool(b)
   | _ -> failwith "value write_ram"
 
 let value_load_raw = function
-- 
cgit v1.2.3


From d482dcd0152b1f44faf1ad3b1ae06c029a048dab Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Thu, 12 Jul 2018 16:14:13 +0100
Subject: Handle failures during interpreting better

Changes to the interpreter to better support constant folding during
compilation mean it can now throw exceptions to the caller, allow the
caller to handle the error, rather than simply printing an error. This
broke the ARM interpreter test because exit() is handled by throwing
an Exit exception in the interpreter.
---
 src/isail.ml | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/src/isail.ml b/src/isail.ml
index 593167f9..4adc1cd2 100644
--- a/src/isail.ml
+++ b/src/isail.ml
@@ -127,7 +127,12 @@ let rec run () =
           print_endline ("Result = " ^ Value.string_of_value v);
           current_mode := Normal
        | Step (out, state, _, stack) ->
-          current_mode := Evaluation (eval_frame !interactive_ast frame);
+          begin
+            try
+              current_mode := Evaluation (eval_frame !interactive_ast frame)
+            with
+            | Failure str -> print_endline str; current_mode := Normal
+          end;
           run ()
        | Break frame ->
           print_endline "Breakpoint";
@@ -147,7 +152,12 @@ let rec run_steps n =
           print_endline ("Result = " ^ Value.string_of_value v);
           current_mode := Normal
        | Step (out, state, _, stack) ->
-          current_mode := Evaluation (eval_frame !interactive_ast frame);
+          begin
+            try
+              current_mode := Evaluation (eval_frame !interactive_ast frame)
+            with
+            | Failure str -> print_endline str; current_mode := Normal
+          end;
           run_steps (n - 1)
        | Break frame ->
           print_endline "Breakpoint";
@@ -352,9 +362,14 @@ let handle_input' input =
                print_endline ("Result = " ^ Value.string_of_value v);
                current_mode := Normal
             | Step (out, state, _, stack) ->
-               interactive_state := state;
-               current_mode := Evaluation (eval_frame !interactive_ast frame);
-               print_program ()
+               begin
+                 try
+                   interactive_state := state;
+                   current_mode := Evaluation (eval_frame !interactive_ast frame);
+                   print_program ()
+                 with
+                 | Failure str -> print_endline str; current_mode := Normal
+               end
             | Break frame ->
                print_endline "Breakpoint";
                current_mode := Evaluation frame
-- 
cgit v1.2.3


From e6977ee8e2ba7a53d69f2fb3b715846a62a50454 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 12 Jul 2018 17:04:11 +0100
Subject: make unziping freebsd kernel more robust if run again.

---
 test/cheri/run_tests.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/cheri/run_tests.sh b/test/cheri/run_tests.sh
index 848a07e2..337974d7 100755
--- a/test/cheri/run_tests.sh
+++ b/test/cheri/run_tests.sh
@@ -67,7 +67,7 @@ fi
 
 printf "Booting FreeBSD-MIPS...\n"
 
-bunzip2 freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2
+bunzip2 -fk freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2
 time $SAILDIR/mips/mips_c --cyclelimit 85000000 --binary 0x100000,freebsd-beri-sim-mdroot-smoketest_bootonly-kernel --binary 0x7f010000,sim.dtb  --image simboot_128m.sailbin > freebsd_out.txt
 if  grep -q 'Done booting' freebsd_out.txt;
 then
-- 
cgit v1.2.3


From 3c4a27d7041d71fb229970dacab013cf84669755 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 12 Jul 2018 17:04:40 +0100
Subject: Add missing builtins needed for cheri128 C. Still doesn't build
 possibly due to code gen issue.

---
 lib/sail.c        | 13 +++++++++++++
 lib/sail.h        |  3 +++
 mips/prelude.sail |  4 ++--
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/lib/sail.c b/lib/sail.c
index 4cb9cdc1..38c8c273 100644
--- a/lib/sail.c
+++ b/lib/sail.c
@@ -781,6 +781,19 @@ void shift_bits_right_arith(sail_bits *rop, const sail_bits op1, const sail_bits
   }
 }
 
+void shiftl(sail_bits *rop, const sail_bits op1, const sail_int op2)
+{
+  rop->len = op1.len;
+  mpz_mul_2exp(*rop->bits, *op1.bits, mpz_get_ui(op2));
+  normalize_sail_bits(rop);
+}
+
+void shiftr(sail_bits *rop, const sail_bits op1, const sail_int op2)
+{
+  rop->len = op1.len;
+  mpz_tdiv_q_2exp(*rop->bits, *op1.bits, mpz_get_ui(op2));
+}
+
 void reverse_endianness(sail_bits *rop, const sail_bits op)
 {
   rop->len = op.len;
diff --git a/lib/sail.h b/lib/sail.h
index bbdccd09..9ce3ec6b 100644
--- a/lib/sail.h
+++ b/lib/sail.h
@@ -273,6 +273,9 @@ void shift_bits_left(sail_bits *rop, const sail_bits op1, const sail_bits op2);
 void shift_bits_right(sail_bits *rop, const sail_bits op1, const sail_bits op2);
 void shift_bits_right_arith(sail_bits *rop, const sail_bits op1, const sail_bits op2);
 
+void shiftl(sail_bits *rop, const sail_bits op1, const sail_int op2);
+void shiftr(sail_bits *rop, const sail_bits op1, const sail_int op2);
+
 void reverse_endianness(sail_bits*, sail_bits);
 
 /* ***** Sail reals ***** */
diff --git a/mips/prelude.sail b/mips/prelude.sail
index 85060dda..4c77d522 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -116,9 +116,9 @@ val max_nat = {lem: "max", coq: "Z.max", _: "max_int"} : (nat, nat) -> nat
 
 val max_int = {lem: "max", coq: "Z.max", _: "max_int"} : (int, int) -> int
 
-val min_atom = {ocaml: "min_int", lem: "min", coq: "min_atom"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c <= 'a & 'c <= 'b . atom('c)}
+val min_atom = {ocaml: "min_int", lem: "min", coq: "min_atom", c:"min_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c <= 'a & 'c <= 'b . atom('c)}
 
-val max_atom = {ocaml: "max_int", lem: "max", coq: "max_atom"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c >= 'a & 'c >= 'b . atom('c)}
+val max_atom = {ocaml: "max_int", lem: "max", coq: "max_atom", c:"max_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c >= 'a & 'c >= 'b . atom('c)}
 
 overload min = {min_atom, min_nat, min_int}
 
-- 
cgit v1.2.3


From 6586abcc185fa4e0f3853a73d91f097fbde16aca Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Fri, 13 Jul 2018 10:14:57 +0100
Subject: Coq: avoid a couple of common identifiers

---
 src/pretty_print_coq.ml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 52ecc715..aaef83cb 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -135,6 +135,8 @@ let rec fix_id remove_tick name = match name with
   | "GT"
   | "EQ"
   | "Z"
+  | "O"
+  | "S"
   | "mod"
   | "M"
     -> name ^ "'"
-- 
cgit v1.2.3


From 7bdcdcc7abdde74993020d1f2c33ea00d6784fc4 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Fri, 13 Jul 2018 12:14:17 +0100
Subject: prepare for new opam release

---
 opam | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/opam b/opam
index 3e3c93a9..be29c2ef 100644
--- a/opam
+++ b/opam
@@ -1,6 +1,6 @@
 opam-version: "1.2"
 name: "sail"
-version: "0.2"
+version: "0.3"
 maintainer: "Sail Devs <cl-sail-dev@lists.cam.ac.uk>"
 authors: [
   "Alasdair Armstrong"
@@ -29,6 +29,6 @@ depends: [
   "linenoise"
   "ott" {>= "0.28"}
   "lem"
-  "linksem" {>= "0.2"}
+  "linksem" {>= "0.3"}
 ]
 available: [ocaml-version >= "4.02.3"]
-- 
cgit v1.2.3


From a48dad8232a7db82c74a72157249a27ce25d326e Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 16 Jul 2018 15:59:23 +0100
Subject: Coq: add support for more complex atom types As a result, add proof
 to pow2.

---
 lib/coq/Sail2_values.v  |  8 +++++++-
 src/pretty_print_coq.ml | 47 +++++++++++++++++++++++++++++++++++++++++------
 2 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index ab557ff4..335ebf26 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -73,7 +73,13 @@ Definition nn := nat.
 (*val pow : Z -> Z -> Z*)
 Definition pow m n := m ^ n.
 
-Definition pow2 n := pow 2 n.
+Program Definition pow2 n : {z : Z & ArithFact (2 ^ n <= z <= 2 ^ n)} := existT _ (pow 2 n) _.
+Next Obligation.
+constructor.
+unfold pow.
+auto using Z.le_refl.
+Qed.
+
 (*
 Definition inline lt := (<)
 Definition inline gt := (>)
diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index aaef83cb..95b3fb68 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -749,6 +749,28 @@ let condition_produces_constraint exp =
          List.exists (fun id -> String.compare name id == 0) constraint_fns)
     } exp
 
+(* For most functions whose return types are non-trivial atoms we return a
+   dependent pair with a proof that the result is the expected integer.  This
+   is redundant for basic arithmetic functions and functions which we unfold
+   in the constraint solver. *)
+let no_Z_proof_fns = ["Z.add"; "Z.sub"; "Z.opp"; "Z.mul"; "length_mword"]
+
+let is_no_Z_proof_fn env id =
+  if Env.is_extern id env "coq"
+  then
+    let s = Env.get_extern id env "coq" in
+    List.exists (fun x -> String.compare x s == 0) no_Z_proof_fns
+  else false
+
+let replace_atom_return_type ret_typ =
+  (* TODO: more complex uses of atom *)
+  match ret_typ with
+  | Typ_aux (Typ_app (Id_aux (Id "atom",_), [Typ_arg_aux (Typ_arg_nexp nexp,_)]),l) ->
+     let kid = mk_kid "_retval" in (* TODO: collision avoidance *)
+     true, Typ_aux (Typ_exist ([kid], nc_eq (nvar kid) nexp, atom_typ (nvar kid)),Generated l)
+  | _ -> false, ret_typ
+
+
 let prefix_recordtype = true
 let report = Reporting_basic.err_unreachable
 let doc_exp_lem, doc_let_lem =
@@ -1014,6 +1036,9 @@ let doc_exp_lem, doc_let_lem =
               let ann_typ = Env.expand_synonyms env (typ_of_annot (l,annot)) in
               let ann_typ = expand_range_type ann_typ in
               let ret_typ_inst = expand_range_type (Env.expand_synonyms env ret_typ_inst) in
+              let ret_typ_inst =
+                if is_no_Z_proof_fn env f then ret_typ_inst
+                else snd (replace_atom_return_type ret_typ_inst) in
               let unpack, build_ex, in_typ, out_typ =
                 match ret_typ_inst, ann_typ with
                 | Typ_aux (Typ_exist (_,_,t1),_), Typ_aux (Typ_exist (_,_,t2),_) ->
@@ -1497,17 +1522,23 @@ let demote_as_pattern i (P_aux (_,p_annot) as pat,typ) =
       E_aux (E_let (LB_aux (LB_val (pat, E_aux (E_id id, p_annot)),p_annot),e),e_ann)
   else (pat,typ), fun e -> e
 
-(* Ideally we'd remove the duplication between type variables and atom
-   arguments, but for now we just add an equality constraint. *)
+(* Add equality constraints between arguments and nexps, except in the case
+   that they've been merged. *)
 
 let atom_constraint ctxt (pat, typ) =
   let typ = Env.base_typ_of (pat_env_of pat) typ in
   match pat, typ with
   | P_aux (P_id id, _),
       Typ_aux (Typ_app (Id_aux (Id "atom",_),
-                        [Typ_arg_aux (Typ_arg_nexp (Nexp_aux (Nexp_var kid,_)),_)]),_) ->
-     Some (bquote ^^ braces (string "ArithFact" ^^ space ^^
-                               parens (doc_op equals (doc_id id) (doc_var_lem ctxt kid))))
+                        [Typ_arg_aux (Typ_arg_nexp nexp,_)]),_) ->
+     (match nexp with
+       (* When the kid is mapped to the id, we don't need a constraint *)
+     | Nexp_aux (Nexp_var kid,_)
+         when (try Id.compare (KBindings.find kid ctxt.kid_id_renames) id == 0 with _ -> false) ->
+           None
+     | _ ->
+        Some (bquote ^^ braces (string "ArithFact" ^^ space ^^
+                                  parens (doc_op equals (doc_id id) (doc_nexp ctxt nexp)))))
   | _ -> None
 
 let all_ids pexp =
@@ -1616,6 +1647,7 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
   let patspp = separate_map space doc_binder pats in
   let atom_constrs = Util.map_filter (atom_constraint ctxt) pats in
   let atom_constr_pp = separate space atom_constrs in
+  let build_ex, ret_typ = replace_atom_return_type ret_typ in
   let retpp =
     if effectful eff
     then string "M" ^^ space ^^ parens (doc_typ ctxt ret_typ)
@@ -1639,10 +1671,12 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
     | _ ->
        raise (Reporting_basic.err_unreachable l
                 "guarded pattern expression should have been rewritten before pretty-printing") in
+  let bodypp = doc_fun_body ctxt exp in
+  let bodypp = if build_ex then string "build_ex" ^^ space ^^ parens bodypp else bodypp in
   group (prefix 3 1
     (separate space ([idpp] @ quantspp @ [patspp] @ constrspp @ [atom_constr_pp]) ^/^
        separate space [colon; retpp; coloneq])
-    (doc_fun_body ctxt exp ^^ dot)) ^^ implicitargs
+    (bodypp ^^ dot)) ^^ implicitargs
 
 let get_id = function
   | [] -> failwith "FD_function with empty list"
@@ -1769,6 +1803,7 @@ let doc_axiom_typschm typ_env (TypSchm_aux (TypSchm_ts (tqs,typ),l) as ts) =
        | _ -> parens (underscore ^^ string " : " ^^ doc_typ empty_ctxt typ)
      in
      let arg_typs_pp = separate space (List.map doc_typ' typs) in
+     let _, ret_ty = replace_atom_return_type ret_ty in
      let ret_typ_pp = doc_typ empty_ctxt ret_ty in
      let tyvars_pp, constrs_pp = doc_typquant_items_separate empty_ctxt braces tqs in
      string "forall" ^/^ separate space tyvars_pp ^/^
-- 
cgit v1.2.3


From 786ff327752c7fd26550d96ed2ba328f0facdb4a Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 16 Jul 2018 17:07:24 +0100
Subject: Coq: handle simple type variable matches properly and nat type

---
 src/pretty_print_coq.ml | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 95b3fb68..62ff2b3b 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -768,6 +768,9 @@ let replace_atom_return_type ret_typ =
   | Typ_aux (Typ_app (Id_aux (Id "atom",_), [Typ_arg_aux (Typ_arg_nexp nexp,_)]),l) ->
      let kid = mk_kid "_retval" in (* TODO: collision avoidance *)
      true, Typ_aux (Typ_exist ([kid], nc_eq (nvar kid) nexp, atom_typ (nvar kid)),Generated l)
+  | Typ_aux (Typ_id (Id_aux (Id "nat",_)),l) ->
+     let kid = mk_kid "_retval" in
+     true, Typ_aux (Typ_exist ([kid], nc_gteq (nvar kid) (nconstant Nat_big_num.zero), atom_typ (nvar kid)),Generated l)
   | _ -> false, ret_typ
 
 
@@ -1525,7 +1528,7 @@ let demote_as_pattern i (P_aux (_,p_annot) as pat,typ) =
 (* Add equality constraints between arguments and nexps, except in the case
    that they've been merged. *)
 
-let atom_constraint ctxt (pat, typ) =
+let rec atom_constraint ctxt (pat, typ) =
   let typ = Env.base_typ_of (pat_env_of pat) typ in
   match pat, typ with
   | P_aux (P_id id, _),
@@ -1539,6 +1542,11 @@ let atom_constraint ctxt (pat, typ) =
      | _ ->
         Some (bquote ^^ braces (string "ArithFact" ^^ space ^^
                                   parens (doc_op equals (doc_id id) (doc_nexp ctxt nexp)))))
+  | P_aux (P_id id, _),
+        Typ_aux (Typ_id (Id_aux (Id "nat",_)),_) ->
+     Some (bquote ^^ braces (string "ArithFact" ^^ space ^^
+                                  parens (doc_op (string ">=") (doc_id id) (string "0"))))
+  | P_aux (P_typ (_,p),_), _ -> atom_constraint ctxt (p, typ)
   | _ -> None
 
 let all_ids pexp =
@@ -1609,6 +1617,13 @@ let merge_kids_atoms pats =
   let gone,map,_ = List.fold_left try_eliminate (KidSet.empty, KBindings.empty, KidSet.empty) pats in
   gone,map
 
+let merge_var_patterns map pats =
+  let map,pats = List.fold_left (fun (map,pats) (pat, typ) ->
+    match pat with
+    | P_aux (P_var (P_aux (P_id id,_), TP_aux (TP_var kid,_)),ann) ->
+       KBindings.add kid id map, (P_aux (P_id id,ann), typ) :: pats
+    | _ -> map, (pat,typ)::pats) (map,[]) pats
+  in map, List.rev pats
 
 let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
   let (tq,typ) = Env.get_val_spec_orig id (env_of_annot annot) in
@@ -1622,6 +1637,7 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
   let pats, bind = untuple_args_pat arg_typ pat in
   let pats, binds = List.split (Util.list_mapi demote_as_pattern pats) in
   let eliminated_kids, kid_to_arg_rename = merge_kids_atoms pats in
+  let kid_to_arg_rename, pats = merge_var_patterns kid_to_arg_rename pats in
   let kids_used = KidSet.diff kids_used eliminated_kids in
   let ctxt =
     { early_ret = contains_early_return exp;
-- 
cgit v1.2.3


From 0effbdd2468859924363fe00f29c0afcb727f065 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 16 Jul 2018 18:02:09 +0100
Subject: Coq: we also unfold length

---
 src/pretty_print_coq.ml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 62ff2b3b..7a31465d 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -753,7 +753,7 @@ let condition_produces_constraint exp =
    dependent pair with a proof that the result is the expected integer.  This
    is redundant for basic arithmetic functions and functions which we unfold
    in the constraint solver. *)
-let no_Z_proof_fns = ["Z.add"; "Z.sub"; "Z.opp"; "Z.mul"; "length_mword"]
+let no_Z_proof_fns = ["Z.add"; "Z.sub"; "Z.opp"; "Z.mul"; "length_mword"; "length"]
 
 let is_no_Z_proof_fn env id =
   if Env.is_extern id env "coq"
-- 
cgit v1.2.3


From eec725af3dbfc0e8c0ccb79cf8eb457ff5cf68a4 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 16 Jul 2018 18:29:18 +0100
Subject: Coq: fix false existential problem

---
 src/pretty_print_coq.ml | 13 +++++++------
 src/type_check.ml       |  6 ++++++
 src/type_check.mli      |  4 ++++
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 7a31465d..32a560ea 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1023,16 +1023,17 @@ let doc_exp_lem, doc_let_lem =
             (* Decide whether to unpack an existential result, pack one, or cast.
                To do this we compare the expected type stored in the checked expression
                with the inferred type. *)
-            let ret_typ_inst =
-              match infer_exp env (strip_exp full_exp) with
-              | typed_exp -> typ_of typed_exp
+            let inst =
+              match instantiation_of_without_type full_exp with
+              | x -> x
               (* Not all function applications can be inferred, so try falling back to the
                  type inferred when we know the target type.
                  TODO: there are probably some edge cases where this won't pick up a need
                  to cast. *)
-              | exception _ ->
-                 let inst = instantiation_of full_exp in
-                 let inst = KBindings.fold (fun k u m -> KBindings.add (orig_kid k) u m) inst KBindings.empty in
+              | exception _ -> instantiation_of full_exp
+            in
+            let inst = KBindings.fold (fun k u m -> KBindings.add (orig_kid k) u m) inst KBindings.empty in
+            let ret_typ_inst =
                  subst_unifiers inst ret_typ
             in
             let unpack,build_ex,autocast =
diff --git a/src/type_check.ml b/src/type_check.ml
index db85bf33..2d1241b9 100644
--- a/src/type_check.ml
+++ b/src/type_check.ml
@@ -3302,6 +3302,12 @@ and instantiation_of (E_aux (exp_aux, (l, _)) as exp) =
   | E_app (f, xs) -> snd (infer_funapp' l (Env.no_casts env) f (Env.get_val_spec f env) (List.map strip_exp xs) (Some (typ_of exp)))
   | _ -> invalid_arg ("instantiation_of expected application,  got " ^ string_of_exp exp)
 
+and instantiation_of_without_type (E_aux (exp_aux, (l, _)) as exp) =
+  let env = env_of exp in
+  match exp_aux with
+  | E_app (f, xs) -> snd (infer_funapp' l (Env.no_casts env) f (Env.get_val_spec f env) (List.map strip_exp xs) None)
+  | _ -> invalid_arg ("instantiation_of expected application,  got " ^ string_of_exp exp)
+
 and infer_funapp' l env f (typq, f_typ) xs ret_ctx_typ =
   let annot_exp exp typ eff = E_aux (exp, (l, Some (env, typ, eff))) in
   let switch_annot env typ = function
diff --git a/src/type_check.mli b/src/type_check.mli
index fd1ddb92..665981e9 100644
--- a/src/type_check.mli
+++ b/src/type_check.mli
@@ -355,6 +355,10 @@ val alpha_equivalent : Env.t -> typ -> typ -> bool
 (** Throws Invalid_argument if the argument is not a E_app expression *)
 val instantiation_of : tannot exp -> uvar KBindings.t
 
+(** Doesn't use the type of the expression when calculating instantiations.
+    May fail if the arguments aren't sufficient to calculate all unifiers. *)
+val instantiation_of_without_type : tannot exp -> uvar KBindings.t
+
 (* Type variable instantiations that inference will extract from constraints *)
 val instantiate_simple_equations : quant_item list -> uvar KBindings.t
 
-- 
cgit v1.2.3


From 48c73e33a621034ba020b9b1bc83c5f70a19314f Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 17 Jul 2018 12:19:15 +0100
Subject: Coq: handle E_constraint properly Adds missing constraints for
 aarch64

---
 lib/coq/Sail2_values.v  | 16 ++++++++++++++++
 src/pretty_print_coq.ml | 30 +++++++++++++++++++++++-------
 2 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 335ebf26..0bd4707d 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -239,6 +239,22 @@ f_equal.
 auto using just_list_length.
 Qed.
 
+Fixpoint member_Z_list (x : Z) (l : list Z) : bool :=
+match l with
+| [] => false
+| h::t => if x =? h then true else member_Z_list x t
+end.
+
+Lemma member_Z_list_In {x l} : member_Z_list x l = true <-> In x l.
+induction l.
+* simpl. split. congruence. tauto.
+* simpl. destruct (x =? a) eqn:H.
+  + rewrite Z.eqb_eq in H. subst. tauto.
+  + rewrite Z.eqb_neq in H. split.
+    - intro Heq. right. apply IHl. assumption.
+    - intros [bad | good]. congruence. apply IHl. assumption.
+Qed.
+
 (*** Bits *)
 Inductive bitU := B0 | B1 | BU.
 
diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 32a560ea..5c4e4e54 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -323,7 +323,7 @@ let drop_duplicate_atoms kids ty =
   in aux_typ ty
 
 (* TODO: parens *)
-let rec doc_nc ctx (NC_aux (nc,_)) =
+let rec doc_nc_prop ctx (NC_aux (nc,_)) =
   match nc with
   | NC_equal (ne1, ne2) -> doc_op equals (doc_nexp ctx ne1) (doc_nexp ctx ne2)
   | NC_bounded_ge (ne1, ne2) -> doc_op (string ">=") (doc_nexp ctx ne1) (doc_nexp ctx ne2)
@@ -333,11 +333,27 @@ let rec doc_nc ctx (NC_aux (nc,_)) =
      separate space [string "In"; doc_var_lem ctx kid;
                      brackets (separate (string "; ")
                                  (List.map (fun i -> string (Nat_big_num.to_string i)) is))]
-  | NC_or (nc1, nc2) -> doc_op (string "\\/") (doc_nc ctx nc1) (doc_nc ctx nc2)
-  | NC_and (nc1, nc2) -> doc_op (string "/\\") (doc_nc ctx nc1) (doc_nc ctx nc2)
+  | NC_or (nc1, nc2) -> doc_op (string "\\/") (doc_nc_prop ctx nc1) (doc_nc_prop ctx nc2)
+  | NC_and (nc1, nc2) -> doc_op (string "/\\") (doc_nc_prop ctx nc1) (doc_nc_prop ctx nc2)
   | NC_true -> string "True"
   | NC_false -> string "False"
 
+(* TODO: parens *)
+let rec doc_nc_exp ctx (NC_aux (nc,_)) =
+  match nc with
+  | NC_equal (ne1, ne2) -> doc_op (string "=?") (doc_nexp ctx ne1) (doc_nexp ctx ne2)
+  | NC_bounded_ge (ne1, ne2) -> doc_op (string ">=?") (doc_nexp ctx ne1) (doc_nexp ctx ne2)
+  | NC_bounded_le (ne1, ne2) -> doc_op (string "<=?") (doc_nexp ctx ne1) (doc_nexp ctx ne2)
+  | NC_not_equal (ne1, ne2) -> string "negb" ^^ space ^^ parens (doc_op (string "=?") (doc_nexp ctx ne1) (doc_nexp ctx ne2))
+  | NC_set (kid, is) -> (* TODO: is this a good translation? *)
+     separate space [string "member_Z_list"; doc_var_lem ctx kid;
+                     brackets (separate (string "; ")
+                                 (List.map (fun i -> string (Nat_big_num.to_string i)) is))]
+  | NC_or (nc1, nc2) -> doc_op (string "||") (doc_nc_exp ctx nc1) (doc_nc_exp ctx nc2)
+  | NC_and (nc1, nc2) -> doc_op (string "&&") (doc_nc_exp ctx nc1) (doc_nc_exp ctx nc2)
+  | NC_true -> string "true"
+  | NC_false -> string "false"
+
 let maybe_expand_range_type (Typ_aux (typ,l) as full_typ) =
   match typ with
   | Typ_app(Id_aux (Id "range", _), [Typ_arg_aux(Typ_arg_nexp low,_);
@@ -352,7 +368,7 @@ let maybe_expand_range_type (Typ_aux (typ,l) as full_typ) =
 let expand_range_type typ = Util.option_default typ (maybe_expand_range_type typ)
 
 let doc_arithfact ctxt nc =
-  string "ArithFact" ^^ space ^^ parens (doc_nc ctxt nc)
+  string "ArithFact" ^^ space ^^ parens (doc_nc_prop ctxt nc)
 
 (* When making changes here, check whether they affect lem_tyvars_of_typ *)
 let doc_typ, doc_atomic_typ =
@@ -1273,7 +1289,7 @@ let doc_exp_lem, doc_let_lem =
           parens (doc_typ ctxt (typ_of full_exp));
           parens (doc_typ ctxt (typ_of r))] in
       align (parens (string "early_return" ^//^ expV true r ^//^ ta))
-    | E_constraint _ -> string "true"
+    | E_constraint nc -> wrap_parens (doc_nc_exp ctxt nc)
     | E_comment _ | E_comment_struc _ -> empty
     | E_internal_cast _ | E_internal_exp _ | E_sizeof_internal _
     | E_internal_exp_user _ | E_internal_value _ ->
@@ -1964,8 +1980,8 @@ try
           (fun lib -> separate space [string "Require Import";string lib] ^^ dot) defs_modules;hardline;
         string "Import ListNotations.";
         hardline;
-        string "Open Scope string.";
-        hardline;
+        string "Open Scope string."; hardline;
+        string "Open Scope bool."; hardline;
         (* Put the body into a Section so that we can define some values with
            Let to put them into the local context, where tactics can see them *)
         string "Section Content.";
-- 
cgit v1.2.3


From 48cc76254b6cbbf536a0424275087b084d40f4cb Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 17 Jul 2018 13:19:53 +0100
Subject: Coq: add printing stubs

---
 lib/coq/Sail2_values.v | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 0bd4707d..63cf7542 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -112,7 +112,12 @@ Definition negate_real r := realNegate r
 Definition abs_real r := realAbs r
 Definition power_real b e := realPowInteger b e*)
 
+Definition print_endline (_ : string) : unit := tt.
+Definition prerr_endline (_ : string) : unit := tt.
+Definition prerr (_ : string) : unit := tt.
 Definition print_int (_ : string) (_ : Z) : unit := tt.
+Definition prerr_int (_ : string) (_ : Z) : unit := tt.
+Definition putchar (_ : Z) : unit := tt.
 
 (*
 Definition or_bool l r := (l || r)
-- 
cgit v1.2.3


From 904b625c79b8f96d758a880918cdf6901d2b9ebf Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 17 Jul 2018 15:02:12 +0100
Subject: Coq: integer shifts

---
 lib/coq/Sail2_values.v | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 63cf7542..0c806222 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -119,6 +119,9 @@ Definition print_int (_ : string) (_ : Z) : unit := tt.
 Definition prerr_int (_ : string) (_ : Z) : unit := tt.
 Definition putchar (_ : Z) : unit := tt.
 
+Definition shl_int := Z.shiftl.
+Definition shr_int := Z.shiftr.
+
 (*
 Definition or_bool l r := (l || r)
 Definition and_bool l r := (l && r)
-- 
cgit v1.2.3


From ba4250ac585a247ab71656f57aced6857b98ecea Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 17 Jul 2018 15:50:08 +0100
Subject: Coq: support returning rich integer types from effectful functions
 (e.g., coerce_int_nat in aarch64)

---
 src/pretty_print_coq.ml | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 5c4e4e54..44670277 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -96,12 +96,14 @@ type context = {
   kid_renames : kid KBindings.t; (* Plain tyvar -> tyvar renames *)
   kid_id_renames : id KBindings.t; (* tyvar -> argument renames *)
   bound_nexps : NexpSet.t;
+  build_ex_return : bool;
 }
 let empty_ctxt = {
   early_ret = false;
   kid_renames = KBindings.empty;
   kid_id_renames = KBindings.empty;
-  bound_nexps = NexpSet.empty
+  bound_nexps = NexpSet.empty;
+  build_ex_return = false;
 }
 
 let langlebar = string "<|"
@@ -1272,7 +1274,11 @@ let doc_exp_lem, doc_let_lem =
             if aexp_needed then parens (align epp) else epp
        end
     | E_internal_return (e1) ->
-       wrap_parens (align (separate space [string "returnm"; expY e1]))
+       let e1pp = expY e1 in
+       let valpp = if ctxt.build_ex_return
+         then parens (string "build_ex" ^^ space ^^ e1pp)
+         else e1pp in
+       wrap_parens (align (separate space [string "returnm"; valpp]))
     | E_sizeof nexp ->
       (match nexp_simp nexp with
         | Nexp_aux (Nexp_constant i, _) -> doc_lit (L_aux (L_num i, l))
@@ -1648,6 +1654,7 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
     | Typ_aux (Typ_fn (arg_typ, ret_typ, eff),_) -> arg_typ, ret_typ, eff
     | _ -> failwith ("Function " ^ string_of_id id ^ " does not have function type")
   in
+  let build_ex, ret_typ = replace_atom_return_type ret_typ in
   let ids_to_avoid = all_ids pexp in
   let kids_used = tyvars_of_typquant tq in
   let pat,guard,exp,(l,_) = destruct_pexp pexp in
@@ -1660,7 +1667,9 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
     { early_ret = contains_early_return exp;
       kid_renames = mk_kid_renames ids_to_avoid kids_used;
       kid_id_renames = kid_to_arg_rename;
-      bound_nexps = NexpSet.union (lem_nexps_of_typ typ) (typeclass_nexps typ) } in
+      bound_nexps = NexpSet.union (lem_nexps_of_typ typ) (typeclass_nexps typ);
+      build_ex_return = effectful eff && build_ex;
+    } in
   (* Put the constraints after pattern matching so that any type variable that's
      been replaced by one of the term-level arguments is bound. *)
   let quantspp, constrspp = doc_typquant_items_separate ctxt braces tq in
@@ -1680,7 +1689,6 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
   let patspp = separate_map space doc_binder pats in
   let atom_constrs = Util.map_filter (atom_constraint ctxt) pats in
   let atom_constr_pp = separate space atom_constrs in
-  let build_ex, ret_typ = replace_atom_return_type ret_typ in
   let retpp =
     if effectful eff
     then string "M" ^^ space ^^ parens (doc_typ ctxt ret_typ)
@@ -1705,7 +1713,7 @@ let doc_funcl (FCL_aux(FCL_Funcl(id, pexp), annot)) =
        raise (Reporting_basic.err_unreachable l
                 "guarded pattern expression should have been rewritten before pretty-printing") in
   let bodypp = doc_fun_body ctxt exp in
-  let bodypp = if build_ex then string "build_ex" ^^ space ^^ parens bodypp else bodypp in
+  let bodypp = if effectful eff || not build_ex then bodypp else string "build_ex" ^^ parens bodypp in
   group (prefix 3 1
     (separate space ([idpp] @ quantspp @ [patspp] @ constrspp @ [atom_constr_pp]) ^/^
        separate space [colon; retpp; coloneq])
-- 
cgit v1.2.3


From 0c5ff0aa6cd611ab40233b284b0a6054bc27166e Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Tue, 17 Jul 2018 16:06:27 +0100
Subject: Coq: support effectful function signatures in axiom generation

---
 src/pretty_print_coq.ml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml
index 44670277..74e97a29 100644
--- a/src/pretty_print_coq.ml
+++ b/src/pretty_print_coq.ml
@@ -1846,6 +1846,11 @@ let doc_axiom_typschm typ_env (TypSchm_aux (TypSchm_ts (tqs,typ),l) as ts) =
      let arg_typs_pp = separate space (List.map doc_typ' typs) in
      let _, ret_ty = replace_atom_return_type ret_ty in
      let ret_typ_pp = doc_typ empty_ctxt ret_ty in
+     let ret_typ_pp =
+       if effectful eff
+       then string "M" ^^ space ^^ parens ret_typ_pp
+       else ret_typ_pp
+     in
      let tyvars_pp, constrs_pp = doc_typquant_items_separate empty_ctxt braces tqs in
      string "forall" ^/^ separate space tyvars_pp ^/^
        arg_typs_pp ^/^ separate space constrs_pp ^^ comma ^/^ ret_typ_pp
-- 
cgit v1.2.3


From 92f1e32b677d3b80eb509ddadb323714de2b3092 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Wed, 18 Jul 2018 11:35:04 +0100
Subject: Coq: constraint solving improvements Use eauto so that user-added
 hints are more flexible, example with Replicate in aarch64, dropped zbool to
 prevent slow proof searches (and preprocessing deals with boolean comparisons
 now). Report failed constraints after preprocessing; Separate preprocessing
 tactic out.

---
 aarch64/aarch64_extras.v | 25 +++++++++++++++++++++++++
 lib/coq/Sail2_values.v   | 13 +++++++------
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/aarch64/aarch64_extras.v b/aarch64/aarch64_extras.v
index 7d5020ec..94851ef5 100644
--- a/aarch64/aarch64_extras.v
+++ b/aarch64/aarch64_extras.v
@@ -10,6 +10,31 @@ Axiom set_slice : forall (n : Z) (m : Z), mword n -> Z -> mword m -> mword n.
 Definition length {n} (x : mword n) := length_mword x.
 Hint Unfold length : sail.
 
+
+Lemma Replicate_lemma1 {N M O x} :
+  O * M = N ->
+  O = Z.quot N M ->
+  x = Z.quot N M -> M * x = N.
+intros. rewrite H1.
+rewrite H0 in H.
+rewrite Z.mul_comm.
+assumption.
+Qed.
+Hint Resolve Replicate_lemma1 : sail.
+
+Lemma Replicate_lemma2 {N M x} :
+ M >= 0 /\ N >= 0 ->
+ x = Z.quot N M ->
+ x >= 0.
+intros; subst.
+destruct M; destruct N; intros; try easy.
+unfold Z.quot, Z.quotrem.
+destruct (N.pos_div_eucl p0 (N.pos p)) as [x y].
+case x; easy.
+Qed.
+Hint Resolve Replicate_lemma2 : sail.
+
+
 (*
 let hexchar_to_bool_list c =
   if c = #'0' then      Just ([false;false;false;false])
diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v
index 0c806222..0ce6134f 100644
--- a/lib/coq/Sail2_values.v
+++ b/lib/coq/Sail2_values.v
@@ -921,12 +921,10 @@ Class ReasonableSize (a : Z) : Prop := {
   isPositive : a >= 0
 }.
 
-Hint Resolve -> Z.gtb_lt Z.geb_le Z.ltb_lt Z.leb_le : zbool.
-Hint Resolve <- Z.ge_le_iff Z.gt_lt_iff : zbool.
-
 (* Omega doesn't know about In, but can handle disjunctions. *)
 Ltac unfold_In :=
 repeat match goal with
+| H:context [member_Z_list _ _ = true] |- _ => rewrite member_Z_list_In in H
 | H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H
 | H:context [In ?x []] |- _ => change (In x []) with False in H
 end.
@@ -1002,7 +1000,7 @@ Ltac dump_context :=
   | H:=?X |- _ => idtac H ":=" X; fail
   | H:?X |- _ => idtac H ":" X; fail end;
   match goal with |- ?X => idtac "Goal:" X end.
-Ltac solve_arithfact :=
+Ltac prepare_for_solver :=
 (*dump_context;*)
  clear_non_Z_defns;
  extract_properties;
@@ -1012,12 +1010,15 @@ Ltac solve_arithfact :=
  autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *)
  unbool_comparisons;
  reduce_list_lengths;
- reduce_pow;
+ reduce_pow.
+Ltac solve_arithfact :=
+prepare_for_solver;
 (*dump_context;*)
  solve [apply ArithFact_mword; assumption
        | constructor; omega with Z
          (* The datatypes hints give us some list handling, esp In *)
-       | constructor; auto with datatypes zbool zarith sail].
+       | constructor; eauto with datatypes zarith sail
+       | constructor; idtac "Unable to solve constraint"; dump_context; fail].
 Hint Extern 0 (ArithFact _) => solve_arithfact : typeclass_instances.
 
 Hint Unfold length_mword : sail.
-- 
cgit v1.2.3


From 4c25326519d00bc781d6ee33ca507d1d525af686 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Fri, 20 Jul 2018 16:57:44 -0700
Subject: Add assorted comments, consistency fixes and cleanup.

---
 riscv/riscv.sail          | 647 ++++++++++++++++++++++------------------------
 riscv/riscv_mem.sail      |   8 +-
 riscv/riscv_platform.sail |  20 +-
 riscv/riscv_step.sail     |  12 +-
 riscv/riscv_sys.sail      | 125 ++++++---
 riscv/riscv_types.sail    | 260 ++++++++++---------
 riscv/riscv_vmem.sail     |  37 +--
 7 files changed, 578 insertions(+), 531 deletions(-)

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 497c5e7a..f81de3e9 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -1,3 +1,8 @@
+/* Instruction definitions.
+ *
+ * This includes decoding, execution, and assembly parsing and printing.
+ */
+
 scattered union ast
 
 val decode : bits(32) -> option(ast) effect pure
@@ -28,22 +33,23 @@ mapping encdec_uop : uop <-> bits(7) = {
 
 mapping clause encdec = UTYPE(imm, rd, op) <-> imm @ rd @ encdec_uop(op)
 
-function clause execute UTYPE(imm, rd, op) =
-    let off : xlenbits = EXTS(imm @ 0x000) in
-    let ret : xlenbits   = match op {
-      RISCV_LUI   => off,
-      RISCV_AUIPC => PC + off
-    } in {
-      X(rd) = ret;
-      true
-    }
+function clause execute UTYPE(imm, rd, op) = {
+  let off : xlenbits = EXTS(imm @ 0x000);
+  let ret : xlenbits = match op {
+    RISCV_LUI   => off,
+    RISCV_AUIPC => PC + off
+  };
+  X(rd) = ret;
+  true
+}
 
 mapping utype_mnemonic : uop <-> string = {
   RISCV_LUI   <-> "lui",
   RISCV_AUIPC <-> "auipc"
 }
 
-mapping clause assembly = UTYPE(imm, rd, op) <-> utype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_20(imm)
+mapping clause assembly = UTYPE(imm, rd, op)
+                      <-> utype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_20(imm)
 
 /* ****************************************************************** */
 union clause ast = RISCV_JAL : (bits(21), regbits)
@@ -64,11 +70,11 @@ but this is difficult
 */
 
 function clause execute (RISCV_JAL(imm, rd)) = {
-    let pc : xlenbits = PC;
-    X(rd) = nextPC;  /* compatible with JAL and C.JAL */
-    let offset : xlenbits = EXTS(imm);
-    nextPC = pc + offset;
-    true
+  let pc : xlenbits = PC;
+  X(rd) = nextPC;  /* compatible with JAL and C.JAL */
+  let offset : xlenbits = EXTS(imm);
+  nextPC = pc + offset;
+  true
 }
 
 /* TODO: handle 2-byte-alignment in mappings */
@@ -81,31 +87,32 @@ union clause ast = RISCV_JALR : (bits(12), regbits, regbits)
 mapping clause encdec = RISCV_JALR(imm, rs1, rd) <-> imm @ rs1 @ 0b000 @ rd @ 0b1100111
 
 function clause execute (RISCV_JALR(imm, rs1, rd)) = {
-    /* write rd before anything else to prevent unintended strength */
-    X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
-    let newPC : xlenbits = X(rs1) + EXTS(imm);
+  /* write rd before anything else to prevent unintended strength */
+  X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
+  let newPC : xlenbits = X(rs1) + EXTS(imm);
 /*  RMEM FIXME: For the sequential model, the above definition doesn't work directly
     if rs1 = rd.  We would effectively have to keep a regfile for reads and another for
     writes, and swap on instruction fetch.  This could perhaps be optimized in
     some manner, but for now, we just reorder the previous two lines to improve simulator
     performance in the sequential model, as below:
-    let newPC : xlenbits = X(rs1) + EXTS(imm);
-    X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
+  let newPC : xlenbits = X(rs1) + EXTS(imm);
+  X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
 */
-    nextPC = newPC[63..1] @ 0b0;
-    true
+  nextPC = newPC[63..1] @ 0b0;
+  true
 }
 
-mapping clause assembly = RISCV_JALR(imm, rs1, rd) <-> "jalr" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
+mapping clause assembly = RISCV_JALR(imm, rs1, rd)
+                      <-> "jalr" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
 /* ****************************************************************** */
 union clause ast = BTYPE : (bits(13), regbits, regbits, bop)
 
 mapping encdec_bop : bop <-> bits(3) = {
-  RISCV_BEQ <-> 0b000,
-  RISCV_BNE <-> 0b001,
-  RISCV_BLT <-> 0b100,
-  RISCV_BGE <-> 0b101,
+  RISCV_BEQ  <-> 0b000,
+  RISCV_BNE  <-> 0b001,
+  RISCV_BLT  <-> 0b100,
+  RISCV_BGE  <-> 0b101,
   RISCV_BLTU <-> 0b110,
   RISCV_BGEU <-> 0b111
 }
@@ -113,9 +120,9 @@ mapping encdec_bop : bop <-> bits(3) = {
 mapping clause encdec = BTYPE(imm7_6 @ imm5_0 @ imm7_5_0 @ imm5_4_1 @ 0b0, rs2, rs1, op)
                     <-> imm7_6 : bits(1) @ imm7_5_0 : bits(6) @ rs2 @ rs1 @ encdec_bop(op) @ imm5_4_1 : bits(4) @ imm5_0 : bits(1) @ 0b1100011
 
-function clause execute (BTYPE(imm, rs2, rs1, op)) =
-  let rs1_val = X(rs1) in
-  let rs2_val = X(rs2) in
+function clause execute (BTYPE(imm, rs2, rs1, op)) = {
+  let rs1_val = X(rs1);
+  let rs2_val = X(rs2);
   let taken : bool = match op {
     RISCV_BEQ  => rs1_val == rs2_val,
     RISCV_BNE  => rs1_val != rs2_val,
@@ -123,11 +130,10 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) =
     RISCV_BGE  => rs1_val >=_s rs2_val,
     RISCV_BLTU => rs1_val <_u rs2_val,
     RISCV_BGEU => rs1_val >=_u rs2_val
-  } in {
-    if taken then nextPC = PC + EXTS(imm);
-    true
-  }
-
+  };
+  if taken then nextPC = PC + EXTS(imm);
+  true
+}
 
 mapping btype_mnemonic : bop <-> string = {
   RISCV_BEQ  <-> "beq",
@@ -138,8 +144,8 @@ mapping btype_mnemonic : bop <-> string = {
   RISCV_BGEU <-> "bgeu"
 }
 
-mapping clause assembly = BTYPE(imm, rs2, rs1, op) <-> btype_mnemonic(op) ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_13(imm)
-
+mapping clause assembly = BTYPE(imm, rs2, rs1, op)
+                      <-> btype_mnemonic(op) ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_13(imm)
 
 /* ****************************************************************** */
 union clause ast = ITYPE : (bits(12), regbits, regbits, iop)
@@ -155,9 +161,9 @@ mapping encdec_iop : iop <-> bits(3) = {
 
 mapping clause encdec = ITYPE(imm, rs1, rd, op) <-> imm @ rs1 @ encdec_iop(op) @ rd @ 0b0010011
 
-function clause execute (ITYPE (imm, rs1, rd, op)) =
-  let rs1_val = X(rs1) in
-  let immext : xlenbits = EXTS(imm) in
+function clause execute (ITYPE (imm, rs1, rd, op)) = {
+  let rs1_val = X(rs1);
+  let immext : xlenbits = EXTS(imm);
   let result : xlenbits = match op {
     RISCV_ADDI  => rs1_val + immext,
     RISCV_SLTI  => EXTZ(rs1_val <_s immext),
@@ -165,11 +171,10 @@ function clause execute (ITYPE (imm, rs1, rd, op)) =
     RISCV_XORI  => rs1_val ^ immext,
     RISCV_ORI   => rs1_val | immext,
     RISCV_ANDI  => rs1_val & immext
-  } in {
-    X(rd) = result;
-    true
-  }
-
+  };
+  X(rd) = result;
+  true
+}
 
 mapping itype_mnemonic : iop <-> string = {
   RISCV_ADDI  <-> "addi",
@@ -180,7 +185,8 @@ mapping itype_mnemonic : iop <-> string = {
   RISCV_ANDI  <-> "andi"
 }
 
-mapping clause assembly = ITYPE(imm, rs1, rd, op) <-> itype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
+mapping clause assembly = ITYPE(imm, rs1, rd, op)
+                      <-> itype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
 /* ****************************************************************** */
 union clause ast = SHIFTIOP : (bits(6), regbits, regbits, sop)
@@ -195,17 +201,16 @@ mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ sham
 mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011
 mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011
 
-function clause execute (SHIFTIOP(shamt, rs1, rd, op)) =
-    let rs1_val = X(rs1) in
-    let result : xlenbits = match op {
-      RISCV_SLLI => rs1_val << shamt,
-      RISCV_SRLI => rs1_val >> shamt,
-      RISCV_SRAI => shift_right_arith64(rs1_val, shamt)
-    } in {
-      X(rd) = result;
-      true
-    }
-
+function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = {
+  let rs1_val = X(rs1);
+  let result : xlenbits = match op {
+    RISCV_SLLI => rs1_val << shamt,
+    RISCV_SRLI => rs1_val >> shamt,
+    RISCV_SRAI => shift_right_arith64(rs1_val, shamt)
+  };
+  X(rd) = result;
+  true
+}
 
 mapping shiftiop_mnemonic : sop <-> string = {
   RISCV_SLLI <-> "slli",
@@ -213,7 +218,8 @@ mapping shiftiop_mnemonic : sop <-> string = {
   RISCV_SRAI <-> "srai"
 }
 
-mapping clause assembly = SHIFTIOP(shamt, rs1, rd, op) <-> shiftiop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_6(shamt)
+mapping clause assembly = SHIFTIOP(shamt, rs1, rd, op)
+                      <-> shiftiop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_6(shamt)
 
 /* ****************************************************************** */
 union clause ast = RTYPE : (regbits, regbits, regbits, rop)
@@ -229,9 +235,9 @@ mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SRA)  <-> 0b0100000 @ rs2 @ rs
 mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_OR)   <-> 0b0000000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011
 mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_AND)  <-> 0b0000000 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011
 
-function clause execute (RTYPE(rs2, rs1, rd, op)) =
-  let rs1_val = X(rs1) in
-  let rs2_val = X(rs2) in
+function clause execute (RTYPE(rs2, rs1, rd, op)) = {
+  let rs1_val = X(rs1);
+  let rs2_val = X(rs2);
   let result : xlenbits = match op {
     RISCV_ADD  => rs1_val + rs2_val,
     RISCV_SUB  => rs1_val - rs2_val,
@@ -243,11 +249,10 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) =
     RISCV_SRA  => shift_right_arith64(rs1_val, rs2_val[5..0]),
     RISCV_OR   => rs1_val | rs2_val,
     RISCV_AND  => rs1_val & rs2_val
-  } in {
-    X(rd) = result;
-    true
-  }
-
+  };
+  X(rd) = result;
+  true
+}
 
 mapping rtype_mnemonic : rop <-> string = {
   RISCV_ADD  <-> "add",
@@ -262,14 +267,16 @@ mapping rtype_mnemonic : rop <-> string = {
   RISCV_AND  <-> "and"
 }
 
-mapping clause assembly = RTYPE(rs2, rs1, rd, op) <-> rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = RTYPE(rs2, rs1, rd, op)
+                      <-> rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 union clause ast = LOAD : (bits(12), regbits, regbits, bool, word_width, bool, bool)
 
 /* I am assuming that load unsigned double wasn't meant to be missing here? */
 /* TODO: aq/rl */
-mapping clause encdec = LOAD(imm, rs1, rd, is_unsigned, size, false, false) <-> imm @ rs1 @ bool_bits(is_unsigned) @ size_bits(size) @ rd @ 0b0000011
+mapping clause encdec = LOAD(imm, rs1, rd, is_unsigned, size, false, false)
+                    <-> imm @ rs1 @ bool_bits(is_unsigned) @ size_bits(size) @ rd @ 0b0000011
 
 val extend_value : forall 'n, 0 < 'n <= 8. (bool, MemoryOpResult(bits(8 * 'n))) -> MemoryOpResult(xlenbits)
 function extend_value(is_unsigned, value) = match (value) {
@@ -285,7 +292,7 @@ function process_load(rd, addr, value, is_unsigned) =
   }
 
 function check_misaligned(vaddr : xlenbits, width : word_width) -> bool =
-  if plat_enable_misaligned_access() then false
+  if   plat_enable_misaligned_access() then false
   else match width {
          BYTE   => false,
          HALF   => vaddr[0] == true,
@@ -294,20 +301,19 @@ function check_misaligned(vaddr : xlenbits, width : word_width) -> bool =
        }
 
 function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) =
-    let vaddr : xlenbits = X(rs1) + EXTS(imm) in
-    if check_misaligned(vaddr, width)
-    then { handle_mem_exception(vaddr, E_Load_Addr_Align); false }
-    else match translateAddr(vaddr, Read, Data) {
-      TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
-      TR_Address(addr) =>
-        match width {
-          BYTE   => process_load(rd, vaddr, mem_read(addr, 1, aq, rl, false), is_unsigned),
-          HALF   => process_load(rd, vaddr, mem_read(addr, 2, aq, rl, false), is_unsigned),
-          WORD   => process_load(rd, vaddr, mem_read(addr, 4, aq, rl, false), is_unsigned),
-          DOUBLE => process_load(rd, vaddr, mem_read(addr, 8, aq, rl, false), is_unsigned)
-        }
-    }
-
+  let vaddr : xlenbits = X(rs1) + EXTS(imm) in
+  if   check_misaligned(vaddr, width)
+  then { handle_mem_exception(vaddr, E_Load_Addr_Align); false }
+  else match translateAddr(vaddr, Read, Data) {
+    TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
+    TR_Address(addr) =>
+      match width {
+        BYTE   => process_load(rd, vaddr, mem_read(addr, 1, aq, rl, false), is_unsigned),
+        HALF   => process_load(rd, vaddr, mem_read(addr, 2, aq, rl, false), is_unsigned),
+        WORD   => process_load(rd, vaddr, mem_read(addr, 4, aq, rl, false), is_unsigned),
+        DOUBLE => process_load(rd, vaddr, mem_read(addr, 8, aq, rl, false), is_unsigned)
+      }
+  }
 
 /* TODO FIXME: is this the actual aq/rl syntax? */
 val maybe_aq : bool <-> string
@@ -329,50 +335,53 @@ mapping maybe_u = {
 }
 
 
-mapping clause assembly = LOAD(imm, rs1, rd, is_unsigned, size, aq, rl) <-> "l" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
+mapping clause assembly = LOAD(imm, rs1, rd, is_unsigned, size, aq, rl)
+                      <-> "l" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
 /* ****************************************************************** */
 union clause ast = STORE : (bits(12), regbits, regbits, word_width, bool, bool)
 
 /* TODO: aq/rl */
-mapping clause encdec = STORE(imm7 @ imm5, rs2, rs1, size, false, false) <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ imm5 : bits(5) @ 0b0100011
+mapping clause encdec = STORE(imm7 @ imm5, rs2, rs1, size, false, false)
+                    <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ imm5 : bits(5) @ 0b0100011
 
 /* NOTE: Currently, we only EA if address translation is successful.
    This may need revisiting. */
 function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) =
-    let vaddr : xlenbits = X(rs1) + EXTS(imm) in
-    if check_misaligned(vaddr, width)
-    then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false }
-    else match translateAddr(vaddr, Write, Data) {
-      TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
-      TR_Address(addr) =>
-        let eares : MemoryOpResult(unit) = match width {
-          BYTE   => mem_write_ea(addr, 1, aq, rl, false),
-          HALF   => mem_write_ea(addr, 2, aq, rl, false),
-          WORD   => mem_write_ea(addr, 4, aq, rl, false),
-          DOUBLE => mem_write_ea(addr, 8, aq, rl, false)
-        } in
-        match (eares) {
-          MemException(e) => { handle_mem_exception(addr, e); false },
-          MemValue(_) => {
-            let rs2_val = X(rs2) in
-            let res : MemoryOpResult(bool) = match width {
-              BYTE   => mem_write_value(addr, 1, rs2_val[7..0],  aq, rl, false),
-              HALF   => mem_write_value(addr, 2, rs2_val[15..0], aq, rl, false),
-              WORD   => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, false),
-              DOUBLE => mem_write_value(addr, 8, rs2_val,        aq, rl, false)
-            } in
-            match (res) {
-              MemValue(true)     => true,
-              MemValue(false)    => internal_error("store got false from mem_write_value"),
-              MemException(e) => { handle_mem_exception(addr, e); false }
-            }
+  let vaddr : xlenbits = X(rs1) + EXTS(imm) in
+  if   check_misaligned(vaddr, width)
+  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false }
+  else match translateAddr(vaddr, Write, Data) {
+    TR_Failure(e) => { handle_mem_exception(vaddr, e); false },
+    TR_Address(addr) => {
+      let eares : MemoryOpResult(unit) = match width {
+        BYTE   => mem_write_ea(addr, 1, aq, rl, false),
+        HALF   => mem_write_ea(addr, 2, aq, rl, false),
+        WORD   => mem_write_ea(addr, 4, aq, rl, false),
+        DOUBLE => mem_write_ea(addr, 8, aq, rl, false)
+      };
+      match (eares) {
+        MemException(e) => { handle_mem_exception(addr, e); false },
+        MemValue(_) => {
+          let rs2_val = X(rs2);
+          let res : MemoryOpResult(bool) = match width {
+            BYTE   => mem_write_value(addr, 1, rs2_val[7..0],  aq, rl, false),
+            HALF   => mem_write_value(addr, 2, rs2_val[15..0], aq, rl, false),
+            WORD   => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, false),
+            DOUBLE => mem_write_value(addr, 8, rs2_val,        aq, rl, false)
+          };
+          match (res) {
+            MemValue(true)     => true,
+            MemValue(false)    => internal_error("store got false from mem_write_value"),
+            MemException(e) => { handle_mem_exception(addr, e); false }
           }
         }
+      }
     }
+  }
 
-
-mapping clause assembly = STORE(imm, rs1, rd, size, aq, rl) <-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
+mapping clause assembly = STORE(imm, rs1, rd, size, aq, rl)
+                      <-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
 
 
 /* ****************************************************************** */
@@ -396,17 +405,16 @@ mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SLLI) <-> 0b0000000 @ shamt
 mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SRLI) <-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
 mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SRAI) <-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
 
-function clause execute (SHIFTW(shamt, rs1, rd, op)) =
-    let rs1_val = (X(rs1))[31..0] in
-    let result : bits(32) = match op {
-      RISCV_SLLI => rs1_val << shamt,
-      RISCV_SRLI => rs1_val >> shamt,
-      RISCV_SRAI => shift_right_arith32(rs1_val, shamt)
-    } in {
-      X(rd) = EXTS(result);
-      true
-    }
-
+function clause execute (SHIFTW(shamt, rs1, rd, op)) = {
+  let rs1_val = (X(rs1))[31..0];
+  let result : bits(32) = match op {
+    RISCV_SLLI => rs1_val << shamt,
+    RISCV_SRLI => rs1_val >> shamt,
+    RISCV_SRAI => shift_right_arith32(rs1_val, shamt)
+  };
+  X(rd) = EXTS(result);
+  true
+}
 
 mapping shiftw_mnemonic : sop <-> string = {
   RISCV_SLLI <-> "slli",
@@ -414,7 +422,8 @@ mapping shiftw_mnemonic : sop <-> string = {
   RISCV_SRAI <-> "srai"
 }
 
-mapping clause assembly = SHIFTW(shamt, rs1, rd, op) <-> shiftw_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)
+mapping clause assembly = SHIFTW(shamt, rs1, rd, op)
+                      <-> shiftw_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)
 
 /* ****************************************************************** */
 union clause ast = RTYPEW : (regbits, regbits, regbits, ropw)
@@ -425,20 +434,19 @@ mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SLLW) <-> 0b0000000 @ rs2 @ r
 mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRLW) <-> 0b0000000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011
 mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRAW) <-> 0b0100000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011
 
-function clause execute (RTYPEW(rs2, rs1, rd, op)) =
-  let rs1_val = (X(rs1))[31..0] in
-  let rs2_val = (X(rs2))[31..0] in
+function clause execute (RTYPEW(rs2, rs1, rd, op)) = {
+  let rs1_val = (X(rs1))[31..0];
+  let rs2_val = (X(rs2))[31..0];
   let result : bits(32) = match op {
     RISCV_ADDW => rs1_val + rs2_val,
     RISCV_SUBW => rs1_val - rs2_val,
     RISCV_SLLW => rs1_val << (rs2_val[4..0]),
     RISCV_SRLW => rs1_val >> (rs2_val[4..0]),
     RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0])
-  } in {
-    X(rd) = EXTS(result);
-    true
-  }
-
+  };
+  X(rd) = EXTS(result);
+  true
+}
 
 mapping rtypew_mnemonic : ropw <-> string = {
   RISCV_ADDW <-> "addw",
@@ -448,7 +456,8 @@ mapping rtypew_mnemonic : ropw <-> string = {
   RISCV_SRAW <-> "sraw"
 }
 
-mapping clause assembly = RTYPEW(rs2, rs1, rd, op) <-> rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = RTYPEW(rs2, rs1, rd, op)
+                      <-> rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 /* FIXME: separate these out into separate ast variants */
@@ -462,18 +471,19 @@ mapping encdec_mul_op : (bool, bool, bool) <-> bits(3) = {
 }
 
 /* for some reason the : bits(3) here is still necessary - BUG */
-mapping clause encdec = MUL(rs2, rs1, rd, high, signed1, signed2) <-> 0b0000001 @ rs2 @ rs1 @ encdec_mul_op(high, signed1, signed2) : bits(3) @ rd @ 0b0110011
-
-function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) =
-  let rs1_val = X(rs1) in
-  let rs2_val = X(rs2) in
-  let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val) in
-  let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val) in
-  let result128 = to_bits(128, rs1_int * rs2_int) in
-  let result = if high then result128[127..64] else result128[63..0] in {
-    X(rd) = result;
-    true
-  }
+mapping clause encdec = MUL(rs2, rs1, rd, high, signed1, signed2)
+                    <-> 0b0000001 @ rs2 @ rs1 @ encdec_mul_op(high, signed1, signed2) : bits(3) @ rd @ 0b0110011
+
+function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) = {
+  let rs1_val = X(rs1);
+  let rs2_val = X(rs2);
+  let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val);
+  let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val);
+  let result128 = to_bits(128, rs1_int * rs2_int);
+  let result = if high then result128[127..64] else result128[63..0];
+  X(rd) = result;
+  true
+}
 
 mapping mul_mnemonic : (bool, bool, bool) <-> string = {
   (false, true, true)  <-> "mul",
@@ -489,40 +499,40 @@ union clause ast = DIV : (regbits, regbits, regbits, bool)
 
 mapping clause encdec = DIV(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0110011
 
-function clause execute (DIV(rs2, rs1, rd, s)) =
-  let rs1_val = X(rs1) in
-  let rs2_val = X(rs2) in
-  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in
-  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in
-  let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int) in
-  let q': int = if s & q > xlen_max_signed then xlen_min_signed else q in /* check for signed overflow */ {
-    X(rd) = to_bits(xlen, q');
-    true
-  }
-
+function clause execute (DIV(rs2, rs1, rd, s)) = {
+  let rs1_val = X(rs1);
+  let rs2_val = X(rs2);
+  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);
+  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);
+  let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);
+  let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; /* check for signed overflow */
+  X(rd) = to_bits(xlen, q');
+  true
+}
 
 mapping maybe_not_u : bool <-> string = {
   false <-> "u",
-  true <-> ""
+  true  <-> ""
 }
 
-mapping clause assembly = DIV(rs2, rs1, rd, s) <-> "div" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = DIV(rs2, rs1, rd, s)
+                      <-> "div" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 union clause ast = REM : (regbits, regbits, regbits, bool)
 
 mapping clause encdec = REM(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0110011
 
-function clause execute (REM(rs2, rs1, rd, s)) =
-  let rs1_val = X(rs1) in
-  let rs2_val = X(rs2) in
-  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in
-  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in
-  let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int) in {
+function clause execute (REM(rs2, rs1, rd, s)) = {
+  let rs1_val = X(rs1);
+  let rs2_val = X(rs2);
+  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);
+  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);
+  let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int);
   /* signed overflow case returns zero naturally as required due to -1 divisor */
-    X(rd) = to_bits(xlen, r);
-    true
-  }
+  X(rd) = to_bits(xlen, r);
+  true
+}
 
 mapping clause assembly = REM(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
@@ -531,55 +541,54 @@ union clause ast = MULW : (regbits, regbits, regbits)
 
 mapping clause encdec = MULW(rs2, rs1, rd) <-> 0b0000001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011
 
-function clause execute (MULW(rs2, rs1, rd)) =
-  let rs1_val = X(rs1)[31..0] in
-  let rs2_val = X(rs2)[31..0] in
-  let rs1_int : int = signed(rs1_val) in
-  let rs2_int : int = signed(rs2_val) in
-  let result32 = to_bits(64, rs1_int * rs2_int)[31..0] in /* XXX surprising behaviour of to_bits requires exapnsion to 64 bits followed by truncation... */
-  let result : xlenbits = EXTS(result32) in {
-    X(rd) = result;
-    true
-  }
-
+function clause execute (MULW(rs2, rs1, rd)) = {
+  let rs1_val = X(rs1)[31..0];
+  let rs2_val = X(rs2)[31..0];
+  let rs1_int : int = signed(rs1_val);
+  let rs2_int : int = signed(rs2_val);
+  let result32 = to_bits(64, rs1_int * rs2_int)[31..0]; /* XXX surprising behaviour of to_bits requires expansion to 64 bits followed by truncation... */
+  let result : xlenbits = EXTS(result32);
+  X(rd) = result;
+  true
+}
 
-mapping clause assembly = MULW(rs2, rs1, rd) <->  "mulw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = MULW(rs2, rs1, rd)
+                      <-> "mulw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 union clause ast = DIVW : (regbits, regbits, regbits, bool)
 
 mapping clause encdec = DIVW(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0111011
 
-function clause execute (DIVW(rs2, rs1, rd, s)) =
-  let rs1_val = X(rs1)[31..0] in
-  let rs2_val = X(rs2)[31..0] in
-  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in
-  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in
-  let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int) in
-  let q': int = if s & q > (2 ^ 31 - 1) then  (0 - 2^31) else q in /* check for signed overflow */ {
-    X(rd) = EXTS(to_bits(32, q'));
-    true
-  }
-
+function clause execute (DIVW(rs2, rs1, rd, s)) = {
+  let rs1_val = X(rs1)[31..0];
+  let rs2_val = X(rs2)[31..0];
+  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);
+  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);
+  let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);
+  let q': int = if s & q > (2 ^ 31 - 1) then  (0 - 2^31) else q; /* check for signed overflow */
+  X(rd) = EXTS(to_bits(32, q'));
+  true
+}
 
-mapping clause assembly = DIVW(rs2, rs1, rd, s) <-> "div" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = DIVW(rs2, rs1, rd, s)
+                      <-> "div" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 union clause ast = REMW : (regbits, regbits, regbits, bool)
 
 mapping clause encdec = REMW(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0111011
 
-function clause execute (REMW(rs2, rs1, rd, s)) =
-  let rs1_val = X(rs1)[31..0] in
-  let rs2_val = X(rs2)[31..0] in
-  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in
-  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in
-  let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int) in {
-    /* signed overflow case returns zero naturally as required due to -1 divisor */
-    X(rd) = EXTS(to_bits(32, r));
-    true
-  }
-
+function clause execute (REMW(rs2, rs1, rd, s)) = {
+  let rs1_val = X(rs1)[31..0];
+  let rs2_val = X(rs2)[31..0];
+  let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);
+  let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);
+  let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int);
+  /* signed overflow case returns zero naturally as required due to -1 divisor */
+  X(rd) = EXTS(to_bits(32, r));
+  true
+}
 
 mapping clause assembly = REMW(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
@@ -650,18 +659,17 @@ union clause ast = ECALL : unit
 
 mapping clause encdec = ECALL() <-> 0b000000000000 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011
 
-function clause execute ECALL() =
+function clause execute ECALL() = {
   let t : sync_exception =
     struct { trap = match (cur_privilege) {
-                      User => E_U_EnvCall,
+                      User       => E_U_EnvCall,
                       Supervisor => E_S_EnvCall,
-                      Machine => E_M_EnvCall
+                      Machine    => E_M_EnvCall
                     },
-             excinfo = (None() : option(xlenbits)) } in {
-    nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC);
-    false
-  }
-
+             excinfo = (None() : option(xlenbits)) };
+  nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC);
+  false
+}
 
 mapping clause assembly = ECALL() <-> "ecall"
 
@@ -671,10 +679,9 @@ union clause ast = MRET : unit
 mapping clause encdec = MRET() <-> 0b0011000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011
 
 function clause execute MRET() = {
-  if cur_privilege == Machine then
-    nextPC = handle_exception(cur_privilege, CTL_MRET(), PC)
-  else
-    handle_illegal();
+  if   cur_privilege == Machine
+  then nextPC = handle_exception(cur_privilege, CTL_MRET(), PC)
+  else handle_illegal();
   false
 }
 
@@ -688,7 +695,7 @@ mapping clause encdec = SRET() <-> 0b0001000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b000
 function clause execute SRET() = {
   match cur_privilege {
     User       => handle_illegal(),
-    Supervisor => if mstatus.TSR() == true
+    Supervisor => if   mstatus.TSR() == true
                   then handle_illegal()
                   else nextPC = handle_exception(cur_privilege, CTL_SRET(), PC),
     Machine    => nextPC = handle_exception(cur_privilege, CTL_SRET(), PC)
@@ -718,7 +725,7 @@ mapping clause encdec = WFI() <-> 0b000100000101 @ 0b00000 @ 0b000 @ 0b00000 @ 0
 function clause execute WFI() =
   match cur_privilege {
     Machine    => true,
-    Supervisor => if mstatus.TW() == true
+    Supervisor => if   mstatus.TW() == true
                   then { handle_illegal(); false }
                   else true,
     User       => { handle_illegal(); false }
@@ -733,7 +740,8 @@ mapping clause encdec = SFENCE_VMA(rs1, rs2) <-> 0b0001001 @ rs2 @ rs1 @ 0b000 @
 
 function clause execute SFENCE_VMA(rs1, rs2) = {
   /* TODO: handle PMP/TLB synchronization when executed in M-mode. */
-  if cur_privilege == User then { handle_illegal(); false }
+  if   cur_privilege == User
+  then { handle_illegal(); false }
   else match (architecture(mstatus.SXL()), mstatus.TVM()) {
     (Some(RV64), true)  => { handle_illegal(); false },
     (Some(RV64), false) => {
@@ -746,7 +754,8 @@ function clause execute SFENCE_VMA(rs1, rs2) = {
   }
 }
 
-mapping clause assembly = SFENCE_VMA(rs1, rs2) <-> "sfence.vma" ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = SFENCE_VMA(rs1, rs2)
+                      <-> "sfence.vma" ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 // Some print utils for lr/sc.
@@ -813,12 +822,14 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) =
            }
        }
 
-mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) <-> "lr." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)
+mapping clause assembly = LOADRES(aq, rl, rs1, size, rd)
+                      <-> "lr." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)
 
 /* ****************************************************************** */
 union clause ast = STORECON : (bool, bool, regbits, regbits, word_width, regbits)
 
-mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111
+mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd)
+                    <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111
 
 /* NOTE: Currently, we only EA if address translation is successful.
    This may need revisiting. */
@@ -844,7 +855,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
   if (~ (aligned))
   then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false }
   else {
-    if match_reservation(vaddr) == false
+    if   match_reservation(vaddr) == false
     then { X(rd) = EXTZ(0b1); true }
     else {
       match translateAddr(vaddr, Write, Data) {
@@ -867,7 +878,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
               match (res) {
                 MemValue(true)     => { X(rd) = EXTZ(0b0); cancel_reservation(); true },
                 MemValue(false)    => { X(rd) = EXTZ(0b1); cancel_reservation(); true },
-                MemException(e) => { handle_mem_exception(addr, e); false }
+                MemException(e)    => { handle_mem_exception(addr, e); false }
               }
             }
           }
@@ -917,10 +928,10 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
           _        => internal_error ("AMO expected WORD or DOUBLE")
           };
           match (rval) {
-            MemException(e) => { handle_mem_exception(addr, e); false },
+            MemException(e)  => { handle_mem_exception(addr, e); false },
             MemValue(loaded) => {
               rs2_val : xlenbits = X(rs2);
-              result : xlenbits =
+              result  : xlenbits =
                 match op {
                   AMOSWAP => rs2_val,
                   AMOADD  => rs2_val + loaded,
@@ -941,7 +952,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
                 _      => internal_error("AMO expected WORD or DOUBLE")
               };
               match (wval) {
-                MemValue(true) => { X(rd) = loaded; true },
+                MemValue(true)  => { X(rd) = loaded; true },
                 MemValue(false) => { internal_error("AMO got false from mem_write_value") },
                 MemException(e) => { handle_mem_exception(addr, e); false }
               }
@@ -966,7 +977,8 @@ mapping amo_mnemonic : amoop <-> string = {
   AMOMAXU <-> "amomaxu"
 }
 
-mapping clause assembly = AMO(op, aq, rl, rs2, rs1, width, rd) <-> amo_mnemonic(op) ^ "." ^ size_mnemonic(width) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
+mapping clause assembly = AMO(op, aq, rl, rs2, rs1, width, rd)
+                      <-> amo_mnemonic(op) ^ "." ^ size_mnemonic(width) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
 union clause ast = CSR  : (bits(12), regbits, regbits, bool, csrop)
@@ -1121,10 +1133,10 @@ mapping clause assembly = CSR(csr, rs1, rd, false, op) <-> csr_mnemonic(op) ^ sp
 /* ****************************************************************** */
 union clause ast = NOP : unit
 
-function clause decodeCompressed (0b000 @ nzi1 : bits(1) @ 0b00000 @ (nzi0 : bits(5)) @ 0b01) : bits(16) = {
-  if (nzi1 == 0b0) & (nzi0 == 0b00000) then Some(NOP())
+function clause decodeCompressed (0b000 @ nzi1 : bits(1) @ 0b00000 @ (nzi0 : bits(5)) @ 0b01) : bits(16) =
+  if   (nzi1 == 0b0) & (nzi0 == 0b00000)
+  then Some(NOP())
   else None()
-}
 
 function clause execute NOP() = true
 
@@ -1135,17 +1147,16 @@ function clause print_insn (NOP()) =
 
 union clause ast = C_ADDI4SPN : (cregbits, bits(8))
 
-function clause decodeCompressed (0b000 @ nz54 : bits(2) @ nz96 : bits(4) @ nz2 : bits(1) @ nz3 : bits(1) @ rd : cregbits @ 0b00) : bits(16) = {
-  let nzimm = (nz96 @ nz54 @ nz3 @ nz2) : bits(8) in
-  if nzimm == 0b00000000 then None()
+function clause decodeCompressed (0b000 @ nz54 : bits(2) @ nz96 : bits(4) @ nz2 : bits(1) @ nz3 : bits(1) @ rd : cregbits @ 0b00) : bits(16) =
+  let  nzimm = (nz96 @ nz54 @ nz3 @ nz2) : bits(8) in
+  if   nzimm == 0b00000000
+  then None()
   else Some(C_ADDI4SPN(rd, nzimm))
-}
 
-function clause execute (C_ADDI4SPN(rdc, nzimm)) = {
+function clause execute (C_ADDI4SPN(rdc, nzimm)) =
   let imm : bits(12) = (0b00 @ nzimm @ 0b00) in
   let rd = creg2reg_bits(rdc) in
   execute(ITYPE(imm, sp, rd, RISCV_ADDI))
-}
 
 function clause print_insn (C_ADDI4SPN(rdc, nzimm)) =
   "c.addi4spn " ^ creg2reg_bits(rdc) ^ ", " ^ BitStr(nzimm)
@@ -1153,17 +1164,15 @@ function clause print_insn (C_ADDI4SPN(rdc, nzimm)) =
 /* ****************************************************************** */
 union clause ast = C_LW : (bits(5), cregbits, cregbits)
 
-function clause decodeCompressed (0b010 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregbits @ 0b00) : bits(16) = {
+function clause decodeCompressed (0b010 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregbits @ 0b00) : bits(16) =
   let uimm = (ui6 @ ui53 @ ui2) : bits(5) in
   Some(C_LW(uimm, rs1, rd))
-}
 
-function clause execute (C_LW(uimm, rsc, rdc)) = {
+function clause execute (C_LW(uimm, rsc, rdc)) =
   let imm : bits(12) = EXTZ(uimm @ 0b00) in
   let rd = creg2reg_bits(rdc) in
   let rs = creg2reg_bits(rsc) in
   execute(LOAD(imm, rs, rd, false, WORD, false, false))
-}
 
 function clause print_insn (C_LW(uimm, rsc, rdc)) =
   "c.lw   " ^ creg2reg_bits(rdc) ^ ", " ^ creg2reg_bits(rsc) ^ ", " ^ BitStr(uimm)
@@ -1171,17 +1180,15 @@ function clause print_insn (C_LW(uimm, rsc, rdc)) =
 /* ****************************************************************** */
 union clause ast = C_LD : (bits(5), cregbits, cregbits)
 
-function clause decodeCompressed (0b011 @ ui53 : bits(3) @ rs1 : cregbits @ ui76 : bits(2) @ rd : cregbits @ 0b00) : bits(16) = {
+function clause decodeCompressed (0b011 @ ui53 : bits(3) @ rs1 : cregbits @ ui76 : bits(2) @ rd : cregbits @ 0b00) : bits(16) =
   let uimm = (ui76 @ ui53) : bits(5) in
   Some(C_LD(uimm, rs1, rd))
-}
 
-function clause execute (C_LD(uimm, rsc, rdc)) = {
+function clause execute (C_LD(uimm, rsc, rdc)) =
   let imm : bits(12) = EXTZ(uimm @ 0b000) in
   let rd = creg2reg_bits(rdc) in
   let rs = creg2reg_bits(rsc) in
   execute(LOAD(imm, rs, rd, false, DOUBLE, false, false))
-}
 
 function clause print_insn (C_LD(uimm, rsc, rdc)) =
   "c.ld   " ^ creg2reg_bits(rdc) ^ ", " ^ creg2reg_bits(rsc) ^ ", " ^ BitStr(uimm)
@@ -1189,17 +1196,15 @@ function clause print_insn (C_LD(uimm, rsc, rdc)) =
 /* ****************************************************************** */
 union clause ast = C_SW : (bits(5), cregbits, cregbits)
 
-function clause decodeCompressed (0b110 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregbits @ 0b00) : bits(16) = {
+function clause decodeCompressed (0b110 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregbits @ 0b00) : bits(16) =
   let uimm = (ui6 @ ui53 @ ui2) : bits(5) in
   Some(C_SW(uimm, rs1, rs2))
-}
 
-function clause execute (C_SW(uimm, rsc1, rsc2)) = {
+function clause execute (C_SW(uimm, rsc1, rsc2)) =
   let imm : bits(12) = EXTZ(uimm @ 0b00) in
   let rs1 = creg2reg_bits(rsc1) in
   let rs2 = creg2reg_bits(rsc2) in
   execute(STORE(imm, rs2, rs1, WORD, false, false))
-}
 
 function clause print_insn (C_SW(uimm, rsc1, rsc2)) =
   "c.sw   " ^ creg2reg_bits(rsc1) ^ ", " ^ creg2reg_bits(rsc2) ^ ", " ^ BitStr(uimm)
@@ -1207,17 +1212,15 @@ function clause print_insn (C_SW(uimm, rsc1, rsc2)) =
 /* ****************************************************************** */
 union clause ast = C_SD : (bits(5), cregbits, cregbits)
 
-function clause decodeCompressed (0b111 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00): bits(16) = {
+function clause decodeCompressed (0b111 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00): bits(16) =
   let uimm = (ui76 @ ui53) : bits(5) in
   Some(C_SD(uimm, rs1, rs2))
-}
 
-function clause execute (C_SD(uimm, rsc1, rsc2)) = {
+function clause execute (C_SD(uimm, rsc1, rsc2)) =
   let imm : bits(12) = EXTZ(uimm @ 0b000) in
   let rs1 = creg2reg_bits(rsc1) in
   let rs2 = creg2reg_bits(rsc2) in
   execute(STORE(imm, rs2, rs1, DOUBLE, false, false))
-}
 
 function clause print_insn (C_SD(uimm, rsc1, rsc2)) =
   "c.sd   " ^ creg2reg_bits(rsc1) ^ ", " ^ creg2reg_bits(rsc2) ^ ", " ^ BitStr(uimm)
@@ -1225,16 +1228,14 @@ function clause print_insn (C_SD(uimm, rsc1, rsc2)) =
 /* ****************************************************************** */
 union clause ast = C_ADDI : (bits(6), regbits)
 
-function clause decodeCompressed (0b000 @ nzi5 : bits(1) @ rsd : regbits @ nzi40 : bits(5) @ 0b01) : bits(16) = {
+function clause decodeCompressed (0b000 @ nzi5 : bits(1) @ rsd : regbits @ nzi40 : bits(5) @ 0b01) : bits(16) =
   let nzi = (nzi5 @ nzi40) : bits(6) in
   if (nzi == 0b000000) | (rsd == zreg) then None()
   else Some(C_ADDI(nzi, rsd))
-}
 
-function clause execute (C_ADDI(nzi, rsd)) = {
+function clause execute (C_ADDI(nzi, rsd)) =
   let imm : bits(12) = EXTS(nzi) in
   execute(ITYPE(imm, rsd, rsd, RISCV_ADDI))
-}
 
 function clause print_insn (C_ADDI(nzi, rsd)) =
   "c.addi   " ^ rsd ^ ", " ^ BitStr(nzi)
@@ -1249,9 +1250,8 @@ union clause ast = C_ADDIW : (bits(6), regbits)
 function clause decodeCompressed (0b001 @ imm5 : bits(1) @ rsd : regbits @ imm40 : bits(5) @ 0b01) =
   Some (C_ADDIW((imm5 @ imm40), rsd))
 
-function clause execute (C_JAL(imm)) = {
+function clause execute (C_JAL(imm)) =
   execute(RISCV_JAL(EXTS(imm @ 0b0), ra))
-}
 
 function clause execute (C_ADDIW(imm, rsd)) = {
   let imm : bits(32) = EXTS(imm);
@@ -1270,15 +1270,14 @@ function clause print_insn (C_ADDIW(imm, rsd)) =
 /* ****************************************************************** */
 union clause ast = C_LI : (bits(6), regbits)
 
-function clause decodeCompressed (0b010 @ imm5 : bits(1) @ rd : regbits @ imm40 : bits(5) @ 0b01) = {
-  if (rd == zreg) then None()
+function clause decodeCompressed (0b010 @ imm5 : bits(1) @ rd : regbits @ imm40 : bits(5) @ 0b01) =
+  if   rd == zreg
+  then None()
   else Some(C_LI(imm5 @ imm40, rd))
-}
 
-function clause execute (C_LI(imm, rd)) = {
+function clause execute (C_LI(imm, rd)) =
   let imm : bits(12) = EXTS(imm) in
   execute(ITYPE(imm, zreg, rd, RISCV_ADDI))
-}
 
 function clause print_insn (C_LI(imm, rd)) =
   "c.li  " ^ rd ^ ", " ^ BitStr(imm)
@@ -1286,16 +1285,15 @@ function clause print_insn (C_LI(imm, rd)) =
 /* ****************************************************************** */
 union clause ast = C_ADDI16SP : (bits(6))
 
-function clause decodeCompressed (0b011 @ nzi9 : bits(1) @ /* x2 */ 0b00010 @ nzi4 : bits(1) @ nzi6 : bits(1) @ nzi87 : bits(2) @ nzi5 : bits(1) @ 0b01) = {
-  let nzimm = nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 in
-  if (nzimm == 0b000000) then None()
+function clause decodeCompressed (0b011 @ nzi9 : bits(1) @ /* x2 */ 0b00010 @ nzi4 : bits(1) @ nzi6 : bits(1) @ nzi87 : bits(2) @ nzi5 : bits(1) @ 0b01) =
+  let  nzimm = nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 in
+  if   nzimm == 0b000000
+  then None()
   else Some(C_ADDI16SP(nzimm))
-}
 
-function clause execute (C_ADDI16SP(imm)) = {
+function clause execute (C_ADDI16SP(imm)) =
   let imm : bits(12) = EXTS(imm @ 0x0) in
   execute(ITYPE(imm, sp, sp, RISCV_ADDI))
-}
 
 function clause print_insn (C_ADDI16SP(imm)) =
   "c.addi16sp  " ^ BitStr(imm)
@@ -1303,15 +1301,14 @@ function clause print_insn (C_ADDI16SP(imm)) =
 /* ****************************************************************** */
 union clause ast = C_LUI : (bits(6), regbits)
 
-function clause decodeCompressed (0b011 @ imm17 : bits(1) @ rd : regbits @ imm1612 : bits(5) @ 0b01) = {
-  if (rd == zreg) | (rd == sp) then None()
+function clause decodeCompressed (0b011 @ imm17 : bits(1) @ rd : regbits @ imm1612 : bits(5) @ 0b01) =
+  if   (rd == zreg) | (rd == sp)
+  then None()
   else Some(C_LUI(imm17 @ imm1612, rd))
-}
 
-function clause execute (C_LUI(imm, rd)) = {
+function clause execute (C_LUI(imm, rd)) =
   let res : bits(20) = EXTS(imm) in
   execute(UTYPE(res, rd, RISCV_LUI))
-}
 
 function clause print_insn (C_LUI(imm, rd)) =
   "c.lui  " ^ rd ^ ", " ^ BitStr(imm)
@@ -1319,17 +1316,15 @@ function clause print_insn (C_LUI(imm, rd)) =
 /* ****************************************************************** */
 union clause ast = C_SRLI : (bits(6), cregbits)
 
-function clause decodeCompressed (0b100 @ nzui5 : bits(1) @ 0b00 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01) = {
-  let shamt : bits(6) = nzui5 @ nzui40 in
-  if shamt == 0b000000 /* TODO: On RV32, also need shamt[5] == 0 */
+function clause decodeCompressed (0b100 @ nzui5 : bits(1) @ 0b00 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01) =
+  let  shamt : bits(6) = nzui5 @ nzui40 in
+  if   shamt == 0b000000 /* TODO: On RV32, also need shamt[5] == 0 */
   then None()
   else Some(C_SRLI(shamt, rsd))
-}
 
-function clause execute (C_SRLI(shamt, rsd)) = {
+function clause execute (C_SRLI(shamt, rsd)) =
   let rsd = creg2reg_bits(rsd)  in
   execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRLI))
-}
 
 function clause print_insn (C_SRLI(shamt, rsd)) =
   "c.srli  " ^ creg2reg_bits(rsd) ^ ", " ^ BitStr(shamt)
@@ -1337,17 +1332,15 @@ function clause print_insn (C_SRLI(shamt, rsd)) =
 /* ****************************************************************** */
 union clause ast = C_SRAI : (bits(6), cregbits)
 
-function clause decodeCompressed (0b100 @ nzui5 : bits(1) @ 0b01 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01) = {
-  let shamt : bits(6) = nzui5 @ nzui40 in
-  if shamt == 0b000000 /* TODO: On RV32, also need shamt[5] == 0 */
+function clause decodeCompressed (0b100 @ nzui5 : bits(1) @ 0b01 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01) =
+  let  shamt : bits(6) = nzui5 @ nzui40 in
+  if   shamt == 0b000000 /* TODO: On RV32, also need shamt[5] == 0 */
   then None()
   else Some(C_SRAI(shamt, rsd))
-}
 
-function clause execute (C_SRAI(shamt, rsd)) = {
+function clause execute (C_SRAI(shamt, rsd)) =
   let rsd = creg2reg_bits(rsd)  in
   execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRAI))
-}
 
 function clause print_insn (C_SRAI(shamt, rsd)) =
   "c.srai  " ^ creg2reg_bits(rsd) ^ ", " ^ BitStr(shamt)
@@ -1357,10 +1350,9 @@ union clause ast = C_ANDI : (bits(6), cregbits)
 
 function clause decodeCompressed (0b100 @ i5 : bits(1) @ 0b10 @ rsd : cregbits @ i40 : bits(5) @ 0b01) = Some(C_ANDI(i5 @ i40, rsd))
 
-function clause execute (C_ANDI(imm, rsd)) = {
+function clause execute (C_ANDI(imm, rsd)) =
   let rsd = creg2reg_bits(rsd) in
   execute(ITYPE(EXTS(imm), rsd, rsd, RISCV_ANDI))
-}
 
 function clause print_insn (C_ANDI(imm, rsd)) =
   "c.andi  " ^ creg2reg_bits(rsd) ^ ", " ^ BitStr(imm)
@@ -1370,11 +1362,10 @@ union clause ast = C_SUB : (cregbits, cregbits)
 
 function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b00 @ rs2 : cregbits @ 0b01) = Some(C_SUB(rsd, rs2))
 
-function clause execute (C_SUB(rsd, rs2)) = {
+function clause execute (C_SUB(rsd, rs2)) =
   let rsd = creg2reg_bits(rsd) in
   let rs2 = creg2reg_bits(rs2) in
   execute(RTYPE(rs2, rsd, rsd, RISCV_SUB))
-}
 
 function clause print_insn (C_SUB(rsd, rs2)) =
   "c.sub  " ^ creg2reg_bits(rsd) ^ ", " ^ creg2reg_bits(rs2)
@@ -1384,11 +1375,10 @@ union clause ast = C_XOR : (cregbits, cregbits)
 
 function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b01 @ rs2 : cregbits @ 0b01) = Some(C_XOR(rsd, rs2))
 
-function clause execute (C_XOR(rsd, rs2)) = {
+function clause execute (C_XOR(rsd, rs2)) =
   let rsd = creg2reg_bits(rsd) in
   let rs2 = creg2reg_bits(rs2) in
   execute(RTYPE(rs2, rsd, rsd, RISCV_XOR))
-}
 
 function clause print_insn (C_XOR(rsd, rs2)) =
   "c.xor  " ^ creg2reg_bits(rsd) ^ ", " ^ creg2reg_bits(rs2)
@@ -1398,11 +1388,10 @@ union clause ast = C_OR : (cregbits, cregbits)
 
 function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b10 @ rs2 : cregbits @ 0b01) = Some(C_OR(rsd, rs2))
 
-function clause execute (C_OR(rsd, rs2)) = {
+function clause execute (C_OR(rsd, rs2)) =
   let rsd = creg2reg_bits(rsd) in
   let rs2 = creg2reg_bits(rs2) in
   execute(RTYPE(rs2, rsd, rsd, RISCV_OR))
-}
 
 function clause print_insn (C_OR(rsd, rs2)) =
   "c.or   " ^ creg2reg_bits(rsd) ^ ", " ^ creg2reg_bits(rs2)
@@ -1412,11 +1401,10 @@ union clause ast = C_AND : (cregbits, cregbits)
 
 function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b11 @ rs2 : cregbits @ 0b01) = Some(C_AND(rsd, rs2))
 
-function clause execute (C_AND(rsd, rs2)) = {
+function clause execute (C_AND(rsd, rs2)) =
   let rsd = creg2reg_bits(rsd) in
   let rs2 = creg2reg_bits(rs2) in
   execute(RTYPE(rs2, rsd, rsd, RISCV_AND))
-}
 
 function clause print_insn (C_AND(rsd, rs2)) =
   "c.and  " ^ creg2reg_bits(rsd) ^ ", " ^ creg2reg_bits(rs2)
@@ -1427,11 +1415,10 @@ union clause ast = C_SUBW : (cregbits, cregbits)
 /* TODO: invalid on RV32 */
 function clause decodeCompressed (0b100 @ 0b1 @ 0b11 @ rsd : cregbits @ 0b00 @ rs2 : cregbits @ 0b01) = Some(C_SUBW(rsd, rs2))
 
-function clause execute (C_SUBW(rsd, rs2)) = {
+function clause execute (C_SUBW(rsd, rs2)) =
   let rsd = creg2reg_bits(rsd) in
   let rs2 = creg2reg_bits(rs2) in
   execute(RTYPEW(rs2, rsd, rsd, RISCV_SUBW))
-}
 
 function clause print_insn (C_SUBW(rsd, rs2)) =
   "c.subw " ^ creg2reg_bits(rsd) ^ ", " ^ creg2reg_bits(rs2)
@@ -1442,11 +1429,10 @@ union clause ast = C_ADDW : (cregbits, cregbits)
 /* TODO: invalid on RV32 */
 function clause decodeCompressed (0b100 @ 0b1 @ 0b11 @ rsd : cregbits @ 0b01 @ rs2 : cregbits @ 0b01) = Some(C_ADDW(rsd, rs2))
 
-function clause execute (C_ADDW(rsd, rs2)) = {
+function clause execute (C_ADDW(rsd, rs2)) =
   let rsd = creg2reg_bits(rsd) in
   let rs2 = creg2reg_bits(rs2) in
   execute(RTYPEW(rs2, rsd, rsd, RISCV_ADDW))
-}
 
 function clause print_insn (C_ADDW(rsd, rs2)) =
   "c.addw " ^ creg2reg_bits(rsd) ^ ", " ^ creg2reg_bits(rs2)
@@ -1490,12 +1476,11 @@ function clause print_insn (C_BNEZ(imm, rs)) =
 /* ****************************************************************** */
 union clause ast = C_SLLI : (bits(6), regbits)
 
-function clause decodeCompressed (0b000 @ nzui5 : bits(1) @ rsd : regbits @ nzui40 : bits(5) @ 0b10) = {
-  let shamt : bits(6) = nzui5 @ nzui40 in
-  if shamt == 0b000000 | rsd == zreg /* TODO: On RV32, also need shamt[5] == 0 */
+function clause decodeCompressed (0b000 @ nzui5 : bits(1) @ rsd : regbits @ nzui40 : bits(5) @ 0b10) =
+  let  shamt : bits(6) = nzui5 @ nzui40 in
+  if   shamt == 0b000000 | rsd == zreg /* TODO: On RV32, also need shamt[5] == 0 */
   then None()
   else Some(C_SLLI(shamt, rsd))
-}
 
 function clause execute (C_SLLI(shamt, rsd)) =
   execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SLLI))
@@ -1506,17 +1491,15 @@ function clause print_insn (C_SLLI(shamt, rsd)) =
 /* ****************************************************************** */
 union clause ast = C_LWSP : (bits(6), regbits)
 
-function clause decodeCompressed (0b010 @ ui5 : bits(1) @ rd : regbits @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10) = {
-  let uimm : bits(6) = ui76 @ ui5 @ ui42 in
-  if  rd == zreg
+function clause decodeCompressed (0b010 @ ui5 : bits(1) @ rd : regbits @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10) =
+  let  uimm : bits(6) = ui76 @ ui5 @ ui42 in
+  if   rd == zreg
   then None()
   else Some(C_LWSP(uimm, rd))
-}
 
-function clause execute (C_LWSP(uimm, rd)) = {
+function clause execute (C_LWSP(uimm, rd)) =
   let imm : bits(12) = EXTZ(uimm @ 0b00) in
   execute(LOAD(imm, sp, rd, false, WORD, false, false))
-}
 
 function clause print_insn (C_LWSP(uimm, rd)) =
   "c.lwsp " ^ rd ^ ", " ^ BitStr(uimm)
@@ -1524,17 +1507,15 @@ function clause print_insn (C_LWSP(uimm, rd)) =
 /* ****************************************************************** */
 union clause ast = C_LDSP : (bits(6), regbits)
 
-function clause decodeCompressed (0b011 @ ui5 : bits(1) @ rd : regbits @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10) = {
-  let uimm : bits(6) = ui86 @ ui5 @ ui43 in
-  if  rd == zreg
+function clause decodeCompressed (0b011 @ ui5 : bits(1) @ rd : regbits @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10) =
+  let  uimm : bits(6) = ui86 @ ui5 @ ui43 in
+  if   rd == zreg
   then None()
   else Some(C_LDSP(uimm, rd))
-}
 
-function clause execute (C_LDSP(uimm, rd)) = {
+function clause execute (C_LDSP(uimm, rd)) =
   let imm : bits(12) = EXTZ(uimm @ 0b000) in
   execute(LOAD(imm, sp, rd, false, DOUBLE, false, false))
-}
 
 function clause print_insn (C_LDSP(uimm, rd)) =
   "c.ldsp " ^ rd ^ ", " ^ BitStr(uimm)
@@ -1542,15 +1523,13 @@ function clause print_insn (C_LDSP(uimm, rd)) =
 /* ****************************************************************** */
 union clause ast = C_SWSP : (bits(6), regbits)
 
-function clause decodeCompressed (0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regbits @ 0b10) = {
+function clause decodeCompressed (0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regbits @ 0b10) =
   let uimm : bits(6) = ui76 @ ui52 in
   Some(C_SWSP(uimm, rs2))
-}
 
-function clause execute (C_SWSP(uimm, rs2)) = {
+function clause execute (C_SWSP(uimm, rs2)) =
   let imm : bits(12) = EXTZ(uimm @ 0b00) in
   execute(STORE(imm, rs2, sp, WORD, false, false))
-}
 
 function clause print_insn (C_SWSP(uimm, rd)) =
   "c.swsp " ^ rd ^ ", " ^ BitStr(uimm)
@@ -1558,15 +1537,13 @@ function clause print_insn (C_SWSP(uimm, rd)) =
 /* ****************************************************************** */
 union clause ast = C_SDSP : (bits(6), regbits)
 
-function clause decodeCompressed (0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regbits @ 0b10) = {
+function clause decodeCompressed (0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regbits @ 0b10) =
   let uimm : bits(6) = ui86 @ ui53 in
   Some(C_SDSP(uimm, rs2))
-}
 
-function clause execute (C_SDSP(uimm, rs2)) = {
+function clause execute (C_SDSP(uimm, rs2)) =
   let imm : bits(12) = EXTZ(uimm @ 0b000) in
   execute(STORE(imm, rs2, sp, DOUBLE, false, false))
-}
 
 function clause print_insn (C_SDSP(uimm, rd)) =
   "c.sdsp " ^ rd ^ ", " ^ BitStr(uimm)
@@ -1574,11 +1551,10 @@ function clause print_insn (C_SDSP(uimm, rd)) =
 /* ****************************************************************** */
 union clause ast = C_JR : (regbits)
 
-function clause decodeCompressed (0b100 @ 0b0 @ rs1 : regbits @ 0b00000 @ 0b10) = {
-  if rs1 == zreg
+function clause decodeCompressed (0b100 @ 0b0 @ rs1 : regbits @ 0b00000 @ 0b10) =
+  if   rs1 == zreg
   then None()
   else Some(C_JR(rs1))
-}
 
 function clause execute (C_JR(rs1)) =
   execute(RISCV_JALR(EXTZ(0b0), rs1, zreg))
@@ -1589,11 +1565,10 @@ function clause print_insn (C_JR(rs1)) =
 /* ****************************************************************** */
 union clause ast = C_JALR : (regbits)
 
-function clause decodeCompressed (0b100 @ 0b1 @ rs1 : regbits @ 0b00000 @ 0b10) = {
-  if rs1 == zreg
+function clause decodeCompressed (0b100 @ 0b1 @ rs1 : regbits @ 0b00000 @ 0b10) =
+  if   rs1 == zreg
   then None()
   else Some(C_JALR(rs1))
-}
 
 function clause execute (C_JALR(rs1)) =
   execute(RISCV_JALR(EXTZ(0b0), rs1, ra))
@@ -1604,11 +1579,10 @@ function clause print_insn (C_JALR(rs1)) =
 /* ****************************************************************** */
 union clause ast = C_MV : (regbits, regbits)
 
-function clause decodeCompressed (0b100 @ 0b0 @ rd : regbits @ rs2 : regbits @ 0b10) = {
-  if rs2 == zreg | rd == zreg
+function clause decodeCompressed (0b100 @ 0b0 @ rd : regbits @ rs2 : regbits @ 0b10) =
+  if   rs2 == zreg | rd == zreg
   then None()
   else Some(C_MV(rd, rs2))
-}
 
 function clause execute (C_MV(rd, rs2)) =
   execute(RTYPE(rs2, zreg, rd, RISCV_ADD))
@@ -1619,11 +1593,10 @@ function clause print_insn (C_MV(rd, rs2)) =
 /* ****************************************************************** */
 union clause ast = C_ADD : (regbits, regbits)
 
-function clause decodeCompressed (0b100 @ 0b1 @ rsd : regbits @ rs2 : regbits @ 0b10) = {
-  if rsd == zreg | rs2 == zreg
+function clause decodeCompressed (0b100 @ 0b1 @ rsd : regbits @ rs2 : regbits @ 0b10) =
+  if   rsd == zreg | rs2 == zreg
   then None()
   else Some(C_ADD(rsd, rs2))
-}
 
 function clause execute (C_ADD(rsd, rs2)) =
   execute(RTYPE(rs2, rsd, rsd, RISCV_ADD))
diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail
index 21a40af4..72b7e8da 100644
--- a/riscv/riscv_mem.sail
+++ b/riscv/riscv_mem.sail
@@ -1,4 +1,8 @@
-/* memory */
+/* Physical memory model.
+ *
+ * This assumes that the platform memory map has been defined, so that accesses
+ * to MMIO regions can be dispatched.
+ */
 
 function is_aligned_addr (addr : xlenbits, width : atom('n)) -> forall 'n. bool =
   unsigned(addr) % width == 0
@@ -87,9 +91,7 @@ function mem_write_ea (addr, width, aq, rl, con) = {
 // only used for actual memory regions, to avoid MMIO effects
 function phys_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> forall 'n. MemoryOpResult(bool) = {
   print("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
-//  if   
   MemValue(__RISCV_write(addr, width, data))
-//  else MemException(E_SAMO_Access_Fault)
 }
 
 // dispatches to MMIO regions or physical memory regions depending on physical memory map
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail
index 558ca2db..7ab83aa6 100644
--- a/riscv/riscv_platform.sail
+++ b/riscv/riscv_platform.sail
@@ -1,4 +1,4 @@
-/* Platform and devices */
+/* Platform-specific definitions, and basic MMIO devices. */
 
 /* Current constraints on this implementation are:
    - it cannot access memory directly, but instead provides definitions for the physical memory model
@@ -21,8 +21,8 @@ val plat_enable_misaligned_access = {ocaml: "Platform.enable_misaligned_access",
                                      lem: "plat_enable_misaligned_access"} : unit -> bool
 
 /* ROM holding reset vector and device-tree DTB */
-val plat_rom_base = {ocaml: "Platform.rom_base", lem: "plat_rom_base"} : unit -> xlenbits
-val plat_rom_size = {ocaml: "Platform.rom_size", lem: "plat_rom_size"} : unit -> xlenbits
+val plat_rom_base   = {ocaml: "Platform.rom_base", lem: "plat_rom_base"} : unit -> xlenbits
+val plat_rom_size   = {ocaml: "Platform.rom_size", lem: "plat_rom_size"} : unit -> xlenbits
 
 /* Location of clock-interface, which should match with the spec in the DTB */
 val plat_clint_base = {ocaml: "Platform.clint_base", lem: "plat_clint_base"} : unit -> xlenbits
@@ -69,11 +69,9 @@ register mtimecmp : xlenbits  // memory-mapped internal clint register.
 
 /* CLINT memory-mapped IO */
 
-let MSIP_BASE     : xlenbits = 0x0000000000000000
-let MTIMECMP_BASE : xlenbits = 0x0000000000004000
-let MTIME_BASE    : xlenbits = 0x000000000000bff8
-
-/* 0000 msip hart 0         -- memory-mapped software interrupt
+/* relative address map:
+ *
+ * 0000 msip hart 0         -- memory-mapped software interrupt
  * 0004 msip hart 1
  * 4000 mtimecmp hart 0 lo  -- memory-mapped timer thresholds
  * 4004 mtimecmp hart 0 hi
@@ -83,6 +81,10 @@ let MTIME_BASE    : xlenbits = 0x000000000000bff8
  * bffc mtime hi
  */
 
+let MSIP_BASE     : xlenbits = 0x0000000000000000
+let MTIMECMP_BASE : xlenbits = 0x0000000000004000
+let MTIME_BASE    : xlenbits = 0x000000000000bff8
+
 val clint_load : forall 'n. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg}
 function clint_load(addr, width) = {
   let addr = addr - plat_clint_base ();
@@ -162,7 +164,7 @@ register htif_done   : bool
 register htif_exit_code : xlenbits
 
 
-/* since the htif tohost port is only available at a single address,
+/* Since the htif tohost port is only available at a single address,
  * we'll assume here that physical memory model has correctly
  * dispatched the address.
  */
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index a095c9cb..2d074f27 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -1,6 +1,8 @@
+/* The emulator fetch-execute-interrupt dispatch loop. */
+
 union FetchResult = {
-  F_Base : word,                       /* Base ISA */
-  F_RVC : half,                        /* Compressed ISA */
+  F_Base  : word,                      /* Base ISA */
+  F_RVC   : half,                      /* Compressed ISA */
   F_Error : (ExceptionType, xlenbits)  /* exception and PC */
 }
 
@@ -8,7 +10,7 @@ function isRVC(h : half) -> bool =
  ~ (h[1 .. 0] == 0b11)
 
 val fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wreg}
-function fetch() -> FetchResult = {
+function fetch() -> FetchResult =
   /* check for legal PC */
   if (PC[0] != 0b0 | (PC[1] != 0b0 & (~ (haveRVC()))))
   then F_Error(E_Fetch_Addr_Align, PC)
@@ -39,11 +41,10 @@ function fetch() -> FetchResult = {
       }
     }
   }
-}
 
 /* returns whether an instruction was retired, and whether to increment the step count in the trace */
 val step : int -> (bool, bool) effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
-function step(step_no) = {
+function step(step_no) =
   match curInterrupt(cur_privilege, mip, mie, mideleg) {
     Some(intr, priv) => {
       print_bits("Handling interrupt: ", intr);
@@ -87,7 +88,6 @@ function step(step_no) = {
       }
     }
   }
-}
 
 val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
 function loop () = {
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 9153c3cb..451ff9ec 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -1,3 +1,5 @@
+/* Machine-mode and supervisor-mode state definitions and operations. */
+
 /* privilege level */
 
 register cur_privilege : Privilege
@@ -6,6 +8,34 @@ register cur_privilege : Privilege
 
 register cur_inst : xlenbits
 
+/* State projections
+ *
+ * Some machine state is processed via projections from machine-mode views to
+ * views from lower privilege levels.  So, for e.g. when mstatus is read from
+ * lower privilege levels, we use 'lowering_' projections:
+ *
+ *   mstatus  ->  sstatus  ->  ustatus
+ *
+ * Similarly, when machine state is written from lower privileges, that state is
+ * lifted into the appropriate value for the machine-mode state.
+ *
+ *   ustatus  ->  sstatus  ->  mstatus
+ *
+ * In addition, several fields in machine state registers are WARL or WLRL,
+ * requiring that values written to the registers be legalized.  For each such
+ * register, there will be an associated 'legalize_' function.  These functions
+ * will need to be supplied externally, and will depend on the legal values
+ * supported by a platform/implementation (or misa).  The legalize_ functions
+ * generate a legal value from the current value and the written value.  In more
+ * complex cases, they will also implicitly read the current values of misa,
+ * mstatus, etc.
+ *
+ * Each register definition below is followed by custom projections
+ * and choice of legalizations if needed.  For now, we typically
+ * implement the simplest legalize_ alternatives.
+ */
+
+
 /* M-mode registers */
 
 bitfield Misa : bits(64) = {
@@ -44,7 +74,7 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
   /* Allow modifications to C. */
   let v = Mk_Misa(v);
   // Suppress changing C if nextPC would become misaligned.
-  if v.C() == false & nextPC[1] == true
+  if   v.C() == false & nextPC[1] == true
   then m
   else update_C(m, v.C())
 }
@@ -93,14 +123,14 @@ function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = {
   m
 }
 
-/* machine state utilities */
+/* architecture and extension checks */
 
 function cur_Architecture() -> Architecture = {
   let a : arch_xlen =
     match (cur_privilege) {
-      Machine => misa.MXL(),
+      Machine    => misa.MXL(),
       Supervisor => mstatus.SXL(),
-      User => mstatus.UXL()
+      User       => mstatus.UXL()
     };
   match architecture(a) {
     Some(a) => a,
@@ -117,10 +147,7 @@ function haveRVC()     -> bool = { misa.C() == true }
 function haveMulDiv()  -> bool = { misa.M() == true }
 function haveFP()      -> bool = { misa.F() == true | misa.D() == true }
 
-function pc_alignment_mask() -> xlenbits =
-  ~(EXTZ(if misa.C() == true then 0b00 else 0b10))
-
-/* interrupt registers */
+/* interrupt processing state */
 
 bitfield Minterrupts : bits(64) = {
   MEI : 11, /* external interrupts */
@@ -171,7 +198,7 @@ function legalize_mideleg(o : Minterrupts, v : xlenbits) -> Minterrupts = {
   m
 }
 
-/* exception registers */
+/* exception processing state */
 
 bitfield Medeleg : bits(64) = {
   SAMO_Page_Fault   : 15,
@@ -233,14 +260,22 @@ function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = {
   }
 }
 
-/* auxiliary exception registers */
+/* Exception PC */
+
 register mepc : xlenbits
 
+// legalizing writes to xepc
 function legalize_xepc(v : xlenbits) -> xlenbits = {
   v & EXTS(if haveRVC() then 0b110 else 0b100)
 }
 
-register mtval : xlenbits
+// masking for reads to xepc
+function pc_alignment_mask() -> xlenbits =
+  ~(EXTZ(if misa.C() == true then 0b00 else 0b10))
+
+/* auxiliary exception registers */
+
+register mtval    : xlenbits
 register mscratch : xlenbits
 
 /* counters */
@@ -274,15 +309,17 @@ function legalize_scounteren(c : Counteren, v : xlenbits) -> Counteren = {
 register mcycle : xlenbits
 register mtime : xlenbits
 
-/* minstret is an architectural register, and can be written to.  The
-   spec says that minstret increments on instruction retires need to
-   occur before any explicit writes to instret.  However, in our
-   simulation loop, we need to execute an instruction to find out
-   whether it retired, and hence can only increment instret after
-   execution.  To avoid doing this in the case minstret was explicitly
-   written to, we track writes to it in a separate model-internal
-   register.
-*/
+/* minstret
+ *
+ * minstret is an architectural register, and can be written to.  The
+ * spec says that minstret increments on instruction retires need to
+ * occur before any explicit writes to instret.  However, in our
+ * simulation loop, we need to execute an instruction to find out
+ * whether it retired, and hence can only increment instret after
+ * execution.  To avoid doing this in the case minstret was explicitly
+ * written to, we track writes to it in a separate model-internal
+ * register.
+ */
 register minstret : xlenbits
 register minstret_written : bool
 
@@ -303,8 +340,10 @@ register mhartid : xlenbits
 register pmpaddr0 : xlenbits
 register pmpcfg0 : xlenbits
 
-/* supervisor mode registers */
 
+/* S-mode registers */
+
+/* sstatus reveals a subset of mstatus */
 bitfield Sstatus : bits(64) = {
   SD   : 63,
   UXL  : 33 .. 32,
@@ -337,7 +376,8 @@ function lower_mstatus(m : Mstatus) -> Sstatus = {
 
 function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {
   let m = update_SD(m, s.SD());
-  // let m = update_UXL(m, s.UXL());  FIXME: This should be parameterized by a platform setting.  For now, match spike.
+  // FIXME: This should be parameterized by a platform setting.  For now, match spike.
+  // let m = update_UXL(m, s.UXL());
   let m = update_MXR(m, s.MXR());
   let m = update_SUM(m, s.SUM());
   let m = update_XS(m, s.XS());
@@ -433,6 +473,7 @@ function legalize_sie(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterr
 
 register sideleg : Sinterrupts
 
+/* s-mode address translation and protection (satp) */
 bitfield Satp64 : bits(64) = {
   Mode : 63 .. 60,
   Asid : 59 .. 44,
@@ -449,16 +490,17 @@ function legalize_satp(a : Architecture, o : xlenbits, v : xlenbits) -> xlenbits
   }
 }
 
-register stvec : Mtvec
+/* other supervisor state */
+register stvec    : Mtvec
 register sscratch : xlenbits
-register sepc : xlenbits
-register scause : Mcause
-register stval : xlenbits
+register sepc     : xlenbits
+register scause   : Mcause
+register stval    : xlenbits
 
 /* disabled trigger/debug module */
 register tselect : xlenbits
 
-/* csr name printer */
+/* CSR names */
 
 val cast csr_name : csreg -> string
 function csr_name(csr) = {
@@ -624,7 +666,7 @@ mapping csr_name_map : csreg <-> string = {
  }
 
 
-/* csr access control */
+/* CSR access control */
 
 function csrAccess(csr : csreg) -> csrRW = csr[11..10]
 function csrPriv(csr : csreg) -> priv_level = csr[9..8]
@@ -807,10 +849,10 @@ function curInterrupt(priv : Privilege, pend : Minterrupts, enbl : Minterrupts,
   }
 }
 
-/* instruction control flow */
+/* privilege transitions due to exceptions and interrupts */
 
 struct sync_exception = {
-  trap : ExceptionType,
+  trap    : ExceptionType,
   excinfo : option(xlenbits)
 }
 
@@ -896,7 +938,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       handle_trap(del_priv, false, e.trap, pc, e.excinfo)
     },
     (_, CTL_MRET())  => {
-      let prev_priv = cur_privilege;
+      let prev_priv   = cur_privilege;
       mstatus->MIE()  = mstatus.MPIE();
       mstatus->MPIE() = true;
       cur_privilege   = privLevel_of_bits(mstatus.MPP());
@@ -909,7 +951,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       mepc & pc_alignment_mask()
     },
     (_, CTL_SRET())  => {
-      let prev_priv = cur_privilege;
+      let prev_priv   = cur_privilege;
       mstatus->SIE()  = mstatus.SPIE();
       mstatus->SPIE() = true;
       cur_privilege   = if mstatus.SPP() == true then Supervisor else User;
@@ -945,10 +987,12 @@ function handle_illegal() -> unit = {
   nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC)
 }
 
+/* state state initialization */
+
 function init_sys() -> unit = {
   cur_privilege = Machine;
 
-  mhartid = EXTZ(0b0);
+  mhartid     = EXTZ(0b0);
 
   misa->MXL() = arch_to_bits(RV64);
   misa->A()   = true; /* atomics */
@@ -959,9 +1003,9 @@ function init_sys() -> unit = {
   misa->S()   = true; /* supervisor-mode */
 
   /* 64-bit only mode with no extensions */
-  mstatus->SXL() = misa.MXL();
-  mstatus->UXL() = misa.MXL();
-  mstatus->SD()  = false;
+  mstatus->SXL()  = misa.MXL();
+  mstatus->UXL()  = misa.MXL();
+  mstatus->SD()   = false;
 
   mip->bits()     = EXTZ(0b0);
   mie->bits()     = EXTZ(0b0);
@@ -977,8 +1021,9 @@ function init_sys() -> unit = {
   mtime           = EXTZ(0b0);
 
   mcounteren->bits() = EXTZ(0b0);
-  minstret = EXTZ(0b0);
-  minstret_written = false;
+
+  minstret           = EXTZ(0b0);
+  minstret_written   = false;
 
   // log compatibility with spike
   print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(EXTZ(0b0) : xlenbits) ^ ")")
@@ -987,6 +1032,6 @@ function init_sys() -> unit = {
 /* memory access exceptions, defined here for use by the platform model. */
 
 union MemoryOpResult ('a : Type) = {
-  MemValue : 'a,
-  MemException: ExceptionType
+  MemValue     : 'a,
+  MemException : ExceptionType
 }
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index ddce0615..77df74db 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -1,7 +1,8 @@
-/* basic types */
+/* Basic type and function definitions used pervasively in the model. */
 
 let xlen = 64
 type xlenbits = bits(64)
+
 let xlen_max_unsigned = 2 ^ xlen - 1
 let xlen_max_signed = 2 ^ (xlen - 1) - 1
 let xlen_min_signed = 0 - 2 ^ (xlen - 1)
@@ -9,24 +10,31 @@ let xlen_min_signed = 0 - 2 ^ (xlen - 1)
 type half = bits(16)
 type word = bits(32)
 
+/* register identifiers */
+
+type regbits  = bits(5)
+type cregbits = bits(3)    /* identifiers in RVC instructions */
+type csreg    = bits(12)   /* CSR addressing */
+
+/* register file indexing */
+
 type regno ('n : Int), 0 <= 'n < 32 = atom('n)
-type regbits = bits(5)
-type cregbits = bits(3)
-type csreg = bits(12)
 
 val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)}
 function regbits_to_regno b = let 'r = unsigned(b) in r
 
+/* mapping RVC register indices into normal indices */
 val creg2reg_bits : cregbits -> regbits
 function creg2reg_bits(creg) = 0b01 @ creg
 
-/* some arch and ABI relevant registers */
+/* some architecture and ABI relevant register identifiers */
+let zreg : regbits = 0b00000  /* x0, zero register  */
+let ra   : regbits = 0b00001  /* x1, return address */
+let sp   : regbits = 0b00010  /* x2, stack pointer  */
 
-let zreg : regbits = 0b00000
-let ra : regbits = 0b00001  /* x1 */
-let sp : regbits = 0b00010  /* x2 */
+/* program counter */
 
-register PC : xlenbits
+register PC     : xlenbits
 register nextPC : xlenbits
 
 /* register file and accessors */
@@ -147,7 +155,7 @@ function wX (r, v) = {
 
 overload X = {rX, wX}
 
-/* register name printers */
+/* register names */
 
 val cast reg_name_abi : regbits -> string
 
@@ -191,11 +199,12 @@ function reg_name_abi(r) = {
 /* instruction fields */
 
 type opcode = bits(7)
-type imm12 = bits(12)
-type imm20 = bits(20)
-type amo = bits(1)
+type imm12  = bits(12)
+type imm20  = bits(20)
+type amo    = bits(1)  /* amo opcode flags */
 
 /* base architecture definitions */
+
 enum Architecture = {RV32, RV64, RV128}
 type arch_xlen = bits(2)
 function architecture(a : arch_xlen) -> option(Architecture) =
@@ -216,14 +225,14 @@ function arch_to_bits(a : Architecture) -> arch_xlen =
 /* privilege levels */
 
 type priv_level = bits(2)
-enum Privilege = {User, Supervisor, Machine}
+enum Privilege  = {User, Supervisor, Machine}
 
 val cast privLevel_to_bits : Privilege -> priv_level
 function privLevel_to_bits (p) =
   match (p) {
-    User => 0b00,
+    User       => 0b00,
     Supervisor => 0b01,
-    Machine => 0b11
+    Machine    => 0b11
   }
 
 val cast privLevel_of_bits : priv_level -> Privilege
@@ -237,35 +246,67 @@ function privLevel_of_bits (p) =
 val cast privLevel_to_str : Privilege -> string
 function privLevel_to_str (p) =
   match (p) {
-    User => "U",
+    User       => "U",
     Supervisor => "S",
-    Machine => "M"
+    Machine    => "M"
   }
 
-/* access types */
+/* memory access types */
 
 enum AccessType = {Read, Write, ReadWrite, Execute}
+
 val cast accessType_to_str : AccessType -> string
 function accessType_to_str (a) =
   match (a) {
-    Read => "R",
-    Write => "W",
+    Read      => "R",
+    Write     => "W",
     ReadWrite => "RW",
-    Execute => "X"
+    Execute   => "X"
   }
 
 enum ReadType   = {Instruction, Data}
+
 val cast readType_to_str : ReadType -> string
 function readType_to_str (r) =
   match (r) {
     Instruction => "I",
-    Data => "D"
+    Data        => "D"
   }
 
-/* architectural exception and interrupt definitions */
+enum word_width = {BYTE, HALF, WORD, DOUBLE}
+
+/* architectural interrupt definitions */
 
 type exc_code = bits(4)
 
+enum InterruptType = {
+  I_U_Software,
+  I_S_Software,
+  I_M_Software,
+  I_U_Timer,
+  I_S_Timer,
+  I_M_Timer,
+  I_U_External,
+  I_S_External,
+  I_M_External
+}
+
+val cast interruptType_to_bits : InterruptType -> exc_code
+function interruptType_to_bits (i) =
+  match (i) {
+    I_U_Software => 0x0,
+    I_S_Software => 0x1,
+    I_M_Software => 0x3,
+    I_U_Timer    => 0x4,
+    I_S_Timer    => 0x5,
+    I_M_Timer    => 0x7,
+    I_U_External => 0x8,
+    I_S_External => 0x9,
+    I_M_External => 0xb
+  }
+
+/* architectural exception definitions */
+
 enum ExceptionType = {
  E_Fetch_Addr_Align,
  E_Fetch_Access_Fault,
@@ -288,87 +329,50 @@ enum ExceptionType = {
 val cast exceptionType_to_bits : ExceptionType -> exc_code
 function exceptionType_to_bits(e) =
   match (e) {
-    E_Fetch_Addr_Align => 0x0,
+    E_Fetch_Addr_Align   => 0x0,
     E_Fetch_Access_Fault => 0x1,
-    E_Illegal_Instr => 0x2,
-    E_Breakpoint => 0x3,
-    E_Load_Addr_Align => 0x4,
-    E_Load_Access_Fault => 0x5,
-    E_SAMO_Addr_Align => 0x6,
-    E_SAMO_Access_Fault => 0x7,
-    E_U_EnvCall => 0x8,
-    E_S_EnvCall => 0x9,
-    E_Reserved_10 => 0xa,
-    E_M_EnvCall => 0xb,
-    E_Fetch_Page_Fault => 0xc,
-    E_Load_Page_Fault => 0xd,
-    E_Reserved_14 => 0xe,
-    E_SAMO_Page_Fault => 0xf
+    E_Illegal_Instr      => 0x2,
+    E_Breakpoint         => 0x3,
+    E_Load_Addr_Align    => 0x4,
+    E_Load_Access_Fault  => 0x5,
+    E_SAMO_Addr_Align    => 0x6,
+    E_SAMO_Access_Fault  => 0x7,
+    E_U_EnvCall          => 0x8,
+    E_S_EnvCall          => 0x9,
+    E_Reserved_10        => 0xa,
+    E_M_EnvCall          => 0xb,
+    E_Fetch_Page_Fault   => 0xc,
+    E_Load_Page_Fault    => 0xd,
+    E_Reserved_14        => 0xe,
+    E_SAMO_Page_Fault    => 0xf
   }
 
 val cast exceptionType_to_str : ExceptionType -> string
 function exceptionType_to_str(e) =
   match (e) {
-    E_Fetch_Addr_Align => "misaligned-fetch",
+    E_Fetch_Addr_Align   => "misaligned-fetch",
     E_Fetch_Access_Fault => "fetch-access-fault",
-    E_Illegal_Instr => "illegal-instruction",
-    E_Breakpoint => "breakpoint",
-    E_Load_Addr_Align => "misaligned-load",
-    E_Load_Access_Fault => "load-access-fault",
-    E_SAMO_Addr_Align => "misaliged-store/amo",
-    E_SAMO_Access_Fault => "store/amo-access-fault",
-    E_U_EnvCall => "u-call",
-    E_S_EnvCall => "s-call",
-    E_Reserved_10 => "reserved-0",
-    E_M_EnvCall => "m-call",
-    E_Fetch_Page_Fault => "fetch-page-fault",
-    E_Load_Page_Fault => "load-page-fault",
-    E_Reserved_14 => "reserved-1",
-    E_SAMO_Page_Fault => "store/amo-page-fault"
-  }
-
-enum InterruptType = {
-  I_U_Software,
-  I_S_Software,
-  I_M_Software,
-  I_U_Timer,
-  I_S_Timer,
-  I_M_Timer,
-  I_U_External,
-  I_S_External,
-  I_M_External
-}
-
-val cast interruptType_to_bits : InterruptType -> exc_code
-function interruptType_to_bits (i) =
-  match (i) {
-    I_U_Software => 0x0,
-    I_S_Software => 0x1,
-    I_M_Software => 0x3,
-    I_U_Timer    => 0x4,
-    I_S_Timer    => 0x5,
-    I_M_Timer    => 0x7,
-    I_U_External => 0x8,
-    I_S_External => 0x9,
-    I_M_External => 0xb
-  }
-
-type tv_mode = bits(2)
-enum TrapVectorMode = {TV_Direct, TV_Vector, TV_Reserved}
-
-val cast trapVectorMode_of_bits : tv_mode -> TrapVectorMode
-function trapVectorMode_of_bits (m) =
-  match (m) {
-    0b00 => TV_Direct,
-    0b01 => TV_Vector,
-    _    => TV_Reserved
+    E_Illegal_Instr      => "illegal-instruction",
+    E_Breakpoint         => "breakpoint",
+    E_Load_Addr_Align    => "misaligned-load",
+    E_Load_Access_Fault  => "load-access-fault",
+    E_SAMO_Addr_Align    => "misaliged-store/amo",
+    E_SAMO_Access_Fault  => "store/amo-access-fault",
+    E_U_EnvCall          => "u-call",
+    E_S_EnvCall          => "s-call",
+    E_Reserved_10        => "reserved-0",
+    E_M_EnvCall          => "m-call",
+    E_Fetch_Page_Fault   => "fetch-page-fault",
+    E_Load_Page_Fault    => "load-page-fault",
+    E_Reserved_14        => "reserved-1",
+    E_SAMO_Page_Fault    => "store/amo-page-fault"
   }
 
-/* other exceptions */
+/* model-internal exceptions */
 
 union exception = {
   Error_not_implemented : string,
-  Error_internal_error : unit
+  Error_internal_error  : unit
 }
 
 val not_implemented : forall ('a : Type). string -> 'a effect {escape}
@@ -380,6 +384,19 @@ function internal_error(s) = {
     throw Error_internal_error()
 }
 
+/* trap modes */
+
+type tv_mode = bits(2)
+enum TrapVectorMode = {TV_Direct, TV_Vector, TV_Reserved}
+
+val cast trapVectorMode_of_bits : tv_mode -> TrapVectorMode
+function trapVectorMode_of_bits (m) =
+  match (m) {
+    0b00 => TV_Direct,
+    0b01 => TV_Vector,
+    _    => TV_Reserved
+  }
+
 /* extension context status */
 
 type ext_status = bits(2)
@@ -388,10 +405,10 @@ enum ExtStatus = {Off, Initial, Clean, Dirty}
 val cast extStatus_to_bits : ExtStatus -> ext_status
 function extStatus_to_bits(e) =
   match (e) {
-    Off => 0b00,
+    Off     => 0b00,
     Initial => 0b01,
-    Clean => 0b10,
-    Dirty => 0b11
+    Clean   => 0b10,
+    Dirty   => 0b11
   }
 
 val cast extStatus_of_bits : ext_status -> ExtStatus
@@ -410,24 +427,32 @@ enum SATPMode = {Sbare, Sv32, Sv39}
 
 function satpMode_of_bits(a : Architecture, m : satp_mode) -> option(SATPMode) =
   match (a, m) {
-    (_, 0x0)    => Some(Sbare),
+    (_,    0x0) => Some(Sbare),
     (RV32, 0x1) => Some(Sv32),
     (RV64, 0x8) => Some(Sv39),
     (_, _)      => None()
   }
 
 /* CSR access control bits (from CSR addresses) */
+
 type csrRW = bits(2)  /* read/write */
 
-enum uop = {RISCV_LUI, RISCV_AUIPC} /* upper immediate ops */
-enum bop = {RISCV_BEQ, RISCV_BNE, RISCV_BLT, RISCV_BGE, RISCV_BLTU, RISCV_BGEU} /* branch ops */
-enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, RISCV_XORI, RISCV_ORI, RISCV_ANDI} /* immediate ops */
-enum sop = {RISCV_SLLI, RISCV_SRLI, RISCV_SRAI} /* shift ops */
-enum rop = {RISCV_ADD, RISCV_SUB, RISCV_SLL, RISCV_SLT, RISCV_SLTU, RISCV_XOR, RISCV_SRL, RISCV_SRA, RISCV_OR, RISCV_AND} /* reg-reg ops */
-enum ropw = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW, RISCV_SRLW, RISCV_SRAW} /* reg-reg 32-bit ops */
-enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, AMOMIN, AMOMAX, AMOMINU, AMOMAXU} /* AMO ops */
-enum csrop = {CSRRW, CSRRS, CSRRC}
-enum word_width = {BYTE, HALF, WORD, DOUBLE}
+/* instruction opcode grouping */
+enum uop = {RISCV_LUI, RISCV_AUIPC}               /* upper immediate ops */
+enum bop = {RISCV_BEQ, RISCV_BNE, RISCV_BLT,
+            RISCV_BGE, RISCV_BLTU, RISCV_BGEU}    /* branch ops */
+enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU,
+            RISCV_XORI, RISCV_ORI, RISCV_ANDI}    /* immediate ops */
+enum sop = {RISCV_SLLI, RISCV_SRLI, RISCV_SRAI}   /* shift ops */
+enum rop = {RISCV_ADD, RISCV_SUB, RISCV_SLL, RISCV_SLT,
+            RISCV_SLTU, RISCV_XOR, RISCV_SRL, RISCV_SRA,
+            RISCV_OR, RISCV_AND}                  /* reg-reg ops */
+
+enum ropw  = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW,
+              RISCV_SRLW, RISCV_SRAW}             /* reg-reg 32-bit ops */
+enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR,
+              AMOMIN, AMOMAX, AMOMINU, AMOMAXU}   /* AMO ops */
+enum csrop = {CSRRW, CSRRS, CSRRC}                /* CSR ops */
 
 /* mappings for assembly */
 
@@ -469,30 +494,29 @@ mapping reg_name = {
 
 val sep : unit <-> string
 mapping sep : unit <-> string = {
-  () <-> opt_spc() ^ "," ^ def_spc()
+  ()     <-> opt_spc() ^ "," ^ def_spc()
 }
 
 mapping bool_bits : bool <-> bits(1) = {
-  true <-> 0b1,
-  false <-> 0b0
+  true   <-> 0b1,
+  false  <-> 0b0
 }
 
 mapping bool_not_bits : bool <-> bits(1) = {
-  true <-> 0b0,
-  false <-> 0b1
+  true   <-> 0b0,
+  false  <-> 0b1
 }
 
-
 mapping size_bits : word_width <-> bits(2) = {
-  BYTE <-> 0b00,
-  HALF <-> 0b01,
-  WORD <-> 0b10,
+  BYTE   <-> 0b00,
+  HALF   <-> 0b01,
+  WORD   <-> 0b10,
   DOUBLE <-> 0b11
 }
 
 mapping size_mnemonic : word_width <-> string = {
-  BYTE <-> "b",
-  HALF <-> "h",
-  WORD <-> "w",
+  BYTE   <-> "b",
+  HALF   <-> "h",
+  WORD   <-> "w",
   DOUBLE <-> "d"
 }
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index a067e94d..caafb131 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -1,3 +1,5 @@
+/* Supervisor-mode address translation and page-table walks. */
+
 /* PageSize */
 
 let PAGESIZE_BITS = 12
@@ -29,23 +31,23 @@ function isInvalidPTE(p : pteAttribs) -> bool = {
 
 function checkPTEPermission(ac : AccessType, priv : Privilege, mxr : bool, do_sum : bool, p : PTE_Bits) -> bool = {
   match (ac, priv) {
-    (Read, User)      => p.U() == true & (p.R() == true | (p.X() == true & mxr)),
-    (Write, User)     => p.U() == true & p.W() == true,
-    (ReadWrite, User) => p.U() == true & p.W() == true & (p.R() == true | (p.X() == true & mxr)),
-    (Execute, User)   => p.U() == true & p.X() == true,
+    (Read,      User)       => p.U() == true & (p.R() == true | (p.X() == true & mxr)),
+    (Write,     User)       => p.U() == true & p.W() == true,
+    (ReadWrite, User)       => p.U() == true & p.W() == true & (p.R() == true | (p.X() == true & mxr)),
+    (Execute,   User)       => p.U() == true & p.X() == true,
 
-    (Read, Supervisor)      => (p.U() == false | do_sum) & (p.R() == true | (p.X() == true & mxr)),
-    (Write, Supervisor)     => (p.U() == false | do_sum) & p.W() == true,
+    (Read,      Supervisor) => (p.U() == false | do_sum) & (p.R() == true | (p.X() == true & mxr)),
+    (Write,     Supervisor) => (p.U() == false | do_sum) & p.W() == true,
     (ReadWrite, Supervisor) => (p.U() == false | do_sum) & p.W() == true & (p.R() == true | (p.X() == true & mxr)),
-    (Execute, Supervisor)   => p.U() == false & p.X() == true,
+    (Execute,   Supervisor) => p.U() == false & p.X() == true,
 
-    (_, Machine)      => internal_error("m-mode mem perm check")
+    (_,         Machine)    => internal_error("m-mode mem perm check")
   }
 }
 
 function update_PTE_Bits(p : PTE_Bits, a : AccessType) -> option(PTE_Bits) = {
-  let update_d = (a == Write | a == ReadWrite) & p.D() == false;
-  let update_a = p.A() == false;
+  let update_d = (a == Write | a == ReadWrite) & p.D() == false; // dirty-bit
+  let update_a = p.A() == false;                                 // accessed-bit
   if update_d | update_a then {
     let np = update_A(p, true);
     let np = if update_d then update_D(p, true) else np;
@@ -143,7 +145,7 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
   let pt_ofs : paddr39 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV39_LEVEL_BITS))[(SV39_LEVEL_BITS - 1) .. 0]),
                                 PTE39_LOG_SIZE);
   let pte_addr = ptb + pt_ofs;
-  /* FIXME: we assume here that walks only access memory-backed addresses. */
+  /* FIXME: we assume here that walks only access physical-memory-backed addresses, and not MMIO regions. */
   match (phys_mem_read(Data, EXTZ(pte_addr), 8, false, false, false)) {
     MemException(_) => {
 /*    print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
@@ -245,7 +247,6 @@ function make_TLB39_Entry(asid, global, vAddr, pAddr, pte, level, pteAddr) = {
 }
 
 /* TODO: make this a vector or array of entries */
-let TLBEntries = 32
 register tlb39 : option(TLB39_Entry)
 
 val lookupTLB39 : (asid64, vaddr39) -> option((int, TLB39_Entry)) effect {rreg}
@@ -262,7 +263,7 @@ function lookupTLB39(asid, vaddr) = {
 val addToTLB39 : (asid64, vaddr39, paddr39, SV39_PTE, paddr39, nat, bool) -> unit effect {wreg, rreg}
 function addToTLB39(asid, vAddr, pAddr, pte, pteAddr, level, global) = {
   let ent = make_TLB39_Entry(asid, global, vAddr, pAddr, pte, level, pteAddr);
-  tlb39 = Some(ent)
+  tlb39   = Some(ent)
 }
 
 function writeTLB39(idx : int, ent : TLB39_Entry) -> unit =
@@ -387,12 +388,12 @@ val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result effect {escape
 function translateAddr(vAddr, ac, rt) = {
   let effPriv : Privilege = match rt {
     Instruction => cur_privilege,
-    Data => if mstatus.MPRV() == true
-            then privLevel_of_bits(mstatus.MPP())
-            else cur_privilege
+    Data        => if   mstatus.MPRV() == true
+                   then privLevel_of_bits(mstatus.MPP())
+                   else cur_privilege
   };
-  let mxr : bool = mstatus.MXR() == true;
-  let do_sum : bool = mstatus.SUM() == true;
+  let mxr    : bool   = mstatus.MXR() == true;
+  let do_sum : bool   = mstatus.SUM() == true;
   let mode : SATPMode = translationMode(effPriv);
   match mode {
     Sbare => TR_Address(vAddr),
-- 
cgit v1.2.3


From f3ef82fee78d40c628d319dab4cc35a41c638e8e Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 23 Jul 2018 16:14:12 +0100
Subject: Coq: make all pattern matches in the output exhaustive Uses previous
 stage to deal with (e.g.) guards. New option -dcoq_warn_nonex tells you where
 all of the extra default cases were added.

---
 aarch64/full/spec.sail     |   2 +-
 src/process_file.ml        |   2 +-
 src/rewrites.ml            | 296 +++++++++++++++++++++++++++++++++++++++++++++
 src/rewrites.mli           |   7 ++
 src/sail.ml                |   3 +
 src/type_check.mli         |   1 +
 test/coq/pass/allpats.sail | 100 +++++++++++++++
 7 files changed, 409 insertions(+), 2 deletions(-)
 create mode 100644 test/coq/pass/allpats.sail

diff --git a/aarch64/full/spec.sail b/aarch64/full/spec.sail
index 6920db48..897fa56e 100644
--- a/aarch64/full/spec.sail
+++ b/aarch64/full/spec.sail
@@ -4027,7 +4027,7 @@ function FPRoundBase (op, fpcr, rounding) = {
   };
   let 'F = F_mut;
   let 'E = E_mut;
-  assert(constraint('F in {10, 23, 52} & 'E in {5, 8, 11}));
+  assert(constraint('F in {10, 23, 52} & 'E in {5, 8, 11} & 'N > 'F));
   mantissa : real = undefined;
   sign : bits(1) = undefined;
   if op < 0.0 then {
diff --git a/src/process_file.ml b/src/process_file.ml
index 9ed52e8d..c3e1b510 100644
--- a/src/process_file.ml
+++ b/src/process_file.ml
@@ -398,7 +398,7 @@ let rewrite rewriters defs =
 let rewrite_ast = rewrite [("initial", Rewriter.rewrite_defs)]
 let rewrite_undefined bitvectors = rewrite [("undefined", fun x -> Rewrites.rewrite_undefined bitvectors x)]
 let rewrite_ast_lem = rewrite Rewrites.rewrite_defs_lem
-let rewrite_ast_coq = rewrite Rewrites.rewrite_defs_lem
+let rewrite_ast_coq = rewrite Rewrites.rewrite_defs_coq
 let rewrite_ast_ocaml = rewrite Rewrites.rewrite_defs_ocaml
 let rewrite_ast_c ast =
   ast
diff --git a/src/rewrites.ml b/src/rewrites.ml
index 8fe30d6b..246a2670 100644
--- a/src/rewrites.ml
+++ b/src/rewrites.ml
@@ -4001,6 +4001,263 @@ let rewrite_defs_realise_mappings (Defs defs) =
   in
   Defs (List.map rewrite_def defs |> List.flatten)
 
+
+(* Rewrite to make all pattern matches in Coq output exhaustive.
+   Assumes that guards, vector patterns, etc have been rewritten already. *)
+
+let opt_coq_warn_nonexhaustive = ref false
+
+module MakeExhaustive =
+struct
+
+type rlit =
+  | RL_unit
+  | RL_zero
+  | RL_one
+  | RL_true
+  | RL_false
+  | RL_inf
+
+let string_of_rlit = function
+  | RL_unit -> "()"
+  | RL_zero -> "bitzero"
+  | RL_one -> "bitone"
+  | RL_true -> "true"
+  | RL_false -> "false"
+  | RL_inf -> "..."
+
+let rlit_of_lit (L_aux (l,_)) =
+  match l with
+  | L_unit -> RL_unit
+  | L_zero -> RL_zero
+  | L_one -> RL_one
+  | L_true -> RL_true
+  | L_false -> RL_false
+  | L_num _ | L_hex _ | L_bin _ | L_string _ | L_real _ -> RL_inf
+  | L_undef -> assert false
+
+let inv_rlit_of_lit (L_aux (l,_)) =
+  match l with
+  | L_unit -> []
+  | L_zero -> [RL_one]
+  | L_one -> [RL_zero]
+  | L_true -> [RL_false]
+  | L_false -> [RL_true]
+  | L_num _ | L_hex _ | L_bin _ | L_string _ | L_real _ -> [RL_inf]
+  | L_undef -> assert false
+
+type residual_pattern =
+  | RP_any
+  | RP_lit of rlit
+  | RP_enum of id
+  | RP_app of id * residual_pattern list
+  | RP_tup of residual_pattern list
+  | RP_nil
+  | RP_cons of residual_pattern * residual_pattern
+
+let rec string_of_rp = function
+  | RP_any -> "_"
+  | RP_lit rlit -> string_of_rlit rlit
+  | RP_enum id -> string_of_id id
+  | RP_app (f,args) -> string_of_id f ^ "(" ^ String.concat "," (List.map string_of_rp args) ^ ")"
+  | RP_tup rps -> "(" ^ String.concat "," (List.map string_of_rp rps) ^ ")"
+  | RP_nil -> "[| |]"
+  | RP_cons (rp1,rp2) -> string_of_rp rp1 ^ "::" ^ string_of_rp rp2
+
+type ctx = {
+  env : Env.t;
+  enum_to_rest: (residual_pattern list) Bindings.t;
+  constructor_to_rest: (residual_pattern list) Bindings.t
+}
+
+let make_enum_mappings ids m =
+  IdSet.fold (fun id m ->
+    Bindings.add id
+      (List.map (fun e -> RP_enum e) (IdSet.elements (IdSet.remove id ids))) m)
+    ids
+    m
+
+let make_cstr_mappings env ids m =
+  let ids = IdSet.elements ids in
+  let constructors = List.map
+    (fun id ->
+      let _,ty = Env.get_val_spec id env in
+      let args = match ty with
+        | Typ_aux (Typ_fn (Typ_aux (Typ_tup tys,_),_,_),_) -> List.map (fun _ -> RP_any) tys
+        | _ -> [RP_any]
+      in RP_app (id,args)) ids in
+  let rec aux ids acc l =
+    match ids, l with
+    | [], [] -> m
+    | id::ids, rp::t ->
+       let m = aux ids (acc@[rp]) t in
+       Bindings.add id (acc@t) m
+    | _ -> assert false
+  in aux ids [] constructors
+
+let ctx_from_pattern_completeness_ctx env =
+  let ctx = Env.pattern_completeness_ctx env in
+  { env = env;
+    enum_to_rest = Bindings.fold (fun _ ids m -> make_enum_mappings ids m) 
+      ctx.Pattern_completeness.enums Bindings.empty;
+    constructor_to_rest = Bindings.fold (fun _ ids m -> make_cstr_mappings env ids m)
+      ctx.Pattern_completeness.variants Bindings.empty
+  }
+
+let printprefix = ref "  "
+
+let rec remove_clause_from_pattern ctx (P_aux (rm_pat,ann)) res_pat =
+  let subpats rm_pats res_pats =
+    let res_pats' = List.map2 (remove_clause_from_pattern ctx) rm_pats res_pats in
+    let rec aux acc fixed residual =
+      match fixed, residual with
+      | [], [] -> []
+      | (fh::ft), (rh::rt) ->
+         let rt' = aux (acc@[fh]) ft rt in
+         let newr = List.map (fun x -> acc @ (x::ft)) rh in
+         newr @ rt'
+      | _,_ -> assert false (* impossible because we managed map2 above *)
+    in aux [] res_pats res_pats'
+  in
+  let inconsistent () =
+    raise (Reporting_basic.err_unreachable (fst ann)
+             ("Inconsistency during exhaustiveness analysis with " ^
+                 string_of_rp res_pat))
+  in
+  (*let _ = print_endline (!printprefix ^ "pat: " ^string_of_pat (P_aux (rm_pat,ann))) in
+  let _ = print_endline (!printprefix ^ "res_pat: " ^string_of_rp res_pat) in
+  let _ = printprefix := "  " ^ !printprefix in*)
+  let rp' =
+  match rm_pat with
+  | P_wild -> []
+  | P_id id when (match Env.lookup_id id ctx.env with Unbound | Local _ -> true | _ -> false) -> []
+  | P_lit lit ->
+     (match res_pat with
+     | RP_any -> List.map (fun l -> RP_lit l) (inv_rlit_of_lit lit)
+     | RP_lit RL_inf -> [res_pat]
+     | RP_lit lit' -> if lit' = rlit_of_lit lit then [] else [res_pat]
+     | _ -> inconsistent ())
+  | P_as (p,_) 
+  | P_typ (_,p)
+  | P_var (p,_) 
+    -> remove_clause_from_pattern ctx p res_pat
+  | P_id id ->
+     (match Env.lookup_id id ctx.env with
+     | Enum enum ->
+        (match res_pat with
+        | RP_any -> Bindings.find id ctx.enum_to_rest
+        | RP_enum id' -> if Id.compare id id' == 0 then [] else [res_pat]
+        | _ -> inconsistent ())
+     | _ -> assert false)
+  | P_tup rm_pats ->
+     let previous_res_pats = 
+       match res_pat with
+       | RP_tup res_pats -> res_pats
+       | RP_any -> List.map (fun _ -> RP_any) rm_pats
+       | _ -> inconsistent ()
+     in
+     let res_pats' = subpats rm_pats previous_res_pats in
+     List.map (fun rps -> RP_tup rps) res_pats'
+  | P_app (id,args) ->
+     (match res_pat with
+     | RP_app (id',residual_args) ->
+        if Id.compare id id' == 0 then
+          let res_pats' = subpats args residual_args in
+          List.map (fun rps -> RP_app (id,rps)) res_pats'
+        else [res_pat]
+     | RP_any ->
+        let res_args = subpats args (List.map (fun _ -> RP_any) args) in
+        (List.map (fun l -> (RP_app (id,l))) res_args) @
+          (Bindings.find id ctx.constructor_to_rest)
+     | _ -> inconsistent ()
+     )
+  | P_list ps ->
+     (match ps with
+     | p1::ptl -> remove_clause_from_pattern ctx (P_aux (P_cons (p1,P_aux (P_list ptl,ann)),ann)) res_pat
+     | [] ->
+        match res_pat with
+        | RP_any -> [RP_cons (RP_any,RP_any)]
+        | RP_cons _ -> [res_pat]
+        | RP_nil -> []
+        | _ -> inconsistent ())
+  | P_cons (p1,p2) -> begin
+     let rp',rps = 
+       match res_pat with
+       | RP_cons (rp1,rp2) -> [], Some [rp1;rp2]
+       | RP_any -> [RP_nil], Some [RP_any;RP_any]
+       | RP_nil -> [RP_nil], None
+       | _ -> inconsistent ()
+     in
+     match rps with
+     | None -> rp'
+     | Some rps ->
+        let res_pats = subpats [p1;p2] rps in
+        rp' @ List.map (function [rp1;rp2] -> RP_cons (rp1,rp2) | _ -> assert false) res_pats
+  end
+  | P_record _ ->
+     raise (Reporting_basic.err_unreachable (fst ann)
+              "Record pattern not supported")
+  | P_vector _
+  | P_vector_concat _
+  | P_string_append _ ->
+     raise (Reporting_basic.err_unreachable (fst ann)
+              "Found pattern that should have been rewritten away in earlier stage")
+
+  (*in let _ = printprefix := String.sub (!printprefix) 0 (String.length !printprefix - 2)
+  in let _ = print_endline (!printprefix ^ "res_pats': " ^ String.concat "; " (List.map string_of_rp rp'))*)
+  in rp'
+
+let process_pexp env =
+  let ctx = ctx_from_pattern_completeness_ctx env in
+  fun rps patexp ->
+  (*let _ = print_endline ("res_pats: " ^ String.concat "; " (List.map string_of_rp rps)) in
+    let _ = print_endline ("pat: " ^ string_of_pexp patexp) in*)
+  match patexp with
+  | Pat_aux (Pat_exp (p,_),_) -> 
+     List.concat (List.map (remove_clause_from_pattern ctx p) rps)
+  | Pat_aux (Pat_when _,(l,_)) ->
+     raise (Reporting_basic.err_unreachable l
+              "Guarded pattern should have been rewritten away")
+
+let rewrite_case (e,ann) =
+  match e with
+  | E_case (e1,cases) ->
+     begin
+     let env = env_of_annot ann in
+     let rps = List.fold_left (process_pexp env) [RP_any] cases in
+     match rps with
+     | [] -> E_aux (E_case (e1,cases),ann)
+     | (example::_) ->
+
+        let _ =
+          if !opt_coq_warn_nonexhaustive
+          then Reporting_basic.print_err false false
+            (fst ann) "Non-exhaustive matching" ("Example: " ^ string_of_rp example) in
+
+        let l = Parse_ast.Generated Parse_ast.Unknown in
+        let p = P_aux (P_wild, (l, None)) in
+        let ann' = Some (env, typ_of_annot ann, mk_effect [BE_escape]) in
+        (* TODO: use an expression that specifically indicates a failed pattern match *)
+        let b = E_aux (E_exit (E_aux (E_lit (L_aux (L_unit, l)),(l,None))),(l,ann')) in
+        E_aux (E_case (e1,cases@[Pat_aux (Pat_exp (p,b),(l,None))]),ann)
+     end
+  | _ -> E_aux (e,ann)
+
+let rewrite =
+  let alg = { id_exp_alg with e_aux = rewrite_case } in
+  rewrite_defs_base
+    { rewrite_exp = (fun _ -> fold_exp alg)
+    ; rewrite_pat = rewrite_pat
+    ; rewrite_let = rewrite_let
+    ; rewrite_lexp = rewrite_lexp
+    ; rewrite_fun = rewrite_fun
+    ; rewrite_def = rewrite_def
+    ; rewrite_defs = rewrite_defs_base
+    }
+
+
+end
+
 let recheck_defs defs = fst (Type_error.check initial_env defs)
 
 let remove_mapping_valspecs (Defs defs) =
@@ -4049,6 +4306,45 @@ let rewrite_defs_lem = [
   ("recheck_defs", recheck_defs)
   ]
 
+let rewrite_defs_coq = [
+  ("realise_mappings", rewrite_defs_realise_mappings);
+  ("remove_mapping_valspecs", remove_mapping_valspecs);
+  ("pat_string_append", rewrite_defs_pat_string_append);
+  ("mapping_builtins", rewrite_defs_mapping_patterns);
+  ("pat_lits", rewrite_defs_pat_lits rewrite_lit_lem);
+  ("vector_concat_assignments", rewrite_vector_concat_assignments);
+  ("tuple_assignments", rewrite_tuple_assignments);
+  ("simple_assignments", rewrite_simple_assignments);
+  ("remove_vector_concat", rewrite_defs_remove_vector_concat);
+  ("remove_bitvector_pats", rewrite_defs_remove_bitvector_pats);
+  ("remove_numeral_pats", rewrite_defs_remove_numeral_pats);
+  ("guarded_pats", rewrite_defs_guarded_pats);
+  ("bitvector_exps", rewrite_bitvector_exps);
+  (* ("register_ref_writes", rewrite_register_ref_writes); *)
+  ("nexp_ids", rewrite_defs_nexp_ids);
+  ("fix_val_specs", rewrite_fix_val_specs);
+  ("split_execute", rewrite_split_fun_constr_pats "execute");
+  ("recheck_defs", recheck_defs);
+  ("exp_lift_assign", rewrite_defs_exp_lift_assign);
+  (* ("constraint", rewrite_constraint); *)
+  (* ("remove_assert", rewrite_defs_remove_assert); *)
+  ("top_sort_defs", top_sort_defs);
+  ("trivial_sizeof", rewrite_trivial_sizeof);
+  ("sizeof", rewrite_sizeof);
+  ("early_return", rewrite_defs_early_return);
+  ("make_cases_exhaustive", MakeExhaustive.rewrite);
+  ("fix_val_specs", rewrite_fix_val_specs);
+  ("recheck_defs", recheck_defs);
+  ("remove_blocks", rewrite_defs_remove_blocks);
+  ("letbind_effects", rewrite_defs_letbind_effects);
+  ("remove_e_assign", rewrite_defs_remove_e_assign);
+  ("internal_lets", rewrite_defs_internal_lets);
+  ("remove_superfluous_letbinds", rewrite_defs_remove_superfluous_letbinds);
+  ("remove_superfluous_returns", rewrite_defs_remove_superfluous_returns);
+  ("merge function clauses", merge_funcls);
+  ("recheck_defs", recheck_defs)
+  ]
+
 let rewrite_defs_ocaml = [
     (* ("undefined", rewrite_undefined); *)
   ("no_effect_check", (fun defs -> opt_no_effects := true; defs));
diff --git a/src/rewrites.mli b/src/rewrites.mli
index 70cb75af..7d6bc0b2 100644
--- a/src/rewrites.mli
+++ b/src/rewrites.mli
@@ -66,6 +66,13 @@ val rewrite_defs_interpreter : (string * (tannot defs -> tannot defs)) list
 (* Perform rewrites to exclude AST nodes not supported for lem out*)
 val rewrite_defs_lem : (string * (tannot defs -> tannot defs)) list
 
+(* Perform rewrites to exclude AST nodes not supported for coq out*)
+val rewrite_defs_coq : (string * (tannot defs -> tannot defs)) list
+
+(* Warn about matches where we add a default case for Coq because they're not
+   exhaustive *)
+val opt_coq_warn_nonexhaustive : bool ref
+
 (* Perform rewrites to exclude AST nodes not supported for C compilation *)
 val rewrite_defs_c : (string * (tannot defs -> tannot defs)) list
 
diff --git a/src/sail.ml b/src/sail.ml
index 64e60c23..f0903146 100644
--- a/src/sail.ml
+++ b/src/sail.ml
@@ -151,6 +151,9 @@ let options = Arg.align ([
   ( "-dcoq_undef_axioms",
     Arg.Set Pretty_print_coq.opt_undef_axioms,
     "Generate axioms for functions that are declared but not defined");
+  ( "-dcoq_warn_nonex",
+    Arg.Set Rewrites.opt_coq_warn_nonexhaustive,
+    "Generate warnings for non-exhaustive pattern matches in the Coq backend");
   ( "-latex_prefix",
     Arg.String (fun prefix -> Latex.opt_prefix_latex := prefix),
     " set a custom prefix for generated latex command (default sail)");
diff --git a/src/type_check.mli b/src/type_check.mli
index 665981e9..31a5a8dd 100644
--- a/src/type_check.mli
+++ b/src/type_check.mli
@@ -197,6 +197,7 @@ module Env : sig
 
   val empty : t
 
+  val pattern_completeness_ctx : t -> Pattern_completeness.ctx
 end
 
 (** Push all the type variables and constraints from a typquant into
diff --git a/test/coq/pass/allpats.sail b/test/coq/pass/allpats.sail
new file mode 100644
index 00000000..c6e111e9
--- /dev/null
+++ b/test/coq/pass/allpats.sail
@@ -0,0 +1,100 @@
+/* Not really *all* of the patterns, but enough to exercise the exhaustiveness
+   checker for Coq output */
+
+default Order dec
+$include <prelude.sail>
+
+enum anenum = {Athing, Bthing, Cthing}
+
+union aunion = {Dthing: unit, Ething: anenum, Fthing: (anenum,int)}
+
+struct arecord = {elone: anenum, eltwo: aunion}
+
+val f : (anenum, aunion, arecord, vector(5,dec,int), bits(4),list(anenum)) -> unit
+
+function f(a,b,c,d,e,g) = {
+  match a {
+  Athing => (),
+  Bthing => (),
+  Cthing => ()
+  };
+  match a {
+  Athing => (),
+  _ => ()
+  };
+  match a {
+  Athing => (),
+  Bthing => ()
+  };
+  match b {
+  Dthing(()) => (),
+  Ething(Athing) => (),
+  Ething(Bthing) => (),
+  Ething(Cthing) => (),
+  Fthing(Athing,_) => (),
+  Fthing(Bthing,_) => (),
+  Fthing(Cthing,_) => ()
+  };
+  match b {
+  Dthing(()) => (),
+  Ething(Athing) => (),
+  Ething(Bthing) => (),
+  Ething(Cthing) => (),
+  Fthing(Athing,_) => (),
+  Fthing(Cthing,_) => ()
+  };
+  match b {
+  Dthing(()) => (),
+  Ething(Athing) => (),
+  Ething(Bthing) => (),
+  Ething(Cthing) => (),
+  Fthing(Athing,_) => (),
+  Fthing(_ as x,_) => ()
+  };
+  /* Um, no syntax for record patterns? */
+  /* Vector patterns must be bits? */
+  match e {
+  [_,_,_,bitzero] => (),
+  [_,_,_,_] => ()
+  };
+  match e {
+  [_,_,_,bitzero] => ()
+  };
+  match e {
+  [_,bitzero] @ (_ : bits(2)) => (),
+  _ => ()
+  };
+  match e {
+  [_,bitzero] @ (_ : bits(2)) => ()
+  };
+  match (a,b) {
+  (Athing,Ething(Bthing)) => (),
+  (_,Fthing(_,_)) => (),
+  (_,Dthing(())) => (),
+  (Bthing,_) => (),
+  (Cthing,_) => ()
+  };
+  match (a,b) {
+  (Athing,Ething(Bthing)) => (),
+  (Athing,Ething(_)) => (),
+  (_,Fthing(_,_)) => (),
+  (_,Dthing(())) => (),
+  (Bthing,_) => (),
+  (Cthing,_) => ()
+  };
+  match g {
+  [| |] => (),
+  [| Athing, Bthing |] => (),
+  _::_::_ => ()
+  };
+  match g {
+  [| |] => (),
+  [| Athing, _, Bthing |] => (),
+  _::_::_::_ => ()
+  };
+  match g {
+  [| |] => (),
+  [| Athing, _, Bthing |] => (),
+  _::_ => ()
+  }
+}
\ No newline at end of file
-- 
cgit v1.2.3


From 7bb57d9886259fb584a3b814bdc49f8c70eb2663 Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 23 Jul 2018 16:14:46 +0100
Subject: Coq test for a few non-trivial atom types

---
 test/coq/pass/atom.sail | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 test/coq/pass/atom.sail

diff --git a/test/coq/pass/atom.sail b/test/coq/pass/atom.sail
new file mode 100644
index 00000000..c9c27b5d
--- /dev/null
+++ b/test/coq/pass/atom.sail
@@ -0,0 +1,21 @@
+default Order dec
+$include <flow.sail>
+$include <arith.sail>
+
+val f : forall 'n, 'n >= 0. atom(8 * 'n) -> int
+
+function f(x) = x+1
+
+val g : forall 'n, 'n > 0. atom('n) -> atom(2*'n)
+val h : forall 'n, 'n > 1. atom('n) -> int
+
+function h(x) = x
+
+val test : unit -> bool
+
+function test() = {
+  /* Using f with Coq would need us to provide/infer witnesses for 'n
+  f(0) == 1 & f(8) == 9
+  */
+  h(g(1)) == 2
+}
\ No newline at end of file
-- 
cgit v1.2.3


From 294ff935decaf8450bf3d3557218b936b473ce0b Mon Sep 17 00:00:00 2001
From: Brian Campbell
Date: Mon, 23 Jul 2018 16:15:29 +0100
Subject: Coq: faster MIPS extras without confusing message

---
 mips/mips_extras.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mips/mips_extras.v b/mips/mips_extras.v
index cc905f11..6a6aed5c 100644
--- a/mips/mips_extras.v
+++ b/mips/mips_extras.v
@@ -140,7 +140,7 @@ Definition eq_bit (x : bitU) (y : bitU) : bool :=
 
 Require Import Zeuclid.
 Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
-refine (build_ex (ZEuclid.modulo m n)).
+refine (existT _ (ZEuclid.modulo m n) _).
 constructor.
 destruct H.
 assert (Zabs n = n). { rewrite Zabs_eq; auto with zarith. }
-- 
cgit v1.2.3


From 13ca82515d512a4fb9bbc5cdd9ea1dd0803e9ad5 Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Mon, 23 Jul 2018 17:31:25 +0100
Subject: AArch64 patches: EL2 secure not implemented

Several v8.4 tests were failing because they attempted to enter EL2 secure
mode (which is supported on v8.4 but not on v8.3).
This test detects an attempt to enter EL2 secure and reports an easily diagnosed
error message.
---
 aarch64/elfmain.sail | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index 24579b79..ad564108 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -98,6 +98,13 @@ function Step_CPU() = {
               "\n")));
         exit()
       };
+      // test for ERET instruction from EL3_Secure - only supported in v8.4
+      if (__currentInstr == 0xd69f_03e0) & (PSTATE.EL == EL3) & (SCR_EL3[0] == bitzero) then {
+        print(concat_str("UNIMPLEMENTED: EL2_Secure support (v8.4 feature) ",
+              concat_str(HexStr(UInt(__currentInstr)),
+              "\n")));
+        exit()
+      };
       try {
           __PC_changed = false;
           ShouldAdvanceIT = (PSTATE.nRW == [bitone]) & (PSTATE.T == [bitone]);
-- 
cgit v1.2.3


From 8114501b7b956ee4a98fa8599c7efee62fc19206 Mon Sep 17 00:00:00 2001
From: Alastair Reid
Date: Mon, 23 Jul 2018 17:32:23 +0100
Subject: RTS: make g_cycle_count public

This allows debug messages to include the current cycle count
which can be useful for debugging.
---
 lib/rts.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/rts.c b/lib/rts.c
index 97aad8a4..729e2a8b 100644
--- a/lib/rts.c
+++ b/lib/rts.c
@@ -7,7 +7,7 @@
 #include"elf.h"
 
 static uint64_t g_elf_entry;
-static uint64_t g_cycle_count = 0;
+uint64_t g_cycle_count = 0;
 static uint64_t g_cycle_limit;
 
 void sail_match_failure(sail_string msg)
-- 
cgit v1.2.3